MF1574-01 CMOS 32-BIT SINGLE CHIP MICROCOMPUTER S1C33L03 Technical Manual S1C33L03 PRODUCT PART S1C33L03 FUNCTION PART NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. (c) SEIKO EPSON CORPORATION 2003, All rights reserved. S1C33L03 Technical Manual This manual describes the hardware specifications of the Seiko Epson original 32-bit microcomputer S1C33L03. S1C33L03 PRODUCT PART Describes the hardware specifications of the S1C33L03 except for details of the peripheral circuits. S1C33L03 FUNCTION PART Describes details of all the peripheral circuit blocks for the S1C33 Family microcomputers. Refer to the "S1C33000 Core CPU Manual" for details of the S1C33000 32-bit RISC CPU. Configuration of product number Devices S1 C 33209 F 00E1 00 Packing specifications 00 : Besides tape & reel 0A : TCP BL 2 directions 0B : Tape & reel BACK 0C : TCP BR 2 directions 0D : TCP BT 2 directions 0E : TCP BD 2 directions 0F : Tape & reel FRONT 0G : TCP BT 4 directions 0H : TCP BD 4 directions 0J : TCP SL 2 directions 0K : TCP SR 2 directions 0L : Tape & reel LEFT 0M: TCP ST 2 directions 0N : TCP SD 2 directions 0P : TCP ST 4 directions 0Q : TCP SD 4 directions 0R : Tape & reel RIGHT 99 : Specs not fixed Specification Package D: die form; F: QFP Model number Model name C: microcomputer, digital products Product classification S1: semiconductor Development tools S5U1 C 33000 H2 1 00 Packing specifications 00: standard packing Version 1: Version 1 Tool type Hx : ICE Dx : Evaluation board Ex : ROM emulation board Mx : Emulation memory for external ROM Tx : A socket for mounting Cx : Compiler package Sx : Middleware package Corresponding model number 33L01: for S1C33L01 Tool classification C: microcomputer use Product classification S5U1: development tool for semiconductor products TABLE OF CONTENTS S1C33L03 PRODUCT PART Table of Contents 1 Outline..................................................................................................................................... A-1 1.1 Features.....................................................................................................................................A-1 1.2 Block Diagram ...........................................................................................................................A-3 1.3 Pin Description ..........................................................................................................................A-4 1.3.1 Pin Layout Diagram (plastic package) ......................................................................A-4 1.3.2 Pin Functions .............................................................................................................A-5 2 Power Supply .......................................................................................................................A-12 2.1 2.2 2.3 2.4 Power Supply Pins ..................................................................................................................A-12 Operating Voltage (VDD, VSS).................................................................................................A-12 Power Supply for I/O Interface (VDDE)....................................................................................A-13 Power Supply for Analog Circuits (AVDDE).............................................................................A-13 3 Internal Memory...................................................................................................................A-14 3.1 ROM and Boot Address ..........................................................................................................A-14 3.2 RAM .........................................................................................................................................A-15 4 Peripheral Circuits ..............................................................................................................A-16 4.1 List of Peripheral Circuits ........................................................................................................A-16 4.2 I/O Memory Map......................................................................................................................A-17 5 Power-Down Control...........................................................................................................A-65 6 Basic External Wiring Diagram .........................................................................................A-68 7 Precautions on Mounting...................................................................................................A-69 8 Electrical Characteristics ...................................................................................................A-71 8.1 8.2 8.3 8.4 8.5 8.6 Absolute Maximum Rating ......................................................................................................A-71 Recommended Operating Conditions ....................................................................................A-72 DC Characteristics ..................................................................................................................A-73 Current Consumption ..............................................................................................................A-75 A/D Converter Characteristics ................................................................................................A-76 AC Characteristics...................................................................................................................A-78 8.6.1 Symbol Description ..................................................................................................A-78 8.6.2 AC Characteristics Measurement Condition...........................................................A-78 8.6.3 C33 Block AC Characteristic Tables .......................................................................A-79 8.6.4 C33 Block AC Characteristic Timing Charts ...........................................................A-87 8.6.5 LCD Interface AC Characteristics ...........................................................................A-96 8.7 Oscillation Characteristics.................................................................................................... A-107 8.8 PLL Characteristics .............................................................................................................. A-108 9 Package ..............................................................................................................................A-109 9.1 Plastic Package .................................................................................................................... A-109 10 Pad Layout .........................................................................................................................A-110 10.1 Pad Layout Diagram............................................................................................................. A-110 10.2 Pad Coordinate..................................................................................................................... A-111 S1C33L03 TECHNICAL MANUAL EPSON i TABLE OF CONTENTS Appendix A <Reference> External Device Interface Timings.......................................... A-113 A.1 A.2 A.3 A.4 A.5 A.6 DRAM (70ns)........................................................................................................................ A-114 DRAM (60ns)........................................................................................................................ A-117 ROM and Burst ROM ........................................................................................................... A-121 SRAM (55ns) ........................................................................................................................ A-123 SRAM (70ns) ........................................................................................................................ A-125 8255A.................................................................................................................................... A-127 Appendix B Pin Characteristics ........................................................................................... A-128 ii EPSON S1C33L03 TECHNICAL MANUAL TABLE OF CONTENTS S1C33L03 FUNCTION PART Table of Contents I OUTLINE I-1 INTRODUCTION ............................................................................................................ B-I-1-1 I-2 BLOCK DIAGRAM......................................................................................................... B-I-2-1 I-3 LIST OF PINS................................................................................................................. B-I-3-1 List of External I/O Pins............................................................................................................... B-I-3-1 II CORE BLOCK II-1 INTRODUCTION ........................................................................................................... B-II-1-1 II-2 CPU AND OPERATING MODE ................................................................................... B-II-2-1 CPU ............................................................................................................................................ B-II-2-1 Standby Mode............................................................................................................................. B-II-2-2 HALT Mode ..................................................................................................................... B-II-2-2 SLEEP Mode .................................................................................................................. B-II-2-2 Notes on Standby Mode ................................................................................................. B-II-2-3 Test Mode ................................................................................................................................... B-II-2-3 Debug Mode ............................................................................................................................... B-II-2-3 Trap Table................................................................................................................................... B-II-2-4 II-3 INITIAL RESET ............................................................................................................. B-II-3-1 Pins for Initial Reset.................................................................................................................... B-II-3-1 Cold Start and Hot Start ............................................................................................................. B-II-3-1 Power-on Reset .......................................................................................................................... B-II-3-2 Reset Pulse................................................................................................................................. B-II-3-2 Boot Address .............................................................................................................................. B-II-3-3 Notes Related to Initial Reset..................................................................................................... B-II-3-3 II-4 BCU (Bus Control Unit)............................................................................................... B-II-4-1 Pin Assignment for External System Interface .......................................................................... B-II-4-1 I/O Pin List....................................................................................................................... B-II-4-1 Combination of System Bus Control Signals................................................................. B-II-4-3 Memory Area .............................................................................................................................. B-II-4-4 Memory Map ................................................................................................................... B-II-4-4 External Memory Map and Chip Enable ........................................................................ B-II-4-5 Using Internal Memory on External Memory Area......................................................... B-II-4-7 Exclusive Signals for Areas............................................................................................ B-II-4-7 Area 10............................................................................................................................ B-II-4-8 Area 3.............................................................................................................................. B-II-4-9 Setting External Bus Conditions .............................................................................................. B-II-4-10 Setting Device Type and Size ...................................................................................... B-II-4-10 Setting SRAM Timing Conditions................................................................................. B-II-4-11 Setting Timing Conditions of Burst ROM ..................................................................... B-II-4-12 Bus Operation........................................................................................................................... B-II-4-13 Data Arrangement in Memory ...................................................................................... B-II-4-13 Bus Operation of External Memory .............................................................................. B-II-4-13 S1C33L03 TECHNICAL MANUAL EPSON iii TABLE OF CONTENTS Bus Clock.................................................................................................................................. B-II-4-17 Bus Speed Mode .......................................................................................................... B-II-4-18 Bus Clock Output .......................................................................................................... B-II-4-18 Bus Cycles in External System Interface................................................................................. B-II-4-19 SRAM Read Cycles ...................................................................................................... B-II-4-19 Bus Timing .................................................................................................................... B-II-4-20 SRAM Write Cycles ...................................................................................................... B-II-4-21 Burst ROM Read Cycles .............................................................................................. B-II-4-23 DRAM Direct Interface.............................................................................................................. B-II-4-24 Outline of DRAM Interface............................................................................................ B-II-4-24 DRAM Setting Conditions............................................................................................. B-II-4-25 DRAM Read/Write Cycles ............................................................................................ B-II-4-28 DRAM Refresh Cycles.................................................................................................. B-II-4-31 Releasing External Bus ............................................................................................................ B-II-4-32 Power-down Control by External Device ................................................................................. B-II-4-33 I/O Memory of BCU .................................................................................................................. B-II-4-34 II-5 ITC (Interrupt Controller).............................................................................................B-II-5-1 Outline of Interrupt Functions..................................................................................................... B-II-5-1 Maskable Interrupts ........................................................................................................ B-II-5-1 Interrupt Factors and Intelligent DMA ............................................................................ B-II-5-3 Nonmaskable Interrupt (NMI) ......................................................................................... B-II-5-3 Interrupt Processing by the CPU.................................................................................... B-II-5-3 Clearing Standby Mode by Interrupts............................................................................. B-II-5-3 Trap Table................................................................................................................................... B-II-5-4 Control of Maskable Interrupts................................................................................................... B-II-5-5 Structure of the Interrupt Controller................................................................................ B-II-5-5 Processor Status Register (PSR)................................................................................... B-II-5-5 Interrupt Factor Flag and Interrupt Enable Register...................................................... B-II-5-6 Interrupt Priority Register and Interrupt Levels .............................................................. B-II-5-8 IDMA Invocation ......................................................................................................................... B-II-5-9 HSDMA Invocation ................................................................................................................... B-II-5-11 I/O Memory of Interrupt Controller ........................................................................................... B-II-5-12 Programming Notes.................................................................................................................. B-II-5-25 II-6 CLG (Clock Generator)................................................................................................B-II-6-1 Configuration of Clock Generator .............................................................................................. B-II-6-1 I/O Pins of Clock Generator ....................................................................................................... B-II-6-2 High-Speed (OSC3) Oscillation Circuit...................................................................................... B-II-6-2 PLL ............................................................................................................................................ B-II-6-3 Controlling Oscillation................................................................................................................. B-II-6-3 Setting and Switching Over the CPU Operating Clock ............................................................. B-II-6-4 Power-Control Register Protection Flag .................................................................................... B-II-6-5 Operation in Standby Mode ....................................................................................................... B-II-6-5 I/O Memory of Clock Generator ................................................................................................. B-II-6-6 Programming Notes.................................................................................................................... B-II-6-9 II-7 DBG (Debug Unit).........................................................................................................B-II-7-1 Debug Circuit .............................................................................................................................. B-II-7-1 I/O Pins of Debug Circuit............................................................................................................ B-II-7-1 iv EPSON S1C33L03 TECHNICAL MANUAL TABLE OF CONTENTS III PERIPHERAL BLOCK III-1 INTRODUCTION ......................................................................................................... B-III-1-1 III-2 PRESCALER............................................................................................................... B-III-2-1 Configuration of Prescaler......................................................................................................... B-III-2-1 Source Clock ............................................................................................................................. B-III-2-1 Selecting Division Ratio and Output Control for Prescaler ...................................................... B-III-2-2 Source Clock Output to 8-Bit Programmable Timer................................................................. B-III-2-2 I/O Memory of Prescaler ........................................................................................................... B-III-2-3 Programming Notes................................................................................................................... B-III-2-8 III-3 8-BIT PROGRAMMABLE TIMERS............................................................................ B-III-3-1 Configuration of 8-Bit Programmable Timer ............................................................................. B-III-3-1 Output Pins of 8-Bit Programmable Timers.............................................................................. B-III-3-1 Uses of 8-Bit Programmable Timers......................................................................................... B-III-3-2 Control and Operation of 8-Bit Programmable Timer............................................................... B-III-3-4 Control of Clock Output ............................................................................................................. B-III-3-7 8-Bit Programmable Timer Interrupts and DMA ....................................................................... B-III-3-8 I/O Memory of 8-Bit Programmable Timers............................................................................ B-III-3-10 Programming Notes................................................................................................................. B-III-3-17 III-4 16-BIT PROGRAMMABLE TIMERS.......................................................................... B-III-4-1 Configuration of 16-Bit Programmable Timer ........................................................................... B-III-4-1 I/O Pins of 16-Bit Programmable Timers.................................................................................. B-III-4-2 Uses of 16-Bit Programmable Timers....................................................................................... B-III-4-3 Control and Operation of 16-Bit Programmable Timer ............................................................ B-III-4-4 Controlling Clock Output ........................................................................................................... B-III-4-7 16-Bit Programmable Timer Interrupts and DMA..................................................................... B-III-4-9 I/O Memory of 16-Bit Programmable Timers.......................................................................... B-III-4-12 Programming Notes................................................................................................................. B-III-4-25 III-5 WATCHDOG TIMER................................................................................................... B-III-5-1 Configuration of Watchdog Timer ............................................................................................. B-III-5-1 Control of Watchdog Timer ....................................................................................................... B-III-5-1 Operation in Standby Modes.....................................................................................................B-III-5-2 I/O Memory of Watchdog Timer................................................................................................ B-III-5-3 Programming Notes................................................................................................................... B-III-5-3 III-6 LOW-SPEED (OSC1) OSCILLATION CIRCUIT ....................................................... B-III-6-1 Configuration of Low-Speed (OSC1) Oscillation Circuit .......................................................... B-III-6-1 I/O Pins of Low-Speed (OSC1) Oscillation Circuit ................................................................... B-III-6-1 Oscillator Types ......................................................................................................................... B-III-6-2 Controlling Oscillation................................................................................................................ B-III-6-3 Switching Over the CPU Operating Clock ................................................................................ B-III-6-3 Power-Control Register Protection Flag ................................................................................... B-III-6-4 Operation in Standby Mode ......................................................................................................B-III-6-4 OSC1 Clock Output to External Devices .................................................................................. B-III-6-4 I/O Memory of Low-Speed (OSC1) Oscillation Circuit ............................................................. B-III-6-5 Programming Notes................................................................................................................... B-III-6-8 S1C33L03 TECHNICAL MANUAL EPSON v TABLE OF CONTENTS III-7 CLOCK TIMER ............................................................................................................B-III-7-1 Configuration of Clock Timer..................................................................................................... B-III-7-1 Control and Operation of the Clock Timer ................................................................................ B-III-7-2 Interrupt Function....................................................................................................................... B-III-7-4 Examples of Use of Clock Timer............................................................................................... B-III-7-6 I/O Memory of Clock Timer ....................................................................................................... B-III-7-7 Programming Notes................................................................................................................. B-III-7-12 III-8 SERIAL INTERFACE ..................................................................................................B-III-8-1 Configuration of Serial Interfaces.............................................................................................. B-III-8-1 Features of Serial Interfaces ......................................................................................... B-III-8-1 I/O Pins of Serial Interface............................................................................................. B-III-8-2 Setting Transfer Mode ................................................................................................... B-III-8-3 Clock-Synchronized Interface ...................................................................................................B-III-8-4 Outline of Clock-Synchronized Interface....................................................................... B-III-8-4 Setting Clock-Synchronized Interface........................................................................... B-III-8-5 Control and Operation of Clock-Synchronized Transfer .............................................. B-III-8-7 Asynchronous Interface........................................................................................................... B-III-8-12 Outline of Asynchronous Interface .............................................................................. B-III-8-12 Setting Asynchronous Interface .................................................................................. B-III-8-13 Control and Operation of Asynchronous Transfer......................................................B-III-8-16 IrDA Interface........................................................................................................................... B-III-8-21 Outline of IrDA Interface .............................................................................................. B-III-8-21 Setting IrDA Interface .................................................................................................. B-III-8-21 Control and Operation of IrDA Interface ..................................................................... B-III-8-23 Serial Interface Interrupts and DMA........................................................................................ B-III-8-24 I/O Memory of Serial Interface ................................................................................................ B-III-8-28 Programming Notes................................................................................................................. B-III-8-46 III-9 INPUT/OUTPUT PORTS.............................................................................................B-III-9-1 Input Ports (K Ports) .................................................................................................................. B-III-9-1 Structure of Input Port.................................................................................................... B-III-9-1 Input-Port Pins ............................................................................................................... B-III-9-2 Notes on Use ................................................................................................................. B-III-9-2 I/O Memory of Input Ports ............................................................................................. B-III-9-3 I/O Ports (P Ports) ..................................................................................................................... B-III-9-4 Structure of I/O Port....................................................................................................... B-III-9-4 I/O Port Pins................................................................................................................... B-III-9-4 I/O Control Register and I/O Modes.............................................................................. B-III-9-5 I/O Memory of I/O Ports................................................................................................. B-III-9-6 Input Interrupt .......................................................................................................................... B-III-9-12 Port Input Interrupt....................................................................................................... B-III-9-12 Key Input Interrupt ....................................................................................................... B-III-9-14 Control Registers of the Interrupt Controller............................................................... B-III-9-16 I/O Memory for Input Interrupts ................................................................................... B-III-9-18 Programming Notes.................................................................................................................B-III-9-25 vi EPSON S1C33L03 TECHNICAL MANUAL TABLE OF CONTENTS IV ANALOG BLOCK IV-1 INTRODUCTION .........................................................................................................B-IV-1-1 IV-2 A/D CONVERTER .......................................................................................................B-IV-2-1 Features and Structure of A/D Converter .................................................................................B-IV-2-1 I/O Pins of A/D Converter..........................................................................................................B-IV-2-2 Setting A/D Converter ...............................................................................................................B-IV-2-3 Control and Operation of A/D Conversion ................................................................................B-IV-2-5 A/D Converter Interrupt and DMA.............................................................................................B-IV-2-7 I/O Memory of A/D Converter....................................................................................................B-IV-2-9 Programming Notes.................................................................................................................B-IV-2-15 V DMA BLOCK V-1 INTRODUCTION .......................................................................................................... B-V-1-1 V-2 HSDMA (High-Speed DMA) ....................................................................................... B-V-2-1 Functional Outline of HSDMA ....................................................................................................B-V-2-1 I/O Pins of HSDMA.....................................................................................................................B-V-2-2 Programming Control Information..............................................................................................B-V-2-3 Setting the Registers in Dual-Address Mode.................................................................B-V-2-3 Setting the Registers in Single-Address Mode ..............................................................B-V-2-6 Enabling/Disabling DMA Transfer..............................................................................................B-V-2-7 Trigger Factor .............................................................................................................................B-V-2-8 Operation of HSDMA..................................................................................................................B-V-2-9 Operation in Dual-Address Mode...................................................................................B-V-2-9 Operation in Single-Address Mode ..............................................................................B-V-2-12 Timing Chart..................................................................................................................B-V-2-13 Interrupt Function of HSDMA ...................................................................................................B-V-2-15 I/O Memory of HSDMA.............................................................................................................B-V-2-17 Programming Notes..................................................................................................................B-V-2-36 V-3 IDMA (Intelligent DMA)...............................................................................................B-V-3-1 Functional Outline of IDMA ........................................................................................................B-V-3-1 Programming Control Information..............................................................................................B-V-3-1 IDMA Invocation .........................................................................................................................B-V-3-5 Operation of IDMA......................................................................................................................B-V-3-8 Linking.......................................................................................................................................B-V-3-12 Interrupt Function of Intelligent DMA .......................................................................................B-V-3-13 I/O Memory of Intelligent DMA.................................................................................................B-V-3-14 Programming Notes..................................................................................................................B-V-3-17 S1C33L03 TECHNICAL MANUAL EPSON vii TABLE OF CONTENTS VI SDRAM CONTROLLER BLOCK VI-1 INTRODUCTION......................................................................................................... B-VI-1-1 VI-2 SDRAM INTERFACE ................................................................................................. B-VI-2-1 Outline of SDRAM Interface......................................................................................................B-VI-2-1 SDRAM Controller Block Diagram ............................................................................................B-VI-2-1 I/O Pins and Connection ...........................................................................................................B-VI-2-2 I/O Pins...........................................................................................................................B-VI-2-2 Connection Examples....................................................................................................B-VI-2-2 SDRAM Controller Configuration ..............................................................................................B-VI-2-5 Setting PLL.....................................................................................................................B-VI-2-5 BCU Configuration.........................................................................................................B-VI-2-5 SDRAM Setting Conditions ...........................................................................................B-VI-2-6 SDRAM Operation...................................................................................................................B-VI-2-12 Synchronous Clock......................................................................................................B-VI-2-12 Power-up and Initialization ..........................................................................................B-VI-2-13 SDRAM Commands ....................................................................................................B-VI-2-14 Burst Read Cycle.........................................................................................................B-VI-2-15 Single Read/Single Write.............................................................................................B-VI-2-16 Refresh Mode ..............................................................................................................B-VI-2-17 Power-down Mode.......................................................................................................B-VI-2-19 Bus Release Procedure...............................................................................................B-VI-2-19 I/O Memory of SDRAM Interface ............................................................................................B-VI-2-21 Programming Notes.................................................................................................................B-VI-2-32 Examples of SDRAM Controller Initialization Program ..........................................................B-VI-2-33 VII LCD CONTROLLER BLOCK VII-1 INTRODUCTION........................................................................................................ B-VII-1-1 VII-2 LCD CONTROLLER.................................................................................................. B-VII-2-1 Overview ...................................................................................................................................B-VII-2-1 Features ........................................................................................................................B-VII-2-1 Block Diagram...............................................................................................................B-VII-2-3 I/O Pins of the LCD Controller..................................................................................................B-VII-2-4 System Settings........................................................................................................................B-VII-2-5 Setting the BCU ............................................................................................................B-VII-2-5 Display Memory ............................................................................................................B-VII-2-5 LCD Controller Setting Procedure................................................................................B-VII-2-6 Clock .............................................................................................................................B-VII-2-7 Setting the LCD Panel ..............................................................................................................B-VII-2-8 Types of Panels ............................................................................................................B-VII-2-8 Resolution .....................................................................................................................B-VII-2-8 Display Modes ..............................................................................................................B-VII-2-9 Look-up Tables .......................................................................................................... B-VII-2-11 Frame Rates .............................................................................................................. B-VII-2-19 Other Settings ............................................................................................................ B-VII-2-20 Display Control ...................................................................................................................... B-VII-2-21 Controlling LCD Power Up/Down.............................................................................. B-VII-2-21 Reading/Writing Display Data ................................................................................... B-VII-2-22 Setting the Display Start Address ............................................................................. B-VII-2-22 Split-Screen Display .................................................................................................. B-VII-2-23 viii EPSON S1C33L03 TECHNICAL MANUAL TABLE OF CONTENTS Virtual Screen and View Port .................................................................................... B-VII-2-23 Inverting and Blanking the Display............................................................................ B-VII-2-25 Portrait Mode ............................................................................................................. B-VII-2-25 Power Save................................................................................................................ B-VII-2-29 Controlling the GPIO Pins ......................................................................................... B-VII-2-30 I/O Memory of LCD Controller............................................................................................... B-VII-2-31 Programming Notes............................................................................................................... B-VII-2-42 Precautions on Using ICD33................................................................................................. B-VII-2-42 Examples of LCD Controller Setting Program...................................................................... B-VII-2-43 APPENDIX I/O MAP S1C33L03 TECHNICAL MANUAL EPSON ix S1C33L03 PRODUCT PART 1 OUTLINE A-1 1 Outline The S1C33L03 is a Seiko Epson original 32-bit microcomputer with a built-in LCD controller. It features high speed, low power and low-voltage operation and is most suitable for portable equipment that needs display function, such as information terminals, E-mail terminals, electronic dictionaries. The S1C33L03 consists of the S1C33000 32-bit RISC type CPU as the core, a bus control unit, a DMA controller, an interrupt controller, an LCD controller, an SDRAM controller, timers, serial interface circuits, an A/D converter, ROM and RAM. The S1C33L03 provides a DSP function, by using the internal MAC (multiplication and accumulation) operation function with the A/D converter, it makes it possible to design simply speech recognition and voice synthesis systems. Model S1C33L03F00A100 S1C33L03F00A200 S1C33L03D00A100 Package QFP20-144pin QFP20-144pin (Pb-free package) Chip Table 1.1 Model Lineup Internal RAM 8K bytes Internal ROM None Data bus I/F CMOS/LVTTL 8K bytes None CMOS/LVTTL 8K bytes None CMOS/LVTTL 1.1 Features Core CPU Seiko Epson original 32-bit RISC CPU S1C33000 built-in * Basic instruction set: 105 instructions (16-bit fixed size) * Sixteen 32-bit general-purpose register * 32-bit ALU and 8-bit shifter * Multiplication/division instructions and MAC (multiplication and accumulation) instruction are available * 20 ns of minimum instruction execution time at 50 MHz operation Internal memory RAM: 8K bytes Internal peripheral circuits Oscillation circuit: LCD controller: Timers: Serial interface: A/D converter: DMA controller: S1C33L03 PRODUCT PART High-speed (OSC3) oscillation circuit 33 MHz max. Crystal/ceramic oscillator or external clock input Low-speed (OSC1) oscillation circuit 32.768 kHz typ. Crystal oscillator or external clock input 4 or 8-bit monochrome/color LCD interface (based on the S1D13705) 2, 4 or 16-level (1, 2 or 4 bit-per-pixel) gray-scale display 2, 4, 16 or 256-level (1, 2, 4 or 8 bit-per-pixel) color display Resolution examples: 640 x 480 pixels with 1-bpp color depth 640 x 240 pixels with 2-bpp color depth 320 x 240 pixels with 4-bpp color depth 240 x 160 pixels with 8-bpp color depth 8-bit timer 6 channels 16-bit timer 6 channels Watchdog timer (16-bit timer 0's function) Clock timer 1 channel (with alarm function) 4 channels (clock-synchronous system, asynchronous system and IrDA interface are selectable) 10 bits x 8 channels High-speed DMA 4 channels Intelligent DMA 128 channels EPSON A-1 1 OUTLINE Interrupt controller: Possible to invoke DMA Input interrupt 10 types (programmable) DMA controller interrupt 5 types 16-bit programmable timer interrupt 12 types 8-bit programmable timer interrupt 4 types Serial interface interrupt 6 types A/D converter interrupt 1 type Clock timer interrupt 1 type Shared with the I/O pins for internal peripheral circuits Input port 13 bits I/O port 29 bits General-purpose input and output ports: External bus interface BCU (bus control unit) built-in * 24-bit address bus (internal 28-bit processing) * 16-bit data bus Data size is selectable from 8 bits and 16 bits in each area. * Little-endian memory access; big-endian may be set in each area. * Memory mapped I/O * Chip enable and wait control circuits built-in * DRAM direct interface function built-in Supports fast page mode and EDO page mode. Supports self-refresh and CAS-before RAS refresh. * Supports SDRAM. Supports SDRAM self-refresh. * Supports burst ROM. Operating conditions and power consumption Operating voltage: Core (VDD) 1.8 V to 3.6 V I/O (VDDE) 1.8 V to 5.5 V Operating clock frequency: CPU operating clock frequency 50 MHz max. (core voltage = 3.3 V 0.3 V) LCD controller operating clock frequency 25 MHz max. (core voltage = 3.3 V 0.3 V) * When the SDRAM controller is used (core voltage = 3.3 V 0.3 V and PLL is used), In x1 speed mode: CPU = Bus = 25 MHz max. In x2 speed mode: CPU = 35 MHz max., Bus = 17.5 MHz max. Operating temperature: -40 to 85C Power consumption: During SLEEP 3.5 W typ. (3.3 V) During HALT 100 mW typ. (3.3 V, 50 MHz) During execution 200 mW typ. (3.3 V, 50 MHz) Note: The values of power consumption during execution were measured when a test program that consisted of 55% load instructions, 23% arithmetic operation instructions, 1% mac instruction, 12% branch instructions and 9% ext instruction was being continuously executed. Supply form QFP20-144pin plastic package, or chip. A-2 EPSON S1C33L03 PRODUCT PART 1 OUTLINE A-1 1.2 Block Diagram VDD VSS VDDE S1C33L03 A[23:0] D[15:0] #RD #WRL/#WR/#WE #WRH/#BSH #HCAS, #LCAS, #RAS[1:0] #CE10EX, #CE[9:3] #EMEMRD #WAIT(P30) #DRD(P20), #DWE/#SDWE(P21) #GAAS(P21), #GARD(P31) #SDCE[1:0] #SDCAS, #SDRAS SDA10, SDCKE, HDQM, LDQM OSC3 OSC4 PLLS[1:0] PLLC OSC1 OSC2 FOSC1(P14) #DMAREQx(K50, K51, K53, K54) #DMAACKx(P32, P33, P04, P06) #DMAENDx(P15, P16, P05, P07) #RESET #NMI #X2SPD ICEMD DSIO EA10MD[1:0] BCLK #BUSREQ(P34) #BUSACK(P35) #BUSGET(P31) DST[2:0](P10-12) DPCO(P13) DCLK(P14) S1C33000 CPU Core Bus Control Unit SDRAM Controller OSC3/PLL Interrupt Controller Prescaler 16-bit Programmable Timer (6 ch.) EXCLx(P10-13, P15, P16) TMx(P22-27) OSC1 8-bit Programmable Timer (6 ch.) T8UFx(P10-13) Clock Timer Serial Interface (4 ch.) SINx(P00, P04, P27, P33) SOUTx(P01, P05, P26, P16) #SCLKx(P02, P06, P25, P15) #SRDYx(P03, P07, P24, P32) Intelligent DMA (128 ch.) A/D Converter (8 ch.) AD0-7(K60-67) #ADTRG(K52) AVDDE LCD Controller FPDAT[7:4] FPDAT[3:0]/GPO[6:3] FPFRAME FPLINE FPSHIFT DRDY(MOD/FPSHIFT2) LCDPWR High-speed DMA (4 ch.) RAM 8KB P00-07 P10-16 P20-27 P30-35 Input Port I/O Port K50-54 K60-67 Figure 1.2.1 S1C33L03 Block Diagram S1C33L03 PRODUCT PART EPSON A-3 1 OUTLINE 1.3 Pin Description 1.3.1 Pin Layout Diagram (plastic package) QFP20-144pin 108 73 109 72 INDEX 144 37 1 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 36 Pin name No. Pin name P22/TM0 37 K54/#DMAREQ3 P23/TM1 38 K53/#DMAREQ2 VSS 39 K52/#ADTRG P24/TM2/#SRDY2 40 K51/#DMAREQ1 P25/TM3/#SCLK2 41 K50/#DMAREQ0 P26/TM4/SOUT2 42 #WRH/#BSH P27/TM5/SIN2 43 #WRL/#WR/#WE VDD 44 #RD P07/#SRDY1/#DMAEND3 45 VSS P06/#SCLK1/#DMAACK3 46 D15 P05/SOUT1/#DMAEND2 47 D14 P04/SIN1/#DMAACK2 48 D13 FPDAT7 49 D12 FPDAT6 50 D11 FPDAT5 51 VDD FPDAT4 52 D10 FPDAT3/GPO6 53 D9 FPDAT2/GPO5 54 D8 FPDAT1/GPO4 55 D7 FPDAT0/GPO3 56 D6 VDDE 57 D5 DRDY(MOD/FPSHIFT2) 58 D4 FPFRAME 59 VDDE FPLINE 60 D3 FPSHIFT 61 D2 LCDPWR 62 D1 VSS 63 D0 K67/AD7 64 #CE8/#RAS1/#CE14/#RAS3/#SDCE1 K66/AD6 65 #CE7/#RAS0/#CE13/#RAS2/#SDCE0 K65/AD5 66 VSS K64/AD4 67 OSC2 K63/AD3 68 OSC1 K62/AD2 69 #RESET K61/AD1 70 P35/#BUSACK/GPIO1 K60/AD0 71 P34/#BUSREQ/#CE6/GPIO0 AVDDE 72 P33/#DMAACK1/SIN3/SDA10 No. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Pin name P32/#DMAACK0/#SRDY3/HDQM P31/#BUSGET/#GARD/GPIO2 P30/#WAIT/#CE4&5 #LCAS/#SDRAS #HCAS/#SDCAS VDD P21/#DWE/#GAAS/#SDWE P20/#DRD/SDCKE BCLK/SDCLK VSS P16/EXCL5/#DMAEND1/SOUT3 P15/EXCL4/#DMAEND0/#SCLK3/LDQM A0/#BSL A1/SDA0 A2/SDA1 A3/SDA2 A4/SDA3 A5/SDA4 VDDE A6/SDA5 A7/SDA6 A8/SDA7 A9/SDA8 A10/SDA9 A11 VSS A12/SDA11 A13/SDA12 A14/SDBA0 A15/SDBA1 A16 A17 VSS A18 A19 A20 No. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Pin name A21 A22 A23 PLLS1 PLLS0 VSS PLLC VSS DSIO P14/FOSC1/DCLK P13/EXCL3/T8UF3/DPCO P12/EXCL2/T8UF2/DST2 P11/EXCL1/T8UF1/DST1 P10/EXCL0/T8UF0/DST0 EA10MD1 EA10MD0 ICEMD #EMEMRD VDD OSC4 OSC3 #NMI #CE9/#CE17/#CE17&18 VDDE #CE5/#CE15/#CE15&16 N.C. #CE3 VSS #CE10EX/#CE9&10EX #CE6/#CE7&8 #CE4/#CE11/#CE11&12 #X2SPD P03/#SRDY0 P02/#SCLK0 P01/SOUT0 P00/SIN0 Figure 1.3.1 Pin Layout Diagram (QFP20-144pin) A-4 EPSON S1C33L03 PRODUCT PART 1 OUTLINE A-1 1.3.2 Pin Functions Table 1.3.1 List of Pins for Power Supply System Pin name VDD VSS VDDE AVDDE Pin No. I/O Pull-up 8,51,78,127 3,27,45,66, 82,98,105, 114,116,136 21,59,91,132 36 - - - - Power supply (+) for the internal logic Power supply (-); GND Function - - - - Power supply (+) for the I/O block Analog system power supply (+); AVDDE = VDDE Pin No. I/O Pull-up 85 O - 85-90,92-96 O - 97 99,100 O O - - 101,102 O - 103,104, O 106-111 46-50,52-58, I/O 60-63 137 O - A0: Address bus (A0) when SBUSST(D3/0x4812E) = "0" (default) #BSL: Bus strobe (low byte) signal when SBUSST(D3/0x4812E) = "1" A[10:1]: Address bus (A1-A10) SDA[9:0]: SDRAM address bus (SDA0-SDA9) Address bus (A11) A[13:12]: Address bus (A12-A13) SDA[12:11]: SDRAM address bus (SDA11-SDA12) A[15:14]: Address bus (A14-A15) SDBA[1:0]: SDRAM bank select (SDBA0-SDBA1) Address bus (A16-A23) - Data bus (D0-D15) - Area 10 chip enable for external memory * When CEFUNC[1:0] = "1x", this pin outputs #CE9+#CE10EX signal. #CE9: Area 9 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "00" (default) #CE17: Area 17 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "01" * When CEFUNC[1:0] = "1x", this pin outputs #CE17+#CE18 signal. #CE8: Area 8 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "00", A8DRA(D8/0x48128) = "0" and SDRPC1(D2/0x39FFC0) = "0" (default) #RAS1: Area 8 DRAM row strobe when CEFUNC[1:0](D[A:9]/0x48130) = "00", A8DRA(D8/0x48128) = "1" and SDRPC1(D2/0x39FFC0) = "0" #CE14: Area 14 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "01" or "1x", A14DRA(D8/0x48122) = "0" and SDRPC1(D2/0x39FFC0) = "0" #RAS3: Area 14 DRAM row strobe when CEFUNC[1:0](D[A:9]/0x48130) = "01" or "1x", A14DRA(D8/0x48122) = "1" and SDRPC1(D2/0x39FFC0) = "0" #SDCE1: SDRAM chip enable 1 when SDRPC1(D2/0x39FFC0) = "1" and SDRENA(D7/0x39FFC1) = "1" #CE7: Area 7 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "00", A7DRA(D7/0x48128) = "0" and SDRPC0(D3/0x39FFC0) = "0" (default) #RAS0: Area 7 DRAM row strobe when CEFUNC[1:0](D[A:9]/0x48130) = "00", A7DRA(D7/0x48128) = "1" and SDRPC0(D3/0x39FFC0) = "0" #CE13: Area 13 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "01" or "1x", A13DRA(D7/0x48122) = "0" and SDRPC0(D3/0x39FFC0) = "0" #RAS2: Area 13 DRAM row strobe when CEFUNC[1:0](D[A:9]/0x48130) = "01" or "1x", A13DRA(D7/0x48122) = "1" and SDRPC0(D3/0x39FFC0) = "0" #SDCE0: SDRAM chip enable 0 when SDRPC0(D3/0x39FFC0) = "1" and SDRENA(D7/0x39FFC1) = "1" Area 6 chip enable * When CEFUNC[1:0] = "1x", this pin outputs #CE7+#CE8 signal. #CE5: Area 5 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "00" (default) #CE15: Area 15 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "01" * When CEFUNC[1:0] = "1x", this pin outputs #CE15+#CE16 signal. #CE4: Area 4 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "00" (default) #CE11: Area 11 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "01" * When CEFUNC[1:0] = "1x", this pin outputs #CE11+#CE12 signal. Area 3 chip enable Read signal Read signal for internal ROM emulation memory Table 1.3.2 List of Pins for External Bus Interface Signals Pin name A0 #BSL A[10:1] SDA[9:0] A11 A[13:12] SDA[12:11] A[15:14] SDBA[1:0] A[23:16] D[15:0] #CE10EX #CE9&10EX #CE9 #CE17 #CE17&18 #CE8 #RAS1 #CE14 #RAS3 #SDCE1 131 O - 64 O - #CE7 #RAS0 #CE13 #RAS2 #SDCE0 65 O - #CE6 #CE7&8 #CE5 #CE15 #CE15&16 #CE4 #CE11 #CE11&12 #CE3 #RD #EMEMRD 138 O - 133 O - 139 O - 135 44 126 O O O - - - S1C33L03 PRODUCT PART Function EPSON A-5 1 OUTLINE Pin No. I/O Pull-up #WRL #WR #WE #WRH #BSH #HCAS #SDCAS Pin name 43 O - 42 O 77 O #LCAS #SDRAS 76 O BCLK SDCLK P34 #BUSREQ #CE6 GPIO0 81 O 71 I/O P35 #BUSACK GPIO1 70 I/O P30 #WAIT #CE4&5 75 I/O P20 #DRD SDCKE 80 I/O P21 #DWE #GAAS #SDWE 79 I/O P31 #BUSGET #GARD GPIO2 74 I/O EA10MD1 123 I EA10MD0 124 I A-6 Function #WRL: #WR: #WE: #WRH: #BSH: #HCAS: Write (low byte) signal when SBUSST(D3/0x4812E) = "0" (default) Write signal when SBUSST(D3/0x4812E) = "1" DRAM write signal - Write (high byte) signal when SBUSST(D3/0x4812E) = "0" (default) Bus strobe (high byte) signal when SBUSST(D3/0x4812E) = "1" - DRAM column address strobe (high byte) signal when SDRENA(D7/0x39FFC1) = "0" (default) #SDCAS: SDRAM column address strobe when SDRENA(D7/0x39FFC1) = "1" - #LCAS: DRAM column address strobe (low byte) signal when SDRENA(D7/0x39FFC1) = "0" (default) #SDRAS: SDRAM row address strobe when SDRENA(D7/0x39FFC1) = "1" - BCLK: Bus clock output when SDRENA(D7/0x39FFC1) = "0" (default) SDCLK: SDRAM clock output when SDRENA(D7/0x39FFC1) = "1" - P34: I/O port when CFP34(D4/0x402DC) = "0" (default) #BUSREQ: Bus release request input when CFP34(D4/0x402DC) = "1" #CE6: Area 6 chip enable when CFP34(D4/0x402DC) = "1" and IOC34(D4/0x402DE) = "1" GPIO0: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and BREQEN(D2/0x39FFFD) = "0" - P35: I/O port when CFP35(D5/0x402DC) = "0" (default) #BUSACK: Bus acknowledge output when CFP35(D5/0x402DC) = "1" and CFP34(D4/0x402DC) = "1" GPIO1: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and BREQEN(D2/0x39FFFD) = "0" - P30: I/O port when CFP30(D0/0x402DC) = "0" (default) #WAIT: Wait cycle request input when CFP30(D0/0x402DC) = "1" #CE4&5: Areas 4&5 chip enable when CFP30(D0/0x402DC) = "1" and IOC30(D0/0x402DE) = "1" - P20: I/O port when CFP20(D0/0x402D8) = "0" and SDRENA(D7/0x39FFC1) = "0" (default) #DRD: DRAM read signal output for successive RAS mode when CFP20(D0/0x402D8) = "1" and SDRENA(D7/0x39FFC1) = "0" SDCKE: SDRAM clock enable signal when SDRENA(D7/0x39FFC1) = "1" - P21: I/O port when CFP21(D1/0x402D8) = "0", CFEX2(D2/0x402DF) = "0" and SDRENA(D7/0x39FFC1) = "0" (default) #DWE: DRAM write signal output for successive RAS mode when CFP21(D1/0x402D8) = "1", CFEX2(D2/0x402DF) = "0" and SDRENA(D7/0x39FFC1) = "0" #GAAS: Area address strobe output for GA when CFEX2(D2/0x402DF) = "1" and SDRENA(D7/0x39FFC1) = "0" #SDWE: SDRAM write signal when SDRENA(D7/0x39FFC1) = "1" - P31: I/O port when CFP31(D1/0x402DC) = "0" and CFEX3(D3/0x402DF) = "0" (default) #BUSGET: Bus status monitor signal output for bus release request when CFP31(D1/0x402DC) = "1" and CFEX3(D3/0x402DF) = "0" #GARD: Area read signal output for GA when CFEX3(D3/0x402DF) = "1" GPIO2: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and BREQEN(D2/0x39FFFD) = "0" Pull-up Area 10 boot mode selection EA10MD1 EA10MD0 Mode - 1 1 External ROM mode 1 0 Internal ROM mode EPSON S1C33L03 PRODUCT PART 1 OUTLINE A-1 Table 1.3.3 List of Pins for HSDMA Control Signals Pin name K50 #DMAREQ0 K51 #DMAREQ1 K53 #DMAREQ2 K54 #DMAREQ3 P32 #DMAACK0 #SRDY3 HDQM Pin No. 41 I/O I 40 I 38 I 37 I 73 I/O Pull-up Pull-up K50: #DMAREQ0: Pull-up K51: #DMAREQ1: Pull-up K53: #DMAREQ2: Pull-up K54: #DMAREQ3: - P32: #DMAACK0: #SRDY3: HDQM: P33 #DMAACK1 SIN3 SDA10 72 I/O - P33: #DMAACK1: SIN3: P04 SIN1 #DMAACK2 12 P06 #SCLK1 #DMAACK3 10 P15 EXCL4 #DMAEND0 #SCLK3 LDQM 84 I/O - SDA10: P04: SIN1: I/O - #DMAACK2: P06: #SCLK1: I/O - #DMAACK3: P15: EXCL4: #DMAEND0: #SCLK3: LDQM: P16 EXCL5 #DMAEND1 SOUT3 83 I/O - P16: EXCL5: #DMAEND1: SOUT3: P05 SOUT1 #DMAEND2 11 P07 #SRDY1 #DMAEND3 9 I/O - P05: SOUT1: I/O - #DMAEND2: P07: #SRDY1: #DMAEND3: S1C33L03 PRODUCT PART Function Input port when CFK50(D0/0x402C0) = "0" (default) HSDMA Ch. 0 request input when CFK50(D0/0x402C0) = "1" Input port when CFK51(D1/0x402C0) = "0" (default) HSDMA Ch. 1 request input when CFK51(D1/0x402C0) = "1" Input port when CFK53(D3/0x402C0) = "0" (default) HSDMA Ch. 2 request input when CFK53(D3/0x402C0) = "1" Input port when CFK54(D4/0x402C0) = "0" (default) HSDMA Ch. 3 request input when CFK54(D4/0x402C0) = "1" I/O port when CFP32(D2/0x402DC) = "0" and SDRENA(D7/0x39FFC1) = "0" (default) HSDMA Ch. 0 acknowledge output when CFP32(D2/0x402DC) = "1" and SDRENA(D7/0x39FFC1) = "0" Serial I/F Ch. 3 ready signal input/output when SSRDY3(D3/0x402D7) = "1", CFP32(D2/0x402DC) = "0" and SDRENA(D7/0x39FFC1) = "0" SDRAM data (high byte) input/output mask signal when SDRENA(D7/0x39FFC1) = "1" I/O port when CFP33(D3/0x402DC) = "0" and SDRENA(D7/0x39FFC1) = "0" (default) HSDMA Ch. 1 acknowledge output when CFP33(D3/0x402DC) = "1" and SDRENA(D7/0x39FFC1) = "0" Serial I/F Ch. 3 data input when SSIN3(D0/0x402D7) = "1", CFP33(D3/0x402DC) = "0" and SDRENA(D7/0x39FFC1) = "0" SDRAM address bus bit 10 when SDRENA(D7/0x39FFC1) = "1" I/O port when CFP04(D4/0x402D0) = "0" and CFEX4(D4/0x402DF) = "0" (default) Serial I/F Ch. 1 data input when CFP04(D4/0x402D0) = "1" and CFEX4(D4/0x402DF) = "0" HSDMA Ch. 2 acknowledge output when CFEX4(D4/0x402DF) = "1" I/O port when CFP06(D6/0x402D0) = "0" and CFEX6(D6/0x402DF) = "0" (default) Serial I/F Ch. 1 clock input/output when CFP06(D6/0x402D0) = "1" and CFEX6(D6/0x402DF) = "0" HSDMA Ch. 3 acknowledge output when CFEX6(D6/0x402DF) = "1" I/O port when CFP15(D5/0x402D4) = "0" and SDRENA(D7/0x39FFC1) = "0" (default) 16-bit timer 4 event counter input when CFP15(D5/0x402D4) = "1", IOC15(D5/0x402D6) = "0" and SDRENA(D7/0x39FFC1) = "0" HSDMA Ch. 0 end-of-transfer signal output when CFP15(D5/0x402D4) = "1", IOC15(D5/0x402D6) = "1" and SDRENA(D7/0x39FFC1) = "0" Serial I/F Ch. 3 clock input/output when SSCLK3(D2/0x402D7) = "1", CFP15(D5/0x402D4) = "0" and SDRENA(D7/0x39FFC1) = "0" SDRAM data (low byte) input/output mask signal when SDRENA(D7/0x39FFC1) = "1" I/O port when CFP16(D6/0x402D4) = "0" (default) 16-bit timer 5 event counter input when CFP16(D6/0x402D4) = "1" and IOC16(D6/0x402D6) = "0" HSDMA Ch. 1 end-of-transfer signal output when CFP16(D6/0x402D4) = "1" and IOC16(D6/0x402D6) = "1" Serial I/F Ch. 3 data output when SSOUT3(D1/0x402D7) = "1" and CFP16(D6/0x402D4) = "0" I/O port when CFP05(D5/0x402D0) = "0" and CFEX5(D5/0x402DF) = "0" (default) Serial I/F Ch. 1 data output when CFP05(D5/0x402D0) = "1" and CFEX5(D5/0x402DF) = "0" HSDMA Ch. 2 end-of-transfer signal output when CFEX5(D5/0x402DF) = "1" I/O port when CFP07(D7/0x402D0) = "0" and CFEX7(D7/0x402DF) = "0" (default) Serial I/F Ch. 1 ready signal output when CFP07(D7/0x402D0) = "1" and CFEX5(D5/0x402DF) = "0" HSDMA Ch. 3 end-of-transfer signal output when CFEX7(D7/0x402DF) = "1" EPSON A-7 1 OUTLINE Table 1.3.4 List of Pins for Internal Peripheral Circuits Pin name K50 #DMAREQ0 K51 #DMAREQ1 K52 #ADTRG K53 #DMAREQ2 K54 #DMAREQ3 K60 AD0 K61 AD1 K62 AD2 K63 AD3 K64 AD4 K65 AD5 K66 AD6 K67 AD7 P00 SIN0 P01 SOUT0 P02 #SCLK0 P03 #SRDY0 P04 SIN1 #DMAACK2 Pin No. 41 I/O I 40 I 39 I 38 I 37 I 35 I 34 I 33 I 32 I 31 I 30 I 29 I 28 I 144 I/O 143 I/O 142 I/O 141 I/O 12 I/O P05 SOUT1 #DMAEND2 11 Pull-up Pull-up K50: #DMAREQ0: Pull-up K51: #DMAREQ1: Pull-up K52: #ADTRG: Pull-up K53: #DMAREQ2: Pull-up K54: #DMAREQ3: - K60: AD0: - K61: AD1: - K62: AD2: - K63: AD3: - K64: AD4: - K65: AD5: - K66: AD6: - K67: AD7: - P00: SIN0: - P01: SOUT0: - P02: #SCLK0: - P03: #SRDY0: - P04: SIN1: I/O - #DMAACK2: P05: SOUT1: #DMAEND2: P06 #SCLK1 #DMAACK3 10 P07 #SRDY1 #DMAEND3 9 I/O - P06: #SCLK1: I/O - #DMAACK3: P07: #SRDY1: #DMAEND3: P10 EXCL0 T8UF0 DST0 122 I/O - P10: EXCL0: T8UF0: DST0: A-8 Function Input port when CFK50(D0/0x402C0) = "0" (default) HSDMA Ch. 0 request input when CFK50(D0/0x402C0) = "1" Input port when CFK51(D1/0x402C0) = "0" (default) HSDMA Ch. 1 request input when CFK51(D1/0x402C0) = "1" Input port when CFK52(D2/0x402C0) = "0" (default) A/D converter trigger input when CFK52(D2/0x402C0) = "1" Input port when CFK53(D3/0x402C0) = "0" (default) HSDMA Ch. 2 request input when CFK53(D3/0x402C0) = "1" Input port when CFK54(D4/0x402C0) = "0" (default) HSDMA Ch. 3 request input when CFK54(D4/0x402C0) = "1" Input port when CFK60(D0/0x402C3) = "0" (default) A/D converter Ch. 0 input when CFK60(D0/0x402C3) = "1" Input port when CFK61(D1/0x402C3) = "0" (default) A/D converter Ch. 1 input when CFK61(D1/0x402C3) = "1" Input port when CFK62(D2/0x402C3) = "0" (default) A/D converter Ch. 2 input when CFK62(D2/0x402C3) = "1" Input port when CFK63(D3/0x402C3) = "0" (default) A/D converter Ch. 3 input when CFK63(D3/0x402C3) = "1" Input port when CFK64(D4/0x402C3) = "0" (default) A/D converter Ch. 4 input when CFK64(D4/0x402C3) = "1" Input port when CFK65(D5/0x402C3) = "0" (default) A/D converter Ch. 5 input when CFK65(D5/0x402C3) = "1" Input port when CFK66(D6/0x402C3) = "0" (default) A/D converter Ch. 6 input when CFK66(D6/0x402C3) = "1" Input port when CFK67(D7/0x402C3) = "0" (default) A/D converter Ch. 7 input when CFK67(D7/0x402C3) = "1" I/O port when CFP00(D0/0x402D0) = "0" (default) Serial I/F Ch. 0 data input when CFP00(D0/0x402D0) = "1" I/O port when CFP01(D1/0x402D0) = "0" (default) Serial I/F Ch. 0 data output when CFP01(D1/0x402D0) = "1" I/O port when CFP02(D2/0x402D0) = "0" (default) Serial I/F Ch. 0 clock input/output when CFP02(D2/0x402D0) = "1" I/O port when CFP03(D3/0x402D0) = "0" (default) Serial I/F Ch. 0 ready signal input/output when CFP03(D3/0x402D0) = "1" I/O port when CFP04(D4/0x402D0) = "0" and CFEX4(D4/0x402DF) = "0" (default) Serial I/F Ch. 1 data input when CFP04(D4/0x402D0) = "1" and CFEX4(D4/0x402DF) = "0" HSDMA Ch. 2 acknowledge output when CFEX4(D4/0x402DF) = "1" I/O port when CFP05(D5/0x402D0) = "0" and CFEX5(D5/0x402DF) = "0" (default) Serial I/F Ch. 1 data output when CFP05(D5/0x402D0) = "1" and CFEX5(D5/0x402DF) = "0" HSDMA Ch. 2 end-of-transfer signal output when CFEX5(D5/0x402DF) = "1" I/O port when CFP06(D6/0x402D0) = "0" and CFEX6(D6/0x402DF) = "0" (default) Serial I/F Ch. 1 clock input/output when CFP06(D6/0x402D0) = "1" and CFEX6(D6/0x402DF) = "0" HSDMA Ch. 3 acknowledge output when CFEX6(D6/0x402DF) = "1" I/O port when CFP07(D7/0x402D0) = "0" and CFEX7(D7/0x402DF) = "0" (default) Serial I/F Ch. 1 ready signal output when CFP07(D7/0x402D0) = "1" and CFEX5(D5/0x402DF) = "0" HSDMA Ch. 3 end-of-transfer signal output when CFEX7(D7/0x402DF) = "1" I/O port when CFP10(D0/0x402D4) = "0" and CFEX1(D1/0x402DF) = "0" 16-bit timer 0 event counter input when CFP10(D0/0x402D4) = "1", IOC10(D0/0x402D6) = "0" and CFEX1(D1/0x402DF) = "0" 8-bit timer 0 output when CFP10(D0/0x402D4) = "1", IOC10(D0/0x402D6) = "1" and CFEX1(D1/0x402DF) = "0" DST0 signal output when CFEX1(D1/0x402DF) = "1" (default) EPSON S1C33L03 PRODUCT PART 1 OUTLINE Pin name Pin No. I/O Pull-up P11 EXCL1 T8UF1 DST1 121 I/O - P12 EXCL2 T8UF2 DST2 120 I/O - P13 EXCL3 T8UF3 DPCO 119 I/O - P14 FOSC1 DCLK 118 I/O - P15 EXCL4 #DMAEND0 #SCLK3 LDQM 84 I/O - P16 EXCL5 #DMAEND1 SOUT3 83 I/O - P20 #DRD SDCKE 80 I/O - P21 #DWE #GAAS #SDWE 79 I/O - P22 TM0 P23 TM1 P24 TM2 #SRDY2 1 I/O - 2 I/O - 4 I/O - P25 TM3 #SCLK2 5 I/O - S1C33L03 PRODUCT PART A-1 Function P11: EXCL1: I/O port when CFP11(D1/0x402D4) = "0" and CFEX1(D1/0x402DF) = "0" 16-bit timer 1 event counter input when CFP11(D1/0x402D4) = "1", IOC11(D1/0x402D6) = "0" and CFEX1(D1/0x402DF) = "0" T8UF1: 8-bit timer 1 output when CFP11(D1/0x402D4) = "1", IOC11(D1/0x402D6) = "1" and CFEX1(D1/0x402DF) = "0" DST1: DST1 signal output when CFEX1(D1/0x402DF) = "1" (default) P12: I/O port when CFP12(D2/0x402D4) = "0" and CFEX0(D0/0x402DF) = "0" EXCL2: 16-bit timer 2 event counter input when CFP12(D2/0x402D4) = "1", IOC12(D2/0x402D6) = "0" and CFEX0(D0/0x402DF) = "0" T8UF2: 8-bit timer 2 output when CFP12(D2/0x402D4) = "1", IOC12(D2/0x402D6) = "1" and CFEX0(D0/0x402DF) = "0" DST2: DST2 signal output when CFEX0(D0/0x402DF) = "1" (default) P13: I/O port when CFP13(D3/0x402D4) = "0" and CFEX1(D1/0x402DF) = "0" EXCL3: 16-bit timer 3 event counter input when CFP13(D3/0x402D4) = "1", IOC13(D3/0x402D6) = "0" and CFEX1(D1/0x402DF) = "0" T8UF3: 8-bit timer 3 output when CFP13(D3/0x402D4) = "1", IOC13(D3/0x402D6) = "1" and CFEX1(D1/0x402DF) = "0" DPCO: DPCO signal output when CFEX1(D1/0x402DF) = "1" (default) P14: I/O port when CFP14(D4/0x402D4) = "0" and CFEX0(D0/0x402DF) = "0" FOSC1: OSC1 clock output when CFP14(D4/0x402D4) = "1" and CFEX0(D0/0x402DF) = "0" DCLK: DCLK signal output when CFEX0(D0/0x402DF) = "1" (default) P15: I/O port when CFP15(D5/0x402D4) = "0" and SDRENA(D7/0x39FFC1) = "0" (default) EXCL4: 16-bit timer 4 event counter input when CFP15(D5/0x402D4) = "1", IOC15(D5/0x402D6) = "0" and SDRENA(D7/0x39FFC1) = "0" #DMAEND0: HSDMA Ch. 0 end-of-transfer signal output when CFP15(D5/0x402D4) = "1", IOC15(D5/0x402D6) = "1" and SDRENA(D7/0x39FFC1) = "0" #SCLK3: Serial I/F Ch. 3 clock input/output when SSCLK3(D2/0x402D7) = "1", CFP15(D5/0x402D4) = "0" and SDRENA(D7/0x39FFC1) = "0" LDQM: SDRAM data (low byte) input/output mask signal when SDRENA(D7/0x39FFC1) = "1" P16: I/O port when CFP16(D6/0x402D4) = "0" (default) EXCL5: 16-bit timer 5 event counter input when CFP16(D6/0x402D4) = "1" and IOC16(D6/0x402D6) = "0" #DMAEND1: HSDMA Ch. 1 end-of-transfer signal output when CFP16(D6/0x402D4) = "1" and IOC16(D6/0x402D6) = "1" SOUT3: Serial I/F Ch. 3 data output when SSOUT3(D1/0x402D7) = "1" and CFP16(D6/0x402D4) = "0" P20: I/O port when CFP20(D0/0x402D8) = "0" and SDRENA(D7/0x39FFC1) = "0" (default) #DRD: DRAM read signal output for successive RAS mode when CFP20(D0/0x402D8) = "1" and SDRENA(D7/0x39FFC1) = "0" SDCKE: SDRAM clock enable signal when SDRENA(D7/0x39FFC1) = "1" P21: I/O port when CFP21(D1/0x402D8) = "0", CFEX2(D2/0x402DF) = "0" and SDRENA(D7/0x39FFC1) = "0" (default) #DWE: DRAM write signal output for successive RAS mode when CFP21(D1/0x402D8) = "1", CFEX2(D2/0x402DF) = "0" and SDRENA(D7/0x39FFC1) = "0" #GAAS: Area address strobe output for GA when CFEX2(D2/0x402DF) = "1" and SDRENA(D7/0x39FFC1) = "0" #SDWE: SDRAM write signal when SDRENA(D7/0x39FFC1) = "1" P22: I/O port when CFP22(D2/0x402D8) = "0" (default) TM0: 16-bit timer 0 output when CFP22(D2/0x402D8) = "1" P23: I/O port when CFP23(D3/0x402D8) = "0" (default) TM1: 16-bit timer 1 output when CFP23(D3/0x402D8) = "1" P24: I/O port when CFP24(D4/0x402D8) = "0" (default) TM2: 16-bit timer 2 output when CFP24(D4/0x402D8) = "1" #SRDY2: Serial I/F Ch. 2 ready signal input/output when SSRDY2(D3/0x402DB) = "1" and CFP24(D4/0x402D8) = "0" P25: I/O port when CFP25(D5/0x402D8) = "0" (default) TM3: 16-bit timer 3 output when CFP25(D5/0x402D8) = "1" #SCLK2: Serial I/F Ch. 2 clock input/output when SSCLK2(D2/0x402DB) = "1" and CFP25(D5/0x402D8) = "0" EPSON A-9 1 OUTLINE Pin No. I/O Pull-up P26 TM4 SOUT2 Pin name 6 I/O - P27 TM5 SIN2 7 I/O - P30 #WAIT #CE4&5 75 I/O - P31 #BUSGET #GARD GPIO2 74 I/O - P32 #DMAACK0 #SRDY3 HDQM 73 I/O - P33 #DMAACK1 SIN3 SDA10 72 I/O - P34 #BUSREQ #CE6 GPIO0 71 I/O - P35 #BUSACK GPIO1 70 I/O - A-10 Function P26: TM4: SOUT2: I/O port when CFP26(D6/0x402D8) = "0" (default) 16-bit timer 4 output when CFP26(D6/0x402D8) = "1" Serial I/F Ch. 2 data output when SSOUT2(D1/0x402DB) = "1" and CFP26(D6/0x402D8) = "0" P27: I/O port when CFP27(D7/0x402D8) = "0" (default) TM5: 16-bit timer 5 output when CFP27(D7/0x402D8) = "1" SIN2: Serial I/F Ch. 2 data input when SSIN2(D0/0x402DB) = "1" and CFP27(D7/0x402D8) = "0" P30: I/O port when CFP30(D0/0x402DC) = "0" (default) #WAIT: Wait cycle request input when CFP30(D0/0x402DC) = "1" #CE4&5: Areas 4&5 chip enable when CFP30(D0/0x402DC) = "1" and IOC30(D0/0x402DE) = "1" P31: I/O port when CFP31(D1/0x402DC) = "0" and CFEX3(D3/0x402DF) = "0" (default) #BUSGET: Bus status monitor signal output for bus release request when CFP31(D1/0x402DC) = "1" and CFEX3(D3/0x402DF) = "0" #GARD: Area read signal output for GA when CFEX3(D3/0x402DF) = "1" GPIO2: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and BREQEN(D2/0x39FFFD) = "0" P32: I/O port when CFP32(D2/0x402DC) = "0" and SDRENA(D7/0x39FFC1) = "0" (default) #DMAACK0: HSDMA Ch. 0 acknowledge output when CFP32(D2/0x402DC) = "1" and SDRENA(D7/0x39FFC1) = "0" #SRDY3: Serial I/F Ch. 3 ready signal input/output when SSRDY3(D3/0x402D7) = "1", CFP32(D2/0x402DC) = "0" and SDRENA(D7/0x39FFC1) = "0" HDQM: SDRAM data (high byte) input/output mask signal when SDRENA(D7/0x39FFC1) = "1" P33: I/O port when CFP33(D3/0x402DC) = "0" and SDRENA(D7/0x39FFC1) = "0" (default) #DMAACK1: HSDMA Ch. 1 acknowledge output when CFP33(D3/0x402DC) = "1" and SDRENA(D7/0x39FFC1) = "0" SIN3: Serial I/F Ch. 3 data input when SSIN3(D0/0x402D7) = "1", CFP33(D3/0x402DC) = "0" and SDRENA(D7/0x39FFC1) = "0" SDA10: SDRAM address bus bit 10 when SDRENA(D7/0x39FFC1) = "1" P34: I/O port when CFP34(D4/0x402DC) = "0" (default) #BUSREQ: Bus release request input when CFP34(D4/0x402DC) = "1" #CE6: Area 6 chip enable when CFP34(D4/0x402DC) = "1" and IOC34(D4/0x402DE) = "1" GPIO0: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and BREQEN(D2/0x39FFFD) = "0" P35: I/O port when CFP35(D5/0x402DC) = "0" (default) #BUSACK: Bus acknowledge output when CFP35(D5/0x402DC) = "1" and CFP34(D4/0x402DC) = "1" GPIO1: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and BREQEN(D2/0x39FFFD) = "0" EPSON S1C33L03 PRODUCT PART 1 OUTLINE A-1 Table 1.3.5 List of Pins for LCD Controller Pin No. I/O Pull-up FPDAT[7:4] Pin name 13-16 O - FPDAT[3:0] GPO[6:3] FPFRAME FPLINE FPSHIFT DRDY(MOD) (FPSHIFT2) LCDPWR 17-20 O - 23 24 25 22 O O O O - - - - 26 O - Pin name Pin No. I/O Pull-up 68 67 129 128 112,113 I O I O I - - - - - 115 - - Pin No. I/O Pull-up /down ICEMD 125 I DSIO 117 I/O #X2SPD 140 I #NMI #RESET 130 69 I I Function 4 high-order bits of data bus for 8-bit LCD panels Data bus for 4-bit LCD panels FPDAT[3:0]: 4 low-order bits of data bus for 8-bit LCD panels GPO[6:3]: General-purpose outputs when a 4-bit LCD panel is used Frame pulse output Line pulse output Shift clock output MOD: LCD backplane bias (for panels other than 8-bit color panel format 1) FPSHIFT2: Second shift clock (for 8-bit color panel format 1) LCD power control output (active high) Table 1.3.6 List of Pins for Clock Generator OSC1 OSC2 OSC3 OSC4 PLLS[1:0] PLLC Function Low-speed (OSC1) oscillation input (32 kHz crystal oscillator or external clock input) Low-speed (OSC1) oscillation output High-speed (OSC3) oscillation input (crystal/ceramic oscillator or external clock input) High-speed (OSC3) oscillation output PLL set-up pins PLLS1 PLLS0 fin (fOSC3) fout (fPSCIN) 1 1 10-25MHz 20-50MHz 0 1 10-12.5MHz 40-50MHz 0 0 PLL is not used L Capacitor connecting pin for PLL Table 1.3.7 List of Other Pins Pin name Function Pulldown High-impedance control input pin When this pin is set to High, all the output pins go into high-impedance state. This makes it possible to disable the S1C33 chip on the board. Pull-up Serial I/O pin for debugging This pin is used to communicate with the debugging tool S5U1C33000H. - Clock doubling mode set-up pin 1: CPU clock = bus clock x 1, 0: CPU clock = bus clock x 2 Pull-up NMI request input pin Pull-up Initial reset input pin Note: "#" in the pin names indicates that the signal is low active. S1C33L03 PRODUCT PART EPSON A-11 2 POWER SUPPLY 2 Power Supply This chapter explains the operating voltage of the S1C33L03. 2.1 Power Supply Pins The S1C33L03 has the power supply pins shown in Table 2.1.1. Pin name VDD VSS VDDE AVDDE Table 2.1.1 Power Supply Pins Pin No. Function 8,51,78,127 Power supply (+) for the internal logic 3,27,45,66,82,98,105,114,116,136 Power supply (-); GND 21,59,91,132 Power supply (+) for the I/O block 36 Analog system power supply (+); AVDDE = VDDE 1.8 to 3.6 V VDD CPU core 1.8 to 5.5 V Internal peripheral circuit VDDE I/O interface circuit 1.8 to 5.5 V GND I/O pins AVDDE Analog circuits (A/D converter) VSS Figure 2.1.1 Power Supply System 2.2 Operating Voltage (VDD, VSS) The core CPU and internal peripheral circuits operate with a voltage supplied between the VDD and VSS pins. The following operating voltage can be used: VDD = 1.8 V to 3.6 V (VSS = GND) Note: The S1C33L03 has 4 VDD pins and 10 VSS pins. Be sure to supply the operating voltage to all the pins. Do not open any of them. The operating clock frequency range (OSC3) is 5 MHz to 50 MHz with this voltage. A-12 EPSON S1C33L03 PRODUCT PART 2 POWER SUPPLY A-1 2.3 Power Supply for I/O Interface (VDDE) A-2 The VDDE voltage is used for interfacing with external I/O signals. For the output interface of the S1C33L03, the VDDE voltage is used as high level and the VSS voltage as low level. Normally, supply the same voltage level as VDD. It can be supplied separately from VDD for 5 V interface. The VSS pin is used for the ground common with VDD. The following voltage is enabled for VDDE: VDDE = 1.8 V to 5.5 V (VSS = GND) Notes: * The S1C33L03 has 4 VDDE pins. Be sure to supply a voltage to all the pins. Do not open any of them. * When an external clock is input to the OSC1 or OSC3 pin, the clock signal level must be VDD. * The interface voltage level of the DSIO, P10, P11, P12, P13 and P14 pins is VDD. 2.4 Power Supply for Analog Circuits (AVDDE) The analog power supply pin (AVDDE) is provided separately from the VDD and VDDE pins in order that the digital circuits do not affect the analog circuit (A/D converter). The AVDDE pin is used to supply an analog power voltage and the VSS pin is used as the analog ground. Supply the same voltage level as the VDDE to the AVDDE pin. AVDDE = VDDE, VSS = GND Note: Be sure to supply VDDE to the AVDDE pin even if the analog circuit is not used. Noise on the analog power lines decrease the A/D converting precision, so use a stabilized power supply and make the board pattern with consideration given to that. S1C33L03 PRODUCT PART EPSON A-13 3 INTERNAL MEMORY 3 Internal Memory This chapter explains the internal memory configuration. Figure 3.1 shows the S1C33L03 memory map. Address Area Areas 18-11 0xFFFFFFF External Memory Area 10 0x1000000 0x0FFFFFF Areas 9-7 0x0C00000 0x0BFFFFF Area 6 0x0400000 0x03FFFFF Areas 5-4 0x0300000 0x02FFFFF Area 3 0x0100000 0x00FFFFF Area 2 0x0080000 0x007FFFF Area 1 0x0060000 0x005FFFF External Memory External Memory LCD controller SDRAM controller External Memory (Reserved) For middleware use (Reserved) For CPU, debug mode (Mirror of internal peripheral circuits) 0x0050000 0x004FFFF Internal peripheral circuits 0x0040000 0x003FFFF Area 0 (Mirror of internal peripheral circuits) 0x0030000 0x002FFFF (Mirror of internal RAM) 0x0002000 0x0001FFF Internal RAM (8KB) 0x0000000 Figure 3.1 Memory Map Area 2 is used in debug mode only and it cannot be accessed in user mode (normal program execution status). 3.1 ROM and Boot Address The S1C33L03 does not have a built-in ROM. The boot address is fixed at 0x0C00000, and so external ROM/Flash should be used in Area 10. For setting up Area 10, refer to the "BCU (Bus Control Unit)" in "S1C33L03 FUNCTION PART" in this manual. A-14 EPSON S1C33L03 PRODUCT PART 3 INTERNAL MEMORY A-1 3.2 RAM The S1C33L03 has a built-in 8KB RAM. The RAM is allocated to Area 0, address 0x0000000 to address 0x0001FFF. The internal RAM is a 32-bit sized device and data can be read/written in 1 cycle regardless of data size (byte, halfword or word). S1C33L03 PRODUCT PART EPSON A-15 A-3 4 PERIPHERAL CIRCUITS 4 Peripheral Circuits This chapter lists the built-in peripheral circuits and the I/O memory map. For details of the circuits, refer to the "S1C33L03 FUNCTION PART". 4.1 List of Peripheral Circuits The S1C33L03 consists of the C33 Core Block, C33 SDRAM Controller Block, C33 Peripheral Block, C33 DMA Block, C33 Analog Block, and C33 LCD Controller Block. C33 Core Block CPU BCU (Bus Control Unit) ITC (Interrupt Controller) CLG (Clock Generator) DBG (Debug Unit) S1C33000 32-bit RISC type CPU 24-bit external address bus and 16-bit data bus All the BCU functions can be used. 39 types of interrupts are available. OSC3 oscillation circuit (33 MHz Max.), PLL and OSC1 oscillation circuit (32.768 kHz Typ.) built-in Functional block for debugging with the S5U1C33000H (In-Circuit Debugger for S1C33 Family) C33 SDRAM Controller Block SDRAM interface Up to two 128M-bit SDRAMs or a 256M-bit SDRAM (32MB) can be connected directly. C33 Peripheral Block Prescaler 8-bit programmable timer 16-bit programmable timer Serial interface Input and I/O ports Clock timer Programmable clock generator for peripheral circuits 6 channels with clock output function 6 channels with event counter, clock output and watchdog timer functions 4 channels (asynchronous mode, clock synchronous mode and IrDA are selectable.) 13 bits of input ports and 29 bits of I/O ports (used for peripheral I/O) 1 channel with alarm function C33 DMA Block HSDMA (High-Speed DMA) 4 channels IDMA (Intelligent DMA) 128 channels C33 Analog Block A/D converter 10-bit A/D converter with 8 input channels C33 LCD Controller Block LCD controller A-16 4 or 8-bit monochrome/color LCD interface 2, 4 or 16-level (1, 2 or 4 bit-per-pixel) gray-scale display 2, 4, 16 or 256-level (1, 2, 4 or 8 bit-per-pixel) color display Resolution examples: 640 x 480 pixels with 1bpp color depth 640 x 240 pixels with 2bpp color depth 320 x 240 pixels with 4bpp color depth 240 x 160 pixels with 8bpp color depth EPSON S1C33L03 PRODUCT PART 4 PERIPHERAL CIRCUITS A-1 4.2 I/O Memory Map Table 4.2.1 I/O Memory Map Register name Address 8-bit timer 4/5 clock select register 0040140 (B) 8-bit timer 4/5 clock control register 0040145 (B) Bit Name D7-2 - D1 P8TPCK5 D0 P8TPCK4 D7 D6 D5 D4 D3 D2 D1 D0 P8TON5 P8TS52 P8TS51 P8TS50 P8TON4 P8TS42 P8TS41 P8TS40 Function reserved 8-bit timer 5 clock selection 8-bit timer 4 clock selection 8-bit timer 5 clock control 8-bit timer 5 clock division ratio selection 8-bit timer 4 clock control 8-bit timer 4 clock division ratio selection 8-bit timer clock select register 0040146 (B) D7-4 D3 D2 D1 D0 - P8TPCK3 P8TPCK2 P8TPCK1 P8TPCK0 reserved 8-bit timer 3 clock selection 8-bit timer 2 clock selection 8-bit timer 1 clock selection 8-bit timer 0 clock selection 16-bit timer 0 clock control register 0040147 (B) D7-4 D3 D2 D1 D0 - P16TON0 P16TS02 P16TS01 P16TS00 reserved 16-bit timer 0 clock control 16-bit timer 0 clock division ratio selection 16-bit timer 1 clock control register 0040148 (B) D7-4 D3 D2 D1 D0 - P16TON1 P16TS12 P16TS11 P16TS10 reserved 16-bit timer 1 clock control 16-bit timer 1 clock division ratio selection 16-bit timer 2 clock control register 0040149 (B) D7-4 D3 D2 D1 D0 - P16TON2 P16TS22 P16TS21 P16TS20 reserved 16-bit timer 2 clock control 16-bit timer 2 clock division ratio selection Init. - - 0 0 - 0 when being read. R/W : selected by R/W Prescaler clock select register (0x40181) 0 0 0 0 R/W R/W : selected by R/W Prescaler clock select R/W register (0x40181) 1 /1 1 /1 1 On 1 1 1 1 1 0 1 0 0 1 0 1 0 0 0 0 1 On 1 1 1 1 1 0 1 0 0 1 0 1 0 0 0 0 0 Divided clk. 0 Divided clk. 0 Off /256 /128 /64 /32 /16 /8 /4 /2 0 Off /4096 /2048 /64 /32 /16 /8 /4 /2 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 - 1 1 1 1 /1 /1 /1 /1 0 0 0 0 Divided clk. Divided clk. Divided clk. Divided clk. - 1 On P16TS0[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 Off Division ratio /4096 /1024 /256 /64 /16 /4 /2 /1 - 1 On P16TS1[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 Off Division ratio /4096 /1024 /256 /64 /16 /4 /2 /1 - 1 On P16TS2[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 Off Division ratio /4096 /1024 /256 /64 /16 /4 /2 /1 R/W A-4 Setting Remarks 8-bit timer 5 can generate the clock for the serial I/F Ch.3. 0 0 0 0 R/W R/W : selected by R/W Prescaler clock select R/W register (0x40181) 8-bit timer 4 can generate the clock for the serial I/F Ch.2. - 0 0 0 0 - R/W R/W R/W R/W 0 when being read. : selected by Prescaler clock select register (0x40181) - 0 0 0 0 - 0 when being read. R/W R/W : selected by Prescaler clock select register (0x40181) 16-bit timer 0 can be used as a watchdog timer. - 0 0 0 0 - 0 when being read. R/W R/W : selected by Prescaler clock select register (0x40181) - 0 0 0 0 - 0 when being read. R/W R/W : selected by Prescaler clock select register (0x40181) (B) in [Address] indicates an 8-bit register and (HW) indicates a 16-bit register. The meaning of the symbols described in [Init.] are listed below: 0, 1: Initial values that are set at initial reset. (However, the registers for the bus and input/output ports are not initialized at hot start.) X: Not initialized at initial reset. -: Not set in the circuit. S1C33L03 PRODUCT PART EPSON A-17 4 PERIPHERAL CIRCUITS Register name Address Bit Name Function 16-bit timer 3 clock control register 004014A D7-4 - (B) D3 P16TON3 D2 P16TS32 D1 P16TS31 D0 P16TS30 reserved 16-bit timer 3 clock control 16-bit timer 3 clock division ratio selection 16-bit timer 4 clock control register 004014B D7-4 - (B) D3 P16TON4 D2 P16TS42 D1 P16TS41 D0 P16TS40 reserved 16-bit timer 4 clock control 16-bit timer 4 clock division ratio selection 16-bit timer 5 clock control register 004014C D7-4 - (B) D3 P16TON5 D2 P16TS52 D1 P16TS51 D0 P16TS50 reserved 16-bit timer 5 clock control 16-bit timer 5 clock division ratio selection 8-bit timer 0/1 clock control register 004014D (B) 8-bit timer 1 clock control 8-bit timer 1 clock division ratio selection D7 D6 D5 D4 D3 D2 D1 D0 A-18 P8TON1 P8TS12 P8TS11 P8TS10 P8TON0 P8TS02 P8TS01 P8TS00 8-bit timer 0 clock control 8-bit timer 0 clock division ratio selection EPSON Setting - 1 On P16TS3[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 Off Division ratio /4096 /1024 /256 /64 /16 /4 /2 /1 - 1 On P16TS4[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 Off Division ratio /4096 /1024 /256 /64 /16 /4 /2 /1 - 1 On P16TS5[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 Off Division ratio /4096 /1024 /256 /64 /16 /4 /2 /1 1 On P8TS1[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 1 On P8TS0[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 Off Division ratio /4096 /2048 /1024 /512 /256 /128 /64 /32 0 Off Division ratio /256 /128 /64 /32 /16 /8 /4 /2 Init. R/W Remarks - 0 0 0 0 - 0 when being read. R/W R/W : selected by Prescaler clock select register (0x40181) - 0 0 0 0 - 0 when being read. R/W R/W : selected by Prescaler clock select register (0x40181) - 0 0 0 0 - 0 when being read. R/W R/W : selected by Prescaler clock select register (0x40181) 0 0 0 0 R/W R/W : selected by Prescaler clock select register (0x40181) 8-bit timer 1 can generate the OSC3 oscillation-stabilize waiting period. 0 0 0 0 R/W R/W : selected by Prescaler clock select register (0x40181) 8-bit timer 0 can generate the DRAM refresh clock. S1C33L03 PRODUCT PART 4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Name 8-bit timer 2/3 clock control register D7 D6 D5 D4 P8TON3 P8TS32 P8TS31 P8TS30 004014E (B) D3 D2 D1 D0 P8TON2 P8TS22 P8TS21 P8TS20 A/D clock 004014F control register (B) D7-4 D3 D2 D1 D0 Clock timer Run/Stop register D7-2 - D1 TCRST D0 TCRUN 0040151 (B) Clock timer 0040152 interrupt (B) control register Clock timer 0040153 divider register (B) Clock timer second register 0040154 (B) - PSONAD PSAD2 PSAD1 PSAD0 Function 8-bit timer 3 clock control 8-bit timer 3 clock division ratio selection 8-bit timer 2 clock control 8-bit timer 2 clock division ratio selection reserved A/D converter clock control A/D converter clock division ratio selection reserved Clock timer reset Clock timer Run/Stop control Setting 1 On P8TS3[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 1 On P8TS2[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 Init. R/W 0 Off Division ratio /256 /128 /64 /32 /16 /8 /4 /2 0 Off Division ratio /4096 /2048 /64 /32 /16 /8 /4 /2 - R/W R/W : selected by Prescaler clock select register (0x40181) 8-bit timer 2 can generate the clock for the serial I/F Ch.0. - 0 when being read. W 0 when being read. R/W X X X R/W X X X R/W X X R/W Reset by writing 1. R/W Reset by writing 1. Low Low Low Low Low Low Low Low X X X X X X X X R R R R R R R R - 0 to 59 seconds - X X X X X X - R 0 Invalid 0 Stop Clock timer interrupt factor selection D4 D3 D2 TCASE2 TCASE1 TCASE0 D1 D0 TCIF TCAF TCISE[2:0] Interrupt factor 1 1 1 None 1 1 0 Day 1 0 1 Hour 1 0 0 Minute 0 1 1 1 Hz 0 1 0 2 Hz 0 0 1 8 Hz 0 0 0 32 Hz Alarm factor Clock timer alarm factor selection TCASE[2:0] 1 X X Day X 1 X Hour X X 1 Minute 0 0 0 None 1 Generated 0 Not generated Interrupt factor generation flag 1 Generated 0 Not generated Alarm factor generation flag D7 D6 D5 D4 D3 D2 D1 D0 TCD7 TCD6 TCD5 TCD4 TCD3 TCD2 TCD1 TCD0 Clock timer data 1 Hz Clock timer data 2 Hz Clock timer data 4 Hz Clock timer data 8 Hz Clock timer data 16 Hz Clock timer data 32 Hz Clock timer data 64 Hz Clock timer data 128 Hz - TCMD5 TCMD4 TCMD3 TCMD2 TCMD1 TCMD0 reserved Clock timer second counter data TCMD5 = MSB TCMD0 = LSB EPSON 0 0 0 0 - X X - 1 Reset 1 Run TCISE2 TCISE1 TCISE0 S1C33L03 PRODUCT PART 8-bit timer 3 can generate the clock for the serial I/F Ch.1. - 0 when being read. R/W R/W : selected by Prescaler clock select register (0x40181) 0 Off Division ratio /256 /128 /64 /32 /16 /8 /4 /2 D7 D6 D5 D7-6 D5 D4 D3 D2 D1 D0 R/W R/W : selected by Prescaler clock select register (0x40181) - 0 0 0 0 1 On P8TS0[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 Remarks High High High High High High High High 0 0 0 0 0 0 0 0 0 when being read. A-19 A-4 4 PERIPHERAL CIRCUITS Register name Address Bit Clock timer 0040155 minute register (B) D7-6 D5 D4 D3 D2 D1 D0 - TCHD5 TCHD4 TCHD3 TCHD2 TCHD1 TCHD0 reserved Clock timer minute counter data TCHD5 = MSB TCHD0 = LSB Clock timer hour register D7-5 D4 D3 D2 D1 D0 - TCDD4 TCDD3 TCDD2 TCDD1 TCDD0 Clock timer 0040157 day (low-order) (B) register D7 D6 D5 D4 D3 D2 D1 D0 Clock timer day (highorder) register 0040158 (B) Clock timer minute comparison register 0040159 (B) Clock timer hour comparison register Clock timer day comparison register A-20 Name Function Setting Init. R/W Remarks - 0 to 59 minutes - X X X X X X - 0 when being read. R/W reserved Clock timer hour counter data TCDD4 = MSB TCDD0 = LSB - 0 to 23 hours - X X X X X - 0 when being read. R/W TCND7 TCND6 TCND5 TCND4 TCND3 TCND2 TCND1 TCND0 Clock timer day counter data (low-order 8 bits) TCND0 = LSB 0 to 65535 days (low-order 8 bits) X X X X X X X X R/W D7 D6 D5 D4 D3 D2 D1 D0 TCND15 TCND14 TCND13 TCND12 TCND11 TCND10 TCND9 TCND8 Clock timer day counter data (high-order 8 bits) TCND15 = MSB 0 to 65535 days (high-order 8 bits) X X X X X X X X R/W D7-6 D5 D4 D3 D2 D1 D0 - TCCH5 TCCH4 TCCH3 TCCH2 TCCH1 TCCH0 reserved Clock timer minute comparison data TCCH5 = MSB TCCH0 = LSB - 0 to 59 minutes (Note) Can be set within 0-63. - X X X X X X - 0 when being read. R/W 004015A D7-5 - (B) D4 TCCD4 D3 TCCD3 D2 TCCD2 D1 TCCD1 D0 TCCD0 reserved - 0 to 23 hours Clock timer hour comparison data (Note) Can be set within 0-31. TCCD4 = MSB TCCD0 = LSB - X X X X X - 0 when being read. R/W 004015B D7-5 - (B) D4 TCCN4 D3 TCCN3 D2 TCCN2 D1 TCCN1 D0 TCCN0 reserved Clock timer day comparison data TCCN4 = MSB TCCN0 = LSB - X X X X X - 0 when being read. R/W Compared with TCND[4:0]. 0040156 (B) EPSON - 0 to 31 days S1C33L03 PRODUCT PART 4 PERIPHERAL CIRCUITS A-1 Register name Address Bit 8-bit timer 0 0040160 control register (B) D7-3 D2 D1 D0 Name Function - PTOUT0 PSET0 PTRUN0 reserved 8-bit timer 0 clock output control 8-bit timer 0 preset 8-bit timer 0 Run/Stop control Setting - 1 On 1 Preset 1 Run 0 Off 0 Invalid 0 Stop Init. R/W Remarks - 0 - 0 - 0 when being read. R/W W 0 when being read. R/W 8-bit timer 0 reload data register 0040161 (B) D7 D6 D5 D4 D3 D2 D1 D0 RLD07 RLD06 RLD05 RLD04 RLD03 RLD02 RLD01 RLD00 8-bit timer 0 reload data RLD07 = MSB RLD00 = LSB 0 to 255 X X X X X X X X R/W 8-bit timer 0 counter data register 0040162 (B) D7 D6 D5 D4 D3 D2 D1 D0 PTD07 PTD06 PTD05 PTD04 PTD03 PTD02 PTD01 PTD00 8-bit timer 0 counter data PTD07 = MSB PTD00 = LSB 0 to 255 X X X X X X X X R - PTOUT1 PSET1 PTRUN1 reserved 8-bit timer 1 clock output control 8-bit timer 1 preset 8-bit timer 1 Run/Stop control - - 0 - 0 - 0 when being read. R/W W 0 when being read. R/W 8-bit timer 1 0040164 control register (B) D7-3 D2 D1 D0 1 On 1 Preset 1 Run 0 Off 0 Invalid 0 Stop 8-bit timer 1 reload data register 0040165 (B) D7 D6 D5 D4 D3 D2 D1 D0 RLD17 RLD16 RLD15 RLD14 RLD13 RLD12 RLD11 RLD10 8-bit timer 1 reload data RLD17 = MSB RLD10 = LSB 0 to 255 X X X X X X X X R/W 8-bit timer 1 counter data register 0040166 (B) D7 D6 D5 D4 D3 D2 D1 D0 PTD17 PTD16 PTD15 PTD14 PTD13 PTD12 PTD11 PTD10 8-bit timer 1 counter data PTD17 = MSB PTD10 = LSB 0 to 255 X X X X X X X X R - PTOUT2 PSET2 PTRUN2 reserved 8-bit timer 2 clock output control 8-bit timer 2 preset 8-bit timer 2 Run/Stop control - - 0 - 0 - 0 when being read. R/W W 0 when being read. R/W 8-bit timer 2 0040168 control register (B) D7-3 D2 D1 D0 1 On 1 Preset 1 Run 0 Off 0 Invalid 0 Stop 8-bit timer 2 reload data register 0040169 (B) D7 D6 D5 D4 D3 D2 D1 D0 RLD27 RLD26 RLD25 RLD24 RLD23 RLD22 RLD21 RLD20 8-bit timer 2 reload data RLD27 = MSB RLD20 = LSB 0 to 255 X X X X X X X X R/W 8-bit timer 2 counter data register 004016A (B) D7 D6 D5 D4 D3 D2 D1 D0 PTD27 PTD26 PTD25 PTD24 PTD23 PTD22 PTD21 PTD20 8-bit timer 2 counter data PTD27 = MSB PTD20 = LSB 0 to 255 X X X X X X X X R S1C33L03 PRODUCT PART EPSON A-21 A-4 4 PERIPHERAL CIRCUITS Register name Address Bit Name Function 8-bit timer 3 004016C D7-3 - control register (B) D2 PTOUT3 D1 PSET3 D0 PTRUN3 reserved 8-bit timer 3 clock output control 8-bit timer 3 preset 8-bit timer 3 Run/Stop control 8-bit timer 3 reload data register 004016D (B) D7 D6 D5 D4 D3 D2 D1 D0 RLD37 RLD36 RLD35 RLD34 RLD33 RLD32 RLD31 RLD30 8-bit timer 3 reload data RLD37 = MSB RLD30 = LSB 8-bit timer 3 counter data register 004016E (B) D7 D6 D5 D4 D3 D2 D1 D0 PTD37 PTD36 PTD35 PTD34 PTD33 PTD32 PTD31 PTD30 8-bit timer 3 counter data PTD37 = MSB PTD30 = LSB - PTOUT4 PSET4 PTRUN4 reserved 8-bit timer 4 clock output control 8-bit timer 4 preset 8-bit timer 4 Run/Stop control 8-bit timer 4 0040174 control register (B) D7-3 D2 D1 D0 Setting - Init. R/W Remarks - 0 - 0 - 0 when being read. R/W W 0 when being read. R/W 0 to 255 X X X X X X X X R/W 0 to 255 X X X X X X X X R - - 0 - 0 - 0 when being read. R/W W 0 when being read. R/W 1 On 1 Preset 1 Run 0 Off 0 Invalid 0 Stop 1 On 1 Preset 1 Run 0 Off 0 Invalid 0 Stop 8-bit timer 4 reload data register 0040175 (B) D7 D6 D5 D4 D3 D2 D1 D0 RLD47 RLD46 RLD45 RLD44 RLD43 RLD42 RLD41 RLD40 8-bit timer 4 reload data RLD47 = MSB RLD40 = LSB 0 to 255 X X X X X X X X R/W 8-bit timer 4 counter data register 0040176 (B) D7 D6 D5 D4 D3 D2 D1 D0 PTD47 PTD46 PTD45 PTD44 PTD43 PTD42 PTD41 PTD40 8-bit timer 4 counter data PTD47 = MSB PTD40 = LSB 0 to 255 X X X X X X X X R - PTOUT5 PSET5 PTRUN5 reserved 8-bit timer 5 clock output control 8-bit timer 5 preset 8-bit timer 5 Run/Stop control - - 0 - 0 - 0 when being read. R/W W 0 when being read. R/W 8-bit timer 5 0040178 control register (B) D7-3 D2 D1 D0 1 On 1 Preset 1 Run 0 Off 0 Invalid 0 Stop 8-bit timer 5 reload data register 0040179 (B) D7 D6 D5 D4 D3 D2 D1 D0 RLD57 RLD56 RLD55 RLD54 RLD53 RLD52 RLD51 RLD50 8-bit timer 5 reload data RLD57 = MSB RLD50 = LSB 0 to 255 X X X X X X X X R/W 8-bit timer 5 counter data register 004017A (B) D7 D6 D5 D4 D3 D2 D1 D0 PTD57 PTD56 PTD55 PTD54 PTD53 PTD52 PTD51 PTD50 8-bit timer 5 counter data PTD57 = MSB PTD50 = LSB 0 to 255 X X X X X X X X R A-22 EPSON S1C33L03 PRODUCT PART 4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Name Function Setting Init. R/W Remarks Watchdog 0040170 timer write(B) protect register D7 WRWD D6-0 - EWD write protection - 1 Write enabled 0 Write-protect - 0 - R/W - 0 when being read. Watchdog timer enable register D7-2 - D1 EWD D0 - - Watchdog timer enable - - 1 NMI enabled 0 NMI disabled - - 0 - - 0 when being read. R/W - 0 when being read. 0040171 (B) S1C33L03 PRODUCT PART EPSON A-23 A-4 4 PERIPHERAL CIRCUITS Register name Address Bit Name Power control register D7 D6 CLKDT1 CLKDT0 System clock division ratio selection D5 D4-3 D2 D1 D0 PSCON - CLKCHG SOSC3 SOSC1 Prescaler On/Off control reserved 1 OSC3 CPU operating clock switch High-speed (OSC3) oscillation On/Off 1 On Low-speed (OSC1) oscillation On/Off 1 On 0040180 (B) Function Setting CLKDT[1:0] 1 1 1 0 0 1 0 0 1 On R/W 1 0 1 1 1 R/W - Writing 1 not allowed. R/W R/W R/W - 0 0 - R/W - 0 1 0 0 - 0 when being read. R/W R/W - Do not write 1. R/W 0 0 0 0 0 0 0 0 R/W D7-1 - D0 PSCDT0 reserved Prescaler clock selection Clock option register D7-4 D3 D2 D1 D0 - HLT2OP 8T1ON - PF1ON - HALT clock option OSC3-stabilize waiting function reserved OSC1 external output control CLGP7 CLGP6 CLGP5 CLGP4 CLGP3 CLGP2 CLGP1 CLGP0 Power control register protect flag Writing 10010110 (0x96) removes the write protection of the power control register (0x40180) and the clock option register (0x40190). Writing another value set the write protection. Power control 004019E protect register (B) A-24 D7 D6 D5 D4 D3 D2 D1 D0 EPSON 1 OSC1 0 OSC3/PLL - 1 On 1 Off 0 Off 0 On - 1 On Remarks 0 0 Prescaler clock 0040181 select register (B) 0040190 (B) Init. R/W Division ratio 1/8 1/4 1/2 1/1 0 Off - 0 OSC1 0 Off 0 Off 0 Off S1C33L03 PRODUCT PART 4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Name Function Serial I/F Ch.0 transmit data register 00401E0 (B) D7 D6 D5 D4 D3 D2 D1 D0 TXD07 TXD06 TXD05 TXD04 TXD03 TXD02 TXD01 TXD00 Serial I/F Ch.0 transmit data TXD07(06) = MSB TXD00 = LSB 0x0 to 0xFF(0x7F) Serial I/F Ch.0 receive data register 00401E1 (B) D7 D6 D5 D4 D3 D2 D1 D0 RXD07 RXD06 RXD05 RXD04 RXD03 RXD02 RXD01 RXD00 Serial I/F Ch.0 receive data RXD07(06) = MSB RXD00 = LSB 0x0 to 0xFF(0x7F) X X X X X X X X R 7-bit asynchronous mode does not use RXD07 (fixed at 0). - - 0 0 0 0 1 0 - R R/W R/W R/W R R 0 when being read. 1 Enabled 0 Disabled 1 Enabled 0 Disabled 1 With parity 0 No parity 1 Odd 0 Even 1 2 bits 0 1 bit 1 #SCLK0 0 Internal clock SMD0[1:0] Transfer mode 1 1 8-bit asynchronous 1 0 7-bit asynchronous Clock sync. Slave 0 1 Clock sync. Master 0 0 0 0 X X X X X X R/W R/W R/W Valid only in R/W asynchronous mode. R/W R/W R/W - - X X X X X - 0 when being read. R/W R/W Valid only in R/W asynchronous mode. R/W Serial I/F Ch.0 00401E2 D7-6 - status register (B) D5 TEND0 D4 FER0 D3 PER0 D2 OER0 D1 TDBE0 D0 RDBF0 - Ch.0 transmit-completion flag Ch.0 flaming error flag Ch.0 parity error flag Ch.0 overrun error flag Ch.0 transmit data buffer empty Ch.0 receive data buffer full Serial I/F Ch.0 00401E3 control register (B) Ch.0 transmit enable Ch.0 receive enable Ch.0 parity enable Ch.0 parity mode selection Ch.0 stop bit selection Ch.0 input clock selection Ch.0 transfer mode selection Serial I/F Ch.0 IrDA register D7 D6 D5 D4 D3 D2 D1 D0 TXEN0 RXEN0 EPR0 PMD0 STPB0 SSCK0 SMD01 SMD00 00401E4 D7-5 - (B) D4 DIVMD0 D3 IRTL0 D2 IRRL0 D1 IRMD01 D0 IRMD00 S1C33L03 PRODUCT PART - Ch.0 async. clock division ratio Ch.0 IrDA I/F output logic inversion Ch.0 IrDA I/F input logic inversion Ch.0 interface mode selection EPSON Setting 1 1 1 1 1 1 Transmitting Error Error Error Empty Buffer full 1 1/8 1 Inverted 1 Inverted IRMD0[1:0] 1 1 1 0 0 1 0 0 0 0 0 0 0 0 Init. R/W End Normal Normal Normal Buffer full Empty 0 1/16 0 Direct 0 Direct I/F mode reserved IrDA 1.0 reserved General I/F X X X X X X X X Remarks R/W 7-bit asynchronous mode does not use TXD07. Reset by writing 0. Reset by writing 0. Reset by writing 0. A-25 A-4 4 PERIPHERAL CIRCUITS Register name Address Bit Serial I/F Ch.1 transmit data register 00401E5 (B) D7 D6 D5 D4 D3 D2 D1 D0 TXD17 TXD16 TXD15 TXD14 TXD13 TXD12 TXD11 TXD10 Name Serial I/F Ch.1 transmit data TXD17(16) = MSB TXD10 = LSB Function 0x0 to 0xFF(0x7F) X X X X X X X X Serial I/F Ch.1 receive data register 00401E6 (B) D7 D6 D5 D4 D3 D2 D1 D0 RXD17 RXD16 RXD15 RXD14 RXD13 RXD12 RXD11 RXD10 Serial I/F Ch.1 receive data RXD17(16) = MSB RXD10 = LSB 0x0 to 0xFF(0x7F) X X X X X X X X R 7-bit asynchronous mode does not use RXD17 (fixed at 0). - - 0 0 0 0 1 0 - R R/W R/W R/W R R 0 when being read. 1 Enabled 0 Disabled 1 Enabled 0 Disabled 1 With parity 0 No parity 1 Odd 0 Even 1 2 bits 0 1 bit 1 #SCLK1 0 Internal clock SMD1[1:0] Transfer mode 1 1 8-bit asynchronous 1 0 7-bit asynchronous Clock sync. Slave 0 1 Clock sync. Master 0 0 0 0 X X X X X X R/W R/W R/W Valid only in R/W asynchronous mode. R/W R/W R/W - - X X X X X - 0 when being read. R/W R/W Valid only in R/W asynchronous mode. R/W Serial I/F Ch.1 00401E7 D7-6 - status register (B) D5 TEND1 D4 FER1 D3 PER1 D2 OER1 D1 TDBE1 D0 RDBF1 - Ch.1 transmit-completion flag Ch.1 flaming error flag Ch.1 parity error flag Ch.1 overrun error flag Ch.1 transmit data buffer empty Ch.1 receive data buffer full Serial I/F Ch.1 00401E8 control register (B) Ch.1 transmit enable Ch.1 receive enable Ch.1 parity enable Ch.1 parity mode selection Ch.1 stop bit selection Ch.1 input clock selection Ch.1 transfer mode selection D7 D6 D5 D4 D3 D2 D1 D0 TXEN1 RXEN1 EPR1 PMD1 STPB1 SSCK1 SMD11 SMD10 Setting 1 1 1 1 1 1 Transmitting Error Error Error Empty Buffer full 0 0 0 0 0 0 Init. R/W End Normal Normal Normal Buffer full Empty Serial I/F Ch.1 IrDA register 00401E9 D7-5 - (B) D4 DIVMD1 D3 IRTL1 D2 IRRL1 D1 IRMD11 D0 IRMD10 - Ch.1 async. clock division ratio Ch.1 IrDA I/F output logic inversion Ch.1 IrDA I/F input logic inversion Ch.1 interface mode selection Serial I/F Ch.2 transmit data register 00401F0 (B) D7 D6 D5 D4 D3 D2 D1 D0 TXD27 TXD26 TXD25 TXD24 TXD23 TXD22 TXD21 TXD20 Serial I/F Ch.2 transmit data TXD27(26) = MSB TXD20 = LSB 0x0 to 0xFF(0x7F) X X X X X X X X R/W Serial I/F Ch.2 receive data register 00401F1 (B) D7 D6 D5 D4 D3 D2 D1 D0 RXD27 RXD26 RXD25 RXD24 RXD23 RXD22 RXD21 RXD20 Serial I/F Ch.2 receive data RXD27(26) = MSB RXD20 = LSB 0x0 to 0xFF(0x7F) X X X X X X X X R D7-6 D5 D4 D3 D2 D1 D0 - TEND2 FER2 PER2 OER2 TDBE2 RDBF2 reserved Ch.2 transmit-completion flag Ch.2 flaming error flag Ch.2 parity error flag Ch.2 overrun error flag Ch.2 transmit data buffer empty Ch.2 receive data buffer full - - 0 0 0 0 1 0 - R R/W R/W R/W R R Serial I/F Ch.2 00401F2 status register (B) A-26 EPSON 1 1/8 1 Inverted 1 Inverted IRMD1[1:0] 1 1 1 0 0 1 0 0 1 1 1 1 1 1 Transmitting Error Error Error Empty Buffer full 0 1/16 0 Direct 0 Direct I/F mode reserved IrDA 1.0 reserved General I/F 0 0 0 0 0 0 End Normal Normal Normal Buffer full Empty Remarks R/W 7-bit asynchronous mode does not use TXD17. Reset by writing 0. Reset by writing 0. Reset by writing 0. 0 when being read. Reset by writing 0. Reset by writing 0. Reset by writing 0. S1C33L03 PRODUCT PART 4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Name Function Serial I/F Ch.2 00401F3 control register (B) D7 D6 D5 D4 D3 D2 D1 D0 TXEN2 RXEN2 EPR2 PMD2 STPB2 SSCK2 SMD21 SMD20 Ch.2 transmit enable Ch.2 receive enable Ch.2 parity enable Ch.2 parity mode selection Ch.2 stop bit selection Ch.2 input clock selection Ch.2 transfer mode selection - DIVMD2 IRTL2 IRRL2 IRMD21 IRMD20 reserved Ch.2 async. clock division ratio Ch.2 IrDA I/F output logic inversion Ch.2 IrDA I/F input logic inversion Ch.2 interface mode selection Setting Init. R/W Remarks 1 Enabled 0 Disabled 1 Enabled 0 Disabled 1 With parity 0 No parity 1 Odd 0 Even 1 2 bits 0 1 bit 1 #SCLK2 0 Internal clock SMD2[1:0] Transfer mode 1 1 8-bit asynchronous 1 0 7-bit asynchronous Clock sync. Slave 0 1 Clock sync. Master 0 0 0 0 X X X X X X R/W R/W R/W Valid only in R/W asynchronous mode. R/W R/W R/W - - X X X X X - 0 when being read. R/W R/W Valid only in R/W asynchronous mode. R/W Serial I/F Ch.2 IrDA register 00401F4 (B) D7-5 D4 D3 D2 D1 D0 Serial I/F Ch.3 transmit data register 00401F5 (B) D7 D6 D5 D4 D3 D2 D1 D0 TXD37 TXD36 TXD35 TXD34 TXD33 TXD32 TXD31 TXD30 Serial I/F Ch.3 transmit data TXD37(36) = MSB TXD30 = LSB 0x0 to 0xFF(0x7F) X X X X X X X X R/W Serial I/F Ch.3 receive data register 00401F6 (B) D7 D6 D5 D4 D3 D2 D1 D0 RXD37 RXD36 RXD35 RXD34 RXD33 RXD32 RXD31 RXD30 Serial I/F Ch.3 receive data RXD37(36) = MSB RXD30 = LSB 0x0 to 0xFF(0x7F) X X X X X X X X R D7-6 D5 D4 D3 D2 D1 D0 - TEND3 FER3 PER3 OER3 TDBE3 RDBF3 reserved Ch.3 transmit-completion flag Ch.3 flaming error flag Ch.3 parity error flag Ch.3 overrun error flag Ch.3 transmit data buffer empty Ch.3 receive data buffer full - - 0 0 0 0 1 0 - R R/W R/W R/W R R D7 D6 D5 D4 D3 D2 D1 D0 TXEN3 RXEN3 EPR3 PMD3 STPB3 SSCK3 SMD31 SMD30 Ch.3 transmit enable Ch.3 receive enable Ch.3 parity enable Ch.3 parity mode selection Ch.3 stop bit selection Ch.3 input clock selection Ch.3 transfer mode selection 1 Enabled 0 Disabled 1 Enabled 0 Disabled 1 With parity 0 No parity 1 Odd 0 Even 1 2 bits 0 1 bit 1 #SCLK3 0 Internal clock SMD3[1:0] Transfer mode 1 1 8-bit asynchronous 1 0 7-bit asynchronous Clock sync. Slave 0 1 Clock sync. Master 0 0 0 0 X X X X X X R/W R/W R/W Valid only in R/W asynchronous mode. R/W R/W R/W D7-5 D4 D3 D2 D1 D0 - DIVMD3 IRTL3 IRRL3 IRMD31 IRMD30 reserved Ch.3 async. clock division ratio Ch.3 IrDA I/F output logic inversion Ch.3 IrDA I/F input logic inversion Ch.3 interface mode selection - - X X X X X - 0 when being read. R/W R/W Valid only in R/W asynchronous mode. R/W Serial I/F Ch.3 00401F7 status register (B) Serial I/F Ch.3 00401F8 control register (B) Serial I/F Ch.3 IrDA register 00401F9 (B) S1C33L03 PRODUCT PART EPSON 1 1/8 1 Inverted 1 Inverted IRMD2[1:0] 1 1 1 0 0 1 0 0 1 1 1 1 1 1 0 1/16 0 Direct 0 Direct I/F mode reserved IrDA 1.0 reserved General I/F Transmitting Error Error Error Empty Buffer full 1 1/8 1 Inverted 1 Inverted IRMD3[1:0] 1 1 1 0 0 1 0 0 0 0 0 0 0 0 End Normal Normal Normal Buffer full Empty 0 1/16 0 Direct 0 Direct I/F mode reserved IrDA 1.0 reserved General I/F 0 when being read. Reset by writing 0. Reset by writing 0. Reset by writing 0. A-27 A-4 4 PERIPHERAL CIRCUITS Register name Address Bit A/D conversion 0040240 result (low(B) order) register D7 D6 D5 D4 D3 D2 D1 D0 Name ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 Function 0 0 0 0 0 0 0 0 R - 0x0 to 0x3FF (high-order 2 bits) - 0 0 - R - - 0 0 0 D7-2 - D1 ADD9 D0 ADD8 - A/D converted data (high-order 2 bits) ADD9 = MSB A/D trigger register D7-6 D5 D4 D3 - MS TS1 TS0 - A/D conversion mode selection A/D conversion trigger selection D2 D1 D0 CH2 CH1 CH0 A/D conversion channel status D7-6 D5 D4 D3 - CE2 CE1 CE0 - A/D converter end channel selection D2 D1 D0 CS2 CS1 CS0 A/D converter start channel selection - ADF ADE ADST OWE - Conversion-complete flag A/D enable A/D conversion control/status Overwrite error flag A/D channel register 0040243 (B) A/D enable register 0040244 (B) D7-4 D3 D2 D1 D0 A/D sampling register 0040245 (B) D7-2 - D1 ST1 D0 ST0 A-28 Init. R/W 0x0 to 0x3FF (low-order 8 bits) A/D conversion 0040241 result (high(B) order) register 0040242 (B) Setting A/D converted data (low-order 8 bits) ADD0 = LSB - Input signal sampling time setup EPSON 1 Continuous TS[1:0] 1 1 1 0 0 1 0 0 CH[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 CE[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 CS[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 1 1 1 1 Completed Enabled Start/Run Error ST[1:0] 1 1 1 0 0 1 0 0 0 Normal Trigger #ADTRG pin 8-bit timer 0 16-bit timer 0 Software Channel AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 0 0 0 Remarks 0 when being read. - 0 when being read. R/W R/W R - End channel AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Start channel AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 - 0 0 0 - 0 when being read. R/W 0 0 0 R/W - - 0 0 0 0 - 0 when being read. R Reset when ADD is read. R/W R/W R/W Reset by writing 0. - 1 1 - 0 when being read. R/W Use with 9 clocks. 0 0 0 0 Run/Standby Disabled Stop Normal - Sampring time 9 clocks 7 clocks 5 clocks 3 clocks S1C33L03 PRODUCT PART 4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Port input 0/1 0040260 interrupt (B) priority register D7 D6 D5 D4 D3 D2 D1 D0 - PP1L2 PP1L1 PP1L0 - PP0L2 PP0L1 PP0L0 reserved Port input 1 interrupt level - 0 to 7 reserved Port input 0 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - PP3L2 PP3L1 PP3L0 - PP2L2 PP2L1 PP2L0 reserved Port input 3 interrupt level - 0 to 7 reserved Port input 2 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - PK1L2 PK1L1 PK1L0 - PK0L2 PK0L1 PK0L0 reserved Key input 1 interrupt level - 0 to 7 reserved Key input 0 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - PHSD1L2 PHSD1L1 PHSD1L0 - PHSD0L2 PHSD0L1 PHSD0L0 reserved High-speed DMA Ch.1 interrupt level - 0 to 7 reserved High-speed DMA Ch.0 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - PHSD3L2 PHSD3L1 PHSD3L0 - PHSD2L2 PHSD2L1 PHSD2L0 reserved High-speed DMA Ch.3 interrupt level - 0 to 7 reserved High-speed DMA Ch.2 interrupt level - 0 to 7 - PDM2 PDM1 PDM0 reserved IDMA interrupt level Port input 2/3 0040261 interrupt (B) priority register Key input 0040262 interrupt (B) priority register High-speed 0040263 DMA Ch.0/1 (B) interrupt priority register High-speed 0040264 DMA Ch.2/3 (B) interrupt priority register Name Function Setting - 0 when being read. R/W - X X X - X X X - 0 when being read. R/W - X X X - X X X - 0 when being read. R/W - X X X - X X X - 0 when being read. R/W - X X X - X X X - 0 when being read. R/W - 0 to 7 - X X X - 0 when being read. R/W - X X X - X X X - 0 when being read. R/W - X X X - X X X - 0 when being read. R/W - X X X - X X X - 0 when being read. R/W D7-3 D2 D1 D0 16-bit timer 0/1 0040266 interrupt (B) priority register D7 D6 D5 D4 D3 D2 D1 D0 - P16T12 P16T11 P16T10 - P16T02 P16T01 P16T00 reserved 16-bit timer 1 interrupt level - 0 to 7 reserved 16-bit timer 0 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - P16T32 P16T31 P16T30 - P16T22 P16T21 P16T20 reserved 16-bit timer 3 interrupt level - 0 to 7 reserved 16-bit timer 2 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - P16T52 P16T51 P16T50 - P16T42 P16T41 P16T40 reserved 16-bit timer 5 interrupt level - 0 to 7 reserved 16-bit timer 4 interrupt level - 0 to 7 16-bit timer 4/5 0040268 interrupt (B) priority register S1C33L03 PRODUCT PART EPSON Remarks - X X X - X X X IDMA interrupt 0040265 priority register (B) 16-bit timer 2/3 0040267 interrupt (B) priority register Init. R/W A-4 - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W A-29 4 PERIPHERAL CIRCUITS Register name Address Bit 8-bit timer, 0040269 serial I/F Ch.0 (B) interrupt priority register D7 D6 D5 D4 D3 D2 D1 D0 - PSIO02 PSIO01 PSIO00 - P8TM2 P8TM1 P8TM0 reserved Serial interface Ch.0 interrupt level - 0 to 7 reserved 8-bit timer 0-3 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - PAD2 PAD1 PAD0 - PSIO12 PSIO11 PSIO10 reserved A/D converter interrupt level - 0 to 7 reserved Serial interface Ch.1 interrupt level - 0 to 7 Clock timer 004026B D7-3 - interrupt (B) D2 PCTM2 priority register D1 PCTM1 D0 PCTM0 reserved Clock timer interrupt level Port input 4/5 004026C interrupt (B) priority register Serial I/F Ch.1, 004026A A/D interrupt (B) priority register Port input 6/7 004026D interrupt (B) priority register A-30 Name Function Setting Remarks - X X X - X X X - 0 when being read. R/W - X X X - X X X - 0 when being read. R/W - 0 to 7 - X X X - Writing 1 not allowed. R/W - X X X - X X X - 0 when being read. R/W - X X X - X X X - 0 when being read. R/W D7 D6 D5 D4 D3 D2 D1 D0 - PP5L2 PP5L1 PP5L0 - PP4L2 PP4L1 PP4L0 reserved Port input 5 interrupt level - 0 to 7 reserved Port input 4 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - PP7L2 PP7L1 PP7L0 - PP6L2 PP6L1 PP6L0 reserved Port input 7 interrupt level - 0 to 7 reserved Port input 6 interrupt level - 0 to 7 EPSON Init. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W S1C33L03 PRODUCT PART 4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Name Function Key input, 0040270 port input 0-3 (B) interrupt enable register D7-6 D5 D4 D3 D2 D1 D0 - EK1 EK0 EP3 EP2 EP1 EP0 reserved Key input 1 Key input 0 Port input 3 Port input 2 Port input 1 Port input 0 DMA interrupt 0040271 enable register (B) D7-5 D4 D3 D2 D1 D0 - EIDMA EHDM3 EHDM2 EHDM1 EHDM0 reserved IDMA High-speed DMA Ch.3 High-speed DMA Ch.2 High-speed DMA Ch.1 High-speed DMA Ch.0 16-bit timer 0/1 0040272 interrupt (B) enable register D7 D6 D5-4 D3 D2 D1-0 E16TC1 E16TU1 - E16TC0 E16TU0 - D7 D6 D5-4 D3 D2 D1-0 Setting - 1 Enabled 0 Disabled - 1 Enabled 0 Disabled 16-bit timer 1 comparison A 16-bit timer 1 comparison B reserved 16-bit timer 0 comparison A 16-bit timer 0 comparison B reserved 1 Enabled 0 Disabled E16TC3 E16TU3 - E16TC2 E16TU2 - 16-bit timer 3 comparison A 16-bit timer 3 comparison B reserved 16-bit timer 2 comparison A 16-bit timer 2 comparison B reserved 1 Enabled D7 D6 D5-4 D3 D2 D1-0 E16TC5 E16TU5 - E16TC4 E16TU4 - 16-bit timer 5 comparison A 16-bit timer 5 comparison B reserved 16-bit timer 4 comparison A 16-bit timer 4 comparison B reserved 1 Enabled 8-bit timer 0040275 interrupt (B) enable register D7-4 D3 D2 D1 D0 - E8TU3 E8TU2 E8TU1 E8TU0 reserved 8-bit timer 3 underflow 8-bit timer 2 underflow 8-bit timer 1 underflow 8-bit timer 0 underflow Serial I/F 0040276 interrupt (B) enable register D7-6 D5 D4 D3 D2 D1 D0 - ESTX1 ESRX1 ESERR1 ESTX0 ESRX0 ESERR0 reserved SIF Ch.1 transmit buffer empty SIF Ch.1 receive buffer full SIF Ch.1 receive error SIF Ch.0 transmit buffer empty SIF Ch.0 receive buffer full SIF Ch.0 receive error Port input 4-7, 0040277 clock timer, (B) A/D interrupt enable register D7-6 D5 D4 D3 D2 D1 D0 - EP7 EP6 EP5 EP4 ECTM EADE reserved Port input 7 Port input 6 Port input 5 Port input 4 Clock timer A/D converter 16-bit timer 2/3 0040273 interrupt (B) enable register 16-bit timer 4/5 0040274 interrupt (B) enable register S1C33L03 PRODUCT PART - 1 Enabled 0 Disabled - 0 Disabled - 1 Enabled 0 Disabled - 0 Disabled - 1 Enabled 0 Disabled - - 1 Enabled 0 Disabled - 1 Enabled 0 Disabled - 1 Enabled EPSON 0 Disabled Init. R/W Remarks - 0 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W R/W - 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W 0 0 - 0 0 - R/W R/W - 0 when being read. R/W R/W - 0 when being read. 0 0 - 0 0 - R/W R/W - 0 when being read. R/W R/W - 0 when being read. 0 0 - 0 0 - R/W R/W - 0 when being read. R/W R/W - 0 when being read. - 0 0 0 0 - 0 when being read. R/W R/W R/W R/W - 0 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W R/W - 0 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W R/W A-31 A-4 4 PERIPHERAL CIRCUITS Register name Address Bit Key input, 0040280 port input 0-3 (B) interrupt factor flag register D7-6 D5 D4 D3 D2 D1 D0 - FK1 FK0 FP3 FP2 FP1 FP0 Name reserved Key input 1 Key input 0 Port input 3 Port input 2 Port input 1 Port input 0 Function DMA interrupt factor flag register 0040281 (B) D7-5 D4 D3 D2 D1 D0 - FIDMA FHDM3 FHDM2 FHDM1 FHDM0 reserved IDMA High-speed DMA Ch.3 High-speed DMA Ch.2 High-speed DMA Ch.1 High-speed DMA Ch.0 16-bit timer 0/1 0040282 interrupt factor (B) flag register D7 D6 D5-4 D3 D2 D1-0 F16TC1 F16TU1 - F16TC0 F16TU0 - D7 D6 D5-4 D3 D2 D1-0 Setting - 1 Factor is generated 0 No factor is generated - 1 Factor is generated 0 No factor is generated 16-bit timer 1 comparison A 16-bit timer 1 comparison B reserved 16-bit timer 0 comparison A 16-bit timer 0 comparison B reserved 1 Factor is generated 0 No factor is generated F16TC3 F16TU3 - F16TC2 F16TU2 - 16-bit timer 3 comparison A 16-bit timer 3 comparison B reserved 16-bit timer 2 comparison A 16-bit timer 2 comparison B reserved 1 Factor is generated D7 D6 D5-4 D3 D2 D1-0 F16TC5 F16TU5 - F16TC4 F16TU4 - 16-bit timer 5 comparison A 16-bit timer 5 comparison B reserved 16-bit timer 4 comparison A 16-bit timer 4 comparison B reserved 1 Factor is generated 8-bit timer 0040285 interrupt factor (B) flag register D7-4 D3 D2 D1 D0 - F8TU3 F8TU2 F8TU1 F8TU0 reserved 8-bit timer 3 underflow 8-bit timer 2 underflow 8-bit timer 1 underflow 8-bit timer 0 underflow Serial I/F 0040286 interrupt factor (B) flag register D7-6 D5 D4 D3 D2 D1 D0 - FSTX1 FSRX1 FSERR1 FSTX0 FSRX0 FSERR0 reserved SIF Ch.1 transmit buffer empty SIF Ch.1 receive buffer full SIF Ch.1 receive error SIF Ch.0 transmit buffer empty SIF Ch.0 receive buffer full SIF Ch.0 receive error Port input 4-7, 0040287 clock timer, A/D (B) interrupt factor flag register D7-6 D5 D4 D3 D2 D1 D0 - FP7 FP6 FP5 FP4 FCTM FADE reserved Port input 7 Port input 6 Port input 5 Port input 4 Clock timer A/D converter 16-bit timer 2/3 0040283 interrupt factor (B) flag register 16-bit timer 4/5 0040284 interrupt factor (B) flag register A-32 - 1 Factor is generated 0 No factor is generated - 0 No factor is generated - 1 Factor is generated 0 No factor is generated - 0 No factor is generated - 1 Factor is generated 0 No factor is generated - - 1 Factor is generated 0 No factor is generated - 1 Factor is generated 0 No factor is generated - 1 Factor is generated EPSON 0 No factor is generated Init. R/W Remarks - X X X X X X - 0 when being read. R/W R/W R/W R/W R/W R/W - X X X X X - 0 when being read. R/W R/W R/W R/W R/W X X - X X - R/W R/W - 0 when being read. R/W R/W - 0 when being read. X X - X X - R/W R/W - 0 when being read. R/W R/W - 0 when being read. X X - X X - R/W R/W - 0 when being read. R/W R/W - 0 when being read. - X X X X - 0 when being read. R/W R/W R/W R/W - X X X X X X - 0 when being read. R/W R/W R/W R/W R/W R/W - X X X X X X - 0 when being read. R/W R/W R/W R/W R/W R/W S1C33L03 PRODUCT PART 4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Name Port input 0-3, high-speed DMA Ch. 0/1, 16-bit timer 0 IDMA request register D7 D6 D5 D4 D3 D2 D1 D0 R16TC0 R16TU0 RHDM1 RHDM0 RP3 RP2 RP1 RP0 16-bit timer 0 comparison A 16-bit timer 0 comparison B High-speed DMA Ch.1 High-speed DMA Ch.0 Port input 3 Port input 2 Port input 1 Port input 0 1 IDMA request 16-bit timer 1-4 0040291 IDMA request (B) register D7 D6 D5 D4 D3 D2 D1 D0 R16TC4 R16TU4 R16TC3 R16TU3 R16TC2 R16TU2 R16TC1 R16TU1 16-bit timer 4 comparison A 16-bit timer 4 comparison B 16-bit timer 3 comparison A 16-bit timer 3 comparison B 16-bit timer 2 comparison A 16-bit timer 2 comparison B 16-bit timer 1 comparison A 16-bit timer 1 comparison B 1 IDMA request 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA request register 0040292 (B) D7 D6 D5 D4 D3 D2 D1 D0 RSTX0 RSRX0 R8TU3 R8TU2 R8TU1 R8TU0 R16TC5 R16TU5 SIF Ch.0 transmit buffer empty SIF Ch.0 receive buffer full 8-bit timer 3 underflow 8-bit timer 2 underflow 8-bit timer 1 underflow 8-bit timer 0 underflow 16-bit timer 5 comparison A 16-bit timer 5 comparison B Serial I/F Ch.1, A/D, port input 4-7 IDMA request register 0040293 (B) D7 D6 D5 D4 D3 D2 D1 D0 RP7 RP6 RP5 RP4 - RADE RSTX1 RSRX1 0040294 (B) D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 1-4 0040295 IDMA enable (B) register 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA enable register Serial I/F Ch.1, A/D, port input 4-7 IDMA enable register Port input 0-3, high-speed DMA Ch. 0/1, 16-bit timer 0 IDMA enable register 0040290 (B) Function Setting Remarks 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 Interrupt request 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 1 IDMA request 0 Interrupt request 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Port input 7 Port input 6 Port input 5 Port input 4 reserved A/D converter SIF Ch.1 transmit buffer empty SIF Ch.1 receive buffer full 1 IDMA request 0 Interrupt request 1 IDMA request 0 Interrupt request 0 0 0 0 - 0 0 0 R/W R/W R/W R/W - 0 when being read. R/W R/W R/W DE16TC0 DE16TU0 DEHDM1 DEHDM0 DEP3 DEP2 DEP1 DEP0 16-bit timer 0 comparison A 16-bit timer 0 comparison B High-speed DMA Ch.1 High-speed DMA Ch.0 Port input 3 Port input 2 Port input 1 Port input 0 1 IDMA enabled 0 IDMA disabled 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W D7 D6 D5 D4 D3 D2 D1 D0 DE16TC4 DE16TU4 DE16TC3 DE16TU3 DE16TC2 DE16TU2 DE16TC1 DE16TU1 16-bit timer 4 comparison A 16-bit timer 4 comparison B 16-bit timer 3 comparison A 16-bit timer 3 comparison B 16-bit timer 2 comparison A 16-bit timer 2 comparison B 16-bit timer 1 comparison A 16-bit timer 1 comparison B 1 IDMA enabled 0 IDMA disabled 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 0040296 (B) D7 D6 D5 D4 D3 D2 D1 D0 DESTX0 DESRX0 DE8TU3 DE8TU2 DE8TU1 DE8TU0 DE16TC5 DE16TU5 SIF Ch.0 transmit buffer empty SIF Ch.0 receive buffer full 8-bit timer 3 underflow 8-bit timer 2 underflow 8-bit timer 1 underflow 8-bit timer 0 underflow 16-bit timer 5 comparison A 16-bit timer 5 comparison B 1 IDMA enabled 0 IDMA disabled 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 0040297 (B) D7 D6 D5 D4 D3 D2 D1 D0 DEP7 DEP6 DEP5 DEP4 - DEADE DESTX1 DESRX1 Port input 7 Port input 6 Port input 5 Port input 4 reserved A/D converter SIF Ch.1 transmit buffer empty SIF Ch.1 receive buffer full 1 IDMA enabled 0 IDMA disabled 0 0 0 0 - 0 0 0 R/W R/W R/W R/W - 0 when being read. R/W R/W R/W S1C33L03 PRODUCT PART EPSON 0 Interrupt request Init. R/W - - 1 IDMA enabled 0 IDMA disabled A-4 A-33 4 PERIPHERAL CIRCUITS Register name Address Bit Name High-speed DMA Ch.0/1 trigger set-up register D7 D6 D5 D4 HSD1S3 HSD1S2 HSD1S1 HSD1S0 High-speed DMA Ch.1 trigger set-up D3 D2 D1 D0 HSD0S3 HSD0S2 HSD0S1 HSD0S0 High-speed DMA Ch.0 trigger set-up D7 D6 D5 D4 HSD3S3 HSD3S2 HSD3S1 HSD3S0 High-speed DMA Ch.3 trigger set-up D3 D2 D1 D0 HSD2S3 HSD2S2 HSD2S1 HSD2S0 High-speed DMA Ch.2 trigger set-up High-speed DMA Ch.2/3 trigger set-up register 0040298 (B) 0040299 (B) High-speed 004029A D7-4 - DMA software (B) D3 HST3 trigger register D2 HST2 D1 HST1 D0 HST0 Flag set/reset method select register A-34 004029F (B) Function reserved HSDMA Ch.3 software trigger HSDMA Ch.2 software trigger HSDMA Ch.1 software trigger HSDMA Ch.0 software trigger Setting Software trigger K51 input (falling edge) K51 input (rising edge) Port 1 input Port 5 input 8-bit timer Ch.1 underflow 16-bit timer Ch.1 compare B 16-bit timer Ch.1 compare A 16-bit timer Ch.5 compare B 16-bit timer Ch.5 compare A SI/F Ch.1 Rx buffer full SI/F Ch.1 Tx buffer empty A/D conversion completion Software trigger K50 input (falling edge) K50 input (rising edge) Port 0 input Port 4 input 8-bit timer Ch.0 underflow 16-bit timer Ch.0 compare B 16-bit timer Ch.0 compare A 16-bit timer Ch.4 compare B 16-bit timer Ch.4 compare A SI/F Ch.0 Rx buffer full SI/F Ch.0 Tx buffer empty A/D conversion completion 0 0 0 0 R/W 0 0 0 0 R/W 0 1 2 3 4 5 6 7 8 9 A B C 0 1 2 3 4 5 6 7 8 9 A B C Software trigger K54 input (falling edge) K54 input (rising edge) Port 3 input Port 7 input 8-bit timer Ch.3 underflow 16-bit timer Ch.3 compare B 16-bit timer Ch.3 compare A 16-bit timer Ch.5 compare B 16-bit timer Ch.5 compare A SI/F Ch.1 Rx buffer full SI/F Ch.1 Tx buffer empty A/D conversion completion Software trigger K53 input (falling edge) K53 input (rising edge) Port 2 input Port 6 input 8-bit timer Ch.2 underflow 16-bit timer Ch.2 compare B 16-bit timer Ch.2 compare A 16-bit timer Ch.4 compare B 16-bit timer Ch.4 compare A SI/F Ch.0 Rx buffer full SI/F Ch.0 Tx buffer empty A/D conversion completion 0 0 0 0 R/W 0 0 0 0 R/W - 0 0 0 0 - W W W W - 1 - R/W 1 R/W 1 R/W - 1 Trigger 0 Invalid D7-3 - reserved - 0 RD/WR D2 DENONLY IDMA enable register set method 1 Set only selection D1 IDMAONLY IDMA request register set method 1 Set only 0 RD/WR selection D0 RSTONLY Interrupt factor flag reset method 1 Reset only 0 RD/WR selection EPSON Init. R/W 0 1 2 3 4 5 6 7 8 9 A B C 0 1 2 3 4 5 6 7 8 9 A B C Remarks 0 when being read. S1C33L03 PRODUCT PART 4 PERIPHERAL CIRCUITS A-1 Register name Address K5 function select register Bit Name Function 00402C0 D7-5 - (B) D4 CFK54 D3 CFK53 D2 CFK52 D1 CFK51 D0 CFK50 reserved K54 function selection K53 function selection K52 function selection K51 function selection K50 function selection K5 input port data register 00402C1 D7-5 - (B) D4 K54D D3 K53D D2 K52D D1 K51D D0 K50D reserved K54 input port data K53 input port data K52 input port data K51 input port data K50 input port data K6 function select register 00402C3 (B) D7 D6 D5 D4 D3 D2 D1 D0 CFK67 CFK66 CFK65 CFK64 CFK63 CFK62 CFK61 CFK60 K6 input port data register 00402C4 (B) D7 D6 D5 D4 D3 D2 D1 D0 K67D K66D K65D K64D K63D K62D K61D K60D S1C33L03 PRODUCT PART Setting Init. R/W - 1 1 1 1 1 #DMAREQ3 #DMAREQ2 #ADTRG #DMAREQ1 #DMAREQ0 0 0 0 0 0 K54 K53 K52 K51 K50 - - R R R R R K67 K66 K65 K64 K63 K62 K61 K60 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 Low - - - - - - - - R R R R R R R R 0 Low K67 function selection K66 function selection K65 function selection K64 function selection K63 function selection K62 function selection K61 function selection K60 function selection 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 K67 input port data K66 input port data K65 input port data K64 input port data K63 input port data K62 input port data K61 input port data K60 input port data 1 High EPSON - 0 when being read. R/W R/W R/W R/W R/W - - - - - - 1 High AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 - 0 0 0 0 0 Remarks 0 when being read. A-35 A-4 4 PERIPHERAL CIRCUITS Register name Address Bit Interrupt factor 00402C5 FP function switching register D7 D6 T8CH5S0 SIO3TS0 8-bit timer 5 underflow SIO Ch.3 transmit buffer empty D5 D4 T8CH4S0 SIO3RS0 8-bit timer 4 underflow SIO Ch.3 receive buffer full D3 SIO2TS0 SIO Ch.2 transmit buffer empty D2 SIO3ES0 SIO Ch.3 receive error D1 SIO2RS0 SIO Ch.2 receive buffer full D0 SIO2ES0 SIO Ch.2 receive error D7 D6 D5 D4 D3 D2 D1 D0 SPT31 SPT30 SPT21 SPT20 SPT11 SPT10 SPT01 SPT00 FPT3 interrupt input port selection D7 D6 D5 D4 D3 D2 D1 D0 SPT71 SPT70 SPT61 SPT60 SPT51 SPT50 SPT41 SPT40 FPT7 interrupt input port selection Port input 00402C6 interrupt select (B) register 1 Port input 00402C7 interrupt select (B) register 2 Name Function FPT2 interrupt input port selection FPT1 interrupt input port selection FPT0 interrupt input port selection FPT6 interrupt input port selection FPT5 interrupt input port selection FPT4 interrupt input port selection Setting 1 T8 Ch.5 UF 1 SIO Ch.3 TXD Emp. 1 T8 Ch.4 UF 1 SIO Ch.3 RXD Full 1 SIO Ch.2 TXD Emp. 1 SIO Ch.3 RXD Err. 1 SIO Ch.2 RXD Full 1 SIO Ch.2 RXD Err. Init. R/W 0 FP7 0 FP6 0 0 R/W R/W 0 FP5 0 FP4 0 0 R/W R/W 0 FP3 0 R/W 0 FP2 0 R/W 0 FP1 0 R/W 0 FP0 0 R/W 11 P23 11 P22 11 P21 11 P20 10 P03 10 P02 10 P01 10 P00 01 K53 01 K52 01 K51 01 K50 00 K63 00 K62 00 K61 00 K60 0 0 0 0 0 0 0 0 R/W 11 P27 11 P26 11 P25 11 P24 10 P07 10 P06 10 P05 10 P04 01 P33 01 P32 01 P31 01 K54 00 K67 00 K66 00 K65 00 K64 0 0 0 0 0 0 0 0 R/W Low level or Falling edge 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Port input interrupt input polarity select register 00402C8 (B) D7 D6 D5 D4 D3 D2 D1 D0 SPPT7 SPPT6 SPPT5 SPPT4 SPPT3 SPPT2 SPPT1 SPPT0 FPT7 input polarity selection FPT6 input polarity selection FPT5 input polarity selection FPT4 input polarity selection FPT3 input polarity selection FPT2 input polarity selection FPT1 input polarity selection FPT0 input polarity selection 1 High level 0 or Rising edge Port input interrupt edge/level select register 00402C9 (B) D7 D6 D5 D4 D3 D2 D1 D0 SEPT7 SEPT6 SEPT5 SEPT4 SEPT3 SEPT2 SEPT1 SEPT0 FPT7 edge/level selection FPT6 edge/level selection FPT5 edge/level selection FPT4 edge/level selection FPT3 edge/level selection FPT2 edge/level selection FPT1 edge/level selection FPT0 edge/level selection 1 Edge 0 Level Remarks R/W R/W R/W R/W R/W R/W Key input 00402CA D7-4 - interrupt select (B) D3 SPPK11 register D2 SPPK10 D1 SPPK01 D0 SPPK00 reserved FPK1 interrupt input port selection - 11 10 01 00 P2[7:4] P0[7:4] K6[7:4] K6[3:0] FPK0 interrupt input port selection 11 10 01 00 P2[4:0] P0[4:0] K6[4:0] K5[4:0] - 0 0 0 0 - 0 when being read. R/W Interrupt factor 00402CB TM16 function switching register 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W A-36 D7 T8CH5S1 8-bit timer 5 underflow D6 T8CH4S1 8-bit timer 4 underflow D5 SIO3ES1 SIO Ch.3 receive error D4 SIO2ES1 SIO Ch.2 receive error D3 SIO3TS1 SIO Ch.3 transmit buffer empty D2 SIO3RS1 SIO Ch.3 receive buffer full D1 SIO2TS1 SIO Ch.2 transmit buffer empty D0 SIO2RS1 SIO Ch.2 receive buffer full EPSON 1 T8 Ch.5 UF 0 TM16 Ch.2 comp.A 1 T8 Ch.4 UF 0 TM16 Ch.2 comp.B 1 SIO Ch.3 0 TM16 Ch.3 RXD Err. comp.A 1 SIO Ch.2 0 TM16 Ch.3 RXD Err. comp.B 1 SIO Ch.3 0 TM16 Ch.4 TXD Emp. comp.A 1 SIO Ch.3 0 TM16 Ch.4 RXD Full comp.B 1 SIO Ch.2 0 TM16 Ch.5 TXD Emp. comp.A 1 SIO Ch.2 0 TM16 Ch.5 RXD Full comp.B R/W S1C33L03 PRODUCT PART 4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Name Function Key input interrupt (FPK0) input comparison register 00402CC D7-5 - (B) D4 SCPK04 D3 SCPK03 D2 SCPK02 D1 SCPK01 D0 SCPK00 reserved FPK04 input comparison FPK03 input comparison FPK02 input comparison FPK01 input comparison FPK00 input comparison Key input interrupt (FPK1) input comparison register 00402CD D7-4 - (B) D3 SCPK13 D2 SCPK12 D1 SCPK11 D0 SCPK10 reserved FPK13 input comparison FPK12 input comparison FPK11 input comparison FPK10 input comparison Key input interrupt (FPK0) input mask register 00402CE D7-5 - (B) D4 SMPK04 D3 SMPK03 D2 SMPK02 D1 SMPK01 D0 SMPK00 reserved FPK04 input mask FPK03 input mask FPK02 input mask FPK01 input mask FPK00 input mask Key input interrupt (FPK1) input mask register 00402CF D7-4 - (B) D3 SMPK13 D2 SMPK12 D1 SMPK11 D0 SMPK10 reserved FPK13 input mask FPK12 input mask FPK11 input mask FPK10 input mask P0 function select register 00402D0 (B) D7 D6 D5 D4 D3 D2 D1 D0 CFP07 CFP06 CFP05 CFP04 CFP03 CFP02 CFP01 CFP00 P0 I/O port data 00402D1 register (B) D7 D6 D5 D4 D3 D2 D1 D0 P0 I/O control register 00402D2 (B) P1 function select register 00402D4 (B) P1 I/O port data 00402D5 register (B) Setting Init. R/W - 1 High - 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W - 0 0 0 0 - 0 when being read. R/W R/W R/W R/W - 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W - 0 0 0 0 - 0 when being read. R/W R/W R/W R/W P07 P06 P05 P04 P03 P02 P01 P00 0 0 0 0 0 0 0 0 R/W Extended functions R/W (0x402DF) R/W R/W R/W R/W R/W R/W 0 Low - 1 High 0 Low - 1 Interrupt enabled Remarks 0 Interrupt disabled - 1 Interrupt enabled 0 Interrupt disabled P07 function selection P06 function selection P05 function selection P04 function selection P03 function selection P02 function selection P01 function selection P00 function selection 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 P07D P06D P05D P04D P03D P02D P01D P00D P07 I/O port data P06 I/O port data P05 I/O port data P04 I/O port data P03 I/O port data P02 I/O port data P01 I/O port data P00 I/O port data 1 High 0 Low 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W D7 D6 D5 D4 D3 D2 D1 D0 IOC07 IOC06 IOC05 IOC04 IOC03 IOC02 IOC01 IOC00 P07 I/O control P06 I/O control P05 I/O control P04 I/O control P03 I/O control P02 I/O control P01 I/O control P00 I/O control 1 Output 0 Input 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W D7 D6 - CFP16 reserved P16 function selection - 0 - 0 when being read. R/W D5 CFP15 P15 function selection 0 R/W D4 CFP14 P14 function selection - 1 EXCL5 0 P16 #DMAEND1 1 EXCL4 0 P15 #DMAEND0 1 FOSC1 0 P14 0 D3 CFP13 P13 function selection 0 P13 0 D2 CFP12 P12 function selection 0 P12 0 R/W D1 CFP11 P11 function selection 0 P11 0 R/W D0 CFP10 P10 function selection 1 EXCL3 T8UF3 1 EXCL2 T8UF2 1 EXCL1 T8UF1 1 EXCL0 T8UF0 R/W Extended functions (0x402DF) R/W 0 P10 0 R/W D7 D6 D5 D4 D3 D2 D1 D0 - P16D P15D P14D P13D P12D P11D P10D reserved P16 I/O port data P15 I/O port data P14 I/O port data P13 I/O port data P12 I/O port data P11 I/O port data P10 I/O port data - 0 0 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W R/W R/W S1C33L03 PRODUCT PART #SRDY1 #SCLK1 SOUT1 SIN1 #SRDY0 #SCLK0 SOUT0 SIN0 - 1 High EPSON 0 Low This register indicates the values of the I/O control signals of the ports when it is read. (See detailed explanation.) A-37 A-4 4 PERIPHERAL CIRCUITS Register name Address Bit P1 I/O control register 00402D6 (B) D7 D6 D5 D4 D3 D2 D1 D0 Port SIO function extension register 00402D7 D7-4 - D3 SSRDY3 reserved Serial I/F Ch.3 SRDY selection 1 #SRDY3 D2 SSCLK3 Serial I/F Ch.3 SCLK selection 1 #SCLK3 D1 SSOUT3 Serial I/F Ch.3 SOUT selection 1 SOUT3 D0 SSIN3 Serial I/F Ch.3 SIN selection 1 SIN3 00402D8 (B) D7 D6 D5 D4 D3 D2 D1 D0 CFP27 CFP26 CFP25 CFP24 CFP23 CFP22 CFP21 CFP20 P27 function selection P26 function selection P25 function selection P24 function selection P23 function selection P22 function selection P21 function selection P20 function selection 1 1 1 1 1 1 1 1 P2 I/O port data 00402D9 register (B) D7 D6 D5 D4 D3 D2 D1 D0 P27D P26D P25D P24D P23D P22D P21D P20D P27 I/O port data P26 I/O port data P25 I/O port data P24 I/O port data P23 I/O port data P22 I/O port data P21 I/O port data P20 I/O port data P2 I/O control register 00402DA (B) D7 D6 D5 D4 D3 D2 D1 D0 IOC27 IOC26 IOC25 IOC24 IOC23 IOC22 IOC21 IOC20 P27 I/O control P26 I/O control P25 I/O control P24 I/O control P23 I/O control P22 I/O control P21 I/O control P20 I/O control Port SIO function extension register 00402DB D7-4 D3 D2 D1 D0 - SSRDY2 SSCLK2 SSOUT2 SSIN2 reserved Serial I/F Ch.2 SRDY selection Serial I/F Ch.2 SCLK selection Serial I/F Ch.2 SOUT selection Serial I/F Ch.2 SIN selection P2 function select register Name - IOC16 IOC15 IOC14 IOC13 IOC12 IOC11 IOC10 P3 function 00402DC D7-6 - select register (B) D5 CFP35 D4 CFP34 D3 D2 D1 D0 CFP33 CFP32 CFP31 CFP30 Function reserved P16 I/O control P15 I/O control P14 I/O control P13 I/O control P12 I/O control P11 I/O control P10 I/O control P3 I/O control register reserved P35 I/O control P34 I/O control P33 I/O control P32 I/O control P31 I/O control P30 I/O control A-38 00402DE D7-6 - (B) D5 IOC35 D4 IOC34 D3 IOC33 D2 IOC32 D1 IOC31 D0 IOC30 - R/W R/W R/W R/W R/W R/W R/W - 0 - R/W 0 R/W 0 R/W 0 R/W P27 P26 P25 P24 P23 P22 P21 P20 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W Ext. func.(0x402DF) R/W 1 High 0 Low 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 1 Output 0 Input 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W P24/TM2 P25/TM3 P26/TM4 P27/TM5 - 0 0 0 0 - R/W R/W R/W R/W P35 P34 - 0 0 - 0 when being read. R/W R/W P33 P32 P31 P30 0 0 0 0 R/W R/W R/W Ext. func.(0x402DF) R/W - 0 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W R/W - 0 0 0 0 0 0 - R/W R/W R/W R/W R/W R/W 0 Input - 0 P32/ #DMAACK0 0 P15/EXCL4/ #DMAEND0 0 P16/EXCL5/ #DMAEND1 0 P33/ #DMAACK1 TM5 TM4 TM3 TM2 TM1 TM0 #DWE #DRD 0 0 0 0 0 0 0 0 - 1 1 1 1 #SRDY2 #SCLK2 SOUT2 SIN2 0 0 0 0 - 1 #BUSACK 0 1 #BUSREQ 0 #CE6 1 #DMAACK1 0 1 #DMAACK0 0 1 #BUSGET 0 1 #WAIT 0 #CE4/#CE5 - 1 High 0 Low - 1 Output EPSON Remarks - 0 0 0 0 0 0 0 1 Output P33 function selection P32 function selection P31 function selection P30 function selection reserved P35 I/O port data P34 I/O port data P33 I/O port data P32 I/O port data P31 I/O port data P30 I/O port data Init. R/W - reserved P35 function selection P34 function selection P3 I/O port data 00402DD D7-6 - register (B) D5 P35D D4 P34D D3 P33D D2 P32D D1 P31D D0 P30D Setting 0 Input 0 when being read. This register indicates the values of the I/O control signals of the ports when it is read. (See detailed explanation.) This register indicates the values of the I/O control signals of the ports when it is read. (See detailed explanation.) 0 when being read. This register indicates the values of the I/O control signals of the ports when it is read. (See detailed explanation.) S1C33L03 PRODUCT PART 4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Port function extension register D7 D6 D5 D4 D3 D2 D1 CFEX7 CFEX6 CFEX5 CFEX4 CFEX3 CFEX2 CFEX1 P07 port extended function P06 port extended function P05 port extended function P04 port extended function P31 port extended function P21 port extended function P10, P11, P13 port extended function D0 CFEX0 P12, P14 port extended function DF DE DD DC - A18SZ A18DF1 A18DF0 DB DA D9 D8 - A18WT2 A18WT1 A18WT0 D7 D6 D5 D4 - A16SZ A16DF1 A16DF0 D3 D2 D1 D0 - A16WT2 A16WT1 A16WT0 DF-9 D8 D7 D6 D5 D4 D3 D2 D1 D0 00402DF (B) Areas 18-15 0048120 set-up register (HW) Areas 14-13 0048122 set-up register (HW) S1C33L03 PRODUCT PART Name Function Setting #DMAEND3 #DMAACK3 #DMAEND2 #DMAACK2 #GARD #GAAS DST0 DST1 DPC0 1 DST2 DCLK 0 0 0 0 0 0 0 P07, etc. P06, etc. P05, etc. P04, etc. P31, etc. P21, etc. P10, etc. P11, etc. P13, etc. 0 P12, etc. P14, etc. Remarks 0 0 0 0 0 0 1 R/W R/W R/W R/W R/W R/W R/W 1 R/W reserved - Areas 18-17 device size selection 1 8 bits 0 16 bits Areas 18-17 A18DF[1:0] Number of cycles 1 1 3.5 output disable delay time 1 0 2.5 0 1 1.5 0 0 0.5 - reserved A18WT[2:0] Wait cycles Areas 18-17 wait control 1 1 1 7 1 1 0 6 1 0 1 5 1 0 0 4 0 1 1 3 0 1 0 2 0 0 1 1 0 0 0 0 - reserved Areas 16-15 device size selection 1 8 bits 0 16 bits Areas 16-15 A16DF[1:0] Number of cycles 1 1 3.5 output disable delay time 1 0 2.5 0 1 1.5 0 0 0.5 - reserved A16WT[2:0] Wait cycles Areas 16-15 wait control 1 1 1 7 1 1 0 6 1 0 1 5 1 0 0 4 0 1 1 3 0 1 0 2 0 0 1 1 0 0 0 0 - 0 1 1 - 0 when being read. R/W R/W - 1 1 1 - 0 when being read. R/W - 0 1 1 - 0 when being read. R/W R/W - 1 1 1 - 0 when being read. R/W - A14DRA A13DRA A14SZ A14DF1 A14DF0 reserved Area 14 DRAM selection Area 13 DRAM selection Areas 14-13 device size selection Areas 14-13 output disable delay time - 0 0 0 1 1 - 0 when being read. R/W R/W R/W R/W - A14WT2 A14WT1 A14WT0 reserved Areas 14-13 wait control - 1 1 1 - 0 when being read. R/W EPSON 1 1 1 1 1 1 1 Init. R/W - 1 Used 0 Not used 1 Used 0 Not used 1 8 bits 0 16 bits A14DF[1:0] Number of cycles 1 1 3.5 1 0 2.5 0 1 1.5 0 0 0.5 - A14WT[2:0] Wait cycles 1 1 1 7 1 1 0 6 1 0 1 5 1 0 0 4 0 1 1 3 0 1 0 2 0 0 1 1 0 0 0 0 A-4 A-39 4 PERIPHERAL CIRCUITS Register name Address Bit Areas 12-11 0048124 set-up register (HW) DF-7 D6 D5 D4 - A12SZ A12DF1 A12DF0 D3 D2 D1 D0 - A12WT2 A12WT1 A12WT0 DF DE DD DC Areas 10-9 0048126 set-up register (HW) Areas 8-7 0048128 set-up register (HW) A-40 Name Function Setting Init. R/W Remarks reserved - Areas 12-11 device size selection 1 8 bits 0 16 bits Areas 12-11 A18DF[1:0] Number of cycles 1 1 3.5 output disable delay time 1 0 2.5 0 1 1.5 0 0 0.5 - reserved A18WT[2:0] Wait cycles Areas 12-11 wait control 1 1 1 7 1 1 0 6 1 0 1 5 1 0 0 4 0 1 1 3 0 1 0 2 0 0 1 1 0 0 0 0 - 0 1 1 - 0 when being read. R/W R/W - 1 1 1 - 0 when being read. R/W - A10IR2 A10IR1 A10IR0 reserved Area 10 internal ROM size selection - 1 1 1 - 0 when being read. R/W DB DA D9 - A10BW1 A10BW0 reserved Areas 10-9 burst ROM burst read cycle wait control - 0 0 - 0 when being read. R/W D8 D7 D6 D5 D4 A10DRA A9DRA A10SZ A10DF1 A10DF0 Area 10 burst ROM selection Area 9 burst ROM selection Areas 10-9 device size selection Areas 10-9 output disable delay time 0 0 0 1 1 R/W R/W R/W R/W D3 D2 D1 D0 - A10WT2 A10WT1 A10WT0 reserved Areas 10-9 wait control - A10BW[1:0] Wait cycles 1 1 3 1 0 2 0 1 1 0 0 0 1 Used 0 Not used 1 Used 0 Not used 1 8 bits 0 16 bits A10DF[1:0] Number of cycles 1 1 3.5 1 0 2.5 0 1 1.5 0 0 0.5 - A10WT[2:0] Wait cycles 1 1 1 7 1 1 0 6 1 0 1 5 1 0 0 4 0 1 1 3 0 1 0 2 0 0 1 1 0 0 0 0 - 1 1 1 - 0 when being read. R/W DF-9 D8 D7 D6 D5 D4 - A8DRA A7DRA A8SZ A8DF1 A8DF0 reserved Area 8 DRAM selection Area 7 DRAM selection Areas 8-7 device size selection Areas 8-7 output disable delay time - - 0 0 0 1 1 - 0 when being read. R/W R/W R/W R/W D3 D2 D1 D0 - A8WT2 A8WT1 A8WT0 reserved Areas 8-7 wait control - 1 1 1 - 0 when being read. R/W EPSON - A10IR[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 1 Used 1 Used 1 8 bits A8DF[1:0] 1 1 1 0 0 1 0 0 ROM size 2MB 1MB 512KB 256KB 128KB 64KB 32KB 16KB 0 Not used 0 Not used 0 16 bits Number of cycles 3.5 2.5 1.5 0.5 - A8WT[2:0] Wait cycles 1 1 1 7 1 1 0 6 1 0 1 5 1 0 0 4 0 1 1 3 0 1 0 2 0 0 1 1 0 0 0 0 S1C33L03 PRODUCT PART 4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Name Areas 6-4 004812A DF-E - set-up register (HW) DD A6DF1 DC A6DF0 Function reserved Area 6 output disable delay time Setting - Number of cycles 3.5 2.5 1.5 0.5 - A6WT[2:0] Wait cycles 1 1 1 7 1 1 0 6 1 0 1 5 1 0 0 4 0 1 1 3 0 1 0 2 0 0 1 1 0 0 0 0 - 1 8 bits 0 16 bits A5DF[1:0] Number of cycles 1 1 3.5 1 0 2.5 0 1 1.5 0 0 0.5 A6DF[1:0] 1 1 1 0 0 1 0 0 Init. R/W Remarks - 1 1 - 0 when being read. R/W - 1 1 1 - 0 when being read. R/W - 0 1 1 - 0 when being read. R/W R/W - 1 1 1 - 0 when being read. R/W A-4 DB DA D9 D8 - A6WT2 A6WT1 A6WT0 reserved Area 6 wait control D7 D6 D5 D4 - A5SZ A5DF1 A5DF0 reserved Areas 5-4 device size selection Areas 5-4 output disable delay time D3 D2 D1 D0 - A5WT2 A5WT1 A5WT0 reserved Areas 5-4 wait control TTBR write 004812D protect register (B) D7 D6 D5 D4 D3 D2 D1 D0 TBRP7 TBRP6 TBRP5 TBRP4 TBRP3 TBRP2 TBRP1 TBRP0 TTBR register write protect Writing 01011001 (0x59) removes the TTBR (0x48134) write protection. Writing other data sets the write protection. 0 0 0 0 0 0 0 0 Bus control register DF DE DD DC DB DA RBCLK - RBST8 REDO RCA1 RCA0 BCLK output control reserved Burst ROM burst mode selection DRAM page mode selection Column address size selection 1 Fixed at H 0 0 0 0 0 0 R/W - Writing 1 not allowed. R/W R/W R/W D9 D8 D7 D6 D5 RPC2 RPC1 RPC0 RRA1 RRA0 0 0 0 0 0 R/W R/W R/W R/W D4 D3 D2 D1 D0 - SBUSST SEMAS SEPD SWAITE 0 0 0 0 0 - Writing 1 not allowed. R/W R/W R/W R/W 004812E (HW) S1C33L03 PRODUCT PART A5WT[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 Wait cycles 7 6 5 4 3 2 1 0 0 Enabled - 1 8-successive 0 4-successive 1 EDO 0 Fast page RCA[1:0] Size 1 1 11 1 0 10 0 1 9 0 0 8 Refresh enable 1 Enabled 0 Disabled 1 Self-refresh 0 CBR-refresh Refresh method selection 1 2.0 0 1.0 Refresh RPC delay setup RRA[1:0] Number of cycles Refresh RAS pulse width 1 1 5 selection 1 0 4 0 1 3 0 0 2 - reserved External interface method selection 1 #BSL 0 A0 External bus master setup 1 Existing 0 Nonexistent 1 Enabled 0 Disabled External power-down control 1 Enabled 0 Disabled #WAIT enable EPSON W Undefined in read. A-41 4 PERIPHERAL CIRCUITS Register name Address Bit Name Function DRAM timing 0048130 DF-C - reserved set-up register (HW) DB A3EEN Area 3 emulation DA CEFUNC1 #CE pin function selection D9 CEFUNC0 Setting Init. R/W Remarks - 1 Internal ROM 0 Emulation CEFUNC[1:0] #CE output 1 x #CE7/8..#CE17/18 #CE6..#CE17 0 1 #CE4..#CE10 0 0 1 Successive 0 Normal RPRC[1:0] Number of cycles 1 1 4 1 0 3 0 1 2 0 0 1 - CASC[1:0] Number of cycles 1 1 4 1 0 3 0 1 2 0 0 1 - RASC[1:0] Number of cycles 1 1 4 1 0 3 0 1 2 0 0 1 - 1 0 0 - 0 when being read. R/W R/W 0 0 0 R/W R/W - 0 0 - 0 when being read. R/W - 0 0 - 0 when being read. R/W D8 D7 D6 CRAS RPRC1 RPRC0 Successive RAS mode setup DRAM RAS precharge cycles selection D5 D4 D3 - CASC1 CASC0 reserved DRAM CAS cycles selection D2 D1 D0 - RASC1 RASC0 reserved DRAM RAS cycles selection Access control 0048132 register (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A18IO A16IO A14IO A12IO - A8IO A6IO A5IO A18EC A16EC A14EC A12EC A10EC A8EC A6EC A5EC Area 18, 17 internal/external access 1 Internal 0 External Area 16, 15 internal/external access access access Area 14, 13 internal/external access Area 12, 11 internal/external access reserved - 0 External Area 8, 7 internal/external access 1 Internal Area 6 internal/external access access access Area 5, 4 internal/external access Area 18, 17 endian control 1 Big endian 0 Little endian Area 16, 15 endian control Area 14, 13 endian control Area 12, 11 endian control Area 10, 9 endian control Area 8, 7 endian control Area 6 endian control Area 5, 4 endian control 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W - 0 when being read. R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TTBR loworder register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TTBR15 TTBR14 TTBR13 TTBR12 TTBR11 TTBR10 TTBR09 TTBR08 TTBR07 TTBR06 TTBR05 TTBR04 TTBR03 TTBR02 TTBR01 TTBR00 Trap table base address [15:10] R/W Trap table base address [9:0] Fixed at 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R 0 when being read. Writing 1 not allowed. DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TTBR33 TTBR32 TTBR31 TTBR30 TTBR2B TTBR2A TTBR29 TTBR28 TTBR27 TTBR26 TTBR25 TTBR24 TTBR23 TTBR22 TTBR21 TTBR20 Trap table base address [31:28] Fixed at 0 R 0 when being read. Writing 1 not allowed. Trap table base address [27:16] 0x0C0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 TTBR highorder register A-42 0048134 (HW) 0048136 (HW) EPSON R/W S1C33L03 PRODUCT PART 4 PERIPHERAL CIRCUITS A-1 Register name Address Bit G/A read signal 0048138 control register (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BCLK select register Name A18AS A16AS A14AS A12AS - A8AS A6AS A5AS A18RD A16RD A14RD A12RD - A8RD A6RD A5RD 004813A D7-4 - (B) D3 A1X1MD D2 - D1 BCLKSEL1 D0 BCLKSEL0 S1C33L03 PRODUCT PART Function Area 18, 17 address strobe signal Area 16, 15 address strobe signal Area 14, 13 address strobe signal Area 12, 11 address strobe signal reserved Area 8, 7 address strobe signal Area 6 address strobe signal Area 5, 4 address strobe signal Area 18, 17 read signal Area 16, 15 read signal Area 14, 13 read signal Area 12, 11 read signal reserved Area 8, 7 read signal Area 6 read signal Area 5, 4 read signal reserved Area 1 access-speed reserved BCLK output clock selection EPSON Setting 1 Enabled 0 Disabled - 1 Enabled 0 Disabled 1 Enabled 0 Disabled - 1 Enabled 0 Disabled - 1 2 cycles 0 4 cycles - BCLKSEL[1:0] 1 1 1 0 0 1 0 0 BCLK PLL_CLK OSC3_CLK BCU_CLK CPU_CLK Init. R/W Remarks 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W - 0 when being read. R/W R/W R/W R/W R/W R/W R/W - 0 when being read. R/W R/W R/W 0 0 0 0 0 - 0 when being read. R/W x2 speed mode only - 0 when being read. R/W A-43 A-4 4 PERIPHERAL CIRCUITS Register name Address Bit Name Function Setting 16-bit timer 0 comparison register A 0048180 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR0A15 CR0A14 CR0A13 CR0A12 CR0A11 CR0A10 CR0A9 CR0A8 CR0A7 CR0A6 CR0A5 CR0A4 CR0A3 CR0A2 CR0A1 CR0A0 16-bit timer 0 comparison data A CR0A15 = MSB CR0A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 0 comparison register B 0048182 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR0B15 CR0B14 CR0B13 CR0B12 CR0B11 CR0B10 CR0B9 CR0B8 CR0B7 CR0B6 CR0B5 CR0B4 CR0B3 CR0B2 CR0B1 CR0B0 16-bit timer 0 comparison data B CR0B15 = MSB CR0B0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 0 counter data register 0048184 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC015 TC014 TC013 TC012 TC011 TC010 TC09 TC08 TC07 TC06 TC05 TC04 TC03 TC02 TC01 TC00 16-bit timer 0 counter data TC015 = MSB TC00 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R 16-bit timer 0 0048186 control register (B) D7 D6 D5 D4 D3 D2 D1 D0 - SELFM0 SELCRB0 OUTINV0 CKSL0 PTM0 PRESET0 PRUN0 reserved 16-bit timer 0 fine mode selection 16-bit timer 0 comparison buffer 16-bit timer 0 output inversion 16-bit timer 0 input clock selection 16-bit timer 0 clock output control 16-bit timer 0 reset 16-bit timer 0 Run/Stop control A-44 EPSON 1 1 1 1 1 1 1 - Fine mode 0 Enabled 0 Invert 0 External clock 0 On 0 Reset 0 Run 0 Init. R/W Normal Disabled Normal Internal clock Off Invalid Stop 0 0 0 0 0 0 0 0 Remarks - 0 when being read. R/W R/W R/W R/W R/W W 0 when being read. R/W S1C33L03 PRODUCT PART 4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Name Function Setting 16-bit timer 1 comparison register A 0048188 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 1 comparison register B 004818A (HW) 16-bit timer 1 counter data register CR1A15 CR1A14 CR1A13 CR1A12 CR1A11 CR1A10 CR1A9 CR1A8 CR1A7 CR1A6 CR1A5 CR1A4 CR1A3 CR1A2 CR1A1 CR1A0 16-bit timer 1 comparison data A CR1A15 = MSB CR1A0 = LSB 0 to 65535 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR1B15 CR1B14 CR1B13 CR1B12 CR1B11 CR1B10 CR1B9 CR1B8 CR1B7 CR1B6 CR1B5 CR1B4 CR1B3 CR1B2 CR1B1 CR1B0 16-bit timer 1 comparison data B CR1B15 = MSB CR1B0 = LSB 004818C (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC115 TC114 TC113 TC112 TC111 TC110 TC19 TC18 TC17 TC16 TC15 TC14 TC13 TC12 TC11 TC10 16-bit timer 1 counter data TC115 = MSB TC10 = LSB 16-bit timer 1 004818E control register (B) D7 D6 D5 D4 D3 D2 D1 D0 - SELFM1 SELCRB1 OUTINV1 CKSL1 PTM1 PRESET1 PRUN1 reserved 16-bit timer 1 fine mode selection 16-bit timer 1 comparison buffer 16-bit timer 1 output inversion 16-bit timer 1 input clock selection 16-bit timer 1 clock output control 16-bit timer 1 reset 16-bit timer 1 Run/Stop control S1C33L03 PRODUCT PART EPSON 1 1 1 1 1 1 1 Init. R/W X X X X X X X X X X X X X X X X R/W 0 to 65535 X X X X X X X X X X X X X X X X R/W 0 to 65535 X X X X X X X X X X X X X X X X R - Fine mode 0 Enabled 0 Invert 0 External clock 0 On 0 Reset 0 Run 0 Normal Disabled Normal Internal clock Off Invalid Stop 0 0 0 0 0 0 0 0 Remarks A-4 - 0 when being read. R/W R/W R/W R/W R/W W 0 when being read. R/W A-45 4 PERIPHERAL CIRCUITS Register name Address Bit Name Function Setting 16-bit timer 2 comparison register A 0048190 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR2A15 CR2A14 CR2A13 CR2A12 CR2A11 CR2A10 CR2A9 CR2A8 CR2A7 CR2A6 CR2A5 CR2A4 CR2A3 CR2A2 CR2A1 CR2A0 16-bit timer 2 comparison data A CR2A15 = MSB CR2A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 2 comparison register B 0048192 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR2B15 CR2B14 CR2B13 CR2B12 CR2B11 CR2B10 CR2B9 CR2B8 CR2B7 CR2B6 CR2B5 CR2B4 CR2B3 CR2B2 CR2B1 CR2B0 16-bit timer 2 comparison data B CR2B15 = MSB CR2B0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 2 counter data register 0048194 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC215 TC214 TC213 TC212 TC211 TC210 TC29 TC28 TC27 TC26 TC25 TC24 TC23 TC22 TC21 TC20 16-bit timer 2 counter data TC215 = MSB TC20 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R 16-bit timer 2 0048196 control register (B) D7 D6 D5 D4 D3 D2 D1 D0 - SELFM2 SELCRB2 OUTINV2 CKSL2 PTM2 PRESET2 PRUN2 reserved 16-bit timer 2 fine mode selection 16-bit timer 2 comparison buffer 16-bit timer 2 output inversion 16-bit timer 2 input clock selection 16-bit timer 2 clock output control 16-bit timer 2 reset 16-bit timer 2 Run/Stop control A-46 EPSON 1 1 1 1 1 1 1 - Fine mode 0 Enabled 0 Invert 0 External clock 0 On 0 Reset 0 Run 0 Init. R/W Normal Disabled Normal Internal clock Off Invalid Stop 0 0 0 0 0 0 0 0 Remarks - 0 when being read. R/W R/W R/W R/W R/W W 0 when being read. R/W S1C33L03 PRODUCT PART 4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Name Function Setting 16-bit timer 3 comparison register A 0048198 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 3 comparison register B 004819A (HW) 16-bit timer 3 counter data register CR3A15 CR3A14 CR3A13 CR3A12 CR3A11 CR3A10 CR3A9 CR3A8 CR3A7 CR3A6 CR3A5 CR3A4 CR3A3 CR3A2 CR3A1 CR3A0 16-bit timer 3 comparison data A CR3A15 = MSB CR3A0 = LSB 0 to 65535 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR3B15 CR3B14 CR3B13 CR3B12 CR3B11 CR3B10 CR3B9 CR3B8 CR3B7 CR3B6 CR3B5 CR3B4 CR3B3 CR3B2 CR3B1 CR3B0 16-bit timer 3 comparison data B CR3B15 = MSB CR3B0 = LSB 004819C (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC315 TC314 TC313 TC312 TC311 TC310 TC39 TC38 TC37 TC36 TC35 TC34 TC33 TC32 TC31 TC30 16-bit timer 3 counter data TC315 = MSB TC30 = LSB 16-bit timer 3 004819E control register (B) D7 D6 D5 D4 D3 D2 D1 D0 - SELFM3 SELCRB3 OUTINV3 CKSL3 PTM3 PRESET3 PRUN3 reserved 16-bit timer 3 fine mode selection 16-bit timer 3 comparison buffer 16-bit timer 3 output inversion 16-bit timer 3 input clock selection 16-bit timer 3 clock output control 16-bit timer 3 reset 16-bit timer 3 Run/Stop control S1C33L03 PRODUCT PART EPSON 1 1 1 1 1 1 1 Init. R/W X X X X X X X X X X X X X X X X R/W 0 to 65535 X X X X X X X X X X X X X X X X R/W 0 to 65535 X X X X X X X X X X X X X X X X R - Fine mode 0 Enabled 0 Invert 0 External clock 0 On 0 Reset 0 Run 0 Normal Disabled Normal Internal clock Off Invalid Stop 0 0 0 0 0 0 0 0 Remarks A-4 - 0 when being read. R/W R/W R/W R/W R/W W 0 when being read. R/W A-47 4 PERIPHERAL CIRCUITS Register name Address Bit Name Function Setting 16-bit timer 4 comparison register A 00481A0 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR4A15 CR4A14 CR4A13 CR4A12 CR4A11 CR4A10 CR4A9 CR4A8 CR4A7 CR4A6 CR4A5 CR4A4 CR4A3 CR4A2 CR4A1 CR4A0 16-bit timer 4 comparison data A CR4A15 = MSB CR4A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 4 comparison register B 00481A2 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR4B15 CR4B14 CR4B13 CR4B12 CR4B11 CR4B10 CR4B9 CR4B8 CR4B7 CR4B6 CR4B5 CR4B4 CR4B3 CR4B2 CR4B1 CR4B0 16-bit timer 4 comparison data B CR4B15 = MSB CR4B0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 4 counter data register 00481A4 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC415 TC414 TC413 TC412 TC411 TC410 TC49 TC48 TC47 TC46 TC45 TC44 TC43 TC42 TC41 TC40 16-bit timer 4 counter data TC415 = MSB TC40 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R 16-bit timer 4 00481A6 control register (B) D7 D6 D5 D4 D3 D2 D1 D0 - SELFM4 SELCRB4 OUTINV4 CKSL4 PTM4 PRESET4 PRUN4 reserved 16-bit timer 4 fine mode selection 16-bit timer 4 comparison buffer 16-bit timer 4 output inversion 16-bit timer 4 input clock selection 16-bit timer 4 clock output control 16-bit timer 4 reset 16-bit timer 4 Run/Stop control A-48 EPSON 1 1 1 1 1 1 1 - Fine mode 0 Enabled 0 Invert 0 External clock 0 On 0 Reset 0 Run 0 Init. R/W Normal Disabled Normal Internal clock Off Invalid Stop 0 0 0 0 0 0 0 0 Remarks - 0 when being read. R/W R/W R/W R/W R/W W 0 when being read. R/W S1C33L03 PRODUCT PART 4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Name Function Setting 16-bit timer 5 comparison register A 00481A8 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 5 comparison register B 00481AA (HW) 16-bit timer 5 counter data register CR5A15 CR5A14 CR5A13 CR5A12 CR5A11 CR5A10 CR5A9 CR5A8 CR5A7 CR5A6 CR5A5 CR5A4 CR5A3 CR5A2 CR5A1 CR5A0 16-bit timer 5 comparison data A CR5A15 = MSB CR5A0 = LSB 0 to 65535 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR5B15 CR5B14 CR5B13 CR5B12 CR5B11 CR5B10 CR5B9 CR5B8 CR5B7 CR5B6 CR5B5 CR5B4 CR5B3 CR5B2 CR5B1 CR5B0 16-bit timer 5 comparison data B CR5B15 = MSB CR5B0 = LSB 00481AC (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC515 TC514 TC513 TC512 TC511 TC510 TC59 TC58 TC57 TC56 TC55 TC54 TC53 TC52 TC51 TC50 16-bit timer 5 counter data TC515 = MSB TC50 = LSB 16-bit timer 5 00481AE control register (B) D7 D6 D5 D4 D3 D2 D1 D0 - SELFM5 SELCRB5 OUTINV5 CKSL5 PTM5 PRESET5 PRUN5 reserved 16-bit timer 5 fine mode selection 16-bit timer 5 comparison buffer 16-bit timer 5 output inversion 16-bit timer 5 input clock selection 16-bit timer 5 clock output control 16-bit timer 5 reset 16-bit timer 5 Run/Stop control S1C33L03 PRODUCT PART EPSON 1 1 1 1 1 1 1 Init. R/W X X X X X X X X X X X X X X X X R/W 0 to 65535 X X X X X X X X X X X X X X X X R/W 0 to 65535 X X X X X X X X X X X X X X X X R - Fine mode 0 Enabled 0 Invert 0 External clock 0 On 0 Reset 0 Run 0 Normal Disabled Normal Internal clock Off Invalid Stop 0 0 0 0 0 0 0 0 Remarks A-4 - 0 when being read. R/W R/W R/W R/W R/W W 0 when being read. R/W A-49 4 PERIPHERAL CIRCUITS Register name Address Bit IDMA base address loworder register 0048200 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 IDMA base address high-order register 0048202 DF-C - (HW) DB DBASEH11 DA DBASEH10 D9 DBASEH9 D8 DBASEH8 D7 DBASEH7 D6 DBASEH6 D5 DBASEH5 D4 DBASEH4 D3 DBASEH3 D2 DBASEH2 D1 DBASEH1 D0 DBASEH0 reserved IDMA base address high-order 12 bits (Initial value: 0x0C003A0) IDMA start register 0048204 (B) D7 DSTART D6-0 DCHN IDMA start IDMA channel number 1 IDMA start 0 Stop 0 to 127 IDMA enable register 0048205 (B) D7-1 - D0 IDMAEN reserved IDMA enable 1 Enabled A-50 Name Function Setting DBASEL15 IDMA base address DBASEL14 low-order 16 bits DBASEL13 (Initial value: 0x0C003A0) DBASEL12 DBASEL11 DBASEL10 DBASEL9 DBASEL8 DBASEL7 DBASEL6 DBASEL5 DBASEL4 DBASEL3 DBASEL2 DBASEL1 DBASEL0 - - EPSON 0 Disabled Init. R/W Remarks 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 R/W - 0 0 0 0 1 1 0 0 0 0 0 0 - Undefined in read. R/W 0 0 R/W R/W - 0 - R/W S1C33L03 PRODUCT PART 4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Name High-speed DMA Ch.0 transfer counter register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC0_L7 TC0_L6 TC0_L5 TC0_L4 TC0_L3 TC0_L2 TC0_L1 TC0_L0 BLKLEN07 BLKLEN06 BLKLEN05 BLKLEN04 BLKLEN03 BLKLEN02 BLKLEN01 BLKLEN00 Ch.0 transfer counter[7:0] (block transfer mode) DF DE DUALM0 D0DIR DD-8 D7 D6 D5 D4 D3 D2 D1 D0 - TC0_H7 TC0_H6 TC0_H5 TC0_H4 TC0_H3 TC0_H2 TC0_H1 TC0_H0 Ch.0 address mode selection D) Invalid S) Ch.0 transfer direction control reserved Ch.0 transfer counter[15:8] (block transfer mode) 0048220 (HW) High-speed 0048222 DMA Ch.0 (HW) control register Note: D) Dual address mode S) Single address mode High-speed 0048224 DMA Ch.0 (HW) low-order source address set-up register Note: D) Dual address mode S) Single address mode High-speed 0048226 DMA Ch.0 (HW) high-order source address set-up register Note: D) Dual address mode S) Single address mode Function Ch.0 transfer counter[15:8] (single/successive transfer mode) Ch.0 block length (block transfer mode) Ch.0 transfer counter[7:0] (single/successive transfer mode) 1 Dual addr 0 Single addr - 1 Memory WR 0 Memory RD - Ch.0 transfer counter[23:16] (single/successive transfer mode) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S0ADRL15 D) Ch.0 source address[15:0] S0ADRL14 S) Ch.0 memory address[15:0] S0ADRL13 S0ADRL12 S0ADRL11 S0ADRL10 S0ADRL9 S0ADRL8 S0ADRL7 S0ADRL6 S0ADRL5 S0ADRL4 S0ADRL3 S0ADRL2 S0ADRL1 S0ADRL0 DF DE DD DC - DATSIZE0 S0IN1 S0IN0 DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S0ADRH11 D) Ch.0 source address[27:16] S0ADRH10 S) Ch.0 memory address[27:16] S0ADRH9 S0ADRH8 S0ADRH7 S0ADRH6 S0ADRH5 S0ADRH4 S0ADRH3 S0ADRH2 S0ADRH1 S0ADRH0 S1C33L03 PRODUCT PART Setting reserved Ch.0 transfer data size D) Ch.0 source address control S) Ch.0 memory address control EPSON - 1 Half word S0IN[1:0] 1 1 1 0 0 1 0 0 0 Byte Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed Init. R/W Remarks X X X X X X X X X X X X X X X X R/W 0 - 0 - X X X X X X X X R/W - R/W - Undefined in read. R/W X X X X X X X X X X X X X X X X R/W - 0 0 0 - R/W R/W X X X X X X X X X X X X R/W A-4 R/W A-51 4 PERIPHERAL CIRCUITS Register name Address Bit High-speed 0048228 DMA Ch.0 (HW) low-order destination address set-up register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D0ADRL15 D) Ch.0 destination address[15:0] D0ADRL14 S) Invalid D0ADRL13 D0ADRL12 D0ADRL11 D0ADRL10 D0ADRL9 D0ADRL8 D0ADRL7 D0ADRL6 D0ADRL5 D0ADRL4 D0ADRL3 D0ADRL2 D0ADRL1 D0ADRL0 DF DE D0MOD1 D0MOD0 Ch.0 transfer mode DD DC D0IN1 D0IN0 D) Ch.0 destination address control S) Invalid DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D0ADRH11 D) Ch.0 destination D0ADRH10 address[27:16] D0ADRH9 S) Invalid D0ADRH8 D0ADRH7 D0ADRH6 D0ADRH5 D0ADRH4 D0ADRH3 D0ADRH2 D0ADRH1 D0ADRH0 Note: D) Dual address mode S) Single address mode High-speed 004822A DMA Ch.0 (HW) high-order destination address set-up register Note: D) Dual address mode S) Single address mode Name Function High-speed 004822C DF-1 - DMA Ch.0 (HW) D0 HS0_EN enable register reserved High-speed DMA Ch.0 trigger flag register reserved A-52 004822E DF-1 - (HW) D0 HS0_TF Setting D0MOD[1:0] 1 1 1 0 0 1 0 0 D0IN[1:0] 1 1 1 0 0 1 0 0 Mode Invalid Block Successive Single Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed - Ch.0 enable 1 Enable 0 Disable - Ch.0 trigger flag clear (writing) Ch.0 trigger flag status (reading) EPSON 1 Clear 1 Set 0 No operation 0 Cleared Init. R/W X X X X X X X X X X X X X X X X R/W 0 0 R/W 0 0 R/W X X X X X X X X X X X X R/W - - 0 R/W - - 0 R/W Remarks Undefined in read. Undefined in read. S1C33L03 PRODUCT PART 4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Name High-speed DMA Ch.1 transfer counter register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC1_L7 TC1_L6 TC1_L5 TC1_L4 TC1_L3 TC1_L2 TC1_L1 TC1_L0 BLKLEN17 BLKLEN16 BLKLEN15 BLKLEN14 BLKLEN13 BLKLEN12 BLKLEN11 BLKLEN10 Ch.1 transfer counter[7:0] (block transfer mode) DF DE DUALM1 D1DIR DD-8 D7 D6 D5 D4 D3 D2 D1 D0 - TC1_H7 TC1_H6 TC1_H5 TC1_H4 TC1_H3 TC1_H2 TC1_H1 TC1_H0 Ch.1 address mode selection D) Invalid S) Ch.1 transfer direction control reserved Ch.1 transfer counter[15:8] (block transfer mode) 0048230 (HW) High-speed 0048232 DMA Ch.1 (HW) control register Note: D) Dual address mode S) Single address mode High-speed 0048234 DMA Ch.1 (HW) low-order source address set-up register Note: D) Dual address mode S) Single address mode High-speed 0048236 DMA Ch.1 (HW) high-order source address set-up register Note: D) Dual address mode S) Single address mode Function Ch.1 transfer counter[15:8] (single/successive transfer mode) Ch.1 block length (block transfer mode) Ch.1 transfer counter[7:0] (single/successive transfer mode) 1 Dual addr 0 Single addr - 1 Memory WR 0 Memory RD - Ch.1 transfer counter[23:16] (single/successive transfer mode) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1ADRL15 D) Ch.1 source address[15:0] S1ADRL14 S) Ch.1 memory address[15:0] S1ADRL13 S1ADRL12 S1ADRL11 S1ADRL10 S1ADRL9 S1ADRL8 S1ADRL7 S1ADRL6 S1ADRL5 S1ADRL4 S1ADRL3 S1ADRL2 S1ADRL1 S1ADRL0 DF DE DD DC - DATSIZE1 S1IN1 S1IN0 DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1ADRH11 D) Ch.1 source address[27:16] S1ADRH10 S) Ch.1 memory address[27:16] S1ADRH9 S1ADRH8 S1ADRH7 S1ADRH6 S1ADRH5 S1ADRH4 S1ADRH3 S1ADRH2 S1ADRH1 S1ADRH0 S1C33L03 PRODUCT PART Setting reserved Ch.1 transfer data size D) Ch.1 source address control S) Ch.1 memory address control EPSON - 1 Half word S1IN[1:0] 1 1 1 0 0 1 0 0 0 Byte Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed Init. R/W Remarks X X X X X X X X X X X X X X X X R/W 0 - 0 - X X X X X X X X R/W - R/W - Undefined in read. R/W X X X X X X X X X X X X X X X X R/W - 0 0 0 - R/W R/W X X X X X X X X X X X X R/W A-4 R/W A-53 4 PERIPHERAL CIRCUITS Register name Address Bit High-speed 0048238 DMA Ch.1 (HW) low-order destination address set-up register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D1ADRL15 D) Ch.1 destination address[15:0] D1ADRL14 S) Invalid D1ADRL13 D1ADRL12 D1ADRL11 D1ADRL10 D1ADRL9 D1ADRL8 D1ADRL7 D1ADRL6 D1ADRL5 D1ADRL4 D1ADRL3 D1ADRL2 D1ADRL1 D1ADRL0 DF DE D1MOD1 D1MOD0 Ch.1 transfer mode DD DC D1IN1 D1IN0 D) Ch.1 destination address control S) Invalid DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D1ADRH11 D) Ch.1 destination D1ADRH10 address[27:16] D1ADRH9 S) Invalid D1ADRH8 D1ADRH7 D1ADRH6 D1ADRH5 D1ADRH4 D1ADRH3 D1ADRH2 D1ADRH1 D1ADRH0 Note: D) Dual address mode S) Single address mode High-speed 004823A DMA Ch.1 (HW) high-order destination address set-up register Note: D) Dual address mode S) Single address mode Name Function High-speed 004823C DF-1 - DMA Ch.1 (HW) D0 HS1_EN enable register reserved High-speed DMA Ch.1 trigger flag register reserved A-54 004823E DF-1 - (HW) D0 HS1_TF Setting D1MOD[1:0] 1 1 1 0 0 1 0 0 D1IN[1:0] 1 1 1 0 0 1 0 0 Mode Invalid Block Successive Single Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed - Ch.1 enable 1 Enable 0 Disable - Ch.1 trigger flag clear (writing) Ch.1 trigger flag status (reading) EPSON 1 Clear 1 Set 0 No operation 0 Cleared Init. R/W X X X X X X X X X X X X X X X X R/W 0 0 R/W 0 0 R/W X X X X X X X X X X X X R/W - - 0 R/W - - 0 R/W Remarks Undefined in read. Undefined in read. S1C33L03 PRODUCT PART 4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Name High-speed DMA Ch.2 transfer counter register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC2_L7 TC2_L6 TC2_L5 TC2_L4 TC2_L3 TC2_L2 TC2_L1 TC2_L0 BLKLEN27 BLKLEN26 BLKLEN25 BLKLEN24 BLKLEN23 BLKLEN22 BLKLEN21 BLKLEN20 Ch.2 transfer counter[7:0] (block transfer mode) DF DE DUALM2 D2DIR DD-8 D7 D6 D5 D4 D3 D2 D1 D0 - TC2_H7 TC2_H6 TC2_H5 TC2_H4 TC2_H3 TC2_H2 TC2_H1 TC2_H0 Ch.2 address mode selection D) Invalid S) Ch.2 transfer direction control reserved Ch.2 transfer counter[15:8] (block transfer mode) 0048240 (HW) High-speed 0048242 DMA Ch.2 (HW) control register Note: D) Dual address mode S) Single address mode High-speed 0048244 DMA Ch.2 (HW) low-order source address set-up register Note: D) Dual address mode S) Single address mode High-speed 0048246 DMA Ch.2 (HW) high-order source address set-up register Note: D) Dual address mode S) Single address mode Function Ch.2 transfer counter[15:8] (single/successive transfer mode) Ch.2 block length (block transfer mode) Ch.2 transfer counter[7:0] (single/successive transfer mode) 1 Dual addr 0 Single addr - 1 Memory WR 0 Memory RD - Ch.2 transfer counter[23:16] (single/successive transfer mode) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S2ADRL15 D) Ch.2 source address[15:0] S2ADRL14 S) Ch.2 memory address[15:0] S2ADRL13 S2ADRL12 S2ADRL11 S2ADRL10 S2ADRL9 S2ADRL8 S2ADRL7 S2ADRL6 S2ADRL5 S2ADRL4 S2ADRL3 S2ADRL2 S2ADRL1 S2ADRL0 DF DE DD DC - DATSIZE2 S2IN1 S2IN0 DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S2ADRH11 D) Ch.2 source address[27:16] S2ADRH10 S) Ch.2 memory address[27:16] S2ADRH9 S2ADRH8 S2ADRH7 S2ADRH6 S2ADRH5 S2ADRH4 S2ADRH3 S2ADRH2 S2ADRH1 S2ADRH0 S1C33L03 PRODUCT PART Setting reserved Ch.2 transfer data size D) Ch.2 source address control S) Ch.2 memory address control EPSON - 1 Half word S2IN[1:0] 1 1 1 0 0 1 0 0 0 Byte Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed Init. R/W Remarks X X X X X X X X X X X X X X X X R/W 0 - 0 - X X X X X X X X R/W - R/W - Undefined in read. R/W X X X X X X X X X X X X X X X X R/W - 0 0 0 - R/W R/W X X X X X X X X X X X X R/W A-4 R/W A-55 4 PERIPHERAL CIRCUITS Register name Address Bit High-speed 0048248 DMA Ch.2 (HW) low-order destination address set-up register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D2ADRL15 D) Ch.2 destination address[15:0] D2ADRL14 S) Invalid D2ADRL13 D2ADRL12 D2ADRL11 D2ADRL10 D2ADRL9 D2ADRL8 D2ADRL7 D2ADRL6 D2ADRL5 D2ADRL4 D2ADRL3 D2ADRL2 D2ADRL1 D2ADRL0 DF DE D2MOD1 D2MOD0 Ch.2 transfer mode DD DC D2IN1 D2IN0 D) Ch.2 destination address control S) Invalid DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D2ADRH11 D) Ch.2 destination D2ADRH10 address[27:16] D2ADRH9 S) Invalid D2ADRH8 D2ADRH7 D2ADRH6 D2ADRH5 D2ADRH4 D2ADRH3 D2ADRH2 D2ADRH1 D2ADRH0 Note: D) Dual address mode S) Single address mode High-speed 004824A DMA Ch.2 (HW) high-order destination address set-up register Note: D) Dual address mode S) Single address mode Name Function High-speed 004824C DF-1 - DMA Ch.2 (HW) D0 HS2_EN enable register reserved High-speed DMA Ch.2 trigger flag register reserved A-56 004824E DF-1 - (HW) D0 HS2_TF Setting D2MOD[1:0] 1 1 1 0 0 1 0 0 D2IN[1:0] 1 1 1 0 0 1 0 0 Mode Invalid Block Successive Single Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed - Ch.2 enable 1 Enable 0 Disable - Ch.2 trigger flag clear (writing) Ch.2 trigger flag status (reading) EPSON 1 Clear 1 Set 0 No operation 0 Cleared Init. R/W X X X X X X X X X X X X X X X X R/W 0 0 R/W 0 0 R/W X X X X X X X X X X X X R/W - - 0 R/W - - 0 R/W Remarks Undefined in read. Undefined in read. S1C33L03 PRODUCT PART 4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Name High-speed DMA Ch.3 transfer counter register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC3_L7 TC3_L6 TC3_L5 TC3_L4 TC3_L3 TC3_L2 TC3_L1 TC3_L0 BLKLEN37 BLKLEN36 BLKLEN35 BLKLEN34 BLKLEN33 BLKLEN32 BLKLEN31 BLKLEN30 Ch.3 transfer counter[7:0] (block transfer mode) DF DE DUALM3 D3DIR DD-8 D7 D6 D5 D4 D3 D2 D1 D0 - TC3_H7 TC3_H6 TC3_H5 TC3_H4 TC3_H3 TC3_H2 TC3_H1 TC3_H0 Ch.3 address mode selection D) Invalid S) Ch.3 transfer direction control reserved Ch.3 transfer counter[15:8] (block transfer mode) 0048250 (HW) High-speed 0048252 DMA Ch.3 (HW) control register Note: D) Dual address mode S) Single address mode High-speed 0048254 DMA Ch.3 (HW) low-order source address set-up register Note: D) Dual address mode S) Single address mode High-speed 0048256 DMA Ch.3 (HW) high-order source address set-up register Note: D) Dual address mode S) Single address mode Function Ch.3 transfer counter[15:8] (single/successive transfer mode) Ch.3 block length (block transfer mode) Ch.3 transfer counter[7:0] (single/successive transfer mode) 1 Dual addr 0 Single addr - 1 Memory WR 0 Memory RD - Ch.3 transfer counter[23:16] (single/successive transfer mode) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S3ADRL15 D) Ch.3 source address[15:0] S3ADRL14 S) Ch.3 memory address[15:0] S3ADRL13 S3ADRL12 S3ADRL11 S3ADRL10 S3ADRL9 S3ADRL8 S3ADRL7 S3ADRL6 S3ADRL5 S3ADRL4 S3ADRL3 S3ADRL2 S3ADRL1 S3ADRL0 DF DE DD DC - DATSIZE3 S3IN1 S3IN0 DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S3ADRH11 D) Ch.3 source address[27:16] S3ADRH10 S) Ch.3 memory address[27:16] S3ADRH9 S3ADRH8 S3ADRH7 S3ADRH6 S3ADRH5 S3ADRH4 S3ADRH3 S3ADRH2 S3ADRH1 S3ADRH0 S1C33L03 PRODUCT PART Setting reserved Ch.3 transfer data size D) Ch.3 source address control S) Ch.3 memory address control EPSON - 1 Half word S3IN[1:0] 1 1 1 0 0 1 0 0 0 Byte Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed Init. R/W Remarks X X X X X X X X X X X X X X X X R/W 0 - 0 - X X X X X X X X R/W - R/W - Undefined in read. R/W X X X X X X X X X X X X X X X X R/W - 0 0 0 - R/W R/W X X X X X X X X X X X X R/W A-4 R/W A-57 4 PERIPHERAL CIRCUITS Register name Address Bit High-speed 0048258 DMA Ch.3 (HW) low-order destination address set-up register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D3ADRL15 D) Ch.3 destination address[15:0] D3ADRL14 S) Invalid D3ADRL13 D3ADRL12 D3ADRL11 D3ADRL10 D3ADRL9 D3ADRL8 D3ADRL7 D3ADRL6 D3ADRL5 D3ADRL4 D3ADRL3 D3ADRL2 D3ADRL1 D3ADRL0 DF DE D3MOD1 D3MOD0 Ch.3 transfer mode DD DC D3IN1 D3IN0 D) Ch.3 destination address control S) Invalid DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D3ADRH11 D) Ch.3 destination D3ADRH10 address[27:16] D3ADRH9 S) Invalid D3ADRH8 D3ADRH7 D3ADRH6 D3ADRH5 D3ADRH4 D3ADRH3 D3ADRH2 D3ADRH1 D3ADRH0 Note: D) Dual address mode S) Single address mode High-speed 004825A DMA Ch.3 (HW) high-order destination address set-up register Note: D) Dual address mode S) Single address mode Name Function High-speed 004825C DF-1 - DMA Ch.3 (HW) D0 HS3_EN enable register reserved High-speed DMA Ch.3 trigger flag register reserved A-58 004825E DF-1 - (HW) D0 HS3_TF Setting D3MOD[1:0] 1 1 1 0 0 1 0 0 D3IN[1:0] 1 1 1 0 0 1 0 0 Mode Invalid Block Successive Single Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed - Ch.3 enable 1 Enable 0 Disable - Ch.3 trigger flag clear (writing) Ch.3 trigger flag status (reading) EPSON 1 Clear 1 Set 0 No operation 0 Cleared Init. R/W X X X X X X X X X X X X X X X X R/W 0 0 R/W 0 0 R/W X X X X X X X X X X X X R/W - - 0 R/W - - 0 R/W Remarks Undefined in read. Undefined in read. S1C33L03 PRODUCT PART 4 PERIPHERAL CIRCUITS A-1 Register name Address SDRAM area configuration register 039FFC0 (B) SDRAM 039FFC1 control register (B) Bit Name SDRAR0 SDRAR1 - SDRPC0 SDRPC1 - Area 7/13 configuration Area 8/14 configuration reserved #CE7/13 pin configuration #CE8/14 pin configuration reserved 1 SDRAM 1 SDRAM D7 D6 D5 D4 SDRENA SDRINI SDRSRF SDRIS Enable SDRAM signals Start SDRAM power up Enable SDRAM self-refresh Initial command sequence 1 1 1 1 039FFC2 D7 - (B) D6-5 SDRCA1 SDRCA0 D4 - D3-2 SDRRA1 SDRRA0 D1 D0 SDRAM mode set-up register SDRBA - 039FFC3 D7 - (B) D6-5 SDRCL1 SDRCL0 D4 - D3-2 SDRBL1 SDRBL0 D1-0 - SDRAM timing set-up register 1 Setting D7 D6 D5-4 D3 D2 D1-0 D3 SDRCLK D2-0 - SDRAM address configuration register Function Keep SDCLK during self-refresh reserved reserved SDRAM page size (column range) - 1 #SDCE0 1 #SDCE1 0 #CE7/13 0 #CE8/14 - Enabled 0 Start 0 Enabled 0 1 precharge 0 2 set reg. 3 refresh 1 Kept 0 - Disabled - Disabled 1 precharge 2 refresh 3 set reg. Stopped - reserved SDRAM row addressing range Number of SDRAM banks reserved reserved SDRAM CAS latency Page size reserved 1K (SDA[9:0]) 512 (SDA[8:0]) 256 (SDA[7:0]) - SDRRA[1:0] Addressing range 1 1 reserved 1 0 8K (SDA[12:0]) 0 1 4K (SDA[11:0]) 0 0 2K (SDA[10:0]) 1 4 banks 0 2 banks - SDRCL[1:0] 1 0 reserved SDRAM burst length SDRBL[1:0] 1 1 1 0 0 1 0 0 reserved - CAS latency 2 CAS latency - Burst length 8 4 2 1 - SDRTRAS[2:0] Number of clocks 1 1 1 7 1 1 0 6 1 0 1 5 1 0 0 4 0 1 1 3 0 1 0 2 0 0 1 1 0 0 0 8 SDRTRP[1:0] Number of clocks 1 1 3 1 0 2 0 1 1 0 0 4 SDRTRC[2:0] Number of clocks 1 1 1 7 1 1 0 6 1 0 1 5 1 0 0 4 0 1 1 3 0 1 0 2 0 0 1 1 0 0 0 8 SDRAM tRP spec D2-0 SDRTRC2 SDRAM tRC spec SDRTRC1 SDRTRC0 S1C33L03 PRODUCT PART 0 Not SDRAM 0 Not SDRAM SDRCA[1:0] 1 1 1 0 0 1 0 0 039FFC4 D7-5 SDRTRAS2 SDRAM tRAS spec (B) SDRTRAS1 SDRTRAS0 D4-3 SDRTRP1 SDRTRP0 Init. EPSON R/W Remarks 0 0 - 0 0 - R/W R/W - 0 when being read. R/W R/W - 0 when being read. 0 0 0 0 R/W R/W 0 when being read. R/W R/W 1 - R/W - 0 when being read. - 0 0 - 0 when being read. R/W - 0 0 - 0 when being read. R/W 0 - R/W - 0 when being read. - 1 1 - 1 1 - 0 when being read. R/W - 0 when being read. R/W - - 0 0 0 R/W 0 0 R/W 0 0 0 R/W 0 when being read. A-59 A-4 4 PERIPHERAL CIRCUITS Register name Address SDRAM timing set-up register 2 Bit Name Function 039FFC5 D7-6 SDRTRCD1 SDRAM tRCD spec (B) SDRTRCD0 0 0 0 R/W R/W - - - 0 to 4096 - 1 1 1 1 1 1 1 1 1 1 1 1 - 0 when being read. R/W - 2 to 15 - 1 1 1 1 - 0 when being read. R/W This register must not be set less than "0x02". reserved - 1 8 bits 0 16 bits SDRAM data path bit width SDRAM bank interleaved access 1 Interleaved 0 One bank - reserved - 0 0 - - 0 when being read. R/W R/W - 0 when being read. SDRAM mode register set flag SDRAM current refresh mode reserved 1 1 - reserved 039FFC6 DF-C - reserved (HW) DB SDRARFC11 SDRAM auto refresh count [11:0] DA SDRARFC10 D9 SDRARFC9 D8 SDRARFC8 D7 SDRARFC7 D6 SDRARFC6 D5 SDRARFC5 D4 SDRARFC4 D3 SDRARFC3 D2 SDRARFC2 D1 SDRARFC1 D0 SDRARFC0 SDRAM self refresh count register 039FFC8 D7-4 - reserved (B) D3 SDRSRFC3 SDRAM self refresh count [3:0] D2 SDRSRFC2 D1 SDRSRFC1 D0 SDRSRFC0 SDRAM advanced control register 039FFC9 (B) SDRAM 039FFCA status register (B) A-60 - SDRSZ SDRBI - D7 SDRMRS D6 SDRSRM D5-0 - Remarks R/W SDRAM auto refresh count register D7 D6 D5 D4-0 Init. R/W 0 0 D5 SDRTRSC SDRAM tRSC spec D4-3 SDRTRRD1 SDRAM tRRD spec SDRTRRD0 D2-0 - Setting SDRTRCD[1:0] Number of clocks 1 1 3 1 0 2 0 1 1 0 0 4 1 1 clock 0 2 clocks SDRTRRD[1:0] Number of clocks 1 1 3 1 0 2 0 1 1 0 0 4 - EPSON 1 Not finished 0 Done 1 Auto refresh 0 Self refresh - R R - 0 when being read. 0 when being read. S1C33L03 PRODUCT PART 4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Name Revision code register D7 D6 D5 D4 D3 D2 D1 D0 PCODE5 PCODE4 PCODE3 PCODE2 PCODE1 PCODE0 RCODE1 RCODE0 LCDC mode register 0 LCDC mode register 1 039FFE0 (B) Revision code 039FFE2 (B) BPP1 BPP0 Bit-per-pixel select (Display mode) - DBLANK FRMRPT - INVDISP reserved Blank display Frame repeat for EL panel reserved Invert display 039FFE3 D7-6 - (B) D5 LCDCEN D4 LPWREN D3-2 - D1 LPSAVE1 D0 LPSAVE0 Init. R/W 0b000010 reserved Color/monochrome select reserved Mask FPSHIFT signal LCD data width/format D7 D6 Setting Product code 039FFE1 D7-6 - (B) D5 LDCOLOR D4-3 - D2 FPSMASK D1 LDDW1 D0 LDDW0 D5-4 D3 D2 D1 D0 LCDC mode register 2 Function reserved LCD controller enable LCDPWR enable reserved Power save mode - 1 Color 0 Mono - 1 Masked LDDW[1:0] 1 x 0 1 0 0 LDDW[1:0] 1 1 1 0 0 1 0 0 0 Output Monochrome reserved 8 bits 4 bits Color 8 bits/format 2 reserved 8 bits/format 1 4 bits BPP[1:0] 1 1 1 0 0 1 0 0 Mode 8 bpp 4 bpp 2 bpp 1 bpp - 1 Blank 1 Repeated 0 Normal 0 Not repeated - 1 Inverted 0 Normal - 1 Enabled 1 Enabled 0 Disabled 0 Disabled - LPSAVE[1:0] Mode 1 1 Normal operation 1 0 Doze 0 1 reserved 0 0 Power save 0 0 0 0 1 0 0 0 Remarks R A-4 R - 0 - 0 0 0 - 0 when being read. R/W - 0 when being read. R/W R/W 0 0 R/W - 0 0 - 0 - 0 when being read. R/W R/W - 0 when being read. R/W - 0 0 - 0 0 - 0 when being read. R/W R/W - 0 when being read. R/W Horizontal panel size register 039FFE4 D7-6 - reserved (B) D5 LDHSIZE5 Horizontal panel size D4 LDHSIZE4 D3 LDHSIZE3 D2 LDHSIZE2 D1 LDHSIZE1 D0 LDHSIZE0 - H resolution (pixels) -1 16 - 0 0 0 0 0 0 - 0 when being read. R/W Vertical panel size register 0 039FFE5 (B) LDVSIZE7 Vertical panel size LDVSIZE6 (low-order 8 bits) LDVSIZE5 LDVSIZE4 LDVSIZE3 LDVSIZE2 LDVSIZE1 LDVSIZE0 V resolution (lines) - 1 0 0 0 0 0 0 0 0 R/W Vertical panel size register 1 039FFE6 D7-2 - reserved (B) D1 LDVSIZE9 Vertical panel size D0 LDVSIZE8 (high-order 2 bits) - V resolution (lines) - 1 - 0 0 - 0 when being read. R/W - Non-display period (pixels) -4 8 - 0 0 0 0 0 - 0 when being read. R/W D7 D6 D5 D4 D3 D2 D1 D0 Horizontal 039FFE7 D7-5 - non-display (B) D4 HNDP4 period register D3 HNDP3 D2 HNDP2 D1 HNDP1 D0 HNDP0 S1C33L03 PRODUCT PART reserved Horizontal non-display period EPSON A-61 4 PERIPHERAL CIRCUITS Register name Address Bit Vertical 039FFEA non-display (B) period register D7 D6 D5 D4 D3 D2 D1 D0 Name VNDPF - VNDP5 VNDP4 VNDP3 VNDP2 VNDP1 VNDP0 Function Setting Vertical non-display period status 1 VNDP 0 Display - reserved Non display period (lines) Vertical non-display period - Init. R/W Remarks 0 - 0 0 0 0 0 0 R - 0 when being read. R/W - 0 0 0 0 0 0 - 0 when being read. R/W MOD rate register 039FFEB D7-6 - reserved (B) D5 MODRATE5 MOD rate D4 MODRATE4 D3 MODRATE3 D2 MODRATE2 D1 MODRATE1 D0 MODRATE0 Screen 1 start address register 0 039FFEC (B) D7 D6 D5 D4 D3 D2 D1 D0 S1ADDR7 S1ADDR6 S1ADDR5 S1ADDR4 S1ADDR3 S1ADDR2 S1ADDR1 S1ADDR0 Screen 1 start address (low-order 8 bits) 0 0 0 0 0 0 0 0 R/W Screen 1 start address register 1 039FFED (B) D7 D6 D5 D4 D3 D2 D1 D0 S1ADDR15 Screen 1 start address S1ADDR14 (high-order 8 bits) S1ADDR13 S1ADDR12 S1ADDR11 S1ADDR10 S1ADDR9 S1ADDR8 0 0 0 0 0 0 0 0 R/W Screen 2 start address register 0 039FFEE (B) D7 D6 D5 D4 D3 D2 D1 D0 S2ADDR7 S2ADDR6 S2ADDR5 S2ADDR4 S2ADDR3 S2ADDR2 S2ADDR1 S2ADDR0 Screen 2 start address (low-order 8 bits) 0 0 0 0 0 0 0 0 R/W Screen 2 start address register 1 039FFEF (B) D7 D6 D5 D4 D3 D2 D1 D0 S2ADDR15 Screen 2 start address S2ADDR14 (high-order 8 bits) S2ADDR13 S2ADDR12 S2ADDR11 S2ADDR10 S2ADDR9 S2ADDR8 0 0 0 0 0 0 0 0 R/W Screen 1 start address register 2 039FFF0 D7-1 - reserved (B) D0 S1ADDR16 Screen 1 start address (MSB) (for portrait mode; fix at 0 in landscape mode) - 0 - 0 when being read. R/W - Memory 039FFF1 address offset (B) register D7 D6 D5 D4 D3 D2 D1 D0 MADOFS7 Memory address offset MADOFS6 MADOFS5 MADOFS4 MADOFS3 MADOFS2 MADOFS1 MADOFS0 0 0 0 0 0 0 0 0 R/W Screen 1 vertical size register 0 D7 D6 D5 D4 D3 D2 D1 D0 S1VSIZE7 S1VSIZE6 S1VSIZE5 S1VSIZE4 S1VSIZE3 S1VSIZE2 S1VSIZE1 S1VSIZE0 0 0 0 0 0 0 0 0 R/W A-62 039FFF2 (B) Screen 1 vertical size (low-order 8 bits) EPSON S1C33L03 PRODUCT PART 4 PERIPHERAL CIRCUITS A-1 Register name Address Bit Name Screen 1 vertical size register 1 039FFF3 D7-2 - (B) D1 S1VSIZE9 D0 S1VSIZE8 FIFO control register 039FFF4 (B) D7 D6 D5 D4 D3 D2 D1 D0 Function Setting reserved Screen 1 vertical size (high-order 2 bits) - reserved FIFOEO3 FIFO empty offset FIFOEO2 FIFOEO1 FIFOEO0 LCLKSEL2 LCDC clock select LCLKSEL1 LCLKSEL0 - 0 0 - 0 when being read. R/W - Fix at 8 (0b1000) - 0 0 0 0 0 0 0 - 0 when being read. R/W - 0 0 0 0 - 0 when being read. R/W 0 0 0 0 - R/W 0 Input 0 Input 0 Input - 0 0 0 - 0 when being read. R/W R/W R/W 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 R/W 0 0 - 0 0 R/W R/W - 0 when being read. R/W 0 0 0 0 0 0 0 0 R/W LCLKSEL[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 LCDC clock BCU_CLK/4 BCU_CLK/3 BCU_CLK/2 BCU_CLK reserved Stop Stop Stop 039FFF5 D7-4 - reserved (B) D3 LUTADDR3 Look-up table address D2 LUTADDR2 D1 LUTADDR1 D0 LUTADDR0 Look-up table data register 039FFF7 (B) reserved - GPIO configuration register 039FFF8 D7-3 - (B) D2 GPIO2C D1 GPIO1C D0 GPIO0C reserved GPIO2 configuration GPIO1 configuration GPIO0 configuration - 1 Output 1 Output 1 Output GPIO status/control register 039FFF9 (B) D7 D6 D5 D4 D3 D2 D1 D0 - GPO6D GPO5D GPO4D GPO3D GPIO2D GPIO1D GPIO0D reserved GPO6 data GPO5 data GPO4 data GPO3 data GPIO2 data GPIO1 data GPIO0 data 1 1 1 1 1 1 1 Scratch pad register 039FFFA (B) D7 D6 D5 D4 D3 D2 D1 D0 SP1A7 SP1A6 SP1A5 SP1A4 SP1A3 SP1A2 SP1A1 SP1A0 Scratch pad Portrait mode register 039FFFB (B) D7 D6 D5-2 D1 D0 PMODEN PMODSEL - PMODCLK1 PMODCLK0 Portrait mode enable Portrait mode select reserved Portrait mode clock select (LCDC clock division ratio) LUTDT3 LUTDT2 LUTDT1 LUTDT0 - Line byte count register for portrait mode 039FFFC (B) D7 D6 D5 D4 D3 D2 D1 D0 S1C33L03 PRODUCT PART - Look-up table data - Division ratio 1: Default mode Division ratio 2: Alternate mode P: Pixel clock, M: Memory clock PMODLBC7 Line byte count PMODLBC6 PMODLBC5 PMODLBC4 PMODLBC3 PMODLBC2 PMODLBC1 PMODLBC0 EPSON Remarks - Look-up table address register D7 D6 D5 D4 D3-0 Init. R/W High High High High High High High 1 Portrait 1 Alternate Low Low Low Low Low Low Low 0 Landscape 0 Default - PMODCLK[1:0] Division ratio 1 1 1 P: 1/8, M: 1/8 1 0 P: 1/4, M: 1/4 0 1 P: 1/2, M: 1/2 0 0 P: 1/1, M: 1/1 PMODCLK[1:0] Division ratio 2 1 1 P: 1/8, M: 1/4 1 0 P: 1/4, M: 1/2 0 1 P: 1/2, M: 1/1 0 0 P: 1/2, M: 1/1 R/W - 0 when being read. A-63 A-4 4 PERIPHERAL CIRCUITS Register name Address Bit Name LCDC 039FFFD system control (B) register D7 D6 D5 D4 D3 D2 D1 D0 VRAMAR VRAMWT2 VRAMWT1 VRAMWT0 EDMAEN BREQEN LCDCST LCDCEC A-64 Function Setting VRAM area select 1 Area 8 VRAM wait control (number of wait cycles for SRAM) External DMA enable External bus-request enable A0/BSL select Big/little endian select EPSON 1 1 1 1 Init. R/W 0 Area 7 0-7 Enabled Enabled BSL Big endian 0 0 0 0 Disabled Disabled A0 Little endian 0 0 0 0 0 0 0 0 Remarks R/W R/W R/W R/W R/W R/W S1C33L03 PRODUCT PART 5 POWER-DOWN CONTROL A-1 5 Power-Down Control This chapter describes the controls used to reduce power consumption of the device. Points on power saving The current consumption of the device varies greatly with the CPU's operation mode, the system clocks used, and the peripheral circuits operated. Current consumption CPU/BCU System clock OSC3 oscillation circuit Prescaler/peripheral circuit low SLEEP - OFF STOP HALT2 OSC1 OFF Operating OSC1 OFF HALT2 OSC3 ON HALT(basic) OSC3 ON high Operating OSC3 ON RUN To reduce power consumption of the device, it is important that as many unnecessary circuits as possible be turned off. In particular, peripheral circuits operating at a fast-clock rate consume a large amount of current, so design the program so that these circuits are turned off whenever unnecessary. Power-saving in standby modes When CPU processing is unnecessary, such as when waiting for an interrupt from key entries or peripheral circuits, place the device in standby mode to reduce current consumption. Standby mode Method to enter the mode Circuits/functions stopped Execute the halt instruction after setting HLT2OP CPU (DMA cannot be used.) (D3)/Clock option register (0x40190) to "0". When the #BUSREQ signal is asserted from an external bus master while SEPD (D1)/Bus control register (0x4812E) = "1". Execute the halt instruction after setting HLT2OP CPU, BCU, bus clock, and DMA to "1". Execute the slp instruction. CPU, BCU, bus clock, DMA, high-speed (OSC3) oscillation circuit, prescaler, and peripheral circuits that use the prescaler output clocks Basic HALT mode HALT2 mode SLEEP mode HLT2OP (D3)/Clock option register (0x40190) that is used to select a HALT mode is set to "0" (basic HALT mode) at initial reset. Notes: * In systems in which DRAM or SDRAM is connected directly to the device, the refresh function is turned off during HALT2 and SLEEP modes. However, the SDRAM self refresh function can be used by activating it before the CPU enters HALT2 or SLEEP mode. * The standby mode is cleared by interrupt generation (except for the basic HALT mode, which is set using an external bus master). Therefore, before entering standby mode, set the related registers to allow an interrupt to be used to clear the standby mode to be generated. * When clearing the standby mode with an interrupt from port input, the interrupt operates as a level interrupt regardless of the interrupt trigger setting. When edge trigger is set for the interrupt trigger, attention must be paid to the port level during standby mode. The low-speed (OSC1) oscillation circuit and clock timer continue operating even during SLEEP mode. If they are unnecessary, these circuits can also be turned off. Function Control bit "1" "0" Default Low-speed (OSC1) oscillation ON/OFF control SOSC1(D0)/ Power control register(0x40180) ON OFF ON Switching over the system clocks Normally, the system is clocked by the high-speed (OSC3) oscillation clock. If high-speed operation is unnecessary, switch the system clock to the low-speed (OSC1) oscillation clock and turn off the high-speed (OSC3) oscillation circuit. This helps to reduce current consumption. However, if DRAM is connected directly to the device, note that the refresh function is also turned off. Even during operation using the high-speed (OSC3) oscillation clock, power reduction can also be achieved through the use of a system clock derived from the OSC3 clock by dividing it (1/1, 1/2, 1/4, or 1/8). S1C33L03 PRODUCT PART EPSON A-65 A-5 5 POWER-DOWN CONTROL Function System clock switch over High-speed (OSC3) oscillation ON/OFF control System clock division ratio selection Control bit CLKCHG(D2)/ Power control register(0x40180) SOSC3(D1)/ Power control register(0x40180) CLKDT(D[7:6])/ Power control register(0x40180) "1" "0" Default OSC3 OSC1 OSC3 ON OFF "11" = 1/8 "10" = 1/4 "01" = 1/2 "00" = 1/1 ON 1/1 Turning off the prescaler and peripheral circuits Current consumption can be reduced by turning off the peripheral circuits operating at high speed as much as possible. The peripheral circuits are as follows. 1) Peripheral circuits using the clock generated by the prescaler * 16-bit programmable timers 0 to 5 (watchdog timer) * 8-bit programmable timers 0 to 5 (DRAM refresh, serial interface) * A/D converter 2) Peripheral circuits using the clock (source clock for prescaler) supplied to the prescaler * 16-bit programmable timers 0 to 5 (watchdog timer) * 8-bit programmable timers 0 to 5 (DRAM refresh) * A/D converter * Serial interface * Input/output ports If none of all circuits of the above 1) and 2) need to be used, turn off the prescaler. If the circuit of the above 1) or 2) need to be used, do not turn off the prescaler. When operation of the prescaler is stopped, the clock supply to the circuits of the above 2) stops. When some these circuits of the above 1) need to be used, turn off all other unnecessary circuits and stop the clock supply from the prescaler to those circuits. The prescaler operating control and the clock supply control bits for each peripheral circuit are shown in the table below. Function Prescaler ON/OFF 16-bit timer 0 clock control 16-bit timer 0 Run/Stop 16-bit timer 1 clock control 16-bit timer 1 Run/Stop 16-bit timer 2 clock control 16-bit timer 2 Run/Stop 16-bit timer 3 clock control 16-bit timer 3 Run/Stop 16-bit timer 4 clock control 16-bit timer 4 Run/Stop 16-bit timer 5 clock control 16-bit timer 5 Run/Stop 8-bit timer 0 clock control 8-bit timer 0 Run/Stop 8-bit timer 1 clock control 8-bit timer 1 Run/Stop 8-bit timer 2 clock control 8-bit timer 2 Run/Stop 8-bit timer 3 clock control 8-bit timer 3 Run/Stop 8-bit timer 4 clock control 8-bit timer 4 Run/Stop 8-bit timer 5 clock control 8-bit timer 5 Run/Stop A/D converter clock control A/D conversion enable A-66 Control bit PSCON(D5)/Power control register(0x40180) P16TON0(D3)/16-bit timer 0 clock control register(0x40147) PRUN0(D0)/16-bit timer 0 control register(0x48186) P16TON1(D3)/16-bit timer 1 clock control register(0x40148) PRUN1(D0)/16-bit timer 1 control register(0x4818E) P16TON2(D3)/16-bit timer 2 clock control register(0x40149) PRUN2(D0)/16-bit timer 2 control register(0x48196) P16TON3(D3)/16-bit timer 3 clock control register(0x4014A) PRUN3(D0)/16-bit timer 3 control register(0x4819E) P16TON4(D3)/16-bit timer 4 clock control register(0x4014B) PRUN4(D0)/16-bit timer 4 control register(0x481A6) P16TON5(D3)/16-bit timer 5 clock control register(0x4014C) PRUN5(D0)/16-bit timer 5 control register(0x481AE) P8TON0(D3)/8-bit timer 0/1 clock control register(0x4014D) PTRUN0(D0)/8-bit timer 0 control register(0x40160) P8TON1(D7)/8-bit timer 0/1 clock control register(0x4014D) PTRUN1(D0)/8-bit timer 1 control register(0x40164) P8TON2(D3)/8-bit timer 2/3 clock control register(0x4014E) PTRUN2(D0)/8-bit timer 2 control register(0x40168) P8TON3(D7)/8-bit timer 2/3 clock control register(0x4014E) PTRUN3(D0)/8-bit timer 3 control register(0x4016C) P8TON4(D3)/8-bit timer 4/5 clock control register(0x40145) PTRUN4(D0)/8-bit timer 4 control register(0x40174) P8TON5(D7)/8-bit timer 4/5 clock control register(0x40145) PTRUN5(D0)/8-bit timer 5 control register(0x40178) PSONAD(D3)/A/D clock control register(0x4014F) ADE(D2)/A/D enable register(0x40244) EPSON "1" "0" Default ON ON RUN ON RUN ON RUN ON RUN ON RUN ON RUN ON RUN ON RUN ON RUN ON RUN ON RUN ON RUN ON RUN OFF OFF STOP OFF STOP OFF STOP OFF STOP OFF STOP OFF STOP OFF STOP OFF STOP OFF STOP OFF STOP OFF STOP OFF STOP OFF STOP ON OFF STOP OFF STOP OFF STOP OFF STOP OFF STOP OFF STOP OFF STOP OFF STOP OFF STOP OFF STOP OFF STOP OFF STOP OFF STOP S1C33L03 PRODUCT PART 5 POWER-DOWN CONTROL A-1 The same clock source must be used for the prescaler operating clock and the CPU operating clock. Therefore, when operating the CPU in low-speed with the OSC1 clock, the prescaler input clock must be switched according to the CPU operating clock. In this case, in order to prevent a malfunction in the peripheral circuit, the prescaler should be turned off before switching the CPU operating clock. After the CPU operating clock has been switched, switch the prescaler operating clock and then turn the prescaler on. Function Prescaler operating clock switch over Control bit "1" "0" PSCDT0 (D0)/Prescaler clock select register(0x40181) OSC1 OSC3/ PLL Default OSC3/ PLL Power-down control of the LCD controller The LCD controller provides the power save mode on its own. Since the power save mode can be controlled by software, set the mode when turning the LCD display off. Function Power save mode Control bit LPSAVE[1:0] D([1:0])/LCDC mode register 2 (0x39FFE3) "11" Normal operation "00" Default Power Power save mode save mode Note: The power save mode switches the LCD panel power control signal (LCDPWR) to the inactive state. This may cause damage of the LCD panel if the clock supply to the LCD controller is stopped at the same time. Therefore, do not stop the clock supply for 1 frame cycles or more after setting the LCD controller to power save mode. S1C33L03 PRODUCT PART EPSON A-67 A-5 6 BASIC EXTERNAL WIRING DIAGRAM 6 Basic External Wiring Diagram FPDAT[7:0] FPSHIFT FPFRAME FPLINE DRDY LCDPWR LCD panel External Bus HSDMA A[23:0] D[15:0] #RD #EMEMRD #DRD #GARD #GAAS #WRL/#WR/#WE #WRH/#BSH #DWE/#SDWE #HCAS/#SDCAS #LCAS/#SDRAS #CExx/#RASx/#SDCEx SDA10 SDCKE HDQM/LDQM #CE10EX #WAIT BCLK S1C33L03 #BUSREQ [The potential of the substrate #BUSACK (back of the chip) is VSS.] #BUSGET #NMI VDD VDDE AVDDE EA10MD0 EA10MD1 #X2SPD 1 PLLS0 PLLS1 OSC3 OSC4 Serial I/O A/D input #ADTRG ADx OSC2 Input Kxx I/O Pxx X'tal1 CG1 CD1 Rf1 X'tal2 CR CG2 CD2 Rf2 R1 C1 C2 Crystal oscillator Gate capacitor Drain capacitor Feedback resistor Crystal oscillator Ceramic oscillator Gate capacitor Drain capacitor Feedback resistor Resistor Capacitor Capacitor C2 C1 R1 PLLC #DMAREQx #DMAACKx #DMAENDx CG2 X'tal2 or CR Rf2 X'tal1 Rf1 OSC1 EXCLx TMx T8UFx 3.3V ICEMD SINx SOUTx #SCLKx #SRDYx Timer input/output + DSIO CD2 CG1 CD1 #RESET VSS 32.768 kHz, CI(Max.) = 34 k 10 pF 10 pF 10 M 33 MHz (Max.) 33 MHz (Max.) 10 pF 10 pF 1 M 4.7 k 100 pF 5 pF 1: When the PLL is not used, leave the PLLC pin open. Note: The above table is simply an example, and is not guaranteed to work. A-68 EPSON S1C33L03 PRODUCT PART 7 PRECAUTIONS ON MOUNTING A-1 7 Precautions on Mounting The following shows the precautions when designing the board and mounting the IC. Oscillation Circuit * Oscillation characteristics change depending on conditions (board pattern, components used, etc.). In particular, when a ceramic oscillator or crystal oscillator is used, use the oscillator manufacturer's recommended values for constants such as capacitance and resistance. A-7 * Disturbances of the oscillation clock due to noise may cause a malfunction. Consider the following points to prevent this: (1) Components which are connected to the OSC3 (OSC1), OSC4 (OSC2) and PLLC pins, such as oscillators, resistors and capacitors, should be connected in the shortest line. (2) As shown in the figure below, make a VSS pattern as large as possible at circumscription of the OSC3 (OSC1) and OSC4 (OSC2) pins and the components connected to these pins. The same applies to the PLLC pin. Furthermore, do not use this VSS pattern to connect other components than the oscillation system. Sample VSS pattern OSC3 and OSC4 PLLC VSS OSC4 PLLC OSC3 VSS VSS (3) When supplying an external clock to the OSC3 (OSC1) pin, the clock source should be connected to the OSC3 (OSC1) pin in the shortest line. Furthermore, do not connect anything else to the OSC4 (OSC2) pin. * In order to prevent unstable operation of the oscillation circuit due to current leak between OSC3 (OSC1) and VDD, please keep enough distance between OSC3 (OSC1) and VDD or other signals on the board pattern. Reset Circuit * The power-on reset signal which is input to the #RESET pin changes depending on conditions (power rise time, components used, board pattern, etc.). Decide the time constant of the capacitor and resistor after enough tests have been completed with the application product. * In order to prevent any occurrences of unnecessary resetting caused by noise during operating, components such as capacitors and resistors should be connected to the #RESET pin in the shortest line. Power Supply Circuit * Sudden power supply variation due to noise may cause malfunction. Consider the following points to prevent this: (1) The power supply should be connected to the VDD, VDDE, VSS and AVDDE pins with patterns as short and large as possible. In particular, the power supply for AVDDE affects A/D conversion precision. S1C33205 PRODUCT PART EPSON A-69 7 PRECAUTIONS ON MOUNTING (2) When connecting between the VDD and VSS pins with a bypass capacitor, the pins should be connected as short as possible. Bypass capacitor connection example VDD VDD VSS VSS A/D Converter * When the A/D converter is not used, the power supply pin AVDDE for the analog system should be connected to VDDE. Arrangement of Signal Lines * In order to prevent generation of electromagnetic induction noise caused by mutual inductance, do not arrange a large current signal line near the circuits that are sensitive to noise such as the oscillation unit and analog input unit. * When a signal line is parallel with a high-speed line in long distance or intersects a high-speed line, noise may generated by mutual interference between the signals and it may cause a malfunction. Do not arrange a high-speed signal line especially near circuits that are sensitive to noise such as the oscillation unit and analog input unit. Prohibited pattern K60 (AD0) OSC4 OSC3 Large current signal line High-speed signal line VSS Large current signal line High-speed signal line A-70 EPSON S1C33205 PRODUCT PART 8 ELECTRICAL CHARACTERISTICS A-1 8 Electrical Characteristics 8.1 Absolute Maximum Rating Item Symbol Supply voltage C33 I/O power voltage Input voltage High-level output current VDD VDDE VI IOH Low-level output current IOL Analog power voltage Analog input voltage Storage temperature AVDDE AVIN TSTG S1C33L03 PRODUCT PART Condition Rated value 1 pin Total of all pins 1 pin Total of all pins -0.3 to +4.0 -0.3 to +7.0 -0.3 to VDDE+0.5 -10 -40 10 40 -0.3 to +7.0 -0.3 to AVDDE+0.3 -65 to +150 EPSON (VSS=0V) V V V mA mA mA mA V V C Unit A-71 A-8 8 ELECTRICAL CHARACTERISTICS 8.2 Recommended Operating Conditions 1) 3.3 V/5.0 V dual power source Item Supply voltage (high voltage) Supply voltage (low voltage) Input voltage CPU operating clock frequency External bus operating clock frequency Low-speed oscillation frequency Operating temperature Input rise time (normal input) Input fall time (normal input) Input rise time (schmitt input) Input fall time (schmitt input) Symbol Condition VDDE VDD HVI LVI fCPU fBUS fOSC1 Ta tri tfi tri tfi Min. Typ. Max. 4.50 2.70 VSS VSS - - - -40 - - - - 5.00 - - - - - 32.768 25 - - - - 5.50 3.60 VDDE VDD 50 35 - 85 50 50 5 5 (VSS=0V) Unit V V V V MHz MHz kHz C ns ns ms ms 2) 3.3 V single power source Item Supply voltage Input voltage CPU operating clock frequency External bus operating clock frequency Low-speed oscillation frequency Operating temperature Input rise time (normal input) Input fall time (normal input) Input rise time (schmitt input) Input fall time (schmitt input) Symbol Condition VDD VI fCPU fBUS fOSC1 Ta tri tfi tri tfi Min. 2.70 VSS - - - -40 - - - - (VDDE=VDD, VSS=0V) Max. Unit - 3.60 V - VDD V - 50 MHz - 35 MHz 32.768 - kHz 25 85 C - 50 ns - 50 ns - 5 ms - 5 ms Typ. 3) 2.0 V single power source Item Supply voltage Input voltage CPU operating clock frequency External bus operating clock frequency Low-speed oscillation frequency Operating temperature Input rise time (normal input) Input fall time (normal input) Input rise time (schmitt input) Input fall time (schmitt input) A-72 Symbol Condition VDD VI fCPU fBUS fOSC1 Ta tri tfi tri tfi Min. 1.80 VSS - - - -40 - - - - EPSON (VDDE=VDD, VSS=0V) Max. Unit 2.00 2.20 V - VDD V - 20 MHz - 20 MHz 32.768 - kHz 25 85 C - 100 ns - 100 ns - 10 ms - 10 ms Typ. S1C33L03 PRODUCT PART 8 ELECTRICAL CHARACTERISTICS A-1 8.3 DC Characteristics 1) 3.3 V/5.0 V dual power source (Unless otherwise specified: VDDE=5V0.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40C to +85C) Symbol Condition Min. Typ. Max. Unit Input leakage current ILI -1 - 1 A Off-state leakage current IOZ -1 - 1 A High-level output voltage VOH IOH=-3mA (Type1), IOH=-12mA (Type3), VDDE - - V -0.4 VDDE=Min. Low-level output voltage VOL IOL=3mA (Type1), IOL=12mA (Type3), - - 0.4 V Item High-level input voltage Low-level input voltage Positive trigger input voltage Negative trigger input voltage Hysteresis voltage High-level input voltage Low-level input voltage Pull-up resistor Pull-down resistor Input pin capacitance Output pin capacitance I/O pin capacitance VIH VIL VT+ VTVH VIH2 VIL2 RPU RPD CI CO CIO VDDE=Min. CMOS level, VDDE=Max. CMOS level, VDDE=Min. CMOS Schmitt CMOS Schmitt CMOS Schmitt TTL level, VDDE=Max. TTL level, VDDE=Min. VI=0V VI=VDDE (ICEMD) f=1MHz, VDDE=0V f=1MHz, VDDE=0V f=1MHz, VDDE=0V 3.5 - 2.0 0.8 0.3 2.0 - 60 30 - - - - - - - - - - 120 60 - - - - 1.0 4.0 3.1 - - 0.8 288 144 10 10 10 V V V V V V V k k pF pF pF 2) 3.3 V single power source Item Symbol Static current consumption Input leakage current Off-state leakage current High-level output voltage IDDS ILI IOZ VOH Low-level output voltage VOL High-level input voltage Low-level input voltage Positive trigger input voltage Negative trigger input voltage Hysteresis voltage Pull-up resistor VIH VIL VT+ VTVH RPU Pull-down resistor Input pin capacitance Output pin capacitance I/O pin capacitance RPD CI CO CIO (Unless otherwise specified: VDDE=VDD=2.7V to 3.6V, Ta=-40C to +85C) Condition Min. Typ. Max. Unit Static state, Tj=85C - - 90 A -1 - 1 A -1 - 1 A IOH=-2mA (Type1), IOH=-6mA (Type2), VDD - - V -0.4 IOH=-12mA (Type3), VDD=Min. IOL=2mA (Type1), IOL=6mA (Type2), - - 0.4 V IOL=12mA (Type3), VDD=Min. CMOS level, VDD=Max. CMOS level, VDD=Min. LVTTL Schmitt LVTTL Schmitt LVTTL Schmitt VI=0V Other than DSIO DSIO VI=VDD (ICEMD) f=1MHz, VDD=0V f=1MHz, VDD=0V f=1MHz, VDD=0V 2.0 - 1.1 0.6 0.1 80 40 40 - - - - - - - - 200 100 100 - - - - 0.8 2.4 1.8 - 480 240 240 10 10 10 V V V V V k k k pF pF pF Note: See Appendix B for pin characteristics. S1C33L03 PRODUCT PART EPSON A-73 A-8 8 ELECTRICAL CHARACTERISTICS 3) 2.0 V single power source Item (Unless otherwise specified: VDDE=VDD=2V0.2V, VSS=0V, Ta=-40C to +85C) Condition Min. Typ. Max. Unit Static state, Tj=85C - - 80 A -1 - 1 A -1 - 1 A IOH=-0.6mA (Type1), IOH=-2mA (Type2), VDD - - V -0.2 IOH=-4mA (Type3), VDD=Min. IOL=0.6mA (Type1), IOL=2mA (Type2), - - 0.2 V Symbol Static current consumption Input leakage current Off-state leakage current High-level output voltage IDDS ILI IOZ VOH Low-level output voltage VOL High-level input voltage Low-level input voltage Positive trigger input voltage Negative trigger input voltage Hysteresis voltage Pull-up resistor VIH VIL VT+ VTVH RPU Pull-down resistor Input pin capacitance Output pin capacitance I/O pin capacitance RPD CI CO CIO IOL=4mA (Type3), VDD=Min. CMOS level, VDD=Max. CMOS level, VDD=Min. CMOS Schmitt CMOS Schmitt CMOS Schmitt VI=0V Other than DSIO DSIO VI=VDD (ICEMD) f=1MHz, VDD=0V f=1MHz, VDD=0V f=1MHz, VDD=0V 1.6 - 0.4 0.3 0 120 60 60 - - - - - - - - 480 240 240 - - - - 0.3 1.6 1.4 - 1200 600 600 10 10 10 V V V V V k k k pF pF pF Note: See Appendix B for pin characteristics. A-74 EPSON S1C33L03 PRODUCT PART 8 ELECTRICAL CHARACTERISTICS A-1 8.4 Current Consumption 1) 3.3 V power source (Unless otherwise specified: VDDE=2.7V to 5.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40C to +85C) Symbol Condition Min. Typ. Max. Unit Operating current IDD1 When CPU is operating 20MHz - 27 35 mA 1 33MHz - 45 60 50MHz - 65 85 IDD2 HALT mode 20MHz - 13 16 mA 2 33MHz - 22 30 50MHz - 30 40 IDD3 HALT2 mode 20MHz - 6 8 mA 3 33MHz - 9 12 50MHz - 14 18 IDD4 SLEEP mode - 1 30 A 4 Clock timer operating current IDDCT When clock timer only is operating - 7 - A 5 OSC1 oscillation: 32kHz Item 2) 2.0 V power source Item (Unless otherwise specified: VDDE=VDD=2.0V0.2V, VSS=0V, Ta=-40C to +85C) Condition Min. Typ. Max. Unit IDD1 When CPU is operating 20MHz - 14 18 mA 1 IDD2 HALT mode 20MHz - 7 10 mA 2 IDD3 HALT2 mode 20MHz - 2.5 4 mA 3 IDD4 SLEEP mode - 1 30 A 4 IDDCT When clock timer only is operating - 1.5 - A 5 OSC1 oscillation: 32kHz Symbol Operating current Clock timer operating current 3) Analog power current Item Symbol A/D converter operating current AIDD1 (Unless otherwise specified: VSS=0V, Ta=-40C to +85C) Min. Typ. Max. Unit VDD=3.6V, VDDE=AVDDE=5.0V0.5V - 800 1400 A 6 VDD=VDDE=AVDDE=2.7V to 3.6V - 500 800 Condition 4) LCD controller operating current (Unless otherwise specified: VDDE=2.7V to 5.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40C to +85C) Symbol Condition Min. Typ. Max. Unit LCD controller operating current LIDD1 Display resolution = 320 x 240, 1bpp - 6.5 7 mA LCDC CLK = 25MHz (VRAM = SRAM) - 12 13 mA LIDD2 Display resolution = 320 x 240, 1bpp LCDC CLK = 25MHz (VRAM = SDRAM) Item Current consumption measurement condition: VIH=VDD, VIL=0V, output pins are open, VDDE current is not included note) No. OSC3 OSC1 CPU Clock timer Other peripheral circuits 2 1 2 3 4 5 6 On On On Off Off On Off Off Off Off On Off Normal operation 1 HALT mode HALT2 mode SLEEP mode HALT mode HALT mode Stop Stop Stop Stop Run Stop Stop Stop Stop Stop Stop A/D converter only operated, conversion clock frequency=2MHz 1: The values of current consumption while the CPU is operating were measured when a test program that consists of 55% load instructions, 23% arithmetic operation instructions, 1% mac instruction, 12% branch instructions and 9% ext instruction is being executed in the built-in ROM continuously. 2: The LCD controller is included. S1C33L03 PRODUCT PART EPSON A-75 A-8 8 ELECTRICAL CHARACTERISTICS 8.5 A/D Converter Characteristics 1) 3.3 V/5.0 V dual power source (Unless otherwise specified: VDDE=AVDDE=4.5V to 5.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40C to +85C, ST[1:0]=11) Item Symbol Condition Min. Typ. Max. Unit Resolution - - 10 - bit Conversion time - 5 - - s 1 Zero scale error EZS 0 2 4 LSB Full scale error EFS -2 - 2 LSB Integral linearity error EL -3 - 3 LSB Differential linearity error ED -3 - 3 LSB Permissible signal source impedance - - - 5 k Analog input capacitance - - - 45 pF note 1) Indicates the minimum value when A/D clock = 4MHz (maximum clock frequency in 5V system). Indicates the maximum value when A/D clock = 32kHz (minimum clock frequency in 5V system). 2) 3.3 V single power source (Unless otherwise specified: VDDE=AVDDE=VDD=2.7V to 3.6V, VSS=0V, Ta=-40C to +85C, ST[1:0]=11) Item Symbol Condition Min. Typ. Max. Unit Resolution - - 10 - bit Conversion time - 10 - 625 s 1 Zero scale error EZS 0 2 4 LSB Full scale error EFS -2 - 2 LSB Integral linearity error EL -3 - 3 LSB Differential linearity error ED -3 - 3 LSB Permissible signal source impedance - - - 5 k Analog input capacitance - - - 45 pF note 1) Indicates the minimum value when A/D clock = 2MHz (maximum clock frequency in 3V system). Indicates the maximum value when A/D clock = 32kHz (minimum clock frequency in 3V system). Note: * Be sure to use as VDDE = AVDDE. * The A/D converter cannot be used when the S1C33L03 is used with a 2V power source. A/D conversion error V[000]h V'[000]h V[3FF]h V'[3FF]h A-76 = Ideal voltage at zero-scale point (=0.5LSB) = Actual voltage at zero-scale point = Ideal voltage at full-scale point (=1022.5LSB) = Actual voltage at full-scale point AVDDE - VSS 210 - 1 V'[3FF]h - V'[000]h 1LSB' = 210 - 2 1LSB = EPSON S1C33L03 PRODUCT PART 8 ELECTRICAL CHARACTERISTICS A-1 Zero scale error Digital output (hex) 004 Ideal conversion characteristic 003 002 V[000]h (=0.5LSB) Actual conversion characteristic Zero scale error EZS = 001 (V'[000]h - 0.5LSB') - (V[000]h - 0.5LSB) [LSB] 1LSB V'[000]h 000 VSS A-8 Analog input Full scale error V[3FF]h (=1022.5LSB) V'[3FF]h Digital output (hex) 3FF 3FE Full scale error EFS = 3FD (V'[3FF]h + 0.5LSB') - (V[3FF]h + 0.5LSB) [LSB] 1LSB Actual conversion characteristic 3FC Ideal conversion characteristic 3FB AVDDE Analog input Integral linearity error 3FF Digital output (hex) 3FE V'[3FF]h 3FD Integral linearity error EL = V N' - V N [LSB] 1LSB' VN VN' 003 Actual conversion characteristic 002 Ideal conversion characteristic 001 V'[000]h 000 VSS Analog input AVDDE Differential linearity error Digital output (hex) N+1 Ideal conversion characteristic N Actual conversion characteristic N-1 V'[N]h Differential linearity error ED = N-2 V'[N-1]h V'[N]h - V'[N-1]h - 1 [LSB] 1LSB' Analog input S1C33L03 PRODUCT PART EPSON A-77 8 ELECTRICAL CHARACTERISTICS 8.6 AC Characteristics 8.6.1 Symbol Description tCYC: Bus-clock cycle time * In x1 mode, tCYC = 50 ns (20 MHz) when the CPU is operated with a 20-MHz clock tCYC = 30 ns (33 MHz) when the CPU is operated with a 33-MHz clock * In x2 mode, tCYC = 50 ns (20 MHz) when the CPU is operated with a 40-MHz clock tCYC = 40 ns (25 MHz) when the CPU is operated with a 50-MHz clock tCYC = 33 ns (30 MHz) when the CPU is operated with a 60-MHz clock WC: Number of wait cycles Up to 7 cycles can be set for the number of cycles using the BCU control register. Furthermore, it can be extended to a desired number of cycles by setting the #WAIT pin from outside of the IC. The minimum number of read cycles with no wait (0) inserted is 1 cycle. The minimum number of write cycles with no wait cycle (0) inserted is 2 cycles. It does not change even if 1-wait cycle is set. The write cycle is actually extended when 2 or more wait cycles are set. When inserting wait cycles by controlling the #WAIT pin from outside of the IC, pay attention to the timing of the #WAIT signal sampling. Read cycles are terminated at the cycle in which the #WAIT signal is negated. Write cycles are terminated at the following cycle after the #WAIT signal is negated. C1, C2, C3, Cn: Cycle number C1 indicates the first cycle when the BCU transfers data from/to an external memory or another device. Similarly, C2 and Cn indicate the second cycle and nth cycle, respectively. Cw: Wait cycle Indicates that the cycle is wait cycle inserted. 8.6.2 AC Characteristics Measurement Condition Signal detection level: Input signal High level Low level Output signal High level Low level VIH = VDDE - 0.4 V VIL = 0.4 V VOH = 1/2 VDDE VOL = 1/2 VDDE The following applies when OSC3 is external clock input: Input signal High level VIH = 1/2 VDD Low level VIL = 1/2 VDD Input signal waveform: Rise time (10% 90% VDD) 5 ns Fall time (90% 10% VDD) 5 ns Output load capacitance: CL = 50 pF A-78 EPSON S1C33L03 PRODUCT PART 8 ELECTRICAL CHARACTERISTICS A-1 8.6.3 C33 Block AC Characteristic Tables External clock input characteristics (Note) These AC characteristics apply to input signals from outside the IC. The OSC3 input clock must be within VDD to VSS voltage range. 1) 3.3 V/5.0 V dual power source (Unless otherwise specified: VDDE=5.0V0.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40C to +85C) Symbol Min. Max. Unit High-speed clock cycle time tC3 30 ns OSC3 clock input duty tC3ED 45 55 % OSC3 clock input rise time tIF 5 ns OSC3 clock input fall time tIR 5 ns BCLK high-level output delay time tCD1 35 ns BCLK low-level output delay time tCD2 35 ns Minimum reset pulse width tRST 6*tCYC ns Item 2) 3.3 V single power source (Unless otherwise specified: VDDE=VDD=2.7V to 3.6V, VSS=0V, Ta=-40C to +85C) Symbol Min. Max. Unit High-speed clock cycle time tC3 30 ns OSC3 clock input duty tC3ED 45 55 % OSC3 clock input rise time tIF 5 ns OSC3 clock input fall time tIR 5 ns BCLK high-level output delay time tCD1 35 ns BCLK low-level output delay time tCD2 35 ns Minimum reset pulse width tRST 6*tCYC ns Item 3) 2.0 V single power source (Unless otherwise specified: VDDE=VDD=2.0V0.2V, VSS=0V, Ta=-40C to +85C) Symbol Min. Max. Unit High-speed clock cycle time tC3 50 ns OSC3 clock input duty tC3ED 45 55 % OSC3 clock input rise time tIF 5 ns OSC3 clock input fall time tIR 5 ns BCLK high-level output delay time tCD1 60 ns BCLK low-level output delay time tCD2 60 ns Minimum reset pulse width tRST 6*tCYC ns Item BCLK clock output characteristics (Note) These AC characteristic values are applied only when the high-speed oscillation circuit is used. 1) 3.3 V/5.0 V dual power source (Unless otherwise specified: VDDE=5.0V0.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40C to +85C) Symbol Min. Max. Unit BCLK clock output duty tCBD 40 60 % Item 2) 3.3 V single power source Item BCLK clock output duty (Unless otherwise specified: VDDE=VDD=2.7V to 3.6V, VSS=0V, Ta=-40C to +85C) Symbol Min. Max. Unit tCBD 40 60 % 3) 2.0 V single power source Item BCLK clock output duty S1C33L03 PRODUCT PART (Unless otherwise specified: VDDE=VDD=2.0V0.2V, VSS=0V, Ta=-40C to +85C) Symbol Min. Max. Unit tCBD 40 60 % EPSON A-79 A-8 8 ELECTRICAL CHARACTERISTICS Common characteristics 1) 3.3 V/5.0 V dual power source (Unless otherwise specified: VDDE=5.0V0.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40C to +85C) Symbol Min. Max. Unit Address delay time tAD - 8 ns 1 #CEx delay time (1) tCE1 - 8 ns #CEx delay time (2) tCE2 - 8 ns Wait setup time tWTS 15 - ns Wait hold time tWTH 0 - ns Read signal delay time (1) tRDD1 8 ns 2 Read data setup time tRDS 12 ns Read data hold time tRDH 0 ns Write signal delay time (1) tWRD1 8 ns 3 Write data delay time (1) tWDD1 10 ns Write data delay time (2) tWDD2 0 10 ns Write data hold time tWDH 0 ns Item 2) 3.3 V single power source Item Address delay time #CEx delay time (1) #CEx delay time (2) Wait setup time Wait hold time Read signal delay time (1) Read data setup time Read data hold time Write signal delay time (1) Write data delay time (1) Write data delay time (2) Write data hold time (Unless otherwise specified: VDDE=VDD=2.7V to 3.6V, VSS=0V, Ta=-40C to +85C) Symbol Min. Max. Unit tAD - 10 ns 1 tCE1 - 10 ns tCE2 - 10 ns tWTS 15 - ns tWTH 0 - ns tRDD1 10 ns 2 tRDS 15 ns tRDH 0 ns tWRD1 10 ns 3 tWDD1 10 ns tWDD2 0 10 ns tWDH 0 ns 3) 2.0 V single power source Item Address delay time #CEx delay time (1) #CEx delay time (2) Wait setup time Wait hold time Read signal delay time (1) Read data setup time Read data hold time Write signal delay time (1) Write data delay time (1) Write data delay time (2) Write data hold time (Unless otherwise specified: VDDE=VDD=2.0V0.2V, VSS=0V, Ta=-40C to +85C) Symbol Min. Max. Unit tAD - 20 ns 1 tCE1 - 20 ns tCE2 - 20 ns tWTS 40 - ns tWTH 0 - ns tRDD1 20 ns 2 tRDS 40 ns tRDH 0 ns tWRD1 20 ns 3 tWDD1 20 ns tWDD2 0 20 ns tWDH 0 ns note 1) This applies to the #BSH and #BSL timings. 2) This applies to the #GAAS and #GARD timings. 3) This applies to the #GAAS timing. A-80 EPSON S1C33L03 PRODUCT PART 8 ELECTRICAL CHARACTERISTICS A-1 SRAM read cycle 1) 3.3 V/5.0 V dual power source (Unless otherwise specified: VDDE=5.0V0.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40C to +85C) Symbol Min. Max. Unit Read signal delay time (2) tRDD2 8 ns Read signal pulse width tRDW tCYC(0.5+WC)-8 ns Read address access time (1) tACC1 tCYC(1+WC)-20 ns Chip enable access time (1) tCEAC1 tCYC(1+WC)-20 ns Read signal access time (1) tRDAC1 tCYC(0.5+WC)-20 ns Item 2) 3.3 V single power source (Unless otherwise specified: VDDE=VDD=2.7V to 3.6V, VSS=0V, Ta=-40C to +85C) Symbol Min. Max. Unit Read signal delay time (2) tRDD2 10 ns Read signal pulse width tRDW tCYC(0.5+WC)-10 ns Read address access time (1) tACC1 tCYC(1+WC)-25 ns Chip enable access time (1) tCEAC1 tCYC(1+WC)-25 ns Read signal access time (1) tRDAC1 tCYC(0.5+WC)-25 ns Item 3) 2.0 V single power source Item Read signal delay time (2) Read signal pulse width Read address access time (1) Chip enable access time (1) Read signal access time (1) (Unless otherwise specified: VDDE=VDD=2.0V0.2V, VSS=0V, Ta=-40C to +85C) Symbol Min. Max. Unit tRDD2 10 ns tRDW tCYC(0.5+WC)-10 ns tACC1 tCYC(1+WC)-60 ns tCEAC1 tCYC(1+WC)-60 ns tRDAC1 tCYC(0.5+WC)-60 ns SRAM write cycle 1) 3.3 V/5.0 V dual power source (Unless otherwise specified: VDDE=5.0V0.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40C to +85C) Symbol Min. Max. Unit Write signal delay time (2) tWRD2 8 ns Write signal pulse width tWRW tCYC(1+WC)-10 ns Item 2) 3.3 V single power source Item Write signal delay time (2) Write signal pulse width (Unless otherwise specified: VDDE=VDD=2.7V to 3.6V, VSS=0V, Ta=-40C to +85C) Symbol Min. Max. Unit tWRD2 10 ns tWRW tCYC(1+WC)-10 ns 3) 2.0 V single power source Item Write signal delay time (2) Write signal pulse width S1C33L03 PRODUCT PART (Unless otherwise specified: VDDE=VDD=2.0V0.2V, VSS=0V, Ta=-40C to +85C) Symbol Min. Max. Unit tWRD2 20 ns tWRW tCYC(1+WC)-20 ns EPSON A-81 A-8 8 ELECTRICAL CHARACTERISTICS DRAM access cycle common characteristics 1) 3.3 V/5.0 V dual power source (Unless otherwise specified: VDDE=5.0V0.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40C to +85C) Symbol Min. Max. Unit #RAS signal delay time (1) tRASD1 10 ns #RAS signal delay time (2) tRASD2 10 ns #RAS signal pulse width tRASW tCYC(2+WC)-10 ns #CAS signal delay time (1) tCASD1 10 ns #CAS signal delay time (2) tCASD2 10 ns #CAS signal pulse width tCASW tCYC(0.5+WC)-5 ns Read signal delay time (3) tRDD3 10 ns Read signal pulse width (2) tRDW2 tCYC(2+WC)-10 ns Write signal delay time (3) tWRD3 10 ns Write signal pulse width (2) tWRW2 tCYC(2+WC)-10 ns Item 2) 3.3 V single power source Item #RAS signal delay time (1) #RAS signal delay time (2) #RAS signal pulse width #CAS signal delay time (1) #CAS signal delay time (2) #CAS signal pulse width Read signal delay time (3) Read signal pulse width (2) Write signal delay time (3) Write signal pulse width (2) (Unless otherwise specified: VDDE=VDD=2.7V to 3.6V, VSS=0V, Ta=-40C to +85C) Symbol Min. Max. Unit tRASD1 10 ns tRASD2 10 ns tRASW tCYC(2+WC)-10 ns tCASD1 10 ns tCASD2 10 ns tCASW tCYC(0.5+WC)-10 ns tRDD3 10 ns tRDW2 tCYC(2+WC)-10 ns tWRD3 10 ns tWRW2 tCYC(2+WC)-10 ns 3) 2.0 V single power source Item #RAS signal delay time (1) #RAS signal delay time (2) #RAS signal pulse width #CAS signal delay time (1) #CAS signal delay time (2) #CAS signal pulse width Read signal delay time (3) Read signal pulse width (2) Write signal delay time (3) Write signal pulse width (2) A-82 (Unless otherwise specified: VDDE=VDD=2.0V0.2V, VSS=0V, Ta=-40C to +85C) Symbol Min. Max. Unit tRASD1 20 ns tRASD2 20 ns tRASW tCYC(2+WC)-20 ns tCASD1 20 ns tCASD2 20 ns tCASW tCYC(0.5+WC)-20 ns tRDD3 20 ns tRDW2 tCYC(2+WC)-20 ns tWRD3 20 ns tWRW2 tCYC(2+WC)-20 ns EPSON S1C33L03 PRODUCT PART 8 ELECTRICAL CHARACTERISTICS A-1 DRAM random access cycle and DRAM fast-page cycle 1) 3.3 V/5.0 V dual power source (Unless otherwise specified: VDDE=5.0V0.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40C to +85C) Symbol Min. Max. Unit Column address access time tACCF tCYC(1+WC)-25 ns #RAS access time tRACF tCYC(1.5+WC)-25 ns #CAS access time tCACF tCYC(0.5+WC)-25 ns Item 2) 3.3 V single power source Item Column address access time #RAS access time #CAS access time A-8 (Unless otherwise specified: VDDE=VDD=2.7V to 3.6V, VSS=0V, Ta=-40C to +85C) Symbol Min. Max. Unit tACCF tCYC(1+WC)-25 ns tRACF tCYC(1.5+WC)-25 ns tCACF tCYC(0.5+WC)-25 ns 3) 2.0 V single power source Item Column address access time #RAS access time #CAS access time (Unless otherwise specified: VDDE=VDD=2.0V0.2V, VSS=0V, Ta=-40C to +85C) Symbol Min. Max. Unit tACCF tCYC(1+WC)-60 ns tRACF tCYC(1.5+WC)-60 ns tCACF tCYC(0.5+WC)-60 ns EDO DRAM random access cycle and EDO DRAM page cycle 1) 3.3 V/5.0 V dual power source (Unless otherwise specified: VDDE=5.0V0.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40C to +85C) Symbol Min. Max. Unit Column address access time tACCE tCYC(1.5+WC)-25 ns #RAS access time tRACE tCYC(2+WC)-25 ns #CAS access time tCACE tCYC(1+WC)-15 ns Read data setup time tRDS2 20 ns Item 2) 3.3 V single power source Item Column address access time #RAS access time #CAS access time Read data setup time (Unless otherwise specified: VDDE=VDD=2.7V to 3.6V, VSS=0V, Ta=-40C to +85C) Symbol Min. Max. Unit tACCE tCYC(1.5+WC)-25 ns tRACE tCYC(2+WC)-25 ns tCACE tCYC(1+WC)-20 ns tRDS2 20 ns 3) 2.0 V single power source Item Column address access time #RAS access time #CAS access time Read data setup time S1C33L03 PRODUCT PART (Unless otherwise specified: VDDE=VDD=2.0V0.2V, VSS=0V, Ta=-40C to +85C) Symbol Min. Max. Unit tACCE tCYC(1.5+WC)-60 ns tRACE tCYC(2+WC)-60 ns tCACE tCYC(1+WC)-60 ns tRDS2 20 ns EPSON A-83 8 ELECTRICAL CHARACTERISTICS SDRAM access cycle 1) #X2SPD = "1" (CPU : SDRAM clock = 1 : 1), 3.3 V single power source (Unless otherwise specified: VDDE=VDD=3.0V to 3.6V, VSS=0V, Ta=-40C to +85C) Symbol Min. Max. Unit OSC3 input clock frequency fOSC3 25 MHz BCLK clock output cycle time t(C3) 40 ns Address delay time t(AD) 11 ns SDA10 delay time t(A10D) 11 ns #SDCEx delay time (1) t(CED)n 11 ns #SDCEx delay time (2) t(CED)p 11 ns #SDRAS signal delay time (1) t(RASD)n 12 ns #SDRAS signal delay time (2) t(RASD)p 11 ns #SDCAS signal delay time (1) t(CASD)n 11 ns #SDCAS signal delay time (2) t(CASD)p 11 ns HDQM, LDQM signal delay time (1) t(DQMD)n 11 ns HDQM, LDQM signal delay time (2) t(DQMD)p 11 ns SDCKE signal delay time (1) t(CKED)n 11 ns SDCKE signal delay time (2) t(CKED)p 11 ns #SDWE signal delay time (1) t(WED)n 11 ns #SDWE signal delay time (2) t(WED)p 11 ns Read data setup time t(RDS) (14) ns Read data hold time t(RDH) (0) ns Write data delay time t(WDD) 11 ns Write data hold time t(WDH) T+11 ns Item 2) #X2SPD = "0" (CPU : SDRAM clock = 2 : 1), 3.3 V single power source (Unless otherwise specified: VDDE=VDD=3.0V to 3.6V, VSS=0V, Ta=-40C to +85C) Symbol Min. Max. Unit OSC3 input clock frequency fOSC3 17.5 MHz BCLK clock output cycle time t(C3x2) 57 ns Address delay time t(ADx2) T+11 ns SDA10 delay time t(A10Dx2) T+11 ns #SDCEx delay time (1) t(CEDx2)n T+11 ns #SDCEx delay time (2) t(CEDx2)p T+11 ns #SDRAS signal delay time (1) t(RASDx2)n T+11 ns #SDRAS signal delay time (2) t(RASDx2)p T+11 ns #SDCAS signal delay time (1) t(CASDx2)n T+11 ns #SDCAS signal delay time (2) t(CASDx2)p T+11 ns HDQM, LDQM signal delay time (1) t(DQMDx2)n T+11 ns HDQM, LDQM signal delay time (2) t(DQMDx2)p T+11 ns SDCKE signal delay time (1) t(CKEDx2)n T+11 ns SDCKE signal delay time (2) t(CKEDx2)p T+11 ns #SDWE signal delay time (1) t(WEDx2)n T+11 ns #SDWE signal delay time (2) t(WEDx2)p T+11 ns Read data setup time t(RDSx2) (14) ns Read data hold time t(RDHx2) (0) ns Write data delay time t(WDDx2) 11 ns Write data hold time t(WDHx2) T+11 ns Item Note: "T" indicates one cycle time of the CPU clock. A-84 EPSON S1C33L03 PRODUCT PART 8 ELECTRICAL CHARACTERISTICS A-1 Burst ROM read cycle 1) 3.3 V/5.0 V dual power source (Unless otherwise specified: VDDE=5.0V0.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40C to +85C) Symbol Min. Max. Unit Read address access time (2) tACC2 tCYC(1+WC)-20 ns Chip enable access time (2) tCEAC2 tCYC(1+WC)-20 ns Read signal access time (2) tRDAC2 tCYC(0.5+WC)-20 ns Burst address access time tACCB tCYC(1+WC)-20 ns Item A-8 2) 3.3 V single power source (Unless otherwise specified: VDDE=VDD=2.7V to 3.6V, VSS=0V, Ta=-40C to +85C) Symbol Min. Max. Unit Read address access time (2) tACC2 tCYC(1+WC)-25 ns Chip enable access time (2) tCEAC2 tCYC(1+WC)-25 ns Read signal access time (2) tRDAC2 tCYC(0.5+WC)-25 ns Burst address access time tACCB tCYC(1+WC)-25 ns Item 3) 2.0 V single power source Item Read address access time (2) Chip enable access time (2) Read signal access time (2) Burst address access time (Unless otherwise specified: VDDE=VDD=2.0V0.2V, VSS=0V, Ta=-40C to +85C) Symbol Min. Max. Unit tACC2 tCYC(1+WC)-60 ns tCEAC2 tCYC(1+WC)-60 ns tRDAC2 tCYC(0.5+WC)-60 ns tACCB tCYC(1+WC)-60 ns External bus master and NMI 1) 3.3 V/5.0 V dual power source (Unless otherwise specified: VDDE=5.0V0.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40C to +85C) Symbol Min. Max. Unit #BUSREQ signal setup time tBRQS 15 ns #BUSREQ signal hold time tBRQH 0 ns #BUSACK signal output delay time tBAKD 10 ns High-impedance output delay time tZ2E 10 ns Output high-impedance delay time tB2Z 10 ns #NMI pulse width tNMIW 30 ns Item 2) 3.3 V single power source (Unless otherwise specified: VDDE=VDD=2.7V to 3.6V, VSS=0V, Ta=-40C to +85C) Symbol Min. Max. Unit #BUSREQ signal setup time tBRQS 15 ns #BUSREQ signal hold time tBRQH 0 ns #BUSACK signal output delay time tBAKD 10 ns High-impedance output delay time tZ2E 10 ns Output high-impedance delay time tB2Z 10 ns #NMI pulse width tNMIW 30 ns Item 3) 2.0 V single power source (Unless otherwise specified: VDDE=VDD=2.0V0.2V, VSS=0V, Ta=-40C to +85C) Symbol Min. Max. Unit #BUSREQ signal setup time tBRQS 40 ns #BUSREQ signal hold time tBRQH 0 ns #BUSACK signal output delay time tBAKD 20 ns High-impedance output delay time tZ2E 20 ns Output high-impedance delay time tB2Z 20 ns #NMI pulse width tNMIW 90 ns Item S1C33L03 PRODUCT PART EPSON A-85 8 ELECTRICAL CHARACTERISTICS Input, Output and I/O port 1) 3.3 V/5.0 V dual power source (Unless otherwise specified: VDDE=5.0V0.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40C to +85C) Symbol Min. Max. Unit Input data setup time tINPS 20 ns Input data hold time tINPH 10 ns Output data delay time tOUTD 20 ns K-port interrupt SLEEP, HALT2 mode tKINW 30 ns input pulse width Others 2 x tCYC ns Item 2) 3.3 V single power source (Unless otherwise specified: VDDE=VDD=2.7V to 3.6V, VSS=0V, Ta=-40C to +85C) Symbol Min. Max. Unit Input data setup time tINPS 20 ns Input data hold time tINPH 10 ns Output data delay time tOUTD 20 ns K-port interrupt SLEEP, HALT2 mode tKINW 30 ns input pulse width Others 2 x tCYC ns Item 3) 2.0 V single power source (Unless otherwise specified: VDDE=VDD=2.0V0.2V, VSS=0V, Ta=-40C to +85C) Symbol Min. Max. Unit Input data setup time tINPS 40 ns Input data hold time tINPH 20 ns Output data delay time tOUTD 30 ns K-port interrupt SLEEP, HALT2 mode tKINW 90 ns input pulse width Others 2 x tCYC ns Item A-86 EPSON S1C33L03 PRODUCT PART 8 ELECTRICAL CHARACTERISTICS A-1 8.6.4 C33 Block AC Characteristic Timing Charts Clock (1) When an external clock is input (in x1 speed mode): tC3 tC3H tC3ED = tC3H/tC3 OSC3 (High-speed clock) tIF tIR A-8 tC3 tCD1 tCD2 BCLK (Clock output) (2) When the high-speed oscillation circuit is used for the operating clock: tC3 tCBH tCBD = tCBH/tC3 BCLK (Clock output) S1C33L03 PRODUCT PART EPSON A-87 8 ELECTRICAL CHARACTERISTICS SRAM read cycle (basic cycle: 1 cycle) tC3 BCLK ;;;; ;;;; t tAD tAD A[23:0] tCE1 CE2 #CEx tRDD1 tRDD2 tRDW #RD tCEAC1 tACC1 ;;;;;;; ;;;;;;; t tRDAC1 D[15:0] 1 tRDH RDS ;;;;;; ;;;;;; #WAIT tWTS tWTH ;;;;;; ;;;;;; *1 tRDH is measured with respect to the first signal change (negation) from among the #RD, #CEx and A[23:0] signals. SRAM read cycle (when a wait cycle is inserted) C1 Cw(wait cycle) Cn(last cycle) BCLK ;;;; ;;;; t tAD tAD A[23:0] tCE1 CE2 #CEx tRDD1 (C1 only) tRDD2 tRDW #RD tCEAC1 tACC1 tRDAC1 D[15:0] tWTS #WAIT ;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;; tWTH tWTS tWTH tWTS ;;;;;;; ;;;;;;; tWTH tRDS tRDH 1 ;;;;;;;; ;;;;;;;; *1 tRDH is measured with respect to the first signal change (negation) from among the #RD, #CEx and A[23:0] signals. A-88 EPSON S1C33L03 PRODUCT PART 8 ELECTRICAL CHARACTERISTICS A-1 SRAM write cycle (basic cycle: 2 cycles) C1 C2 BCLK ;;;; ;;;; t tAD tAD A[23:0] tCE1 CE2 A-8 #CEx tWRD1 tWRD2 tWRW #WR tWDD1 tWDH D[15:0] t ;;;; ;;;; t ;;;;;; ;;;;;; WTS #WAIT WTH SRAM write cycle (when wait cycles are inserted) C1 Cw(wait cycle) Cw(wait cycle) Wait cycle follows Last cycle follows Cn(last cycle) BCLK ;;; ;;; t tAD tAD A[23:0] tCE1 CE2 #CEx tWRD1 tWRD2 tWRW #WR tWDD1 tWDH D[15:0] tWTS #WAIT S1C33L03 PRODUCT PART ;;;;; ;;;;; tWTH tWTS ;;;;; ;;;;; tWTH tWTS EPSON ;;;;;;;;;;;;;; ;;;;;;;;;;;;;; tWTH A-89 8 ELECTRICAL CHARACTERISTICS DRAM random access cycle (basic cycle) Data transfer #1 RAS1 Next data transfer CAS1 PRE1(precharge) RAS1' CAS1' BCLK tAD ;;;;;;;;; ;;;;;;;;; t tAD tAD A[23:0] tRASD1 RASD2 tRASW #RAS tCASD1 tCASD2 tCASW #HCAS/ #LCAS tRDD1 tRDD3 tRDW2 #RD tCACF tRACF tACCF tRDS tRDH 1 ;;;;;;;;;; ;;;;;;;;;; t D[15:0] ;;;;; ;;;;; t WRD1 ;;;;;;; ;;;;;;; WRD3 tWRW2 #WE ;;;;; ;;;;; tWDD1 tWDD2 D[15:0] 1 tRDH is measured with respect to the first signal change (negation) of either the #RD or the A[23:0] signals. DRAM fast-page access cycle Data transfer #1 RAS1 Data transfer #2 CAS1 CAS2 Next data transfer PRE1(precharge) RAS1' BCLK tAD tAD ;;;;;;;;; ;;;;;;;;; t tAD A[23:0] tRASD1 RASD2 tRASW #RAS tCASD1 tCASD2 tCASW #HCAS/ #LCAS tRDD1 tRDD3 tRDW2 #RD tCACF tACCF tRACF tACCF tRDS D[15:0] ;;;;;;;;;; ;;;;;;;;;; t WRD1 1 ;;;;; ;;;;; tRDH tRDS 1 ;;;;; ;;;;; t tRDH WRD3 ;;;;; ;;;;; tWRW2 #WE tWDD1 tWDD2 D[15:0] ;;;;; ;;;;; tWDD2 1 tRDH is measured with respect to the first signal change (negation) of either the #RD or the A[23:0] signals. A-90 EPSON S1C33L03 PRODUCT PART 8 ELECTRICAL CHARACTERISTICS A-1 EDO DRAM random access cycle (basic cycle) Data transfer #1 RAS1 Next data transfer CAS1 PRE1(precharge) RAS1' CAS1' BCLK tAD ;;;;;;;;; ;;;;;;;;; t tAD tAD A[23:0] tRASD1 RASD2 A-8 tRASW #RAS tCASD1 tCASD2 tCASW #HCAS/ #LCAS tRDD1 tRDD3 tRDW2 #RD tCACE tRACE tACCE tRDH 1 ;;;;;;;;;; ;;;;;;;;;; tRDS2 D[15:0] tWRD1 ;;; ;;; tWRD3 tWRW2 #WE ;;;;; ;;;;; tWDD1 tWDD2 D[15:0] 1 tRDH is measured with respect to the first signal change (negation) of either the #RD or the #RASx signals. EDO DRAM page access cycle Data transfer #1 RAS1 Data transfer #2 CAS1 CAS2 Next data transfer PRE1(precharge) RAS1' BCLK tAD tAD ;;;;;;;;; ;;;;;;;;; t tAD A[23:0] tRASD1 RASD2 tRASW #RAS tCASD1 tCASD2 tCASW #HCAS/ #LCAS tRDD1 tRDD3 tRDW2 #RD tACCE tCACE tRACE ;;;;;;;;;;;;;; ;;;;;;;;;;;;;; t tRDS tRDH tACCE D[15:0] WRD1 ;;;; ;;;; tRDS tRDH 1 ;;;; ;;;; tWRD3 ;;;;; ;;;;; tWRW2 #WE tWDD1 tWDD2 D[15:0] ;;;;; ;;;;; tWDD2 1 tRDH is measured with respect to the first signal change from among the #RD (negation), #RASx (negation) and #CAS (fall) signals. S1C33L03 PRODUCT PART EPSON A-91 8 ELECTRICAL CHARACTERISTICS DRAM CAS-before-RAS refresh cycle CBR refresh cycle CCBR1 CCBR2 CCBR3 BCLK ;;;;;;;; ;;;;;;;; #RAS tRASD1 tCASD1 tRASD2 tCASD2 ;;;;;; ;;;;;; #HCAS/ #LCAS #WE ;;;;;;;; ;;;;;;;; ;;;;;; ;;;;;; DRAM self-refresh cycle Self-refresh mode setup Self-refresh mode Self-refresh mode canceration 6-cycle precharge (Fixed) BCLK #RAS ;;;;;;; ;;;;;;; tRASD1 tCASD1 ;;;; ;;;; tRASD2 tCASD2 #HCAS/ #LCAS SDRAM clock (1) #X2SPD = high (CPU clock : SDRAM clock = 1 : 1) OSC3 (High-speed clock) tC3 tCBH tCBD = tCBH/tC3 BCLK (SDRAM clock output) (2) #X2SPD = low (CPU clock : SDRAM clock = 2 : 1) tC3 tCBH tCBD = tCBH/tC3 BCLK (SDRAM clock output) A-92 EPSON S1C33L03 PRODUCT PART 8 ELECTRICAL CHARACTERISTICS A-1 SDRAM access cycle Bank active Read/write nop nop Precharge BCLK SDCKE A[23:0] SDA10 H ;;; t ;;; ;;; t ;;; AD valid (Bank, Row) valid (Column) A10D valid valid tCED1 ;;;;;;;;;;;;; ;;;;;;;;;;;;; ;;;;;;;;;;;;; ;;;;;;;;;;;;; valid valid tCED2 ;;;; ;;;; ;;;; ;;;; A-8 #SDCEx tRASD1 tRASD2 #SDRAS tCASD1 tCASD2 #SDCAS tWED1 tWED2 #SDWE (read) D[15:0] t ;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;; RDS tRDH valid valid tDQMD1 HDQM/ LDQM tWED1 tDQMD2 ;;;; ;;;; tWED2 #SDWE (write) D[15:0] t ;;;;;; ;;;;;; ;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;; tWDH WDD valid Read: CAS latency = 2, burst length = 2 Write: single write SDRAM mode-register-set cycle Mode register set nop nop nop nop BCLK SDCKE A[23:0] SDA10 #SDCEx #SDRAS #SDCAS #SDWE D[15:0] HDQM/ LDQM H t ;;; ;;; t ;;; ;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;; t t ;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;; t t ;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;; t t ;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;; t t ;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; S1C33L03 PRODUCT PART AD valid AD valid CED1 CED2 RASD1 RASD2 CASD1 CASD2 WED1 WED2 EPSON A-93 8 ELECTRICAL CHARACTERISTICS SDRAM auto-refresh cycle Auto refresh nop nop nop nop BCLK SDCKE A[23:0] SDA10 #SDCEx #SDRAS #SDCAS #SDWE D[15:0] HDQM/ LDQM H ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; t t ;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;; t t ;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;; t t ;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;; t t ;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;; CED1 CED2 RASD1 RASD2 CASD1 CASD2 WED1 WED2 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; A precharge cycle is necessary before entering the auto refresh mode. SDRAM self-refresh cycle Enter self refresh mode BCLK tCKE1 ;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;; Exit self refresh mode tCKE2 SDCKE A[23:0] SDA10 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; t ;;;;;;;;;;;;;;;;;;; t ;;;;;;;;;;;;;;;;;;; t ;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;; t ;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;; t ;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; CED1 #SDCEx CED2 RASD1 #SDRAS CASD1 #SDCAS WED1 #SDWE D[15:0] HDQM/ LDQM A-94 A precharge cycle is necessary before entering the self refresh mode. EPSON S1C33L03 PRODUCT PART 8 ELECTRICAL CHARACTERISTICS A-1 Burst ROM read cycle SRAM read cycle Burst cycle Burst cycle Burst cycle BCLK tAD tAD A[23:2] tAD tAD tAD tAD tAD A[1:0] A-8 tCE1 tCE2 #CEx tRDD1 tRDD2 #RD tACC2 tCEAC tRDAC2 tRDS D[15:0] ;;;;; ;;;;; tACCB tACCB ;;;;; ;;;;; t tACCB ;;;;; ;;;;; t tRDS tRDS RDH RDH ;;;;; ;;;;; t tRDS RDH tRDH1 1 tRDH is measured with respect to the first signal change (negation) from among the #RD, #CEx and A[23:0] signals. #BUSREQ, #BUSACK and #NMI timing BCLK ;;; ;;; tBRQS #BUSREQ ;;;;; ;;;;; tBRQH Valid input tBAKD #BUSACK tZ2E eBUS_OUT signals 1 tB2Z eBUS_OUT signals 1 tNMIW #NMI 1 eBUS_OUT indicates the following pins: A[23:0], #RD, #WRL, #WRH, #HCAS, #LCAS, #CE[17:4], D[15:0] Input, output and I/O port timing BCLK ;;;; ;;;;Valid input ;;;;; ;;;;; tINPS Kxx, Pxx (input: data read from the port) tINPH tOUTD Pxx, Rxx (output) tKINW Kxx (K-port interrupt input) S1C33L03 PRODUCT PART EPSON A-95 8 ELECTRICAL CHARACTERISTICS 8.6.5 LCD Interface AC Characteristics Conditions: VDDE=3.3V10% or 5.0V10%, Ta=-40C to +85C, CL=60pF (LCD panel interface) Trise and Tfall for all inputs must be less than 5 ns (10%-90%). Power up/down timing LCDCEN bit LPWEREN bit LPSAVE[1:0] bits FP signals 00 11 Inactive Active 00 11 Inactive t1 t4 t2 t3 00 Active Inactive t1 t4 LCDPWR signal Symbol t1 t2 t3 t4 t5 t6 A-96 t6 t5 Parameter t6 Min. Power Save inactive to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY active FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY active to LCDPWR active Power Save active to LCDPWR inactive Power Save active to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY inactive LPWREN = "1" to LCDPWR active (when FP signals are active) LPWREN = "0" to LCDPWR inactive EPSON Typ. Max. Unit 1 Frame 0 Frame 1 1 Frame Frame 0 0 Frame Frame S1C33L03 PRODUCT PART 8 ELECTRICAL CHARACTERISTICS A-1 4-bit single monochrome panel timing VDP VNDP FPFRAME FPLINE DRDY (MOD) FPDAT[7:4] Line 1 Line 2 Line 3 Line 4 Line 239 Line 240 Line 1 Line 2 A-8 FPLINE DRDY (MOD) HDP HNDP FPSHIFT FPDAT7 1-1 1-5 1-317 FPDAT6 1-2 1-6 1-318 FPDAT5 1-3 1-7 1-319 FPDAT4 1-4 1-8 1-320 Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320 x 240 panel For this timing diagram FPSMASK (D2/0x39FFE1) is set to "1" VDP = Vertical Display Period = LDVSIZE[9:0] + 1 (lines) LDVSIZE[9:0] (0x39FFE5, D[1:0]/0x39FFE6) VNDP = Vertical Non-Display Period = VNDP[5:0] (lines) HDP = (LDHSIZE[5:0] + 1) x 16 (Ts) VNDP[5:0] (D[5:0]/0x39FFEA) = Horizontal Display Period LDHSIZE[5:0] (D[5:0]/0x39FFE4) HNDP = Horizontal Non-Display Period = (HNDP[4:0] + 4) x 8 (Ts) HNDP[4:0] (D[4:0]/0x39FFE7) S1C33L03 PRODUCT PART EPSON A-97 8 ELECTRICAL CHARACTERISTICS Sync Timing t1 t2 Frame Pulse t4 t3 Line Pulse t5 DRDY (MOD) Data Timing Line Pulse t6 t8 t7 t9 t14 t11 t10 Shift Pulse t12 FPDAT[7:4] Note: t13 1 2 For this timing diagram FPSMASK (D2/0x39FFE1) is set to "1". 4-bit Single Monochrome Panel AC Timing Symbol Parameter Min. t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Frame Pulse setup to Line Pulse falling edge Frame Pulse hold from Line Pulse falling edge Line Pulse period Line Pulse width MOD delay from Line Pulse rising edge Shift Pulse falling edge to Line Pulse rising edge Shift Pulse falling edge to Line Pulse falling edge Line Pulse falling edge to Shift Pulse falling edge Shift Pulse period Shift Pulse width low Shift Pulse width high FPDAT[7:4] setup to Shift Pulse falling edge FPDAT[7:4] hold from Shift Pulse falling edge Line Pulse falling edge to Shift Pulse rising edge note) 1.Ts = pixel clock period 2.t1min = t3min - 9 (Ts) 3.t3min = (LDHSIZE[5:0] + 1) x 16 + (HNDP[4:0] + 4) x 8 (Ts) 4.t6min = HNDP[4:0] x 8 + 2 (Ts) 5.t7min = HNDP[4:0] x 8 + 11 (Ts) A-98 EPSON Typ. Max. Unit note 2 (note 1) 9 Ts note 3 9 1 Ts Ts note 4 note 5 t14+2 4 2 2 2 2 23 Ts Ts Ts Ts Ts Ts Ts S1C33L03 PRODUCT PART 8 ELECTRICAL CHARACTERISTICS A-1 8-bit single monochrome panel timing VDP VNDP FPFRAME FPLINE DRDY (MOD) FPDAT[7:0] Line 1 Line 2 Line 3 Line 4 Line 479 Line 480 Line 1 Line 2 A-8 FPLINE DRDY (MOD) HDP HNDP FPSHIFT FPDAT7 1-1 1-9 1-633 FPDAT6 1-2 1-10 1-634 FPDAT5 1-3 1-11 1-635 FPDAT4 1-4 1-12 1-636 FPDAT3 1-5 1-13 1-637 FPDAT2 1-6 1-14 1-638 FPDAT1 1-7 1-15 1-639 FPDAT0 1-8 1-16 1-640 Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640 x 480 panel For this timing diagram FPSMASK (D2/0x39FFE1) is set to "1" VDP = Vertical Display Period = LDVSIZE[9:0] + 1 (lines) LDVSIZE[9:0] (0x39FFE5, D[1:0]/0x39FFE6) VNDP = Vertical Non-Display Period = VNDP[5:0] (lines) HDP = (LDHSIZE[5:0] + 1) x 16 (Ts) VNDP[5:0] (D[5:0]/0x39FFEA) = Horizontal Display Period LDHSIZE[5:0] (D[5:0]/0x39FFE4) HNDP = Horizontal Non-Display Period = (HNDP[4:0] + 4) x 8 (Ts) HNDP[4:0] (D[4:0]/0x39FFE7) S1C33L03 PRODUCT PART EPSON A-99 8 ELECTRICAL CHARACTERISTICS Sync Timing t1 t2 Frame Pulse t4 t3 Line Pulse t5 DRDY (MOD) Data Timing Line Pulse t6 t8 t7 t9 t14 t11 t10 Shift Pulse t12 FPDAT[7:0] Note: t13 1 2 For this timing diagram FPSMASK (D2/0x39FFE1) is set to "1". 8-bit Single Monochrome Panel AC Timing Symbol Parameter Min. t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Frame Pulse setup to Line Pulse falling edge Frame Pulse hold from Line Pulse falling edge Line Pulse period Line Pulse width MOD delay from Line Pulse rising edge Shift Pulse falling edge to Line Pulse rising edge Shift Pulse falling edge to Line Pulse falling edge Line Pulse falling edge to Shift Pulse falling edge Shift Pulse period Shift Pulse width low Shift Pulse width high FPDAT[7:0] setup to Shift Pulse falling edge FPDAT[7:0] hold from Shift Pulse falling edge Line Pulse falling edge to Shift Pulse rising edge note) 1.Ts = pixel clock period 2.t1min = t3min - 9 (Ts) 3.t3min = (LDHSIZE[5:0] + 1) x 16 + (HNDP[4:0] + 4) x 8 (Ts) 4.t6min = HNDP[4:0] x 8 + 4 (Ts) 5.t7min = HNDP[4:0] x 8 + 13 (Ts) A-100 EPSON Typ. Max. Unit note 2 (note 1) 9 Ts note 3 9 1 Ts Ts note 4 note 5 t14+4 8 4 4 4 4 23 Ts Ts Ts Ts Ts Ts Ts S1C33L03 PRODUCT PART 8 ELECTRICAL CHARACTERISTICS A-1 4-bit single color panel timing VDP VNDP FPFRAME FPLINE DRDY (MOD) FPDAT[7:4] Line 1 Line 2 Line 3 Line 4 Line 239 Line 240 Line 1 Line 2 A-8 FPLINE DRDY (MOD) HDP HNDP FPSHIFT FPDAT7 1-R1 1-G2 1-B3 1-B319 FPDAT6 1-G1 1-B2 1-R4 1-R320 FPDAT5 1-B1 1-R3 1-G4 1-G320 FPDAT4 1-R2 1-G3 1-B4 1-B320 Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320 x 240 panel VDP = Vertical Display Period = LDVSIZE[9:0] + 1 (lines) LDVSIZE[9:0] (0x39FFE5, D[1:0]/0x39FFE6) VNDP = Vertical Non-Display Period = VNDP[5:0] (lines) HDP = (LDHSIZE[5:0] + 1) x 16 (Ts) VNDP[5:0] (D[5:0]/0x39FFEA) = Horizontal Display Period LDHSIZE[5:0] (D[5:0]/0x39FFE4) HNDP = Horizontal Non-Display Period = (HNDP[4:0] + 4) x 8 (Ts) HNDP[4:0] (D[4:0]/0x39FFE7) S1C33L03 PRODUCT PART EPSON A-101 8 ELECTRICAL CHARACTERISTICS Sync Timing t1 t2 Frame Pulse t4 t3 Line Pulse t5 DRDY (MOD) Data Timing Line Pulse t6 t8 t7 t9 t14 t11 t10 Shift Pulse t12 FPDAT[7:4] t13 1 2 4-bit Single Color Panel AC Timing Symbol Parameter Min. t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Frame Pulse setup to Line Pulse falling edge Frame Pulse hold from Line Pulse falling edge Line Pulse period Line Pulse width MOD delay from Line Pulse rising edge Shift Pulse falling edge to Line Pulse rising edge Shift Pulse falling edge to Line Pulse falling edge Line Pulse falling edge to Shift Pulse falling edge Shift Pulse period Shift Pulse width low Shift Pulse width high FPDAT[7:4] setup to Shift Pulse falling edge FPDAT[7:4] hold from Shift Pulse falling edge Line Pulse falling edge to Shift Pulse rising edge note) 1.Ts = pixel clock period 2.t1min = t3min - 9 (Ts) 3.t3min = (LDHSIZE[5:0] + 1) x 16 + (HNDP[4:0] + 4) x 8 (Ts) 4.t6min = HNDP[4:0] x 8 + 1.5 (Ts) 5.t7min = HNDP[4:0] x 8 + 10.5 (Ts) A-102 EPSON Typ. Max. Unit note 2 (note 1) 9 Ts note 3 9 1 Ts Ts note 4 note 5 t14+0.5 1 0.5 0.5 1.5 1.5 24 Ts Ts Ts Ts Ts Ts Ts S1C33L03 PRODUCT PART 8 ELECTRICAL CHARACTERISTICS A-1 8-bit single color panel timing (Format 1) VDP VNDP FPFRAME FPLINE FPDAT[7:0] Line 1 Line 2 Line 3 Line 4 Line 479 Line 480 Line 1 Line 2 A-8 FPLINE FPSHIFT HDP HNDP FPSHIFT2 FPDAT7 1-R1 1-G1 1-G6 1-B6 1-B11 1-R12 1-R636 FPDAT6 1-B1 1-R2 1-R7 1-G7 1-G12 1-B12 1-B636 FPDAT5 1-G2 1-B2 1-B7 1-R8 1-R13 1-G13 1-G637 FPDAT4 1-R3 1-G3 1-G8 1-B8 1-B13 1-R14 1-R638 FPDAT3 1-B3 1-R4 1-R9 1-G9 1-G14 1-B14 1-B638 FPDAT2 1-G4 1-B4 1-B9 1-R10 1-R15 1-G15 1-G639 FPDAT1 1-R5 1-G5 1-G10 1-B10 1-B15 1-R16 1-R640 FPDAT0 1-B5 1-R6 1-R11 1-G11 1-G16 1-B16 1-B640 Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640 x 480 panel VDP = Vertical Display Period = LDVSIZE[9:0] + 1 (lines) LDVSIZE[9:0] (0x39FFE5, D[1:0]/0x39FFE6) VNDP = Vertical Non-Display Period = VNDP[5:0] (lines) HDP = (LDHSIZE[5:0] + 1) x 16 (Ts) VNDP[5:0] (D[5:0]/0x39FFEA) = Horizontal Display Period LDHSIZE[5:0] (D[5:0]/0x39FFE4) HNDP = Horizontal Non-Display Period = (HNDP[4:0] + 4) x 8 (Ts) HNDP[4:0] (D[4:0]/0x39FFE7) S1C33L03 PRODUCT PART EPSON A-103 8 ELECTRICAL CHARACTERISTICS Sync Timing t1 t2 Frame Pulse t4 t3 Line Pulse Data Timing Line Pulse t6a t6b t8 t7a t9 t14 t11 t10 Shift Pulse 2 t7b Shift Pulse t12 t13 t12 t13 FPDAT[7:0] 1 2 8-bit Single Color Panel AC Timing (Format 1) Symbol Parameter Min. t1 t2 t3 t4 t6a t6b t7a t7b t8 t9 t10 t11 t12 t13 t14 Frame Pulse setup to Line Pulse falling edge Frame Pulse hold from Line Pulse falling edge Line Pulse period Line Pulse width Shift Pulse falling edge to Line Pulse rising edge Shift Pulse 2 falling edge to Line Pulse rising edge Shift Pulse 2 falling edge to Line Pulse falling edge Shift Pulse falling edge to Line Pulse falling edge Line Pulse falling edge to Shift Pulse rising, Shift Pulse 2 falling edge Shift Pulse 2, Shift Pulse period Shift Pulse 2, Shift Pulse width low Shift Pulse 2, Shift Pulse width high FPDAT[7:0] setup to Shift Pulse 2, Shift Pulse falling edge FPDAT[7:0] hold from Shift Pulse 2, Shift Pulse falling edge Line Pulse falling edge to Shift Pulse 2 rising edge note) 1.Ts = pixel clock period 2.t1min = t3min - 9 (Ts) 3.t3min = (LDHSIZE[5:0] + 1) x 16 + (HNDP[4:0] + 4) x 8 + 1 (Ts) 4.t6amin = HNDP[4:0] x 8 + t13 - t10 + 1 (Ts) 5.t6bmin = HNDP[4:0] x 8 + t13 + 1 (Ts) 6.t7amin = HNDP[4:0] x 8 + 11 (Ts) 7.t7bmin = HNDP[4:0] x 8 + 11 - t10 (Ts) A-104 EPSON Typ. Max. Unit note 2 (note 1) 9 Ts note 3 9 Ts note 4 note 5 note 6 note 7 t14+2 4 2 2 1 1 23 Ts Ts Ts Ts Ts Ts Ts S1C33L03 PRODUCT PART 8 ELECTRICAL CHARACTERISTICS A-1 8-bit single color panel timing (Format 2) VDP VNDP FPFRAME FPLINE DRDY (MOD) FPDAT[7:0] Line 1 Line 2 Line 3 Line 4 Line 479 Line 480 Line 1 Line 2 A-8 FPLINE DRDY (MOD) HDP HNDP FPSHIFT FPDAT7 1-R1 1-B3 1-G6 1-G638 FPDAT6 1-G1 1-R4 1-B6 1-B638 FPDAT5 1-B1 1-G4 1-R7 1-R639 FPDAT4 1-R2 1-B4 1-G7 1-G639 FPDAT3 1-G2 1-R5 1-B7 1-B639 FPDAT2 1-B2 1-G5 1-R8 1-R640 FPDAT1 1-R3 1-B5 1-G8 1-G640 FPDAT0 1-G3 1-R6 1-B8 1-B640 Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640 x 480 panel VDP = Vertical Display Period = LDVSIZE[9:0] + 1 (lines) LDVSIZE[9:0] (0x39FFE5, D[1:0]/0x39FFE6) VNDP = Vertical Non-Display Period = VNDP[5:0] (lines) HDP = (LDHSIZE[5:0] + 1) x 16 (Ts) VNDP[5:0] (D[5:0]/0x39FFEA) = Horizontal Display Period LDHSIZE[5:0] (D[5:0]/0x39FFE4) HNDP = Horizontal Non-Display Period = (HNDP[4:0] + 4) x 8 (Ts) HNDP[4:0] (D[4:0]/0x39FFE7) S1C33L03 PRODUCT PART EPSON A-105 8 ELECTRICAL CHARACTERISTICS Sync Timing t1 t2 Frame Pulse t4 t3 Line Pulse t5 DRDY (MOD) Data Timing Line Pulse t6 t8 t7 t9 t14 t11 t10 Shift Pulse t12 FPDAT[7:0] t13 1 2 8-bit Single Color Panel AC Timing (Format 2) Symbol Parameter Min. t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Frame Pulse setup to Line Pulse falling edge Frame Pulse hold from Line Pulse falling edge Line Pulse period Line Pulse width MOD delay from Line Pulse rising edge Shift Pulse falling edge to Line Pulse rising edge Shift Pulse falling edge to Line Pulse falling edge Line Pulse falling edge to Shift Pulse falling edge Shift Pulse period Shift Pulse width low Shift Pulse width high FPDAT[7:0] setup to Shift Pulse falling edge FPDAT[7:0] hold from Shift Pulse falling edge Line Pulse falling edge to Shift Pulse rising edge note) 1.Ts = pixel clock period 2.t1min = t3min - 9 (Ts) 3.t3min = (LDHSIZE[5:0] + 1) x 16 + (HNDP[4:0] + 4) x 8 + 1 (Ts) 4.t6min = HNDP[4:0] x 8 + 1 (Ts) 5.t7min = HNDP[4:0] x 8 + 10 (Ts) A-106 EPSON Typ. Max. Unit note 2 (note 1) 9 Ts note 3 9 1 Ts Ts note 4 note 5 t14+2 2 1 1 1 1 23 Ts Ts Ts Ts Ts Ts Ts S1C33L03 PRODUCT PART 8 ELECTRICAL CHARACTERISTICS A-1 8.7 Oscillation Characteristics Oscillation characteristics change depending on conditions (board pattern, components used, etc.). Use the following characteristics as reference values. In particular, when a ceramic or crystal oscillator is used, use the oscillator manufacturer recommended values for constants such as capacitance and resistance. OSC1 crystal oscillation (Unless otherwise specified: crystal=Q11C02RX#1 32.768kHz, Rf1=20M, CG1=CD1=15pF#2) Symbol Condition Min. Typ. Max. Unit Operating temperature Ta VDD=2.7V to 3.6V -40 85 C VDD=1.9V to 2.2V -40 85 C VDD=1.8V to 2.2V 0 70 C #1 Q11C02RX: Crystal resonator made by Seiko Epson #2 "CG1=CD1=15pF" includes board capacitance. Item (Unless otherwise specified: VDD=3.3V, VSS=0V, crystal=Q11C02RX#1 32.768kHz, Rf1=20M, CG1=CD1=15pF#2, Ta=25C) Item Symbol Condition Min. Typ. Max. Unit Oscillation start time tSTA1 3 s External gate/drain capacitance CG1, CD1 CG1=CD1, 5 25 pF including board capacitance Frequency/IC deviation f/IC -10 10 ppm Frequency/power voltage deviation f/V -10 10 ppm/V Frequency adjustment range f/CG CG1=CD1= 5 to 25pF 50 ppm #1 Q11C02RX: Crystal resonator made by Seiko Epson #2 "CG1=CD1=15pF" includes board capacitance. (Unless otherwise specified: VDD=2.0V, VSS=0V, crystal=Q11C02RX#1 32.768kHz, Rf1=20M, CG1=CD1=15pF#2, Ta=25C) Item Symbol Condition Min. Typ. Max. Unit Oscillation start time tSTA1 20 s External gate/drain capacitance CG1, CD1 CG1=CD1, 5 25 pF including board capacitance Frequency/IC deviation f/IC -10 10 ppm Frequency/power voltage deviation f/V -10 10 ppm/V Frequency adjustment range f/CG CG1=CD1= 5 to 25pF 50 ppm #1 Q11C02RX: Crystal resonator made by Seiko Epson #2 "CG1=CD1=15pF" includes board capacitance. OSC3 crystal oscillation Note: A "crystal resonator that uses a fundamental" should be used for the OSC3 crystal oscillation circuit. (Unless otherwise specified: VSS=0V, crystal=Q22MA306#1 33.8688MHz, Rf2=1M, CG1=CD1=15pF#2, Ta=25C) Item Symbol Condition Min. Typ. Max. Unit Oscillation start time tSTA3 VDD=3.3V 10 ms VDD=2.0V 25 ms #1 Q22MA306: Crystal resonator made by Seiko Epson #2 "CG1=CD1=15pF" includes board capacitance. S1C33L03 PRODUCT PART EPSON A-107 A-8 8 ELECTRICAL CHARACTERISTICS OSC3 ceramic oscillation Item Symbol tSTA3 Oscillation start time (Unless otherwise specified: VSS=0V, Ta=25C) Min. Typ. Max. Unit 10MHz ceramic oscillator 10 ms 1 16MHz ceramic oscillator 10 ms 2 20MHz ceramic oscillator 10 ms 3 25MHz ceramic oscillator 5 ms 4 33MHz ceramic oscillator 5 ms 5 Condition note) No. 1 2 3 4 5 1 Ceramic Recommended constants Power voltage oscillator CG2 (pF) CD2 (pF) Rf2 (M) range (V) CST10.0MTW 30 30 1 1.8 to 2.2 CST16.00MXW0C1 5 5 1 1.8 to 2.2 CST20.00MXW0H1 5 5 1 1.8 to 2.2 CST25.00MXW0H1 5 5 1 2.7 to 3.6 CST33.00MXZ040 Open Open 1 2.7 to 3.6 This oscillator has a tendency to rise to the frequency of 0.3%. Remarks (Manufacturer) (Murata Mfg. corporation) 1 (Murata Mfg. corporation) (Murata Mfg. corporation) (Murata Mfg. corporation) (Murata Mfg. corporation) 8.8 PLL Characteristics Setting the PLLS0 and PLLS1 pins (recommended operating condition) VDD=2.7V to 3.6V PLLS1 PLLS0 Mode Fin (OSC3 clock) Fout 1 0 0 1 1 0 x2 x4 PLL not used 10 to 25MHz 10 to 12.5MHz - 20 to 50MHz 40 to 50MHz - PLLS1 PLLS0 Mode Fin (OSC3 clock) Fout 1 0 1 0 x2 PLL not used 10MHz - 20MHz - VDD=2.0V0.2V PLL characteristics (Unless otherwise specified: VDD=2.7V to 3.6V, VSS=0V, crystal oscillator=Q3204DC#1, R1=4.7k, C1=100pF, C2=5pF, Ta=-40C to +85C) Item Symbol Condition Min. Typ. Max. Unit Jitter (peak jitter) tpj -1 1 ns Lockup time tpll 1 ms #1 Q3204DC: Crystal oscillator made by Seiko Epson (Unless otherwise specified: VDD=2.0V0.2V, VSS=0V, crystal oscillator=Q3204DC#1, R1=4.7k, C1=100pF, C2=5pF, Ta=-40C to +85C) Item Symbol Condition Min. Typ. Max. Unit Jitter (peak jitter) tpj -2 2 ns Lockup time tpll 2 ms #1 Q3204DC: Crystal oscillator made by Seiko Epson A-108 EPSON S1C33L03 PRODUCT PART 9 PACKAGE A-1 9 Package 9.1 Plastic Package QFP20-144pin (Unit: mm) 220.4 200.1 108 A-9 73 200.1 220.4 72 109 INDEX 37 144 1 +0.1 36 1.40.1 0.2 -0.05 +0.05 0.125-0.025 0 10 0.50.2 0.1 1.7max 0.5 1 Limit of power consumption The chip temperature of an LSI rises according to power consumption. The chip temperature can be calculated from environment temperature (Ta), thermal package resistance () and power consumption (PD). Chip temperature (Tj) = Ta + (PD x ) (C) As a guide, normally keep the chip temperature (Tj) lower than 85C. The thermal resistance of the QFP20-144pin package is as follows: Thermal resistance (C/W) = 110 to 120C (90 to 100C for Cu lead frame) This thermal resistance is a value under the condition that the measured device is hanging in the air and has no air-cooling. Thermal resistance greatly varies according to the mounting condition on the board and aircooling condition. S1C33L03 PRODUCT PART EPSON A-109 10 PAD LAYOUT 10 Pad Layout 10.1 Pad Layout Diagram Die No. 120 115 110 105 100 95 90 85 80 125 75 130 70 135 65 140 X (0, 0) 60 145 5.38 mm Y 55 150 50 155 45 160 1 5 10 15 20 25 30 35 40 5.97 mm A-110 EPSON S1C33L03 PRODUCT PART 10 PAD LAYOUT A-1 10.2 Pad Coordinate (Unit: m) No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Pad name P22/TM0 N.C. P23/TM1 N.C. VSS N.C. P24/TM2/#SRDY2 N.C. P25/TM3/#SCLK2 P26/TM4/SOUT2 P27/TM5/SIN2 VDD P07/#SRDY1/#DMAEND3 P06/#SCLK1/#DMAACK3 P05/SOUT1/#DMAEND2 P04/SIN1/#DMAACK2 FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT3/GPO6 FPDAT2/GPO5 FPDAT1/GPO4 FPDAT0/GPO3 VDDE DRDY(MOD/FPSHIFT2) FPFRAME FPLINE FPSHIFT N.C. LCDPWR N.C. VSS K67/AD7 K66/AD6 K65/AD5 K64/AD4 K63/AD3 K62/AD2 N.C. K61/AD1 K60/AD0 AVDDE K54/#DMAREQ3 K53/#DMAREQ2 K52/#ADTRG K51/#DMAREQ1 K50/#DMAREQ0 #WRH/#BSH #WRL/#WR/#WE S1C33L03 PRODUCT PART X -2310.0 -2200.0 -2090.0 -1980.0 -1870.0 -1760.0 -1650.0 -1540.0 -1430.0 -1320.0 -1210.0 -1100.0 -990.0 -880.0 -770.0 -660.0 -550.0 -440.0 -330.0 -220.0 -110.0 0.0 110.0 220.0 330.0 440.0 550.0 660.0 770.0 880.0 990.0 1100.0 1210.0 1320.0 1430.0 1540.0 1650.0 1760.0 1870.0 1980.0 2090.0 2200.0 2310.0 2843.5 2843.5 2843.5 2843.5 2843.5 2843.5 2843.5 Y No. -2549.5 51 -2549.5 52 -2549.5 53 -2549.5 54 -2549.5 55 -2549.5 56 -2549.5 57 -2549.5 58 -2549.5 59 -2549.5 60 -2549.5 61 -2549.5 62 -2549.5 63 -2549.5 64 -2549.5 65 -2549.5 66 -2549.5 67 -2549.5 68 -2549.5 69 -2549.5 70 -2549.5 71 -2549.5 72 -2549.5 73 -2549.5 74 -2549.5 75 -2549.5 76 -2549.5 77 -2549.5 78 -2549.5 79 -2549.5 80 -2549.5 81 -2549.5 82 -2549.5 83 -2549.5 84 -2549.5 85 -2549.5 86 -2549.5 87 -2549.5 88 -2549.5 89 -2549.5 90 -2549.5 91 -2549.5 92 -2549.5 93 -1980.0 94 -1870.0 95 -1760.0 96 -1650.0 97 -1540.0 98 -1430.0 99 -1320.0 100 Pad name #RD VSS D15 D14 D13 D12 D11 VDD D10 D9 D8 D7 D6 D5 D4 VDDE D3 D2 D1 D0 #CE8/#RAS1/#CE14/#RAS3/#SDCE1 #CE7/#RAS0/#CE13/#RAS2/#SDCE0 VSS OSC2 OSC1 #RESET P35/#BUSACK/GPIO1 N.C. P34/#BUSREQ/#CE6/GPIO0 P33/#DMAACK1/SIN3/SDA10 P32/#DMAACK0/#SRDY3/HDQM N.C. P31/#BUSGET/#GARD/GPIO2 N.C. P30/#WAIT/#CE4&5 N.C. #LCAS/#SDRAS N.C. #HCAS/#SDCAS VDD P21/#DWE/#GAAS/#SDWE P20/#DRD/SDCKE BCLK/SDCLK VSS P16/EXCL5/#DMAEND1/SOUT3 P15/EXCL4/#DMAEND0/#SCLK3/LDQM A0/#BSL A1/SDA0 A2/SDA1 A3/SDA2 EPSON X 2843.5 2843.5 2843.5 2843.5 2843.5 2843.5 2843.5 2843.5 2843.5 2843.5 2843.5 2843.5 2843.5 2843.5 2843.5 2843.5 2843.5 2843.5 2843.5 2843.5 2843.5 2843.5 2843.5 2843.5 2843.5 2843.5 2843.5 2843.5 2843.5 2843.5 2310.0 2200.0 2090.0 1980.0 1870.0 1760.0 1650.0 1540.0 1430.0 1320.0 1210.0 1100.0 990.0 880.0 770.0 660.0 550.0 440.0 330.0 220.0 Y -1210.0 -1100.0 -990.0 -880.0 -770.0 -660.0 -550.0 -440.0 -330.0 -220.0 -110.0 0.0 110.0 220.0 330.0 440.0 550.0 660.0 770.0 880.0 990.0 1100.0 1210.0 1320.0 1430.0 1540.0 1650.0 1760.0 1870.0 1980.0 2549.5 2549.5 2549.5 2549.5 2549.5 2549.5 2549.5 2549.5 2549.5 2549.5 2549.5 2549.5 2549.5 2549.5 2549.5 2549.5 2549.5 2549.5 2549.5 2549.5 A-111 A-10 10 PAD LAYOUT No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 A-112 Pad name A4/SDA3 A5/SDA4 VDDE A6/SDA5 A7/SDA6 A8/SDA7 A9/SDA8 A10/SDA9 A11 VSS A12/SDA11 A13/SDA12 A14/SDBA0 A15/SDBA1 A16 A17 VSS N.C. A18 N.C. A19 N.C. A20 A21 A22 A23 PLLS1 PLLS0 VSS PLLC X 110.0 0.0 -110.0 -220.0 -330.0 -440.0 -550.0 -660.0 -770.0 -880.0 -990.0 -1100.0 -1210.0 -1320.0 -1430.0 -1540.0 -1650.0 -1760.0 -1870.0 -1980.0 -2090.0 -2200.0 -2310.0 -2843.5 -2843.5 -2843.5 -2843.5 -2843.5 -2843.5 -2843.5 Y No. 2549.5 2549.5 2549.5 2549.5 2549.5 2549.5 2549.5 2549.5 2549.5 2549.5 2549.5 2549.5 2549.5 2549.5 2549.5 2549.5 2549.5 2549.5 2549.5 2549.5 2549.5 2549.5 2549.5 1980.0 1870.0 1760.0 1650.0 1540.0 1430.0 1320.0 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 EPSON Pad name VSS DSIO P14/FOSC1/DCLK P13/EXCL3/T8UF3/DPCO P12/EXCL2/T8UF2/DST2 P11/EXCL1/T8UF1/DST1 P10/EXCL0/T8UF0/DST0 EA10MD1 EA10MD0 ICEMD #EMEMRD VDD OSC4 OSC3 #NMI #CE9/#CE17/#CE17&18 VDDE #CE5/#CE15/#CE15&16 N.C. #CE3 VSS #CE10EX/#CE9&10EX #CE6/#CE7&8 #CE4/#CE11/#CE11&12 #X2SPD P03/#SRDY0 P02/#SCLK0 N.C. P01/SOUT0 P00/SIN0 X -2843.5 -2843.5 -2843.5 -2843.5 -2843.5 -2843.5 -2843.5 -2843.5 -2843.5 -2843.5 -2843.5 -2843.5 -2843.5 -2843.5 -2843.5 -2843.5 -2843.5 -2843.5 -2843.5 -2843.5 -2843.5 -2843.5 -2843.5 -2843.5 -2843.5 -2843.5 -2843.5 -2843.5 -2843.5 -2843.5 Y 1210.0 1100.0 990.0 880.0 770.0 660.0 550.0 440.0 330.0 220.0 110.0 0.0 -110.0 -220.0 -330.0 -440.0 -550.0 -660.0 -770.0 -880.0 -990.0 -1100.0 -1210.0 -1320.0 -1430.0 -1540.0 -1650.0 -1760.0 -1870.0 -1980.0 S1C33L03 PRODUCT PART APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS A-1 Appendix A <Reference> External Device Interface Timings This section shows setup examples for setting timing conditions of the external system interface as a reference material used when configuring a system with external devices. Pay attention to the following precautions when using this material. * The described AC characteristic values of external devices are standard values. They may differ from those of the devices actually used, so the actual setup values (number of cycles) should be determined by referring the manual or specification of the device to be used. * It is necessary to set the timing values allowing ample margin according to the load capacitance of the bus and signal lines, number of devices to be connected, operating temperature range, I/O levels and other conditions. The number of cycles described in this section is an example and the conditions are not considered. * The values described in "Time" column of the tables are simply calculated by multiplying the number of cycles by the cycle time. Conditions such as the output delay time of the device, delay due to wiring and load capacitance, and input setup time are not considered. * The described contents are reference data and cannot be guaranteed to work. S1C33L03 PRODUCT PART EPSON A-113 A-ap APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS A.1 DRAM (70ns) DRAM interface setup examples - 70ns Operating frequency RAS precharge cycle RAS cycle CAS cycle Refresh RAS pulse width Refresh RPC delay 20MHz 25MHz 33MHz 2 2 2 1 1 2 2 2 3 2 2 3 1 1 1 DRAM interface timing - 70ns DRAM interface Parameter Unit: ns Min. Max. tRC tRP tRAS tCAS tASR tRAH tASC tRCD tRAD 130 50 70 20 0 10 0 20 15 - - 10000 10000 - - - - - 7 2 5 2.5 0.5 1.5 0.5 2.0 1.5 210 60 150 75 15 45 15 60 45 5 2 3 1.5 0.5 0.5 0.5 1.0 0.5 200 80 120 60 20 20 20 40 20 5 2 3 1.5 0.5 0.5 0.5 1.0 0.5 250 100 150 75 25 25 25 50 25 tRAC tCAC tAA tOAC tOFF - - - - 0 70 20 35 20 20 4.5 2.5 3.0 4.5 2 135 75 90 135 60 2.5 1.5 2.0 2.5 2 100 60 80 100 80 2.5 1.5 2.0 2.5 2 125 75 100 125 100 tDH 15 - 2.5 75 1.5 60 1.5 75 tPC tCP tACP 45 10 - - - 40 3.0 0.5 3.0 90 15 90 2.0 0.5 2.0 80 20 80 2.0 0.5 2.0 100 25 100 tCSR tCHR tPPC tRAS 10 10 10 70 - - - 10000 1.0 2.5 1.0 3.0 30 75 30 90 1.0 1.5 1.0 2.0 40 60 40 80 1.0 1.5 1.0 2.0 50 75 50 100 Symbol 33MHz Cycle Time 25MHz Cycle Time 20MHz Cycle Time <Common parameters> Random read/random write cycle time #RAS precharge time #RAS pulse width #CAS pulse width Row address setup time Row address hold time Column address setup time #RAS#CAS delay time #RAScolumn address delay time <Read-cycle parameters> #RAS access time #CAS access time Address access time #OE access time Output buffer turn-off time <Write-cycle parameters> Data input hold time <Fast-page mode> Fast-page mode cycle time Fast-page mode #CAS precharge time Access time after #CAS precharge <Refresh cycle> #CAS setup time #CAS hold time #RAS precharge#CAS hold time #RAS pulse width (only in refresh cycle) A-114 EPSON S1C33L03 PRODUCT PART APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS A-1 DRAM: 70ns, CPU: 33MHz, random read/write cycle tRC RAS cycle CAS cycle RAS precharge 2 3 2 ROW #1 COL #1 ;;;;;;;;; ;;;;;;;;; BCLK A[11:0] tRAD tRAH tASC tRAS tASR ROW #2 tRP #RAS tRCD tCAS A-ap #CAS #RD tRAC tOAC tAA tCAC tOFF ;;;;;;;;; ;;;;;;;;; t D[15:0](RD) RD data ;;;; ;;;; WP #WE tDS tDH D[15:0](WR) ;;; ;;; WR data DRAM: 70ns, CPU: 33MHz, page-mode read/write cycle tPC RAS cycle CAS cycle CAS cycle RAS precharge 2 3 3 2 ROW #1 COL #1 COL #2 ;;;;;; ;;;;;; BCLK A[11:0] tRAS #RAS tCP #CAS #RD ;;;;;;;;; ;;;;;;;;; D[15:0](RD) RD data #WE D[15:0](WR) tACP ;;;;;;;;; ;;;;;;;;; WR data RD data WR data ;;; ;;; DRAM: 70ns, CPU: 33MHz, CAS-before-RAS refresh cycle RPC delay Fixed Refresh RAS pulse width RAS precharge 1 1 3 2 BCLK tRAS #RAS tRPC tCSR tCHR #CAS S1C33L03 PRODUCT PART EPSON A-115 APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS DRAM: 70ns, CPU: 25/20MHz, random read/write cycle RAS cycle CAS cycle RAS precharge 1 2 2 COL #1 ;;;;;;;;; ;;;;;;;;; BCLK A[11:0] ROW #1 ROW #2 tRAS #RAS #CAS #RD ;;;;; ;;;;; D[15:0](RD) ;; ;; RD data #WE D[15:0](WR) ;;; ;;; WR data DRAM: 70ns, CPU: 25/20MHz, page-mode read/write cycle RAS cycle CAS cycle CAS cycle RAS precharge 1 2 2 2 COL #2 ;;;;;;;;; ;;;;;;;;; BCLK A[11:0] ROW #1 COL #1 tRAS #RAS #CAS #RD ;;;;; ;;;;; D[15:0](RD) ;;;;; ;;;;; RD data #WE D[15:0](WR) RD data WR data ;;; ;;; WR data DRAM: 70ns, CPU: 25/20MHz, CAS-before-RAS refresh cycle RPC delay Fixed Refresh RAS pulse width RAS precharge 1 1 2 2 BCLK tRAS #RAS tRPC tCSR tCHR #CAS A-116 EPSON S1C33L03 PRODUCT PART APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS A-1 A.2 DRAM (60ns) DRAM interface setup examples - 60ns Operating frequency RAS precharge cycle RAS cycle CAS cycle 20MHz 25MHz 33MHz 1 2 2 1 1 2 2 2 2 Refresh RAS pulse Refresh RPC delay width 2 2 3 1 1 1 DRAM interface timing - 60ns DRAM interface Parameter Unit: ns Min. Max. tRC tRP tRAS tCAS tASR tRAH tASC tRCD tRAD 110 40 60 15 0 10 0 20 15 - - 10000 10000 - - - - - 6 2 4 1.5 0.5 1.5 0.5 2.0 1.5 180 60 120 45 15 45 15 60 45 5 2 3 1.5 0.5 0.5 0.5 1.0 0.5 200 80 120 60 20 20 20 40 20 4 1 3 1.5 0.5 0.5 0.5 1.0 0.5 200 50 150 75 25 25 25 50 25 tRAC tCAC tAA tOAC tOFF - - - - 0 60 15 30 15 15 3.5 1.5 2.0 3.5 2 105 45 60 105 60 2.5 1.5 2.0 2.5 2 100 60 80 100 80 2.5 1.5 2.0 2.5 1 125 75 100 125 50 tDH 10 - 1.5 45 1.5 60 1.5 75 tPC tCP tACP 40 10 - - - 35 2.0 0.5 2.0 60 15 60 2.0 0.5 2.0 80 20 80 2.0 0.5 2.0 100 25 100 tCSR tCHR tPPC tRAS 10 10 10 60 - - - 10000 1.0 2.5 1.0 3.0 30 75 30 90 1.0 1.5 1.0 2.0 40 60 40 80 1.0 1.5 1.0 2.0 50 75 50 100 Symbol 33MHz Cycle Time 25MHz Cycle Time 20MHz Cycle Time A-ap <Common parameters> Random read/random write cycle time #RAS precharge time #RAS pulse width #CAS pulse width Row address setup time Row address hold time Column address setup time #RAS#CAS delay time #RAScolumn address delay time <Read-cycle parameters> #RAS access time #CAS access time Address access time #OE access time Output buffer turn-off time <Write-cycle parameters> Data input hold time <Fast-page mode> Fast-page mode cycle time Fast-page mode #CAS precharge time Access time after #CAS precharge <Refresh cycle> #CAS setup time #CAS hold time #RAS precharge#CAS hold time #RAS pulse width (only in refresh cycle) S1C33L03 PRODUCT PART EPSON A-117 APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS DRAM: 60ns, CPU: 33MHz, random read/write cycle tRC RAS cycle CAS cycle RAS precharge 2 2 2 ROW #1 COL #1 ;;;;;;;;; ;;;;;;;;; BCLK A[11:0] tRAD tRAH tASC tRAS tASR ROW #2 tRP #RAS tRCD tCAS #CAS #RD tRAC tOAC tAA tCAC tOFF ;;;;; ;;;;; t D[15:0](RD) RD data ;;;; ;;;; WP #WE tDS D[15:0](WR) tDH WR data ;;; ;;; DRAM: 60ns, CPU: 33MHz, page-mode read/write cycle tPC RAS cycle CAS cycle CAS cycle RAS precharge 2 2 2 2 ROW #1 COL #1 BCLK A[11:0] ;;;;;; ;;;;;; COL #2 tRAS #RAS tCP #CAS #RD ;;;;; ;;;;; D[15:0](RD) RD data #WE D[15:0](WR) WR data tACP ;;;;; ;;;;; RD data ;;; ;;; WR data DRAM: 60ns, CPU: 33MHz, CAS-before-RAS refresh cycle RPC delay Fixed Refresh RAS pulse width RAS precharge 1 1 3 2 BCLK tRAS #RAS tRPC tCSR tCHR #CAS A-118 EPSON S1C33L03 PRODUCT PART APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS A-1 DRAM: 60ns, CPU: 25MHz, random read/write cycle RAS cycle CAS cycle RAS precharge 1 2 2 COL #1 ;;;;;;;;; ;;;;;;;;; BCLK A[11:0] ROW #1 ROW #2 tRAS #RAS #CAS #RD ;;;;; ;;;;; D[15:0](RD) ;; ;; RD data #WE D[15:0](WR) A-ap ;;; ;;; WR data DRAM: 60ns, CPU: 25MHz, page-mode read/write cycle RAS cycle CAS cycle CAS cycle RAS precharge 1 2 2 2 COL #2 ;;;;;;;;; ;;;;;;;;; BCLK A[11:0] ROW #1 COL #1 tRAS #RAS #CAS #RD ;;;;; ;;;;; D[15:0](RD) ;;;;; ;;;;; RD data #WE D[15:0](WR) RD data WR data ;;; ;;; WR data DRAM: 60ns, CPU: 25MHz, CAS-before-RAS refresh cycle RPC delay Fixed Refresh RAS pulse width RAS precharge 1 1 2 2 BCLK tRAS #RAS tRPC tCSR tCHR #CAS S1C33L03 PRODUCT PART EPSON A-119 APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS DRAM: 60ns, CPU: 20MHz, random read/write cycle RAS cycle CAS cycle RAS precharge 1 2 1 COL #1 ;;;;; ;;;;; BCLK A[11:0] ROW #1 ROW #2 tRAS #RAS #CAS #RD ;;;;; ;;;;; D[15:0](RD) ;; ;; RD data #WE D[15:0](WR) ;;; ;;; WR data DRAM: 60ns, CPU: 20MHz, page-mode read/write cycle RAS cycle CAS cycle CAS cycle RAS precharge 1 2 2 1 BCLK A[11:0] ROW #1 COL #1 ;;;;;; ;;;;;; COL #2 tRAS #RAS #CAS #RD ;;;;; ;;;;; D[15:0](RD) RD data #WE D[15:0](WR) ;;;;; ;;;;; RD data WR data WR data ;;; ;;; DRAM: 60ns, CPU: 20MHz, CAS-before-RAS refresh cycle RPC delay Fixed Refresh RAS pulse width 1 1 2 RAS precharge 1 BCLK tRAS #RAS tRPC tCSR tCHR #CAS A-120 EPSON S1C33L03 PRODUCT PART APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS A-1 A.3 ROM and Burst ROM Burst ROM and mask ROM interface setup examples Operating frequency Normal read cycle Wait cycle Read cycle 20MHz 25MHz 33MHz 2 3 4 Burst read cycle Wait cycle Read cycle 3 4 5 1 1 2 Output disable delay cycle 2 2 3 1.5 1.5 1.5 Burst ROM and mask ROM interface timing Burst ROM and mask ROM interface Parameter Symbol Access time #CE output delay time #OE output delay time Burst access time Output disable delay time tACC tCE tOE tBAC tDF Min. Max. - - - - 0 100 100 50 50 40 33MHz Cycle Time 5 5 4.5 3 1.5 150 150 135 90 45 25MHz Cycle Time 4 4 3.5 2 1.5 160 160 140 80 60 20MHz Cycle Time 3 3 2.5 2 1.5 150 150 125 100 75 ROM: 100ns, CPU: 33MHz, normal read BCLK tACC ;;;;; ;;;;; A[23:0] tCE #CE9, 10 tOE #RD ;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;; D[15:0] tDF RD data ;;;; ;;;; ROM: 100ns, CPU: 33MHz, burst read BCLK Normal read cycle Burst read cycle tBAC tBAC tBAC ;;; ;;; A[23:0] #CE9, 10 #RD ;;;;;;;; ;;;;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; RD data D[15:0] S1C33L03 PRODUCT PART RD data EPSON RD data RD data tDF ;;; ;;; A-121 A-ap APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS ROM: 100ns, CPU: 25MHz, normal read BCLK ;;;;; ;;;;; A[23:0] #CE9, 10 #RD ;;;;;;;;;;; ;;;;;;;;;;; D[15:0] ;;;; ;;;; RD data ROM: 100ns, CPU: 25MHz, burst read BCLK Normal read cycle Burst read cycle ;;; ;;; A[23:0] #CE9, 10 #RD ;;;;;; ;;;;;; ;;; ;;; ;;; ;;; ;;; ;;; RD data D[15:0] RD data RD data RD data ;;; ;;; ROM: 100ns, CPU: 20MHz, normal read BCLK ;;;;; ;;;;; A[23:0] #CE9, 10 #RD D[15:0] ;;;;;;; ;;;;;;; ;;;; ;;;; RD data ROM: 100ns, CPU: 20MHz, burst read BCLK Normal read cycle Burst read cycle ;;; ;;; A[23:0] #CE9, 10 #RD ;;;; ;;;; ;;; ;;; ;;; ;;; ;;; ;;; RD data D[15:0] A-122 RD data EPSON RD data RD data ;;; ;;; S1C33L03 PRODUCT PART APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS A-1 A.4 SRAM (55ns) SRAM interface setup examples - 55ns Operating frequency Read cycle Wait cycle Read cycle 20MHz 25MHz 33MHz 1 2 2 Write cycle Output disable delay cycle 2 3 3 1.5 1.5 1.5 2 3 3 SRAM interface timing - 55ns SRAM interface Parameter Symbol 33MHz Cycle Time 25MHz Cycle Time 20MHz Cycle Time Min. Max. tRC tACC tACS tOE tOHZ 55 - - - 0 - 55 55 30 30 3 3 3 2.5 1.5 90 90 90 75 45 3 3 3 2.5 1.5 120 120 120 100 60 2 2 2 1.5 1.5 100 100 100 75 75 tWC tAW tWP tDW tDH 55 50 45 30 0 - - - - - 3 2.5 2 2 0.5 90 75 60 60 15 3 2.5 2 2 0.5 120 100 80 80 20 2 1.5 1 1 0.5 100 75 50 50 25 <Read cycle> Read cycle time Address access time #CE access time #OE access time Output disable delay time <Write cycle> Write cycle time Address enable time Write pulse width Input data setup time Input data hold time SRAM: 55ns, CPU: 33/25MHz, read cycle BCLK tRC ;;;;; ;;;;; A[23:0] tACC #CEx tACS #RD tOE ;;;;;;;;; ;;;;;;;;; tOHZ ;;;; ;;;; RD data D[15:0] SRAM: 55ns, CPU: 33/25MHz, write cycle BCLK tWC A[23:0] tAW ;;;;; ;;;;; #CEx tWP #WR tDW D[15:0] S1C33L03 PRODUCT PART WR data EPSON tDH ;;; ;;; A-123 A-ap APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS SRAM: 55ns, CPU: 20MHz, read cycle BCLK ;;;;; ;;;;; A[23:0] #CEx #RD ;;;;; ;;;;; RD data D[15:0] ;;;; ;;;; SRAM: 55ns, CPU: 20MHz, write cycle BCLK ;;;;; ;;;;; A[23:0] #CEx #WR D[15:0] A-124 WR data EPSON ;;; ;;; S1C33L03 PRODUCT PART APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS A-1 A.5 SRAM (70ns) SRAM interface setup examples - 70ns Operating frequency Read cycle Wait cycle Read cycle 20MHz 25MHz 33MHz 2 2 3 Write cycle Output disable delay cycle 3 3 4 1.5 1.5 1.5 3 3 4 SRAM interface timing - 70ns SRAM interface Parameter Symbol 33MHz Cycle Time 25MHz Cycle Time 20MHz Cycle Time Min. Max. tRC tACC tACS tOE tOHZ 70 - - - 0 - 70 70 40 30 4 4 4 3.5 1.5 120 120 120 105 45 3 3 3 2.5 1.5 120 120 120 100 60 3 3 3 2.5 1.5 150 150 150 125 75 tWC tAW tWP tDW tDH 70 60 55 30 0 - - - - - 4 3.5 3 3 0.5 120 105 90 90 15 3 2.5 2 2 0.5 120 100 80 80 20 3 2.5 2 2 0.5 150 125 100 100 25 <Read cycle> Read cycle time Address access time #CE access time #OE access time Output disable delay time <Write cycle> Write cycle time Address enable time Write pulse width Input data setup time Input data hold time SRAM: 70ns, CPU: 33MHz, read cycle BCLK tRC ;;;;; ;;;;; A[23:0] tACC #CEx tACS #RD tOE ;;;;;;;;;;;;; ;;;;;;;;;;;;; tOHZ ;;;; ;;;; RD data D[15:0] SRAM: 70ns, CPU: 33MHz, write cycle BCLK tWC A[23:0] tAW ;;;;; ;;;;; #CEx tWP #WR tDW D[15:0] S1C33L03 PRODUCT PART WR data EPSON tDH ;;; ;;; A-125 A-ap APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS SRAM: 70ns, CPU: 25/20MHz, read cycle BCLK ;;;;; ;;;;; A[23:0] #CEx #RD ;;;;;;;;; ;;;;;;;;; RD data D[15:0] ;;;; ;;;; SRAM: 70ns, CPU: 25/20MHz, write cycle BCLK ;;;;; ;;;;; A[23:0] #CEx #WR D[15:0] A-126 WR data EPSON ;;; ;;; S1C33L03 PRODUCT PART APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS A-1 A.6 8255A 8255A interface setup examples Operating frequency Read cycle Wait cycle Read cycle 9 1 11 14 20MHz 25MHz 33MHz Write cycle 10 12 15 Output disable delay cycle 10 12 15 3.5 3.5 3.5 2 8255A interface timing SRAM interface Parameter Symbol Min. Max. 33MHz Cycle Time 25MHz Cycle Time 20MHz Cycle Time tRC tACC tACS tOE tOHZ 300 - - - 10 - 250 250 250 150 15 15 15 14.5 3.5 450 450 450 435 105 12 12 12 11.5 3.5 480 480 480 460 140 10 10 10 9.5 3.5 500 500 500 475 175 tWC tAW tWP tDW tDH 430 400 400 100 30 - - - - - 15 14.5 14 14 0.5 450 435 420 420 15 12 11.5 11 11 0.5 480 460 440 440 20 10 9.5 9 9 0.5 500 475 450 450 25 <Read cycle> Read cycle time Address access time #CE access time #OE access time Output disable delay time <Write cycle> Write cycle time Address enable time Write pulse width Input data setup time Input data hold time 3 1 The S1C33L03 enables up to 7 cycles of wait-cycle insertion. If a number of wait cycles more than 7 cycles needs to be inserted, input the #WAIT signal from external hardware. Note that the interface must be set for SRAM type devices to insert wait cycles using the #WAIT pin. (Refer to "BCU (Bus Control Unit)" in the "S1C33L03 FUNCTION PART", for more information.) 2 This setting cannot satisfy the 150 ns of output-disable delay time specification required for the 8255A. When implementing such a low-speed device in the system, the external bus must be separated by inserting a 3-state bus buffer at the output side (when viewed from the CPU) of the external system bus. 3 If the data hold time that can be set is not sufficient for the device, secure it by connecting a bus repeater to the external data bus D[15:0] or by inserting a latch at the output side of the external system interface. S1C33L03 PRODUCT PART EPSON A-127 A-ap APPENDIX B PIN CHARACTERISTICS Appendix B Pin Characteristics Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A-128 Signal name P22/TM0 P23/TM1 VSS P24/TM2/#SRDY2 P25/TM3/#SCLK2 P26/TM4/SOUT2 P27/TM5/SIN2 VDD P07/#SRDY1/#DMAEND3 P06/#SCLK1/#DMAACK3 P05/SOUT1/#DMAEND2 P04/SIN1/#DMAACK2 FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT3/GPO6 FPDAT2/GPO5 FPDAT1/GPO4 FPDAT0/GPO3 VDDE DRDY(MOD/FPSHIFT2) FPFRAME FPLINE FPSHIFT LCDPWR VSS K67/AD7 K66/AD6 K65/AD5 K64/AD4 K63/AD3 K62/AD2 K61/AD1 K60/AD0 AVDDE K54/#DMAREQ3 K53/#DMAREQ2 K52/#ADTRG K51/#DMAREQ1 K50/#DMAREQ0 #WRH/#BSH #WRL/#WR/#WE #RD VSS D15 D14 D13 D12 D11 I/O cell name Characteristic Input XHBH1T XHBH1T VSS XHBH1T XHBH1T XHBH1T XHBH1T LVDD XHBH1T XHBH1T XHBH1T XHBH1T XHBC3BT XHBC3BT XHBC3BT XHBC3BT XHBC3BT XHBC3BT XHBC3BT XHBC3BT HVDD XHBC3BT XHBC3BT XHBC3BT XHBC3BT XHTB1T VSS XHIBCLINW XHIBCLINW XHIBCLINW XHIBCLINW XHIBCLINW XHIBCLINW XHIBCLINW XHIBCLINW HVDD XHIBHP2 XHIBHP2 XHIBHP2 XHIBHP2 XHIBHP2 XHBC1T XHBC1T XHBC1T VSS XHBC1T XHBC1T XHBC1T XHBC1T XHBC1T Output Pullup/down Power supply CMOS/LVTTL SCHMITT CMOS/LVTTL SCHMITT Type1 Type1 VDDE VDDE CMOS/LVTTL SCHMITT CMOS/LVTTL SCHMITT CMOS/LVTTL SCHMITT CMOS/LVTTL SCHMITT Type1 Type1 Type1 Type1 VDDE VDDE VDDE VDDE CMOS/LVTTL SCHMITT CMOS/LVTTL SCHMITT CMOS/LVTTL SCHMITT CMOS/LVTTL SCHMITT CMOS/LVTTL CMOS/LVTTL CMOS/LVTTL CMOS/LVTTL CMOS/LVTTL CMOS/LVTTL CMOS/LVTTL CMOS/LVTTL Type1 Type1 Type1 Type1 Type3 Type3 Type3 Type3 Type3 Type3 Type3 Type3 VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE CMOS/LVTTL CMOS/LVTTL CMOS/LVTTL CMOS/LVTTL Type3 Type3 Type3 Type3 Type1 VDDE VDDE VDDE VDDE VDDE CMOS/LVTTL CMOS/LVTTL CMOS/LVTTL CMOS/LVTTL CMOS/LVTTL CMOS/LVTTL CMOS/LVTTL CMOS/LVTTL AVDDE AVDDE AVDDE AVDDE AVDDE AVDDE AVDDE AVDDE CMOS/LVTTL SCHMITT CMOS/LVTTL SCHMITT CMOS/LVTTL SCHMITT CMOS/LVTTL SCHMITT CMOS/LVTTL SCHMITT note 3 note 3 note 3 Type1 Type1 Type1 VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE CMOS/LVTTL CMOS/LVTTL CMOS/LVTTL CMOS/LVTTL CMOS/LVTTL Type1 Type1 Type1 Type1 Type1 VDDE VDDE VDDE VDDE VDDE EPSON Pull-up Pull-up Pull-up Pull-up Pull-up Remarks note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 S1C33L03 PRODUCT PART APPENDIX B PIN CHARACTERISTICS Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Signal name VDD D10 D9 D8 D7 D6 D5 D4 VDDE D3 D2 D1 D0 #CE8/#RAS1/#CE14/#RAS3/#SDCE1 #CE7/#RAS0/#CE13/#RAS2/#SDCE0 VSS OSC2 OSC1 #RESET P35/#BUSACK/GPIO1 P34/#BUSREQ/#CE6/GPIO0 P33/#DMAACK1/SIN3/SDA10 P32/#DMAACK0/#SRDY3/HDQM P31/#BUSGET/#GARD/GPIO2 P30/#WAIT/#CE4&5 #LCAS/#SDRAS #HCAS/#SDCAS VDD P21/#DWE/#GAAS/#SDWE P20/#DRD/SDCKE BCLK/SDCLK VSS P16/EXCL5/#DMAEND1/SOUT3 P15/EXCL4/#DMAEND0/#SCLK3/LDQM A0/#BSL A1/SDA0 A2/SDA1 A3/SDA2 A4/SDA3 A5/SDA4 VDDE A6/SDA5 A7/SDA6 A8/SDA7 A9/SDA8 A10/SDA9 A11 VSS A12/SDA11 A13/SDA12 S1C33L03 PRODUCT PART I/O cell name LVDD XHBC1T XHBC1T XHBC1T XHBC1T XHBC1T XHBC1T XHBC1T HVDD XHBC1T XHBC1T XHBC1T XHBC1T XHBC1T XHBC1T VSS XLLOT XLLIN XHIBHP2 XHBH1T XHBH1T XHBH1T XHBH1T XHBH1T XHBH1T XHTB1T XHTB1T LVDD XHBH1T XHBH1T XHTB1T VSS XHBH1T XHBH1T XHBC1T XHBC1T XHBC1T XHBC1T XHBC1T XHBC1T HVDD XHBC1T XHBC1T XHBC1T XHBC1T XHBC1T XHBC1T VSS XHBC1T XHBC1T Characteristic Input Output Pullup/down Power supply CMOS/LVTTL CMOS/LVTTL CMOS/LVTTL CMOS/LVTTL CMOS/LVTTL CMOS/LVTTL CMOS/LVTTL Type1 Type1 Type1 Type1 Type1 Type1 Type1 VDDE VDDE VDDE VDDE VDDE VDDE VDDE CMOS/LVTTL CMOS/LVTTL CMOS/LVTTL CMOS/LVTTL note 3 note 3 Type1 Type1 Type1 Type1 Type1 Type1 VDDE VDDE VDDE VDDE VDDE VDDE Type1 Type1 Type1 Type1 Type1 Type1 Type1 Type1 VDD VDD VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE CMOS/LVTTL SCHMITT CMOS/LVTTL SCHMITT Type1 Type1 Type1 VDDE VDDE VDDE CMOS/LVTTL SCHMITT CMOS/LVTTL SCHMITT note 3 note 3 note 3 note 3 note 3 note 3 Type1 Type1 Type1 Type1 Type1 Type1 Type1 Type1 VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE note 3 note 3 note 3 note 3 note 3 note 3 Type1 Type1 Type1 Type1 Type1 Type1 VDDE VDDE VDDE VDDE VDDE VDDE note 3 note 3 Type1 Type1 VDDE VDDE CMOS/LVTTL SCHMITT CMOS/LVTTL SCHMITT CMOS/LVTTL SCHMITT CMOS/LVTTL SCHMITT CMOS/LVTTL SCHMITT CMOS/LVTTL SCHMITT CMOS/LVTTL SCHMITT EPSON Pull-up A-1 Remarks A-ap note 2 A-129 APPENDIX B PIN CHARACTERISTICS Pin No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 I/O cell name Signal name A14/SDBA0 A15/SDBA1 A16 A17 VSS A18 A19 A20 A21 A22 A23 PLLS1 PLLS0 VSS PLLC VSS DSIO P14/FOSC1/DCLK P13/EXCL3/T8UF3/DPCO P12/EXCL2/T8UF2/DST2 P11/EXCL1/T8UF1/DST1 P10/EXCL0/T8UF0/DST0 EA10MD1 EA10MD0 ICEMD #EMEMRD VDD OSC4 OSC3 #NMI #CE9/#CE17/#CE17&18 VDDE #CE5/#CE15/#CE15&16 N.C. #CE3 VSS #CE10EX/#CE9&10EX #CE6/#CE7&8 #CE4/#CE11/#CE11&12 #X2SPD P03/#SRDY0 P02/#SCLK0 P01/SOUT0 P00/SIN0 Characteristic Input XHBC1T XHBC1T XHBC1T XHBC1T VSS XHBC1T XHBC1T XHBC1T XHBC1T XHBC1T XHBC1T XHIBC XHIBC VSS XLLIN VSS XLBH2P2T XLBH2T XLBH2T XLBH2T XLBH2T XLBH2T XHIBCP2 XHIBC XITST1 XHTB1T LVDD XLLOT XLLIN XHIBHP2 XHBC1T HVDD XHBC1T XHTB1T VSS XHBC1T XHBC1T XHBC1T XHIBC XHBH1T XHBH1T XHBH1T XHBH1T Output Pullup/down Power supply note 3 note 3 note 3 note 3 Type1 Type1 Type1 Type1 VDDE VDDE VDDE VDDE note 3 note 3 note 3 note 3 note 3 note 3 CMOS/LVTTL CMOS/LVTTL Type1 Type1 Type1 Type1 Type1 Type1 VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE CMOS/LVTTL SCHMITT CMOS/LVTTL SCHMITT CMOS/LVTTL SCHMITT CMOS/LVTTL SCHMITT CMOS/LVTTL SCHMITT CMOS/LVTTL SCHMITT CMOS/LVTTL CMOS/LVTTL Type2 Type2 Type2 Type2 Type2 Type2 Pull-up Pull-up VDD note 2 VDD VDD VDD VDD VDD VDD VDDE VDDE note 2 note 2 note 2 note 2 note 2 note 2 Pull-down Test pin Type1 VDDE CMOS/LVTTL SCHMITT note 3 Type1 VDD VDD VDDE VDDE note 3 Type1 VDDE Type1 VDDE Type1 Type1 Type1 VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE note 3 note 3 note 3 CMOS/LVTTL CMOS/LVTTL SCHMITT CMOS/LVTTL SCHMITT CMOS/LVTTL SCHMITT CMOS/LVTTL SCHMITT Pull-up Type1 Type1 Type1 Type1 Remarks note 2 note 1) The voltage applied to this pin must be 0V VIN AVDDE. Note that the input voltage range for the K50 pin differs from other K5x pins. note 2) The voltage applied to this pin must be 0V VIN VDD. note 3) This pin is set as an input pin during device testing. Normally it is an output pin. The following table lists output current characteristics. Output current (IOL/IOH) Type1 Type2 Type3 A-130 5.0 V 3 mA - 12 mA 3.3 V 2 mA 6 mA 12 mA 2.0 V 0.6 mA 2 mA 4 mA EPSON S1C33L03 PRODUCT PART S1C33L03 FUNCTION PART S1C33L03 FUNCTION PART I OUTLINE I OUTLINE: INTRODUCTION A-1 I-1 INTRODUCTION The Function Part gives a detailed description of the various function blocks built into the Seiko Epson original 32-bit microcomputer S1C33L03. The S1C33L03 employs a RISC type CPU, and has a powerful instruction set capable of compilation into compact code, despite the small CPU core size. The S1C33L03 has the following features: * Small CPU core: 25K gates * Fast and high performance: DC to 50 MHz operation * Strong instruction set: 16-bit fixed length, 105 basic instructions * Execution cycle: Major instructions are executed in 1 cycle per instruction * MAC function: 16 bits x 16 bits + 64 bits, 2 clock per MAC (25 MOPS in 50 MHz) * Registers: 32 bits x 16 general registers and 32 bits x 5 special registers * Memory space: 256M bytes (28 bits) linear space, code-data-IO shared type * External bus I/F: 15 configurable memory areas Direct connection to external memory * Interrupts: Reset, NMI, up to 128 external interrupts, 4 software interrupts, 2 exceptions * Reset, boot: Cold reset, hot reset * Power down mode: Sleep, Halt * Others: Little endian (partial big endian can be configured) Harvard architecture (fetch, load/store parallel execution) * User logic interface: Programmable wait state (up to 7 cycles) #WAIT pin hand shake is possible. Large memory space for the user logic (up to 16M bytes) BCU configuration registers allow internal use of the external areas (Areas 4 to 18). Many interrupt requests from the user logic are acceptable. S1C33L03 FUNCTION PART EPSON B-I Intro B-I-1-1 I OUTLINE: INTRODUCTION THIS PAGE IS BLANK. B-I-1-2 EPSON S1C33L03 FUNCTION PART I OUTLINE: BLOCK DIAGRAM A-1 I-2 BLOCK DIAGRAM The S1C33L03 consists of seven major blocks: C33 Core Block, C33 Peripheral Block, C33 Analog Block, C33 DMA Block, C33 SDRAM Controller Block, C33 LCD Controller Block and C33 Internal Memory Block. Figure 2.1 shows the configuration of the S1C33 blocks. C33 DMA Block C33 SDRAM Controller Block C33 LCD Controller Block C33_DMA C33_SDRAMC C33_LCDC (IDMA, HSDMA) (SDRAM interface) (LCD panel interface) Pads B-I Internal RAM (Area 0) CORE_PAD C33 Internal Memory Block C33_CORE (CPU, BCU, ITC, CLG, DBG) Internal ROM (Area 10) Block Pads C33_SBUS C33_ADC C33_PERI (A/D converter) (Prescaler, 8-bit timer, 16-bit timer, Clock timer, Serial interface, Ports) C33 Analog Block PERI_PAD C33 Core Block Pads C33 Peripheral Block Figure 2.1 Block Configuration Note: Internal ROM is not provided in the S1C33L03. S1C33L03 FUNCTION PART EPSON B-I-2-1 I OUTLINE: BLOCK DIAGRAM C33 Core Block The C33 Core Block consists of a functional block C33_CORE including CPU, BCU (Bus Control Unit), ITC (Interrupt Controller), CLG (Clock Generator) and DBG (Debug Unit), an I/O pad block for external interface, and an SBUS (Internal Silicon Integration Bus) for interfacing with on-chip Peripheral Macro Cells. The C33 Core Block employs the S1C33000 32-bit RISC type CPU as the core CPU. C33 Peripheral Block The C33 Peripheral Block consists of a prescaler, six channels of 8-bit programmable timer, six channels of 16-bit programmable timer including watchdog timer function, four channels of serial interface, input and I/O ports, and a clock timer. C33 Analog Block The C33 Analog Block consists of an A/D converter with eight input channels. C33 DMA Block The C33 DMA Block is configured with two types of DMA controllers: HSDMA (High-Speed DMA) that has on-chip registers for controlling DMA command information and IDMA (Intelligent DMA) that uses a memory area for storing DMA command information. C33 SDRAM Controller Block The SDRAM Controller Block provides a SDRAM interface that allows direct connection of external SDRAM chips via the BCU. C33 LCD Controller Block The LCD Controller Block provides LCD control signals for a 4- or 8-bit color/monochrome LCD panel. C33 Memory Block The S1C33L03 contains an 8KB of SRAM as the internal memory. For details of the blocks, refer to the respective section in this manual. B-I-2-2 EPSON S1C33L03 FUNCTION PART I OUTLINE: LIST OF PINS A-1 I-3 LIST OF PINS List of External I/O Pins The following lists the external I/O pins of the C33 Core Block, Peripheral Block and LCD Controller Block. Note that some pins are listed in two or more tables. Table 3.1 List of Pins for External Bus Interface Signals Pin name A0 #BSL A[10:1] SDA[9:0] A11 A[13:12] SDA[12:11] A[15:14] SDBA[1:0] A[23:16] D[15:0] #CE10EX #CE9&10EX #CE9 #CE17 #CE17&18 #CE8 #RAS1 #CE14 #RAS3 #SDCE1 Pin No. I/O Pull-up 85 O - 85-90,92-96 O - 97 99,100 O O - - 101,102 O - 103,104, O 106-111 46-50,52-58, I/O 60-63 137 O - A0: Address bus (A0) when SBUSST(D3/0x4812E) = "0" (default) #BSL: Bus strobe (low byte) signal when SBUSST(D3/0x4812E) = "1" A[10:1]: Address bus (A1-A10) SDA[9:0]: SDRAM address bus (SDA0-SDA9) Address bus (A11) A[13:12]: Address bus (A12-A13) SDA[12:11]: SDRAM address bus (SDA11-SDA12) A[15:14]: Address bus (A14-A15) SDBA[1:0]: SDRAM bank select (SDBA0-SDBA1) Address bus (A16-A23) - Data bus (D0-D15) - Area 10 chip enable for external memory * When CEFUNC[1:0] = "1x", this pin outputs #CE9+#CE10EX signal. #CE9: Area 9 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "00" (default) #CE17: Area 17 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "01" * When CEFUNC[1:0] = "1x", this pin outputs #CE17+#CE18 signal. #CE8: Area 8 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "00", A8DRA(D8/0x48128) = "0" and SDRPC1(D2/0x39FFC0) = "0" (default) #RAS1: Area 8 DRAM row strobe when CEFUNC[1:0](D[A:9]/0x48130) = "00", A8DRA(D8/0x48128) = "1" and SDRPC1(D2/0x39FFC0) = "0" #CE14: Area 14 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "01" or "1x", A14DRA(D8/0x48122) = "0" and SDRPC1(D2/0x39FFC0) = "0" #RAS3: Area 14 DRAM row strobe when CEFUNC[1:0](D[A:9]/0x48130) = "01" or "1x", A14DRA(D8/0x48122) = "1" and SDRPC1(D2/0x39FFC0) = "0" #SDCE1: SDRAM chip enable 1 when SDRPC1(D2/0x39FFC0) = "1" and SDRENA(D7/0x39FFC1) = "1" #CE7: Area 7 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "00", A7DRA(D7/0x48128) = "0" and SDRPC0(D3/0x39FFC0) = "0" (default) #RAS0: Area 7 DRAM row strobe when CEFUNC[1:0](D[A:9]/0x48130) = "00", A7DRA(D7/0x48128) = "1" and SDRPC0(D3/0x39FFC0) = "0" #CE13: Area 13 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "01" or "1x", A13DRA(D7/0x48122) = "0" and SDRPC0(D3/0x39FFC0) = "0" #RAS2: Area 13 DRAM row strobe when CEFUNC[1:0](D[A:9]/0x48130) = "01" or "1x", A13DRA(D7/0x48122) = "1" and SDRPC0(D3/0x39FFC0) = "0" #SDCE0: SDRAM chip enable 0 when SDRPC0(D3/0x39FFC0) = "1" and SDRENA(D7/0x39FFC1) = "1" Area 6 chip enable * When CEFUNC[1:0] = "1x", this pin outputs #CE7+#CE8 signal. #CE5: Area 5 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "00" (default) #CE15: Area 15 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "01" * When CEFUNC[1:0] = "1x", this pin outputs #CE15+#CE16 signal. #CE4: Area 4 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "00" (default) #CE11: Area 11 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "01" * When CEFUNC[1:0] = "1x", this pin outputs #CE11+#CE12 signal. Area 3 chip enable Read signal Read signal for internal ROM emulation memory #WRL: Write (low byte) signal when SBUSST(D3/0x4812E) = "0" (default) #WR: Write signal when SBUSST(D3/0x4812E) = "1" #WE: DRAM write signal #WRH: Write (high byte) signal when SBUSST(D3/0x4812E) = "0" (default) #BSH: Bus strobe (high byte) signal when SBUSST(D3/0x4812E) = "1" 131 O - 64 O - #CE7 #RAS0 #CE13 #RAS2 #SDCE0 65 O - #CE6 #CE7&8 #CE5 #CE15 #CE15&16 #CE4 #CE11 #CE11&12 #CE3 #RD #EMEMRD #WRL #WR #WE #WRH #BSH 138 O - 133 O - 139 O - 135 44 126 43 O O O O - - - - 42 O - S1C33L03 FUNCTION PART Function EPSON B-I Pin B-I-3-1 I OUTLINE: LIST OF PINS Pin No. I/O Pull-up #HCAS #SDCAS Pin name 77 O - #LCAS #SDRAS 76 O BCLK SDCLK P34 #BUSREQ #CE6 GPIO0 81 O 71 I/O P35 #BUSACK GPIO1 70 I/O P30 #WAIT #CE4&5 75 I/O P20 #DRD SDCKE 80 I/O P21 #DWE #GAAS #SDWE 79 I/O P31 #BUSGET #GARD GPIO2 74 I/O EA10MD1 123 I EA10MD0 124 I B-I-3-2 Function #HCAS: DRAM column address strobe (high byte) signal when SDRENA(D7/0x39FFC1) = "0" (default) #SDCAS: SDRAM column address strobe when SDRENA(D7/0x39FFC1) = "1" - #LCAS: DRAM column address strobe (low byte) signal when SDRENA(D7/0x39FFC1) = "0" (default) #SDRAS: SDRAM row address strobe when SDRENA(D7/0x39FFC1) = "1" - BCLK: Bus clock output when SDRENA(D7/0x39FFC1) = "0" (default) SDCLK: SDRAM clock output when SDRENA(D7/0x39FFC1) = "1" - P34: I/O port when CFP34(D4/0x402DC) = "0" (default) #BUSREQ: Bus release request input when CFP34(D4/0x402DC) = "1" #CE6: Area 6 chip enable when CFP34(D4/0x402DC) = "1" and IOC34(D4/0x402DE) = "1" GPIO0: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and BREQEN(D2/0x39FFFD) = "0" - P35: I/O port when CFP35(D5/0x402DC) = "0" (default) #BUSACK: Bus acknowledge output when CFP35(D5/0x402DC) = "1" and CFP34(D4/0x402DC) = "1" GPIO1: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and BREQEN(D2/0x39FFFD) = "0" - P30: I/O port when CFP30(D0/0x402DC) = "0" (default) #WAIT: Wait cycle request input when CFP30(D0/0x402DC) = "1" #CE4&5: Areas 4&5 chip enable when CFP30(D0/0x402DC) = "1" and IOC30(D0/0x402DE) = "1" - P20: I/O port when CFP20(D0/0x402D8) = "0" and SDRENA(D7/0x39FFC1) = "0" (default) #DRD: DRAM read signal output for successive RAS mode when CFP20(D0/0x402D8) = "1" and SDRENA(D7/0x39FFC1) = "0" SDCKE: SDRAM clock enable signal when SDRENA(D7/0x39FFC1) = "1" - P21: I/O port when CFP21(D1/0x402D8) = "0", CFEX2(D2/0x402DF) = "0" and SDRENA(D7/0x39FFC1) = "0" (default) #DWE: DRAM write signal output for successive RAS mode when CFP21(D1/0x402D8) = "1", CFEX2(D2/0x402DF) = "0" and SDRENA(D7/0x39FFC1) = "0" #GAAS: Area address strobe output for GA when CFEX2(D2/0x402DF) = "1" and SDRENA(D7/0x39FFC1) = "0" #SDWE: SDRAM write signal when SDRENA(D7/0x39FFC1) = "1" - P31: I/O port when CFP31(D1/0x402DC) = "0" and CFEX3(D3/0x402DF) = "0" (default) #BUSGET: Bus status monitor signal output for bus release request when CFP31(D1/0x402DC) = "1" and CFEX3(D3/0x402DF) = "0" #GARD: Area read signal output for GA when CFEX3(D3/0x402DF) = "1" GPIO2: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and BREQEN(D2/0x39FFFD) = "0" Pull-up Area 10 boot mode selection EA10MD1 EA10MD0 Mode - 1 1 External ROM mode 1 0 Internal ROM mode EPSON S1C33L03 FUNCTION PART I OUTLINE: LIST OF PINS A-1 Table 3.2 List of Pins for HSDMA Control Signals Pin name K50 #DMAREQ0 K51 #DMAREQ1 K53 #DMAREQ2 K54 #DMAREQ3 P32 #DMAACK0 #SRDY3 HDQM Pin No. 41 I/O I 40 I 38 I 37 I 73 I/O Pull-up Pull-up K50: #DMAREQ0: Pull-up K51: #DMAREQ1: Pull-up K53: #DMAREQ2: Pull-up K54: #DMAREQ3: - P32: #DMAACK0: #SRDY3: HDQM: P33 #DMAACK1 SIN3 SDA10 72 I/O - P33: #DMAACK1: SIN3: P04 SIN1 #DMAACK2 12 P06 #SCLK1 #DMAACK3 10 P15 EXCL4 #DMAEND0 #SCLK3 LDQM 84 I/O - SDA10: P04: SIN1: I/O - #DMAACK2: P06: #SCLK1: I/O - #DMAACK3: P15: EXCL4: #DMAEND0: #SCLK3: LDQM: P16 EXCL5 #DMAEND1 SOUT3 83 I/O - P16: EXCL5: #DMAEND1: SOUT3: P05 SOUT1 #DMAEND2 11 P07 #SRDY1 #DMAEND3 9 I/O - P05: SOUT1: I/O - #DMAEND2: P07: #SRDY1: #DMAEND3: S1C33L03 FUNCTION PART Function Input port when CFK50(D0/0x402C0) = "0" (default) HSDMA Ch. 0 request input when CFK50(D0/0x402C0) = "1" Input port when CFK51(D1/0x402C0) = "0" (default) HSDMA Ch. 1 request input when CFK51(D1/0x402C0) = "1" Input port when CFK53(D3/0x402C0) = "0" (default) HSDMA Ch. 2 request input when CFK53(D3/0x402C0) = "1" Input port when CFK54(D4/0x402C0) = "0" (default) HSDMA Ch. 3 request input when CFK54(D4/0x402C0) = "1" I/O port when CFP32(D2/0x402DC) = "0" and SDRENA(D7/0x39FFC1) = "0" (default) HSDMA Ch. 0 acknowledge output when CFP32(D2/0x402DC) = "1" and SDRENA(D7/0x39FFC1) = "0" Serial I/F Ch. 3 ready signal input/output when SSRDY3(D3/0x402D7) = "1", CFP32(D2/0x402DC) = "0" and SDRENA(D7/0x39FFC1) = "0" SDRAM data (high byte) input/output mask signal when SDRENA(D7/0x39FFC1) = "1" I/O port when CFP33(D3/0x402DC) = "0" and SDRENA(D7/0x39FFC1) = "0" (default) HSDMA Ch. 1 acknowledge output when CFP33(D3/0x402DC) = "1" and SDRENA(D7/0x39FFC1) = "0" Serial I/F Ch. 3 data input when SSIN3(D0/0x402D7) = "1", CFP33(D3/0x402DC) = "0" and SDRENA(D7/0x39FFC1) = "0" SDRAM address bus bit 10 when SDRENA(D7/0x39FFC1) = "1" I/O port when CFP04(D4/0x402D0) = "0" and CFEX4(D4/0x402DF) = "0" (default) Serial I/F Ch. 1 data input when CFP04(D4/0x402D0) = "1" and CFEX4(D4/0x402DF) = "0" HSDMA Ch. 2 acknowledge output when CFEX4(D4/0x402DF) = "1" I/O port when CFP06(D6/0x402D0) = "0" and CFEX6(D6/0x402DF) = "0" (default) Serial I/F Ch. 1 clock input/output when CFP06(D6/0x402D0) = "1" and CFEX6(D6/0x402DF) = "0" HSDMA Ch. 3 acknowledge output when CFEX6(D6/0x402DF) = "1" I/O port when CFP15(D5/0x402D4) = "0" and SDRENA(D7/0x39FFC1) = "0" (default) 16-bit timer 4 event counter input when CFP15(D5/0x402D4) = "1", IOC15(D5/0x402D6) = "0" and SDRENA(D7/0x39FFC1) = "0" HSDMA Ch. 0 end-of-transfer signal output when CFP15(D5/0x402D4) = "1", IOC15(D5/0x402D6) = "1" and SDRENA(D7/0x39FFC1) = "0" Serial I/F Ch. 3 clock input/output when SSCLK3(D2/0x402D7) = "1", CFP15(D5/0x402D4) = "0" and SDRENA(D7/0x39FFC1) = "0" SDRAM data (low byte) input/output mask signal when SDRENA(D7/0x39FFC1) = "1" I/O port when CFP16(D6/0x402D4) = "0" (default) 16-bit timer 5 event counter input when CFP16(D6/0x402D4) = "1" and IOC16(D6/0x402D6) = "0" HSDMA Ch. 1 end-of-transfer signal output when CFP16(D6/0x402D4) = "1" and IOC16(D6/0x402D6) = "1" Serial I/F Ch. 3 data output when SSOUT3(D1/0x402D7) = "1" and CFP16(D6/0x402D4) = "0" I/O port when CFP05(D5/0x402D0) = "0" and CFEX5(D5/0x402DF) = "0" (default) Serial I/F Ch. 1 data output when CFP05(D5/0x402D0) = "1" and CFEX5(D5/0x402DF) = "0" HSDMA Ch. 2 end-of-transfer signal output when CFEX5(D5/0x402DF) = "1" I/O port when CFP07(D7/0x402D0) = "0" and CFEX7(D7/0x402DF) = "0" (default) Serial I/F Ch. 1 ready signal output when CFP07(D7/0x402D0) = "1" and CFEX5(D5/0x402DF) = "0" HSDMA Ch. 3 end-of-transfer signal output when CFEX7(D7/0x402DF) = "1" EPSON B-I-3-3 B-I Pin I OUTLINE: LIST OF PINS Table 3.3 List of Pins for Internal Peripheral Circuits Pin name K50 #DMAREQ0 K51 #DMAREQ1 K52 #ADTRG K53 #DMAREQ2 K54 #DMAREQ3 K60 AD0 K61 AD1 K62 AD2 K63 AD3 K64 AD4 K65 AD5 K66 AD6 K67 AD7 P00 SIN0 P01 SOUT0 P02 #SCLK0 P03 #SRDY0 P04 SIN1 #DMAACK2 Pin No. 41 I/O I 40 I 39 I 38 I 37 I 35 I 34 I 33 I 32 I 31 I 30 I 29 I 28 I 144 I/O 143 I/O 142 I/O 141 I/O 12 I/O P05 SOUT1 #DMAEND2 11 Pull-up Pull-up K50: #DMAREQ0: Pull-up K51: #DMAREQ1: Pull-up K52: #ADTRG: Pull-up K53: #DMAREQ2: Pull-up K54: #DMAREQ3: - K60: AD0: - K61: AD1: - K62: AD2: - K63: AD3: - K64: AD4: - K65: AD5: - K66: AD6: - K67: AD7: - P00: SIN0: - P01: SOUT0: - P02: #SCLK0: - P03: #SRDY0: - P04: SIN1: I/O - #DMAACK2: P05: SOUT1: #DMAEND2: P06 #SCLK1 #DMAACK3 10 P07 #SRDY1 #DMAEND3 9 I/O - P06: #SCLK1: I/O - #DMAACK3: P07: #SRDY1: #DMAEND3: P10 EXCL0 T8UF0 DST0 122 I/O - P10: EXCL0: T8UF0: DST0: B-I-3-4 Function Input port when CFK50(D0/0x402C0) = "0" (default) HSDMA Ch. 0 request input when CFK50(D0/0x402C0) = "1" Input port when CFK51(D1/0x402C0) = "0" (default) HSDMA Ch. 1 request input when CFK51(D1/0x402C0) = "1" Input port when CFK52(D2/0x402C0) = "0" (default) A/D converter trigger input when CFK52(D2/0x402C0) = "1" Input port when CFK53(D3/0x402C0) = "0" (default) HSDMA Ch. 2 request input when CFK53(D3/0x402C0) = "1" Input port when CFK54(D4/0x402C0) = "0" (default) HSDMA Ch. 3 request input when CFK54(D4/0x402C0) = "1" Input port when CFK60(D0/0x402C3) = "0" (default) A/D converter Ch. 0 input when CFK60(D0/0x402C3) = "1" Input port when CFK61(D1/0x402C3) = "0" (default) A/D converter Ch. 1 input when CFK61(D1/0x402C3) = "1" Input port when CFK62(D2/0x402C3) = "0" (default) A/D converter Ch. 2 input when CFK62(D2/0x402C3) = "1" Input port when CFK63(D3/0x402C3) = "0" (default) A/D converter Ch. 3 input when CFK63(D3/0x402C3) = "1" Input port when CFK64(D4/0x402C3) = "0" (default) A/D converter Ch. 4 input when CFK64(D4/0x402C3) = "1" Input port when CFK65(D5/0x402C3) = "0" (default) A/D converter Ch. 5 input when CFK65(D5/0x402C3) = "1" Input port when CFK66(D6/0x402C3) = "0" (default) A/D converter Ch. 6 input when CFK66(D6/0x402C3) = "1" Input port when CFK67(D7/0x402C3) = "0" (default) A/D converter Ch. 7 input when CFK67(D7/0x402C3) = "1" I/O port when CFP00(D0/0x402D0) = "0" (default) Serial I/F Ch. 0 data input when CFP00(D0/0x402D0) = "1" I/O port when CFP01(D1/0x402D0) = "0" (default) Serial I/F Ch. 0 data output when CFP01(D1/0x402D0) = "1" I/O port when CFP02(D2/0x402D0) = "0" (default) Serial I/F Ch. 0 clock input/output when CFP02(D2/0x402D0) = "1" I/O port when CFP03(D3/0x402D0) = "0" (default) Serial I/F Ch. 0 ready signal input/output when CFP03(D3/0x402D0) = "1" I/O port when CFP04(D4/0x402D0) = "0" and CFEX4(D4/0x402DF) = "0" (default) Serial I/F Ch. 1 data input when CFP04(D4/0x402D0) = "1" and CFEX4(D4/0x402DF) = "0" HSDMA Ch. 2 acknowledge output when CFEX4(D4/0x402DF) = "1" I/O port when CFP05(D5/0x402D0) = "0" and CFEX5(D5/0x402DF) = "0" (default) Serial I/F Ch. 1 data output when CFP05(D5/0x402D0) = "1" and CFEX5(D5/0x402DF) = "0" HSDMA Ch. 2 end-of-transfer signal output when CFEX5(D5/0x402DF) = "1" I/O port when CFP06(D6/0x402D0) = "0" and CFEX6(D6/0x402DF) = "0" (default) Serial I/F Ch. 1 clock input/output when CFP06(D6/0x402D0) = "1" and CFEX6(D6/0x402DF) = "0" HSDMA Ch. 3 acknowledge output when CFEX6(D6/0x402DF) = "1" I/O port when CFP07(D7/0x402D0) = "0" and CFEX7(D7/0x402DF) = "0" (default) Serial I/F Ch. 1 ready signal output when CFP07(D7/0x402D0) = "1" and CFEX5(D5/0x402DF) = "0" HSDMA Ch. 3 end-of-transfer signal output when CFEX7(D7/0x402DF) = "1" I/O port when CFP10(D0/0x402D4) = "0" and CFEX1(D1/0x402DF) = "0" 16-bit timer 0 event counter input when CFP10(D0/0x402D4) = "1", IOC10(D0/0x402D6) = "0" and CFEX1(D1/0x402DF) = "0" 8-bit timer 0 output when CFP10(D0/0x402D4) = "1", IOC10(D0/0x402D6) = "1" and CFEX1(D1/0x402DF) = "0" DST0 signal output when CFEX1(D1/0x402DF) = "1" (default) EPSON S1C33L03 FUNCTION PART I OUTLINE: LIST OF PINS Pin name Pin No. I/O Pull-up P11 EXCL1 T8UF1 DST1 121 I/O - P12 EXCL2 T8UF2 DST2 120 I/O - P13 EXCL3 T8UF3 DPCO 119 I/O - P14 FOSC1 DCLK 118 I/O - P15 EXCL4 #DMAEND0 #SCLK3 LDQM 84 I/O - P16 EXCL5 #DMAEND1 SOUT3 83 I/O - P20 #DRD SDCKE 80 I/O - P21 #DWE #GAAS #SDWE 79 I/O - P22 TM0 P23 TM1 P24 TM2 #SRDY2 1 I/O - 2 I/O - 4 I/O - P25 TM3 #SCLK2 5 I/O - S1C33L03 FUNCTION PART A-1 Function P11: EXCL1: I/O port when CFP11(D1/0x402D4) = "0" and CFEX1(D1/0x402DF) = "0" 16-bit timer 1 event counter input when CFP11(D1/0x402D4) = "1", IOC11(D1/0x402D6) = "0" and CFEX1(D1/0x402DF) = "0" T8UF1: 8-bit timer 1 output when CFP11(D1/0x402D4) = "1", IOC11(D1/0x402D6) = "1" and CFEX1(D1/0x402DF) = "0" DST1: DST1 signal output when CFEX1(D1/0x402DF) = "1" (default) P12: I/O port when CFP12(D2/0x402D4) = "0" and CFEX0(D0/0x402DF) = "0" EXCL2: 16-bit timer 2 event counter input when CFP12(D2/0x402D4) = "1", IOC12(D2/0x402D6) = "0" and CFEX0(D0/0x402DF) = "0" T8UF2: 8-bit timer 2 output when CFP12(D2/0x402D4) = "1", IOC12(D2/0x402D6) = "1" and CFEX0(D0/0x402DF) = "0" DST2: DST2 signal output when CFEX0(D0/0x402DF) = "1" (default) P13: I/O port when CFP13(D3/0x402D4) = "0" and CFEX1(D1/0x402DF) = "0" EXCL3: 16-bit timer 3 event counter input when CFP13(D3/0x402D4) = "1", IOC13(D3/0x402D6) = "0" and CFEX1(D1/0x402DF) = "0" T8UF3: 8-bit timer 3 output when CFP13(D3/0x402D4) = "1", IOC13(D3/0x402D6) = "1" and CFEX1(D1/0x402DF) = "0" DPCO: DPCO signal output when CFEX1(D1/0x402DF) = "1" (default) P14: I/O port when CFP14(D4/0x402D4) = "0" and CFEX0(D0/0x402DF) = "0" FOSC1: OSC1 clock output when CFP14(D4/0x402D4) = "1" and CFEX0(D0/0x402DF) = "0" DCLK: DCLK signal output when CFEX0(D0/0x402DF) = "1" (default) P15: I/O port when CFP15(D5/0x402D4) = "0" and SDRENA(D7/0x39FFC1) = "0" (default) EXCL4: 16-bit timer 4 event counter input when CFP15(D5/0x402D4) = "1", IOC15(D5/0x402D6) = "0" and SDRENA(D7/0x39FFC1) = "0" #DMAEND0: HSDMA Ch. 0 end-of-transfer signal output when CFP15(D5/0x402D4) = "1", IOC15(D5/0x402D6) = "1" and SDRENA(D7/0x39FFC1) = "0" #SCLK3: Serial I/F Ch. 3 clock input/output when SSCLK3(D2/0x402D7) = "1", CFP15(D5/0x402D4) = "0" and SDRENA(D7/0x39FFC1) = "0" LDQM: SDRAM data (low byte) input/output mask signal when SDRENA(D7/0x39FFC1) = "1" P16: I/O port when CFP16(D6/0x402D4) = "0" (default) EXCL5: 16-bit timer 5 event counter input when CFP16(D6/0x402D4) = "1" and IOC16(D6/0x402D6) = "0" #DMAEND1: HSDMA Ch. 1 end-of-transfer signal output when CFP16(D6/0x402D4) = "1" and IOC16(D6/0x402D6) = "1" SOUT3: Serial I/F Ch. 3 data output when SSOUT3(D1/0x402D7) = "1" and CFP16(D6/0x402D4) = "0" P20: I/O port when CFP20(D0/0x402D8) = "0" and SDRENA(D7/0x39FFC1) = "0" (default) #DRD: DRAM read signal output for successive RAS mode when CFP20(D0/0x402D8) = "1" and SDRENA(D7/0x39FFC1) = "0" SDCKE: SDRAM clock enable signal when SDRENA(D7/0x39FFC1) = "1" P21: I/O port when CFP21(D1/0x402D8) = "0", CFEX2(D2/0x402DF) = "0" and SDRENA(D7/0x39FFC1) = "0" (default) #DWE: DRAM write signal output for successive RAS mode when CFP21(D1/0x402D8) = "1", CFEX2(D2/0x402DF) = "0" and SDRENA(D7/0x39FFC1) = "0" #GAAS: Area address strobe output for GA when CFEX2(D2/0x402DF) = "1" and SDRENA(D7/0x39FFC1) = "0" #SDWE: SDRAM write signal when SDRENA(D7/0x39FFC1) = "1" P22: I/O port when CFP22(D2/0x402D8) = "0" (default) TM0: 16-bit timer 0 output when CFP22(D2/0x402D8) = "1" P23: I/O port when CFP23(D3/0x402D8) = "0" (default) TM1: 16-bit timer 1 output when CFP23(D3/0x402D8) = "1" P24: I/O port when CFP24(D4/0x402D8) = "0" (default) TM2: 16-bit timer 2 output when CFP24(D4/0x402D8) = "1" #SRDY2: Serial I/F Ch. 2 ready signal input/output when SSRDY2(D3/0x402DB) = "1" and CFP24(D4/0x402D8) = "0" P25: I/O port when CFP25(D5/0x402D8) = "0" (default) TM3: 16-bit timer 3 output when CFP25(D5/0x402D8) = "1" #SCLK2: Serial I/F Ch. 2 clock input/output when SSCLK2(D2/0x402DB) = "1" and CFP25(D5/0x402D8) = "0" EPSON B-I-3-5 B-I Pin I OUTLINE: LIST OF PINS Pin No. I/O Pull-up P26 TM4 SOUT2 Pin name 6 I/O - P27 TM5 SIN2 7 I/O - P30 #WAIT #CE4&5 75 I/O - P31 #BUSGET #GARD GPIO2 74 I/O - P32 #DMAACK0 #SRDY3 HDQM 73 I/O - P33 #DMAACK1 SIN3 SDA10 72 I/O - P34 #BUSREQ #CE6 GPIO0 71 I/O - P35 #BUSACK GPIO1 70 I/O - B-I-3-6 Function P26: TM4: SOUT2: I/O port when CFP26(D6/0x402D8) = "0" (default) 16-bit timer 4 output when CFP26(D6/0x402D8) = "1" Serial I/F Ch. 2 data output when SSOUT2(D1/0x402DB) = "1" and CFP26(D6/0x402D8) = "0" P27: I/O port when CFP27(D7/0x402D8) = "0" (default) TM5: 16-bit timer 5 output when CFP27(D7/0x402D8) = "1" SIN2: Serial I/F Ch. 2 data input when SSIN2(D0/0x402DB) = "1" and CFP27(D7/0x402D8) = "0" P30: I/O port when CFP30(D0/0x402DC) = "0" (default) #WAIT: Wait cycle request input when CFP30(D0/0x402DC) = "1" #CE4&5: Areas 4&5 chip enable when CFP30(D0/0x402DC) = "1" and IOC30(D0/0x402DE) = "1" P31: I/O port when CFP31(D1/0x402DC) = "0" and CFEX3(D3/0x402DF) = "0" (default) #BUSGET: Bus status monitor signal output for bus release request when CFP31(D1/0x402DC) = "1" and CFEX3(D3/0x402DF) = "0" #GARD: Area read signal output for GA when CFEX3(D3/0x402DF) = "1" GPIO2: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and BREQEN(D2/0x39FFFD) = "0" P32: I/O port when CFP32(D2/0x402DC) = "0" and SDRENA(D7/0x39FFC1) = "0" (default) #DMAACK0: HSDMA Ch. 0 acknowledge output when CFP32(D2/0x402DC) = "1" and SDRENA(D7/0x39FFC1) = "0" #SRDY3: Serial I/F Ch. 3 ready signal input/output when SSRDY3(D3/0x402D7) = "1", CFP32(D2/0x402DC) = "0" and SDRENA(D7/0x39FFC1) = "0" HDQM: SDRAM data (high byte) input/output mask signal when SDRENA(D7/0x39FFC1) = "1" P33: I/O port when CFP33(D3/0x402DC) = "0" and SDRENA(D7/0x39FFC1) = "0" (default) #DMAACK1: HSDMA Ch. 1 acknowledge output when CFP33(D3/0x402DC) = "1" and SDRENA(D7/0x39FFC1) = "0" SIN3: Serial I/F Ch. 3 data input when SSIN3(D0/0x402D7) = "1", CFP33(D3/0x402DC) = "0" and SDRENA(D7/0x39FFC1) = "0" SDA10: SDRAM address bus bit 10 when SDRENA(D7/0x39FFC1) = "1" P34: I/O port when CFP34(D4/0x402DC) = "0" (default) #BUSREQ: Bus release request input when CFP34(D4/0x402DC) = "1" #CE6: Area 6 chip enable when CFP34(D4/0x402DC) = "1" and IOC34(D4/0x402DE) = "1" GPIO0: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and BREQEN(D2/0x39FFFD) = "0" P35: I/O port when CFP35(D5/0x402DC) = "0" (default) #BUSACK: Bus acknowledge output when CFP35(D5/0x402DC) = "1" and CFP34(D4/0x402DC) = "1" GPIO1: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and BREQEN(D2/0x39FFFD) = "0" EPSON S1C33L03 FUNCTION PART I OUTLINE: LIST OF PINS A-1 Table 3.4 List of Pins for LCD Controller Pin No. I/O Pull-up FPDAT[7:4] Pin name 13-16 O - FPDAT[3:0] GPO[6:3] FPFRAME FPLINE FPSHIFT DRDY(MOD) (FPSHIFT2) LCDPWR 17-20 O - 23 24 25 22 O O O O - - - - 26 O - Pin name Pin No. I/O Pull-up 68 67 129 128 112,113 I O I O I - - - - - 115 - - Pin No. I/O Pull-up /down ICEMD 125 I DSIO 117 I/O #X2SPD 140 I #NMI #RESET 130 69 I I Function 4 high-order bits of data bus for 8-bit LCD panels Data bus for 4-bit LCD panels FPDAT[3:0]: 4 low-order bits of data bus for 8-bit LCD panels GPO[6:3]: General-purpose outputs when a 4-bit LCD panel is used Frame pulse output Line pulse output Shift clock output MOD: LCD backplane bias (for panels other than 8-bit color panel format 1) FPSHIFT2: Second shift clock (for 8-bit color panel format 1) LCD power control output (active high) Table 3.5 List of Pins for Clock Generator OSC1 OSC2 OSC3 OSC4 PLLS[1:0] PLLC B-I Function Low-speed (OSC1) oscillation input (32 kHz crystal oscillator or external clock input) Low-speed (OSC1) oscillation output High-speed (OSC3) oscillation input (crystal/ceramic oscillator or external clock input) High-speed (OSC3) oscillation output PLL set-up pins PLLS1 PLLS0 fin (fOSC3) fout (fPSCIN) 1 1 10-25MHz 20-50MHz 0 1 10-12.5MHz 40-50MHz 0 0 PLL is not used L Capacitor connecting pin for PLL Table 3.6 List of Other Pins Pin name Function Pulldown High-impedance control input pin When this pin is set to High, all the output pins go into high-impedance state. This makes it possible to disable the S1C33 chip on the board. Pull-up Serial I/O pin for debugging This pin is used to communicate with the debugging tool S5U1C33000H. - Clock doubling mode set-up pin 1: CPU clock = bus clock x 1, 0: CPU clock = bus clock x 2 Pull-up NMI request input pin Pull-up Initial reset input pin Note: "#" in the pin names indicates that the signal is low active. S1C33L03 FUNCTION PART EPSON B-I-3-7 Pin I OUTLINE: LIST OF PINS THIS PAGE IS BLANK. B-I-3-8 EPSON S1C33L03 FUNCTION PART S1C33L03 FUNCTION PART II CORE BLOCK II CORE BLOCK: INTRODUCTION A-1 II-1 INTRODUCTION The core block consists of a functional block C33_CORE including CPU, BCU (Bus Control Unit), ITC (Interrupt Controller), CLG (Clock Generator) and DBG (Debug Unit), an I/O pad block for external interface, and an SBUS (Internal Silicon Integration Bus) for interfacing with on-chip Peripheral Macro Cells. C33 DMA Block C33 SDRAM Controller Block C33 LCD Controller Block C33_DMA C33_SDRAMC C33_LCDC (IDMA, HSDMA) (SDRAM interface) (LCD panel interface) Pads Internal RAM (Area 0) CORE_PAD C33 Internal Memory Block C33_CORE (CPU, BCU, ITC, CLG, DBG) Internal ROM (Area 10) Pads Intro C33_SBUS C33_PERI (A/D converter) (Prescaler, 8-bit timer, 16-bit timer, Clock timer, Serial interface, Ports) C33 Analog Block PERI_PAD C33 Core Block C33_ADC Pads C33 Peripheral Block Figure 1.1 Core Block Note: Internal ROM is not provided in the S1C33L03. S1C33L03 FUNCTION PART EPSON B-II B-II-1-1 II CORE BLOCK: INTRODUCTION THIS PAGE IS BLANK. B-II-1-2 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: CPU AND OPERATING MODE A-1 II-2 CPU AND OPERATING MODE CPU The C33 Core Block employs the S1C33000 32-bit RISC type CPU as the core CPU. Since it has a built-in multiplier, all instructions (105 instructions) in the S1C33000 instruction set including the MAC (multiplication and accumulation) instruction and the multiplication/division instructions are available. All the internal registers of the S1C33000 can be used. The CPU registers and CPU address bus can handle 28-bit addresses. However, the core block has a 24-bit external address bus (A[0:23]), so the low-order 24 bits of address data can only be delivered to the external address bus and the internal address bus which is connected to the User Logic Block. Refer to the "S1C33000 Core CPU Manual" for details of the S1C33000. B-II CPU S1C33L03 FUNCTION PART EPSON B-II-2-1 II CORE BLOCK: CPU AND OPERATING MODE Standby Mode The CPU supports three standby modes: two HALT modes and a SLEEP mode. By setting the CPU in the standby mode, power consumption can greatly be reduced. HALT Mode When the CPU executes the halt instruction, it suspends the program execution and enters the HALT mode. The CPU supports two types of HALT modes (basic HALT mode and HALT2 mode) and either can be selected using the HLT2OP (D3) / Clock option register (0x40190). The CPU stops operating in basic HALT mode, so the amount of current consumption can be reduced. The internal peripheral circuits maintain the status (stop/run) before entering HALT mode. The DMA function cannot be used. HALT2 mode stops the external bus control functions including DMA and the bus clock as well as the CPU similar to basic HALT mode. Consequently, HALT2 mode realizes more power saving than the basic HALT mode. The HALT mode is canceled by an initial reset or an interrupt including NMI. This mode is useful for saving power when waiting for an external input or completion of the peripheral circuit operations that do not need to execute the CPU. The CPU transits to program execution status through trap processing when the HALT mode is canceled by an interrupt and executes the interrupt processing routine. The trap processing of the CPU saves the address of the instruction that follows the executed halt instruction into the stack. Therefore, when the interrupt processing routine is terminated by the reti instruction, the program flow returns to the instruction that follows the halt instruction. Note that the HALT mode cannot be canceled with an interrupt factor except for reset and NMI if the PSR is set into interrupt disabled status. SLEEP Mode When the CPU executes the slp instruction, it suspends the program execution and enters SLEEP mode. In SLEEP mode, the CPU and the internal peripheral circuits including the high-speed (OSC3) oscillation circuit stop operating. Thus SLEEP mode can greatly reduce current consumption in comparison to HALT mode. Moreover, the low-speed (OSC1) oscillation circuit and clock timer do not stop operating. The clock function keeps operating in SLEEP mode. SLEEP mode is canceled by an initial reset or an interrupt (NMI, clock timer interrupt, external interrupt such as a key entry). Note that other interrupts by the internal peripheral circuits that use the OSC3 clock cannot be used for canceling SLEEP mode. The CPU transits to program execution status through trap processing when the SLEEP mode is canceled by an interrupt and executes the interrupt processing routine. The trap processing of the CPU saves the address of the instruction that follows the executed slp instruction into the stack. Therefore, when the interrupt processing routine is terminated by the reti instruction, the program flow returns to the instruction that follows the slp instruction. Note that SLEEP mode cannot be canceled with an interrupt factor except for reset and NMI if the PSR is set into interrupt disabled status. B-II-2-2 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: CPU AND OPERATING MODE A-1 Notes on Standby Mode Interrupts The standby mode can be canceled by an interrupt. Therefore, it is necessary to enable the interrupt to be used for canceling the standby mode before setting the CPU in the standby mode. It is also necessary to set the IE (interrupt enable) and IL (interrupt level) bits in the PSR to a condition that can accept the interrupt. Otherwise, the standby mode cannot be canceled even when an interrupt occurs. Refer to "ITC (Interrupt Controller)", for interrupt settings. Oscillation circuit The high-speed (OSC3) oscillation circuit stops in SLEEP mode and restarts oscillating when SLEEP mode is canceled. If the CPU had operated with the OSC3 clock before entering SLEEP mode, the CPU restarts operating with the OSC3 clock immediately after canceling SLEEP mode. However, the OSC3 oscillation needs appropriate stabilization time (10 ms max. under the standard condition in 3.3 V). To restart the CPU after the oscillation stabilizes, a programmable interval can be inserted between cancellation of SLEEP mode and starting the CPU operation. Refer to "CLG (Clock Generator)", for details. The oscillation start time of the high-speed (OSC3) oscillation circuit varies according to the components to be used, board pattern and operating environment. The interval must be set to allow enough margin. BCU When the CPU enters the standby mode, the BCU (bus control unit) stops after the current bus cycle has completed. All the chip enable signals are negated. In basic HALT mode, the BCLK (bus clock) signal is output and DRAM refresh cycles are generated. DMA also operates. In HALT2 or SLEEP mode, the BCLK signal stops, therefore DRAM refresh cycles cannot be generated and DMA stops. Additional The contents of the CPU registers and input/output port status are retained in the standby mode. Almost all control and data registers of the internal peripheral circuits are also retained, note, however, some registers may be changed at the transition to SLEEP mode. Refer to the section of each peripheral circuit for other precautions. Test Mode The C33 Core Block has the ICEMD pin for testing the chip. When this pin is set to High, the IC enters the following state: * All output pins go into high-impedance state except for the clock output pins (OSC2: H, OSC4 H, PLLC: L). * Clock inputs are disabled. OSC1, OSC3 and PLL stop operating. OSC2: H, OSC4 H, PLLC: L * All the pull-up and pull-down resistors enter an inactive state. Leave this pin open or connect to VSS for normal operation. The ICEMD pin has a built-in pull-down resistor. Debug Mode The C33 Core Block supports the debug mode. The debug mode is a CPU function, and realizes single step operation and break functions in the chip itself. Refer to the "S1C33000 Core CPU Manual" for details of the debug mode and the functions. Area 2 in the memory map can only be accessed in the debug mode. In the debug mode, the OSC3 clock is used as the CPU operating clock. Therefore, do not stop the high-speed (OSC3) oscillation circuit when using the debugging functions. Furthermore, only the CPU and BCU operate in the debug mode, and other internal peripheral circuits (except the oscillation circuit) stop operating. S1C33L03 FUNCTION PART EPSON B-II-2-3 B-II CPU II CORE BLOCK: CPU AND OPERATING MODE Trap Table Table 2.1 shows the trap table in the C33 Core. Refer to the "S1C33000 Core CPU Manual" for details of exceptions and Section II-5 in this manual, "ITC (Interrupt Controller)", for interrupts. Serial interface Ch.2 and Ch.3 interrupts share the trap table for port input interrupts and 16-bit timer interrupts. Refer to Section III-8, "Serial Interface", for details of the settings. Table 2.1 Trap Table HEX No. Vector number (Hex address) 0 0(Base) 1-3 4(Base+10) 5 6(Base+18) 0x0 or 0x60000 8(Base+1C) 9-11 12(Base+30) 13(Base+34) 14(Base+38) 15(Base+3C) 16(Base+40) 17(Base+44) 18(Base+48) 19(Base+4C) 20(Base+50) 21(Base+54) 22(Base+58) 23(Base+5C) 24(Base+60) 25(Base+64) 26(Base+68) 27-29 30(Base+78) 31(Base+7C) 32-33 34(Base+88) 35(Base+8C) 36-37 38(Base+98) 39(Base+9C) 40-41 42(Base+A8) 43(Base+AC) 44-45 46(Base+B8) 47(Base+BC) 48-49 50(Base+C8) 51(Base+CC) 52(Base+D0) 53(Base+D4) 54(Base+D8) 55(Base+DC) 4 5 6 7 8 C D E F 10 11 12 13 14 15 16 17 18 19 1A 1E 1F 22 23 26 27 2A 2B 2E 2F 32 33 34 35 36 37 B-II-2-4 Exception/interrupt name Reset reserved Zero division reserved Address error exception Debugging exception NMI reserved Software exception 0 Software exception 1 Software exception 2 Software exception 3 Port input interrupt 0 Port input interrupt 1 Port input interrupt 2 Port input interrupt 3 Key input interrupt 0 Key input interrupt 1 High-speed DMA Ch.0 High-speed DMA Ch.1 High-speed DMA Ch.2 High-speed DMA Ch.3 IDMA reserved 16-bit programmable timer 0 reserved 16-bit programmable timer 1 reserved 16-bit programmable timer 2 reserved 16-bit programmable timer 3 reserved 16-bit programmable timer 4 reserved 16-bit programmable timer 5 8-bit programmable timer Exception/interrupt factor Low input to the reset pin - Division instruction - Memory access instruction brk instruction, etc. Low input to the NMI pin - int instruction int instruction int instruction int instruction Edge (rising or falling) or level (High or Low) Edge (rising or falling) or level (High or Low) Edge (rising or falling) or level (High or Low) Edge (rising or falling) or level (High or Low) Rising or falling edge Rising or falling edge High-speed DMA Ch.0, end of transfer High-speed DMA Ch.1, end of transfer High-speed DMA Ch.2, end of transfer High-speed DMA Ch.3, end of transfer Intelligent DMA, end of transfer - Timer 0 comparison B Timer 0 comparison A - Timer 1 comparison B Timer 1 comparison A - Timer 2 comparison B Timer 2 comparison A - Timer 3 comparison B Timer 3 comparison A - Timer 4 comparison B Timer 4 comparison A - Timer 5 comparison B Timer 5 comparison A Timer 0 underflow Timer 1 underflow Timer 2 underflow Timer 3 underflow EPSON IDMA Ch. - - - - - - - - - - - - 1 2 3 4 - - 5 6 - - - - 7 8 - 9 10 - 11 12 - 13 14 - 15 16 - 17 18 19 20 21 22 Priority High Low S1C33L03 FUNCTION PART II CORE BLOCK: CPU AND OPERATING MODE HEX No. 38 39 3A Vector number (Hex address) 40 41 56(Base+E0) 57(Base+E4) 58(Base+E8) 59 60(Base+F0) 61(Base+F4) 62(Base+F8) 63 64(Base+100) 65(Base+104) 44 45 46 47 66-67 68(Base+110) 69(Base+114) 70(Base+118) 71(Base+11C) 3C 3D 3E Exception/interrupt name Serial interface Ch.0 reserved Serial interface Ch.1 reserved A/D converter Clock timer reserved Port input interrupt 4 Port input interrupt 5 Port input interrupt 6 Port input interrupt 7 Exception/interrupt factor Receive error Receive buffer full Transmit buffer empty - Receive error Receive buffer full Transmit buffer empty - A/D converter, end of conversion Falling edge of 32 Hz, 8 Hz, 2 Hz or 1 Hz signal 1-minuet, 1-hour or specified time count up - Edge (rising or falling) or level (High or Low) Edge (rising or falling) or level (High or Low) Edge (rising or falling) or level (High or Low) Edge (rising or falling) or level (High or Low) IDMA Ch. - 23 24 - - 25 26 - 27 - - 28 29 30 31 A-1 Priority High Low Base = Set value in the TTBR register (0x48134 to 0x48137); 0xC00000 by default. B-II CPU S1C33L03 FUNCTION PART EPSON B-II-2-5 II CORE BLOCK: CPU AND OPERATING MODE THIS PAGE IS BLANK. B-II-2-6 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: INITIAL RESET A-1 II-3 INITIAL RESET Pins for Initial Reset Table 3.1 shows the pins used for initial reset. Table 3.1 Pins for Initial Reset Pin name I/O #RESET I #NMI I Function Initial reset input pin (Low active) Low: Resets the CPU. NMI request input pin This pin is also used for selecting a reset method. High: Cold start Low: Hot start The chip is reset when the #RESET pin goes low and starts operating at the rising edge of the reset signal. The CPU and internal peripheral circuits are initialized while the #RESET pin is low. Cold Start and Hot Start B-II The CPU supports two initial reset methods: cold start and hot start. The #NMI pin is used with the #RESET pin to set this condition. The differences between cold start and hot start are shown in Table 3.2. Reset Table 3.2 Differences between Cold Start and Hot Start Setup contents Cold start Hot start Reset condition #RESET = low & #NMI = high #RESET = low & #NMI = low CPU: PC The vector at the boot address is loaded to the PC. CPU: PSR All the PSR bits are reset to 0. CPU: Other registers Undefined CPU: Operating clock The CPU operates with the OSC3 clock. External bus status (0x48120-0x4813F) Initialized Status is retained. Oscillation circuit Both the OSC1 and OSC3 circuits start oscillating. I/O pin status (0x402C0-0x402DF) Initialized Status is retained. Other peripheral circuit Initialized or undefined Since cold start initializes all the internal peripheral circuits as well as the CPU, it is useful as a power-on reset. Hot start initializes the CPU and peripheral circuits, but does not reset the bus control unit and the input, output and I/O port status. It is therefore useful as a reset that maintains the external bus and I/O pin status during operation. The #NMI pin that specifies the reset method should be set following the timing chart shown in Figure 3.1. Cold start is generated (#RESET = low & #NMI = high) Hot start is generated (#RESET = low & #NMI = low) #NMI #NMI #RESET #RESET #NMI must be set to high longer than the reset pulse width. #NMI must be set to low longer than the reset pulse width. (1) Cold start (2) Hot start Figure 3.1 Setup of #RESET and #NMI Pins S1C33L03 FUNCTION PART EPSON B-II-3-1 II CORE BLOCK: INITIAL RESET Power-on Reset Be sure to reset (cold start) the chip after turning on the power to start operating. Since the #RESET pin is directly connected to an input gate, a power-on reset circuit should be configured outside the chip. An initial reset (#RESET = low) turns the high-speed (OSC3) oscillation circuit on. The CPU starts operating with the OSC3 clock at the rising edge of the reset signal. The high-speed (OSC3) oscillation circuit takes time (10 ms max. under the standard condition in 3.3 V) for the oscillation to stabilize, therefore initial reset must be released after an appropriate oscillation-stabilization time has passed in order to start up the CPU without fault. The initial reset pulse width must be exceeded the oscillation-stabilization time. Figure 3.2 shows a power-on reset timing chart. 3.0 V (VDD = 3.3 V) VDD tSTA3 (OSC3 oscillation start time) or more 0.5VDD #RESET Power on 0.1VDD Figure 3.2 Power-on Reset Timing Maintain the #RESET pin at 0.1*VDD or less (low level) after turning the power on until the supply voltage rises at least to the oscillation start voltage (3.0 V). Furthermore, maintain the #RESET pin at 0.5*VDD or less until the high-speed (OSC3) oscillation circuit stabilizes oscillating. Note: The OSC3 oscillation start time varies due to the elements used, board pattern and operating environment, therefore allow enough margin for the reset-release time. Refer to "Oscillation Characteristics", in which an example of oscillation start time is provided. Reset Pulse A low pulse can be input to the #RESET pin for resetting the chip being operated. The minimum reset pulse width is provided in "AC Characteristics". Be sure to input a pulse that has a pulse width longer than the minimum value. To reset the chip when the high-speed (OSC3) oscillation circuit is in off status, the pulse width must be extended until the oscillation stabilizes similarly to the power-on reset. Be aware that a short reset pulse may cause an operation error. B-II-3-2 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: INITIAL RESET A-1 Boot Address When the core CPU is initially reset, it reads the reset vector (program start address) from the boot address (0x0C00000) and loads the vector to the PC (program counter). Then the CPU starts executing the program from the address when the #RESET pin goes high. The trap table in which trap vectors for interrupts and other trap factors are written also begins from the boot address by the default setting. (Refer to the "S1C33000 Core CPU Manual" for details of the trap table.) The trap table base address can also be changed to a 1KB boundary address using the TTBR register (0x48134 to 0x48137). Notes Related to Initial Reset Core CPU Since the all registers except for the PC and PSR are indeterminate at initial reset, they should be initialized by a program. In particular, the SP (stack pointer) must be initialized before accessing the stack area. NMI requests are disabled until any value is written to the SP. The initialization is necessary when the CPU is cold-started. B-II Internal RAM The contents of the internal RAM are indeterminate at initial reset. Initialize the area to be used if necessary. Reset High-speed (OSC3) oscillation circuit An initial reset activates the high-speed (OSC3) oscillation circuit and the CPU starts operating with the OSC3 clock after the initial reset is released. In order to prevent a malfunction of the CPU due to an unstabilized clock, the #RESET pin must be maintained at low until the OSC3 oscillation stabilizes when performing a power-on reset or resetting while the high-speed (OSC3) oscillation circuit is stopped. Low-speed (OSC1) oscillation circuit A power-on reset or an initial reset when the low-speed (OSC1) oscillation circuit is off starts the OSC1 oscillation. The low-speed (OSC1) oscillation circuit takes a longer stabilization time (3 sec max. under the standard condition) than the high-speed (OSC3) oscillation circuit. In order to prevent a malfunction due to an unstabilized clock, do not use the OSC1 clock until the stabilization time has passed. BCU (Bus Control Unit) Cold-start initializes the control registers for the BCU (bus control unit). Therefore, it is necessary to set up all the bus conditions. Hot-start retains the previous bus conditions before an initial reset. Input/output ports and input/output pins Cold start initializes the control and data registers for the input and I/O ports. Hot start retains the contents of the control registers and input/output pin status before an initial reset. However, when the pins are used for the internal peripheral circuits, it is necessary to set up the control registers of the peripheral circuit because they are initialized by an initial reset. Other internal peripheral circuits The control and data registers of peripheral circuits other than those listed above are initialized with the predefined values or become indeterminate regardless of the reset method (cold start or hot start). Therefore, it is necessary to set up the peripheral circuit conditions. Refer to the I/O maps or explanation of each peripheral circuit section for initial settings of the peripheral circuits. S1C33L03 FUNCTION PART EPSON B-II-3-3 II CORE BLOCK: INITIAL RESET THIS PAGE IS BLANK. B-II-3-4 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: BCU (Bus Control Unit) A-1 II-4 BCU (Bus Control Unit) The BCU (Bus Control Unit) provides an interface for external devices and on-chip user logic block. The types and sizes of memory and peripheral I/O devices can be set for each area of the memory map and can be controlled directly by the BCU. This unit also supports a direct interface for DRAM and burst ROM. This chapter describes how to control the external and internal system interface, and how it operates. Note: The control registers of the external system interface shown in this chapter are mapped to the internal 16-bit I/O area. Therefore, the addresses of these control registers are indicated by halfword (16-bit) addresses unless otherwise specified. Note that the control registers can be accessed in bytes, half-words, or words. Pin Assignment for External System Interface I/O Pin List External I/O pins Table 4.1 lists the pins used for the external system interface. B-II Table 4.1 I/O Pin List Pin name A[0]/#BSL A[10:1]/SDA[9:0] A11 A[13:12]/SDA[12:11] A[15:14]/SDBA[1:0] I/O A[23:16] D[15:0] #CE10EX/#CE9&10EX #CE9/#CE17/#CE17&18 #CE8/#RAS1/#CE14/#RAS3/#SDCE1 #CE7/#RAS0/#CE13/#RAS2/#SDCE0 #CE6/#CE7&8 #CE5/#CE15/#CE15&16 #CE4/#CE11/#CE11&12 #RD #EMEMRD #WRL/#WR/#WE #WRH/#BSH #HCAS/#SDCAS #LCAS/#SDRAS BCLK/SDCLK P35/#BUSACK/GPIO1 P34/#BUSREQ/#CE6/GPIO0 O O O O O O I/O O O O O O O O O O O O O O O I/O I/O P33/#DMAACK1/SIN3/SDA10 I/O P32/#DMAACK0/#SRDY3/HDQM I/O P31/#BUSGET/#GARD/GPIO2 I/O P30/#WAIT/#CE4&5 P21/#DWE/#GAAS/#SDWE P20/#DRD/SDCKE P15/EXCL4/#DMAEND0/#SCLK3/LDQM I/O I/O I/O I/O #X2SPD I EA10MD[1:0] I S1C33L03 FUNCTION PART Function Address bus (A0) / Bus strobe (Low-byte) Address bus (A1-A10) / SDRAM address bus (SDA0-SDA9) Address bus (A11) Address bus (A12-A13) / SDRAM address bus (SDA11-SDA12) Address bus (A14-A15) / SDRAM bank select (SDBA0-SDBA1) BCU Address bus (A16-A23) Data bus (D0-D15) Area 10/(9&10) external memory chip enable Area 9/17/(17&18) chip enable Area 8/14 chip enable / DRAM Row strobe / SDRAM chip enable 1 Area 7/13 chip enable / DRAM Row strobe / SDRAM chip enable 0 Area 6/(7&8) chip enable Area 5/15/(15&16) chip enable Area 4/11/(11&12) chip enable Read signal Read signal for area 3/10 emulation mode Write (Low-byte) / Write / DRAM write Write (High-byte) / Bus strobe (High-byte) DRAM column address strobe (High-byte) / SDRAM column address strobe DRAM column address strobe (Low-byte) / SDRAM row address strobe Bus clock output / SDRAM operating clock I/O port / Bus request acknowledge / LCDC general-purpose input/output I/O port / Bus release request / Area 6 chip enable / LCDC general-purpose input/output I/O port / HSDMA Ch. 1 acknowledge output / Serial I/F Ch. 3 data input / SDRAM address bus 10 I/O port / HSDMA Ch. 0 acknowledge output / Serial I/F Ch. 3 ready signal output / SDRAM data (high byte) input/output mask signal output I/O port / Bus status monitor signal output / Area read signal output for GA / LCDC general-purpose input/output I/O port / Wait cycle request / Areas 4&5 chip enable I/O port / DRAM write (Low-byte) / Area address strobe output for GA / SDRAM write I/O port / DRAM read / SDRAM clock enable I/O port / 16-bit timer 4 event counter input / HSDMA Ch. 0 end-of-transfer signal output / Serial I/F Ch. 3 clock input/output / SDRAM data (low byte) input/output mask signal output CPU - BCLK clock ratio 1: CPU clock = Bus clock, 0: CPU clock = Bus clock x 2 Area 10 boot mode selection 11: External ROM, 10: Internal ROM EPSON B-II-4-1 II CORE BLOCK: BCU (Bus Control Unit) User interface signals Table 4.2 List of User Interface Signals Signal name I/O Internal_addr0 O Internal_addr[23:1] Internal_dout[15:0] O O Internal_din[15:0] I Internal_ce4_x Internal_ce5_x Internal_ce6_x Internal_rd_x O Internal_wrl_x O Internal_wrh_x O Internal_osc3_clk O Internal_pll_clk O Internal_wait_x I Internal_irrd_x O Internal_k60-k67 I O Function * Address bus (a0) when SBUSST(D3/0x4812E) = "0" (default) * Bus strobe (low byte) signal (#BSL) when SBUSST(D3/0x4812E) = "1" Address bus (a1 to a23) Output data bus (dout0 to dout15) This data bus is used when the CPU writes data to the on-chip user logic. Input data bus (din0 to din15) This data bus is used when the CPU reads data from the on-chip user logic. Areas 6-4 chip enable signals These signals go low when the CPU accesses the user logic circuits that are mapped to Areas 6-4. Read signal This signal goes low when the CPU reads data from the user logic. * Write (low byte) signal (#WRL) when SBUSST(D3/0x4812E) = "0" (default) * Write signal (#WR) when SBUSST(D3/0x4812E) = "1" This signal goes low when the CPU write 8 low-order bit data to the user logic. * Write (high byte) signal (#WRH) when SBUSST(D3/0x4812E) = "0" (default) * Bus strobe (high byte) signal (#BSH) when SBUSST(D3/0x4812E) = "1" This signal goes low when the CPU write 8 high-order bit data to the user logic. High-speed (OSC3) oscillation clock output This can be used as a source clock for the user logic. PLL output clock This can be used as a source clock for the user logic. Wait cycle request input The user logic can request to insert wait cycles by setting this signal to low. Instruction fetch indicator signal This signal goes low when the CPU is in an instruction fetch cycle. Input signals These signals are connected to the input ports K60-K67. The user logic can request HSDMA, IDMA and interrupts using these signals. The user logic can also be used as input ports with these signals. The internal bus signals are available when an internal access area is set using the BCU register. The bus conditions can be programmed using the BCU registers similar to the external bus. B-II-4-2 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: BCU (Bus Control Unit) A-1 Combination of System Bus Control Signals The bus control signal pins that have two or more functions have their functionality determined when an interface method is selected by a program. The BCU contains an ordinary external system interface (two interface method are supported) and a DRAM interface. Table 4.3 Interface Selection Interface type Interface method External system interface DRAM interface A0 system (default) #BSL system 2CAS system (fixed) Control bit SBUSST(D3/0x4812E) = "0" SBUSST(D3/0x4812E) = "1" None SBUSST is initialized to "0" at cold start. When the IC is hot-started, these bits retain their status before the chip was reset. Table 4.4 shows combinations of control signals classified by each interface method. Table 4.4 Combinations of Bus Control Signals External system interface A0 system #BSL system A0 #WRL #WRH - - #CEx #BSL (little endian) / #BSH (big endian) 1 #WR #BSH (little endian) / #BSL (big endian) 1 - - #CEx DRAM interface 2CAS system - B-II #WE - #HCAS #LCAS #RASx 2 BCU 1 In the #BSL system, the A0 and #WRH pin functions change according to the endian selected (little endian or big endian). 2 When using DRAM, the #CE output pins in areas 7-8 (areas 13-14) function as the #RAS1-2 (#RAS3-4) pins. S1C33L03 FUNCTION PART EPSON B-II-4-3 II CORE BLOCK: BCU (Bus Control Unit) Memory Area Memory Map Figure 4.1 shows the memory map supported by the BCU. Area Area 9 SRAM type Burst ROM type 8 or 16 bits Area 8 SRAM type DRAM type 8 or 16 bits Area 7 SRAM type DRAM type 8 or 16 bits Area 6 SRAM type Area 5 0x0800000 0x07FFFFF 0x0400000 0x03FFFFF 0x0380000 0x037FFFF 0x0300000 0x02FFFFF Area 0 External I/O (16-bit device) External I/O (8-bit device) 0x0080000 0x007FFFF 0x0060000 0x005FFFF 0x0050000 0x004FFFF 0x0040000 0x003FFFF 0x0030000 0x002FFFF 32 bits SRAM type 8 or 16 bits SRAM type DRAM type 8 or 16 bits Area 13 SRAM type DRAM type 8 or 16 bits External memory (1MB) 0x0100000 0x00FFFFF Area 15 Area 14 0x0200000 0x01FFFFF Fixed at 3 cycles 2 or 4 cycles SRAM type 8 or 16 bits External memory (1MB) 16 bits 8, 16 bits Area 16 External memory (2MB) Fixed at 1 cycle Area 1 SRAM type 8 or 16 bits 0x0600000 0x05FFFFF 16 bits Area 2 Area 17 External memory (2MB) SRAM type 8 or 16 bits Area 3 SRAM type 8 or 16 bits External memory (4MB) SRAM type 8 or 16 bits Area 4 Area Area 18 Address 0x0BFFFFF Area 12 (Reserved) For middleware use Internal I/O Area 11 SRAM type Burst ROM type 8 or 16 bits External memory (16MB) External memory (16MB) External memory (16MB) External memory (16MB) External memory (16MB) 0x2000000 0x1FFFFFF External memory (8MB) 0x1800000 0x17FFFFF SRAM type 8 or 16 bits Area 10 External memory (16MB) 0x3000000 0x2FFFFFF SRAM type 8 or 16 bits (Reserved) For CPU core or debug mode (Mirror of internal I/O) Address 0xFFFFFFF 0xD000000 0xCFFFFFF 0xC000000 0xBFFFFFF 0x9000000 0x8FFFFFF 0x8000000 0x7FFFFFF 0x7000000 0x6FFFFFF 0x6000000 0x5FFFFFF 0x5000000 0x4FFFFFF 0x4000000 0x3FFFFFF External memory (8MB) 0x1000000 0x0FFFFFF External memory (4MB) 0x0C00000 (Mirror of internal I/O) Internal RAM Fixed at 1 cycle 0x0000000 Figure 4.1 Memory Map Basically, Areas 0 to 3 are internal memory areas and Areas 4 to 18 are external memory areas. Area 0 is normally used for a built-in RAM. The built-in memory is mapped from the beginning of the area. Area 1 is reserved for the I/O memory of the on-chip functional blocks. Address 0x0040000 to address 0x004FFFF are used as the control registers and address 0x0050000 to 0x005FFFF are used as the mirror area. Area 2 is used in debug mode only and it cannot be accessed in user mode (normal program execution status). Area 3 is reserved for S1C33 middlewares. Area 4 to 18 can also be configured as internal memory areas using the control register and they can be used for user logic circuits. Note: Addresses 0x39FFC0-0x39FFCD in Area 6 are reserved as the internal memory area for the control I/O memory of the SDRAM controller. Pay attention to this area since it must be accessed when controlling the SDRAM self-refresh mode or other SDRAM functions. B-II-4-4 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: BCU (Bus Control Unit) A-1 External Memory Map and Chip Enable The BCU has a 24-bit external address bus (A[23:0]) and a 16-bit external data bus (D[15:0]), allowing an address space of up to 16 MB to be accessed with one chip enable signal. By default, the address space is divided into 11 areas (areas 0 to 10) for management purposes. Of these, areas 4 to 10 are open to an external system, each provided with an independent chip-enable pin (#CE[10:4]). The C33 Core Block is limited to 24 available pins for the address bus and 7 pins for the #CE output due to its package structure. However, the #CE[4:10] output pins can be switched to the high-order area chip enable output pins as shown in Table 4.5 using software. CEFUNC[1:0] (D[A:9]) / DRAM timing set-up register (0x48130) is used for this switching. Table 4.5 Switching of #CE Output Pin CEFUNC = "00" #CE4 #CE5 #CE6 #CE7/#RAS0 #CE8/#RAS1 #CE9 #CE10EX #CE4 #CE5 #CE6 #CE7/#RAS0 #CE8/#RAS1 #CE9 #CE10EX CEFUNC = "01" #CE11 #CE15 #CE6 #CE13/#RAS2 #CE14/#RAS3 #CE17 #CE10EX CEFUNC = "1x" #CE11+#CE12 #CE15+#CE16 #CE7+#CE8 #CE13/#RAS2 #CE14/#RAS3 #CE17+#CE18 #CE9+#CE10EX (Default: CEFUNC = "00") B-II The high-order areas that are made available for use by writing "01" to CEFUNC can be larger in size than the default low-order areas. For example, when using DRAM in default settings, the available space is 4 MB in areas 7 and 8. However, if areas 13 and 14 are used, up to 32 MB of DRAM can be used. The same applies to the other areas. Furthermore, when CEFUNC is set to "10" or "11", five chip enable signals are expanded into two area size. Although the C33 Core Block has only 24 address output pins, it features 28-bit internal address processing. Figure 4.2 shows a memory map for an external system. Area Area 10 (#CE10) SRAM type Burst ROM type 8 or 16 bits Area 9 (#CE9) SRAM type Burst ROM type 8 or 16 bits Area 8 (#CE8/#RAS1) SRAM type DRAM type 8 or 16 bits Area 7 (#CE7/#RAS0) SRAM type DRAM type 8 or 16 bits Area 6 (#CE6) SRAM type Area 5 (#CE5) External memory 6 (4MB) 0x0C00000 0x0BFFFFF External memory 5 (4MB) 0x0800000 0x07FFFFF External memory 4 (2MB) 0x0600000 0x05FFFFF External memory 3 (2MB) 0x0400000 0x03FFFFF 0x0380000 0x037FFFF 0x0300000 0x02FFFFF SRAM type 8 or 16 bits Area 4 (#CE4) Area Area 17 (#CE17) Address 0x0FFFFFF External I/O (16-bit device) External I/O (8-bit device) SRAM type DRAM type 8 or 16 bits Area 13 (#CE13/#RAS2) SRAM type DRAM type 8 or 16 bits Area 11 (#CE11) SRAM type 8 or 16 bits Area 10 (#CE10) External memory 2 (1MB) 0x0200000 0x01FFFFF SRAM type 8 or 16 bits Address 0xBFFFFFF SRAM type 0x9000000 8 or 16 bits 0x8FFFFFF 0x8000000 Area 15 (#CE15) 0x5FFFFFF SRAM type 0x5000000 8 or 16 bits 0x4FFFFFF 0x4000000 Area 14 (#CE14/#RAS3) 0x3FFFFFF External memory 1 (1MB) SRAM type Burst ROM type 8 or 16 bits Area 6 (#CE6) SRAM type 0x0100000 CEFUNC = "00" S1C33L03 FUNCTION PART (Mirror of External memory 6) External memory 6 (16MB) (Mirror of External memory 5) External memory 5 (16MB) External memory 4 (16MB) 0x3000000 0x2FFFFFF External memory 3 (16MB) 0x2000000 0x17FFFFF External memory 2 (8MB) 0x1000000 0x0FFFFFF External memory 1 (4MB) 0x0C00000 0x03FFFFF 0x0380000 0x037FFFF 0x0300000 External I/O (16-bit device) External I/O (8-bit device) CEFUNC = "01" EPSON B-II-4-5 BCU II CORE BLOCK: BCU (Bus Control Unit) Area Area 17-18 (#CE17+18) SRAM type 8 or 16 bits Areas 15-16 (#CE15+16) SRAM type 8 or 16 bits Area 14 (#CE14/#RAS3) SRAM type DRAM type 8 or 16 bits Area 13 (#CE13/#RAS2) SRAM type DRAM type 8 or 16 bits Areas 11-12 (#CE11+12) SRAM type 8 or 16 bits Areas 9-10 (#CE9+10EX) SRAM type Burst ROM type 8 or 16 bits Areas 7-8 (#CE7+8) SRAM type 8 or 16 bits Address 0xFFFFFFF 0xD000000 0xCFFFFFF 0xC000000 0xBFFFFFF 0x9000000 0x8FFFFFF 0x8000000 0x7FFFFFF 0x7000000 0x6FFFFFF 0x6000000 0x5FFFFFF 0x5000000 0x4FFFFFF 0x4000000 0x3FFFFFF (Mirror of External memory 7') External memory 7' (16MB) (Mirror of External memory 7) External memory 7 (16MB) (Mirror of External memory 6') External memory 6' (16MB) (Mirror of External memory 6) External memory 6 (16MB) External memory 5 (16MB) 0x3000000 0x2FFFFFF External memory 4 (16MB) 0x2000000 0x1FFFFFF External memory 3 (16MB) 0x1000000 0x0FFFFFF External memory 2 (8MB) 0x0800000 0x07FFFFF External memory 1 (4MB) 0x0400000 CEFUNC = "10" or "11" Figure 4.2 External System Memory Map Furthermore, the #CE4+#CE5 and #CE6 signals can be output from the P30 and P34 terminals, respectively. This function expands the accessible area when CEFUNC is set to "01, "10" or "11". To output the #CE4+#CE5 signal from the P30 terminal: CFP30 (D0)/P3 function select register (0x402DC) = "1" IOC30 (D0)/P3 I/O control register (0x402DE) = "1" To output the #CE6 signal from the P34 terminal: CFP34 (D4)/P3 function select register (0x402DC) = "1" IOC34 (D4)/P3 I/O control register (0x402DE) = "1" The P30 and P34 terminals are set for the general I/O ports at initial reset. The P30 and P34 terminals are shared with the #WAIT input and the #BUSREQ input, respectively. Therefore, when using the #WAIT and #BUSREQ signals, these terminals cannot be used for #CE4+#CE5 and #CE6 outputs. B-II-4-6 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: BCU (Bus Control Unit) A-1 Using Internal Memory on External Memory Area The BCU allows using of an internal memory in the external memory areas. The AxxIO bit in the access control register (0x48132) is used to select either internal access or external access. When "1" is written, the internal device will be accessed and when "0" is written, the external device is accessed (external access by default). The bit names and the corresponding areas are as follows: A18IO (DF): Areas 17 and 18 A16IO (DE): Areas 15 and 16 A14IO (DD): Areas 13 and 14 A12IO (DC): Areas 11 and 12 A8IO (DA): Areas 7 and 8 A6IO (D9): Area 6 A5IO (D8): Areas 4 and 5 Exclusive Signals for Areas Areas can be accessed using the exclusive signals (address strobe and read signals) as well as the common control signals. To use these exclusive signals, they should be configured using G/A read signal control register (0x48138). The AxxAS bit is used to enable/disable the address strobe signal, and the AxxRD bit is used to enable/disable the read signal. When "1" is written to the bit, the exclusive signal for the corresponding area(s) is enabled and when "0" is written, it is disabled (disabled by default). The bit names and the corresponding areas are as follows: A18AS (DF), A18RD (D7): Areas 17 and 18 A16AS (DE), A16RD (D6): Areas 15 and 16 A14AS (DD), A14RD (D5): Areas 13 and 14 A12AS (DC), A12RD (D4): Areas 11 and 12 A8AS (DA), A8RD (D2): Areas 7 and 8 A6AS (D9), A6RD (D1): Area 6 A5AS (D8), A5RD (D0): Areas 4 and 5 #CE selected with AxxAS (ORed) #WRH #WRL #RD #CE selected with AxxRD (ORed) Figure 4.3 #GAAS and #GARD Signals #GAAS P21 #GARD P31 The address strobe signal and the read signal are output from the P21 pin and P31 pin, respectively. Therefore, when using these signals, the pin(s) must be configured for exclusive signal output using the port function select register and port function extension register. To output the exclusive address strobe signal #GAAS: CFEX2 (D2)/Port function extension register (0x402DF) = "1" To output the exclusive address strobe signal #GARD: CFEX3 (D3)/Port function extension register (0x402DF) = "1" These signals are common used to all the above areas, so when two or more areas are selected to output the exclusive signal, OR condition is applied. S1C33L03 FUNCTION PART EPSON B-II-4-7 B-II BCU II CORE BLOCK: BCU (Bus Control Unit) Area 10 Area 10 is an external memory area that includes the boot address (0xC00000). This area supports two boot modes. Note: Internal ROM is not provided in the S1C33L03. Area 10 boot mode The boot mode can be configured using the external pins EA10MD[1:0]. Table 4.6 Area 10 Boot Mode Selection EA10MD[1:0] pins 10 11 Area 10 boot mode Internal ROM boot mode External ROM boot mode Internal ROM boot mode The CPU boots by the internal ROM mapped to area 10. The internal ROM size should be selected from among eight types (min. 16 KB, max. 2 MB) using the A10IR[2:0] (D[E:C])/Areas 10-9 set-up register (0x48126). This ROM begins with address 0xC00000 and can be read in one cycle the same as that of area 3. For the remained area within area 10, the external memory will be accessed if it is available. External ROM boot mode The CPU boots by the external ROM (ROM, Flash, SRAM, etc.). This mode uses the bus condition set by the BCU registers for area 10. Setting the internal ROM size When a boot mode other than external ROM boot mode is used, the internal ROM or emulation memory size should be set using A10IR[2:0] (D[E:C)/Areas 10-9 set-up register (0x48126). Table 4.7 Area 10 Internal ROM Size B-II-4-8 A10IR2 A10IR1 A10IR0 ROM size 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 16 KB 32 KB 64 KB 128 KB 256 KB 512 KB 1 MB 2 MB (default) EPSON S1C33L03 FUNCTION PART II CORE BLOCK: BCU (Bus Control Unit) A-1 Area 10 memory map Figure 4.4 shows the memory map of area 10. External ROM boot mode 0x0FFFFFF Other modes 0x0FFFFFF Area 10 Area 10 External memory is accessed. External memory is accessed. Set-up example 25 MHz 5 wait Set-up example 25 MHz 5 wait Internal or emulation memory is accessed. 0x0C00000 0x0C00000 Set-up example 25 MHz (#X2SPD = "1") 25 MHz (#X2SPD = "0") No wait 16KB, 32KB, 64KB, 128KB 256KB, 512KB, 1MB or 2MB selected by A10IR[2:0] B-II Figure 4.4 Area 10 Memory Map Area 3 Area 3 is reserved for S1C33 middleware. To use this area, external emulation memory is used. When external emulation memory is used, A3EEN (DB/0x48130) must be set to "1". BCU Table 4.8 Area 3 Mode Selection A3EEN 0 1 S1C33L03 FUNCTION PART Area 3 mode Emulation mode Unused EPSON B-II-4-9 II CORE BLOCK: BCU (Bus Control Unit) Setting External Bus Conditions The type, size, and wait conditions of a device connected to the external bus can be individually set for each area using the control register (0x48120 to 0x48130). The following explains the available setup conditions individually for each area. For details on how to set the DRAM interface conditions, refer to "DRAM Direct Interface". The control register used to set bus conditions is initialized at cold start. Therefore, please set up these registers again using software according to the external device configuration and specifications. When the IC is hot-started, the setup contents and pins retain their previous status before a reset. Setting Device Type and Size Table 4.9 shows the types of devices that can be connected directly to each area. Table 4.9 Device Type Area SRAM type DRAM type Burst ROM type Control bit 18-15 14 13 12,11 10 9 8 7 6-4 X X X X X X X X X X X X None A14DRA(D8)/Areas 14-13 set-up register(0x48122) A13DRA(D7)/Areas 14-13 set-up register(0x48122) None A10DRA(D8)/Areas 10-9 set-up register(0x48126) A9DRA(D7)/Areas 10-9 set-up register(0x48126) A8DRA(D8)/Areas 8-7 set-up register(0x48128) A7DRA(D7)/Areas 8-7 set-up register(0x48128) None : Can be connected X: Cannot be connected When connecting burst ROM or DRAM, write "1" to each corresponding control bit. These control bits are reset to "0" (SRAM type) at cold start. The device size can be set to 8 or 16 bits once every two areas except for area 6. Area 6 alone has its first half (0x300000-0x37FFFF) fixed to an 8-bit device and the second half (0x380000-0x3FFFFF) fixed to a 16-bit device. Table 4.10 Device Size Control Bits Area 18, 17 16, 15 14, 13 12, 11 10, 9 8, 7 5, 4 Control bit A18SZ(DE)/Areas 18-15 set-up register(0x48120) A16SZ(D6)/Areas 18-15 set-up register(0x48120) A14SZ(D6)/Areas 14-13 set-up register(0x48122) A12SZ(D6)/Areas 12-11 set-up register(0x48124) A10SZ(D6)/Areas 10-9 set-up register(0x48126) A8SZ(D6)/Areas 8-7 set-up register(0x48128) A5SZ(D6)/Areas 6-4 set-up register(0x4812A) At cold start, each area by default is set to 16 bits. When using an 8-bit device, write "1" to the control bit. Note: The BCU supports 16-bit burst ROM. Therefore, when connecting burst ROM to area 10 or area 9, do not set the device size to 8 bits (A10SZ = "1"). For differences in bus operation due to the device size and access data size, refer to "Bus Operation of External Memory". B-II-4-10 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: BCU (Bus Control Unit) A-1 Setting SRAM Timing Conditions The areas set for the SRAM allow wait cycles and output disable delay time to be set. Number of wait cycles: 0 to 7 (incremented in units of one cycle) Output disable delay time: 0.5, 1.5, 2.5, 3.5 cycles This selection can be made once every two areas except for area 6. Table 4.11 Timing Condition Setting Bits (for SRAM type) Area Number of wait cycles Output disable delay time Control register 18, 17 16, 15 14, 13 12, 11 10, 9 8, 7 6 5, 4 A18WT[2:0](D[A:8]) A16WT[2:0](D[2:0]) A14WT[2:0](D[2:0]) A12WT[2:0](D[2:0]) A10WT[2:0](D[2:0]) A8WT[2:0](D[2:0]) A6WT[2:0](D[A:8]) A5WT[2:0](D[2:0]) A18DF[1:0](D[D:C]) A16DF[1:0](D[5:4]) A14DF[1:0](D[5:4]) A12DF[1:0](D[5:4]) A10DF[1:0](D[5:4]) A8DF[1:0](D[5:4]) A6DF[1:0](D[D:C]) A5DF[1:0](D[5:4]) Areas 18-15 set-up register(0x48120) Areas 18-15 set-up register(0x48120) Areas 14-13 set-up register(0x48122) Areas 12-11 set-up register(0x48124) Areas 10-9 set-up register(0x48126) Areas 8-7 set-up register(0x48128) Areas 6-4 set-up register(0x4812A) Areas 6-4 set-up register(0x4812A) At cold start, the number of wait cycles is set to 7 and the output disable delay time is set to 3.5 cycles. Reset up these parameters as necessary using software according to specifications of the connected device. At hot start, these parameters retain their previous settings before a reset. B-II Wait cycles When the number of wait cycles is set for an area using the control bit, the BCU extends the bus cycle for a duration equivalent to the wait cycles set when it accesses the area. Set the desired wait cycles according to the bus clock frequency and the external device's access time. Separately from the wait cycles set here, a wait request from an external device can also be accepted using the #WAIT pin. Since the settings of wait cycles using software are made once every two areas, use this external wait request function if you want the wait cycles to be controlled individually in each area or if you need 7 or more wait cycles. The #WAIT pin is shared with the P30 I/O port. For an external wait request to be accepted, write "1" to CFP30 (D0) / P3 function select register (0x402DC [Byte]) and write "1" (default = "0") to SWAITE (D0) / Bus control register (0x4812E) to enable the #WAIT pin. For timing charts for bus cycles and when wait cycles are inserted, refer to "Bus Cycles in External System Interface". If the number of wait cycles is set to 0 and no external wait is requested, the basic read cycle (read in byte or half-word) for the SRAM external device consists of one cycle. If wait cycles are set, because these cycles are added, the bus read cycle consists of [number of wait cycles + 1] (providing that there is no external wait). On the other hand, the basic write cycle consists of at least two cycles. This does not change regardless of whether zero or one wait cycle is set. If the number of wait cycles set is 2 or more, the bus cycle is actually extended. In this case, the bus write cycle consists of [number of wait cycles + 1], as in the case of read cycles (providing that there is no external wait). S1C33L03 FUNCTION PART EPSON B-II-4-11 BCU II CORE BLOCK: BCU (Bus Control Unit) Output disable delay time In cases when a device having a long output disable time is connected, if a read cycle for that device is followed by the next access, contention for the data bus may occur. (Due to the fact the read device's data bus is not placed in the high-impedance state.) The output disable delay time is provided to prevent such data bus contention. This is accomplished by inserting a specified number of cycles between a read cycle and the next bus operation. Care is required with the #CEx signals, however, since different areas may be asserted consecutively. There are gaps between command signals such as #RD and #WRL/#WRH. Check the specifications of the device to be connected before setting the output disable delay time. The output disable delay time is inserted only in the following cases: * when a read cycle from the external device that has had an output disable delay time set is followed by a write cycle performed by the CPU; and * when a read cycle from the external device that has had an output disable delay time set is followed by a read cycle for a different area (including the internal device). Conversely, no output disable delay time is inserted in the following conditions: * immediately after a write cycle, and * during a successive read from the same external device. Setting Timing Conditions of Burst ROM Wait cycles If burst ROM is selected for area 10 or 9, the wait cycles to be inserted in the burst read cycle can be selected in a range from 0 to 3 cycles. A10BW[1:0] (D[A:9]) / Areas 10-9 set-up register (0x48126) is used for this selection. This selection is applied simultaneously to areas 10 and 9, so wait cycles can not be chosen individually for each area. The wait cycles set at cold start is 0. Even for a burst read, the SRAM settings of wait cycles in the first bus operation are valid. (Refer to A10WT[2:0] in the foregoing section.) The wait cycles set by A10BW[1:0] are inserted into the burst cycles after the first bus operation. In addition, when burst ROM is selected, no wait cycles can be inserted into the read cycle via the #WAIT pin. For writing to an area that has had burst ROM selected, an SRAM write cycle is executed. In this case, both the SRAM settings of wait cycles and those input via the #WAIT pin are valid. Burst mode The burst mode can be selected between an eight-consecutive-burst and a four-consecutive-burst mode. RBST8 (DD) / Bus control register (0x4812E) is used for this selection. The eight-consecutive-burst mode is selected by writing "1" to RBST8 and the four-consecutive-burst mode is selected by setting the bit to "0". At cold start, the four-consecutive-burst mode is set by default. B-II-4-12 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: BCU (Bus Control Unit) A-1 Bus Operation Data Arrangement in Memory The S1C33 Family of devices handle data in bytes (8 bits), half-words (16 bits), and words (32 bits). When accessing data in memory, it is necessary to specify a boundary address that conforms to the data size involved. Specification of an invalid address causes an address error exception. For instructions (e.g., stack manipulation or branch instructions) that rewrite the SP (stack pointer) or PC (program counter), the specified addresses are forcibly modified to appropriate boundary addresses. Therefore, no address error exception occurs in this type of instruction. For details about the address error exception, refer to the "S1C33000 Core CPU Manual". Table 4.12 shows the data arrangement in memory, classified by data type. Table 4.12 Data Arrangement in Memory Data type Arranged location Byte data Half-word data Word data Byte boundary address (all addresses) Half-word boundary address (A[0]="0") Word boundary address (A[1:0]="00") The half-word and word data in memory area accessed in little-endian format by default. It can be changed to bigendian format using AxxEC (D[7:0])/Access control register (0x48132). When "1" is written to AxxEC, the corresponding area is accessed in big-endian method. The bit names and the corresponding areas are as follows: A18EC (D7): Areas 17 and 18 A16EC (D6): Areas 15 and 16 A14EC (D5): Areas 13 and 14 A12EC (D4): Areas 11 and 12 A10EC (D3): Areas 9 and 10 ... Fixed at "0" (little-endian) for booting. A8EC (D2): Areas 7 and 8 A6EC (D1): Area 6 A5EC (D0): Areas 4 and 5 To increase memory efficiency, try to locate the same type of data at continuous locations on exact boundary addresses in order to minimize invalid areas. Bus Operation of External Memory The external data bus is 16-bits wide. For this reason, more than one bus operation occurs depending on the device size and the data size of the instruction executed, as shown in Table 4.13. Table 4.13 Number of Bus Operation Cycles Data size to be accessed Devise size Number of bus operation cycles 32 bits 16 bits 8 bits 16 bits 16 bits 16 bits 2 1 1 32 bits 8 bits 4 16 bits 8 bits 2 8 bits 8 bits 1 Remarks In little-endian method, the low-order byte is accessed when the LSB of the address (A[0]) is "0" or the #BSL signal is L. The high-order byte is accessed when the LSB of the address (A[0]) is "1" or the #BSH signal is H. In big-endian method, the high-order byte is accessed when the LSB of the address (A[0]) is "0" or the #BSL signal is L. The low-order byte is accessed when the LSB of the address (A[0]) is "1" or the #BSH signal is H. In little-endian method, the 8-bit device must be connected to the low-order 8 bits of the data bus. In big-endian method, the 8-bit device must be connected to the high-order 8 bits of the data bus. In little-endian method, the 8-bit device must be connected to the low-order 8 bits of the data bus. In big-endian method, the 8-bit device must be connected to the high-order 8 bits of the data bus. In little-endian method, the 8-bit device must be connected to the low-order 8 bits of the data bus. In big-endian method, the 8-bit device must be connected to the high-order 8 bits of the data bus. These bus operations are shown in the figure below, taking the example of the A0 method. With the BSL method, the following adjustments should be made when reading the figure. (1) For data reads, the operation is as shown in the figure below. (2) For little-endian data writes, read A0 as #BSC, and #WRH as #BSH. (3) For big-endian data writes, read A0 as #BSL, and #WRL as #BSH. S1C33L03 FUNCTION PART EPSON B-II-4-13 B-II BCU II CORE BLOCK: BCU (Bus Control Unit) For information on memory connection, see Figure 4.18. Little-endian 31 Byte 3 Source (general-purpose register) Byte 2 Byte 1 Byte 0 2 15 1 0 15 A[1:0]=10 Bus operation 0 0 A[1:0]=00 No. A1 A0 #WRH #WRL 15 Data bus 1 Byte 1 Byte 0 0 0 0 0 2 Byte 3 Byte 2 0 0 0 1 0 Destination (16-bit device) Big-endian 31 Byte 3 Source (general-purpose register) Byte 2 Byte 1 Byte 0 1 15 2 0 15 A[1:0]=00 Bus operation 0 0 A[1:0]=10 No. A1 A0 #WRH #WRL 15 Data bus 1 Byte 3 Byte 2 0 0 0 0 2 Byte 1 Byte 0 0 0 0 1 0 Destination (16-bit device) Figure 4.5 Word Data Writing to a 16-bit Device Little-endian 31 Destination (general-purpose register) Byte 3 Byte 2 Byte 1 Byte 0 2 15 1 0 15 A[1:0]=10 Bus operation 0 0 A[1:0]=00 No. A1 A0 #WRH #WRL 15 Data bus 1 Byte 1 Byte 0 1 1 0 0 2 Byte 3 Byte 2 1 1 0 1 0 Source (16-bit device) Big-endian 31 Destination (general-purpose register) Byte 3 Byte 2 Byte 1 Byte 0 1 15 2 0 15 A[1:0]=00 Bus operation 0 0 A[1:0]=10 No. A1 A0 #WRH #WRL 15 Data bus 1 Byte 3 Byte 2 1 1 0 0 2 Byte 1 Byte 0 1 1 0 1 0 Source (16-bit device) Figure 4.6 Word Data Reading from a 16-bit Device Little-endian 31 Byte 3 Source (general-purpose register) Byte 2 Byte 1 Byte 0 15 Bus operation 0 1 0 No. A1 A0 #WRH #WRL 15 Data bus 1 Byte 1 Byte 0 0 0 0 0 A[1:0]=0 Destination (16-bit device) Big-endian 31 Byte 3 Source (general-purpose register) Byte 2 Byte 1 Byte 0 15 Bus operation 0 1 0 No. A1 A0 #WRH #WRL 15 Data bus Byte 1 Byte 0 1 0 0 0 0 A[1:0]=0 Destination (16-bit device) Figure 4.7 Half-word Data Writing to a 16-bit Device Little-endian 31 Destination (general-purpose register) Sign or Zero extension Byte 1 Byte 0 15 1 Bus operation 0 0 No. A1 A0 #WRH #WRL 15 Data bus 1 Byte 1 Byte 0 0 1 1 0 A[1:0]=0 Source (16-bit device) Big-endian 31 Destination (general-purpose register) Sign or Zero extension Byte 1 Byte 0 15 1 Bus operation 0 0 No. A1 A0 #WRH #WRL 15 Data bus 1 Byte 1 Byte 0 0 1 1 0 A[1:0]=0 Source (16-bit device) Figure 4.8 Half-word Data Reading from a 16-bit Device B-II-4-14 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: BCU (Bus Control Unit) A-1 Little-endian 31 Byte 3 Source (general-purpose register) Byte 2 Byte 1 Byte 0 1 15 A[1:0]=1 1' 0 Bus operation 0 No. A1 A0 #WRH #WRL 15 Data bus 0 1 Byte 0 Data retained 1 0 1 Data retained Byte 0 1' 0 1 0 A[1:0]=0 Destination (16-bit device) Big-endian 31 Byte 3 Source (general-purpose register) Byte 2 Byte 1 Byte 0 1 15 A[1:0]=0 1' 0 Bus operation 0 No. A1 A0 #WRH #WRL 15 Data bus 0 1 Byte 0 Data retained 0 0 1 1' Data retained Byte 0 1 1 0 A[1:0]=1 Destination (16-bit device) Figure 4.9 Byte Data Writing to a 16-bit Device Little-endian 31 Destination (general-purpose register) 0 Sign or Zero extension RD byte 1 15 A[1:0]=1 1' 0 A[1:0]=0 Bus operation No. A1 A0 #WRH #WRL 15 Data bus 0 RD byte Ignored 1 1 1 1 Ignored RD byte 1' 1 1 0 B-II Source (16-bit device) Big-endian 31 Destination (general-purpose register) 0 Sign or Zero extension RD byte 1 15 A[1:0]=0 1' 0 A[1:0]=1 Bus operation No. A1 A0 #WRH #WRL 15 Data bus 0 RD byte Ignored 1 1 1 0 Ignored RD byte 1' 1 1 1 Source (16-bit device) Figure 4.10 Byte Data Reading from a 16-bit Device Little-endian 31 Byte 3 8 Source (general-purpose register) Byte 2 Byte 1 Byte 0 4 08 A[1:0]=11 3 0 8 A[1:0]=10 2 0 8 A[1:0]=01 Bus operation 0 1 0 A[1:0]=00 Destination (8-bit device) No. A1 A0 #WRH #WRL 15 Data bus 1 Data retained Byte 0 0 X 0 0 Data retained Byte 1 2 0 X 1 0 Data retained Byte 2 3 0 X 0 1 4 Data retained Byte 3 0 X 1 1 (X: Not connected/Unused) Big-endian 31 Byte 3 8 0 Source (general-purpose register) Byte 2 Byte 1 Byte 0 1 08 A[1:0]=00 2 0 8 A[1:0]=01 3 0 8 A[1:0]=10 Bus operation 0 4 0 A[1:0]=11 Destination (8-bit device) No. A1 A0 #WRH #WRL 15 Data bus 0 1 Byte 3 Data retained 1 0 0 0 2 Byte 2 Data retained 1 0 1 0 3 Byte 1 Data retained 1 0 0 1 4 Byte 0 Data retained 1 0 1 1 Figure 4.11 Word Data Writing to an 8-bit Device Little-endian 31 8 Destination (general-purpose register) Byte 3 Byte 2 Byte 1 Byte 0 4 08 A[1:0]=11 3 0 8 A[1:0]=10 2 0 8 A[1:0]=01 Bus operation 0 1 0 A[1:0]=00 Source (8-bit device) No. A1 A0 #WRH #WRL 15 Data bus 1 Ignored Byte 0 1 X 0 0 2 Ignored Byte 1 1 X 1 0 3 Ignored Byte 2 1 X 0 1 4 Ignored Byte 3 1 X 1 1 (X: Not connected/Unused) Big-endian 31 8 Destination (general-purpose register) Byte 3 Byte 2 Byte 1 Byte 0 1 A[1:0]=00 0 08 2 A[1:0]=01 0 8 3 A[1:0]=10 Source (8-bit device) 0 8 Bus operation 0 4 0 A[1:0]=11 No. A1 A0 #WRH #WRL 15 Data bus 0 1 Byte 3 Ignored 1 1 0 0 2 Byte 2 Ignored 1 1 1 0 3 Byte 1 Ignored 1 1 0 1 4 Byte 0 Ignored 1 1 1 1 Figure 4.12 Word Data Reading from an 8-bit Device S1C33L03 FUNCTION PART EPSON B-II-4-15 BCU II CORE BLOCK: BCU (Bus Control Unit) Little-endian 31 Byte 3 Source (general-purpose register) Byte 2 Byte 1 Byte 0 8 2 0 8 A[1:0]=1 Bus operation 0 1 0 A[1:0]=0 Data bus No. A1 A0 #WRH #WRL 15 1 0 Data retained Byte 0 0 X 2 1 Data retained Byte 1 0 X 0 (X: Not connected/Unused) Destination (8-bit device) Big-endian 31 Byte 3 Source (general-purpose register) Byte 2 Byte 1 Byte 0 8 1 0 8 A[1:0]=0 2 0 Bus operation 0 No. A1 A0 #WRH #WRL 15 Data bus 0 1 0 Byte 1 Data retained 0 0 2 1 Byte 0 Data retained 0 0 A[1:0]=1 (: Uniformly 1 or 0) Destination (8-bit device) Figure 4.13 Half-word Data Writing to an 8-bit Device Little-endian 31 Destination (general-purpose register) Sign or Zero extension Byte 1 Byte 0 8 2 0 8 A[1:0]=1 Bus operation 0 1 0 A[1:0]=0 Data bus No. A1 A0 #WRH #WRL 15 1 0 Ignored Byte 0 1 X Ignored Byte 1 2 1 1 X 0 (X: Not connected/Unused) Source (8-bit device) Big-endian 31 Destination (general-purpose register) Sign or Zero extension Byte 1 Byte 0 8 1 0 8 A[1:0]=0 2 0 Bus operation 0 Data bus 0 No. A1 A0 #WRH #WRL 15 1 0 Byte 1 Ignored 1 1 2 1 Byte 0 Ignored 1 1 A[1:0]=1 (: Uniformly 1 or 0) Figure 4.14 Half-word Data Reading from an 8-bit Device Little-endian 31 Byte 3 Source (general-purpose register) Byte 2 Byte 1 Byte 0 8 Bus operation 0 1 0 No. A1 A0 #WRH #WRL 15 Data bus 1 Data retained Byte 0 X 0 0 A[1:0]= (X: Not connected/Unused) Destination (8-bit device) Big-endian 31 Byte 3 Source (general-purpose register) Byte 2 Byte 1 Byte 0 8 1 0 Bus operation 0 No. A1 A0 #WRH #WRL 15 Data bus 0 Byte 0 Data retained 1 0 1 A[1:0]= Destination (8-bit device) Figure 4.15 Byte Data Writing to an 8-bit Device Little-endian 31 Destination (general-purpose register) Sign or Zero extension Byte 0 8 Bus operation 0 1 0 No. A1 A0 #WRH #WRL 15 Data bus 1 Ignored Byte 0 X 1 0 A[1:0]= (X: Not connected/Unused) Source (8-bit device) Big-endian 31 Destination (general-purpose register) Sign or Zero extension Byte 0 8 1 0 Bus operation 0 No. A1 A0 #WRH #WRL 15 Data bus 0 1 Byte 0 Ignored 1 1 A[1:0]= Source (8-bit device) Figure 4.16 Byte Data Reading from an 8-bit Device B-II-4-16 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: BCU (Bus Control Unit) A-1 Bus Clock The bus clock is generated by the BCU using the CPU system clock output from the clock generator. Figure 4.17 shows the clock system. To CPU #X2SPD pin PLLS[1:0] pins Bus clock CLKDT[1:0] CLKCHG CLG High-speed (OSC3) oscillation circuit BCU OSC3_CLK A 1/1-1/8 CPU_CLK BCLKSEL[1:0] BCU_CLK 1/1 or 1/2 PLL SDRENA CPU_CLK OSC3_CLK PLL_CLK PLL_CLK BCLK pin SDRAMC Low-speed (OSC1) oscillation circuit SD_CLK 1/1 or 1/2 Refresh counter PLL_CLK and CPU_CLK OSC3_CLK (PLL: off) B-II PLL_CLK (PLL: x2 mode) PLL_CLK (PLL: x4 mode) (when the CPU system clock source is OSC3) A CPU_CLK (CLKDT = 1/1) BCU CPU_CLK (CLKDT = 1/2) CPU_CLK (CLKDT = 1/4) CPU_CLK (CLKDT = 1/8) BCU_CLK CPU_CLK BCU_CLK (#X2SPD = "1", x1 speed mode) 1 1 1 1 2 1 2 BCU_CLK (#X2SPD = "0", x2 speed mode) 2 1 2 SD_CLK (When #X2SPD = "1") #SDCEx CPU_CLK BCU_CLK SD_CLK (SDRCLK = "1") SD_CLK (SDRCLK = "0") Self refresh SDCKE 3 2 3 2 1 SD_CLK (When #X2SPD = "0") #SDCEx CPU_CLK BCU_CLK SD_CLK (SDRCLK = "1") SD_CLK (SDRCLK = "0") Self refresh SDCKE 1 1 Access to the internal RAM 2 Access to the external memory (other than SDRAM) 3 Access to the SDRAM Figure 4.17 Clock System S1C33L03 FUNCTION PART EPSON B-II-4-17 II CORE BLOCK: BCU (Bus Control Unit) Since the bus clock is generated from the CPU system clock (CPU_CLK), the following settings affect the bus clock: 1. Selection of an oscillation circuit (OSC3 or OSC1) 2. PLL configuration (OSC3_CLK x 1, x2 or x4) 3. CPU clock division ratio for power saving (1/8, 1/4, 1/2, or 1/1 of OSC3_CLK or PLL_CLK) Items 2 and 3 apply when the high-speed (OSC3) oscillation circuit is selected as the CPU clock source. For details about the settings of the system clock, refer to "CLG (Clock Generator)". Bus clock operation during standby is as follows: Basic HALT mode: the BCU and bus clock continue operating. DRAM can be refreshed. HALT2 mode: the BCU and bus clock are stopped. SLEEP mode: the BCU and bus clock are stopped. Bus Speed Mode The CPU - bus clock ratio can be set using the #X2SPD pin as follows: When #X2SPD = "1", x1 speed mode (CPU - bus clock ratio is 1 : 1) is set. The bus clock and the CPU system clock will be the same. When #X2SPD = "0", x2 speed mode (CPU - bus clock ratio is 2 : 1) is set. In x2 speed mode, the bus clock will be dynamically varied according to the memory to be accessed. * When an external memory area is accessed, the bus clock frequency becomes half of the CPU system clock. * When the internal RAM/ROM area is accessed, the bus clock frequency becomes equal to the CPU system clock. In x1 speed mode, area 1 (internal I/O area) is accessed in 4 cycles of the CPU system clock, while in x2 speed mode, the number of access cycles can be selected using A1X1MD (D3) / BCLK select register (0x4813A). When A1X1MD = "1", area 1 is accessed in 2 cycles of the CPU system clock. When A1X1MD = "0", area 1 is accessed in 4 cycles of the CPU system clock. (default) Bus Clock Output The bus clock is also output from the BCLK pin to an external device. The BCLK output clock can be selected from among five types using BCLKSEL[1:0] (D[1:0]) / BCLK select register (0x4813A) and SDRENA (D7) / SDRAM control register (0x39FFC1). Table 4.14 Selection of BCLK Output Clock SDRENA BCLKSEL1 BCLKSEL0 0 1 1 0 0 - 1 0 1 0 - 1 B-II-4-18 EPSON Output clock PLL_CLK (PLL output clock) OSC3_CLK (OSC3 oscillation clock) BCU_CLK (BCU operating clock) CPU_CLK (CPU operating clock) SD_CLK (SDRAM clock) S1C33L03 FUNCTION PART II CORE BLOCK: BCU (Bus Control Unit) A-1 Bus Cycles in External System Interface The following shows a sample SRAM connection the basic bus cycles. S1C33 SRAM S1C33 SRAM S1C33 SRAM A[9:1] D[15:0] A[8:0] I/O[15:0] A[9:1] D[15:0] A[8:0] I/O[15:0] A[9:1] D[15:0] A[8:0] I/O[15:0] #RD #WRH #WRL #CE #RD #WRH #WRL #CE A0 #WRH #WRL #CE #RD #LB #UB #WE #OS #OE A0 #WRH #WRL #CE #RD #LB #UB #WE #OS #OE (1) A0 system (little endian/big endian) (2) #BSL system (little endian) (3) #BSL system (big endian) Figure 4.18 Sample DRAM Connection SRAM Read Cycles Basic read cycle with no wait mode B-II C1 BCLK A[23:0] #CExx D[15:0] #RD addr ;; ;; ;;; ;;; BCU data #WAIT Figure 4.19 Basic Read Cycle with No Wait Read cycle with wait mode Example: When the BCU has no internal wait mode and 2 wait cycles via #WAIT pin are inserted C1 CW BCLK A[23:0] #CExx D[15:0] #RD #WAIT addr CW ;;; ;;; ;;;;;;;;;;;;;; ;;;;;;;;;;;;;; ;;;;; ;;;;;;;;;;; ;;;;;;;;;;; ;;;;; ;;;;; ;;;;; data Figure 4.20 Read Cycle with Wait The #WAIT signal is sampled at the falling edge of the transition of BCLK (bus clock) and when it is sampled on an inactive (high level), the read cycle is terminated. Note: Insertion of wait cycles via the #WAIT pin is possible only when the device for bus conditions is set for SRAM, and SWAITE (D0) / Bus control register (0x4812E) is enabled for waiting. S1C33L03 FUNCTION PART EPSON B-II-4-19 II CORE BLOCK: BCU (Bus Control Unit) The above example shows a read cycle when a wait mode is inserted via the #WAIT signal. A wait mode consisting of 0 to 7 cycles can also be inserted using the wait control bits. The settings of these bits can also be used in combination with the #WAIT signal. In this case as well, the #WAIT signal is sampled at the falling edge of the transition of BCLK. However, even when the #WAIT signal is inactive before the wait cycles set by the wait control bits are terminated, the read cycle is not terminated at that time. Precaution #CE and address hold times at the rising edge of the #RD signal In read cycles of this BCU, the rise of the #RD signal, negating the chip enable (#CExx) signal and changing the address (A[23:0]) occur simultaneously at the same clock edge. No hold time is inserted to the chip enable and address signals. The same applies even when an output disable delay time is inserted. Therefore when connecting a peripheral circuit, which changes its internal state by reading, to the bus, take a measure to insert a delay to the address and chip enable signals. BCLK A[23:0] addr #CE4 #CE7 #RD Hazard occurrence. This hazard causes an erroneous RD operation on the next area. Figure 4.21 Trouble Case Output disable cycle When an output disable cycle (set with output disable delay time parameter) is inserted, the chip enable (#CExx) signal temporarily goes high. This makes an interval between the next read cycle. Note, however, that no output disable cycle is inserted when reading is continuously performed to the area that is accessed with the same chip enable signal. Bus Timing In read cycles, the rise of the #RD signal and changing the chip enable setting (#CE4 to #CE10) and address (A23 to A0) occur at the same clock edge. This timing is the same even if a long setting is made for the output disable cycle by the bus controller, for example, and changeover occurs simultaneously. Therefore, when an I/O peripheral circuit whose internal information is changed by a read operation is connected to the C33 bus, appropriate measures must be taken to insert a delay for the address and chip enable signals. With an output disable cycle, there is normally a gap between one read cycle and the next. Note, however, that this output disable cycle is not inserted in the case of consecutive reads in a memory area for which the same chip enable signal is output. B-II-4-20 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: BCU (Bus Control Unit) A-1 SRAM Write Cycles Basic write cycle with no wait mode C1 C2 BCLK ;;; ;;; addr A[23:0] #CExx data D[15:0] #WRH/#WRL #WAIT #WR #BSL/#BSH B-II Figure 4.22 Half-word Write Cycle with No Wait C1 C2 C3 C4 BCLK ;;; ;;; addr A[23:0] #CExx BCU #WRH #WRL D[15:8] Undefined Valid D[7:0] Valid Undefined Figure 4.23 Byte Write Cycle with No Wait (A0 system, little endian) C1 C2 C3 C4 BCLK ;;; ;;; addr A[23:0] #CExx #BSH #BSL #WRL D[15:8] Undefined Valid D[7:0] Valid Undefined Figure 4.24 Byte Write Cycle with No Wait (#BSL system, little endian) S1C33L03 FUNCTION PART EPSON B-II-4-21 II CORE BLOCK: BCU (Bus Control Unit) Write cycle with wait mode Example: When the BCU has no internal wait mode, and 1 wait cycle is inserted via the #WAIT pin C1 CW C2 BCLK ;;; ;;; addr A[23:0] #CExx data D[15:0] #WRH/#WRL #WAIT #WR #BSL/#BSH Figure 4.25 Half-word Write Cycle with Wait The #WAIT signal is sampled at the falling edge of the transition of BCLK (bus clock), and the write cycle is terminated in the cycle immediately following the cycle in which the #WAIT signal was sampled in an inactive (high level). Note: Insertion of wait cycles via the #WAIT pin is possible only when the device for bus conditions is set to SRAM and SWAITE (D0) / Bus control register (0x4812E) is enabled for waiting. The above example shows a write cycle when a wait mode is inserted via the #WAIT signal. A wait mode consisting of 2 to 7 cycles can also be inserted using the wait control bits. The settings of these bits also can be used in combination with the #WAIT signal. In this case as well, the #WAIT signal is sampled at the falling edge of the transition of BCLK. However, even when the #WAIT signal is inactive before the wait cycles set by the wait control bits are terminated, the write cycle is not terminated at that time. Note: The basic write cycle consists of at least two cycles. This does not change regardless of whether zero or one wait cycle is set by the wait control bits. If the number of wait cycles set is 2 or more, the bus cycle is actually extended. In this case, the bus write cycle consists of [number of wait cycles + 1], as in the case of read cycles (providing that there is no external wait). B-II-4-22 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: BCU (Bus Control Unit) A-1 Burst ROM Read Cycles Burst read cycle Example: When 4-consecutive-burst and 2-wait cycles are set during the first access BCLK addr[23:2] A[23:2] "00" A[1:0] #CE10(9) D[15:0] #RD "01" "10" "11" ;;;;;;;;;;;;;; ;;;; ;;;; ;;;; ;;;;;;;;;;;;;; ;;;; ;;;; ;;;; IR0 IR1 IR2 ;;; ;;; ;;; ;;; IR3 Figure 4.26 Burst Read Cycle A burst read cycle occurs when area 10 or 9 is set for burst ROM and one of those areas is accessed for the following reasons: B-II 1) Instruction fetch The burst read cycle is executed as long as a instruction fetch from contiguous addresses continues until A[2:1] = "11" (for 4-consecutive bursts); or A[3:1] = "111" (for 8-consecutive bursts) BCU 2) Word (32-bit) data read out Note: A 16-bit output is supported for the burst ROM. Set the device size to 16 bits. Wait cycles during burst read In the first bus operation, 0 to 7 wait cycles can be inserted using the wait control bits A10WT[2:0] (D[2:0]) / Areas 10-9 set-up register (0x48126) in the same way as for ordinary SRAM. For the wait cycles to be inserted in the burst cycle that follows, use a dedicated wait control bits, A10BW[1:0], which is only used for reading bursts. The wait cycles can be set in the range from 0 to 3 using these bits. Note that no wait cycle via the #WAIT pin can be inserted into the burst-read cycle. Write cycle to burst ROM area If area 10 or 9 is set for burst ROM, a SRAM write cycle is executed when a write to that area is attempted. In this case, wait cycles via the #WAIT pin can be inserted. S1C33L03 FUNCTION PART EPSON B-II-4-23 II CORE BLOCK: BCU (Bus Control Unit) DRAM Direct Interface Outline of DRAM Interface The BCU incorporates a DRAM direct interface that allows DRAM to be connected directly to areas 8 and 7 or areas 14 and 13. This interface supports the 2CAS method, so that column addresses can be set at between 8 and 11 bits. In addition, this interface supports a fast-page or an EDO-page mode (EDO DRAM directly connectable to areas) as well as random cycles. The refresh method (CAS-before-RAS refresh or self-refresh) and timing conditions (e.g., number of RAS/CAS cycles and number of precharge cycles) can be programmed using a control bit. When selecting areas 8 and 7 or areas 14 and 13 to be used for DRAM, it depends on chip-enable settings using CEFUNC (D9) / DRAM timing set-up register (0x48130). CEFUNC = "00": DRAM can be connected to areas 8 and 7 (default) #CE8 and #CE7 function as #RAS0 and #RAS1, respectively. CEFUNC "00": DRAM can be connected to areas 14 and 13. #CE14 and #CE13 function as #RAS2 and #RAS3, respectively. Figure 4.27 shows a sample DRAM connection. Table 4.15 and Table 4.16 show examples of connectable DRAMs and typical configurations. S1C33 4M DRAM (256K x 16) A[9:1] D[15:0] A[8:0] I/O[15:0] #RD #RASx(#CEx)* #HCAS #LCAS #WE #OE #RAS #HCAS #LCAS #WE x: 14, 13, 8 or 7 Figure 4.27 Sample DRAM Connection Table 4.15 Connectable DRAM Example DRAM 1M (64K x 16) 4M (256K x 16) 16M (1M x 16) Number of devices Number of Row bits Number of Column bits Memory size 1 1 1 8 9 12 8 9 8 128K bytes 512K bytes 2M bytes Table 4.16 DRAM Configuration Example (areas 7 and 8 only) Area 7 1 2 3 4 5 6 I/O I/O I/O DRAM (1M) DRAM (4M) DRAM (16M) Area 8 DRAM (1M) DRAM (4M) DRAM (16M) DRAM (1M) DRAM (4M) DRAM (16M) Total memory size 1M bits 4M bits 16M bits 2M bits 8M bits 32M bits (128K bytes) (512K bytes) (2M bytes) (256K bytes) (1M bytes) (4M bytes) Also, the S1C33L03 provides an SDRAM direct interface. Refer to "VI SDRAM Controller Block" for details. B-II-4-24 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: BCU (Bus Control Unit) A-1 DRAM Setting Conditions The DRAM interface allows the following conditions to be selected. Although DRAM can be used in areas 8 and 7 or areas 14 and 13, these condition are applied to all four areas and cannot be set individually for each area. Table 4.17 DRAM Interface Parameters Parameter Page mode RAS mode Column address size Refresh enable Refresh method Refresh RPC delay Refresh RAS pulse width Number of RAS precharge cycles CAS cycle control RAS cycle control Selectable condition EDO page mode or Fast page mode Successive RAS mode or Normal mode 8, 9, 10 or 11 bits Enabled or Disabled Self-refresh or CAS-before-RAS refresh 2.0 or 1.0 2, 3, 4 or 5 cycles 1, 2, 3 or 4 cycles 1, 2, 3 or 4 cycles 1, 2, 3 or 4 cycles Initial setting Control bits Fast page mode REDO(DC)/Bus control register(0x4812E) Normal mode CRAS(D8)/DRAM timing set-up register(0x48130) 8 bits Disabled CBR refresh RCA[1:0](D[B:A])/Bus control register(0x4812E) RPC2(D9)/Bus control register(0x4812E) RPC1(D8)/Bus control register(0x4812E) 1.0 2 cycles 1 cycle RPC0(D7)/Bus control register(0x4812E) RRA[1:0](D[6:5])/Bus control register(0x4812E) RPRC[1:0](D[7:6])/DRAM timing set-up register(0x48130) 1 cycle 1 cycle CASC[1:0](D[4:3])/DRAM timing set-up register(0x48130) RASC[1:0](D[1:0])/DRAM timing set-up register(0x48130) B-II Page mode The DRAM interface allows EDO DRAM to be connected directly. Therefore, the EDO-page mode is supported along with the fast-page mode. Use REDO to choose the desired page mode that suits the DRAM to be used. REDO = "1": EDO page mode REDO = "0": Fast page mode (default) BCU Successive RAS mode For applications that require high-speed DRAM access, the DRAM interface supports a successive RAS mode. In this mode, even when successive accesses to the DRAM are not requested by the CPU or DMA, the #RAS signal is kept low and operation is continued without inserting any precharge cycle. Therefore, when accessing the same page (row address) of the DRAM that has been accessed previously, the page mode remains active, allowing read/write to be performed at high speeds. However, to maintain the rated AC characteristics, one idle cycle is inserted when access in the page mode is begun and when finished. CRAS is used to set the successive RAS mode. CRAS = "1": Successive RAS mode CRAS = "0": Normal mode (default) The successive RAS mode is suspended by one of the following causes: * a refresh cycle has occurred; * bus control is requested by an external bus master; * the requested device and page are not compatible with DRAM memory; and * the slp or halt instruction is executed. If the successive RAS mode is suspended, a precharge cycle is inserted before the next bus cycle begins. Note: When using the successive RAS mode, always be sure to use #DRD for the read signal and #DWE for the low-byte write signal. S1C33L03 FUNCTION PART EPSON B-II-4-25 II CORE BLOCK: BCU (Bus Control Unit) Column address size When accessing DRAM, addresses are divided into a row address and a column address as they are output. Choose the size of this column address using RCA, as shown below. Table 4.18 Column Address Size RCA1 RCA0 Column address size 1 1 0 0 1 0 1 0 11 10 9 8 The initial default size is 8 bits. Choose the desired size according to the address input pins of the DRAM to be used. The row addresses output synchronously with falling edges of the #RAS signal are derived from the CPU's internal 28-bit addresses by logically shifting them to the right by an amount equal to the column address size. The MSB contains a 1. The column addresses are output to the address bus along with the falling edges of the #CAS signal. These addresses are derived directly from the CPU's internal 28-bit addresses. Figure 4.28 shows the contents of the row addresses thus output. 28-bit CPU internal address 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (1) Row address when column address is set to 8 bits T T T T T T T T 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 (2) Row address when column address is set to 9 bits T T T T T T T T T 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 (3) Row address when column address is set to 10 bits T T T T T T T T T T 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 (4) Row address when column address is set to 11 bits T T T T T T T T T T T 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 T = "1", 0-27: Bit number of CPU internal address Figure 4.28 Example of Row/Column Address Mapping Refresh enable Use RPC2 to enable or disable the internal refresh function. RPC2 = "1": Enabled RPC2 = "0": Disabled (default) After choosing the desired refresh method using RPC1, write "1" to RPC2. Refresh method The DRAM interface supports both a CAS-before-RAS refresh cycle and a self-refresh cycle. Choose the desired method using RPC1. RPC1 = "1": Self-refresh RPC1 = "0": CAS-before-RAS refresh The generation interval of the CAS-before-RAS refresh is determined by the underflow signal of an 8-bit programmable timer 0. Consequently, before the CAS-before-RAS refresh can be executed, the 8-bit programmable timer 0 must be set to obtain the necessary underflow timing. When this method is selected and RPC2 is enabled, the refresh cycle is generated each time the 8-bit programmable timer 0 underflows. The self-refresh is started by writing "1" to RPC2 while RPC1 = "1" and is terminated by clearing RPC1 or RPC2 to "0". If RPC1 is switched over when RPC2 = "1" (refresh enabled), an undesirable self-refresh cycle is generated. So be sure to clear RPC2 to "0" (refresh disabled) before selecting the refresh method. B-II-4-26 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: BCU (Bus Control Unit) A-1 Refresh RPC delay Use RPC0 to set the RPC delay value of a refresh cycle (a delay time from the immediately preceding precharge to the fall of #CAS). RPC0 = "1": 2 cycles RPC0 = "0": 1 cycle Refresh RAS pulse width Use RRA to set the #RAS pulse width of a CAS-before-RAS refresh cycle. Table 4.19 Refresh RAS Pulse Width RRA1 RRA0 Pulse width 1 1 0 0 1 0 1 0 5 cycles 4 cycles 3 cycles 2 cycles The initial default value is 2 cycles. Number of RAS precharge cycles B-II Use RPRC to choose the number of RAS precharge cycles. Table 4.20 Number of RAS Precharge Cycles RPRC1 RPRC0 Number of cycles 1 1 0 0 1 0 1 0 4 cycles 3 cycles 2 cycles 1 cycle BCU The initial default value is 1 cycle. CAS cycle control Use CASC to choose the number of CAS cycles when accessing DRAM. Table 4.21 Number of CAS Cycles CASC1 CASC0 Number of cycles 1 1 0 0 1 0 1 0 4 cycles 3 cycles 2 cycles 1 cycle The initial default value is 1 cycle. RAS cycle control Use RASC to choose the number of RAS cycles when accessing DRAM. Table 4.22 Number of RAS Cycles RASC1 RASC0 Number of cycles 1 1 0 0 1 0 1 0 4 cycles 3 cycles 2 cycles 1 cycle The initial default value is 1 cycle. S1C33L03 FUNCTION PART EPSON B-II-4-27 II CORE BLOCK: BCU (Bus Control Unit) DRAM Read/Write Cycles The following shows the basic bus cycles of DRAM. The DRAM interface does not accept wait cycles inserted via the #WAIT pin. DRAM random read cycle Example: RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle RAS cycle Precharge cycle CAS cycle BCLK A[11:0] ROW ;;;;;;; ;;;;;;; COL #RASx #HCAS/ #LCAS #RD D[15:0] ;;;;;;;;;;;;; ;;;;;;;;;;;;; data Figure 4.29 DRAM Random Read Cycle ;;;; ;;;; DRAM read cycle (fast page mode) Example: RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle RAS cycle CAS cycle #1 Precharge cycle CAS cycle #2 BCLK A[11:0] ROW COL #1 ;;;;;;; ;;;;;;; COL #2 #RASx #HCAS/ #LCAS #RD D[15:0] ;;;;;;;;;;;;; ;;;;;;;;;;;;; data ;;;;;;;;; ;;;;;;;;; Figure 4.30 DRAM Read Cycle (fast page mode) data ;;;; ;;;; DRAM read cycle (EDO page mode) Example: RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle RAS cycle CAS cycle #1 CAS cycle #2 BCLK A[11:0] ROW COL #1 COL #2 #RASx Precharge cycle ;;;;;;; ;;;;;;; #HCAS/ #LCAS #RD D[15:0] ;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;; data ;;;;;;;;; ;;;;;;;;; Figure 4.31 DRAM Read Cycle (EDO page mode) data ;; ;; The read timing in EDO page-mode lags 0.5 cycles behind that in fast page mode. B-II-4-28 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: BCU (Bus Control Unit) A-1 DRAM random write cycle Example: RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle RAS cycle BCLK A[11:0] Precharge cycle CAS cycle ROW COL #RASx ;;;;;;; ;;;;;;; #HCAS/ #LCAS #WE write data D[15:0] ;;;;; ;;;;; Figure 4.32 2CAS Type DRAM Random Write Cycle DRAM write cycle (fast page or EDO page mode) B-II Example: RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle; word-write sample RAS cycle CAS cycle #1 CAS cycle #2 BCLK A[11:0] ROW Precharge cycle COL #1 COL #2 #RASx ;;;;;;; ;;;;;;; #HCAS/ #LCAS #WE write data D[15:0] write data Figure 4.33 DRAM Word-Write Cycle (fast page or EDO page mode) ;;;;; ;;;;; Example: RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle; byte-write sample (little endian) RAS cycle CAS cycle #1 CAS cycle #2 BCLK A[11:0] ROW Precharge cycle ;;;;;;; ;;;;;;; COL #RASx #HCAS #LCAS #WE D[15:8] Undefined write data D[7:0] write data Undefined Figure 4.34 DRAM Byte-Write Cycle (fast page or EDO page mode) S1C33L03 FUNCTION PART EPSON ;;;;; ;;;;; ;;;;; ;;;;; B-II-4-29 BCU II CORE BLOCK: BCU (Bus Control Unit) Operation in successive RAS mode Example: RAS: 2 cycles; CAS: 1 cycle; Precharge: 2 cycles (1) RAS cycle CAS cycles in page mode (2) (3) Deassert cycle Assert cycle (4) CAS cycles in page mode Precharge cycle RAS cycle CAS cycles BCLK A[11:0] #RASx #HCAS/ #LCAS #DRD #DWE Accsess to other device than DRAM Not asserted for areas other than DRAM Figure 4.35 Operation in Successive RAS Mode (1) When accessing the DRAM area, an ordinary RAS cycle is executed first. (2) If access to the same DRAM is suspended during a page mode, #RASx remains asserted while some other device is accessed. In this case, a cycle to temporarily deassert #DRD/#DWE is inserted before accessing the other device. (3) If access to the same page in the same DRAM area as in (1) is requested after (2), #DRD/#DWE is asserted back again to restart the page mode. (4) A precharge cycle is executed when one of the following conditions that cause the page mode to suspend is encountered: * access to different DRAM is requested; * access to a different page in the same DRAM area is requested; * access to some other device than DRAM is requested; * CAS-before-RAS refresh is requested; and * relinquishing of bus control is requested by an external bus master. Note: When using the successive RAS mode, always be sure to use #DRD for the read signal and #DWE for the low-byte write signal. B-II-4-30 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: BCU (Bus Control Unit) A-1 DRAM Refresh Cycles The DRAM interface supports a CAS-before-RAS refresh cycle and a self-refresh cycle. CAS-before-RAS refresh cycle Before performing a CAS-before-RAS refresh, set RPC2 to "1" while RPC1 = "0" in order to enable the DRAM refresh function. Once this is done, the BCU executes a CAS-before-RAS refresh by using the underflow signal that is output by the 8-bit programmable timer 0 as a trigger. Therefore, refresh generation timing can be programmed using the internal prescaler and 8-bit programmable timer 0. For details on how to control the prescaler and 8-bit programmable timer 0, refer to "Prescaler and Operating Clock for Peripheral Circuits", and "8-Bit Programmable Timers". Example: RPC delay: 1 cycle; Refresh RAS pulse width: 2 cycles; Precharge: 1 cycle CAS-before-RAS refresh cycle BCLK ;;;;;;; ;;;;;;; #HCAS/ ;;;; ;;;; #RAS B-II #LCAS Refresh RPC delay Fixed at 1 cycle Refresh RPC pulse width Precharge cycle Figure 4.36 CAS-Before-RAS Refresh When the refresh cycle is terminated, the #HCAS/#LCAS signal boot timing is 0.5 cycles before that of #RAS. Consequently, the pulse width of #HCAS/#LCAS is determined by the refresh RAS pulse width that was set using RRA. The number of precharge cycles after the refresh cycle is defined by the value that was set using RPRC, the same value that is used for both random cycles and page mode accesses. Self-refresh To support DRAM chips equipped with a self-refresh function, the BCU has a function to generate a selfrefresh cycle. To start a self-refresh cycle, set RPC2 to "1" after setting RPC1 to "1". To deactivate a self-refresh cycle, write "0" to RPC1 or RPC2. Example: RPC delay: 1 cycle Self-refresh mode set up BCLK #RAS Self-refresh mode Self-refresh mode deactivation ;;;;;;; ;;;;;;; ;;;; ;;;; #HCAS/ #LCAS Refresh RPC delay Fixed at 1 cycle Precharge cycle (6 cycles) Figure 4.37 Self-Refresh For a self-refresh function as well, the RPC delay is determined by setting RPC0 in the same way as for a CAS-before-RAS refresh. The refresh RAS pulse width is determined by the timing at which the refresh is deactivated in software and is unaffected by settings of RRA. #RAS and #HCAS/#LCAS are booted up simultaneously upon completion of a self-refresh and the precharge duration that follows is fixed at 6 cycles. S1C33L03 FUNCTION PART EPSON B-II-4-31 BCU II CORE BLOCK: BCU (Bus Control Unit) Normally, DRAM specifications require that the contents of all row addresses be refreshed within a certain time before and after a self-refresh. To meet this requirement, make sure a CAS-before-RAS refresh is executed by a program. In this case, set the 8-bit programmable timer 0 so that the contents of all row addresses are refreshed within a predetermined time. Note: If read from or write to the DRAM under a self-refresh is attempted, the BCU keeps #RAS and #HCAS/#LCAS low as it executes a read/write cycle. Other bus signals than #RAS and #HCAS/#LCAS (e.g., address, data, and control signals) change their state according to the specified conditions. Since said attempt initiates an invalid access to the DRAM, do not read from or write to the DRAM during a self-refresh. Releasing External Bus The external bus is normally controlled by the CPU, but the BCU is designed to release control of the bus ownership to an external device. This function is enabled by writing "1" to SEMAS (D2) / Bus control register (0x4812E) (disabled by default). The #BUSREQ (P34) and #BUSACK (P35) pins are used for control of the bus ownership. To direct the P34 and P35 pins for input/output of the #BUSREQ and #BUSACK signals, write "1" to CFP34 (D4) and CFP35 (D5) / P3 function select register (0x402DC [Byte]). Sequence in which control of the bus is released This sequence is described below. 1. The external bus master device requesting control of the bus ownership lowers the #BUSREQ pin. 2. The CPU keeps monitoring the status of the #BUSREQ pin, so that when this pin is lower, the CPU terminates the bus cycle being executed and places the signals listed below in high-impedance state one cycle later: A[23:0], D[15:0], #RD, #WRL, #WRH, #HCAS, #LCAS, #CExx Then the CPU lowers the #BUSACK pin to inform the external device that control of the bus ownership has been released. 3. One cycle later, the external bus starts its own bus cycle. The external bus master must hold the #BUSREQ pin low until the bus cycle is completed. 4. After completing the necessary bus cycles, the external bus master places the bus in high-impedance state and releases the #BUSREQ pin back high. 5. After confirming that the #BUSREQ pin is raised again, the CPU raises the #BUSACK pin one cycle later and resumes the processing that has been suspended. BCLK Synchronization #BUSREQ Synchronization #BUSACK The S1C33 terminates the bus cycle being executed. 1 cycle 1 cycle The external bus master controls bus cycles. 1 cycle The S1C33 controls bus cycles. D[15:0] A[23:0] #RD, #WR Hi-Z Figure 4.38 External Bus Release Timing If control of the bus ownership is requested during a DMA transfer by the internal DMA controller, the DMA transfer under way is suspended at a break in data to accept the request for bus ownership control. The DMA transfer that has been kept pending is restarted when the CPU gains control of the bus ownership. B-II-4-32 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: BCU (Bus Control Unit) A-1 DRAM refresh when bus ownership control is released In systems where DRAM is connected directly, a refresh request could arise while control of the bus ownership is released from the CPU. In such a case, take one of the corrective measures described below. * Monitoring the output signal of the 8-bit programmable timer 0 The underflow signal (DRAM refresh request) of the 8-bit programmable timer 0 can be output from the P10 I/O port pin. If a refresh request arises while the external bus master is monitoring this output, release #BUSREQ back high to drop the request for bus ownership control. Start a DRAM refresh cycle when control of the bus ownership is returned to the CPU. To direct the P10 pin in order to output the underflow signal of the 8-bit programmable timer 0, write "1" to CFP10 (D0) / P1 function select register (0x402D4 [Byte]) and IOC10 (D0) / P1 I/O control register (0x402D6 [Byte]). Also, to output the underflow signal to an external device, write "1" to PTOUT0 (D2) / 8bit Timer 0 control register (0x40160 [Byte]). For details about output control, refer to "8-Bit Programmable Timers". * Monitoring the #BUSGET signal The #BUSGET signal can be output from the P31 I/O port pin. The #BUSGET signal is derived from logical sum of the following signals: 1. DRAM refresh request signal (output from the 8-bit programmable timer 0) 2. Interrupt request signal from the interrupt controller to the CPU 3. Startup request signal from the interrupt controller to the IDMA B-II If the #BUSGET signal is found to be active when the external bus master is monitoring it, release #BUSREQ back high to drop the request for bus ownership control. When using the #BUSGET signal to only monitor a refresh request, set the interrupt controller in such a way that no interrupt request or IDMA startup request will be generated. To direct the P31 pin for output of the #BUSGET signal, write "1" to CFEX3 (D3) / Port function extension register (0x402DF [Byte]). Power-down Control by External Device In addition to requesting the releasing of bus ownership control described above, it is possible to place the CPU in a HALT state by using the #BUSREQ signal. This allows the CPU to be stopped during bus operation by an external bus master in order to conserve power. This function is enabled by writing "1" to SEPD (D1) / Bus control register (0x4812E). If SEPD = "1", the CPU and the BCU stop operating when the #BUSREQ pin is lowered, thus entering a HALT state. This HALT state is not cleared by an interrupt from the internal peripheral circuits and remains set until the #BUSREQ pin is released back high. Unlike in the case of ordinary releasing of the bus by #BUSREQ, the address bus and bus control signals are not placed in high-impedance state. For a DRAM refresh request that may arise in this HALT state, take one of the corrective measures described above. S1C33L03 FUNCTION PART EPSON B-II-4-33 BCU II CORE BLOCK: BCU (Bus Control Unit) I/O Memory of BCU Table 4.23 shows the control bits of the BCU. These I/O memories are mapped into the area (0x48000 and following addresses) used for the internal 16-bit peripheral circuits. However, these I/O memories can be accessed in bytes or words, as well as in half-words. For the control bits of the external system interface pins assigned to the I/O ports, and for details on how to control the 8-bit programmable timer 0 in order to generate a DRAM refresh cycle, refer to each corresponding section in this manual. Table 4.23 Control Bits of External System Interface Register name Address Bit Name Areas 18-15 0048120 set-up register (HW) DF DE DD DC - A18SZ A18DF1 A18DF0 DB DA D9 D8 - A18WT2 A18WT1 A18WT0 D7 D6 D5 D4 - A16SZ A16DF1 A16DF0 D3 D2 D1 D0 - A16WT2 A16WT1 A16WT0 DF-9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Areas 14-13 0048122 set-up register (HW) B-II-4-34 Function Setting Init. R/W Remarks reserved - Areas 18-17 device size selection 1 8 bits 0 16 bits Areas 18-17 A18DF[1:0] Number of cycles 1 1 3.5 output disable delay time 1 0 2.5 0 1 1.5 0 0 0.5 - reserved A18WT[2:0] Wait cycles Areas 18-17 wait control 1 1 1 7 1 1 0 6 1 0 1 5 1 0 0 4 0 1 1 3 0 1 0 2 0 0 1 1 0 0 0 0 - reserved Areas 16-15 device size selection 1 8 bits 0 16 bits Areas 16-15 A16DF[1:0] Number of cycles 1 1 3.5 output disable delay time 1 0 2.5 0 1 1.5 0 0 0.5 - reserved A16WT[2:0] Wait cycles Areas 16-15 wait control 1 1 1 7 1 1 0 6 1 0 1 5 1 0 0 4 0 1 1 3 0 1 0 2 0 0 1 1 0 0 0 0 - 0 1 1 - 0 when being read. R/W R/W - 1 1 1 - 0 when being read. R/W - 0 1 1 - 0 when being read. R/W R/W - 1 1 1 - 0 when being read. R/W - A14DRA A13DRA A14SZ A14DF1 A14DF0 reserved Area 14 DRAM selection Area 13 DRAM selection Areas 14-13 device size selection Areas 14-13 output disable delay time - 0 0 0 1 1 - 0 when being read. R/W R/W R/W R/W - A14WT2 A14WT1 A14WT0 reserved Areas 14-13 wait control - 1 1 1 - 0 when being read. R/W EPSON - 1 Used 0 Not used 1 Used 0 Not used 1 8 bits 0 16 bits A14DF[1:0] Number of cycles 1 1 3.5 1 0 2.5 0 1 1.5 0 0 0.5 - A14WT[2:0] Wait cycles 1 1 1 7 1 1 0 6 1 0 1 5 1 0 0 4 0 1 1 3 0 1 0 2 0 0 1 1 0 0 0 0 S1C33L03 FUNCTION PART II CORE BLOCK: BCU (Bus Control Unit) A-1 Register name Address Bit Areas 12-11 0048124 set-up register (HW) DF-7 D6 D5 D4 - A12SZ A12DF1 A12DF0 D3 D2 D1 D0 - A12WT2 A12WT1 A12WT0 DF DE DD DC - A10IR2 A10IR1 A10IR0 Areas 10-9 0048126 set-up register (HW) Areas 8-7 0048128 set-up register (HW) Name Function Init. R/W Remarks reserved - Areas 12-11 device size selection 1 8 bits 0 16 bits Areas 12-11 A18DF[1:0] Number of cycles 1 1 3.5 output disable delay time 1 0 2.5 0 1 1.5 0 0 0.5 - reserved A18WT[2:0] Wait cycles Areas 12-11 wait control 1 1 1 7 1 1 0 6 1 0 1 5 1 0 0 4 0 1 1 3 0 1 0 2 0 0 1 1 0 0 0 0 - 0 1 1 - 0 when being read. R/W R/W - 1 1 1 - 0 when being read. R/W reserved Area 10 internal ROM size selection - 1 1 1 - 0 when being read. R/W DB DA D9 - A10BW1 A10BW0 reserved Areas 10-9 burst ROM burst read cycle wait control D8 D7 D6 D5 D4 A10DRA A9DRA A10SZ A10DF1 A10DF0 Area 10 burst ROM selection Area 9 burst ROM selection Areas 10-9 device size selection Areas 10-9 output disable delay time D3 D2 D1 D0 - A10WT2 A10WT1 A10WT0 reserved Areas 10-9 wait control DF-9 D8 D7 D6 D5 D4 - A8DRA A7DRA A8SZ A8DF1 A8DF0 reserved Area 8 DRAM selection Area 7 DRAM selection Areas 8-7 device size selection Areas 8-7 output disable delay time D3 D2 D1 D0 - A8WT2 A8WT1 A8WT0 reserved Areas 8-7 wait control S1C33L03 FUNCTION PART Setting EPSON - A10IR[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 ROM size 2MB 1MB 512KB 256KB 128KB 64KB 32KB 16KB B-II - A10BW[1:0] Wait cycles 1 1 3 1 0 2 0 1 1 0 0 0 1 Used 0 Not used 1 Used 0 Not used 1 8 bits 0 16 bits A10DF[1:0] Number of cycles 1 1 3.5 1 0 2.5 0 1 1.5 0 0 0.5 - A10WT[2:0] Wait cycles 1 1 1 7 1 1 0 6 1 0 1 5 1 0 0 4 0 1 1 3 0 1 0 2 0 0 1 1 0 0 0 0 - 0 0 - 0 when being read. R/W 0 0 0 1 1 R/W R/W R/W R/W - 1 1 1 - 0 when being read. R/W - - 0 0 0 1 1 - 0 when being read. R/W R/W R/W R/W - 1 1 1 - 0 when being read. R/W 1 Used 1 Used 1 8 bits A8DF[1:0] 1 1 1 0 0 1 0 0 0 Not used 0 Not used 0 16 bits Number of cycles 3.5 2.5 1.5 0.5 - A8WT[2:0] Wait cycles 1 1 1 7 1 1 0 6 1 0 1 5 1 0 0 4 0 1 1 3 0 1 0 2 0 0 1 1 0 0 0 0 B-II-4-35 BCU II CORE BLOCK: BCU (Bus Control Unit) Register name Address Bit Name Areas 6-4 004812A DF-E - set-up register (HW) DD A6DF1 DC A6DF0 Bus control register B-II-4-36 004812E (HW) Function reserved Area 6 output disable delay time DB DA D9 D8 - A6WT2 A6WT1 A6WT0 reserved Area 6 wait control D7 D6 D5 D4 - A5SZ A5DF1 A5DF0 reserved Areas 5-4 device size selection Areas 5-4 output disable delay time D3 D2 D1 D0 - A5WT2 A5WT1 A5WT0 reserved Areas 5-4 wait control DF DE DD DC DB DA RBCLK - RBST8 REDO RCA1 RCA0 BCLK output control reserved Burst ROM burst mode selection DRAM page mode selection Column address size selection D9 D8 D7 D6 D5 RPC2 RPC1 RPC0 RRA1 RRA0 D4 D3 D2 D1 D0 - SBUSST SEMAS SEPD SWAITE Setting - A6DF[1:0] Number of cycles 1 1 3.5 1 0 2.5 0 1 1.5 0 0 0.5 - A6WT[2:0] Wait cycles 1 1 1 7 1 1 0 6 1 0 1 5 1 0 0 4 0 1 1 3 0 1 0 2 0 0 1 1 0 0 0 0 - 1 8 bits 0 16 bits A5DF[1:0] Number of cycles 1 1 3.5 1 0 2.5 0 1 1.5 0 0 0.5 A5WT[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 Enabled - 1 8-successive 0 4-successive 1 EDO 0 Fast page RCA[1:0] Size 1 1 11 1 0 10 0 1 9 0 0 8 1 Enabled 0 Disabled Refresh enable 1 Self-refresh 0 CBR-refresh Refresh method selection 1 2.0 0 1.0 Refresh RPC delay setup RRA[1:0] Number of cycles Refresh RAS pulse width 1 1 5 selection 1 0 4 0 1 3 0 0 2 - reserved External interface method selection 1 #BSL 0 A0 External bus master setup 1 Existing 0 Nonexistent 1 Enabled 0 Disabled External power-down control 1 Enabled 0 Disabled #WAIT enable EPSON 1 Fixed at H Wait cycles 7 6 5 4 3 2 1 0 Init. R/W Remarks - 1 1 - 0 when being read. R/W - 1 1 1 - 0 when being read. R/W - 0 1 1 - 0 when being read. R/W R/W - 1 1 1 - 0 when being read. R/W 0 0 0 0 0 0 R/W - Writing 1 not allowed. R/W R/W R/W 0 0 0 0 0 R/W R/W R/W R/W 0 0 0 0 0 - Writing 1 not allowed. R/W R/W R/W R/W S1C33L03 FUNCTION PART II CORE BLOCK: BCU (Bus Control Unit) A-1 Register name Address Bit Name Function DRAM timing 0048130 DF-C - reserved set-up register (HW) DB A3EEN Area 3 emulation DA CEFUNC1 #CE pin function selection D9 CEFUNC0 Access control 0048132 register (HW) G/A read signal 0048138 control register (HW) BCLK select register D8 D7 D6 CRAS RPRC1 RPRC0 Successive RAS mode setup DRAM RAS precharge cycles selection D5 D4 D3 - CASC1 CASC0 reserved DRAM CAS cycles selection D2 D1 D0 - RASC1 RASC0 reserved DRAM RAS cycles selection Setting Init. R/W Remarks - 1 Internal ROM 0 Emulation CEFUNC[1:0] #CE output 1 x #CE7/8..#CE17/18 #CE6..#CE17 0 1 #CE4..#CE10 0 0 1 Successive 0 Normal RPRC[1:0] Number of cycles 1 1 4 1 0 3 0 1 2 0 0 1 - CASC[1:0] Number of cycles 1 1 4 1 0 3 0 1 2 0 0 1 - RASC[1:0] Number of cycles 1 1 4 1 0 3 0 1 2 0 0 1 - 1 0 0 - 0 when being read. R/W R/W 0 0 0 R/W R/W - 0 0 - 0 when being read. R/W - 0 0 - 0 when being read. R/W B-II DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A18IO A16IO A14IO A12IO - A8IO A6IO A5IO A18EC A16EC A14EC A12EC A10EC A8EC A6EC A5EC Area 18, 17 internal/external access 1 Internal 0 External Area 16, 15 internal/external access access access Area 14, 13 internal/external access Area 12, 11 internal/external access reserved - 0 External Area 8, 7 internal/external access 1 Internal Area 6 internal/external access access access Area 5, 4 internal/external access Area 18, 17 endian control 1 Big endian 0 Little endian Area 16, 15 endian control Area 14, 13 endian control Area 12, 11 endian control Area 10, 9 endian control Area 8, 7 endian control Area 6 endian control Area 5, 4 endian control 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W - 0 when being read. R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A18AS A16AS A14AS A12AS - A8AS A6AS A5AS A18RD A16RD A14RD A12RD - A8RD A6RD A5RD Area 18, 17 address strobe signal Area 16, 15 address strobe signal Area 14, 13 address strobe signal Area 12, 11 address strobe signal reserved Area 8, 7 address strobe signal Area 6 address strobe signal Area 5, 4 address strobe signal Area 18, 17 read signal Area 16, 15 read signal Area 14, 13 read signal Area 12, 11 read signal reserved Area 8, 7 read signal Area 6 read signal Area 5, 4 read signal 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W - 0 when being read. R/W R/W R/W R/W R/W R/W R/W - 0 when being read. R/W R/W R/W 0 0 0 0 0 - 0 when being read. R/W x2 speed mode only - 0 when being read. R/W 004813A D7-4 - (B) D3 A1X1MD D2 - D1 BCLKSEL1 D0 BCLKSEL0 S1C33L03 FUNCTION PART reserved Area 1 access-speed reserved BCLK output clock selection EPSON 1 Enabled 0 Disabled - 1 Enabled 0 Disabled 1 Enabled 0 Disabled - 1 Enabled 0 Disabled - 1 2 cycles 0 4 cycles - BCLKSEL[1:0] 1 1 1 0 0 1 0 0 BCLK PLL_CLK OSC3_CLK BCU_CLK CPU_CLK B-II-4-37 BCU II CORE BLOCK: BCU (Bus Control Unit) A18SZ: Areas 18-17 device size selection (DE) / Areas 18-15 set-up register (0x48120) A16SZ: Areas 16-15 device size selection (D6) / Areas 18-15 set-up register (0x48120) A14SZ: Areas 14-13 device size selection (D6) / Areas 14-13 set-up register (0x48122) A12SZ: Areas 12-11 device size selection (D6) / Areas 12-11 set-up register (0x48124) A10SZ: Areas 10-9 device size selection (D6) / Areas 10-9 set-up register (0x48126) A8SZ: Areas 8-7 device size selection (D6) / Areas 8-7 set-up register (0x48128) A5SZ: Areas 5-4 device size selection (D6) / Areas 6-4 set-up register (0x4812A) Select the size of the device connected to each area. Write "1": 8 bits Write "0": 16 bits Read: Valid A device size can be selected for every two areas. An 8-bit size is selected by writing "1" to AxxSZ and a 16-bit size is selected by writing "0" to AxxSZ. Area 6 has its first half (0x300000 through 0x37FFFF) fixed to an 8-bit device and the last half (0x380000 through 0x3FFFFF) fixed to a 16-bit device. At cold start, these bits are set to "0" (16 bits). At hot start, these bits retain their status before being initialized. A18DF1-A18DF0: Areas 18-17 output disable delay time (D[D:C]) / Areas 18-15 set-up register (0x48120) A16DF1-A16DF0: Areas 16-15 output disable delay time (D[5:4]) / Areas 18-15 set-up register (0x48120) A14DF1-A14DF0: Areas 14-13 output disable delay time (D[5:4]) / Areas 14-13 set-up register (0x48122) A12DF1-A12DF0: Areas 12-11 output disable delay time (D[5:4]) / Areas 12-11 set-up register (0x48124) A10DF1-A10DF0: Areas 10-9 output disable delay time (D[5:4]) / Areas 10-9 set-up register (0x48126) A8DF1-A8DF0: Areas 8-7 output disable delay time (D[5:4]) / Areas 8-7 set-up register (0x48128) A6DF1-A6DF0: Area 6 output disable delay time (D[D:C]) / Areas 6-4 set-up register (0x4812A) A5DF1-A5DF0: Areas 5-4 output disable delay time (D[5:4]) / Areas 6-4 set-up register (0x4812A) Set the output-disable delay time. Table 4.24 Output Disable Delay Time AxxDF1 AxxDF0 Delay time 1 1 0 0 1 0 1 0 3.5 cycles 2.5 cycles 1.5 cycles 0.5 cycles When using a device that has a long output-disable time, set a delay time to ensure that no contention for the data bus occurs during the bus operation immediately after a device is read. At cold start, these bits are set to "11" (3.5 cycles). At hot start, the bits retain their status before being initialized. A18WT2-A18WT0: Areas 18-17 wait control (D[A:8]) / Areas 18-15 set-up register (0x48120) A16WT2-A16WT0: Areas 16-15 wait control (D[2:0]) / Areas 18-15 set-up register (0x48120) A14WT2-A14WT0: Areas 14-13 wait control (D[2:0]) / Areas 14-13 set-up register (0x48122) A12WT2-A12WT0: Areas 12-11 wait control (D[2:0]) / Areas 12-11 set-up register (0x48124) A10WT2-A10WT0: Areas 10-9 wait control (D[2:0]) / Areas 10-9 set-up register (0x48126) A8WT2-A8WT0: Areas 8-7 wait control (D[2:0]) / Areas 8-7 set-up register (0x48128) A6WT2-A6WT0: Area 6 wait control (D[A:8]) / Areas 6-4 set-up register (0x4812A) A5WT2-A5WT0: Areas 5-4 wait control (D[2:0]) / Areas 6-4 set-up register (0x4812A) Set the number of wait cycles to be inserted when accessing an SRAM device. The values 0 through 7 written to the control bits equal the number of wait cycles inserted. Note that the write cycle consists of a minimum of two cycles, so that a writing 0 or 1 is invalid. When an SRAM device is connected, wait cycles derived via the #WAIT pin can also be inserted. In this case too, the wait cycles set by AxxWT are valid. The DRAM read/write cycles do not have wait cycles inserted that are set by AxxWT or derived from the #WAIT pin. The burst read cycle of a burst ROM (except for the first access) also does not have any wait cycle inserted. The first read cycle of a burst ROM and the write cycle to the burst ROM area have wait cycles inserted that are set by AxxWT. Wait cycles derived from the #WAIT pin also can be inserted in the cycle for writing to the burst ROM area. At cold start, these bits are set to "111" (7 cycles). At hot start, the bits retain their status before being initialized. B-II-4-38 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: BCU (Bus Control Unit) A-1 A14DRA: Area 14 DRAM selection (D8) / Areas 14-13 set-up register (0x48122) A13DRA: Area 13 DRAM selection (D7) / Areas 14-13 set-up register (0x48122) A8DRA: Area 8 DRAM selection (D8) / Areas 8-7 set-up register (0x48128) A7DRA: Area 7 DRAM selection (D7) / Areas 8-7 set-up register (0x48128) Select the DRAM direct interface. Write "1": DRAM is used Write "0": DRAM is not used Read: Valid When DRAM is used by connecting it directly to the BCU, write "1" to this bit. The ordinary SRAM interface is selected by writing "0" to the control bit. The areas to which DRAM can be connected are areas 8 and 7 when the CEFUNC = "0", or areas 14 and 13 when the bit = "1". At cold start, these bits are set to "0" (DRAM not used). At hot start, the bits retain their status before being initialized. A10IR2-A10IR0: Area 10 internal ROM size selection (D[E:C]) / Areas 10-9 set-up register (0x48126) Select an area 10 internal/emulation memory size. B-II Table 4.25 Area 10 Internal ROM Size A10IR2 A10IR1 A10IR0 ROM size 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 16 KB 32 KB 64 KB 128 KB 256 KB 512 KB 1 MB 2 MB BCU At cold start, A10IR is set to "111" (2 MB). At hot start, A10IR retains its status before being initialized. A10BW1-A10BW0: Burst read cycle wait control (D[A:9]) / Areas 10-9 set-up register (0x48126) Set the number of wait cycles inserted during a burst read. The values 0 to 3 written to the bits constitute the number of wait cycles inserted. The contents set here are applied to both areas 10 and 9. The wait cycles set by AxxWT are inserted in the first read cycle of burst ROM and in the burst ROM write cycle. For the burst ROM write cycle, the wait cycles set via the #WAIT pin can also be used. At cold start, A10BW is set to "0" (no wait cycle). At hot start, A10BW retains its status before being initialized. S1C33L03 FUNCTION PART EPSON B-II-4-39 II CORE BLOCK: BCU (Bus Control Unit) A10DRA: Area 10 burst ROM selection (D8) / Areas 10-9 set-up register (0x48126) A9DRA: Area 9 burst ROM selection (D7) / Areas 10-9 set-up register (0x48126) Set areas 10 and 9 for use of burst ROM. Write "1": Burst ROM is used Write "0": Burst ROM is not used Read: Valid When using burst ROM, write "1" to the control bit. The ordinary SRAM interface is selected by writing "0" to the bit. Area 9 can only be used when the CEFUNC = "00". At cold start, these bits are set to "0" (burst ROM not used). At hot start, the bits retain their status before being initialized. RBCLK: BCLK output control (DF) / Bus control register (0x4812E) Control the bus clock BCLK to enable or disable external output. Write "1": Fixed at high level Write "0": Output enabled Read: Valid To stop outputting the bus clock from the BCLK pin, write "1" to RBCLK. When the clock output is stopped, the BCLK pin is fixed at high level. The bus clock output from the BCLK pin is enabled by writing "0" to RBCLK. The bus clock output from the BCLK pin also is stopped in the HALT2 and the SLEEP modes. At cold start, the RBCLK is set to "0" (output enabled). At hot start, RBCLK retains its status before being initialized. RBST8: Burst mode selection (DD) / Bus control register (0x4812E) Set the operation mode during a burst read. Write "1": 8-successive-burst mode Write "0": 4-successive-burst mode Read: Valid The 8-successive-burst mode is selected by writing "1" to RBST8 and the 4-successive-burst mode is selected by writing "0" to RBST8. This setting is valid when areas 10 and 9 are set for burst ROM, and the setting is applied to both areas simultaneously. At cold start, RBST8 is set to "0" (4-successive-burst mode). At hot start, RBST8 retains its status before being initialized. REDO: Page mode selection (DC) / Bus control register (0x4812E) Select the page mode of DRAM. Write "1": EDO-page mode Write "0": Fast-page mode Read: Valid When using EDO DRAM, write "1" to REDO to select the EDO-page mode. The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM. At cold start, REDO is set to "0" (fast-page mode). At hot start, REDO retains its status before being initialized. B-II-4-40 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: BCU (Bus Control Unit) A-1 RCA1-RCA0: Column address size selection (D[B:A]) / Bus control register (0x4812E) Select the column address size of DRAM. Table 4.26 Column Address Size RCA1 RCA0 Column address size 1 1 0 0 1 0 1 0 11 10 9 8 The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM. RCA can be read to obtain its set value. At cold start, RCA is set to "0" (8 bits). At hot start, RCA retain its status before being initialized. RPC2: Refresh enable (D9) / Bus control register (0x4812E) Control the DRAM refresh function. Write "1": Enabled Write "0": Disabled Read: Valid B-II When DRAM is connected directly, a refresh cycle is generated by writing "1" to RPC2. The internal refresh function is disabled by writing "0" to RPC2. Since the BCU stops operating in the HALT2 and the SLEEP modes, no refresh cycle is generated regardless of how this bit is set. The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM. At cold start, RPC2 is set to "0" (disabled). At hot start, RPC2 retains its status before being initialized. RPC1: Refresh method selection (D8) / Bus control register (0x4812E) Select the DRAM refresh method. Write "1": Self-refresh Write "0": CAS-before-RAS refresh Read: Valid To perform a CAS-before-RAS refresh, set RPC1 to "0" and then RPC2 to "1". This causes the underflow output signal of the 8-bit programmable timer 0 is fed to the DRAM interface, at which timing a refresh cycle is generated. To start a self-refresh, set RPC1 to "1" and then RPC2 to "1". The self-refresh is disabled by writing "0" to RPC2. The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM. At cold start, RPC1 is set to "0" (CAS-before-RAS refresh). At hot start, RPC1 retains its status before being initialized. RPC0: Refresh RPC delay (D7) / Bus control register (0x4812E) Set a RPC delay when at start of refresh. Write "1": 2 cycles Write "0": 1 cycle Read: Valid Set a time from the immediately preceding precharge to the falling transition of #HCAS/#LCAS necessary in order to perform a refresh. This time is 2 cycles when RPC0 = "1" or 1 cycle when RPC0 = "0". The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM. At cold start, RPC0 is set to "0" (1 cycle). At hot start, RPC0 retains its status before being initialized. S1C33L03 FUNCTION PART EPSON B-II-4-41 BCU II CORE BLOCK: BCU (Bus Control Unit) RRA1-RRA0: Refresh RAS pulse width selection (D[6:5]) / Bus control register (0x4812E) Select the RAS pulse width of a CAS-before-RAS refresh. Table 4.27 Refresh RAS Pulse Width RRA1 RRA0 Pulse width 1 1 0 0 1 0 1 0 5 cycles 4 cycles 3 cycles 2 cycles The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM. The RRA can be read to obtain their set value. At cold start, RRA is set to "0" (2 cycles). At hot start, RRA retains its status before being initialized. SBUSST: External interface method select register (D3) / Bus control register (0x4812E) Select the interface method of an SRAM device. Write "1": #BSL system Write "0": A0 system Read: Valid When using the #BSL system, write "1" to SBUSST. The contents set here are applied to all areas that are set for the SRAM type. At cold start, SBUSST is set to "0" (A0 system). At hot start, SBUSST retains its status before being initialized. SEMAS: External bus master setup (D2) / Bus control register (0x4812E) Specify whether an external bus master exists. Write "1": Existing Write "0": Nonexistent Read: Valid A request for bus ownership control via the #BUSREQ pin is made acceptable by writing "1" to SEMAS. If the system does not have any external bus master, fix this register at "0". At cold start, SEMAS is set to "0" (nonexistent). At hot start, SEMAS retains its status before being initialized. SEPD: External power-down control (D1) / Bus control register (0x4812E) Enable or disable the CPU's power-down control by an external bus master. Write "1": Enabled Write "0": Disabled Read: Valid Power-down control via an external pin (#BUSREQ) is enabled by writing "1" to SEPD. If the #BUSREQ pin is lowered when external power-down control is thus enabled, the CPU is placed in a HALT state, allowing for reduction in power consumption. At cold start, SEPD is set to "0" (disabled). At hot start, SEPD retains its status before being initialized. B-II-4-42 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: BCU (Bus Control Unit) A-1 SWAITE: #WAIT enable (D0) / Bus control register (0x4812E) Enable or disable wait cycle control via the #WAIT pin. Write "1": Enabled Write "0": Disabled Read: Valid A wait request from an SRAM device is made acceptable by writing "1" to SWAITE. The wait request signal input from the #WAIT pin is sampled at each falling edge of the bus clock when executing an SRAM read/write cycle. Wait cycles are inserted until the wait request signal is sampled and detected as high (inactive). Wait control for 0 to 7 cycles can be accomplished by AxxWT without using the #WAIT pin. However, since the setting via AxxWT is applied to every two areas, the number of wait cycles may be controlled individually in each area or more than 7 wait cycles may be set. In such a case, use an external wait request via the #WAIT pin. Wait requests from the #WAIT pin are ignored when SWAITE = "0". The contents set here are applied to all areas that are set for SRAM, and are also effective for write cycles in the areas that are set for burst ROM. At cold start, SWAITE is set to "0" (disabled). At hot start, SWAITE retains its status before being initialized. A3EEN: Area 3 emulation (DB) / DRAM timing set-up register (0x48130) B-II Select area 3 emulation mode. Write "1": Internal ROM mode Write "0": Emulation mode Read: Valid BCU When "0" is written to A3EEN, internal ROM emulation mode is selected and the external device will be accessed with the same condition as the internal ROM. When "1" is written, the internal ROM will be used for accessing area 3. This bit functions the same as the EA3MD pin. The bit status and the pin status are logically ORed. At cold start, A3EEN is set to "1" (internal ROM mode). At hot start, A3EEN retains its status before being initialized. CEFUNC1-CEFUNC0: #CE pin function selection (D[A:9]) / DRAM timing set-up register (0x48130) Change the #CE pin-assigned area. Table 4.28 #CE Output Assignment Pin #CE4 #CE5 #CE6 #CE7/#RAS0 #CE8/#RAS1 #CE9 #CE10EX CEFUNC = "00" #CE4 #CE5 #CE6 #CE7/#RAS0 #CE8/#RAS1 #CE9 #CE10EX CEFUNC = "01" #CE11 #CE15 #CE6 #CE13/#RAS2 #CE14/#RAS3 #CE17 #CE10EX CEFUNC = "1x" #CE11+#CE12 #CE15+#CE16 #CE7+#CE8 #CE13/#RAS2 #CE14/#RAS3 #CE17+#CE18 #CE9+#CE10EX (Default: CEFUNC = "00") The high-order areas that are made available for use by writing "01" to CEFUNC can be larger in size than the default low-order areas. For example, when using DRAM in default settings, the available space is 4 MB in areas 7 and 8. However, if areas 13 and 14 are used, up to 32 MB of DRAM can be used. The same applies to the other areas. Furthermore, when CEFUNC is set to "10" or "11", four chip enable signal is expanded into two area size. At cold start, CEFUNC is set to "00". At hot start, CEFUNC retains its status before being initialized. S1C33L03 FUNCTION PART EPSON B-II-4-43 II CORE BLOCK: BCU (Bus Control Unit) CRAS: Successive RAS mode (D8) / DRAM timing set-up register (0x48130) Set the successive RAS mode. Write "1": Successive RAS mode Write "0": Normal mode Read: Valid In systems using DRAM, the successive RAS mode is entered by writing "1" to CRAS. In this mode, read/write operations can be performed in page mode even when DRAM accesses do not occur back-to-back. When using the successive RAS mode, be sure to use #DRD for the read signal and #DWE for the write signal for low-byte. When CRAS = "0", random read/write cycles are used for non-successive DRAM accesses. The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM. At cold start, CRAS is set to "0" (normal mode). At hot start, CRAS retains its status before being initialized. RPRC1-RPRC0: Number of RAS precharge cycles (D[7:6]) / DRAM timing set-up register (0x48130) Select the number of precharge cycles during a DRAM access. Table 4.29 Number of RAS Precharge Cycles RPRC1 RPRC0 Number of cycles 1 1 0 0 1 0 1 0 4 cycles 3 cycles 2 cycles 1 cycle The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM. At cold start, RPRC is set to "0" (1 cycle). At hot start, RPRC retains its status before being initialized. CASC1-CASC0: Number of CAS cycles (D[4:3]) / DRAM timing set-up register (0x48130) Select the number of CAS cycles during a DRAM access. Table 4.30 Number of CAS Cycles CASC1 CASC0 Number of cycles 1 1 0 0 1 0 1 0 4 cycles 3 cycles 2 cycles 1 cycle The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM. At cold start, CASC is set to "0" (1 cycle). At hot start, CASC retains its status before being initialized. RASC1-RASC0: Number of RAS cycles (D[1:0]) / DRAM timing set-up register (0x48130) Select the number of RAS cycles during a DRAM access. Table 4.31 Number of RAS Cycles RASC1 RASC0 Number of cycles 1 1 0 0 1 0 1 0 4 cycles 3 cycles 2 cycles 1 cycle The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM. At cold start, RASC is set to "0" (1 cycle). At hot start, RASC retains its status before being initialized. B-II-4-44 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: BCU (Bus Control Unit) A-1 A18IO: Areas 18-17 internal/external access selection (DF) / Access control register (0x48132) A16IO: Areas 16-15 internal/external access selection (DE) / Access control register (0x48132) A14IO: Areas 14-13 internal/external access selection (DD) / Access control register (0x48132) A12IO: Areas 12-11 internal/external access selection (DC) / Access control register (0x48132) A8IO: Areas 8-7 internal/external access selection (DA) / Access control register (0x48132) A6IO: Area 6 internal/external access selection (D9) / Access control register (0x48132) A5IO: Areas 5-4 internal/external access selection (D8) / Access control register (0x48132) Select either internal access or external access for each area. Write "1": Internal access Write "0": External access Read: Valid When AxxIO is set to "1", the internal device that mapped to the corresponding area is accessed. When AxxIO is set to "0", the external device is accessed. At cold start, these bits are set to "0" (external access). At hot start, these bits retain their status before being initialized. A18EC: Areas 18-17 little/big endian method selection (D7) / Access control register (0x48132) A16EC: Areas 16-15 little/big endian method selection (D6) / Access control register (0x48132) A14EC: Areas 14-13 little/big endian method selection (D5) / Access control register (0x48132) A12EC: Areas 12-11 little/big endian method selection (D4) / Access control register (0x48132) A10EC: Areas 10-9 little/big endian method selection (D3) / Access control register (0x48132) A8EC: Areas 8-7 little/big endian method selection (D2) / Access control register (0x48132) A6EC: Area 6 little/big endian method selection (D1) / Access control register (0x48132) A5EC: Areas 5-4 little/big endian method selection (D0) / Access control register (0x48132) Select either little endian or big-endian method for accessing each area. B-II BCU Write "1": Big-endian Write "0": Little-endian Read: Valid When AxxEC is set to "1", the corresponding area is accessed in big-endian method. When AxxEC is set to "0", the area is accessed in little-endian method. When using area 10 as the boot area, fix A10EC at "0" (little-endian). At cold start, these bits are set to "0" (little-endian). At hot start, these bits retain their status before being initialized. A18AS: Areas 18-17 address strobe signal (DF) / G/A read signal control register (0x48138) A16AS: Areas 16-15 address strobe signal (DE) / G/A read signal control register (0x48138) A14AS: Areas 14-13 address strobe signal (DD) / G/A read signal control register (0x48138) A12AS: Areas 12-11 address strobe signal (DC) / G/A read signal control register (0x48138) A8AS: Areas 8-7 address strobe signal (DA) / G/A read signal control register (0x48138) A6AS: Area 6 address strobe signal (D9) / G/A read signal control register (0x48138) A5AS: Areas 5-4 address strobe signal (D8) / G/A read signal control register (0x48138) Enable/disable the exclusive address strobe signal output. Write "1": Enabled Write "0": Disabled Read: Valid If AxxAS is set to "1", the exclusive address strobe signal is output from #GAAS (P21) pin when the corresponding area is accessed. If AxxAS is set to "0", the signal output is disabled. At cold start, these bits are set to "0" (disabled). At hot start, these bits retain their status before being initialized. S1C33L03 FUNCTION PART EPSON B-II-4-45 II CORE BLOCK: BCU (Bus Control Unit) A18RD: Areas 18-17 read signal (D7) / G/A read signal control register (0x48138) A16RD: Areas 16-15 read signal (D6) / G/A read signal control register (0x48138) A14RD: Areas 14-13 read signal (D5) / G/A read signal control register (0x48138) A12RD: Areas 12-11 read signal (D4) / G/A read signal control register (0x48138) A8RD: Areas 8-7 read signal (D2) / G/A read signal control register (0x48138) A6RD: Area 6 read signal (D1) / G/A read signal control register (0x48138) A5RD: Areas 5-4 read signal (D0) / G/A read signal control register (0x48138) Enable/disable the exclusive read signal output. Write "1": Enabled Write "0": Disabled Read: Valid If AxxRD is set to "1", the exclusive read signal is output from #GARD (P31) pin when the corresponding area is read. If AxxRD is set to "0", the signal output is disabled. At cold start, these bits are set to "0" (disabled). At hot start, these bits retain their status before being initialized. BCLKSEL1-BCLKSEL0: BCLK output clock selection (D[1:0]) / BCLK select register (0x4813A) Select a clock to be output from the BCLK pin. These bits are effective only when SDRENA (D7/0x39FFC1) is "0". Table 4.32 Selection of BCLK Output Clock SDRENA BCLKSEL1 BCLKSEL0 0 1 1 0 0 - 1 0 1 0 - 1 PLL_CLK: Output clock PLL_CLK (PLL output clock) OSC3_CLK (OSC3 oscillation clock) BCU_CLK (BCU operating clock) CPU_CLK (CPU operating clock) SD_CLK (SDRAM clock) PLL output clock. This clock is stable and kept as output except in the following cases: 1. When the PLL is off by setting the PLLS[1:0] pins. 2. When the OSC3 (high-speed) oscillation is stopped by executing the SLP instruction. 3. When the OSC3 (high-speed) oscillation is stopped using the CLG register. Note that the PLL_CLK clock is out of phase with the CPU operating clock. OSC3_CLK: OSC3 (high-speed) oscillation circuit output clock. This clock is stable and kept as output except in the following cases: 1. When the OSC3 (high-speed) oscillation is stopped by executing the SLP instruction. 2. When the OSC3 (high-speed) oscillation is stopped using the CLG register. Note that the OSC3_CLK clock is out of phase with the CPU operating clock. BCU_CLK: Bus clock in the bus controller. This clock varies according to the bus cycle speed. Furthermore, the clock frequency changes dynamically in x2 speed mode as follows: 1. When the internal RAM/ROM is accessed, x2 clock (e.g., 50 MHz same as the CPU operating clock) is output. 2. When an external device is accessed via the external bus, x1 clock (e.g., 25 MHz) is output. This dynamic change (e.g., between 50 MHz and 25 MHz) does not affect the external memory access timing, such as position relationship between the rising or falling edge of the 25 MHz clock and the falling edge of the #WR signal. (It is the same as that in the x1 speed mode with 25 MHz clock.) CPU_CLK: The CPU operating clock. The clock frequency is as follows: 1. Equals to the PLL output clock frequency when the PLL is on. 2. Equals to the OSC3 (high-speed) oscillation circuit output clock frequency when the PLL is off. 3. However, it equals to the divided frequency when the CLG is set to generate the CPU operating clock by dividing the source clock. 4. When the CPU stops by the HALT or SLP instruction, this clock is also stopped. This clock is almost in phase with the bus clock. At initial reset, BCLKSEL is set to "00" (CPU_CLK). B-II-4-46 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: BCU (Bus Control Unit) A-1 SDRENA: Enable SDRAM signals (D7) / SDRAM control register (0x39FFC1) Enable the pins used for the SDRAM. Write "1": Enabled Write "0": Disabled Read: Valid Writing "1" to SDRENA sets the pins shared with other functions to be used for the SDRAM, with the SDRAM clock output from the BCLK pin. If SDRENA = "0", the shared pins serve other functions. The SDRAM clock output from the BCLK pin is stopped in the HALT2 and the SLEEP modes. At cold start, SDRENA is set to "0" (disabled). At hot start, SDRENA retains its status before being initialized. A1X1MD: Area 1 access speed (D3) / BCLK select register (0x4813A) Select a number of access cycles for area 1 in x2 speed mode. Write "1": 2 cycles Write "0": 4 cycles Read: Valid When x2 speed mode is set (#X2SPD pin = "0") and A1X1MD = "1", area 1 is read/written in 2 cycles of the CPU system clock. When A1X1MD = "0", area 1 is read/written in 4 cycles. When x1 speed mode is set (#X2SPD pin = "1"), area 1 is always accessed in 2 cycles regardless of the A1X1MD value. At cold start, A1X1MD is set to "0" (4 cycles). At hot start, A1X1MD retains its status before being initialized. S1C33L03 FUNCTION PART EPSON B-II-4-47 B-II BCU II CORE BLOCK: BCU (Bus Control Unit) THIS PAGE IS BLANK. B-II-4-48 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: ITC (Interrupt Controller) A-1 II-5 ITC (Interrupt Controller) The C33 Core Block contains an interrupt controller, making it possible to control all interrupts generated by the internal peripheral circuits. This section explains the functions of this interrupt controller centering around the method for controlling maskable interrupts. For details about the various factors and conditions under which interrupts are generated, refer to the description of each peripheral circuit in this manual. Outline of Interrupt Functions Maskable Interrupts The ITC can handle 39 kinds of maskable interrupts as shown in the table below. Table 5.1 List of Maskable Interrupts HEX Vector number No. No. (Hex address) 1 2 3 4 5 6 7 8 9 10 11 - 12 13 - 14 15 - 16 17 - 18 19 - 20 21 - 22 23 24 25 26 27 28 29 30 - 31 32 33 - 34 35 - 36 37 38 39 10 11 12 13 14 15 16 17 18 19 1A Interrupt system (Peripheral circuit) Port input interrupt 0 Port input interrupt 1 Port input interrupt 2 Port input interrupt 3 Key input interrupt 0 Key input interrupt 1 High-speed DMA Ch.0 High-speed DMA Ch.1 High-speed DMA Ch.2 High-speed DMA Ch.3 IDMA reserved 16-bit programmable timer 0 40 41 16(Base+40) 17(Base+44) 18(Base+48) 19(Base+4C) 20(Base+50) 21(Base+54) 22(Base+58) 23(Base+5C) 24(Base+60) 25(Base+64) 26(Base+68) 27-29 30(Base+78) 31(Base+7C) 32-33 34(Base+88) 35(Base+8C) 36-37 38(Base+98) 39(Base+9C) 40-41 42(Base+A8) 43(Base+AC) 44-45 46(Base+B8) 47(Base+BC) 48-49 50(Base+C8) 51(Base+CC) 52(Base+D0) 53(Base+D4) 54(Base+D8) 55(Base+DC) 56(Base+E0) 57(Base+E4) 58(Base+E8) 59 60(Base+F0) 61(Base+F4) 62(Base+F8) 63 64(Base+100) 65(Base+104) 44 45 46 47 66-67 68(Base+110) 69(Base+114) 70(Base+118) 71(Base+11C) reserved Port input interrupt 4 Port input interrupt 5 Port input interrupt 6 Port input interrupt 7 1E 1F 22 23 26 27 2A 2B 2E 2F 32 33 34 35 36 37 38 39 3A 3C 3D 3E reserved 16-bit programmable timer 1 reserved 16-bit programmable timer 2 reserved 16-bit programmable timer 3 reserved 16-bit programmable timer 4 reserved 16-bit programmable timer 5 8-bit programmable timer Serial interface Ch.0 reserved Serial interface Ch.1 reserved A/D converter Clock timer S1C33L03 FUNCTION PART Interrupt factor Edge (rising or falling) or level (High or Low) Edge (rising or falling) or level (High or Low) Edge (rising or falling) or level (High or Low) Edge (rising or falling) or level (High or Low) Rising or falling edge Rising or falling edge High-speed DMA Ch.0, end of transfer High-speed DMA Ch.1, end of transfer High-speed DMA Ch.2, end of transfer High-speed DMA Ch.3, end of transfer Intelligent DMA, end of transfer - Timer 0 comparison B Timer 0 comparison A - Timer 1 comparison B Timer 1 comparison A - Timer 2 comparison B Timer 2 comparison A - Timer 3 comparison B Timer 3 comparison A - Timer 4 comparison B Timer 4 comparison A - Timer 5 comparison B Timer 5 comparison A Timer 0 underflow Timer 1 underflow Timer 2 underflow Timer 3 underflow Receive error Receive buffer full Transmit buffer empty - Receive error Receive buffer full Transmit buffer empty - A/D converter, end of conversion Falling edge of 32 Hz, 8 Hz, 2 Hz or 1 Hz signal 1-minuet, 1-hour or specified time count up - Edge (rising or falling) or level (High or Low) Edge (rising or falling) or level (High or Low) Edge (rising or falling) or level (High or Low) Edge (rising or falling) or level (High or Low) EPSON IDMA Ch. Priority 1 2 3 4 - - 5 6 - - - - 7 8 - 9 10 - 11 12 - 13 14 - 15 16 - 17 18 19 20 21 22 - 23 24 - - 25 26 - 27 - - 28 29 30 31 High B-II ITC Low B-II-5-1 II CORE BLOCK: ITC (Interrupt Controller) Contents of table "Hex No." indicates an interrupt number in hexadecimal value. "Vector number (Address)" indicates the trap table's vector number. The numerals in parentheses show an offset (in bytes) from the starting address (Base) of the trap table. The starting address (Base) of the trap table by default is the boot address, 0xC00000 set at an initial reset. This address can be changed using the TTBR register (0x48134 to 0x48137). For details about the trap table contents including exception factors, etc., refer to the "S1C33000 Core CPU Manual". "Interrupt system (Peripheral circuit)" indicates that interrupt levels can be programmed for each peripheral circuit written. "Interrupt factor" indicates the factor of the interrupt occurring in each interrupt system. "IDMA Ch." indicates that an interrupt factor which has a numeric value in this column can start up the intelligent DMA (IDMA) to transfer data when an interrupt factor occurs. The numeric value indicates the IDMA's channel number. Interrupt factors that do not have a numeric value here cannot start up the IDMA. "Priority" indicates the priority of interrupts in cases when all interrupt systems are set to the same interrupt level. If two or more interrupt factors occur simultaneously, interrupt requests are accepted in order of highest priority. Interrupt priority varies depending on the interrupt levels set in each interrupt system. However, the priorities of interrupt factors in the same interrupt system are fixed in the order that they are written here. Maskable interrupt generating conditions A maskable interrupt to the CPU occurs when all of the conditions described below are met. * The interrupt enable register for the interrupt factor that has occurred is set to "1". * The IE (Interrupt Enable) bit of the Processor Status Register (PSR) in the CPU is set to "1". * The interrupt factor that has occurred has a higher priority level than the value that is set in the PSR's Interrupt Level (IL). (The interrupt levels can be set using the interrupt priority register in each interrupt system.) * No other trap factor having higher priority, such as NMI, has occurred. * The interrupt factor does not invoke IDMA (the IDMA request bit is set to "0"). When an interrupt factor occurs, the corresponding interrupt factor flag is set to "1" and the flag remains set until it is reset in the software program. Therefore, in no cases can the generated interrupt factor be inadvertently cleared even if the above conditions are not met when the interrupt factor has occurred. The interrupt will occur when the above conditions are met. However, when the interrupt factor invokes IDMA, the interrupt factor is reset if the following condition is met. * The IDMA transfer counter is not "0". * Interrupts are disabled in the IDMA control information even if the transfer counter is "0". If two or more maskable interrupt factors occur simultaneously, the interrupt factor that has the highest priority is allowed to signal an interrupt request to the CPU. The other interrupts with lower priorities are kept pending until the above conditions are met. The PSR and interrupt control register will be detailed later. For details about interrupt factor generating conditions, refer to the description of each peripheral circuit in this manual. B-II-5-2 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: ITC (Interrupt Controller) A-1 Interrupt Factors and Intelligent DMA Several interrupt factors can be set so that they can invoke IDMA startup. When one of these interrupt factors occurs, IDMA is started up before an interrupt request to the CPU. The interrupt request to the CPU is generated after IDMA is completed. (The interrupt request can be disabled by a program.) IDMA is always started up regardless of how the PSR is set. For details, refer to "IDMA Invocation". Nonmaskable Interrupt (NMI) The nonmaskable interrupt (NMI) can be generated by pulling the #NMI pin low or using the internal watchdog timer. The vector number of NMI is 7, with the vector address set to the trap table's starting address + 28 bytes. This interrupt is prioritized over other interrupts and is unconditionally accepted by the CPU. However, since this interrupt may operate erratically if it occurs before the stack pointer (SP) is set up, it is masked in hardware until a write to the SP is completed after an initial reset. Interrupt Processing by the CPU The CPU keeps sampling interrupt requests every cycle. When the CPU accepts an interrupt request, it enters trap processing after completing execution of the instruction that was being executed. The following lists the contents executed in trap processing. B-II (1) The PSR and the current program counter (PC) value are saved to the stack. (2) The IE bit of the PSR is reset to "0" (following maskable interrupts are disabled). (3) The IL of the PSR is set to the priority level of the accepted interrupt (NMI does not have its interrupt level changed). (4) The vector of the generated interrupt factor is loaded into the PC, thus executing the interrupt processing routine. ITC Thus, once an interrupt is accepted, all maskable interrupts that may follow are disabled in (2). Multiple interrupts can also be handled by setting the IE bit to "1" in the interrupt processing routine. In this case, since the IL has been changed in (3), only an interrupt that has a higher priority than that of the currently processed interrupt is accepted. When the interrupt processing routine is terminated by the reti instruction, the PSR is restored to its previous status before the interrupt has occurred. The program restarts processing after branching to the instruction next to the one that was being executed when the interrupt occurred. Clearing Standby Mode by Interrupts The standby modes (HALT and SLEEP) are cleared by an NMI or a maskable interrupt. All maskable interrupts can be used to clear HALT mode. However, if the bus clock has stopped in HALT2 mode, a DMA interrupt cannot be used. In SLEEP mode, since the high-speed (OSC3) oscillation circuit is deactivated, interrupts from the peripheral circuits that operate with the OSC3 clock cannot be used. Interrupts that can be used to clear basic HALT mode: NMI and all maskable interrupts Interrupts that can be used to clear HALT2 mode: NMI and all maskable interrupts (except DMA interrupts) Interrupts that can be used to clear SLEEP mode: NMI, input port interrupts, and clock timer interrupts Clearing of the standby modes is accomplished by an interrupt request to the CPU. Therefore, this requires that the PSR be set in such a way that the requested interrupt will be accepted, and that the interrupt enable register for the interrupt factor be set to accept the interrupt. When standby mode is cleared and the CPU has accepted the interrupt, it returns to the instruction next to the halt or slp instruction after executing the interrupt processing routine. Note: If the interrupt factor used to restart from the standby mode has been set to invoke the IDMA, the IDMA is started up by that interrupt. In the case of SLEEP mode, the high-speed (OSC3) oscillation circuit also starts operating. If an interrupt to be generated upon completion of IDMA is disabled at the setting of the IDMA side, no interrupt request is signaled to the CPU. Therefore, the CPU remains idle until the next interrupt request is generated. S1C33L03 FUNCTION PART EPSON B-II-5-3 II CORE BLOCK: ITC (Interrupt Controller) Trap Table The C33 Core Block allows the base (starting) address of the trap table to be set by the TTBR register. TTBR0 (D[9:0]) / TTBR low-order register (0x48134): Trap table base address [9:0] (fixed at "0") TTBR1 (D[F:A]) / TTBR low-order register (0x48134): Trap table base address [15:10] TTBR2 (D[B:0]) / TTBR high-order register (0x48136): Trap table base address [27:16] TTBR3 (D[F:C]) / TTBR high-order register (0x48136): Trap table base address [31:28] (fixed at "0") After an initial reset, the TTBR register is set to 0x0C00000. Therefore, even when the trap table position is changed, it is necessary that at least the reset vector be written to the above address. TTBR0 and TTBR3 are read-only bits which are fixed at "0". Therefore, the trap table starting address always begins with a 1KB boundary address. The TTBR register is normally write-protected to prevent them from being inadvertently rewritten. To remove this write protection function, another register, TBRP (D[7:0]) / TTBR write-protect register (0x4812D [byte]), is provided. A write to the TTBR register is enabled by writing "0x59" to TBRP and is disabled back again by a write to the most significant byte of the TTBR register (0x48137). Consequently, a write to the TTBR register needs to begin with the low-order half-word first. However, since an occurrence of NMI or the like between writes of the low-order and high-order half-words would cause a malfunction, it is recommended that the register be written in words. B-II-5-4 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: ITC (Interrupt Controller) A-1 Control of Maskable Interrupts Structure of the Interrupt Controller The interrupt controller is configured as shown in Figure 5.1. ITC Key input x HSDMA x Interrupt factor flag CPU interrupt priority judgment (with interrupt level) Interrupt enable IDMA request Interrupt vector generator IDMA enable Interrupt factors 16-bit timer x 8-bit timer x Serial I/F x A/D Port input x Interrupt factor flag Interrupt enable IDMA request IDMA enable Interrupt request Interrupt level IDMA request priority judgment (without interrupt level) IDMA request IDMA channel number generator IDMA completion ** * CPU Interrupt vector IDMA channel number IDMA Reset A Reset B Reset C B-II HSDMA trigger selection circuit Ch.x HSDMA request HSDMA Ch.x K5x (#DMAREQx) input Software trigger Figure 5.1 Configuration of Interrupt Controller ITC The following sections explain the functions of the registers used to control interrupts. Processor Status Register (PSR) The PSR is a special register incorporated in the core CPU and contains control bits to enable or disable an interrupt request to the CPU. Interrupt Enable (IE) bit: PSR[4] This bit is used to enable or disable an interrupt request to the CPU. When this bit is set to "1", the CPU is enabled to accept a maskable interrupt request. When this bit is reset to "0", no maskable interrupt request is accepted by the CPU. When the CPU accepts an interrupt request (or some other trap occurs), it saves the PSR to the stack and resets the IE bit to "0". Consequently, no maskable interrupt request occurring thereafter will be accepted unless the IE bit is set to "1" in software program or the interrupt (trap) processing routine is terminated by the reti instruction. The IE bit is initialized to "0" (interrupts disabled) by an initial reset. Interrupt Level (IL): PSR[11:8] The IL bits disable the interrupts whose priorities are below the set interrupt level. For example, if the interrupt level set in the IL is 3, the interrupts whose priorities are set below 3 in the interrupt priority register (described later) are not accepted by the CPU even if the IE bit is set to "1". The IL and the interrupt priority register together allow you to control the interrupt priorities in each interrupt system. For details about the interrupt levels, refer to "Interrupt Priority Register and Interrupt Levels". When the CPU accepts a maskable interrupt request, it saves the PSR to the stack and sets the IL to the accepted interrupt's priority level. Therefore, even when the IE bit is set to "1" in the interrupt processing routine, no interrupts whose priority levels are equal or below that of the interrupt currently being processed are accepted unless the IL is rewritten. The IL is restored to its previous status when the interrupt processing routine is terminated by the reti instruction. S1C33L03 FUNCTION PART EPSON B-II-5-5 II CORE BLOCK: ITC (Interrupt Controller) The IL is rewritten for only maskable interrupts and not for any other traps (except a reset). The IL is set to level 0 (that is, all interrupts above level 1 are enabled) by an initial reset. Note: As the S1C33000 Core CPU function, the IL allows interrupt levels to be set in the range of 0 to 15. However, since the interrupt priority register in the ITC consists of three bits, interrupt levels in each interrupt system can only be set for up to 8. Interrupt Factor Flag and Interrupt Enable Register An interrupt factor flag and an interrupt enable register are provided for each maskable interrupt factor. Interrupt factor flag The interrupt factor flag is set to "1" when the corresponding interrupt factor occurs. Reading the flag enables you to determine what caused an interrupt, making it unnecessary to resort to the CPU's trap processing. The interrupt factor flag is reset by writing data in software or by IDMA operation. Note that the method by which this flag is reset can be selected from the software application using either of the two methods described below. This selection is accomplished using RSTONLY (D0) / Flag set/reset method select register (0x4029F). * Reset-only method (default) This method is selected (RSTONLY = "1") when initially reset. With this method, the interrupt factor flag is reset by writing "1". Although multiple interrupt factor flags are located at the same address of the interrupt control register, the interrupt factor flags for which "0" has been written can be neither set nor reset. Therefore, this method ensures that only a specific factor flag is reset. However, when using read-modify-write instructions (e.g., bset, bclr, or bnot), note that an interrupt factor flag that has been set to "1" is reset by writing. In this method, no interrupt factor flag can be set in the software application. * Read/write method This method is selected by writing "0" to RSTONLY. When this method is used, interrupt factor flags can be read and written as for other registers. Therefore, the flag is reset by writing "0" and set by writing "1". In this case, all factor flags for which "0" has been written are reset. Even in a read-modify-write operation, an interrupt factor can occur between the read and the write, so be careful when using this method. Since interrupt factor flags are not initialized by an initial reset, be sure to reset them before enabling interrupts. Note: Even when a maskable interrupt request is accepted by the CPU and control branches off to the interrupt processing routine, the interrupt factor flag is not reset. Consequently, if control is returned from the interrupt processing routine by the reti instruction without resetting the interrupt factor flag in a program, the same interrupt factor occurs again. For details about interrupt factor generating conditions, refer to the description of each peripheral circuit in this manual. B-II-5-6 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: ITC (Interrupt Controller) A-1 Interrupt enable register This register controls the output of an interrupt request to the CPU. Only when the interrupt enable bit of this register is set to "1" can an interrupt request to the CPU be enabled by an occurrence of the corresponding interrupt factor. If the bit is set to "0", no interrupt request is made to the CPU even when the corresponding interrupt factor occurs. Interrupt enable bits can be read and written as for other registers. Therefore, the interrupt enable bit is reset by writing "0" and set by writing "1". By reading this register, its setup status can be checked at any time. Settings of the interrupt enable register do not affect the operation of interrupt factor flags, so when an interrupt factor occurs the interrupt factor flag is set to "1" even if the corresponding interrupt enable bit is set to "0". When initially reset, the interrupt enable register is set to "0" (interrupts are disabled). In cases when IDMA is started up by occurrence of an interrupt factor or when clearing standby mode (HALT or SLEEP mode) too, the corresponding interrupt enable bit must be set to "1". The interrupt controller outputs an interrupt request to the CPU when the following conditions are met: * An interrupt factor has occurred and the interrupt factor flag is set to "1". * The bit of the interrupt enable register for the interrupt factor that has occurred is set to "1" (interrupt enable). * The bit of the IDMA request register for the interrupt factor that has occurred is set to "0" (interrupt request). B-II If two or more interrupt factors occur simultaneously, the interrupt factor that has the highest priority is allowed to signal an interrupt request to the CPU. (See the following section.) When these conditions are met, the interrupt controller outputs an interrupt request signal to the CPU along with the setup content (interrupt level) of the interrupt priority register for the generated interrupt system and its vector number. These signals remain asserted until the interrupt factor flag is reset to "0" or the corresponding bit of the interrupt enable register is set to "0" (interrupts are disabled) or until some other interrupt factor of higher priority occurs. They are not cleared if the CPU simply accepts the interrupt request. S1C33L03 FUNCTION PART EPSON B-II-5-7 ITC II CORE BLOCK: ITC (Interrupt Controller) Interrupt Priority Register and Interrupt Levels The interrupt priority register is a 3-bit register provided for each interrupt system. It allows the interrupt levels of a given interrupt system to be set in the range of 0 to 7. The default priorities shown in Table 5.1 can be modified according to system requirements by this setting. The value set in this register is used by the interrupt controller and the CPU as described below. Roles of the interrupt priority register in the interrupt controller If two or more interrupt factors that have been enabled by the interrupt enable register occur simultaneously, the interrupt factor in the interrupt system whose interrupt priority register contains the greatest value is allowed by the interrupt controller to signal an interrupt request to the CPU. If an interrupt factor occurs in two or more interrupt systems having the same value, the interrupt priority is resolved according to the default priorities in Table 5.1. Interrupt factors in the same interrupt system also have their priorities resolved according to the order in Table 5.1. Other interrupt factors are kept pending until all interrupts of higher priority are accepted by the CPU. When outputting an interrupt request signal to the CPU, the interrupt controller outputs the content of the interrupt priority register to the CPU along with it. If another interrupt factor of higher priority occurs during outputting an interrupt request signal, the interrupt controller changes the vector number and interrupt level to those of the new interrupt factor before they are output to the CPU. The first interrupt request is left pending. Roles of the interrupt priority register in CPU processing The CPU compares the content of the interrupt priority register received from the interrupt controller with the interrupt level that is set in the IL of the PSR to determine whether or not to accept the interrupt request. IE bit = "1" & IL < interrupt priority register: the interrupt request is accepted IE bit = "1" & IL > interrupt priority register: the interrupt request is rejected Before interrupts can be controlled by an interrupt level, the interrupt disabling level must be written to the IL. For example, if the value written to the IL is 3, only the interrupts whose interrupt levels written in the interrupt priority register are 4 or more will be accepted. When an interrupt is accepted, the interrupt level that is set in its interrupt priority register is written to the IL. As a result, the interrupt requests below that interrupt level can no longer be accepted. If the interrupt priority register for an interrupt is set to "0", the interrupt is disabled. However, invoking IDMA by means of an interrupt factor works fine. Notes: * As the S1C33000 Core CPU function, the IL allows interrupt levels to be set in the range of 0 to 15. However, since the interrupt priority register in the C33 Core Block consists of three bits, interrupt levels in each interrupt system can only be set for up to 8. * Multiple interrupts can also be handled by rewriting the interrupt level to the IL in the interrupt processing routine. However, if the interrupt level of the IL is set below the current level and the IE is set to enable interrupts before resetting the interrupt factor flag after an interrupt has occurred, the same interrupt may occur again. B-II-5-8 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: ITC (Interrupt Controller) A-1 IDMA Invocation The interrupt factors for which IDMA channel numbers are written in Table 5.1 have the function to invoke the intelligent DMA (IDMA). IDMA request register The IDMA request register is used to specify the interrupt factor that invoke an IDMA transfer. If an IDMA request bit is set to "1", the IDMA request will be generated when the corresponding interrupt factor occurs. When the IDMA request bit is set to "0", the corresponding interrupt factor does not invoke IDMA and a normal interrupt processing will be performed. The IDMA request register is set to "0" by an initial reset. The method by which this register is set can be selected from the software application using either of the two methods described below. This selection is accomplished using IDMAONLY (D1) / Flag set/reset method select register (0x4029F). * Set-only method (default) This method is selected (IDMAONLY = "1") when initially reset. With this method, an IDMA request bit is set by writing "1". Although multiple IDMA request bits are located in the IDMA request register, the IDMA request bits for which "0" has been written can be neither set nor reset. Therefore, this method ensures that only a specific IDMA request bit is set. However, when using read-modify-write instructions (e.g., bset, bclr, or bnot), note that an IDMA request bit that has been set to "1" is not reset by writing. * Read/write method This method is selected by writing "0" to IDMAONLY. When this method is used, IDMA request bits can be read and written as for other registers. Therefore, the IDMA request bit is reset by writing "0" and set by writing "1". In this case, all IDMA request bits for which "0" has been written are reset. Even in a read-modify-write operation, an IDMA request bit can be reset by the hardware between the read and the write, so be careful when using this method. IDMA enable register To perform IDMA transfer using an interrupt factor, the corresponding bit of the IDMA enable register must be set to "1". If this bit is set to "0", the interrupt factor cannot invoke the IDMA channel. The IDMA enable register is set to "0" by an initial reset. The IDMA enable register allows selection of a set method (set-only method or Read/write method) similar to the IDMA request register. This selection is accomplished using DENONLY (D2) / Flag set/reset method select register (0x4029F). See the above explanation for the set method. Invoking IDMA Before IDMA can be invoked by the occurrence of an interrupt factor, the corresponding bits of the IDMA request and IDMA enable registers must be set to "1". Then when an interrupt factor occurs, the interrupt request to the CPU is made pending and the corresponding IDMA channel is invoked. The DMA transfer is performed according to the control information of that IDMA channel. The interrupt level set by the interrupt priority register of the ITC does not affect the IDMA invocation. The IDMA request can be accepted even if the interrupt level of the CPU is higher than the set value of the interrupt priority register. However, when generating the interrupt request to the CPU after the IDMA transfer is completed, the interrupt is controlled using the interrupt level set by the interrupt priority register. An IDMA invocation request is accepted even when the interrupt enable register and PSR of the CPU is set to disable interrupts. It is also necessary that the control information for the IDMA channel has been set. S1C33L03 FUNCTION PART EPSON B-II-5-9 B-II ITC II CORE BLOCK: ITC (Interrupt Controller) Interrupt after IDMA transfer To generate an interrupt after completion of IDMA transfer: The interrupt request that has been kept pending can be generated after completion of the DMA transfer. In this case, the interrupt must be enabled by the IDMA control information (DINTEM = "1") in adition to the interrupt controller and the PSR register settings. However, if the transfer counter set for the selected IDMA channel does not reach the terminal count of 0 after the number of transfers set have been performed, the interrupt factor flag is reset and no interrupt request is generated. The transfer counter is decremented by 1 for each transfer performed. If the transfer counter is decremented to 0 when DINTEN is set to "1", the interrupt factor flag is not reset and the IDMA request bit is cleared to "0". An interrupt request is generated if other interrupt conditions are met. The IDMA request bit must be set up again in order for IDMA to be invoked when an interrupt factor occurs next time as well. To ensure that no unwanted IDMA request occurs, this setup must be performed after resetting the interrupt factor flag. Figure 5.2 shows the hardware sequence when DINTEN is set to "1". IDMA trigger (interrupt factor flag) 3 Transfer counter 2 1 0 Data transfer Reset A signal (reset interrupt factor flag) Reset B signal (reset IDMA request bit) IDMA request bit Interrupt request Figure 5.2 Sequence when DINTEN = "1" To disable an interrupt after completion of IDMA transfer: If an interrupt has been disabled in the IDMA control information (DINTEN = "0"), the interrupt is not generated since the interrupt factor flag is reset when the transfer counter becomes 0. In this case, the IDMA request bit remains set to "1" without being cleared. However, the IDMA enable bit is cleared, so the following IDMA request by the same interrupt factor will be disabled. Figure 5.3 shows the hardware sequence when DINTEN is set to "0". IDMA trigger (interrupt factor flag) 3 Transfer counter 2 1 0 Data transfer Reset A signal (reset interrupt factor flag) Reset B signal (reset IDMA request bit) Reset C signal (reset IDMA enable bit) IDMA request bit L "1" IDMA enable bit Figure 5.3 Sequence when DINTEN = "0" For details on IDMA, refer to "IDMA (Intelligent DMA)". B-II-5-10 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: ITC (Interrupt Controller) A-1 HSDMA Invocation Some interrupt factors can invoke high-speed DMAs (HSDMA). HSDMA trigger set-up register The DMA block contains four channel of HSDMA circuit. Each channel allows selection of an interrupt factor as the trigger. The HSDMA trigger set-up registers are used for this selection. HSDMA Ch.0: HSD0S[3:0] (D[3:0])/HSDMA Ch.0/1 trigger set-up register (0x40298) HSDMA Ch.1: HSD1S[3:0] (D[7:4])/HSDMA Ch.0/1 trigger set-up register (0x40298) HSDMA Ch.2: HSD2S[3:0] (D[3:0])/HSDMA Ch.2/3 trigger set-up register (0x40299) HSDMA Ch.3: HSD3S[3:0] (D[7:4])/HSDMA Ch.2/3 trigger set-up register (0x40299) Table 5.2 shows the setting value and the corresponding trigger factor. Table 5.2 HSDMA Trigger Factor Value Ch.0 trigger factor Ch.1 trigger factor Ch.2 trigger factor Ch.3 trigger factor 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 Software trigger K50 port input (falling edge) K50 port input (rising edge) Port 0 input Port 4 input 8-bit timer 0 underflow 16-bit timer 0 compare B 16-bit timer 0 compare A 16-bit timer 4 compare B 16-bit timer 4 compare A Serial I/F Ch.0 Rx buffer full Serial I/F Ch.0 Tx buffer empty A/D conversion completion Software trigger K51 port input (falling edge) K51 port input (rising edge) Port 1 input Port 5 input 8-bit timer 1 underflow 16-bit timer 1 compare B 16-bit timer 1 compare A 16-bit timer 5 compare B 16-bit timer 5 compare A Serial I/F Ch.1 Rx buffer full Serial I/F Ch.1 Tx buffer empty A/D conversion completion Software trigger K53 port input (falling edge) K53 port input (rising edge) Port 2 input Port 6 input 8-bit timer 2 underflow 16-bit timer 2 compare B 16-bit timer 2 compare A 16-bit timer 4 compare B 16-bit timer 4 compare A Serial I/F Ch.0 Rx buffer full Serial I/F Ch.0 Tx buffer empty A/D conversion completion Software trigger K54 port input (falling edge) K54 port input (rising edge) Port 3 input Port 7 input 8-bit timer 3 underflow 16-bit timer 3 compare B 16-bit timer 3 compare A 16-bit timer 5 compare B 16-bit timer 5 compare A Serial I/F Ch.1 Rx buffer full Serial I/F Ch.1 Tx buffer empty A/D conversion completion Invoking HSDMA By selecting an interrupt factor with the HSDMA trigger set-up register, the HSDMA channel is invoked when the selected interrupt factor occurs. The interrupt control bits (interrupt factor flag, interrupt enable register, IDMA request register, interrupt priority register) do not affect this invocation. Since HSDMA does not reset the interrupt factor flag, an interrupt will occur when the DMA transfer is completed if the interrupt is enabled by ITC. Before HSDMA can be invoked by the occurrence of an interrupt factor, it is necessary that DMA be enabled on the HSDMA side by setting the control register for HSDMA transfer. For details about HSDMA, refer to "HSDMA (High-Speed DMA)". S1C33L03 FUNCTION PART EPSON B-II-5-11 B-II ITC II CORE BLOCK: ITC (Interrupt Controller) I/O Memory of Interrupt Controller Table 5.3 shows the control bits of the interrupt controller. Table 5.3 Control Bits of Interrupt Controller Register name Address Bit Port input 0/1 0040260 interrupt (B) priority register D7 D6 D5 D4 D3 D2 D1 D0 - PP1L2 PP1L1 PP1L0 - PP0L2 PP0L1 PP0L0 reserved Port input 1 interrupt level - 0 to 7 reserved Port input 0 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - PP3L2 PP3L1 PP3L0 - PP2L2 PP2L1 PP2L0 reserved Port input 3 interrupt level - 0 to 7 reserved Port input 2 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - PK1L2 PK1L1 PK1L0 - PK0L2 PK0L1 PK0L0 reserved Key input 1 interrupt level - 0 to 7 reserved Key input 0 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - PHSD1L2 PHSD1L1 PHSD1L0 - PHSD0L2 PHSD0L1 PHSD0L0 reserved High-speed DMA Ch.1 interrupt level - 0 to 7 reserved High-speed DMA Ch.0 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - PHSD3L2 PHSD3L1 PHSD3L0 - PHSD2L2 PHSD2L1 PHSD2L0 reserved High-speed DMA Ch.3 interrupt level - 0 to 7 reserved High-speed DMA Ch.2 interrupt level - 0 to 7 - PDM2 PDM1 PDM0 reserved IDMA interrupt level Port input 2/3 0040261 interrupt (B) priority register Key input 0040262 interrupt (B) priority register High-speed 0040263 DMA Ch.0/1 (B) interrupt priority register High-speed 0040264 DMA Ch.2/3 (B) interrupt priority register Name Function Setting - 0 when being read. R/W - X X X - X X X - 0 when being read. R/W - X X X - X X X - 0 when being read. R/W - X X X - X X X - 0 when being read. R/W - X X X - X X X - 0 when being read. R/W - 0 to 7 - X X X - 0 when being read. R/W - X X X - X X X - 0 when being read. R/W - X X X - X X X - 0 when being read. R/W D7-3 D2 D1 D0 16-bit timer 0/1 0040266 interrupt (B) priority register D7 D6 D5 D4 D3 D2 D1 D0 - P16T12 P16T11 P16T10 - P16T02 P16T01 P16T00 reserved 16-bit timer 1 interrupt level - 0 to 7 reserved 16-bit timer 0 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - P16T32 P16T31 P16T30 - P16T22 P16T21 P16T20 reserved 16-bit timer 3 interrupt level - 0 to 7 reserved 16-bit timer 2 interrupt level - 0 to 7 B-II-5-12 EPSON Remarks - X X X - X X X IDMA interrupt 0040265 priority register (B) 16-bit timer 2/3 0040267 interrupt (B) priority register Init. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W S1C33L03 FUNCTION PART II CORE BLOCK: ITC (Interrupt Controller) A-1 Register name Address Bit 16-bit timer 4/5 0040268 interrupt (B) priority register D7 D6 D5 D4 D3 D2 D1 D0 - P16T52 P16T51 P16T50 - P16T42 P16T41 P16T40 reserved 16-bit timer 5 interrupt level - 0 to 7 reserved 16-bit timer 4 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - PSI002 PSI001 PSI000 - P8TM2 P8TM1 P8TM0 reserved Serial interface Ch.0 interrupt level - 0 to 7 reserved 8-bit timer 0-3 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - PAD2 PAD1 PAD0 - PSI012 PSI011 PSI010 reserved A/D converter interrupt level - 0 to 7 reserved Serial interface Ch.1 interrupt level - 0 to 7 Clock timer 004026B D7-3 - interrupt (B) D2 PCTM2 priority register D1 PCTM1 D0 PCTM0 reserved Clock timer interrupt level Port input 4/5 004026C interrupt (B) priority register 8-bit timer, 0040269 serial I/F Ch.0 (B) interrupt priority register Serial I/F Ch.1, 004026A A/D interrupt (B) priority register Port input 6/7 004026D interrupt (B) priority register Name Function - X X X - X X X - 0 when being read. R/W - X X X - X X X - 0 when being read. R/W - 0 to 7 - X X X - Writing 1 not allowed. R/W - X X X - X X X - 0 when being read. R/W - X X X - X X X - 0 when being read. R/W - 0 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W R/W - 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W 0 0 - 0 0 - R/W R/W - 0 when being read. R/W R/W - 0 when being read. 0 0 - 0 0 - R/W R/W - 0 when being read. R/W R/W - 0 when being read. reserved Port input 5 interrupt level - 0 to 7 reserved Port input 4 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - PP7L2 PP7L1 PP7L0 - PP6L2 PP6L1 PP6L0 reserved Port input 7 interrupt level - 0 to 7 reserved Port input 6 interrupt level - 0 to 7 - EK1 EK0 EP3 EP2 EP1 EP0 reserved Key input 1 Key input 0 Port input 3 Port input 2 Port input 1 Port input 0 DMA interrupt 0040271 enable register (B) D7-5 D4 D3 D2 D1 D0 - EIDMA EHDM3 EHDM2 EHDM1 EHDM0 reserved IDMA High-speed DMA Ch.3 High-speed DMA Ch.2 High-speed DMA Ch.1 High-speed DMA Ch.0 16-bit timer 0/1 0040272 interrupt (B) enable register D7 D6 D5-4 D3 D2 D1-0 E16TC1 E16TU1 - E16TC0 E16TU0 - D7 D6 D5-4 D3 D2 D1-0 E16TC3 E16TU3 - E16TC2 E16TU2 - S1C33L03 FUNCTION PART - 1 Enabled 0 Disabled - 1 Enabled 0 Disabled 16-bit timer 1 comparison A 16-bit timer 1 comparison B reserved 16-bit timer 0 comparison A 16-bit timer 0 comparison B reserved 1 Enabled 0 Disabled 16-bit timer 3 comparison A 16-bit timer 3 comparison B reserved 16-bit timer 2 comparison A 16-bit timer 2 comparison B reserved 1 Enabled EPSON Remarks - 0 when being read. R/W - PP5L2 PP5L1 PP5L0 - PP4L2 PP4L1 PP4L0 D7-6 D5 D4 D3 D2 D1 D0 Init. R/W - X X X - X X X D7 D6 D5 D4 D3 D2 D1 D0 Key input, 0040270 port input 0-3 (B) interrupt enable register 16-bit timer 2/3 0040273 interrupt (B) enable register Setting - 1 Enabled 0 Disabled - 0 Disabled - 1 Enabled 0 Disabled - - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W B-II-5-13 B-II ITC II CORE BLOCK: ITC (Interrupt Controller) Register name Address Bit 16-bit timer 4/5 0040274 interrupt (B) enable register D7 D6 D5-4 D3 D2 D1-0 E16TC5 E16TU5 - E16TC4 E16TU4 - Name 16-bit timer 5 comparison A 16-bit timer 5 comparison B reserved 16-bit timer 4 comparison A 16-bit timer 4 comparison B reserved Function 8-bit timer 0040275 interrupt (B) enable register D7-4 D3 D2 D1 D0 - E8TU3 E8TU2 E8TU1 E8TU0 reserved 8-bit timer 3 underflow 8-bit timer 2 underflow 8-bit timer 1 underflow 8-bit timer 0 underflow Serial I/F 0040276 interrupt (B) enable register D7-6 D5 D4 D3 D2 D1 D0 - ESTX1 ESRX1 ESERR1 ESTX0 ESRX0 ESERR0 reserved SIF Ch.1 transmit buffer empty SIF Ch.1 receive buffer full SIF Ch.1 receive error SIF Ch.0 transmit buffer empty SIF Ch.0 receive buffer full SIF Ch.0 receive error Port input 4-7, 0040277 clock timer, (B) A/D interrupt enable register D7-6 D5 D4 D3 D2 D1 D0 - EP7 EP6 EP5 EP4 ECTM EADE reserved Port input 7 Port input 6 Port input 5 Port input 4 Clock timer A/D converter Key input, 0040280 port input 0-3 (B) interrupt factor flag register D7-6 D5 D4 D3 D2 D1 D0 - FK1 FK0 FP3 FP2 FP1 FP0 reserved Key input 1 Key input 0 Port input 3 Port input 2 Port input 1 Port input 0 DMA interrupt factor flag register 0040281 (B) D7-5 D4 D3 D2 D1 D0 - FIDMA FHDM3 FHDM2 FHDM1 FHDM0 reserved IDMA High-speed DMA Ch.3 High-speed DMA Ch.2 High-speed DMA Ch.1 High-speed DMA Ch.0 16-bit timer 0/1 0040282 interrupt factor (B) flag register D7 D6 D5-4 D3 D2 D1-0 F16TC1 F16TU1 - F16TC0 F16TU0 - D7 D6 D5-4 D3 D2 D1-0 Setting 1 Enabled 0 Disabled - 1 Enabled 0 Disabled - - 1 Enabled 0 Disabled - 1 Enabled 0 Disabled - 1 Enabled 0 Disabled - 1 Factor is generated 0 No factor is generated - 1 Factor is generated 0 No factor is generated 16-bit timer 1 comparison A 16-bit timer 1 comparison B reserved 16-bit timer 0 comparison A 16-bit timer 0 comparison B reserved 1 Factor is generated 0 No factor is generated F16TC3 F16TU3 - F16TC2 F16TU2 - 16-bit timer 3 comparison A 16-bit timer 3 comparison B reserved 16-bit timer 2 comparison A 16-bit timer 2 comparison B reserved 1 Factor is generated D7 D6 D5-4 D3 D2 D1-0 F16TC5 F16TU5 - F16TC4 F16TU4 - 16-bit timer 5 comparison A 16-bit timer 5 comparison B reserved 16-bit timer 4 comparison A 16-bit timer 4 comparison B reserved 1 Factor is generated 8-bit timer 0040285 interrupt factor (B) flag register D7-4 D3 D2 D1 D0 - F8TU3 F8TU2 F8TU1 F8TU0 reserved 8-bit timer 3 underflow 8-bit timer 2 underflow 8-bit timer 1 underflow 8-bit timer 0 underflow Serial I/F 0040286 interrupt factor (B) flag register D7-6 D5 D4 D3 D2 D1 D0 - FSTX1 FSRX1 FSERR1 FSTX0 FSRX0 FSERR0 reserved SIF Ch.1 transmit buffer empty SIF Ch.1 receive buffer full SIF Ch.1 receive error SIF Ch.0 transmit buffer empty SIF Ch.0 receive buffer full SIF Ch.0 receive error 16-bit timer 2/3 0040283 interrupt factor (B) flag register 16-bit timer 4/5 0040284 interrupt factor (B) flag register B-II-5-14 EPSON - 1 Factor is generated 0 No factor is generated - 0 No factor is generated - 1 Factor is generated 0 No factor is generated - 0 No factor is generated - 1 Factor is generated 0 No factor is generated - - 1 Factor is generated 0 No factor is generated - 1 Factor is generated 0 No factor is generated Init. R/W Remarks 0 0 - 0 0 - R/W R/W - 0 when being read. R/W R/W - 0 when being read. - 0 0 0 0 - 0 when being read. R/W R/W R/W R/W - 0 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W R/W - 0 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W R/W - X X X X X X - 0 when being read. R/W R/W R/W R/W R/W R/W - X X X X X - 0 when being read. R/W R/W R/W R/W R/W X X - X X - R/W R/W - 0 when being read. R/W R/W - 0 when being read. X X - X X - R/W R/W - 0 when being read. R/W R/W - 0 when being read. X X - X X - R/W R/W - 0 when being read. R/W R/W - 0 when being read. - X X X X - 0 when being read. R/W R/W R/W R/W - X X X X X X - 0 when being read. R/W R/W R/W R/W R/W R/W S1C33L03 FUNCTION PART II CORE BLOCK: ITC (Interrupt Controller) A-1 Register name Address Bit Port input 4-7, 0040287 clock timer, A/D (B) interrupt factor flag register D7-6 D5 D4 D3 D2 D1 D0 Port input 0-3, high-speed DMA Ch. 0/1, 16-bit timer 0 IDMA request register Name Function - FP7 FP6 FP5 FP4 FCTM FADE reserved Port input 7 Port input 6 Port input 5 Port input 4 Clock timer A/D converter Setting - 1 Factor is generated 0 No factor is generated Init. R/W Remarks - X X X X X X - 0 when being read. R/W R/W R/W R/W R/W R/W 0040290 (B) D7 D6 D5 D4 D3 D2 D1 D0 R16TC0 R16TU0 RHDM1 RHDM0 RP3 RP2 RP1 RP0 16-bit timer 0 comparison A 16-bit timer 0 comparison B High-speed DMA Ch.1 High-speed DMA Ch.0 Port input 3 Port input 2 Port input 1 Port input 0 1 IDMA request 0 Interrupt request 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 16-bit timer 1-4 0040291 IDMA request (B) register D7 D6 D5 D4 D3 D2 D1 D0 R16TC4 R16TU4 R16TC3 R16TU3 R16TC2 R16TU2 R16TC1 R16TU1 16-bit timer 4 comparison A 16-bit timer 4 comparison B 16-bit timer 3 comparison A 16-bit timer 3 comparison B 16-bit timer 2 comparison A 16-bit timer 2 comparison B 16-bit timer 1 comparison A 16-bit timer 1 comparison B 1 IDMA request 0 Interrupt request 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA request register 0040292 (B) D7 D6 D5 D4 D3 D2 D1 D0 RSTX0 RSRX0 R8TU3 R8TU2 R8TU1 R8TU0 R16TC5 R16TU5 SIF Ch.0 transmit buffer empty SIF Ch.0 receive buffer full 8-bit timer 3 underflow 8-bit timer 2 underflow 8-bit timer 1 underflow 8-bit timer 0 underflow 16-bit timer 5 comparison A 16-bit timer 5 comparison B 1 IDMA request 0 Interrupt request 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Serial I/F Ch.1, A/D, port input 4-7 IDMA request register 0040293 (B) D7 D6 D5 D4 D3 D2 D1 D0 RP7 RP6 RP5 RP4 - RADE RSTX1 RSRX1 Port input 7 Port input 6 Port input 5 Port input 4 reserved A/D converter SIF Ch.1 transmit buffer empty SIF Ch.1 receive buffer full 1 IDMA request 0 Interrupt request 1 IDMA request 0 Interrupt request 0 0 0 0 - 0 0 0 R/W R/W R/W R/W - 0 when being read. R/W R/W R/W 0040294 (B) D7 D6 D5 D4 D3 D2 D1 D0 DE16TC0 DE16TU0 DEHDM1 DEHDM0 DEP3 DEP2 DEP1 DEP0 16-bit timer 0 comparison A 16-bit timer 0 comparison B High-speed DMA Ch.1 High-speed DMA Ch.0 Port input 3 Port input 2 Port input 1 Port input 0 1 IDMA enabled 0 IDMA disabled 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 16-bit timer 1-4 0040295 IDMA enable (B) register D7 D6 D5 D4 D3 D2 D1 D0 DE16TC4 DE16TU4 DE16TC3 DE16TU3 DE16TC2 DE16TU2 DE16TC1 DE16TU1 16-bit timer 4 comparison A 16-bit timer 4 comparison B 16-bit timer 3 comparison A 16-bit timer 3 comparison B 16-bit timer 2 comparison A 16-bit timer 2 comparison B 16-bit timer 1 comparison A 16-bit timer 1 comparison B 1 IDMA enabled 0 IDMA disabled 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA enable register 0040296 (B) D7 D6 D5 D4 D3 D2 D1 D0 DESTX0 DESRX0 DE8TU3 DE8TU2 DE8TU1 DE8TU0 DE16TC5 DE16TU5 SIF Ch.0 transmit buffer empty SIF Ch.0 receive buffer full 8-bit timer 3 underflow 8-bit timer 2 underflow 8-bit timer 1 underflow 8-bit timer 0 underflow 16-bit timer 5 comparison A 16-bit timer 5 comparison B 1 IDMA enabled 0 IDMA disabled 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Serial I/F Ch.1, A/D, port input 4-7 IDMA enable register 0040297 (B) D7 D6 D5 D4 D3 D2 D1 D0 DEP7 DEP6 DEP5 DEP4 - DEADE DESTX1 DESRX1 Port input 7 Port input 6 Port input 5 Port input 4 reserved A/D converter SIF Ch.1 transmit buffer empty SIF Ch.1 receive buffer full 1 IDMA enabled 0 IDMA disabled 0 0 0 0 - 0 0 0 R/W R/W R/W R/W - 0 when being read. R/W R/W R/W Port input 0-3, high-speed DMA Ch. 0/1, 16-bit timer 0 IDMA enable register S1C33L03 FUNCTION PART EPSON - - 1 IDMA enabled 0 IDMA disabled B-II ITC B-II-5-15 II CORE BLOCK: ITC (Interrupt Controller) Register name Address Bit Name High-speed DMA Ch.0/1 trigger set-up register D7 D6 D5 D4 HSD1S3 HSD1S2 HSD1S1 HSD1S0 High-speed DMA Ch.1 trigger set-up D3 D2 D1 D0 HSD0S3 HSD0S2 HSD0S1 HSD0S0 High-speed DMA Ch.0 trigger set-up D7 D6 D5 D4 HSD3S3 HSD3S2 HSD3S1 HSD3S0 High-speed DMA Ch.3 trigger set-up D3 D2 D1 D0 HSD2S3 HSD2S2 HSD2S1 HSD2S0 High-speed DMA Ch.2 trigger set-up High-speed DMA Ch.2/3 trigger set-up register Flag set/reset method select register B-II-5-16 0040298 (B) 0040299 (B) 004029F (B) Function Setting Software trigger K51 input (falling edge) K51 input (rising edge) Port 1 input Port 5 input 8-bit timer Ch.1 underflow 16-bit timer Ch.1 compare B 16-bit timer Ch.1 compare A 16-bit timer Ch.5 compare B 16-bit timer Ch.5 compare A SI/F Ch.1 Rx buffer full SI/F Ch.1 Tx buffer empty A/D conversion completion Software trigger K50 input (falling edge) K50 input (rising edge) Port 0 input Port 4 input 8-bit timer Ch.0 underflow 16-bit timer Ch.0 compare B 16-bit timer Ch.0 compare A 16-bit timer Ch.4 compare B 16-bit timer Ch.4 compare A SI/F Ch.0 Rx buffer full SI/F Ch.0 Tx buffer empty A/D conversion completion 0 0 0 0 R/W 0 0 0 0 R/W 0 1 2 3 4 5 6 7 8 9 A B C 0 1 2 3 4 5 6 7 8 9 A B C Software trigger K54 input (falling edge) K54 input (rising edge) Port 3 input Port 7 input 8-bit timer Ch.3 underflow 16-bit timer Ch.3 compare B 16-bit timer Ch.3 compare A 16-bit timer Ch.5 compare B 16-bit timer Ch.5 compare A SI/F Ch.1 Rx buffer full SI/F Ch.1 Tx buffer empty A/D conversion completion Software trigger K53 input (falling edge) K53 input (rising edge) Port 2 input Port 6 input 8-bit timer Ch.2 underflow 16-bit timer Ch.2 compare B 16-bit timer Ch.2 compare A 16-bit timer Ch.4 compare B 16-bit timer Ch.4 compare A SI/F Ch.0 Rx buffer full SI/F Ch.0 Tx buffer empty A/D conversion completion 0 0 0 0 R/W 0 0 0 0 R/W - 1 - R/W 1 R/W 1 R/W D7-3 - reserved - 0 RD/WR D2 DENONLY IDMA enable register set method 1 Set only selection D1 IDMAONLY IDMA request register set method 1 Set only 0 RD/WR selection D0 RSTONLY Interrupt factor flag reset method 1 Reset only 0 RD/WR selection EPSON Init. R/W 0 1 2 3 4 5 6 7 8 9 A B C 0 1 2 3 4 5 6 7 8 9 A B C Remarks S1C33L03 FUNCTION PART II CORE BLOCK: ITC (Interrupt Controller) A-1 Register name Address Bit Interrupt factor 00402C5 FP function switching register D7 D6 T8CH5S0 SIO3TS0 8-bit timer 5 underflow SIO Ch.3 transmit buffer empty D5 D4 T8CH4S0 SIO3RS0 8-bit timer 4 underflow SIO Ch.3 receive buffer full D3 SIO2TS0 SIO Ch.2 transmit buffer empty D2 SIO3ES0 SIO Ch.3 receive error D1 SIO2RS0 SIO Ch.2 receive buffer full D0 SIO2ES0 SIO Ch.2 receive error D7 T8CH5S1 8-bit timer 5 underflow D6 T8CH4S1 8-bit timer 4 underflow D5 SIO3ES1 SIO Ch.3 receive error D4 SIO2ES1 SIO Ch.2 receive error D3 SIO3TS1 SIO Ch.3 transmit buffer empty D2 SIO3RS1 SIO Ch.3 receive buffer full D1 SIO2TS1 SIO Ch.2 transmit buffer empty D0 SIO2RS1 SIO Ch.2 receive buffer full TTBR write 004812D protect register (B) D7 D6 D5 D4 D3 D2 D1 D0 TBRP7 TBRP6 TBRP5 TBRP4 TBRP3 TBRP2 TBRP1 TBRP0 TTBR register write protect TTBR loworder register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TTBR15 TTBR14 TTBR13 TTBR12 TTBR11 TTBR10 TTBR09 TTBR08 TTBR07 TTBR06 TTBR05 TTBR04 TTBR03 TTBR02 TTBR01 TTBR00 Trap table base address [15:10] Trap table base address [9:0] Fixed at 0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TTBR33 TTBR32 TTBR31 TTBR30 TTBR2B TTBR2A TTBR29 TTBR28 TTBR27 TTBR26 TTBR25 TTBR24 TTBR23 TTBR22 TTBR21 TTBR20 Trap table base address [31:28] Fixed at 0 Trap table base address [27:16] 0x0C0 Interrupt factor 00402CB TM16 function switching register TTBR highorder register 0048134 (HW) 0048136 (HW) S1C33L03 FUNCTION PART Name Function EPSON Setting 1 T8 Ch.5 UF 1 SIO Ch.3 TXD Emp. 1 T8 Ch.4 UF 1 SIO Ch.3 RXD Full 1 SIO Ch.2 TXD Emp. 1 SIO Ch.3 RXD Err. 1 SIO Ch.2 RXD Full 1 SIO Ch.2 RXD Err. Init. R/W Remarks 0 FP7 0 FP6 0 0 R/W R/W 0 FP5 0 FP4 0 0 R/W R/W 0 FP3 0 R/W 0 FP2 0 R/W 0 FP1 0 R/W 0 FP0 0 R/W 1 T8 Ch.5 UF 0 TM16 Ch.2 comp.A 1 T8 Ch.4 UF 0 TM16 Ch.2 comp.B 1 SIO Ch.3 0 TM16 Ch.3 RXD Err. comp.A 1 SIO Ch.2 0 TM16 Ch.3 RXD Err. comp.B 1 SIO Ch.3 0 TM16 Ch.4 TXD Emp. comp.A 1 SIO Ch.3 0 TM16 Ch.4 RXD Full comp.B 1 SIO Ch.2 0 TM16 Ch.5 TXD Emp. comp.A 1 SIO Ch.2 0 TM16 Ch.5 RXD Full comp.B 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Writing 01011001 (0x59) removes the TTBR (0x48134) write protection. Writing other data sets the write protection. 0 0 0 0 0 0 0 0 W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R 0 when being read. Writing 1 not allowed. 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 R 0 when being read. Writing 1 not allowed. B-II Undefined in read. R/W B-II-5-17 ITC II CORE BLOCK: ITC (Interrupt Controller) Register name Address Bit Areas 10-9 0048126 set-up register (HW) DF DE DD DC - A10IR2 A10IR1 A10IR0 Name reserved Area 10 internal ROM size selection Function DB DA D9 - A10BW1 A10BW0 reserved Areas 10-9 burst ROM burst read cycle wait control D8 D7 D6 D5 D4 A10DRA A9DRA A10SZ A10DF1 A10DF0 Area 10 burst ROM selection Area 9 burst ROM selection Areas 10-9 device size selection Areas 10-9 output disable delay time D3 D2 D1 D0 - A10WT2 A10WT1 A10WT0 reserved Areas 10-9 wait control Setting - A10IR[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 ROM size 2MB 1MB 512KB 256KB 128KB 64KB 32KB 16KB - A10BW[1:0] Wait cycles 1 1 3 1 0 2 0 1 1 0 0 0 1 Used 0 Not used 1 Used 0 Not used 1 8 bits 0 16 bits A10DF[1:0] Number of cycles 1 1 3.5 1 0 2.5 0 1 1.5 0 0 0.5 - A10WT[2:0] Wait cycles 1 1 1 7 1 1 0 6 1 0 1 5 1 0 0 4 0 1 1 3 0 1 0 2 0 0 1 1 0 0 0 0 Init. R/W Remarks - 1 1 1 - 0 when being read. R/W - 0 0 - 0 when being read. R/W 0 0 0 1 1 R/W R/W R/W R/W - 1 1 1 - 0 when being read. R/W The following collectively explains the basic functions of each control register/bit. For details about individual interrupt systems and the contents classified by an interrupt factor, refer to the descriptions of the peripheral circuits in this manual. Pxxx2-Pxxx0: Interrupt priority register Set the priority levels of each interrupt system in the range of 0 to 7. If this register is set below the IL value of the PSR, no interrupt is generated. The value of this register when initially reset is indeterminate. Exxx: Interrupt enable register Enable or disable interrupt generation to the CPU. Write "1": Interrupt enabled Write "0": Interrupt disabled Read: Valid Interrupts are enabled when the corresponding bits of this register are set to "1" and are disabled when the bits are set to "0". For the interrupt factors used to request IDMA invocation or clear the standby mode, the corresponding interrupt enable register bit must be set for interrupt enable. When initially reset, this register is set to "0" (interrupt disabled). B-II-5-18 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: ITC (Interrupt Controller) A-1 Fxxx: Interrupt factor flag Indicate the status of interrupt factors generated. When read Read "1": Interrupt factor generated Read "0": No interrupt factor generated When written using the reset-only method (default) Write "1": Factor flag is reset Write "0": Invalid When written using the read/write method Write "1": Factor flag is set Write "0": Factor flag is reset The interrupt factor flag is set to "1" when an interrupt factor occurs in each peripheral circuit. If the following conditions are met at this time, an interrupt is generated to the CPU: 1. The corresponding bit of the interrupt enable register is set to "1". 2. No other interrupt request of higher priority has occurred. 3. The IE bit of the PSR is set to "1" (interrupt enabled). 4. The corresponding interrupt priority register is set to a level higher than the CPU's interrupt level (IL). When using an interrupt factor to request IDMA, note that even when the above conditions are met, no interrupt request to the CPU is generated for the interrupt factor that has occurred. If interrupts are enabled at the setting of IDMA, an interrupt is generated under the above conditions after the data transfer by IDMA is completed. The interrupt factor flag is always set to "1" when an interrupt factor occurs no matter how the interrupt enable and interrupt priority registers are set. In order for the next interrupt to be accepted after interrupt generation, the interrupt factor flag must be reset and the PSR must be set up again (by setting the IL below the level indicated by the interrupt priority register and setting the IE bit to "1" or executing the reti instruction). The interrupt factor flag can only be reset by a write instruction in the software application. If the PSR is again set up to accept interrupts (or the reti instruction is executed) without resetting the interrupt factor flag, the same interrupt may occur again. Note also that the value to be written to reset the flag is "1" when using the reset-only method (RSTONLY = "1") and "0" when using the read/write method (RSTONLY = "0"). Be careful not to confuse these two conditions. The interrupt factor flag becomes indeterminate when initially reset, so be sure to reset the flag in the software application. Rxxx: IDMA request register Specify whether or not to invoke IDMA when an interrupt factor occurs. When using the set-only method (default) Write "1": IDMA request Write "0": Not changed Read: Valid When using the read/write method Write "1": IDMA request Write "0": Interrupt request Read: Valid If a bit of this register is set to "1", IDMA is invoked when the corresponding interrupt factor occurs and the programmed data transfer is performed. If the register bit is set to "0", regular interrupt processing is performed, without ever invoking IDMA. For details about IDMA, refer to "IDMA (Intelligent DMA)". If interrupts are enabled on the IDMA side and the transfer counter reaches the terminal count of 0 after completion of DMA transfer, the IDMA request register is reset to "0" and an interrupt request for the interrupt factor that enabled IDMA invoking is generated. After an initial reset, this register is set to "0" (Interrupt is requested). S1C33L03 FUNCTION PART EPSON B-II-5-19 B-II ITC II CORE BLOCK: ITC (Interrupt Controller) DExxx: IDMA enable register Enable or disable the IDMA request. When using the set-only method (default) Write "1": IDMA enabled Write "0": Not changed Read: Valid When using the read/write method Write "1": IDMA enabled Write "0": IDMA disabled Read: Valid If a bit of this register is set to "1", the IDMA request by the interrupt factor is enabled. If the register bit is set to "0", the IDMA request is disabled. After an initial reset, this register is set to "0" (IDMA is disabled). RSTONLY: Interrupt factor flag reset method selection (D0) / Flag set/reset method select register (0x4029F) Select the method for resetting the interrupt factor flag. Write "1": Reset-only method Write "0": Read/write method Read: Valid With the reset-only method, the interrupt factor flag is reset by writing "1". The interrupt factor flags for which "0" has been written can neither be set nor reset. Therefore, this method ensures that only a specific factor flag is reset. However, when using read-modify-write instructions (e.g., bset, bclr, or bnot), note that an interrupt factor flag that has been set to "1" is reset by writing. This method cannot be used to set any interrupt factor flag in the software application. The read/write method is selected by writing "0" to RSTONLY. When this method is selected, interrupt factor flags can be read and written as for other registers. Therefore, the flag is reset by writing "0" and set by writing "1". In this case all factor flags for which "0" has been written are reset. Even in a read-modify-write operation, an interrupt factor can occur between read and write instructions, so be careful when using this method. After an initial reset, RSTONLY is set to "1" (reset-only method). IDMAONLY: IDMA request register set method selection (D1) / Flag set/reset method select register (0x4029F) Select the method for setting the IDMA request registers. Write "1": Set-only method Write "0": Read/write method Read: Valid With the set-only method, IDMA request bits are set by writing "1". The IDMA request bits for which "0" has been written can neither be set nor reset. Therefore, this method ensures that only a specific IDMA request bit is set. However, when using read-modify-write instructions (e.g., bset, bclr, or bnot), note that an IDMA request bit that has been set to "1" is not reset by writing. The read/write method is selected by writing "0" to IDMAONLY. When this method is selected, IDMA request bits can be read and written as for other registers. Therefore, the IDMA request bit is reset by writing "0" and set by writing "1". In this case all IDMA request bits for which "0" has been written are reset. Even in a read-modifywrite operation, an IDMA request bit can be reset by the hardware between the read and the write, so be careful when using this method. After an initial reset, IDMAONLY is set to "1" (set-only method). B-II-5-20 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: ITC (Interrupt Controller) A-1 DENONLY: IDMA enable register set method selection (D2) / Flag set/reset method select register (0x4029F) Select the method for setting the IDMA enable registers. Write "1": Set-only method Write "0": Read/write method Read: Valid With the set-only method, IDMA enable bits are set by writing "1". The IDMA enable bits for which "0" has been written can neither be set nor reset. Therefore, this method ensures that only a specific IDMA enable bit is set. However, when using read-modify-write instructions (e.g., bset, bclr, or bnot), note that an IDMA enable bit that has been set to "1" is not reset by writing. The read/write method is selected by writing "0" to DENONLY. When this method is selected, IDMA enable bits can be read and written as for other registers. Therefore, the IDMA enable bit is reset by writing "0" and set by writing "1". In this case all IDMA enable bits for which "0" has been written are reset. Even in a read-modify-write operation, an interrupt enable bit can be reset by the hardware between the read and the write, so be careful when using this method. After an initial reset, DENONLY is set to "1" (set-only method). B-II SIO2ES0: SIO Ch.2 receive error/FP0 interrupt factor switching (D0) / Interrupt factor FP function switching register (0x402C5) Switches the interrupt factor. Write "1": SIO Ch.2 receive error Write "0": FP0 input Read: Valid ITC Set to "1" to use the SIO Ch.2 receive error interrupt. Set to "0" to use the FP0 input interrupt. At power-on, this bit is set to "0". SIO2RS0: SIO Ch.2 receive-buffer full/FP1 interrupt factor switching (D1) / Interrupt factor FP function switching register (0x402C5) Switches the interrupt factor. Write "1": SIO Ch.2 receive-buffer full Write "0": FP1 input Read: Valid Set to "1" to use the SIO Ch.2 receive-buffer full interrupt. Set to "0" to use the FP1 input interrupt. At power-on, this bit is set to "0". SIO3ES0: SIO Ch.3 receive error/FP2 interrupt factor switching (D2) / Interrupt factor FP function switching register (0x402C5) Switches the interrupt factor. Write "1": SIO Ch.3 receive error Write "0": FP2 input Read: Valid Set to "1" to use the SIO Ch.3 receive error interrupt. Set to "0" to use the FP2 input interrupt. At power-on, this bit is set to "0". S1C33L03 FUNCTION PART EPSON B-II-5-21 II CORE BLOCK: ITC (Interrupt Controller) SIO2TS0: SIO Ch.2 transmit-buffer empty/FP3 interrupt factor switching (D3) / Interrupt factor FP function switching register (0x402C5) Switches the interrupt factor. Write "1": SIO Ch.2 transmit-buffer empty Write "0": FP3 input Read: Valid Set to "1" to use the SIO Ch.2 transmit-buffer empty interrupt. Set to "0" to use the FP3 input interrupt. At power-on, this bit is set to "0". SIO3RS0: SIO Ch.3 receive-buffer full/FP4 interrupt factor switching (D4) / Interrupt factor FP function switching register (0x402C5) Switches the interrupt factor. Write "1": SIO Ch.3 receive-buffer full Write "0": FP4 input Read: Valid Set to "1" to use the SIO Ch.3 receive-buffer full interrupt. Set to "0" to use the FP4 input interrupt. At power-on, this bit is set to "0". T8CH4S0: 8-bit timer 4 underflow/FP5 interrupt factor switching (D5) / Interrupt factor FP function switching register (0x402C5) Switches the interrupt factor. Write "1": 8-bit timer 4 underflow Write "0": FP5 input Read: Valid Set to "1" to use the 8-bit timer 4 underflow interrupt. Set to "0" to use the FP5 input interrupt. At power-on, this bit is set to "0". SIO3TS0: SIO Ch.3 transmit-buffer empty/FP6 interrupt factor switching (D6) / Interrupt factor FP function switching register (0x402C5) Switches the interrupt factor. Write "1": SIO Ch.3 transmit-buffer empty Write "0": FP6 input Read: Valid Set to "1" to use the SIO Ch.3 transmit-buffer empty interrupt. Set to "0" to use the FP6 input interrupt. At power-on, this bit is set to "0". T8CH5S0: 8-bit timer 5 underflow/FP7 interrupt factor switching (D7) / Interrupt factor FP function switching register (0x402C5) Switches the interrupt factor. Write "1": 8-bit timer 5 underflow Write "0": FP7 input Read: Valid Set to "1" to use the 8-bit timer 5 underflow interrupt. Set to "0" to use the FP7 input interrupt. At power-on, this bit is set to "0". B-II-5-22 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: ITC (Interrupt Controller) A-1 SIO2RS1: SIO Ch.2 receive-buffer full/TM16 Ch.5 compare B interrupt factor switching (D0) / Interrupt factor TM16 function switching register (0x402CB) Switches the interrupt factor. Write "1": SIO Ch.2 receive-buffer full Write "0": TM16 Ch.5 compare B Read: Valid Set to "1" to use the SIO Ch.2 receive-buffer full interrupt. Set to "0" to use the TM16 Ch.5 compare B interrupt. At power-on, this bit is set to "0". SIO2TS1: SIO Ch.2 transmit-buffer empty/TM16 Ch.5 compare A interrupt factor switching (D1) / Interrupt factor TM16 function switching register (0x402CB) Switches the interrupt factor. Write "1": SIO Ch.2 transmit-buffer empty Write "0": TM16 Ch.5 compare A Read: Valid B-II Set to "1" to use the SIO Ch.2 transmit-buffer empty interrupt. Set to "0" to use the TM16 Ch.5 compare A interrupt. At power-on, this bit is set to "0". SIO3RS1: SIO Ch.3 receive-buffer full/TM16 Ch.4 compare B interrupt factor switching (D2) / Interrupt factor TM16 function switching register (0x402CB) Switches the interrupt factor. ITC Write "1": SIO Ch.3 receive-buffer full Write "0": TM16 Ch.4 compare B Read: Valid Set to "1" to use the SIO Ch.3 receive-buffer full interrupt. Set to "0" to use the TM16 Ch.4 compare B interrupt. At power-on, this bit is set to "0". SIO3TS1: SIO Ch.3 transmit-buffer empty/TM16 Ch.4 compare A interrupt factor switching (D3) / Interrupt factor TM16 function switching register (0x402CB) Switches the interrupt factor. Write "1": SIO Ch.3 transmit-buffer empty Write "0": TM16 Ch.4 compare A Read: Valid Set to "1" to use the SIO Ch.3 transmit-buffer empty interrupt. Set to "0" to use the TM16 Ch.4 compare A interrupt. At power-on, this bit is set to "0". SIO2ES1: SIO Ch.2 receive error/TM16 Ch.3 compare B interrupt factor switching (D4) / Interrupt factor TM16 function switching register (0x402CB) Switches the interrupt factor. Write "1": SIO Ch.2 receive error Write "0": TM16 Ch.3 compare B Read: Valid Set to "1" to use the SIO Ch.2 receive error interrupt. Set to "0" to use the TM16 Ch.3 compare B interrupt. At power-on, this bit is set to "0". S1C33L03 FUNCTION PART EPSON B-II-5-23 II CORE BLOCK: ITC (Interrupt Controller) SIO3ES1: SIO Ch.3 receive error/TM16 Ch.3 compare A interrupt factor switching (D5) / Interrupt factor TM16 function switching register (0x402CB) Switches the interrupt factor. Write "1": SIO Ch.3 receive error Write "0": TM16 Ch.3 compare A Read: Valid Set to "1" to use the SIO Ch.3 receive error interrupt. Set to "0" to use the TM16 Ch.3 compare A interrupt. At power-on, this bit is set to "0". T8CH4S1: 8-bit timer 4 underflow/TM16 Ch.2 compare B interrupt factor switching (D6) / Interrupt factor TM16 function switching register (0x402CB) Switches the interrupt factor. Write "1": 8-bit timer 4 underflow Write "0": TM16 Ch.2 compare B Read: Valid Set to "1" to use the 8-bit timer 4 underflow interrupt. Set to "0" to use the TM16 Ch.2 compare B interrupt. At power-on, this bit is set to "0". T8CH5S1: 8-bit timer 5 underflow/TM16 Ch.2 compare A interrupt factor switching (D7) / Interrupt factor TM16 function switching register (0x402CB) Switches the interrupt factor. Write "1": 8-bit timer 5 underflow Write "0": TM16 Ch.2 compare A Read: Valid Set to "1" to use the 8-bit timer 5 underflow interrupt. Set to "0" to use the TM16 Ch.2 compare A interrupt. At power-on, this bit is set to "0". TBRP7-TBRP0: TTBR register write protection ([D[7:0]) / TTBR write-protect register (0x4812D) Remove write protection for the TTBR register. Write 0x59: Write protection is removed Write not the above: No operation (write protected) Read: Valid Before writing to the TTBR register, set TBRP to "0x59" to remove the write protection. Then when data is written to the most significant byte (0x48137) of the TTBR, the register once again becomes write-protected. After an initial reset, TBRP is set to "0x0" (write protected). B-II-5-24 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: ITC (Interrupt Controller) A-1 TTBR09-TTBR00: Trap table base address [9:0] (D[9:0]) / TTBR low-order register (0x48134[HW]) TTBR15-TTBR10: Trap table base address [15:10] (D[F:A]) / TTBR low-order register (0x48134[HW]) TTBR2B-TTBR20: Trap table base address [27:16] (D[B:0]) / TTBR high-order register (0x48136[HW]) TTBR33-TTBR30: Trap table base address [31:28] (D[F:C]) / TTBR high-order register (0x48136[HW]) Set the starting address of the trap table. TTBR0 and TTBR3 are read-only registers and are fixed to "0". For this reason, the trap table starting address always begins with a 1KB boundary address. The TTBR registers normally are write-protected to prevent them from being inadvertently rewritten. To remove this write protect function, another register, TBRP (D[7:0]) / TTBR write-protect register (0x4812D), is provided. A write to the TTBR register is enabled by writing "0x59" to TBRP and is disabled back again by a write to the most significant byte of the TTBR register (0x48137). Consequently, writes to the TTBR register need to begin with the low-order half-word first. However, since occurrences of NMI and the like between writes of the loworder and high-order half-words cause malfunctions, it is recommended that the register be written in words. After an initial reset, the TTBR register is set to 0x0C00000. Programming Notes (1) In cases when an interrupt factor that is used for restarting from the standby mode has been set to invoke IDMA, IDMA is started up by the interrupt at its occurrence. In SLEEP mode, the high-speed (OSC3) oscillation circuit also starts operating. However, if an interrupt to be generated upon completion of IDMA is disabled at the setting of IDMA side, no interrupt request is signaled to the CPU. Therefore, the CPU remains idle until the next interrupt request is generated. (2) As the S1C33000 Core CPU function, the IL allows interrupt levels to be set in the range of 0 to 15. However, since the interrupt priority register in the C33 Core Block consists of three bits, interrupt levels in each interrupt system can only be set for up to 8. (3) When the reset-only method is used to reset the interrupt factor flag (by writing "1"), if a read-modify-write instruction (e.g., bset, bclr, or bnot) is executed, the other interrupt factor flags at the same address that have been set to "1" are reset by a write. This requires caution. In cases when the read/write method is used to reset the interrupt factor flag (by writing "0"), all factor flags for which "0" has been written are reset. When a read-modify-write operation is performed, an interrupt factor may occur between reads and writes, so be careful when using this method. The same applies to the set-only method and read/write method for the IDMA request and IDMA enable registers. (4) After an initial reset, the interrupt factor flags and interrupt priority registers all become indeterminate. To prevent unwanted interrupts or IDMA requests from being generated inadvertently, be sure to reset these flags and registers in the software application. (5) To prevent another interrupt from being generated for the same factor again after generation of an interrupt, be sure to reset the interrupt factor flag before enabling interrupts and setting the PSR again or executing the reti instruction. S1C33L03 FUNCTION PART EPSON B-II-5-25 B-II ITC II CORE BLOCK: ITC (Interrupt Controller) THIS PAGE IS BLANK. B-II-5-26 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: CLG (Clock Generator) A-1 II-6 CLG (Clock Generator) This section describes the method for controlling the system clock. Configuration of Clock Generator The C33 Core Block has a built-in clock generator that consists of a high-speed oscillation circuit (OSC3) and a PLL. The high-speed (OSC3) oscillation circuit generates the main clock for the CPU and internal peripheral circuits (e.g., DMA, serial interface, programmable timer, and A/D converter). Furthermore, the clock generator can input a sub clock, such as low-speed (OSC1, 32.768 kHz, Typ.) clock generated by the Peripheral Block, for the clock timer and for operating the CPU at a low clock speed in order to reduce current consumption. Note: When the Peripheral Block including the low-speed (OSC1) oscillation circuit is used, the source clocks for the CPU and the peripheral circuits (e.g., serial interface, programmable timer, and A/D converter) can be selected between the OSC3 clock and the OSC1 clock. For details, refer to "Setting and Switching Over the CPU Operating Clock" in this section and "Prescaler" and "LowSpeed (OSC1) Oscillation Circuit" of the Peripheral Block. B-II Figure 6.1 shows the configuration of the clock generator. CLG SOSC3 CLKDT[1:0] Oscillation ON/OFF OSC3 OSC4 SLEEP High-speed (OSC3) oscillation circuit PLLC PLLS0 PLLS1 Divider 1/1 to 1/8 CLKCHG Clock switch HALT, HALT2, SLEEP HALT2, SLEEP PLL SLEEP CLG To CPU To BCU and DMA To peripheral circuits To peripheral circuits and clock timer Peripheral Block SOSC1 Oscillation ON/OFF OSC1 OSC2 Low-speed (OSC1) oscillation circuit Figure 6.1 Configuration of Clock Generator After an initial reset, the output (OSC3 clock) of the high-speed (OSC3) oscillation circuit is set for the CPU operating clock. When the low-speed (OSC1) oscillation circuit is used, the CPU operating clock can be switched to the output (OSC1 clock) of the low-speed (OSC1) oscillation circuit in a program. Furthermore, each oscillation circuit can be stopped in a program. If the OSC3 clock is unnecessary such as when performing clock processing only, set the OSC1 clock for operation of the CPU and turn off the high-speed (OSC3) oscillation circuit in order to reduce current consumption. In addition, when SLEEP mode is set, the high-speed (OSC3) oscillation circuit is turned off, greatly reducing current consumption (no internal units except for the clock timer need to be operated). S1C33L03 FUNCTION PART EPSON B-II-6-1 II CORE BLOCK: CLG (Clock Generator) I/O Pins of Clock Generator Table 6.1 lists the I/O pins of the clock generator. Table 6.1 I/O Pins of Clock Generator Pin name I/O OSC3 I OSC4 PLLC PLLS[1:0] Function High-speed (OSC3) oscillation input pin Crystal/ceramic oscillation or external clock input O High-speed (OSC3) oscillation output pin Crystal/ceramic oscillation (open when external clock is used) - Capasitor connecting pin for PLL I PLL set-up pins PLLS1 PLLS0 fin (fOSC3) fout (fPSCIN) 1 1 10-25MHz 20-50MHz 1 0 1 10-12.5MHz 40-50MHz 1 0 0 PLL is not used L 2 1: ROM-less model with 3.3 V 0.3 V operating voltage 2: When the PLL is not used, the OSC3 clock is used directly. High-Speed (OSC3) Oscillation Circuit The high-speed (OSC3) oscillation circuit generates the main clock for the CPU and internal peripheral circuits (e.g., DMA, serial interface, programmable timer, and A/D converter). This circuit can be a crystal or a ceramic oscillation circuit. Optionally an external clock source can be used. Figure 6.2 shows the structure of the high-speed (OSC3) oscillation circuit. CG2 Rf CD2 VSS OSC3 X'tal2 or Ceramic OSC4 VDD VSS fOSC3 Oscillation circuit control signal SLEEP status (1) Crystal/ceramic oscillation circuit OSC3 fOSC3 External clock Oscillation circuit control signal SLEEP status N.C. OSC4 (2) External clock input Figure 6.2 High-Speed (OSC3) Oscillation Circuit When using a crystal or a ceramic oscillation for this circuit, connect a crystal (X'tal2) or ceramic (Ceramic) resonator and feedback resistor (Rf) between the OSC3 and OSC4 pins, and two capacitors (CG2, CD2) between the OSC3 pin and VSS and the OSC4 pin and VSS, respectively. When an external clock is used, leave the OSC4 pin open and input a square-wave clock to the OSC3 pin. The range of oscillation frequencies is 10 MHz to 33 MHz. This frequency range also applies when an external clock is used. Note: When using the PLL, the oscillation frequency range changes according to the PLL setting. See Table 6.2. For details on oscillation characteristics and the external clock input characteristics, refer to "Electrical Characteristics". B-II-6-2 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: CLG (Clock Generator) A-1 PLL The PLL inputs the OSC3 clock and multiply its frequency. The multiply mode should be set using the PLLS[1:0] pins according to the OSC3 clock frequency. Table 6.2 Setting the PLLS[1:0] Pins PLLS1 PLLS0 Mode fin (OSC3 clock) fout Notes 1 0 0 1 1 0 x2 x4 PLL Not used 10 to 25 MHz 10 to 12.5 MHz - 20 to 50 MHz 40 to 50 MHz Not used No ROM, and 3.3 V 0.3 V No ROM, and 3.3 V 0.3 V Figure 6.3 shows a basic external connection diagram for the PLL pins. VDD PLLS1 PLLS0 100 pF PLL 4.7 k PLLC B-II 5 pF VSS Figure 6.3 External Connection Diagram Note: When the PLL is not used, the OSC3 oscillation output is used as the source clock. In this case, the oscillation frequency range is 10 MHz to 33 MHz. Furthermore, leave the PLLC pin open. CLG Controlling Oscillation The high-speed (OSC3) oscillation circuit can be turned on or off using SOSC3 (D1) / Power control register (0x40180). The oscillation circuit is turned off by writing "0" to SOSC3 and turned back on again by writing "1". SOSC3 is set to "1" at initial reset, so the oscillation circuit is turned on. Notes: * When the high-speed (OSC3) oscillation circuit is used as the clock source for the CPU operating clock, it cannot be turned off. In this case, writing "0" to SOSC3 is ignored. Note also that writing to SOSC3 is allowed only when the power-control register protection flag is set to "0b10010110". * Immediately after the oscillation circuit is turned on, a certain period of time is required for oscillation to stabilize (for 3.3-V crystal resonator, this time is 10 ms max.). To prevent the device from operating erratically, do not use the clock until its oscillation has stabilized. The high-speed (OSC3) oscillation circuit turns off when the CPU is set in SLEEP mode. S1C33L03 FUNCTION PART EPSON B-II-6-3 II CORE BLOCK: CLG (Clock Generator) Setting and Switching Over the CPU Operating Clock Setting the CPU operating clock frequency When operating the CPU with the high-speed (OSC3) clock, the operating frequency can be switched over in four steps. Use CLKDT[1:0] (D[7:6]) / Power control register (0x40180) for this switchover. Table 6.3 Setting of CPU Operating Clock CLKDT1 CLKDT0 1 1 0 0 1 0 1 0 Division ratio fout/8 fout/4 fout/2 fout/1 fout: PLL output The clock thus set becomes the system clock, which is used as the CPU operating clock and the bus clock. At initial reset, the division ratio is set to fout/1, so the CPU is operated directly by the PLL output clock. Since the device's current consumption can be decreased by reducing the CPU operating speed, switch over the operating frequency as necessary. This setting is effective only for the high-speed (OSC3) clock, and has no effect when the low-speed (OSC1) clock is used as the system clock. Note: Writing to CLKDT[1:0] is effective only when the power-control register protection flag is set to "0b10010110". Switching over the CPU operating clock Note: The CPU operating clock can be switched from OSC3 to OSC1 only when the low-speed (OSC1) oscillation circuit in the Peripheral Block is used. After an initial reset, the CPU starts operating using the OSC3 clock. All internal peripheral circuits also operate. In cases in which some peripheral circuits (e.g., programmable timer, serial interface, A/D converter, and ports) do not need to be operate or processing in low-speed operation is possible, and the CPU can process its jobs at a low clock speed, the CPU operating clock can be switched to the OSC1 clock, thereby reducing current consumption. Use CLKCHG (D2) / Power control register (0x40180) to switch over the operating clock. Procedure for switching over from the OSC3 clock to the OSC1 clock 1. Turn on the low-speed (OSC1) oscillation circuit (by writing "1" to SOSC1). 2. Wait until the OSC1 oscillation stabilizes (three seconds or more). 3. Change the CPU operating clock (by writing "0" to CLKCHG). 4. Turn off the high-speed (OSC3) oscillation circuit (by writing "0" to SOSC3). Steps 1 and 2 are required only when the low-speed (OSC1) oscillation circuit is inactive. Notes: * Use separate instructions to switch from OSC3 to OSC1 and turn the OSC3 oscillation off. If these operations are processed simultaneously using one instruction, the CPU may operate erratically. * Make sure the operation of the peripheral circuits, such as the programmable timer and serial interface is terminated before the OSC3 oscillation is turned off in order to prevent them from operating erratically or the prescaler clock is set as OSC1. In addition, in order to prevent incorrect operation, a setup of prescaler must be performed before changing the CPU clock. Procedure for switching over from the OSC1 clock to the OSC3 clock 1. Turn on the high-speed (OSC3) oscillation circuit (by writing "1" to SOSC3). 2. Wait until the OSC3 oscillation stabilizes (10 ms or more for a 3.3-V crystal resonator). 3. Switch over the CPU operating clock (by writing "1" to CLKCHG). Note: The operating clock switchover by CLKCHG is effective only when both oscillation circuits are on and the power-control register protection flag is set to "0b10010110". B-II-6-4 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: CLG (Clock Generator) A-1 Power-Control Register Protection Flag The power-control register at address 0x40180, which is used to control the oscillation circuits and the CPU operating clock, is normally disabled against writing in order to prevent it from malfunctioning due to unnecessary writing. To enable this register for writing, the power-control register protection flag CLGP[7:0] (D[7:0]) / Power-control protection register (0x4019E) must be set to "0b10010110". Note that this setting allows for the power-control register (0x40180) to be written to only once, so all bits of CLGP[7:0] are cleared to "0" when this address is written to. Therefore, CLGP[7:0] must be set to "0b10010110" each time the power-control register (0x40180) is written to. The flag CLGP[7:0] does not affect the readout from the power-control register (0x40180). Operation in Standby Mode In HALT mode, which is entered by executing the halt instruction, the high-speed (OSC3) and low-speed (OSC1) oscillation circuits both retain their status before HALT mode is entered. Under normal conditions, therefore, there is no need to control the oscillation circuits before entering or after exiting HALT mode. The high-speed (OSC3) oscillation circuit stops operating after SLEEP mode is entered, which is done by executing the slp (sleep) instruction. If the high-speed (OSC3) oscillation circuit was operating before SLEEP mode was entered, it automatically starts oscillating again after SLEEP mode is exited. In addition, if the CPU was operating using the OSC3 clock before SLEEP mode was entered, the CPU starts operating using the OSC3 clock again even after SLEEP mode is exited. The high-speed (OSC3) oscillation circuit requires 10 ms max. (when using a 3.3-V crystal resonator) for its oscillation to stabilize after oscillation starts. To prevent the CPU from operating erratically upon restart during this period, the C33 Core Block is designed to allow the OSC3 clock supply to the CPU to be disabled in the hardware after SLEEP mode is exited. Use 8T1ON (D2) / Clock option register (0x40190) to select this function. Use 8-bit programmable timer 1 to set the waitting time before clock supply is started. The processing procedure and the operations to be performed when this function is used are as follows: 1. Disable the 8-bit programmable timer 1 interrupt. 2. Preset the initial count to 8-bit programmable timer 1. Set a value that will provide an ample stabilization waiting time. It is also necessary to set the input clock for 8bit programmable timer 1 using the prescaler. 3. Enable the interrupt used to exit SLEEP mode. Before enabling the interrupt, be sure to reset the interrupt factor flag. 4. Write "0" to 8T1ON (turn on the function for waiting until the oscillation stabilizes after exiting SLEEP mode). 5. Activate 8-bit programmable timer 1 to start counting. 6. Enter SLEEP mode using the slp instruction. : SLEEP mode : 7. Exit SLEEP mode using an NMI, input port, or timer interrupt. 8. The high-speed (OSC3) oscillation circuit starts oscillating when SLEEP mode is exited. 8-bit programmable timer 1 also is made to start counting using the OSC3 clock. 9. 8-bit programmable timer 1 underflows. The operating clock supply to the CPU is begun by the underflow signal, so that the CPU restarts. For details on how to control the 8-bit programmable timer, prescaler, and interrupts, refer to the description of each item in this manual. Note: The function for waiting until the high-speed (OSC3) oscillation is stabilized by 8T1ON is effective only when SLEEP mode is exited. Writing to 8T1ON is effective only when the power-control register protection flag is set to "0b10010110". S1C33L03 FUNCTION PART EPSON B-II-6-5 B-II CLG II CORE BLOCK: CLG (Clock Generator) I/O Memory of Clock Generator Table 6.4 lists the control bits of clock generator. Table 6.4 Control Bits of Clock Generator Register name Address Bit Name Power control register D7 D6 CLKDT1 CLKDT0 System clock division ratio selection D5 D4-3 D2 D1 D0 PSCON - CLKCHG SOSC3 SOSC1 Prescaler On/Off control reserved 1 OSC3 CPU operating clock switch High-speed (OSC3) oscillation On/Off 1 On Low-speed (OSC1) oscillation On/Off 1 On D7-4 D3 D2 D1 D0 - HLT2OP 8T1ON - PF1ON - HALT clock option OSC3-stabilize waiting function reserved OSC1 external output control CLGP7 CLGP6 CLGP5 CLGP4 CLGP3 CLGP2 CLGP1 CLGP0 Power control register protect flag Writing 10010110 (0x96) removes the write protection of the power control register (0x40180) and the clock option register (0x40190). Writing another value set the write protection. Clock option register 0040180 (B) 0040190 (B) Power control 004019E protect register (B) D7 D6 D5 D4 D3 D2 D1 D0 Function Setting CLKDT[1:0] 1 1 1 0 0 1 0 0 1 On Remarks 0 0 R/W 1 0 1 1 1 R/W - Writing 1 not allowed. R/W R/W R/W - - 0 1 0 0 - 0 when being read. R/W R/W - Do not write 1. R/W 0 0 0 0 0 0 0 0 R/W 1 On 1 Off 0 Off 0 On - 1 On Init. R/W Division ratio 1/8 1/4 1/2 1/1 0 Off - 0 OSC1 0 Off 0 Off 0 Off SOSC1: Low-speed (OSC1) oscillation control (D0) / Power control register (0x40180) Turns the low-speed (OSC1) oscillation on or off. Write "1": OSC1 oscillation turned on Write "0": OSC1 oscillation turned off Read: Valid The oscillation of the low-speed (OSC1) oscillation circuit is stopped by writing "0" to SOSC1, and started again by writing "1". Since a duration of maximum three seconds is required for oscillation to stabilize after the oscillation has been restarted, at least this length of time must pass before the OSC1 clock can be used. Writing to SOSC1 is allowed only when CLGP[7:0] is set to "0b10010110". Note also that if the CPU is operating using the OSC1 clock, writing "0" to SOSC1 is ignored and the oscillation is not turned off. At initial reset, SOSC1 is set to "1" (OSC1 oscillation turned on). Note: This control bit is effective only when the low-speed (OSC1) oscillation circuit in the Peripheral Block is used. SOSC3: High-speed (OSC3) oscillation control (D1) / Power control register (0x40180) Turns the high-speed (OSC3) oscillation on or off. Write "1": OSC3 oscillation turned on Write "0": OSC3 oscillation turned off Read: Valid The oscillation of the high-speed (OSC3) oscillation circuit is stopped by writing "0" to SOSC3, and started again by writing "1". Since a duration of maximum 10 ms (for a 3.3-V crystal resonator) is required for oscillation to stabilize after the oscillation has been restarted, at least this length of time must pass before the OSC3 clock can be used. Writing to SOSC3 is allowed only when CLGP[7:0] is set to "0b10010110". Note also that if the CPU is operating using the OSC3 clock, writing "0" to SOSC3 is ignored and the oscillation is not turned off. At initial reset, SOSC3 is set to "1" (OSC3 oscillation turned on). B-II-6-6 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: CLG (Clock Generator) A-1 CLKCHG: CPU operating clock switch (D2) / Power control register (0x40180) Selects the CPU operating clock. Write "1": OSC3 clock Write "0": OSC1 clock Read: Valid The OSC3 clock is selected as the CPU operating clock by writing "1" to CLKCHG, and OSC1 is selected by writing "0". The operating clock can be switched over in this way only when both the high-speed (OSC3) and lowspeed (OSC1) oscillation circuits are on. In addition, writing to CLKCHG is effective only when CLGP[7:0] is set to "0b10010110". Immediately after the oscillation circuit has started oscillating, wait for the oscillation to stabilize before switching over the CPU operating clock. At initial reset, CLKCHG is set to "1" (OSC3 clock). Note: This control bit is effective only when the low-speed (OSC1) oscillation circuit in the Peripheral Block is used. CLKDT1-CLKDT0: CPU operating frequency selection (D[7:6]) / Power control register (0x40180) Select the CPU operating clock frequency. B-II Table 6.5 Setting of CPU Operating Clock CLKDT1 CLKDT0 1 1 0 0 1 0 1 0 Division ratio fout/8 fout/4 fout/2 fout/1 fout: PLL output This setting is effective when the CPU is operated using the high-speed (OSC3) clock and has no effect on the lowspeed (OSC1) clock. Writing to CLKDT[1:0] is allowed only when CLGP[7:0] is set to "0b10010110". At initial reset, CLKDT is set to "0" (fout/1). 8T1ON: High-speed (OSC3) oscillation waiting function (D2) / Clock option register (0x40190) Sets the function for waiting until the high-speed (OSC3) oscillation stabilizes after SLEEP mode is exited. Write "1": Off Write "0": On Read: Valid After SLEEP mode is exited, the high-speed (OSC3) oscillation waiting function is effective by writing "1" to 8T1ON. For this function to be used, the waiting time must be set in 8-bit programmable timer 1 to allow it to start counting before entering SLEEP mode. After SLEEP mode is exited, the OSC3 clock is not supplied to the CPU until 8-bit programmable timer 1 underflows. This function will not work when 8T1ON is set to "0". The high-speed (OSC3) oscillation waiting function is effective only when SLEEP mode is exited. Writing to 8T1ON is effective only when CLGP[7:0] is set to "0b10010110". When writing to 8T1ON, always be sure to write "0" to the reserved bits at address 0x40190. At initial reset, 8T1ON is set to "1" (Off). HLT2OP: HALT clock option (D3) / Clock option register (0x40190) Select a HALT condition (basic mode or HALT2 mode). Write "1": HALT2 mode Write "0": Basic mode Read: Valid When "1" is written to HLT2OP, the CPU will enter HALT2 mode when the HALT instruction is executed. When "0" is written, the CPU will enter basic mode. Writing to HLT2OP is allowed only when CLGP[7:0] is set to "0b10010110". At initial reset, HLT2OP is set to "0" (basic mode). The following shows the operating status in HALT mode (basic mode and HALT2 mode) and SLEEP mode. S1C33L03 FUNCTION PART EPSON B-II-6-7 CLG II CORE BLOCK: CLG (Clock Generator) Table 6.6 Operating Status in Standby Mode Standby mode HALT mode Basic mode Operating status * * * * * * HALT2 mode * * * * * * SLEEP mode * * * * * The CPU clock is stopped. (CPU stop status) BCU clock is supplied. (BCU run status) DMA clock is not stopped. (DMA run status) Clocks for the peripheral circuits maintain the status before entering HALT mode. (run or stop) The high-speed oscillation circuit maintains the status before entering HALT mode. The low-speed oscillation circuit maintains the status before entering HALT mode. The CPU clock is stopped. (CPU stop status) BCU clock is stopped. (BCU stop status) DMA clock is stopped. (DMA stop status) Clocks for the peripheral circuits maintain the status before entering HALT mode. (run or stop) The high-speed oscillation circuit maintains the status before entering HALT mode. The low-speed oscillation circuit maintains the status before entering HALT mode. The CPU clock is stopped. (CPU stop status) BCU clock is stopped. (BCU stop status) Clocks for the peripheral circuits are stopped. The high-speed oscillation circuit is stopped. The low-speed oscillation circuit maintains the status before entering SLEEP mode. Reactivating factor * Reset, NMI * Enabled (not masked) interrupt factors A restart is possible only in the case of: * Reset, NMI * Enabled (not masked) interrupt factors Note, however, that an interrupt from a peripheral circuit can restart the CPU only when the operating clock is supplied to the peripheral circuit. * Reset, NMI * Enabled (not masked) input port interrupt factors * Clock timer interrupt when the low-speed oscillation circuit is being operated CLGP7-CLGP0: Power-control register protection flag ([D[7:0]) / Power control protection register (0x4019E) These bits remove the protection against writing to addresses 0x40180 and 0x40190. Write "0b10010110": Write protection removed Write other than the above: No operation (write-protected) Read: Valid Before writing to address 0x40180 or 0x40190, set CLGP[7:0] to "0b10010110" to remove the protection against writing to that address. This clearing of write protection is effective for only one writing, so the bits are cleared to "0b00000000" by one writing. Therefore, CLGP[7:0] must be set each time the protected address is written to. At initial reset, CLGP is set to "0b00000000" (write-protected). B-II-6-8 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: CLG (Clock Generator) A-1 Programming Notes (1) Immediately after the high-speed (OSC3) oscillation circuit is turned on, a certain period of time is required for oscillation to stabilize (for a 3.3-V crystal resonator, this time is 10 ms max.). To prevent the device from operating erratically, do not use the clock until its oscillation has stabilized. In particular, if the CPU is set in SLEEP mode during operation using the OSC3 clock, the high-speed (OSC3) oscillation circuit is turned off during in SLEEP mode and starts oscillating again after SLEEP mode is exited. To prevent the CPU from operating erratically at restart due to an unstable OSC3 clock, set a sufficient stabilization waiting time in 8-bit programmable timer 1 to turn on the oscillation stabilization waiting function after SLEEP mode is exited before entering SLEEP mode. (2) The oscillation circuit used for the CPU operating clock cannot be turned off. (3) The CPU operating clock can only be switched over when both the OSC3 and OSC1 oscillation circuits are on. Furthermore, when turning off an oscillation circuit that has become unnecessary as a result of the CPU operating clock switchover, be sure to use separate instructions for switchover and oscillation turnoff. If these two operations are processed simultaneously using one instruction, the CPU may operate erratically. (4) If the high-speed (OSC3) oscillation circuit is turned off, all peripheral circuits operated using the OSC3 clock will be inactive. B-II (5) If the OSC3 clock is unnecessary, use the OSC1 clock to operate the CPU and turn the high-speed (OSC3) oscillation circuit off. This helps reduce current consumption. (6) In HALT mode, since the DMA and BCU clocks operate, if the next operation is performed in HALT mode, not HALT2 mode, with a setting of 0 in clock option register HLT2OP (D3/0x40190), that operation will be an unpredictable erroneous operation. If a DMA trigger occurs and DMA is invoked while the CPU is stopped after HALT mode execution, erroneous operation will result. Ensure that DMA is not invoked in HALT mode. In HALT2 mode, DMA is not invoked since the DMA and BCU clocks are stopped. (7) In the SLEEP mode, the oscillation circuit clock stops, and in the HALT2 mode, the clocks for peripheral circuits maintain the status before entering HALT2 (stop or run). When restarting from this state, interrupt input from a port can be used as a trigger, but functionally, this interrupt input operates as level input. Therefore, a level input based restart is performed even in the case of set edge input. Restart operation is as follows for rising and falling edges. In case of rising edge interrupt setting: Restarted by high level input. In case of falling edge interrupt setting: Restarted by low level input. In normal operation, a restart begins following the elapse of a given time after execution of the SLP instruction, but when restart by a falling (rising) level (edge) is set, the operation is as follows. * The restart is effected immediately after execution of the SLP instruction. * As ports are already at the low level when the SLP instruction is executed, there is no falling (rising) edge, and therefore the SLEEP state is entered only momentarily, and the restart is effected immediately afterwards. There was a synchronization circuit using a clock signal in the port input circuit, and as the clock is stopped in the SLEEP state and the clock can be stopped in the HALT2 state, the configuration provided for this synchronization circuit to be bypassed when restarting. Therefore, a restart is effected when the input level from a port is active by level. Consequently, the system design should assume that a restart by means of port input from the SLEEP state or HALT2 state is performed by level. S1C33L03 FUNCTION PART EPSON B-II-6-9 CLG II CORE BLOCK: CLG (Clock Generator) (8) If the IC enters the debug mode through the connected S5U1C33000H (In-Circuit Debugger for S1C33 Family) when the OSC3 clock is divided by 2, 4, or 8 using the CLKDT[1:0] (D[7:6])/Power control register (0x40180) to generate the CPU clock (CPU_CLK), the division ratio is automatically changed to 1/1. This may cause the CPU_CLK frequency to exceed the range assumed. Also it affects the BCU_CLK and BCLK output clocks as they are generated from CPU_CLK. If the BCU_CLK and BCLK output clock frequencies exceed the access time condition or operating range of the devices driven with these clocks, debugging functions such as memory dump as well as program execution may not operate correctly. Therefore, prescribe remedies for malfunctions when debugging, for example, changing the number of wait cycles and other parameters in the BCU registers using the debugger, so that the program can be executed and debugged without problems even when the division ratio changes to 1/1. (9) When the base clock (CPU operating clock) is generated by dividing the source clock output from OSC3 or PLL by a value (2, 4, or 8) specified using CLKDT[1:0] (D[7:6])/Power control register (0x40180), the peripheral circuit clocks must be set lower than the base clock frequency using the prescaler. If the peripheral circuit clock frequency is equal to or higher than the base clock frequency, the peripheral circuit does not operate normally. B-II-6-10 EPSON S1C33L03 FUNCTION PART II CORE BLOCK: DBG (Debug Unit) A-1 II-7 DBG (Debug Unit) Debug Circuit The C33 Core Block has a built-in debug circuit. This functional block is provided to simply realize an advanced software development environment. Note: The debug circuit does not work during normal operation. To construct a software development environment using the debug circuit, the S5U1C33000H (In-Circuit Debugger for S1C33 Family) is separately required. I/O Pins of Debug Circuit Six pins used to exclusively connect the S5U1C33000H (In-Circuit Debugger for S1C33 Family) are reserved for the debug circuit. The I/O voltage level of these pins is 3.3 V. Table 7.1 lists the I/O pins of the debug circuit. Table 7.1 I/O Pins of Debug Circuit Pin name I/O Pull-up Initial status Voltage level DCLK O - 1 3.3 V Clock output for debugging DST2 DST1 DST0 DPCO DSIO O O O O I/O - - - - With pull-up 0 1 1 1 1 (Input) 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V Status output 2 for debugging Status output 1 for debugging Status output 0 for debugging PC output for debugging Serial I/O for debugging B-II Function The DCLK, DST[2:0] and DPCO outputs are extended functions of the I/O port pins P14, P1[2:0] and P13, respectively. At initial reset, these pins are set as debug signal outputs. If the debug circuit is not used, these pins can be used for I/O ports or the redefined peripheral circuits by writing "0" to CFEX[1:0] (D[1:0]) / Port function extension register (0x402DF). Refer to "I/O Ports (P Ports)" for the pin functions. Note: When these pins are set as debug signal outputs, only the S5U1C33000H (In-Circuit Debugger for S1C33 Family) can be connected to these pins. Leave these pins open if the S5U1C33000H is not connected. For connecting the S5U1C33000H, refer to the "S5U1C33000H Manual (S1C33 Family In-Circuit Debugger)". Furthermore, the pin status is fixed as shown in the above table after a user reset. S1C33L03 FUNCTION PART EPSON B-II-7-1 DBG II CORE BLOCK: DBG (Debug Unit) THIS PAGE IS BLANK. B-II-7-2 EPSON S1C33L03 FUNCTION PART S1C33L03 FUNCTION PART III PERIPHERAL BLOCK III PERIPHERAL BLOCK: INTRODUCTION A-1 III-1 INTRODUCTION The C33 peripheral block consists of a prescaler, six 8-bit programmable timer channels, six 16-bit programmable timer channels including watchdog timer and event counter functions, four serial interface channels, input and I/O ports, a low-speed (OSC1) oscillation circuit, and a clock timer. C33 DMA Block C33 SDRAM Controller Block C33 LCD Controller Block C33_DMA C33_SDRAMC C33_LCDC (IDMA, HSDMA) (SDRAM interface) (LCD panel interface) Pads Internal RAM (Area 0) CORE_PAD C33 Internal Memory Block C33_CORE (CPU, BCU, ITC, CLG, DBG) Internal ROM (Area 10) Pads C33_SBUS C33_ADC C33_PERI (A/D converter) (Prescaler, 8-bit timer, 16-bit timer, Clock timer, Serial interface, Ports) C33 Analog Block PERI_PAD C33 Core Block B-III Pads C33 Peripheral Block Figure 1.1 Peripheral Block Note: Internal ROM is not provided in the S1C33L03. S1C33L03 FUNCTION PART EPSON B-III-1-1 Intro III PERIPHERAL BLOCK: INTRODUCTION THIS PAGE IS BLANK. B-III-1-2 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: PRESCALER A-1 III-2 PRESCALER Configuration of Prescaler The prescaler divides the source clock (OSC3/PLL output clock or OSC1 clock) to generate the clocks for the internal peripheral circuits. The prescaler division ratio can be selected for each peripheral circuit in a program. A clock control circuit to control the clock supply to each peripheral circuit is also included. The following are the peripheral circuits that use the output clock: * 16-bit programmable timers 5 to 0 (and watchdog timer) * 8-bit programmable timers 5 to 0 (and serial interface) * A/D converter Figure 2.1 shows the configuration of the prescaler. For details on control of each peripheral circuit, refer to each corresponding section in this manual. PSCON OSC3 or PLL output clock Selector OSC1 clock 1/1 1/2 1/4 Division ratio select register Prescaler output control 1/8 1/16 1/32 1/64 1/128 1/256 1/512 1/1024 1/2048 1/4096 Selector Control register 16-bit programmable timer 5-0 8-bit programmable timer 5-0 A/D converter Figure 2.1 Configuration of Prescaler and Clock Control Circuit B-III Source Clock The source clock for the prescaler can be selected using PSCDT0 (D0) / Prescaler clock select register (0x40181). When PSCDT0 = "0", the OSC3 clock (when the PLL is not used) or the PLL output clock (when the PLL is used) is selected. When PSCDT0 = "1", the OSC1 clock (typ. 32 kHz) is selected. At initial reset, the OSC3/PLL output clock is selected. Note: For the prescaler clock, the clock source same as the CPU operating clock must be selected. For details on how to control the oscillation circuit and CPU operating clock, refer to "CLG (Clock Generator)". At initial reset, the OSC3 clock is selected. The source clock is supplied to the prescaler by writing "1" to PSCON (D5) / Power control register (0x40180). At initial reset, PSCON is set to "1", so the prescaler is in an operating state. If all of said peripheral circuits can be turned off and the peripheral circuits (e.g., 16-bit programmable timers (watchdog timer), 8-bit programmable timers (DRAM refresh), A/D converter, serial interface, and ports) that use the prescaler input clock (the source clock for prescaler) can be turned off, stop the prescaler by writing "0" to PSCON. This helps to reduce current consumption. S1C33L03 FUNCTION PART EPSON B-III-2-1 PSC III PERIPHERAL BLOCK: PRESCALER Selecting Division Ratio and Output Control for Prescaler The prescaler has registers for selecting the division ratio and clock output control separately for each peripheral circuit described above, allowing each peripheral circuit to be controlled. The prescaler's division ratio can be selected from among eight ratios set for each peripheral circuit through the use of the division ratio selection bits. The divided clock is output to the corresponding peripheral circuit by writing "1" to the clock control bit. Table 2.1 Control Bits of the Clock Control Registers Peripheral circuit Division ratio selection bit 16-bit programmable timer 0 16-bit programmable timer 1 16-bit programmable timer 2 16-bit programmable timer 3 16-bit programmable timer 4 16-bit programmable timer 5 8-bit programmable timer 0 8-bit programmable timer 1 8-bit programmable timer 2 8-bit programmable timer 3 8-bit programmable timer 4 8-bit programmable timer 5 A/D converter 1 to 4: See Table 2.2. Clock control bit P16TS0[2:0] (D[2:0]/0x40147)1 P16TS1[2:0] (D[2:0]/0x40148)1 P16TS2[2:0] (D[2:0]/0x40149)1 P16TS3[2:0] (D[2:0]/0x4014A)1 P16TS4[2:0] (D[2:0]/0x4014B)1 P16TS5[2:0] (D[2:0]/0x4014C)1 P8TS0[2:0] (D[2:0]/0x4014D)2 P8TS1[2:0] (D[6:4]/0x4014D)3 P8TS2[2:0] (D[2:0]/0x4014E)4 P8TS3[2:0] (D[6:4]/0x4014E)2 P8TS4[2:0] (D[2:0]/0x40145)4 P8TS5[2:0] (D[6:4]/0x40145)2 PSAD[2:0] (D[2:0]/0x4014F)2 P16TON0 (D3/0x40147) P16TON1 (D3/0x40148) P16TON2 (D3/0x40149) P16TON3 (D3/0x4014A) P16TON4 (D3/0x4014B) P16TON5 (D3/0x4014C) P8TON0 (D3/0x4014D) P8TON1 (D7/0x4014D) P8TON2 (D3/0x4014E) P8TON3 (D7/0x4014E) P8TON4 (D3/0x40145) P8TON5 (D7/0x40145) PSONAD (D3/0x4014F) Table 2.2 Division Ratio Bit setting 7 6 1 /4096 /1024 2 /256 /128 3 /4096 /2048 4 /4096 /2048 ( = Source clock selected by PSCDT0) 5 4 3 2 1 0 /256 /64 /1024 /64 /64 /32 /512 /32 /16 /16 /256 /16 /4 /8 /128 /8 /2 /4 /64 /4 /1 /2 /32 /2 Current consumption can be reduced by turning off the clock output to the peripheral circuits that are unused among those listed above. Note: In the following cases, the prescaler output clock may contain a hazard: * If, when a clock is output, its division ratio is changed * When the clock output is switched between on and off * When the oscillation circuit is turned off or the CPU operating clock is switched over Before performing these operations, make sure the 16-bit and 8-bit programmable timers and the A/D converter are turned off. Source Clock Output to 8-Bit Programmable Timer In addition to the divided clock, the prescaler can output the source clock directly to the 8-bit programmable timer. This function can be selected for each 8-bit timer using P8TPCKx bit. 8-bit timer 0: P8TPCK0 (D0) / 8-bit timer clock select register (0x40146) 8-bit timer 1: P8TPCK1 (D1) / 8-bit timer clock select register (0x40146) 8-bit timer 2: P8TPCK2 (D2) / 8-bit timer clock select register (0x40146) 8-bit timer 3: P8TPCK3 (D3) / 8-bit timer clock select register (0x40146) 8-bit timer 4: P8TPCK4 (D0) / 8-bit timer 4/5 clock select register (0x40140) 8-bit timer 5: P8TPCK5 (D1) / 8-bit timer 4/5 clock select register (0x40140) When P8TPCKx is set to "1", the prescaler input clock (/1) is selected for the 8-bit timer x operating clock. The clock output is controlled by the P8TONx bit even if P8TPCKx is set to "1". When P8TPCKx is "0", the divided clock that is selected by P8TSx[2:0] will be output to the 8-bit timer x. At initial reset, P8TPCKx is set to "0" and P8TSx[2:0] becomes effective. B-III-2-2 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: PRESCALER A-1 I/O Memory of Prescaler Table 2.3 shows the control bits of the prescaler. Table 2.3 Control Bits of Prescaler Register name Address 8-bit timer 4/5 clock select register 0040140 (B) 8-bit timer 4/5 clock control register 0040145 (B) Bit Name D7-2 - D1 P8TPCK5 D0 P8TPCK4 D7 D6 D5 D4 D3 D2 D1 D0 P8TON5 P8TS52 P8TS51 P8TS50 P8TON4 P8TS42 P8TS41 P8TS40 Function reserved 8-bit timer 5 clock selection 8-bit timer 4 clock selection 8-bit timer 5 clock control 8-bit timer 5 clock division ratio selection 8-bit timer 4 clock control 8-bit timer 4 clock division ratio selection 8-bit timer clock select register 0040146 (B) D7-4 D3 D2 D1 D0 - P8TPCK3 P8TPCK2 P8TPCK1 P8TPCK0 reserved 8-bit timer 3 clock selection 8-bit timer 2 clock selection 8-bit timer 1 clock selection 8-bit timer 0 clock selection 16-bit timer 0 clock control register 0040147 (B) D7-4 D3 D2 D1 D0 - P16TON0 P16TS02 P16TS01 P16TS00 reserved 16-bit timer 0 clock control 16-bit timer 0 clock division ratio selection 16-bit timer 1 clock control register 0040148 (B) D7-4 D3 D2 D1 D0 - P16TON1 P16TS12 P16TS11 P16TS10 reserved 16-bit timer 1 clock control 16-bit timer 1 clock division ratio selection 16-bit timer 2 clock control register 0040149 (B) D7-4 D3 D2 D1 D0 - P16TON2 P16TS22 P16TS21 P16TS20 reserved 16-bit timer 2 clock control 16-bit timer 2 clock division ratio selection S1C33L03 FUNCTION PART EPSON Setting Init. R/W - 1 /1 1 /1 1 On 1 1 1 1 1 0 1 0 0 1 0 1 0 0 0 0 1 On 1 1 1 1 1 0 1 0 0 1 0 1 0 0 0 0 0 Divided clk. 0 Divided clk. 0 Off /256 /128 /64 /32 /16 /8 /4 /2 0 Off /4096 /2048 /64 /32 /16 /8 /4 /2 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 - 1 1 1 1 /1 /1 /1 /1 0 0 0 0 Divided clk. Divided clk. Divided clk. Divided clk. - 1 On P16TS0[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 Off Division ratio /4096 /1024 /256 /64 /16 /4 /2 /1 - 1 On P16TS1[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 Off Division ratio /4096 /1024 /256 /64 /16 /4 /2 /1 - 1 On P16TS2[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 Off Division ratio /4096 /1024 /256 /64 /16 /4 /2 /1 Remarks - 0 0 - 0 when being read. R/W : selected by R/W Prescaler clock select register (0x40181) 0 0 0 0 R/W R/W : selected by R/W Prescaler clock select R/W register (0x40181) 8-bit timer 5 can generate the clock for the serial I/F Ch.3. 0 0 0 0 R/W R/W : selected by R/W Prescaler clock select R/W register (0x40181) 8-bit timer 4 can generate the clock for the serial I/F Ch.2. - 0 0 0 0 - R/W R/W R/W R/W 0 when being read. : selected by Prescaler clock select register (0x40181) - 0 0 0 0 - 0 when being read. R/W R/W : selected by Prescaler clock select register (0x40181) B-III PSC 16-bit timer 0 can be used as a watchdog timer. - 0 0 0 0 - 0 when being read. R/W R/W : selected by Prescaler clock select register (0x40181) - 0 0 0 0 - 0 when being read. R/W R/W : selected by Prescaler clock select register (0x40181) B-III-2-3 III PERIPHERAL BLOCK: PRESCALER Register name Address Bit Name Function 16-bit timer 3 clock control register 004014A D7-4 - (B) D3 P16TON3 D2 P16TS32 D1 P16TS31 D0 P16TS30 reserved 16-bit timer 3 clock control 16-bit timer 3 clock division ratio selection 16-bit timer 4 clock control register 004014B D7-4 - (B) D3 P16TON4 D2 P16TS42 D1 P16TS41 D0 P16TS40 reserved 16-bit timer 4 clock control 16-bit timer 4 clock division ratio selection 16-bit timer 5 clock control register 004014C D7-4 - (B) D3 P16TON5 D2 P16TS52 D1 P16TS51 D0 P16TS50 reserved 16-bit timer 5 clock control 16-bit timer 5 clock division ratio selection 8-bit timer 0/1 clock control register 004014D (B) 8-bit timer 1 clock control 8-bit timer 1 clock division ratio selection D7 D6 D5 D4 D3 D2 D1 D0 B-III-2-4 P8TON1 P8TS12 P8TS11 P8TS10 P8TON0 P8TS02 P8TS01 P8TS00 8-bit timer 0 clock control 8-bit timer 0 clock division ratio selection EPSON Setting - 1 On P16TS3[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 Off Division ratio /4096 /1024 /256 /64 /16 /4 /2 /1 - 1 On P16TS4[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 Off Division ratio /4096 /1024 /256 /64 /16 /4 /2 /1 - 1 On P16TS5[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 Off Division ratio /4096 /1024 /256 /64 /16 /4 /2 /1 1 On P8TS1[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 1 On P8TS0[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 Off Division ratio /4096 /2048 /1024 /512 /256 /128 /64 /32 0 Off Division ratio /256 /128 /64 /32 /16 /8 /4 /2 Init. R/W Remarks - 0 0 0 0 - 0 when being read. R/W R/W : selected by Prescaler clock select register (0x40181) - 0 0 0 0 - 0 when being read. R/W R/W : selected by Prescaler clock select register (0x40181) - 0 0 0 0 - 0 when being read. R/W R/W : selected by Prescaler clock select register (0x40181) 0 0 0 0 R/W R/W : selected by Prescaler clock select register (0x40181) 8-bit timer 1 can generate the OSC3 oscillation-stabilize waiting period. 0 0 0 0 R/W R/W : selected by Prescaler clock select register (0x40181) 8-bit timer 0 can generate the DRAM refresh clock. S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: PRESCALER A-1 Register name Address Bit Name 8-bit timer 2/3 clock control register D7 D6 D5 D4 P8TON3 P8TS32 P8TS31 P8TS30 004014E (B) D3 D2 D1 D0 A/D clock 004014F control register (B) Power control register 0040180 (B) Prescaler clock 0040181 select register (B) Power control 004019E protect register (B) P8TON2 P8TS22 P8TS21 P8TS20 Function 8-bit timer 3 clock control 8-bit timer 3 clock division ratio selection 8-bit timer 2 clock control 8-bit timer 2 clock division ratio selection Setting 1 On P8TS3[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 1 On P8TS2[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 D7-4 D3 D2 D1 D0 - PSONAD PSAD2 PSAD1 PSAD0 reserved A/D converter clock control A/D converter clock division ratio selection D7 D6 CLKDT1 CLKDT0 System clock division ratio selection D5 D4-3 D2 D1 D0 PSCON - CLKCHG SOSC3 SOSC1 Prescaler On/Off control reserved 1 OSC3 CPU operating clock switch High-speed (OSC3) oscillation On/Off 1 On Low-speed (OSC1) oscillation On/Off 1 On D7-1 - D0 PSCDT0 D7 D6 D5 D4 D3 D2 D1 D0 CLGP7 CLGP6 CLGP5 CLGP4 CLGP3 CLGP2 CLGP1 CLGP0 reserved Prescaler clock selection 0 Off Division ratio /256 /128 /64 /32 /16 /8 /4 /2 0 Off Division ratio /4096 /2048 /64 /32 /16 /8 /4 /2 - 0 0 0 0 Remarks R/W R/W : selected by Prescaler clock select register (0x40181) 8-bit timer 3 can generate the clock for the serial I/F Ch.1. 0 0 0 0 R/W R/W : selected by Prescaler clock select register (0x40181) 8-bit timer 2 can generate the clock for the serial I/F Ch.0. - 0 0 0 0 - 0 when being read. R/W R/W : selected by Prescaler clock select register (0x40181) Division ratio 1/8 1/4 1/2 1/1 0 Off - 0 OSC1 0 Off 0 Off 0 0 R/W 1 0 1 1 1 R/W - Writing 1 not allowed. R/W R/W R/W - 0 0 - R/W 0 0 0 0 0 0 0 0 R/W 1 On P8TS0[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 Off Division ratio /256 /128 /64 /32 /16 /8 /4 /2 CLKDT[1:0] 1 1 1 0 0 1 0 0 1 On 1 OSC1 Init. R/W 0 OSC3/PLL Power control register protect flag Writing 10010110 (0x96) removes the write protection of the power control register (0x40180) and the clock option register (0x40190). Writing another value set the write protection. PSCON: Prescaler on/off control (D5) / Power control register (0x40180) Turns the prescaler on or off. Write "1": On Write "0": Off Read: Valid The source clock is input to the prescaler by writing "1" to PSCON, thereby starting a dividing operation. The prescaler is turned off by writing "0". If the peripheral circuits do not need to be operated, write "0" to this bit to reduce current consumption. Since PSCON is protected against writing the same as SOSC1, SOSC3, CLKCHG and CLKDT[1:0], CLGP[7:0] must be set to "0b10010110" before PSCON can be changed. In addition, writing "0" (Off) to PSCON stops supplying the source clock to the prescaler and stops the peripheral circuits that use the same clock (e.g., 16-bit programmable timers, 8-bit programmable timers, A/D converter, serial interface, and ports). Therefore, do not turn off the prescaler when these peripheral circuits are used. At initial reset, PSCON is set to "1" (On). S1C33L03 FUNCTION PART EPSON B-III-2-5 B-III PSC III PERIPHERAL BLOCK: PRESCALER CLGP7-CLGP0: Power-control register protection flag ([D[7:0]) / Power control protection register (0x4019E) These bits remove the protection against writing to addresses 0x40180 and 0x40190. Write "0b10010110": Write protection removed Write other than the above: No operation (write-protected) Read: Valid Before writing to address 0x40180 or 0x40190, set CLGP[7:0] to "0b10010110" to remove the protection against writing to that address. This clearing of write protection is effective for only one writing, so the bits are cleared to "0b00000000" by one writing. Therefore, CLGP[7:0] must be set each time the protected address is written to. At initial reset, CLGP is set to "0b00000000" (write-protected). PSCDT0: Prescaler clock selection (D0) / Prescaler clock select register (0x40181) Select the source clock for the prescaler. Write "1": OSC1 clock Write "0": OSC3 clock/PLL output clock Read: Valid When "1" is written to PSCDT0, the OSC1 clock (typ. 32 kHz) is selected. When "0" is written, the OSC3 clock (when the PLL is not used) or the PLL output clock (when the PLL is used) is selected. For the prescaler clock, the clock source same as the CPU operating clock must be selected. At initial reset, PSCDT0 is set to "0" (OSC3 clock/PLL output clock). P16TS0[2:0]: 16-bit timer 0 clock division ratio (D[2:0]) / 16-bit timer 0 clock control register (0x40147) P16TS1[2:0]: 16-bit timer 1 clock division ratio (D[2:0]) / 16-bit timer 1 clock control register (0x40148) P16TS2[2:0]: 16-bit timer 2 clock division ratio (D[2:0]) / 16-bit timer 2 clock control register (0x40149) P16TS3[2:0]: 16-bit timer 3 clock division ratio (D[2:0]) / 16-bit timer 3 clock control register (0x4014A) P16TS4[2:0]: 16-bit timer 4 clock division ratio (D[2:0]) / 16-bit timer 4 clock control register (0x4014B) P16TS5[2:0]: 16-bit timer 5 clock division ratio (D[2:0]) / 16-bit timer 5 clock control register (0x4014C) P8TS0[2:0]: 8-bit timer 0 clock division ratio (D[2:0]) / 8-bit timer 0/1 clock control register (0x4014D) P8TS1[2:0]: 8-bit timer 1 clock division ratio (D[6:4]) / 8-bit timer 0/1 clock control register (0x4014D) P8TS2[2:0]: 8-bit timer 2 clock division ratio (D[2:0]) / 8-bit timer 2/3 clock control register (0x4014E) P8TS3[2:0]: 8-bit timer 3 clock division ratio (D[6:4]) / 8-bit timer 2/3 clock control register (0x4014E) P8TS4[2:0]: 8-bit timer 4 clock division ratio (D[2:0]) / 8-bit timer 4/5 clock control register (0x40145) P8TS5[2:0]: 8-bit timer 5 clock division ratio (D[6:4]) / 8-bit timer 4/5 clock control register (0x40145) PSAD[2:0]: A/D converter clock division ratio (D[2:0]) / A/D clock control register (0x4014F) Select a clock for each peripheral circuit. The desired division ratio can be selected from among the eight ratios shown on the I/O map. Note that the division ratio differs for each peripheral circuit. These bits can also be read out. At initial reset, all of these bits are set to "0b000" (highest frequency available). B-III-2-6 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: PRESCALER A-1 P16TON0: 16-bit timer 0 clock control (D3) / 16-bit timer 0 clock control register (0x40147) P16TON1: 16-bit timer 1 clock control (D3) / 16-bit timer 1 clock control register (0x40148) P16TON2: 16-bit timer 2 clock control (D3) / 16-bit timer 2 clock control register (0x40149) P16TON3: 16-bit timer 3 clock control (D3) / 16-bit timer 3 clock control register (0x4014A) P16TON4: 16-bit timer 4 clock control (D3) / 16-bit timer 4 clock control register (0x4014B) P16TON5: 16-bit timer 5 clock control (D3) / 16-bit timer 5 clock control register (0x4014C) P8TON0: 8-bit timer 0 clock control (D3) / 8-bit timer 0/1 clock control register (0x4014D) P8TON1: 8-bit timer 1 clock control (D7) / 8-bit timer 0/1 clock control register (0x4014D) P8TON2: 8-bit timer 2 clock control (D3) / 8-bit timer 2/3 clock control register (0x4014E) P8TON3: 8-bit timer 3 clock control (D7) / 8-bit timer 2/3 clock control register (0x4014E) P8TON4: 8-bit timer 4 clock control (D3) / 8-bit timer 4/5 clock control register (0x40145) P8TON5: 8-bit timer 5 clock control (D7) / 8-bit timer 4/5 clock control register (0x40145) PSONAD: A/D converter clock control (D3) / A/D clock control register (0x4014F) Control the clock supply to each peripheral circuit. Write "1": On Write "0": Off Read: Valid The clock selected using the division ratio setup bits is output to the corresponding peripheral circuit by writing "1" to these bits. The clock is not output by writing "0". If the peripheral circuits do not need to be operated, write "0" to these bits. This helps to reduce current consumption. At initial reset, all of these bits are set to "0" (Off). P8TPCK0: 8-bit timer 0 clock selection (D0) / 8-bit timer clock select register (0x40146) P8TPCK1: 8-bit timer 1 clock selection (D1) / 8-bit timer clock select register (0x40146) P8TPCK2: 8-bit timer 2 clock selection (D2) / 8-bit timer clock select register (0x40146) P8TPCK3: 8-bit timer 3 clock selection (D3) / 8-bit timer clock select register (0x40146) P8TPCK4: 8-bit timer 4 clock selection (D0) / 8-bit timer 4/5 clock select register (0x40140) P8TPCK5: 8-bit timer 5 clock selection (D1) / 8-bit timer 4/5 clock select register (0x40140) B-III PSC Select the operating clock for the 8-bit programmable timer. Write "1": Prescaler input clock (/1) Write "0": Divided clock Read: Valid When "1" is written to P8TPCKx, the prescaler input clock (/1) is selected for the 8-bit timer x operating clock. The clock output is controlled by the P8TONx bit even if P8TPCKx is set to "1". When "0" is written, the divided clock that is selected by P8TSx[2:0] will be output to the 8-bit timer x. At initial reset, P8TPCKx is set to "0" (divided clock). S1C33L03 FUNCTION PART EPSON B-III-2-7 III PERIPHERAL BLOCK: PRESCALER Programming Notes (1) For the prescaler clock, the clock source same as the CPU operating clock must be selected. (2) In the following cases, the prescaler output clock may contain a hazard: * If, during outputting of a clock, its division ratio is changed * When the clock output is switched between on and off * When the oscillation circuit is turned off or the CPU operating clock is switched over Before performing these operations, make sure the 16-bit and 8-bit programmable timers and the A/D converter are turned off. (3) When the 16-bit and 8-bit programmable timers and the A/D converter do not need to be operated, turn off the clock supply to those peripheral circuits. This helps to reduce current consumption. (4) Be aware that some peripheral circuits stops operating when the prescaler is turned off (PSCON (D5) / Power control register (0x40180) = "0") as well as the peripheral circuits that use the prescaler output clock. The prescaler status affects the peripheral circuits shown below. (A) Peripheral circuits that use the clock generated by the prescaler * 16-bit programmable timers (watchdog timer) * 8-bit programmable timers (DRAM refresh, serial interface) * A/D converter (B) Peripheral circuits that use the clock supplied to the prescaler (the source clock for prescaler) * 16-bit programmable timers (watchdog timer) * 8-bit programmable timers (DRAM refresh) * A/D converter * Serial interface * Input/output ports If none of all circuits of the above (A) and (B) need to be used, turn off the prescaler (PSCON = "0"). If a circuit of the above (A) or (B) need to be used, do not turn off the prescaler. When the prescaler is turned off, the clock supply to the circuits of the above (B) stops. When some these circuits of the above (A) need to be used, turn off all other unnecessary circuits and stop the clock supply from the prescaler to those circuits. B-III-2-8 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS A-1 III-3 8-BIT PROGRAMMABLE TIMERS Configuration of 8-Bit Programmable Timer The Peripheral Block contains six channels of 8-bit programmable timers (timers 0 to 5). Figure 3.1 shows the structure of the 8-bit programmable timer. Prescaler 8-bit reload data register (RLDx) Reload Underflow Clock output Underflow signal output Underflow interrupt 8-bit down counter Data bus Clock generator Data buffer (PTDx) Control circuit Control registers Interrupt controller Figure 3.1 Structure of 8-Bit Programmable Timer Each timer consists of an 8-bit presentable counter and can output a clock generated by the counter's underflow signal to the internal peripheral circuits or external devices. The output clock cycle can be selected from a wide range of cycles by setting the preset data that can be set in the software and the input clock in the prescaler. Output Pins of 8-Bit Programmable Timers The underflow signals of 8-bit programmable timers 0 to 3 can be output to external devices. Table 3.1 shows the pins that are used to output the underflow signals of the 8-bit programmable timers to external devices. B-III Table 3.1 Output Pins of 8-Bit Programmable Timers Pin name P10/EXCL0/ T8UF0 P11/EXCL1/ T8UF1 P12/EXCL2/ T8UF2 P13/EXCL3/ T8UF3 I/O Function 8TM Function select bit I/O I/O port / 16-bit timer 0 event counter input / 8-bit timer 0 output / DST0 output I/O I/O port / 16-bit timer 1 event counter input / 8-bit timer 1 output / DST1 output I/O I/O port / 16-bit timer 2 event counter input / 8-bit timer 2 output / DST2 output I/O I/O port / 16-bit timer 3 event counter input / 8-bit timer 3 output / DPCO output CFP10(D0)/P1 function select register (0x402D4) CFEX1(D1)/Port function extension register (0x402DF) CFP11(D1/P1 function select register (0x402D4) CFEX1(D1)/Port function extension register (0x402DF) CFP12(D2/P1 function select register (0x402D4) CFEX0(D0)/Port function extension register (0x402DF) CFP13(D3/P1 function select register (0x402D4) CFEX1(D1)/Port function extension register (0x402DF) T8UFx (output pin of the 8-bit programmable timer) This pin outputs a clock divided in each 8-bit programmable timer. The pulse width is equal to that of input clock of the 8-bit programmable timer (prescaler output). Therefore, the pulse width varies according to the prescaler setting. How to set the output pins of the 8-bit programmable timer All pins used by the 8-bit programmable timers are shared with I/O ports, event counter inputs of the 16-bit programmable timers and debug signal outputs. At cold start, all these pins are set for the debug signal outputs (function select bit CFP1[3:0] = "0", port extended function bit CFEX[1:0] = "1"). When using the clock output function of the 8-bit programmable timer, write "0" to the port extended function bit CFEXx and write "1" to the function select bit CFP1x for the corresponding pin. Then, after setting the above, write "1" to the I/O port's I/O control bit IOC1x (D[3:0]) / P1 I/O control register (0x402D6) to set to output mode. In input mode, the pin functions as the 16-bit programmable timer's event counter input and cannot be used to output a clock of the 8-bit programmable timer. At cold start, the register is set to input mode. At hot start, the register retains its status from prior to the reset. S1C33L03 FUNCTION PART EPSON B-III-3-1 III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS Uses of 8-Bit Programmable Timers The down-counter of the 8-bit programmable timer cyclically outputs an underflow signal according to the preset data that is set in the software. This underflow signal is used to generate an interrupt request to the CPU or to control the internal peripheral circuits. In addition, this signal can be output to external devices. Furthermore, each 8-bit programmable timer generates a clock from the underflow signal by dividing it by 2, and the resulting clock is output to a specific internal peripheral circuit. CPU interrupt request/IDMA invocation request Each timer's underflow condition can be used as an interrupt factor to output an interrupt request to the CPU. Therefore, an interrupt can be generated at an interval that is set in the software. This interrupt factor also can be used to invoke IDMA or HSDMA. Clock output to external devices The underflow signal can be output from the chip to the outside. This output can be used to control external devices. The output pins of each timer are described in the preceding section. Control of and clock supply to internal peripheral circuits The following describes the functions controlled by the underflow signal from the 8-bit programmable timer and the internal peripheral circuits that use the timer's output clock. 8-bit programmable timer 0 * DRAM refresh When the BCU has a DRAM directly connected to its external bus, the underflow signal from timer 0 can be used as a DRAM refresh request signal. This enables the intervals of the refresh cycle to be programmed. To use this function, write "1" to the BCU's control bit RPC2 (D9) / Bus control register (0x4812E) to enable the DRAM refresh. * A/D conversion start trigger The A/D converter enables a trigger for starting the A/D conversion to be selected from among four available types. One of these is the underflow signal of the 8-bit programmable timer 0. This makes it possible to perform the A/D conversion at programmable intervals. To use this function, write "10" to the A/D converter control bit TS[1:0] (D[4:3]) / A/D trigger register (0x40242) to select the 8-bit programmable timer 0 as the trigger. 8-bit programmable timer 1 * Oscillation stabilization wait time of the high-speed (OSC3) oscillation circuit When SLEEP mode is cleared by an external interrupt, the high-speed (OSC3) oscillation circuit starts oscillating. To prevent the CPU from being operated erratically by an unstable clock before the oscillation stabilizes, the C33 Core Block enables setting of the waiting time before the CPU starts operating after SLEEP is cleared. Use the 8-bit programmable timer 1 to generate this waiting time. If the 8-bit programmable timer 1 is set so that the timer is actuated when the high-speed (OSC3) oscillation circuit starts oscillating the timer and, after the oscillation stabilization time elapses, an underflow signal is generated, then the CPU can be started up by that underflow signal. To use this function, write "0" to the oscillation circuit control bit 8T1ON (D2) / Clock option register (0x40190) to enable the oscillation stabilization waiting function. B-III-3-2 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS 8-bit programmable timer 2 * Clock supply to the Ch.0 serial interface When using the Ch.0 serial interface in the clock-synchronized master mode or the internal clock-based asynchronous mode, the output clock derived from the underflow signal of the 8-bit programmable timer 2 by dividing it by 2 is supplied to the serial interface as its operating clock. This enables the transfer rate of the serial interface to be programmed. To use this function, write "0" to the serial interface control bit SSCK0 (D2) / Serial I/F Ch.0 control register (0x401E3) to select the internal clock. A-1 8-bit programmable timer 3 * Clock supply to the Ch.1 serial interface When using the Ch.1 serial interface in the clock-synchronized master mode or the internal clock-based asynchronous mode, the output clock derived from the underflow signal of the 8-bit programmable timer 3 by dividing it by 2 is supplied to the serial interface as its operating clock. This enables the transfer rate of the serial interface to be programmed. To use this function, write "0" to the serial interface control bit SSCK1 (D2) / Serial I/F Ch.1 control register (0x401E8) to select the internal clock. 8-bit programmable timer 4 * Clock supply to the Ch.2 serial interface When using the Ch.2 serial interface in the clock-synchronized master mode or the internal clock-based asynchronous mode, the output clock derived from the underflow signal of the 8-bit programmable timer 4 by dividing it by 2 is supplied to the serial interface as its operating clock. This enables the transfer rate of the serial interface to be programmed. To use this function, write "0" to the serial interface control bit SSCK2 (D2) / Serial I/F Ch.2 control register (0x401F3) to select the internal clock. 8-bit programmable timer 5 * Clock supply to the Ch.3 serial interface When using the Ch.3 serial interface in the clock-synchronized master mode or the internal clock-based asynchronous mode, the output clock derived from the underflow signal of the 8-bit programmable timer 5 by dividing it by 2 is supplied to the serial interface as its operating clock. This enables the transfer rate of the serial interface to be programmed. To use this function, write "0" to the serial interface control bit SSCK3 (D2) / Serial I/F Ch.3 control register (0x401F8) to select the internal clock. S1C33L03 FUNCTION PART EPSON B-III-3-3 B-III 8TM III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS Control and Operation of 8-Bit Programmable Timer With the 8-bit programmable timer, the following settings must first be made before it starts counting: 1. Setting the output pin (only when necessary) 2. Setting the input clock 3. Setting the preset data (initial counter value) 4. Setting the interrupt/IDMA/HSDMA Setting of an output pin is necessary only when the output clock of the 8-bit programmable timer is supplied to external devices. For details on how to set the pin, refer to "Output Pins of 8-Bit Programmable Timers". For details on how to set interrupts and DMA, refer to "8-Bit Programmable Timer Interrupts and DMA". Note: The 8-bit programmable timers 0 through 3 all operate in the same way during counting, and the structure of their control registers is also the same. The control bit names are assigned the numerals "0" through "3" to denote the timer numbers. Since all these timers have common functions, timer numbers here are represented it is by "x" unless necessary to specify a timer number. Setting the input clock The 8-bit programmable timer is operated by the prescaler's output clock. The prescaler's division ratio can be selected for each timer. Division ratio select bit Clock control bit Register 8-bit timer 0: P8TS0[2:0] (D[2:0]) P8TON0 (D3) 8-bit timer 0/1 clock control register (0x4014D) 8-bit timer 1: P8TS1[2:0] (D[6:4]) P8TON1 (D7) 8-bit timer 0/1 clock control register (0x4014D) 8-bit timer 2: P8TS2[2:0] (D[2:0]) P8TON2 (D3) 8-bit timer 2/3 clock control register (0x4014E) 8-bit timer 3: P8TS3[2:0] (D[6:4]) P8TON3 (D7) 8-bit timer 2/3 clock control register (0x4014E) 8-bit timer 4: P8TS4[2:0] (D[2:0]) P8TON4 (D3) 8-bit timer 4/5 clock control register (0x40145) 8-bit timer 5: P8TS5[2:0] (D[6:4]) P8TON5 (D7) 8-bit timer 4/5 clock control register (0x40145) Note that the division ratios differ for each timer (see Table 3.2). Furthermore, the prescaler input clock can be directly supplied to the 8-bit timer by writing "1" to the P8TPCKx bit in the 8-bit timer clock select register (0x40146). Timer 0 clock selection: P8TPCK0 (D0) / 8-bit timer clock select register (0x40146) Timer 1 clock selection: P8TPCK1 (D1) / 8-bit timer clock select register (0x40146) Timer 2 clock selection: P8TPCK2 (D2) / 8-bit timer clock select register (0x40146) Timer 3 clock selection: P8TPCK3 (D3) / 8-bit timer clock select register (0x40146) Timer 4 clock selection: P8TPCK4 (D0) / 8-bit timer clock select register (0x40140) Timer 5 clock selection: P8TPCK5 (D1) / 8-bit timer clock select register (0x40140) When using the divided clock selected by P8TSx, set P8TPCKx to "0". Table 3.2 Input Clock Selection Timer P8TSx = 7 P8TSx = 6 P8TSx = 5 P8TSx = 4 P8TSx = 3 P8TSx = 2 P8TSx = 1 P8TSx = 0 P8TPCK = 1 Timer 0 Timer 1 Timer 2 Timer 3 Timer 4 Timer 5 fPSCIN/256 fPSCIN/4096 fPSCIN/4096 fPSCIN/256 fPSCIN/4096 fPSCIN/256 fPSCIN/128 fPSCIN/2048 fPSCIN/2048 fPSCIN/128 fPSCIN/2048 fPSCIN/128 fPSCIN/64 fPSCIN/1024 fPSCIN/64 fPSCIN/64 fPSCIN/64 fPSCIN/64 fPSCIN/32 fPSCIN/512 fPSCIN/32 fPSCIN/32 fPSCIN/32 fPSCIN/32 fPSCIN/16 fPSCIN/256 fPSCIN/16 fPSCIN/16 fPSCIN/16 fPSCIN/16 fPSCIN/8 fPSCIN/128 fPSCIN/8 fPSCIN/8 fPSCIN/8 fPSCIN/8 fPSCIN/4 fPSCIN/64 fPSCIN/4 fPSCIN/4 fPSCIN/4 fPSCIN/4 fPSCIN/2 fPSCIN/32 fPSCIN/2 fPSCIN/2 fPSCIN/2 fPSCIN/2 fPSCIN/1 fPSCIN/1 fPSCIN/1 fPSCIN/1 fPSCIN/1 fPSCIN/1 fPSCIN: Prescaler input clock frequency The selected clock is output from the prescaler to the 8-bit programmable timer by writing "1" to P8TONx. Notes: * The 8-bit programmable timer operates only when the prescaler is operating. (Refer to "Prescaler".) * Do not use a clock that is faster than the CPU operating clock as the 8-bit programmable timer. * When setting an input clock, make sure the 8-bit programmable timer is turned off. B-III-3-4 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS A-1 Setting preset data (initial counter value) Each timer has an 8-bit down-counter and a reload data register. The reload data register RLDx is used to set the initial value of the down-counter of each timer. Timer 0 reload data: RLD0[7:0] (D[7:0]) / 8-bit timer 0 reload data register (0x40161) Timer 1 reload data: RLD1[7:0] (D[7:0]) / 8-bit timer 1 reload data register (0x40165) Timer 2 reload data: RLD2[7:0] (D[7:0]) / 8-bit timer 2 reload data register (0x40169) Timer 3 reload data: RLD3[7:0] (D[7:0]) / 8-bit timer 3 reload data register (0x4016D) Timer 4 reload data: RLD4[7:0] (D[7:0]) / 8-bit timer 4 reload data register (0x40175) Timer 5 reload data: RLD5[7:0] (D[7:0]) / 8-bit timer 5 reload data register (0x40179) The reload data registers can be read and written. At initial reset, the reload data registers are not initialized. The data written to this register is preset in the down-counter, and the counter starts counting down from the preset value. Data is thus preset in the down-counter in the following two cases: 1. When it is preset in the software Presetting in the software is performed using the preset control bit PSETx. When this bit is set to "1", the content of the reload data register is loaded into the down-counter at that point. Timer 0 preset: PSET0 (D1) / 8-bit timer 0 control register (0x40160) Timer 1 preset: PSET1 (D1) / 8-bit timer 1 control register (0x40164) Timer 2 preset: PSET2 (D1) / 8-bit timer 2 control register (0x40168) Timer 3 preset: PSET3 (D1) / 8-bit timer 3 control register (0x4016C) Timer 4 preset: PSET4 (D1) / 8-bit timer 4 control register (0x40174) Timer 5 preset: PSET5 (D1) / 8-bit timer 5 control register (0x40178) 2. When the down-counter underflown during counting Since the reload data is preset in the down-counter upon underflow, its underflow cycle is determined by the value that is set in the reload data register. This underflow signal controls each function described in the preceding section. B-III Before starting the 8-bit programmable timer, set the initial value in the reload data register and use the PSETx bit to preset the data in the down-counter. The underflow cycle is determined by the prescaler setting and the reload data. The relationship between these two parameters is expressed by the following equation: RLDx + 1 Under flow cycle = ------------ [sec.] fPSCIN x pdr fPSCIN: pdr: RLDx: Prescaler input clock frequency [Hz] Prescaler division ratio set by P8TSx Set value of the RLDx register (0 to 255) Timer RUN/STOP control Each timer has a PTRUNx bit to control RUN/STOP. Timer 0 RUN/STOP control: PTRUN0 (D0) / 8-bit timer 0 control register (0x40160) Timer 1 RUN/STOP control: PTRUN1 (D0) / 8-bit timer 1 control register (0x40164) Timer 2 RUN/STOP control: PTRUN2 (D0) / 8-bit timer 2 control register (0x40168) Timer 3 RUN/STOP control: PTRUN3 (D0) / 8-bit timer 3 control register (0x4016C) Timer 4 RUN/STOP control: PTRUN4 (D0) / 8-bit timer 4 control register (0x40174) Timer 5 RUN/STOP control: PTRUN5 (D0) / 8-bit timer 5 control register (0x40178) The timer is initiated to start counting down by writing "1" to PTRUNx. Writing "0" to PTRUNx disables the clock input and causes the timer to stop counting. This RUN/STOP control does not affect the counter data. Even when the timer has stopped counting, the counter retains its count so that it can start counting again from that point. When the terminal count is reached and the counter underflows, the initial value is reloaded from the reload data register into the counter. S1C33L03 FUNCTION PART EPSON B-III-3-5 8TM III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS When both the timer RUN/STOP control bit (PTRUNx) and the timer preset bit (PSETx) are set to "1" at the same time, the timer starts counting after presetting the reload register value into the counter. PTRUNx PSETx RLDx 0x10 0xA6 0xF3 Input clock PTDx7 PTDx6 PTDx5 PTDx4 PTDx3 PTDx2 PTDx1 PTDx0 Timer initial setup Preset Reload and interrupt Figure 3.2 Basic Operation Timing of Counter Reading out counter data The counter data is read out via a PTDx data buffer. The counter data can be read out at any time. Timer 0 data: PTD0[7:0] (D[7:0]) / 8-bit timer 0 counter data register (0x40162) Timer 1 data: PTD1[7:0] (D[7:0]) / 8-bit timer 1 counter data register (0x40166) Timer 2 data: PTD2[7:0] (D[7:0]) / 8-bit timer 2 counter data register (0x4016A) Timer 3 data: PTD3[7:0] (D[7:0]) / 8-bit timer 3 counter data register (0x4016E) Timer 4 data: PTD4[7:0] (D[7:0]) / 8-bit timer 4 counter data register (0x40176) Timer 5 data: PTD5[7:0] (D[7:0]) / 8-bit timer 5 counter data register (0x4017A) B-III-3-6 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS A-1 Control of Clock Output When outputting an underflow signal of the 8-bit programmable timer to external devices, or when supplying a clock generated by the underflow signal to the serial interface, it is necessary to control the clock output of the timer. Timer 0 clock output control: PTOUT0 (D2) / 8-bit timer 0 control register (0x40160) Timer 1 clock output control: PTOUT1 (D2) / 8-bit timer 1 control register (0x40164) Timer 2 clock output control: PTOUT2 (D2) / 8-bit timer 2 control register (0x40168) Timer 3 clock output control: PTOUT3 (D2) / 8-bit timer 3 control register (0x4016C) To output the underflow signal/clock, write "1" to PTOUTx. If an output pin has been set, the underflow signal is output from that pin. The same applies when timer 2 or 3 has been set as the clock source of the serial interface. A clock generated from the underflow signal by dividing it by 2 is output to the serial interface through this control. The clock output is turned off by writing "0" to PTOUTx, and the external output is fixed at "0" and the internal clock output is fixed at "1". Figure 3.3 shows the waveforms of the output signals. Underflow signal Underflow signal/2 PTOUTx External output T8UFx pin Clock output Figure 3.3 8-Bit Programmable Timer Output Waveform The underflow signal's pulse width (duration of the high period) is equal to that of the timer's input clock (prescaler's output). B-III 8-bit timer external output (P10-P13 ports) 1) After an initial reset (cold start), the ports (P10-P13) are set to debug signal putput ports. 2) The port (P10-P13) outputs "0" when it is set to the 8-bit timer output (timer output is off status). 3) The timer output is left as "0" when the timer output is turned on after setting the input clock and timer initial value. 4) When an underflow occurs after starting the timer, the port outputs a pulse with the same width as the 8-bit timer input clock pulse (prescaler's output). S1C33L03 FUNCTION PART EPSON B-III-3-7 8TM III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS 8-Bit Programmable Timer Interrupts and DMA The 8-bit programmable timer has a function to generate an interrupt based on the underflow state of the timer 0 to 3. The timing at which an interrupt is generated is shown in Figure 3.2 in the preceding section. Control registers of the interrupt controller Table 3.3 shows the interrupt controller's control register provided for each timer. Table 3.3 Control Registers of Interrupt Controller Timer Timer 0 Timer 1 Timer 2 Timer 3 Interrupt factor flag F8TU0(D0/0x40285) F8TU1(D1/0x40285) F8TU2(D2/0x40285) F8TU3(D3/0x40285) Interrupt enable register E8TU0(D0/0x40275) E8TU1(D1/0x40275) E8TU2(D2/0x40275) E8TU3(D3/0x40275) Interrupt priority register P8TM[2:0](D[2:0]/0x40269) When the timer underflows, the corresponding interrupt factor flag is set to "1". If the interrupt enable register bit corresponding to that interrupt factor flag has been set to "1", an interrupt request is generated. An interrupt caused by a timer can be disabled by leaving the interrupt enable register bit for that timer set to "0". The interrupt factor flag is set to "1" whenever the timer underflows, regardless of how the interrupt enable register is set (even when it is set to "0"). The interrupt priority register sets an interrupt priority level (0 to 7) for the four timers as one interrupt source. Within 8-bit programmable timers, timer 0 has the highest priority and timer 3 the lowest. An interrupt request to the CPU is accepted on the condition that no other interrupt request of a higher priority has been generated. It is only when the PSR's IE bit = "1" (interrupts enabled) and the set value of the IL is smaller than the timer interrupt level set by the interrupt priority register, that a timer interrupt request is actually accepted by the CPU. For details on these interrupt control registers and device operation when an interrupt has occurred, refer to "ITC (Interrupt Controller)". Intelligent DMA The underflow interrupt factor of the timer 0 to 3 can invoke intelligent DMA (IDMA). This enables memory-to-memory DMA transfers to be performed cyclically. The following shows the IDMA channel numbers set to each timer: IDMA channel Timer 0: 0x13 Timer 1: 0x14 Timer 2: 0x15 Timer 3: 0x16 For IDMA to be invoked, the IDMA request and IDMA enable bits shown in Table 3.4 must be set to "1" in advance. Transfer conditions, etc. must also be set on the IDMA side in advance. Table 3.4 Control Bits for IDMA Transfer Timer IDMA request bit Timer 0 Timer 1 Timer 2 Timer 3 R8TU0(D2/0x40292) R8TU1(D3/0x40292) R8TU2(D4/0x40292) R8TU3(D5/0x40292) IDMA enable bit DE8TU0(D2/0x40296) DE8TU1(D3/0x40296) DE8TU2(D4/0x40296) DE8TU3(D5/0x40296) If the IDMA request and enable bits are set to "1", IDMA is invoked through generation of an interrupt factor. No interrupt request is generated at that point. An interrupt request is generated after the DMA transfer is completed. The registers can also be set so as not to generate an interrupt, with only a DMA transfer performed. For details on IDMA transfers and interrupt control upon completion of IDMA transfer, refer to "IDMA (Intelligent DMA)". B-III-3-8 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS A-1 High-speed DMA The underflow interrupt factor of the timer 0 to 3 can also invoke high-speed DMA (HSDMA). The following shows the HSDMA channel number and trigger set-up bit corresponding to the timer 0 to 3: Table 3.5 HSDMA Trigger Set-up Bits Timer HSDMA channel Timer 0 Timer 1 Timer 2 Timer 3 0 1 2 3 Trigger set-up bits HSD0S[3:0] (D[3:0]) / HSDMA Ch.0/1 trigger set-up register (0x40298) HSD1S[3:0] (D[7:4]) / HSDMA Ch.0/1 trigger set-up register (0x40298) HSD2S[3:0] (D[3:0]) / HSDMA Ch.2/3 trigger set-up register (0x40299) HSD3S[3:0] (D[7:4]) / HSDMA Ch.2/3 trigger set-up register (0x40299) For HSDMA to be invoked, the trigger set-up bits should be set to "0101" in advance. Transfer conditions, etc. must also be set on the HSDMA side. If the 8-bit timer is selected as the HSDMA trigger, the HSDMA channel is invoked through generation of the interrupt factor. For details on HSDMA transfer, refer to "HSDMA (High-Speed DMA)". Trap vectors The trap vector addresses for individual underflow interrupt factors are set by default as shown below: Timer 0 underflow interrupt: Timer 1 underflow interrupt: Timer 2 underflow interrupt: Timer 3 underflow interrupt: 0x0C000D0 0x0C000D4 0x0C000D8 0x0C000DC The base address of the trap table can be changed using the TTBR register (0x48134 to 0x48137). B-III 8TM S1C33L03 FUNCTION PART EPSON B-III-3-9 III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS I/O Memory of 8-Bit Programmable Timers Table 3.6 shows the control bits of the 8-bit programmable timers. For details on the I/O memory of the prescaler used to set a clock, refer to "Prescaler". Table 3.6 Control Bits of 8-Bit Programmable Timer Register name Address Bit 8-bit timer 0 0040160 control register (B) D7-3 D2 D1 D0 Name Function - PTOUT0 PSET0 PTRUN0 reserved 8-bit timer 0 clock output control 8-bit timer 0 preset 8-bit timer 0 Run/Stop control Setting - 1 On 1 Preset 1 Run 0 Off 0 Invalid 0 Stop Init. R/W Remarks - 0 - 0 - 0 when being read. R/W W 0 when being read. R/W 8-bit timer 0 reload data register 0040161 (B) D7 D6 D5 D4 D3 D2 D1 D0 RLD07 RLD06 RLD05 RLD04 RLD03 RLD02 RLD01 RLD00 8-bit timer 0 reload data RLD07 = MSB RLD00 = LSB 0 to 255 X X X X X X X X R/W 8-bit timer 0 counter data register 0040162 (B) D7 D6 D5 D4 D3 D2 D1 D0 PTD07 PTD06 PTD05 PTD04 PTD03 PTD02 PTD01 PTD00 8-bit timer 0 counter data PTD07 = MSB PTD00 = LSB 0 to 255 X X X X X X X X R - PTOUT1 PSET1 PTRUN1 reserved 8-bit timer 1 clock output control 8-bit timer 1 preset 8-bit timer 1 Run/Stop control - - 0 - 0 - 0 when being read. R/W W 0 when being read. R/W 8-bit timer 1 0040164 control register (B) D7-3 D2 D1 D0 1 On 1 Preset 1 Run 0 Off 0 Invalid 0 Stop 8-bit timer 1 reload data register 0040165 (B) D7 D6 D5 D4 D3 D2 D1 D0 RLD17 RLD16 RLD15 RLD14 RLD13 RLD12 RLD11 RLD10 8-bit timer 1 reload data RLD17 = MSB RLD10 = LSB 0 to 255 X X X X X X X X R/W 8-bit timer 1 counter data register 0040166 (B) D7 D6 D5 D4 D3 D2 D1 D0 PTD17 PTD16 PTD15 PTD14 PTD13 PTD12 PTD11 PTD10 8-bit timer 1 counter data PTD17 = MSB PTD10 = LSB 0 to 255 X X X X X X X X R - PTOUT2 PSET2 PTRUN2 reserved 8-bit timer 2 clock output control 8-bit timer 2 preset 8-bit timer 2 Run/Stop control - - 0 - 0 - 0 when being read. R/W W 0 when being read. R/W 8-bit timer 2 0040168 control register (B) D7-3 D2 D1 D0 1 On 1 Preset 1 Run 0 Off 0 Invalid 0 Stop 8-bit timer 2 reload data register 0040169 (B) D7 D6 D5 D4 D3 D2 D1 D0 RLD27 RLD26 RLD25 RLD24 RLD23 RLD22 RLD21 RLD20 8-bit timer 2 reload data RLD27 = MSB RLD20 = LSB 0 to 255 X X X X X X X X R/W 8-bit timer 2 counter data register 004016A (B) D7 D6 D5 D4 D3 D2 D1 D0 PTD27 PTD26 PTD25 PTD24 PTD23 PTD22 PTD21 PTD20 8-bit timer 2 counter data PTD27 = MSB PTD20 = LSB 0 to 255 X X X X X X X X R B-III-3-10 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS A-1 Register name Address Bit Name Function 8-bit timer 3 004016C D7-3 - control register (B) D2 PTOUT3 D1 PSET3 D0 PTRUN3 reserved 8-bit timer 3 clock output control 8-bit timer 3 preset 8-bit timer 3 Run/Stop control 8-bit timer 3 reload data register 004016D (B) D7 D6 D5 D4 D3 D2 D1 D0 RLD37 RLD36 RLD35 RLD34 RLD33 RLD32 RLD31 RLD30 8-bit timer 3 reload data RLD37 = MSB RLD30 = LSB 8-bit timer 3 counter data register 004016E (B) D7 D6 D5 D4 D3 D2 D1 D0 PTD37 PTD36 PTD35 PTD34 PTD33 PTD32 PTD31 PTD30 8-bit timer 3 counter data PTD37 = MSB PTD30 = LSB - PTOUT4 PSET4 PTRUN4 reserved 8-bit timer 4 clock output control 8-bit timer 4 preset 8-bit timer 4 Run/Stop control 8-bit timer 4 0040174 control register (B) D7-3 D2 D1 D0 Setting - Init. R/W - 0 - 0 - 0 when being read. R/W W 0 when being read. R/W 0 to 255 X X X X X X X X R/W 0 to 255 X X X X X X X X R - - 0 - 0 - 0 when being read. R/W W 0 when being read. R/W 1 On 1 Preset 1 Run 0 Off 0 Invalid 0 Stop 1 On 1 Preset 1 Run 0 Off 0 Invalid 0 Stop 8-bit timer 4 reload data register 0040175 (B) D7 D6 D5 D4 D3 D2 D1 D0 RLD47 RLD46 RLD45 RLD44 RLD43 RLD42 RLD41 RLD40 8-bit timer 4 reload data RLD47 = MSB RLD40 = LSB 0 to 255 X X X X X X X X R/W 8-bit timer 4 counter data register 0040176 (B) D7 D6 D5 D4 D3 D2 D1 D0 PTD47 PTD46 PTD45 PTD44 PTD43 PTD42 PTD41 PTD40 8-bit timer 4 counter data PTD47 = MSB PTD40 = LSB 0 to 255 X X X X X X X X R - PTOUT5 PSET5 PTRUN5 reserved 8-bit timer 5 clock output control 8-bit timer 5 preset 8-bit timer 5 Run/Stop control 8-bit timer 5 0040178 control register (B) D7-3 D2 D1 D0 - 1 On 1 Preset 1 Run 0 Off 0 Invalid 0 Stop B-III 8TM - 0 - 0 - 0 when being read. R/W W 0 when being read. R/W 8-bit timer 5 reload data register 0040179 (B) D7 D6 D5 D4 D3 D2 D1 D0 RLD57 RLD56 RLD55 RLD54 RLD53 RLD52 RLD51 RLD50 8-bit timer 5 reload data RLD57 = MSB RLD50 = LSB 0 to 255 X X X X X X X X R/W 8-bit timer 5 counter data register 004017A (B) D7 D6 D5 D4 D3 D2 D1 D0 PTD57 PTD56 PTD55 PTD54 PTD53 PTD52 PTD51 PTD50 8-bit timer 5 counter data PTD57 = MSB PTD50 = LSB 0 to 255 X X X X X X X X R 8-bit timer, 0040269 serial I/F Ch.0 (B) interrupt priority register D7 D6 D5 D4 D3 D2 D1 D0 - PSIO02 PSIO01 PSIO00 - P8TM2 P8TM1 P8TM0 reserved Serial interface Ch.0 interrupt level - 0 to 7 reserved 8-bit timer 0-3 interrupt level - 0 to 7 - X X X - X X X S1C33L03 FUNCTION PART EPSON Remarks - 0 when being read. R/W - 0 when being read. R/W B-III-3-11 III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS Register name Address Bit 8-bit timer 0040275 interrupt (B) enable register D7-4 D3 D2 D1 D0 - E8TU3 E8TU2 E8TU1 E8TU0 Name reserved 8-bit timer 3 underflow 8-bit timer 2 underflow 8-bit timer 1 underflow 8-bit timer 0 underflow Function Setting 8-bit timer 0040285 interrupt factor (B) flag register D7-4 D3 D2 D1 D0 - F8TU3 F8TU2 F8TU1 F8TU0 reserved 8-bit timer 3 underflow 8-bit timer 2 underflow 8-bit timer 1 underflow 8-bit timer 0 underflow - 1 Enabled 0 Disabled - 1 Factor is generated 0 No factor is generated Init. R/W Remarks - 0 0 0 0 - 0 when being read. R/W R/W R/W R/W - X X X X - 0 when being read. R/W R/W R/W R/W 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA request register 0040292 (B) D7 D6 D5 D4 D3 D2 D1 D0 RSTX0 RSRX0 R8TU3 R8TU2 R8TU1 R8TU0 R16TC5 R16TU5 SIF Ch.0 transmit buffer empty SIF Ch.0 receive buffer full 8-bit timer 3 underflow 8-bit timer 2 underflow 8-bit timer 1 underflow 8-bit timer 0 underflow 16-bit timer 5 comparison A 16-bit timer 5 comparison B 1 IDMA request 0 Interrupt request 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA enable register 0040296 (B) D7 D6 D5 D4 D3 D2 D1 D0 DESTX0 DESRX0 DE8TU3 DE8TU2 DE8TU1 DE8TU0 DE16TC5 DE16TU5 SIF Ch.0 transmit buffer empty SIF Ch.0 receive buffer full 8-bit timer 3 underflow 8-bit timer 2 underflow 8-bit timer 1 underflow 8-bit timer 0 underflow 16-bit timer 5 comparison A 16-bit timer 5 comparison B 1 IDMA enabled 0 IDMA disabled 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W P1 function select register 00402D4 (B) D7 D6 - CFP16 reserved P16 function selection - 0 - 0 when being read. R/W D5 CFP15 P15 function selection 0 R/W D4 CFP14 P14 function selection - 1 EXCL5 0 P16 #DMAEND1 1 EXCL4 0 P15 #DMAEND0 1 FOSC1 0 P14 0 D3 CFP13 P13 function selection 0 P13 0 D2 CFP12 P12 function selection 0 P12 0 R/W D1 CFP11 P11 function selection 0 P11 0 R/W D0 CFP10 P10 function selection 1 EXCL3 T8UF3 1 EXCL2 T8UF2 1 EXCL1 T8UF1 1 EXCL0 T8UF0 R/W Extended functions (0x402DF) R/W 0 P10 0 R/W - 0 0 0 0 0 0 0 - R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 1 R/W R/W R/W R/W R/W R/W R/W 1 R/W P1 I/O control register 00402D6 (B) D7 D6 D5 D4 D3 D2 D1 D0 - IOC16 IOC15 IOC14 IOC13 IOC12 IOC11 IOC10 reserved P16 I/O control P15 I/O control P14 I/O control P13 I/O control P12 I/O control P11 I/O control P10 I/O control Port function extension register 00402DF (B) D7 D6 D5 D4 D3 D2 D1 CFEX7 CFEX6 CFEX5 CFEX4 CFEX3 CFEX2 CFEX1 P07 port extended function P06 port extended function P05 port extended function P04 port extended function P31 port extended function P21 port extended function P10, P11, P13 port extended function D0 CFEX0 P12, P14 port extended function B-III-3-12 - EPSON 1 Output 0 Input 1 1 1 1 1 1 1 0 0 0 0 0 0 0 #DMAEND3 #DMAACK3 #DMAEND2 #DMAACK2 #GARD #GAAS DST0 DST1 DPC0 1 DST2 DCLK P07, etc. P06, etc. P05, etc. P04, etc. P31, etc. P21, etc. P10, etc. P11, etc. P13, etc. 0 P12, etc. P14, etc. 0 when being read. This register indicates the values of the I/O control signals of the ports when it is read. (See detailed explanation.) S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS A-1 CFP13-CFP10: P1[3:0] pin function selection (D[3:0]) / P1 function select register (0x402D4) Selects the pin that is used to output a timer underflow signal to external devices. Write "1": Underflow signal output pin Write "0": I/O port pin Read: Valid Select the pin used to output a timer underflow signal to external devices from among P10 through P13 by writing "1" to the corresponding bit, CFP10 through CFP13. P10 through P13 correspond to timers 0 through 3, respectively. If "0" is written to CFP1x, the pin is set for an I/O port. At cold start, CFP1x is set to "0" (I/O port). At hot start, the bit retains its state from prior to the initial reset. IOC13-IOC10: P1[3:0] port I/O control (D[3:0]) / P1 I/O control register (0x402D6) Directs P10 through P13 for input or output and indicates the I/O control signal value of the port. When writing data Write "1": Output mode Write "0": Input mode If a pin chosen from among P10 through P13 is used to output an underflow signal, write "1" to the corresponding I/O control bit to set it to output mode. If the pin is set to input mode, even if its CFP1x is set to "1", it functions as the event counter input pin of a 16-bit programmable timer cannot be used to output a timer underflow signal. When reading data Read "1": I/O control signal (output) Read "0": I/O control signal (input) The I/O control signal value for the port pin is read from this register. When I/O port function is selected using the CFEX and CFP1x registers, the value written to the IOC register is read out as is. When peripheral function is selected, the read value depends on the peripheral circuit status and may not indicate the value written to the IOC register. B-III At cold start, IOC1x is set to "0" (input mode). At hot start, the bit retains its state from prior to the initial reset. CFEX1: P10, P11, P13 port extended function (D1) / Port function extension register (0x402DF) CFEX0: P12, P14 port extended function (D0) / Port function extension register (0x402DF) 8TM Sets whether the function of an I/O-port pin is to be extended. Write "1": Function-extended pin Write "0": I/O-port/peripheral-circuit pin Read: Valid When CFEX[1:0] is set to "1", the P13-P10 ports function as debug signal output ports. When CFEX[1:0] = "0", the CFP1[3:0] bit becomes effective, so the settings of these bits determine whether the P13-P10 ports function as I/O port s or timer underflow signal output ports. At cold start, CFEX[1:0] is set to "1" (function-extended pins). At hot start, CFEX[1:0] retains its state from prior to the initial reset. RLD07-RLD00: Timer 0 reload data (D[7:0]) / 8-bit timer 0 reload data register (0x40161) RLD17-RLD10: Timer 1 reload data (D[7:0]) / 8-bit timer 1 reload data register (0x40165) RLD27-RLD20: Timer 2 reload data (D[7:0]) / 8-bit timer 2 reload data register (0x40169) RLD37-RLD30: Timer 3 reload data (D[7:0]) / 8-bit timer 3 reload data register (0x4016D) RLD47-RLD40: Timer 4 reload data (D[7:0]) / 8-bit timer 4 reload data register (0x40175) RLD57-RLD50: Timer 5 reload data (D[7:0]) / 8-bit timer 5 reload data register (0x40179) Set the initial counter value of each timer. The reload data set in this register is loaded into each counter, and the counter starts counting down beginning with this data, which is used as the initial count. There are two cases in which the reload data is loaded into the counter: when data is preset after "1" is written to PSETx, or when data is automatically reloaded upon counter underflow. At initial reset, RLD is not initialized. S1C33L03 FUNCTION PART EPSON B-III-3-13 III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS PTD07-PTD00: Timer 0 counter data (D[7:0]) / 8-bit timer 0 counter data (0x40162) PTD17-PTD10: Timer 1 counter data (D[7:0]) / 8-bit timer 1 counter data (0x40166) PTD27-PTD20: Timer 2 counter data (D[7:0]) / 8-bit timer 2 counter data (0x4016A) PTD37-PTD30: Timer 3 counter data (D[7:0]) / 8-bit timer 3 counter data (0x4016E) PTD47-PTD40: Timer 4 counter data (D[7:0]) / 8-bit timer 4 counter data (0x40176) PTD57-PTD50: Timer 5 counter data (D[7:0]) / 8-bit timer 5 counter data (0x4017A) The 8-bit programmable timer data can be read out from these bits. These bits function as buffers that retain the counter data when read out, enabling the data to be read out at any time. At initial reset, PTD is not initialized. PSET0: Timer 0 preset (D1) / 8-bit timer 0 control register (0x40160) PSET1: Timer 1 preset (D1) / 8-bit timer 1 control register (0x40164) PSET2: Timer 2 preset (D1) / 8-bit timer 2 control register (0x40168) PSET3: Timer 3 preset (D1) / 8-bit timer 3 control register (0x4016C) PSET4: Timer 4 preset (D1) / 8-bit timer 4 control register (0x40174) PSET5: Timer 5 preset (D1) / 8-bit timer 5 control register (0x40178) Preset the reload data in the counter. Write "1": Preset Write "0": Invalid Read: Always "0" The reload data of RLDx is preset in the counter of timer x by writing "1" to PSETx. If the counter is preset when in a RUN state, the counter starts counting immediately after the reload data is preset. If the counter is preset when in a STOP state, the reload data that has been preset is retained. Writing "0" results in No Operation. Since PSETx is a write-only bit, its content when read is always "0". PTRUN0: Timer 0 RUN/STOP control (D0) / 8-bit timer 0 control register (0x40160) PTRUN1: Timer 1 RUN/STOP control (D0) / 8-bit timer 1 control register (0x40164) PTRUN2: Timer 2 RUN/STOP control (D0) / 8-bit timer 2 control register (0x40168) PTRUN3: Timer 3 RUN/STOP control (D0) / 8-bit timer 3 control register (0x4016C) PTRUN4: Timer 4 RUN/STOP control (D0) / 8-bit timer 4 control register (0x40174) PTRUN5: Timer 5 RUN/STOP control (D0) / 8-bit timer 5 control register (0x40178) Controls the counter's RUN/STOP states. Write "1": RUN Write "0": STOP Read: Valid The counter of each timer starts counting down when "1" written to PTRUNx, and stops counting when "0" is written. While in a STOP state, the counter retains its count until it is preset with reload data or placed in a RUN state. When the state is changed from STOP to RUN, the counter can restart counting beginning with the retained count. At initial reset, PTRUNx is set to "0" (STOP). B-III-3-14 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS A-1 PTOUT0: Timer 0 clock output control register (D2) / 8-bit timer 0 control register (0x40160) PTOUT1: Timer 1 clock output control register (D2) / 8-bit timer 1 control register (0x40164) PTOUT2: Timer 2 clock output control register (D2) / 8-bit timer 2 control register (0x40168) PTOUT3: Timer 3 clock output control register (D2) / 8-bit timer 3 control register (0x4016C) PTOUT4: Timer 4 clock output control register (D2) / 8-bit timer 4 control register (0x40174) PTOUT5: Timer 5 clock output control register (D2) / 8-bit timer 5 control register (0x40178) Controls the clock output of each timer. Write "1": On Write "0": Off Read: Valid The underflow signal of timer x is output from the external output pin set by CFP1x by writing "1" to PTOUTx. When using timer 2 or 3 as the clock source of the serial interface, a clock generated from the underflow signal by dividing it by 2 is output to the corresponding channel of the serial interface. The clock output is turned off by writing "0" to PTOUT, and the external output is fixed at "0" and the internal clock output is fixed at "1". At initial reset, PTOUT is set to "0" (off). P8TM2-P8TM0: 8-bit timer interrupt level (D[2:0]) / 8-bit timer, serial I/F Ch.0 interrupt priority register (0x40269) Set the priority level of the 8-bit programmable timer interrupt in the range of 0 to 7. At initial reset, the content of the P8TM register becomes indeterminate. E8TU0: Timer 0 interrupt enable (D0) / 8-bit timer interrupt enable register (0x40275) E8TU1: Timer 1 interrupt enable (D1) / 8-bit timer interrupt enable register (0x40275) E8TU2: Timer 2 interrupt enable (D2) / 8-bit timer interrupt enable register (0x40275) E8TU3: Timer 3 interrupt enable (D3) / 8-bit timer interrupt enable register (0x40275) Enables or disables generation of an interrupt to the CPU. B-III Write "1": Interrupt enabled Write "0": Interrupt disabled Read: Valid 8TM E8TUx is the interrupt enable bit which controls the interrupt generated by each timer. The interrupt set to "1" by this bit is enabled, and the interrupt set to "0" by this bit is disabled. At initial reset, E8TUx is set to "0" (interrupt disabled). F8TU0: Timer 0 interrupt factor flag (D0) / 8-bit timer interrupt factor flag register (0x40285) F8TU1: Timer 1 interrupt factor flag (D1) / 8-bit timer interrupt factor flag register (0x40285) F8TU2: Timer 2 interrupt factor flag (D2) / 8-bit timer interrupt factor flag register (0x40285) F8TU3: Timer 3 interrupt factor flag (D3) / 8-bit timer interrupt factor flag register (0x40285) Indicates the interrupt generation status of the 8-bit programmable timer. When read Read "1": Interrupt factor has occurred Read "0": No interrupt factor has occurred When written using the reset-only method (default) Write "1": Interrupt factor flag is reset Write "0": Invalid When written using the read/write method Write "1": Interrupt flag is set Write "0": Interrupt flag is reset S1C33L03 FUNCTION PART EPSON B-III-3-15 III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS F8TUx is the interrupt factor flag corresponding to each timer. It is set to "1" when the counter underflows. At this time, if the following conditions are met, an interrupt to the CPU is generated: 1. The corresponding interrupt enable register bit is set to "1". 2. No other interrupt request of a higher priority has been generated. 3. The IE bit of the PSR is set to "1" (interrupts enabled). 4. The value set in the corresponding interrupt priority register is higher than the interrupt level (IL) of the CPU. When using the interrupt factor of the 8-bit programmable timer to request IDMA, note that even when the above conditions are met, no interrupt request to the CPU is generated for the interrupt factor that has occurred. If interrupts are enabled at the setting of IDMA, an interrupt is generated under the above conditions after the data transfer by IDMA is completed. The interrupt factor flag is set to "1" whenever interrupt generation conditions are met, regardless of how the interrupt enable and interrupt priority registers are set. If the next interrupt is to be accepted after an interrupt has occurred, it is necessary that the interrupt factor flag be reset, and that the PSR be set again (by setting the IE bit to "1" after setting the IL to a value lower than the level indicated by the interrupt priority register, or by executing the reti instruction). The interrupt factor flag can be reset only by writing to it in the software. Note that if the PSR is set again to accept interrupts generated (or if the reti instruction is executed) without resetting the interrupt factor flag, the same interrupt occurs again. Note also that the value to be written to reset the flag is "1" when the reset-only method (RSTONLY = "1") is used, and "0" when the read/write method (RSTONLY = "0") is used. At initial reset, the content of F8TUx becomes indeterminate, so be sure to reset it in the software. R8TU0: Timer 0 IDMA request (D2) / 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA request register (0x40292) R8TU1: Timer 1 IDMA request (D3) / 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA request register (0x40292) R8TU2: Timer 2 IDMA request (D4) / 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA request register (0x40292) R8TU3: Timer 3 IDMA request (D5) / 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA request register (0x40292) Specifies whether IDMA is to be invoked at the occurrence of an interrupt factor. When using the set-only method (default) Write "1": IDMA request Write "0": Not changed Read: Valid When using the read/write method Write "1": IDMA request Write "0": Interrupt request Read: Valid R8TUx is the IDMA request bit for each timer. If this bit is set to "1", IDMA can be invoked when an interrupt factor occurs, and thus programmed data transfers are performed. If the bit is set to "0", normal interrupt processing is performed and IDMA is not invoked. For details on IDMA, refer to "IDMA (Intelligent DMA)". At initial reset, R8TUx is set to "0" (interrupt request). B-III-3-16 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS A-1 DE8TU0: Timer 0 IDMA enable (D2) / 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA enable register (0x40296) DE8TU1: Timer 1 IDMA enable (D3) / 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA enable register (0x40296) DE8TU2: Timer 2 IDMA enable (D4) / 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA enable register (0x40296) DE8TU3: Timer 3 IDMA enable (D5) / 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA enable register (0x40296) Enables IDMA transfer by means of an interrupt factor. When using the set-only method (default) Write "1": IDMA enabled Write "0": Not changed Read: Valid When using the read/write method Write "1": IDMA enabled Write "0": IDMA disabled Read: Valid If DE8TUx is set to "1", the IDMA request by the interrupt factor is enabled. If the register bit is set to "0", the IDMA request is disabled. After an initial reset, DE8TUx is set to "0" (IDMA disabled). Programming Notes (1) The 8-bit programmable timer operates only when the prescaler is operating. (2) Do not use a clock that is faster than the CPU operating clock for the 8-bit programmable timer. (3) When setting an input clock, make sure the 8-bit programmable timer is turned off. (4) Since the underflow interrupt condition and the timer output status are undefined after an initial reset, the counter initial value should be set to the 8-bit timer before resetting the interrupt factor flag or turning the timer output on. B-III (5) After an initial reset, the interrupt factor flag (F8TUx) becomes indeterminate. To prevent generation of an unwanted interrupt or IDMA request, be sure to reset this flag in the software. (6) To prevent another interrupt from being generated again by the same factor after an interrupt has occurred, be sure to reset the interrupt factor flag (F8TUx) before setting the PSR again or executing the reti instruction. S1C33L03 FUNCTION PART EPSON B-III-3-17 8TM III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS THIS PAGE IS BLANK. B-III-3-18 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS A-1 III-4 16-BIT PROGRAMMABLE TIMERS Configuration of 16-Bit Programmable Timer The Peripheral Block contains six systems of 16-bit programmable timers (timers 0 to 5). They also have an event counter function using an I/O port pin. Note: On the following pages, each timer is identified as timer x (x = 0 to 5). The functions and control register structures of 16-bit programmable timers 0 to 5 are the same. Control bit names are assigned numerals "0" to "5" denoting timer numbers. Since explanations are common to all timers, timer numbers are represented by "x" unless it is necessary to specify a timer number. Figure 4.1 shows the structure of one channel of the 16-bit programmable timer. Timer x Comparison register A buffer (CRBxA) Prescaler INCLx 16-bit comparison data register A (CRxA) Clock select circuit EXCLx External clock Comparison match A Comparator 16-bit up counter (TCx) TMx Clock output Control circuit Comparison A interrupt Comparison B interrupt Interrupt controller Comparison match B Comparator Data bus Clock generator 16-bit comparison data register B (CRxB) Comparison A B-III Comparison B Comparison register B buffer (CRBxB) Timer x control register 16TM Figure 4.1 Structure of 16-Bit Programmable Timer In each timer, a 16-bit up-counter (TCx), as well as two 16-bit comparison data registers (CRxA, CRxB) and their buffers (CRBxA, CRBxB), are provided. The 16-bit counter can be reset to "0" by software and counts up using the prescaler output clock or an external signal input from the I/O port. The counter value can be read by software. The comparison data registers A and B are used to store the data to be compared with the content of the up-counter. This register can be directly read and written. Furthermore, comparison data can be set via the comparison register buffer. In this case, the set value is loaded to the comparison data register when the counter is reset by the comparison match B signal or software (by writing "1" to PRESETx bit). The software can select whether comparison data is written to the comparison data register or the buffer. When the counter value matches to the content of each comparison data register, the comparator outputs a signal that controls the interrupt and the output signal. Thus the registers allow interrupt generating intervals and the timer's output clock frequency and duty ratio to be programmed. S1C33L03 FUNCTION PART EPSON B-III-4-1 III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS I/O Pins of 16-Bit Programmable Timers Table 4.1 shows the input/output pins used for the 16-bit programmable timers. Table 4.1 I/O Pins of 16-Bit Programmable Timer Pin name P10/EXCL0/ T8UF0/DST0 P11/EXCL1/ T8UF1/DST1 P12/EXCL2/ T8UF2/DST2 P13/EXCL3/ T8UF3/DPCO P15/EXCL4 /#DMAEND0 P16/EXCL5 /#DMAEND1 P22/TM0 P23/TM1 P24/TM2 P25/TM3 P26/TM4 P27/TM5 I/O Function Function select bit I/O I/O port / 16-bit timer 0 event counter input (I) / 8-bit timer 0 output (O) / DST0 output (Ex) I/O I/O port / 16-bit timer 1 event counter input (I) / 8-bit timer 1 output (O) / DST1 output (Ex) I/O I/O port / 16-bit timer 2 event counter input (I) / 8-bit timer 2 output (O) / DST2 output (Ex) I/O I/O port / 16-bit timer 3 event counter input (I) / 8-bit timer 3 output (O) / DPCO output (Ex) I/O I/O port / 16-bit timer 4 event counter input (I) / High-speed DMA Ch.0 end signal output (O) I/O I/O port / 16-bit timer 5 event counter input (I) / High-speed DMA Ch.1 end signal output (O) I/O I/O port / 16-bit timer 0 output I/O I/O port / 16-bit timer 1 output I/O I/O port / 16-bit timer 2 output I/O I/O port / 16-bit timer 3 output I/O I/O port / 16-bit timer 4 output I/O I/O port / 16-bit timer 5 output CFP10(D0)/P1 function select register(0x402D4) CFEX1(D1)/Port function extension register(0x402DF) CFP11(D1)/P1 function select register(0x402D4) CFEX1(D1)/Port function extension register(0x402DF) CFP12(D2)/P1 function select register(0x402D4) CFEX0(D0)/Port function extension register(0x402DF) CFP13(D3)/P1 function select register(0x402D4) CFEX1(D1)/Port function extension register(0x402DF) CFP15(D5)/P1 function select register(0x402D4) CFP16(D6)/P1 function select register(0x402D4) CFP22(D2)/P2 function select register(0x402D8) CFP23(D3)/P2 function select register(0x402D8) CFP24(D4)/P2 function select register(0x402D8) CFP25(D5)/P2 function select register(0x402D8) CFP26(D6)/P2 function select register(0x402D8) CFP27(D7)/P2 function select register(0x402D8) (I): Input mode, (O): Output mode, (Ex): Extended function TMx (output pin of the 16-bit programmable timer) This pin outputs a clock generated by the timer x. EXCLx (event counter input pin) When using the timer x as an event counter, input count pulses from an external source to this pin. How to set the input/output pins of 16-bit programmable timers All clock output pins used by the 16-bit programmable timers are shared with I/O ports. At cold start, all these pins are set for the I/O port pins P2x (function select bit CFP2x = "0"), and go into high-impedance. When using the clock output function of the 16-bit programmable timer, select the desired timer and write "1" to the function select bit CFP2x for the corresponding pin. At hot start, these pins retain their status before from prior to the reset. All event-counter input pins are also shared with I/O-ports. At cold start, the EXCL[3:0] pins are set for debug signal output pins (function extension bit CFEX[1:0] = "1") and the EXCL[5:4] pins are set for I/Oport pins P1[5:4] (function select bit CFP1[5:4] = "0"). When using the event counter function, select the desired timer and write "1" to the function select bit CFP1x and write "0" to the function select bit CFEXx for the corresponding pin. Note that these pins are also shared with output pins for the 8-bit programmer timers, etc. When the input/output pins are set in input mode, they function as event counter inputs. Therefore, it is necessary to set the I/O port's I/O control bit IOC1x to "0" in advance. At cold start, these pins are set in input mode. At hot start, they retain their status from prior to the reset. B-III-4-2 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS A-1 Uses of 16-Bit Programmable Timers The up-counters of the 16-bit programmable timer cyclically output a comparison-match signal in accordance with the comparison data that are set in the software. This signal is used to generate an interrupt request to the CPU or control the internal peripheral circuits. A clock generated from the signal can also be output to external devices. CPU interrupt request/IDMA invocation request Each timer's comparison match (matching of counter and comparison data) can be used as an interrupt factor to generate an interrupt request to the CPU. Therefore, an interrupt can be generated at an interval that is set in the software. Furthermore, this interrupt factor can also be used to invoke IDMA or HSDMA. Clock output to external devices A clock generated from the comparison-match signal can be output from the chip to the outside. The clock cycle is determined by comparison data B, and the duty ratio is determined by comparison data A. This output can be used to control external devices. The output pins of each timer are described in the preceding section. A/D converter start trigger The A/D converter allows a trigger to start the A/D conversion to be selected from among four available types. One is the comparison-match B of the 16-bit programmable timer 0. This makes it possible to perform the A/D conversion at programmable intervals. To use this function, write "01" to the A/D converter control TS[1:0] (D[4:3]) / A/D trigger register (0x40242) to select the 16-bit programmable timer 0 as the trigger. Watchdog timer The 16-bit programmable timer 0 can be used as a watchdog timer to monitor CPU crash. In this case, the comparison-match B of this timer serves as an NMI request signal to the CPU. To use this function, write "1" to the watchdog timer control bit EWD (D1) / Watchdog timer enable register (0x40171) to enable the NMI. For details on how to control the watchdog timer, refer to "Watchdog Timer". B-III 16TM S1C33L03 FUNCTION PART EPSON B-III-4-3 III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS Control and Operation of 16-Bit Programmable Timer The following settings must first be made before the 16-bit programmable timer starts counting: 1. Setting pins for input/output (only when necessary) 2. Setting input clock 3. Selecting comparison data register/buffer 4. Setting clock output conditions (signal active level, fine mode) 5. Setting comparison data 6. Setting interrupt/IDMA For details on how to set clock output conditions and interrupts and DMA, refer to "Controlling Clock Output" and "16-Bit Programmable Timer Interrupts and DMA". Setting pin for input/output The pin must be set for output for the output clock of the 16-bit programmable timer to be fed to external devices. The pin for input must be set for the 16-bit programmable timer to be used as an event counter that counts external clock pulses. For details on how to set the pin, refer to "I/O Pins of 16-Bit Programmable Timers". Setting the input clock The count clock for each timer can be selected from between an internal clock and an external clock. Use the following control bits to select the input clock: Timer 0 input clock selection: CKSL0 (D3) / 16-bit timer 0 control register (0x48186) Timer 1 input clock selection: CKSL1 (D3) / 16-bit timer 1 control register (0x4818E) Timer 2 input clock selection: CKSL2 (D3) / 16-bit timer 2 control register (0x48196) Timer 3 input clock selection: CKSL3 (D3) / 16-bit timer 3 control register (0x4819E) Timer 4 input clock selection: CKSL4 (D3) / 16-bit timer 4 control register (0x481A6) Timer 5 input clock selection: CKSL5 (D3) / 16-bit timer 5 control register (0x481AE) An external clock is selected by writing "1" to CKSLx, and the internal clock is selected by writing "0". At initial reset, CKSLx is set for the internal clock. An external clock can be used for the timer for which the pin is set for input. * Internal clock When the internal clock is selected as a timer, the timer is operated by the prescaler output clock. The prescaler division ratio can be selected for each timer. Table 4.2 Setting the Internal Clock Timer Timer 0 Timer 1 Timer 2 Timer 3 Timer 4 Timer 5 Control register 16-bit timer 0 clock control register (0x40147) 16-bit timer 1 clock control register (0x40148) 16-bit timer 2 clock control register (0x40149) 16-bit timer 3 clock control register (0x4014A) 16-bit timer 4 clock control register (0x4014B) 16-bit timer 5 clock control register (0x4014C) Division ratio select bit Clock control bit P16TS0[2:0] (D2:0]) P16TS1[2:0] (D2:0]) P16TS2[2:0] (D2:0]) P16TS3[2:0] (D2:0]) P16TS4[2:0] (D2:0]) P16TS5[2:0] (D2:0]) P16TON0 (D3) P16TON1 (D3) P16TON2 (D3) P16TON3 (D3) P16TON4 (D3) P16TON5 (D3) The division ratio can be selected from among eight types as shown in Table 4.3. Table 4.3 Input Clock Selection P16TS = 7 P16TS = 6 fPSCIN/4096 fPSCIN/1024 P16TS = 5 P16TS = 4 P16TS = 3 fPSCIN/256 fPSCIN/64 fPSCIN/16 P16TS = 2 P16TS = 1 P16TS = 0 fPSCIN/4 fPSCIN/2 fPSCIN/1 fPSCIN: Prescaler input clock frequency The selected clock is output from the prescaler to the 16-bit programmable timer by writing "1" to P16TONx. Notes: * When the internal clock is used, the 16-bit programmable timer operates only when the prescaler is operating (refer to "Prescaler"). * When setting an input clock, make sure the 16-bit programmable timer is turned off. B-III-4-4 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS * External clock When using the timer as an event counter by supplying clock pulses from an external source, make sure the event cycle is at least the CPU operating clock period. A-1 Selecting comparison data register/buffer The comparison data registers A and B are used to store the data to be compared with the content of the upcounter. This register can be directly read and written. Furthermore, comparison data can be set via the comparison register buffer. In this case, the set value is loaded to the comparison data register when the counter is reset by the comparison match B signal or software (by writing "1" to PRESETx bit). Select whether comparison data is written to the comparison data register or the buffer using the following control bits: Timer 0 comparison register buffer enable: SELCRB0 (D5) / 16-bit timer 0 control register (0x48186) Timer 1 comparison register buffer enable: SELCRB1 (D5) / 16-bit timer 1 control register (0x4818E) Timer 2 comparison register buffer enable: SELCRB2 (D5) / 16-bit timer 2 control register (0x48196) Timer 3 comparison register buffer enable: SELCRB3 (D5) / 16-bit timer 3 control register (0x4819E) Timer 4 comparison register buffer enable: SELCRB4 (D5) / 16-bit timer 4 control register (0x481A6) Timer 5 comparison register buffer enable: SELCRB5 (D5) / 16-bit timer 5 control register (0x481AE) When "1" is written to SELCRBx, the comparison register buffer is selected and when "0" is written, the comparison data register is selected. At initial reset, the comparison data register is selected. Setting comparison data The programmable timer contains two data comparators that allows the count data to be compared with given values. The following registers are used to set these values. Timer 0 comparison data A: CR0A[15:0] (D[F:0]) / 16-bit timer 0 comparison data A set-up register (0x48180) Timer 0 comparison data B: CR0B[15:0] (D[F:0]) / 16-bit timer 0 comparison data B set-up register (0x48182) Timer 1 comparison data A: CR1A[15:0] (D[F:0]) / 16-bit timer 1 comparison data A set-up register (0x48188) Timer 1 comparison data B: CR1B[15:0] (D[F:0]) / 16-bit timer 1 comparison data B set-up register (0x4818A) Timer 2 comparison data A: CR2A[15:0] (D[F:0]) / 16-bit timer 2 comparison data A set-up register (0x48190) Timer 2 comparison data B: CR2B[15:0] (D[F:0]) / 16-bit timer 2 comparison data B set-up register (0x48192) Timer 3 comparison data A: CR3A[15:0] (D[F:0]) / 16-bit timer 3 comparison data A set-up register (0x48198) Timer 3 comparison data B: CR3B[15:0] (D[F:0]) / 16-bit timer 3 comparison data B set-up register (0x4819A) Timer 4 comparison data A: CR4A[15:0] (D[F:0]) / 16-bit timer 4 comparison data A set-up register (0x481A0) Timer 4 comparison data B: CR4B[15:0] (D[F:0]) / 16-bit timer 4 comparison data B set-up register (0x481A2) Timer 5 comparison data A: CR5A[15:0] (D[F:0]) / 16-bit timer 5 comparison data A set-up register (0x481A8) Timer 5 comparison data B: CR5B[15:0] (D[F:0]) / 16-bit timer 5 comparison data B set-up register (0x481AA) When SELCRBx is set to "0", these registers allow direct reading/writing from/to the comparison data register. When SELCRBx is set to "1", these registers are used to read/write from/to the comparison register buffer. The content of the buffer is loaded to the comparison data register when the counter is reset. At initial reset, the comparison data registers/buffers are not initialized. The programmable timer compares the comparison data register and count data and, when the two values are equal, generates a comparison match signal. This comparison match signal controls the clock output (TMx signal) to external devices, in addition to generating an interrupt. The comparison data B is also used to reset the counter. S1C33L03 FUNCTION PART EPSON B-III-4-5 B-III 16TM III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS Resetting the counter Each timer includes the PRESETx bit to reset the counter. Timer 0 reset: PRESET0 (D1) / 16-bit timer 0 control register (0x48186) Timer 1 reset: PRESET1 (D1) / 16-bit timer 1 control register (0x4818E) Timer 2 reset: PRESET2 (D1) / 16-bit timer 2 control register (0x48196) Timer 3 reset: PRESET3 (D1) / 16-bit timer 3 control register (0x4819E) Timer 4 reset: PRESET4 (D1) / 16-bit timer 4 control register (0x481A6) Timer 5 reset: PRESET5 (D1) / 16-bit timer 5 control register (0x481AE) Normally, reset the counter before starting count-up by writing "1" to this control bit. After the counter starts counting, it will be reset by comparison match B. Timer RUN/STOP control Each timer includes the PRUNx bit to control RUN/STOP. Timer 0 RUN/STOP control: PRUN0 (D0) / 16-bit timer 0 control register (0x48186) Timer 1 RUN/STOP control: PRUN1 (D0) / 16-bit timer 1 control register (0x4818E) Timer 2 RUN/STOP control: PRUN2 (D0) / 16-bit timer 2 control register (0x48196) Timer 3 RUN/STOP control: PRUN3 (D0) / 16-bit timer 3 control register (0x4819E) Timer 4 RUN/STOP control: PRUN4 (D0) / 16-bit timer 4 control register (0x481A6) Timer 5 RUN/STOP control: PRUN5 (D0) / 16-bit timer 5 control register (0x481AE) The timer starts counting when "1" is written to PRUNx. The clock input is disabled and the timer stops counting when "0" is written to PRUNx. This RUN/STOP control does not affect the counter data. Even when the timer has stopped counting, the counter retains its count so that the timer can start counting again from that point. If the count of the counter matches the set value of the comparison data register during count-up, the timer generates a comparison match interrupt. When the counter matches comparison data B, an interrupt is generated and the counter is reset. At the same time, the values set in the compare register buffer are loaded to the compare data register if SELCRBx is set to "1". The counter continues counting up regardless of which interrupt has occurred. In the case of a comparison B interrupt, the counter starts counting beginning with 0. When both the timer RUN/STOP control bit (PRUNx) and the timer reset bit (PRESETx) are set to "1" at the same time, the timer starts counting after resetting the counter. PRUNx PRESETx CRxA 0x2 CRxB 0x5 Input clock 0 TCx Reset 1 2 3 4 5 Comparison A interrupt 0 1 2 3 Reset and Comparison A Comparison B interrupt interrupt Figure 4.2 Basic Operation Timing of Counter 4 5 0 1 Reset and Comparison B interrupt Reading counter data The counter data can be read out from the following addresses shown below at any time: Timer 0 counter data: TC0[15:0] (D[F:0]) / 16-bit timer 0 counter data register (0x48184) Timer 1 counter data: TC1[15:0] (D[F:0]) / 16-bit timer 1 counter data register (0x4818C) Timer 2 counter data: TC2[15:0] (D[F:0]) / 16-bit timer 2 counter data register (0x48194) Timer 3 counter data: TC3[15:0] (D[F:0]) / 16-bit timer 3 counter data register (0x4819C) Timer 4 counter data: TC4[15:0] (D[F:0]) / 16-bit timer 4 counter data register (0x481A4) Timer 5 counter data: TC5[15:0] (D[F:0]) / 16-bit timer 5 counter data register (0x481AC) B-III-4-6 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS A-1 Controlling Clock Output The timers can generate a TMx signal using the comparison match signals from the counter. Setting the signal active level By default, an active high signal (normal low) is generated. This logic can be inverted using the OUTINVx bit. When "1" is written to the OUTINVx bit, the timer generates an active low (normal high) signal. Timer 0 clock output inversion: OUTINV0 (D4) / 16-bit timer 0 control register (0x48186) Timer 1 clock output inversion: OUTINV1 (D4) / 16-bit timer 1 control register (0x4818E) Timer 2 clock output inversion: OUTINV2 (D4) / 16-bit timer 2 control register (0x48196) Timer 3 clock output inversion: OUTINV3 (D4) / 16-bit timer 3 control register (0x4819E) Timer 4 clock output inversion: OUTINV4 (D4) / 16-bit timer 4 control register (0x481A6) Timer 5 clock output inversion: OUTINV5 (D4) / 16-bit timer 5 control register (0x481AE) See Figure 4.3 for the waveforms. Setting the output port The TMx signal generated here can be output from the clock output pins (see Table 4.1), enabling a programmable clock to be supplied to external devices. After a cold start, the output pins are set for the I/O ports and set in input mode. The pins go into highimpedance status. When the pin function is switched to the timer output, the pin goes low if OUTINVx is set to "0" or goes high if OUTINVx is set to "1". Starting clock output To output the TMx clock, write "1" to the clock output control bit PTMx. Clock output is stopped by writing "0" to PTMx and goes to the off level according to the OUTINVx setting (low when OUTINVx = "0" or high when OUTINVx = "1"). Timer 0 clock output control: PTM0 (D2) / 16-bit timer 0 control register (0x48186) Timer 1 clock output control: PTM1 (D2) / 16-bit timer 1 control register (0x4818E) Timer 2 clock output control: PTM2 (D2) / 16-bit timer 2 control register (0x48196) Timer 3 clock output control: PTM3 (D2) / 16-bit timer 3 control register (0x4819E) Timer 4 clock output control: PTM4 (D2) / 16-bit timer 4 control register (0x481A6) Timer 5 clock output control: PTM5 (D2) / 16-bit timer 5 control register (0x481AE) Figure 4.3 shows the waveform of the output signal. Input clock PRUNx CRxA 3 CRxB 5 Counter value 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 Comparison match A signal Comparison match B signal PTMx TMx output (when OUTINVx = "0") TMx output (when OUTINVx = "1") Figure 4.3 Waveform of 16-Bit Programmable Timer Output S1C33L03 FUNCTION PART EPSON B-III-4-7 B-III 16TM III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS When OUTINVx = "0" (active high): The timer outputs a low level until the counter becomes equal to the comparison data A set in the CRxA register. When the counter is incremented to the next value from the comparison data A, the output pin goes high and a comparison A interrupt occurs. When the counter becomes equal to the comparison data B set in the CRxB register, the counter is reset and the output pin goes low. At the same time a comparison B interrupt occurs. When OUTINVx = "1" (active low): The timer outputs a high level until the counter becomes equal to the comparison data A set in the CRxA register. When the counter is incremented to the next value from the comparison data A, the output pin goes low and a comparison A interrupt occurs. When the counter becomes equal to the comparison data B set in the CRxB register, the counter is reset and the output pin goes high. At the same time a comparison B interrupt occurs. Setting clock output fine mode By default (after an initial reset), the clock output signal changes at the rising edge of the input clock when CRxA[15:0] becomes equal to TCx[15:0]. In fine mode, the output signal changes according to CRxA[0] when CRxA[15:1] becomes equal to TCx[14:0]. When CRxA[0] is "0", the output signal changes at the rising edge of the input clock. When CRxA[0] is "1", the output signal changes at the falling edge of the input clock a half cycle from the default setting. Example) CRxA = 3, CRxB = 5 Input clock Counter value 0 1 2 3 4 5 0 1 2 3 4 5 0 1 Comparison match A signal Comparison match B signal TMx output (when OUTINVx = "0") TMx output (when OUTINVx = "1") Figure 4.4 Clock Output in Fine Mode As shown in the figure above, in fine mode the output clock duty ratio can be adjusted in the half cycle of the input clock. However, when the CRxA value is "0", the timer outputs a pulse with a 1-cycle width as the input clock, the same as the default setting. In fine mode, the maximum value of CRxB is 215 - 1 = 32,767 and the range of CRxA that can be set is 0 to (2 x CRxB - 1). The fine mode is set by the following registers: Timer 0 fine mode selection: SELFM0 (D6) / 16-bit timer 0 control register (0x48186) Timer 1 fine mode selection: SELFM1 (D6) / 16-bit timer 1 control register (0x4818E) Timer 2 fine mode selection: SELFM2 (D6) / 16-bit timer 2 control register (0x48196) Timer 3 fine mode selection: SELFM3 (D6) / 16-bit timer 3 control register (0x4819E) Timer 4 fine mode selection: SELFM4 (D6) / 16-bit timer 4 control register (0x481A6) Timer 5 fine mode selection: SELFM5 (D6) / 16-bit timer 5 control register (0x481AE) When "1" is written to the SELFMx bit, fine mode is set. At initial reset, the fine mode is disabled. Precautions 1) If a same value is set to the comparison data A and B registers, a hazard may be generated in the output signal. Therefore, do not set the comparison registers as A = B. There is no problem when the interrupt function only is used. 2) When using the output clock, set the comparison data registers as A 0 and B 1. The minimum settings are A = 0 and B = 1. In this case, the timer output clock cycle is the input clock x 1/2. 3) When the comparison data registers are set as A > B, no comparison A signal is generated. In this case, the output signal is fixed at the off level. B-III-4-8 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS A-1 16-Bit Programmable Timer Interrupts and DMA The 16-bit programmable timer has a function for generating an interrupt using the comparison match A and B states. The timing at which an interrupt is generated is shown in Figure 4.2 in the preceding section. Control registers of the interrupt controller Table 4.4 shows the control registers of the interrupt controller provided for each timer. Table 4.4 Control Registers of Interrupt Controller Interrupt factor Interrupt factor flag Interrupt enable register Interrupt priority register Timer 0 comparison A Timer 0 comparison B Timer 1 comparison A Timer 1 comparison B Timer 2 comparison A Timer 2 comparison B Timer 3 comparison A Timer 3 comparison B Timer 4 comparison A Timer 4 comparison B Timer 5 comparison A Timer 5 comparison B F16TC0 (D3/0x40282) F16TU0 (D2/0x40282) F16TC1 (D7/0x40282) F16TU1 (D6/0x40282) F16TC2 (D3/0x40283) F16TU2 (D2/0x40283) F16TC3 (D7/0x40283) F16TU3 (D6/0x40283) F16TC4 (D3/0x40284) F16TU4 (D2/0x40284) F16TC5 (D7/0x40284) F16TU5 (D6/0x40284) E16TC0 (D3/0x40272) E16TU0 (D2/0x40272) E16TC1 (D7/0x40272) E16TU1 (D6/0x40272) E16TC2 (D3/0x40273) E16TU2 (D2/0x40273) E16TC3 (D7/0x40273) E16TU3 (D6/0x40273) E16TC4 (D3/0x40274) E16TU4 (D2/0x40274) E16TC5 (D7/0x40274) E16TU5 (D6/0x40274) P16T0[2:0] (D[2:0]/0x40266) P16T1[2:0] (D[6:4]/0x40266) P16T2[2:0] (D[2:0]/0x40267) P16T3[2:0] (D[6:4]/0x40267) P16T4[2:0] (D[2:0]/0x40268) P16T5[2:0] (D[6:4]/0x40268) When a comparison match state occurs in the timer, the corresponding interrupt factor flag is set to "1". If the interrupt enable register bit corresponding to that interrupt factor flag has been set to "1", an interrupt request is generated. An interrupt caused by a timer can be disabled by leaving the interrupt enable register bit for that timer set to "0". The interrupt factor flag is always set to "1" by the timer's comparison match state, regardless of how the interrupt enable register is set (even when set to "0"). The interrupt priority register sets an interrupt priority level (0 to 7) for each timer. Priorities within a timer block are such that timers of smaller numbers have a higher priority. Priorities between interrupt types are such that the comparison B interrupt has priority over the comparison A interrupt. An interrupt request to the CPU is accepted only when no other interrupt request of a higher priority has been generated. It is only when the PSR's IE bit = "1" (interrupts enabled) and the set value of the IL is smaller than the timer interrupt level set by the interrupt priority register, that a timer interrupt request is actually accepted by the CPU. For details on these interrupt control registers, as well as the device operation when an interrupt has occurred, refer to "ITC (Interrupt Controller)". Intelligent DMA The interrupt factor of each timer can also invoke intelligent DMA (IDMA). This allows memory-to-memory DMA transfers to be performed cyclically. The following shows the IDMA channel numbers set for each interrupt factor of timer: IDMA Ch. IDMA Ch. Timer 0 comparison B: 0x07 Timer 0 comparison A: 0x08 Timer 1 comparison B: 0x09 Timer 1 comparison A: 0x0A Timer 2 comparison B: 0x0B Timer 2 comparison A: 0x0C Timer 3 comparison B: 0x0D Timer 3 comparison A: 0x0E Timer 4 comparison B: 0x0F Timer 4 comparison A: 0x10 Timer 5 comparison B: 0x11 Timer 5 comparison A: 0x12 S1C33L03 FUNCTION PART EPSON B-III-4-9 B-III 16TM III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS For IDMA to be invoked, the IDMA request and IDMA enable bits shown in Table 4.5 must be set to "1" in advance. Transfer conditions, etc. must also be set on the IDMA side in advance. Table 4.5 Control Bits for IDMA Transfer Interrupt factor Timer 0 comparison A Timer 0 comparison B Timer 1 comparison A Timer 1 comparison B Timer 2 comparison A Timer 2 comparison B Timer 3 comparison A Timer 3 comparison B Timer 4 comparison A Timer 4 comparison B Timer 5 comparison A Timer 5 comparison B IDMA request bit IDMA enable bit R16TC0(D7/0x40290) R16TU0(D6/0x40290) R16TC1(D1/0x40291) R16TU1(D0/0x40291) R16TC2(D3/0x40291) R16TU2(D2/0x40291) R16TC3(D5/0x40291) R16TU3(D4/0x40291) R16TC4(D7/0x40291) R16TU4(D6/0x40291) R16TC5(D1/0x40292) R16TU5(D0/0x40292) DE16TC0(D7/0x40294) DE16TU0(D6/0x40294) DE16TC1(D1/0x40295) DE16TU1(D0/0x40295) DE16TC2(D3/0x40295) DE16TU2(D2/0x40295) DE16TC3(D5/0x40295) DE16TU3(D4/0x40295) DE16TC4(D7/0x40295) DE16TU4(D6/0x40295) DE16TC5(D1/0x40296) DE16TU5(D0/0x40296) If the IDMA request and enable bits are set to "1", IDMA is invoked through generation of an interrupt factor. No interrupt request is generated at that point. An interrupt request is generated after the DMA transfer is completed. The registers can also be set so as not to generate an interrupt, with only a DMA transfer performed. For details on IDMA transfers and interrupt control upon completion of IDMA transfer, refer to "IDMA (Intelligent DMA)". High-speed DMA The interrupt factor of each timer can also invoke high-speed DMA (HSDMA). The following shows the HSDMA channel number and trigger set-up bit corresponding to each timer: Table 4.6 HSDMA Trigger Set-up Bits Interrupt factor Timer 0 comparison A Timer 0 comparison B Timer 1 comparison A Timer 1 comparison B Timer 2 comparison A Timer 2 comparison B Timer 3 comparison A Timer 3 comparison B Timer 4 comparison A Timer 4 comparison B Timer 5 comparison A Timer 5 comparison B HSDMA Ch. Trigger set-up bits 0 0 1 1 2 2 3 3 0 2 0 2 1 3 1 3 HSD0S[3:0] (D[3:0]) / HSDMA Ch.0/1 trigger set-up register (0x40298) = "0111" HSD0S[3:0] (D[3:0]) / HSDMA Ch.0/1 trigger set-up register (0x40298) = "0110" HSD1S[3:0] (D[7:4]) / HSDMA Ch.0/1 trigger set-up register (0x40298) = "0111" HSD1S[3:0] (D[7:4]) / HSDMA Ch.0/1 trigger set-up register (0x40298) = "0110" HSD2S[3:0] (D[3:0]) / HSDMA Ch.2/3 trigger set-up register (0x40299) = "0111" HSD2S[3:0] (D[3:0]) / HSDMA Ch.2/3 trigger set-up register (0x40299) = "0110" HSD3S[3:0] (D[7:4]) / HSDMA Ch.2/3 trigger set-up register (0x40299) = "0111" HSD3S[3:0] (D[7:4]) / HSDMA Ch.2/3 trigger set-up register (0x40299) = "0110" HSD0S[3:0] (D[3:0]) / HSDMA Ch.0/1 trigger set-up register (0x40298) = "1001" HSD2S[3:0] (D[3:0]) / HSDMA Ch.2/3 trigger set-up register (0x40299) = "1001" HSD0S[3:0] (D[3:0]) / HSDMA Ch.0/1 trigger set-up register (0x40298) = "1000" HSD2S[3:0] (D[3:0]) / HSDMA Ch.2/3 trigger set-up register (0x40299) = "1000" HSD1S[3:0] (D[7:4]) / HSDMA Ch.0/1 trigger set-up register (0x40298) = "1001" HSD3S[3:0] (D[7:4]) / HSDMA Ch.2/3 trigger set-up register (0x40299) = "1001" HSD1S[3:0] (D[7:4]) / HSDMA Ch.0/1 trigger set-up register (0x40298) = "1000" HSD3S[3:0] (D[7:4]) / HSDMA Ch.2/3 trigger set-up register (0x40299) = "1000" For HSDMA to be invoked, a 16-bit timer interrupt factor should be selected using the trigger set-up bits in advance. Transfer conditions, etc. must also be set on the HSDMA side. If a 16-bit timer is selected as the HSDMA trigger, the HSDMA channel is invoked through generation of the interrupt factor. For details on HSDMA transfer, refer to "HSDMA (High-Speed DMA)". B-III-4-10 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS A-1 Trap vectors The trap vector addresses for each default interrupt factor are set as shown below: Timer 0 comparison B: Timer 0 comparison A: Timer 1 comparison B: Timer 1 comparison A: Timer 2 comparison B: Timer 2 comparison A: Timer 3 comparison B: Timer 3 comparison A: Timer 4 comparison B: Timer 4 comparison A: Timer 5 comparison B: Timer 5 comparison A: 0x0C00078 0x0C0007C 0x0C00088 0x0C0008C 0x0C00098 0x0C0009C 0x0C000A8 0x0C000AC 0x0C000B8 0x0C000BC 0x0C000C8 0x0C000CC The base address of the trap table can be changed using the TTBR register (0x48134 to 0x48137). Precaution Serial interface Ch.2 and Ch.3 share interrupt signals with the 16-bit timers. A register setting determined which is used. The initial setting is for use of the 16-bit timers. Refer to Section III-8, "Serial Interface", for details of the settings. B-III 16TM S1C33L03 FUNCTION PART EPSON B-III-4-11 III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS I/O Memory of 16-Bit Programmable Timers Table 4.7 shows the control bits of the 16-bit programmable timers. For details on the I/O memory of the prescaler used to set a clock, refer to "Prescaler". Table 4.7 Control Bits of 16-Bit Programmable Timer Register name Address Bit 16-bit timer 0/1 0040266 interrupt (B) priority register D7 D6 D5 D4 D3 D2 D1 D0 - P16T12 P16T11 P16T10 - P16T02 P16T01 P16T00 reserved 16-bit timer 1 interrupt level - 0 to 7 reserved 16-bit timer 0 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - P16T32 P16T31 P16T30 - P16T22 P16T21 P16T20 reserved 16-bit timer 3 interrupt level - 0 to 7 reserved 16-bit timer 2 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - P16T52 P16T51 P16T50 - P16T42 P16T41 P16T40 reserved 16-bit timer 5 interrupt level - 0 to 7 reserved 16-bit timer 4 interrupt level - 0 to 7 D7 D6 D5-4 D3 D2 D1-0 E16TC1 E16TU1 - E16TC0 E16TU0 - 16-bit timer 1 comparison A 16-bit timer 1 comparison B reserved 16-bit timer 0 comparison A 16-bit timer 0 comparison B reserved 1 Enabled D7 D6 D5-4 D3 D2 D1-0 E16TC3 E16TU3 - E16TC2 E16TU2 - 16-bit timer 3 comparison A 16-bit timer 3 comparison B reserved 16-bit timer 2 comparison A 16-bit timer 2 comparison B reserved 1 Enabled D7 D6 D5-4 D3 D2 D1-0 E16TC5 E16TU5 - E16TC4 E16TU4 - 16-bit timer 5 comparison A 16-bit timer 5 comparison B reserved 16-bit timer 4 comparison A 16-bit timer 4 comparison B reserved 1 Enabled D7 D6 D5-4 D3 D2 D1-0 F16TC1 F16TU1 - F16TC0 F16TU0 - 16-bit timer 1 comparison A 16-bit timer 1 comparison B reserved 16-bit timer 0 comparison A 16-bit timer 0 comparison B reserved 1 Factor is generated D7 D6 D5-4 D3 D2 D1-0 F16TC3 F16TU3 - F16TC2 F16TU2 - 16-bit timer 3 comparison A 16-bit timer 3 comparison B reserved 16-bit timer 2 comparison A 16-bit timer 2 comparison B reserved 1 Factor is generated D7 D6 D5-4 D3 D2 D1-0 F16TC5 F16TU5 - F16TC4 F16TU4 - 16-bit timer 5 comparison A 16-bit timer 5 comparison B reserved 16-bit timer 4 comparison A 16-bit timer 4 comparison B reserved 1 Factor is generated 16-bit timer 2/3 0040267 interrupt (B) priority register 16-bit timer 4/5 0040268 interrupt (B) priority register 16-bit timer 0/1 0040272 interrupt (B) enable register 16-bit timer 2/3 0040273 interrupt (B) enable register 16-bit timer 4/5 0040274 interrupt (B) enable register 16-bit timer 0/1 0040282 interrupt factor (B) flag register 16-bit timer 2/3 0040283 interrupt factor (B) flag register 16-bit timer 4/5 0040284 interrupt factor (B) flag register B-III-4-12 Name Function EPSON Setting 0 Disabled - 1 Enabled 0 Disabled - 0 Disabled - 1 Enabled 0 Disabled - 0 Disabled - 1 Enabled 0 Disabled - 0 No factor is generated - 1 Factor is generated 0 No factor is generated - 0 No factor is generated - 1 Factor is generated 0 No factor is generated - 0 No factor is generated - 1 Factor is generated 0 No factor is generated - Init. R/W Remarks - X X X - X X X - 0 when being read. R/W - X X X - X X X - 0 when being read. R/W - X X X - X X X - 0 when being read. R/W 0 0 - 0 0 - R/W R/W - 0 when being read. R/W R/W - 0 when being read. 0 0 - 0 0 - R/W R/W - 0 when being read. R/W R/W - 0 when being read. 0 0 - 0 0 - R/W R/W - 0 when being read. R/W R/W - 0 when being read. X X - X X - R/W R/W - 0 when being read. R/W R/W - 0 when being read. X X - X X - R/W R/W - 0 when being read. R/W R/W - 0 when being read. X X - X X - R/W R/W - 0 when being read. R/W R/W - 0 when being read. - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS A-1 Register name Address Bit Name Port input 0-3, high-speed DMA Ch. 0/1, 16-bit timer 0 IDMA request register 0040290 (B) D7 D6 D5 D4 D3 D2 D1 D0 R16TC0 R16TU0 RHDM1 RHDM0 RP3 RP2 RP1 RP0 16-bit timer 0 comparison A 16-bit timer 0 comparison B High-speed DMA Ch.1 High-speed DMA Ch.0 Port input 3 Port input 2 Port input 1 Port input 0 1 IDMA request 0 Interrupt request 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 16-bit timer 1-4 0040291 IDMA request (B) register D7 D6 D5 D4 D3 D2 D1 D0 R16TC4 R16TU4 R16TC3 R16TU3 R16TC2 R16TU2 R16TC1 R16TU1 16-bit timer 4 comparison A 16-bit timer 4 comparison B 16-bit timer 3 comparison A 16-bit timer 3 comparison B 16-bit timer 2 comparison A 16-bit timer 2 comparison B 16-bit timer 1 comparison A 16-bit timer 1 comparison B 1 IDMA request 0 Interrupt request 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA request register 0040292 (B) D7 D6 D5 D4 D3 D2 D1 D0 RSTX0 RSRX0 R8TU3 R8TU2 R8TU1 R8TU0 R16TC5 R16TU5 SIF Ch.0 transmit buffer empty SIF Ch.0 receive buffer full 8-bit timer 3 underflow 8-bit timer 2 underflow 8-bit timer 1 underflow 8-bit timer 0 underflow 16-bit timer 5 comparison A 16-bit timer 5 comparison B 1 IDMA request 0 Interrupt request 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Port input 0-3, high-speed DMA Ch. 0/1, 16-bit timer 0 IDMA enable register 0040294 (B) D7 D6 D5 D4 D3 D2 D1 D0 DE16TC0 DE16TU0 DEHDM1 DEHDM0 DEP3 DEP2 DEP1 DEP0 16-bit timer 0 comparison A 16-bit timer 0 comparison B High-speed DMA Ch.1 High-speed DMA Ch.0 Port input 3 Port input 2 Port input 1 Port input 0 1 IDMA enabled 0 IDMA disabled 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 16-bit timer 1-4 0040295 IDMA enable (B) register D7 D6 D5 D4 D3 D2 D1 D0 DE16TC4 DE16TU4 DE16TC3 DE16TU3 DE16TC2 DE16TU2 DE16TC1 DE16TU1 16-bit timer 4 comparison A 16-bit timer 4 comparison B 16-bit timer 3 comparison A 16-bit timer 3 comparison B 16-bit timer 2 comparison A 16-bit timer 2 comparison B 16-bit timer 1 comparison A 16-bit timer 1 comparison B 1 IDMA enabled 0 IDMA disabled 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA enable register 0040296 (B) D7 D6 D5 D4 D3 D2 D1 D0 DESTX0 DESRX0 DE8TU3 DE8TU2 DE8TU1 DE8TU0 DE16TC5 DE16TU5 SIF Ch.0 transmit buffer empty SIF Ch.0 receive buffer full 8-bit timer 3 underflow 8-bit timer 2 underflow 8-bit timer 1 underflow 8-bit timer 0 underflow 16-bit timer 5 comparison A 16-bit timer 5 comparison B 1 IDMA enabled 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W P1 function select register 00402D4 (B) D7 D6 - CFP16 reserved P16 function selection - 0 - 0 when being read. R/W D5 CFP15 P15 function selection 0 R/W D4 CFP14 P14 function selection - 1 EXCL5 0 P16 #DMAEND1 1 EXCL4 0 P15 #DMAEND0 1 FOSC1 0 P14 0 D3 CFP13 P13 function selection 0 P13 0 D2 CFP12 P12 function selection 0 P12 0 R/W D1 CFP11 P11 function selection 0 P11 0 R/W D0 CFP10 P10 function selection 1 EXCL3 T8UF3 1 EXCL2 T8UF2 1 EXCL1 T8UF1 1 EXCL0 T8UF0 R/W Extended functions (0x402DF) R/W 0 P10 0 R/W D7 D6 D5 D4 D3 D2 D1 D0 - IOC16 IOC15 IOC14 IOC13 IOC12 IOC11 IOC10 reserved P16 I/O control P15 I/O control P14 I/O control P13 I/O control P12 I/O control P11 I/O control P10 I/O control - 0 0 0 0 0 0 0 - R/W R/W R/W R/W R/W R/W R/W P1 I/O control register 00402D6 (B) S1C33L03 FUNCTION PART Function Setting 0 IDMA disabled - 1 Output EPSON 0 Input Init. R/W Remarks B-III 16TM 0 when being read. This register indicates the values of the I/O control signals of the ports when it is read. (See detailed explanation.) B-III-4-13 III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS Register name Address Bit P2 function select register 00402D8 (B) D7 D6 D5 D4 D3 D2 D1 D0 CFP27 CFP26 CFP25 CFP24 CFP23 CFP22 CFP21 CFP20 Name P27 function selection P26 function selection P25 function selection P24 function selection P23 function selection P22 function selection P21 function selection P20 function selection Function 1 1 1 1 1 1 1 1 Setting Port function extension register 00402DF (B) D7 D6 D5 D4 D3 D2 D1 CFEX7 CFEX6 CFEX5 CFEX4 CFEX3 CFEX2 CFEX1 P07 port extended function P06 port extended function P05 port extended function P04 port extended function P31 port extended function P21 port extended function P10, P11, P13 port extended function 1 1 1 1 1 1 1 D0 CFEX0 P12, P14 port extended function TM5 TM4 TM3 TM2 TM1 TM0 #DWE #DRD 0 0 0 0 0 0 0 0 #DMAEND3 #DMAACK3 #DMAEND2 #DMAACK2 #GARD #GAAS DST0 DST1 DPC0 1 DST2 DCLK Init. R/W P27 P26 P25 P24 P23 P22 P21 P20 0 0 0 0 0 0 0 P07, etc. P06, etc. P05, etc. P04, etc. P31, etc. P21, etc. P10, etc. P11, etc. P13, etc. 0 P12, etc. P14, etc. R/W R/W R/W R/W R/W R/W R/W Ext. func.(0x402DF) R/W 0 0 0 0 0 0 1 R/W R/W R/W R/W R/W R/W R/W 1 R/W 16-bit timer 0 comparison data A set-up register 0048180 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR0A15 CR0A14 CR0A13 CR0A12 CR0A11 CR0A10 CR0A9 CR0A8 CR0A7 CR0A6 CR0A5 CR0A4 CR0A3 CR0A2 CR0A1 CR0A0 16-bit timer 0 comparison data A CR0A15 = MSB CR0A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 0 comparison data B set-up register 0048182 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR0B15 CR0B14 CR0B13 CR0B12 CR0B11 CR0B10 CR0B9 CR0B8 CR0B7 CR0B6 CR0B5 CR0B4 CR0B3 CR0B2 CR0B1 CR0B0 16-bit timer 0 comparison data B CR0B15 = MSB CR0B0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 0 counter data register 0048184 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC015 TC014 TC013 TC012 TC011 TC010 TC09 TC08 TC07 TC06 TC05 TC04 TC03 TC02 TC01 TC00 16-bit timer 0 counter data TC015 = MSB TC00 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R 16-bit timer 0 0048186 control register (B) D7 D6 D5 D4 D3 D2 D1 D0 - SELFM0 SELCRB0 OUTINV0 CKSL0 PTM0 PRESET0 PRUN0 reserved 16-bit timer 0 fine mode selection 16-bit timer 0 comparison buffer 16-bit timer 0 output inversion 16-bit timer 0 input clock selection 16-bit timer 0 clock output control 16-bit timer 0 reset 16-bit timer 0 Run/Stop control B-III-4-14 EPSON 1 1 1 1 1 1 1 - Fine mode 0 Enabled 0 Invert 0 External clock 0 On 0 Reset 0 Run 0 Normal Disabled Normal Internal clock Off Invalid Stop Remarks 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W W 0 when being read. R/W S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS A-1 Register name Address Bit Name Function Setting 16-bit timer 1 comparison data A set-up register 0048188 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 1 comparison data B set-up register 004818A (HW) 16-bit timer 1 counter data register 004818C (HW) CR1A15 CR1A14 CR1A13 CR1A12 CR1A11 CR1A10 CR1A9 CR1A8 CR1A7 CR1A6 CR1A5 CR1A4 CR1A3 CR1A2 CR1A1 CR1A0 16-bit timer 1 comparison data A CR1A15 = MSB CR1A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR1B15 CR1B14 CR1B13 CR1B12 CR1B11 CR1B10 CR1B9 CR1B8 CR1B7 CR1B6 CR1B5 CR1B4 CR1B3 CR1B2 CR1B1 CR1B0 16-bit timer 1 comparison data B CR1B15 = MSB CR1B0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC115 TC114 TC113 TC112 TC111 TC110 TC19 TC18 TC17 TC16 TC15 TC14 TC13 TC12 TC11 TC10 16-bit timer 1 counter data TC115 = MSB TC10 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R 16-bit timer 1 004818E control register (B) D7 D6 D5 D4 D3 D2 D1 D0 - SELFM1 SELCRB1 OUTINV1 CKSL1 PTM1 PRESET1 PRUN1 reserved 16-bit timer 1 fine mode selection 16-bit timer 1 comparison buffer 16-bit timer 1 output inversion 16-bit timer 1 input clock selection 16-bit timer 1 clock output control 16-bit timer 1 reset 16-bit timer 1 Run/Stop control 16-bit timer 2 comparison data A set-up register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR2A15 CR2A14 CR2A13 CR2A12 CR2A11 CR2A10 CR2A9 CR2A8 CR2A7 CR2A6 CR2A5 CR2A4 CR2A3 CR2A2 CR2A1 CR2A0 16-bit timer 2 comparison data A CR2A15 = MSB CR2A0 = LSB 0048190 (HW) S1C33L03 FUNCTION PART EPSON 1 1 1 1 1 1 1 - Fine mode 0 Enabled 0 Invert 0 External clock 0 On 0 Reset 0 Run 0 Init. R/W Normal Disabled Normal Internal clock Off Invalid Stop 0 to 65535 Remarks B-III 16TM 0 0 0 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W W 0 when being read. R/W X X X X X X X X X X X X X X X X R/W B-III-4-15 III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS Register name Address Bit Name Function Setting 16-bit timer 2 comparison data B set-up register 0048192 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR2B15 CR2B14 CR2B13 CR2B12 CR2B11 CR2B10 CR2B9 CR2B8 CR2B7 CR2B6 CR2B5 CR2B4 CR2B3 CR2B2 CR2B1 CR2B0 16-bit timer 2 comparison data B CR2B15 = MSB CR2B0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 2 counter data register 0048194 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC215 TC214 TC213 TC212 TC211 TC210 TC29 TC28 TC27 TC26 TC25 TC24 TC23 TC22 TC21 TC20 16-bit timer 2 counter data TC215 = MSB TC20 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R 16-bit timer 2 0048196 control register (B) D7 D6 D5 D4 D3 D2 D1 D0 - SELFM2 SELCRB2 OUTINV2 CKSL2 PTM2 PRESET2 PRUN2 reserved 16-bit timer 2 fine mode selection 16-bit timer 2 comparison buffer 16-bit timer 2 output inversion 16-bit timer 2 input clock selection 16-bit timer 2 clock output control 16-bit timer 2 reset 16-bit timer 2 Run/Stop control 16-bit timer 3 comparison data A set-up register 0048198 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR3A15 CR3A14 CR3A13 CR3A12 CR3A11 CR3A10 CR3A9 CR3A8 CR3A7 CR3A6 CR3A5 CR3A4 CR3A3 CR3A2 CR3A1 CR3A0 16-bit timer 3 comparison data A CR3A15 = MSB CR3A0 = LSB 16-bit timer 3 comparison data B set-up register 004819A (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR3B15 CR3B14 CR3B13 CR3B12 CR3B11 CR3B10 CR3B9 CR3B8 CR3B7 CR3B6 CR3B5 CR3B4 CR3B3 CR3B2 CR3B1 CR3B0 16-bit timer 3 comparison data B CR3B15 = MSB CR3B0 = LSB B-III-4-16 EPSON 1 1 1 1 1 1 1 - Fine mode 0 Enabled 0 Invert 0 External clock 0 On 0 Reset 0 Run 0 Init. R/W Remarks 0 0 0 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W W 0 when being read. R/W 0 to 65535 X X X X X X X X X X X X X X X X R/W 0 to 65535 X X X X X X X X X X X X X X X X R/W Normal Disabled Normal Internal clock Off Invalid Stop S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS A-1 Register name Address Bit 16-bit timer 3 counter data register 004819C (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC315 TC314 TC313 TC312 TC311 TC310 TC39 TC38 TC37 TC36 TC35 TC34 TC33 TC32 TC31 TC30 16-bit timer 3 counter data TC315 = MSB TC30 = LSB 16-bit timer 3 004819E control register (B) D7 D6 D5 D4 D3 D2 D1 D0 - SELFM3 SELCRB3 OUTINV3 CKSL3 PTM3 PRESET3 PRUN3 reserved 16-bit timer 3 fine mode selection 16-bit timer 3 comparison buffer 16-bit timer 3 output inversion 16-bit timer 3 input clock selection 16-bit timer 3 clock output control 16-bit timer 3 reset 16-bit timer 3 Run/Stop control 16-bit timer 4 comparison data A set-up register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR4A15 CR4A14 CR4A13 CR4A12 CR4A11 CR4A10 CR4A9 CR4A8 CR4A7 CR4A6 CR4A5 CR4A4 CR4A3 CR4A2 CR4A1 CR4A0 16-bit timer 4 comparison data A CR4A15 = MSB CR4A0 = LSB 00481A0 (HW) Name Function Setting Init. R/W 0 to 65535 1 1 1 1 1 1 1 - Fine mode 0 Enabled 0 Invert 0 External clock 0 On 0 Reset 0 Run 0 Normal Disabled Normal Internal clock Off Invalid Stop 0 to 65535 16-bit timer 4 comparison data B set-up register 00481A2 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR4B15 CR4B14 CR4B13 CR4B12 CR4B11 CR4B10 CR4B9 CR4B8 CR4B7 CR4B6 CR4B5 CR4B4 CR4B3 CR4B2 CR4B1 CR4B0 16-bit timer 4 comparison data B CR4B15 = MSB CR4B0 = LSB 0 to 65535 16-bit timer 4 counter data register 00481A4 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC415 TC414 TC413 TC412 TC411 TC410 TC49 TC48 TC47 TC46 TC45 TC44 TC43 TC42 TC41 TC40 16-bit timer 4 counter data TC415 = MSB TC40 = LSB 0 to 65535 S1C33L03 FUNCTION PART EPSON X X X X X X X X X X X X X X X X Remarks R 0 0 0 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W W 0 when being read. R/W X X X X X X X X X X X X X X X X R/W X X X X X X X X X X X X X X X X R/W X X X X X X X X X X X X X X X X R B-III 16TM B-III-4-17 III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS Register name Address Bit Name Function Setting 16-bit timer 4 00481A6 control register (B) D7 D6 D5 D4 D3 D2 D1 D0 - SELFM4 SELCRB4 OUTINV4 CKSL4 PTM4 PRESET4 PRUN4 reserved 16-bit timer 4 fine mode selection 16-bit timer 4 comparison buffer 16-bit timer 4 output inversion 16-bit timer 4 input clock selection 16-bit timer 4 clock output control 16-bit timer 4 reset 16-bit timer 4 Run/Stop control - 16-bit timer 5 comparison data A set-up register 00481A8 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR5A15 CR5A14 CR5A13 CR5A12 CR5A11 CR5A10 CR5A9 CR5A8 CR5A7 CR5A6 CR5A5 CR5A4 CR5A3 CR5A2 CR5A1 CR5A0 16-bit timer 5 comparison data A CR5A15 = MSB CR5A0 = LSB 16-bit timer 5 comparison data B set-up register 00481AA (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR5B15 CR5B14 CR5B13 CR5B12 CR5B11 CR5B10 CR5B9 CR5B8 CR5B7 CR5B6 CR5B5 CR5B4 CR5B3 CR5B2 CR5B1 CR5B0 16-bit timer 5 counter data register 00481AC (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 5 00481AE control register (B) D7 D6 D5 D4 D3 D2 D1 D0 B-III-4-18 Init. R/W Remarks 0 0 0 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W W 0 when being read. R/W 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 5 comparison data B CR5B15 = MSB CR5B0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W TC515 TC514 TC513 TC512 TC511 TC510 TC59 TC58 TC57 TC56 TC55 TC54 TC53 TC52 TC51 TC50 16-bit timer 5 counter data TC515 = MSB TC50 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R - SELFM5 SELCRB5 OUTINV5 CKSL5 PTM5 PRESET5 PRUN5 reserved 16-bit timer 5 fine mode selection 16-bit timer 5 comparison buffer 16-bit timer 5 output inversion 16-bit timer 5 input clock selection 16-bit timer 5 clock output control 16-bit timer 5 reset 16-bit timer 5 Run/Stop control EPSON 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Fine mode Enabled Invert External clock On Reset Run 0 0 0 0 0 0 0 - Fine mode 0 Enabled 0 Invert 0 External clock 0 On 0 Reset 0 Run 0 Normal Disabled Normal Internal clock Off Invalid Stop Normal Disabled Normal Internal clock Off Invalid Stop 0 0 0 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W W 0 when being read. R/W S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS A-1 CFP16-CFP10: P1[6:0] pin function selection (D[6:0]) / P1 function select register (0x402D4) Selects the pin to be used for input of an external count clock to the timer. Write "1": Clock input pin Write "0": I/O port pin Read: Valid Select clock input pins for the timers that are used as an event counter from among P10 through P16, by writing "1" to CFP10-CFP16. For the relationship between each pin and timer, refer to Table 4.1. The pin is set for an I/O port by writing "0" to CFP1x. In addition to pin selection here, the pin to be used for clock input to the 16-bit programmable timer must be set to input mode using the I/O control register. At cold start, CFP1x is set to "0" (I/O port). At hot start, CFP1x retains its status from prior to the initial reset. CFP27-CFP22: P2[7:2] pin function selection (D[7:2]) / P2 function select register (0x402D8) Selects the pin used for clock output. Write "1": Clock output pin Write "0": I/O port pin Read: Valid Select the pin to be used to output a timer-generated clock to external devices from among P22 through P27, by writing "1" to CFP22-CFP27. For the relationship between each pin and timer, refer to Table 4.1. The pin is set for an I/O port by writing "0" to CFP2x. At cold start, CFP2x is set to "0" (I/O port). At hot start, CFP2x retains its status from prior to the initial reset. CFEX1: P10, P11, P13 port extended function (D1) / Port function extension register (0x402DF) CFEX0: P12, P14 port extended function (D0) / Port function extension register (0x402DF) Sets whether the function of an I/O-port pin is to be extended. B-III Write "1": Function-extended pin Write "0": I/O-port/peripheral-circuit pin Read: Valid When CFEX[1:0] is set to "1", the P14-P10 ports function as debug signal output ports. When CFEX[1:0] = "0", the CFP1[4:0] bit becomes effective, so the settings of these bits determine whether the P14-P10 ports function as I/O port s or external clock input ports. At cold start, CFEX[1:0] is set to "1" (function-extended pins). At hot start, CFEX[1:0] retains its state from prior to the initial reset. IOC16-IOC10: P1[6:0] port I/O control (D[6:0]) / P1 I/O control register (0x402D6) Directs P10 through P16 for input or output and indicates the I/O control signal value of the port. When writing data Write "1": Output mode Write "0": Input mode For the pin selected from among P10 through P16 for use for external clock input, write "0" to the corresponding I/O control bit to set it to input mode. If the pin is set to output mode, even though its CFP1x may be set to "1", it functions as the output pin of an 8-bit programmable timer and cannot be used to receive an external clock. When reading data Read "1": I/O control signal (output) Read "0": I/O control signal (input) The I/O control signal value for the port pin is read from this register. When I/O port function is selected using the CFEX and CFP1x registers, the value written to the IOC register is read out as is. When peripheral function is selected, the read value depends on the peripheral circuit status and may not indicate the value written to the IOC register. At cold start, IOC1x is set to "0" (input mode). At hot start, the bit retains its state from prior to the initial reset. S1C33L03 FUNCTION PART EPSON B-III-4-19 16TM III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS SELFM0: Timer 0 fine mode selection (D6) / 16-bit timer 0 control register (0x48186) SELFM1: Timer 1 fine mode selection (D6) / 16-bit timer 1 control register (0x4818E) SELFM2: Timer 2 fine mode selection (D6) / 16-bit timer 2 control register (0x48196) SELFM3: Timer 3 fine mode selection (D6) / 16-bit timer 3 control register (0x4819E) SELFM4: Timer 4 fine mode selection (D6) / 16-bit timer 4 control register (0x481A6) SELFM5: Timer 5 fine mode selection (D6) / 16-bit timer 5 control register (0x481AE) Sets fine mode for clock output. Write "1": Fine mode Write "0": Normal output Read: Valid When SELFMx is set to "1", clock output is set in fine mode which allows adjustment of the output signal duty ratio in units of a half cycle for the input clock. When SELFMx is set to "0", normal clock output will be performed. At initial reset, SELFMx is set to "0" (normal output). SELCRB0: Timer 0 comparison register buffer enable (D5) / 16-bit timer 0 control register (0x48186) SELCRB1: Timer 1 comparison register buffer enable (D5) / 16-bit timer 1 control register (0x4818E) SELCRB2: Timer 2 comparison register buffer enable (D5) / 16-bit timer 2 control register (0x48196) SELCRB3: Timer 3 comparison register buffer enable (D5) / 16-bit timer 3 control register (0x4819E) SELCRB4: Timer 4 comparison register buffer enable (D5) / 16-bit timer 4 control register (0x481A6) SELCRB5: Timer 5 comparison register buffer enable (D5) / 16-bit timer 5 control register (0x481AE) Enables or disables writing to the comparison register buffer. Write "1": Enabled Write "0": Disabled Read: Valid When SELCRBx is set to "1", comparison data is read and written from/to the comparison register buffer. The content of the buffer is loaded to the comparison data register when the counter is reset by the software or the comparison B signal. When SELCRBx is set to "0", comparison data is read and written from/to the comparison data register. At initial reset, SELCRBx is set to "0" (disabled). OUTINV0: Timer 0 output inversion (D4) / 16-bit timer 0 control register (0x48186) OUTINV1: Timer 1 output inversion (D4) / 16-bit timer 1 control register (0x4818E) OUTINV2: Timer 2 output inversion (D4) / 16-bit timer 2 control register (0x48196) OUTINV3: Timer 3 output inversion (D4) / 16-bit timer 3 control register (0x4819E) OUTINV4: Timer 4 output inversion (D4) / 16-bit timer 4 control register (0x481A6) OUTINV5: Timer 5 output inversion (D4) / 16-bit timer 5 control register (0x481AE) Selects a logic of the output signal. Write "1": Inverted (active low) Write "0": Normal (active high) Read: Valid By writing "1" to OUTINVx, an active-low signal (off level = high) is generated for the TMx output. When OUTINVx is set to "0", an active-high signal (off level = low) is generated. At initial reset, OUTINVx is set to "0" (active high). B-III-4-20 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS A-1 CKSL0: Timer 0 input clock selection (D3) / 16-bit timer 0 control register (0x48186) CKSL1: Timer 1 input clock selection (D3) / 16-bit timer 1 control register (0x4818E) CKSL2: Timer 2 input clock selection (D3) / 16-bit timer 2 control register (0x48196) CKSL3: Timer 3 input clock selection (D3) / 16-bit timer 3 control register (0x4819E) CKSL4: Timer 4 input clock selection (D3) / 16-bit timer 4 control register (0x481A6) CKSL5: Timer 5 input clock selection (D3) / 16-bit timer 5 control register (0x481AE) Selects the input clock of each timer. Write "1": External clock Write "0": Internal clock Read: Valid The internal clock (prescaler output) is selected for the input clock of each timer by writing "0" to CKSLx. An external clock (one that is fed from the clock input pin) is selected by writing "1", and the timer functions as an event counter. In this case, the clock input pin must be set using CFP1x before an external clock is selected here. At initial reset, CKSLx is set to "0" (internal clock). PTM0: Timer 0 clock output control (D2) / 16-bit timer 0 control register (0x48186) PTM1: Timer 1 clock output control (D2) / 16-bit timer 1 control register (0x4818E) PTM2: Timer 2 clock output control (D2) / 16-bit timer 2 control register (0x48196) PTM3: Timer 3 clock output control (D2) / 16-bit timer 3 control register (0x4819E) PTM4: Timer 4 clock output control (D2) / 16-bit timer 4 control register (0x481A6) PTM5: Timer 5 clock output control (D2) / 16-bit timer 5 control register (0x481AE) Controls the output of the TMx signal (timer output clock). Write "1": On Write "0": Off Read: Valid The TMx signal is output from the clock output pin by writing "1" to PTMx. Clock output is stopped by writing "0" to PTMx and goes to the off level according to the OUTINVx setting (low when OUTINVx = "0" or high when OUTINVx = "1"). In this case, the clock output pin must be set using CFP2x before outputting the TMx signal here. At initial reset, PTMx is set to "0" (off). PRESET0: Timer 0 reset (D1) / 16-bit timer 0 control register (0x48186) PRESET1: Timer 1 reset (D1) / 16-bit timer 1 control register (0x4818E) PRESET2: Timer 2 reset (D1) / 16-bit timer 2 control register (0x48196) PRESET3: Timer 3 reset (D1) / 16-bit timer 3 control register (0x4819E) PRESET4: Timer 4 reset (D1) / 16-bit timer 4 control register (0x481A6) PRESET5: Timer 5 reset (D1) / 16-bit timer 5 control register (0x481AE) Resets the counter. Write "1": Reset Write "0": Invalid Read: Always "0" The counter of timer x is reset by writing "1" to PRESETx. Writing "0" results in No Operation. Since PRESETx is a write-only bit, its content when read is always "0". S1C33L03 FUNCTION PART EPSON B-III-4-21 B-III 16TM III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS PRUN0: Timer 0 RUN/STOP control (D0) / 16-bit timer 0 control register (0x48186) PRUN1: Timer 1 RUN/STOP control (D0) / 16-bit timer 1 control register (0x4818E) PRUN2: Timer 2 RUN/STOP control (D0) / 16-bit timer 2 control register (0x48196) PRUN3: Timer 3 RUN/STOP control (D0) / 16-bit timer 3 control register (0x4819E) PRUN4: Timer 4 RUN/STOP control (D0) / 16-bit timer 4 control register (0x481A6) PRUN5: Timer 5 RUN/STOP control (D0) / 16-bit timer 5 control register (0x481AE) Controls the timer's RUN/STOP state. Write "1": RUN Write "0": STOP Read: Valid Each timer is made to start counting up by writing "1" to PRUNx and made to stop counting by writing "0". In the STOP state, the counter data is retained until the timer is reset or placed in a RUN state. By changing states from STOP to RUN, the timer can restart counting beginning at the retained count. At initial reset, PRUNx is set to "0" (STOP). CR0A15-CR0A0: Timer 0 comparison data A (D[F:0]) / 16-bit timer 0 comparison data A set-up register (0x48180) CR1A15-CR1A0: Timer 1 comparison data A (D[F:0]) / 16-bit timer 1 comparison data A set-up register (0x48188) CR2A15-CR2A0: Timer 2 comparison data A (D[F:0]) / 16-bit timer 2 comparison data A set-up register (0x48190) CR3A15-CR3A0: Timer 3 comparison data A (D[F:0]) / 16-bit timer 3 comparison data A set-up register (0x48198) CR4A15-CR4A0: Timer 4 comparison data A (D[F:0]) / 16-bit timer 4 comparison data A set-up register (0x481A0) CR5A15-CR5A0: Timer 5 comparison data A (D[F:0]) / 16-bit timer 5 comparison data A set-up register (0x481A8) Sets the comparison data A of each timer. When SELCRBx is set to "0", comparison data is directly read or writing from/to the comparison data register A. When SELCRBx is set to "1", comparison data is read or written from/to the comparison register buffer A. The content of the buffer is loaded to the comparison data register A when the counter is reset. The data set in this register is compared with each corresponding counter data. When the contents match, a comparison A interrupt is generated and the output signal rises (OUTINVx = "0") or falls (OUTINVx = "1"). This does not affect the counter value and count-up operation. At initial reset, CRxA is not initialized. CR0B15-CR0B0: Timer 0 comparison data B (D[F:0]) / 16-bit timer 0 comparison data B set-up register (0x48182) CR1B15-CR1B0: Timer 1 comparison data B (D[F:0]) / 16-bit timer 1 comparison data B set-up register (0x4818A) CR2B15-CR2B0: Timer 2 comparison data B (D[F:0]) / 16-bit timer 2 comparison data B set-up register (0x48192) CR3B15-CR3B0: Timer 3 comparison data B (D[F:0]) / 16-bit timer 3 comparison data B set-up register (0x4819A) CR4B15-CR4B0: Timer 4 comparison data B (D[F:0]) / 16-bit timer 4 comparison data B set-up register (0x481A2) CR5B15-CR5B0: Timer 5 comparison data B (D[F:0]) / 16-bit timer 5 comparison data B set-up register (0x481AA) Sets the comparison data B of each timer. When SELCRBx is set to "0", comparison data is directly read or writing from/to the comparison data register B. When SELCRBx is set to "1", comparison data is read or written from/to the comparison register buffer B. The content of the buffer is loaded to the comparison data register B when the counter is reset. The data set in this register is compared with each corresponding counter data. When the contents match, a comparison B interrupt is generated and the output signal falls (OUTINVx = "0") or rises (OUTINVx = "1"). Furthermore, the counter is reset to "0". At initial reset, CRxB is not initialized. B-III-4-22 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS A-1 TC015-TC00: Timer 0 counter data (D[F:0]) / 16-bit timer 0 counter data register (0x48184) TC115-TC10: Timer 1 counter data (D[F:0]) / 16-bit timer 1 counter data register (0x4818C) TC215-TC20: Timer 2 counter data (D[F:0]) / 16-bit timer 2 counter data register (0x48194) TC315-TC30: Timer 3 counter data (D[F:0]) / 16-bit timer 3 counter data register (0x4819C) TC415-TC40: Timer 4 counter data (D[F:0]) / 16-bit timer 4 counter data register (0x481A4) TC515-TC50: Timer 5 counter data (D[F:0]) / 16-bit timer 5 counter data register (0x481AC) The counter data of each timer can be read from this register. The data can be read out at any time. Since TCx is a read-only register, writing to this register is ignored. At initial reset, TCx is not initialized. P16T02-P16T00: Timer 0 interrupt level (D[2:0]) / 16-bit timer 0/1 interrupt priority register (0x40266) P16T12-P16T10: Timer 1 interrupt level (D[6:4]) / 16-bit timer 0/1 interrupt priority register (0x40266) P16T22-P16T20: Timer 2 interrupt level (D[2:0]) / 16-bit timer 2/3 interrupt priority register (0x40267) P16T32-P16T30: Timer 3 interrupt level (D[6:4]) / 16-bit timer 2/3 interrupt priority register (0x40267) P16T42-P16T40: Timer 4 interrupt level (D[2:0]) / 16-bit timer 4/5 interrupt priority register (0x40268) P16T52-P16T50: Timer 5 interrupt level (D[6:4]) / 16-bit timer 4/5 interrupt priority register (0x40268) Sets the priority levels of 16-bit programmable timer interrupts. The priority level can be set in the range of 0 to 7. At initial reset, P16Tx becomes indeterminate. E16TU0, E16TC0: Timer 0 interrupt enable (D2, D3) / 16-bit timer 0/1 interrupt enable register (0x40272) E16TU1, E16TC1: Timer 1 interrupt enable (D6, D7) / 16-bit timer 0/1 interrupt enable register (0x40272) E16TU2, E16TC2: Timer 2 interrupt enable (D2, D3) / 16-bit timer 2/3 interrupt enable register (0x40273) E16TU3, E16TC3: Timer 3 interrupt enable (D6, D7) / 16-bit timer 2/3 interrupt enable register (0x40273) E16TU4, E16TC4: Timer 4 interrupt enable (D2, D3) / 16-bit timer 4/5 interrupt enable register (0x40274) E16TU5, E16TC5: Timer 5 interrupt enable (D6, D7) / 16-bit timer 4/5 interrupt enable register (0x40274) Enables or disables the generation of an interrupt to the CPU. B-III Write "1": Interrupt enabled Write "0": Interrupt disabled Read: Valid 16TM The E16TUx and E16TCx are provided for the comparison B and comparison A interrupt factors, respectively. The interrupt for which the bit is set to "1" is enabled, and the interrupt for which the bit is set to "0" is disabled. At initial reset, these bits are set to "0" (interrupt disabled). F16TU0, F16TC0: Timer 0 interrupt factor flag (D2, D3) / 16-bit timer 0/1 interrupt factor flag register (0x40282) F16TU1, F16TC1: Timer 1 interrupt factor flag (D6, D7) / 16-bit timer 0/1 interrupt factor flag register (0x40282) F16TU2, F16TC2: Timer 2 interrupt factor flag (D2, D3) / 16-bit timer 2/3 interrupt factor flag register (0x40283) F16TU3, F16TC3: Timer 3 interrupt factor flag (D6, D7) / 16-bit timer 2/3 interrupt factor flag register (0x40283) F16TU4, F16TC4: Timer 4 interrupt factor flag (D2, D3) / 16-bit timer 4/5 interrupt factor flag register (0x40284) F16TU5, F16TC5: Timer 5 interrupt factor flag (D6, D7) / 16-bit timer 4/5 interrupt factor flag register (0x40284) Indicates the status of 16-bit programmable timer interrupt generation. When read Read "1": Interrupt factor has occurred Read "0": No interrupt factor has occurred When written using the reset-only method (default) Write "1": Interrupt factor flag is reset Write "0": Invalid When written using the read/write method Write "1": Interrupt flag is set Write "0": Interrupt flag is reset S1C33L03 FUNCTION PART EPSON B-III-4-23 III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS F16TUx and F16TCx are the interrupt factor flags corresponding to the comparison B and comparison A interrupts, respectively. The flag is set to "1" when each interrupt factor occurs. At this time, if the following conditions are met, an interrupt to the CPU is generated: 1. The corresponding interrupt enable register bit is set to "1". 2. No other interrupt request of a higher priority has been generated. 3. The PSR's IE bit is set to "1" (interrupts enabled). 4. The value set in the corresponding interrupt priority register is higher than the CPU's interrupt level (IL). When using the interrupt factor of the 16-bit programmable timer to request IDMA, note that even when the above conditions are met, no interrupt request to the CPU is generated for the interrupt factor that has occurred. If interrupts are enabled at the setting of IDMA, an interrupt is generated under the above conditions after the data transfer by IDMA is completed. The interrupt factor flag is set to "1" whenever interrupt generation conditions are met, regardless of how the interrupt enable and interrupt priority registers are set. If the next interrupt is to be accepted after an interrupt has occurred, it is necessary that the interrupt factor flag be reset, and that the PSR be set again (by setting the IE bit to "1" after setting the IL to a value lower than the level indicated by the interrupt priority register, or by executing the reti instruction). The interrupt factor flag can be reset only by writing to it in the software. Note that if the PSR is set again to accept interrupts generated (or if the reti instruction is executed) without resetting the interrupt factor flag, the same interrupt occurs again. Note also that the value to be written to reset the flag is "1" when the reset-only method (RSTONLY = "1") is used, and "0" when the read/write method (RSTONLY = "0") is used. At initial reset, all these flags become indeterminate, so be sure to reset them in the software. R16TU0, R16TC0: Timer 0 IDMA request (D6, D7) / Port input 0-3, HSDMA, 16-bit timer 0 IDMA request register (0x40290) R16TU1, R16TC1: Timer 1 IDMA request (D0, D1) / 16-bit timer 1-4 IDMA request register (0x40291) R16TU2, R16TC2: Timer 2 IDMA request (D2, D3) / 16-bit timer 1-4 IDMA request register (0x40291) R16TU3, R16TC3: Timer 3 IDMA request (D4, D5) / 16-bit timer 1-4 IDMA request register (0x40291) R16TU4, R16TC4: Timer 4 IDMA request (D6, D7) / 16-bit timer 1-4 IDMA request register (0x40291) R16TU5, R16TC5: Timer 5 IDMA request (D0, D1) / 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA request register (0x40292) Specifies whether to invoke IDMA when an interrupt factor occurs. When using the set-only method (default) Write "1": IDMA request Write "0": Not changed Read: Valid When using the read/write method Write "1": IDMA request Write "0": Interrupt request Read: Valid R16TUx and R16TCx are IDMA request bits corresponding to the comparison B and comparison A interrupt factors, respectively. When the bit is set to "1", IDMA is invoked when the interrupt factor occurs, thereby performing programmed data transfers. When the register is set to "0", normal interrupt processing is performed and IDMA is not invoked. For details on IDMA, refer to "IDMA (Intelligent DMA)". At initial reset, these bits are set to "0" (interrupt request). B-III-4-24 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS A-1 DE16TU0, DE16TC0: Timer 0 IDMA enable (D6, D7) / Port input 0-3, HSDMA, 16-bit timer 0 IDMA enable register (0x40294) DE16TU1, DE16TC1: Timer 1 IDMA enable (D0, D1) / 16-bit timer 1-4 IDMA enable register (0x40295) DE16TU2, DE16TC2: Timer 2 IDMA enable (D2, D3) / 16-bit timer 1-4 IDMA enable register (0x40295) DE16TU3, DE16TC3: Timer 3 IDMA enable (D4, D5) / 16-bit timer 1-4 IDMA enable register (0x40295) DE16TU4, DE16TC4: Timer 4 IDMA enable (D6, D7) / 16-bit timer 1-4 IDMA enable register (0x40295) DE16TU5, DE16TC5: Timer 5 IDMA enable (D0, D1) / 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA enable register (0x40296) Enables IDMA transfer by means of an interrupt factor. When using the set-only method (default) Write "1": IDMA enabled Write "0": Not changed Read: Valid When using the read/write method Write "1": IDMA enabled Write "0": IDMA disabled Read: Valid DE16TUx and DE16TCx are IDMA enable bits corresponding to the comparison B and comparison A interrupt factors, respectively. If the bit is set to "1", the IDMA request by the interrupt factor is enabled. If the bit is set to "0", the IDMA request is disabled. After an initial reset, these bits are set to "0" (IDMA disabled). Programming Notes (1) The 16-bit programmable timers operate only when the prescaler is operating. (2) When setting the input clock or operation mode, make sure the 16-bit programmable timer is turned off. B-III (3) If a same value is set to the comparison data A and B registers, a hazard may be generated in the output signal. Therefore, do not set the comparison registers as A = B. There is no problem when the interrupt function only is used. (4) When using the output clock, set the comparison data registers as A 0 and B 1. The minimum settings are A = 0 and B = 1. In this case, the timer output clock cycle is the input clock x 1/2. (5) When the comparison data registers are set as A > B in normal mode, no comparison A interrupt is generated. In this case, the output signal is fixed at the off level. In fine mode, no comparison A interrupt is generated when the comparison data registers are set as A > 2 x B + 1. (6) After an initial reset, the interrupt factor flag becomes indeterminate. To prevent generation of an unwanted interrupt or IDMA request, be sure to reset this flag and register in the software. (7) To prevent another interrupt from being generated by the same factor after an interrupt has occurred, be sure to reset the interrupt factor flag before setting the PSR again or executing the reti instruction. (8) Be aware that unnecessary pulse may be generated according to the control of the clock output and port configuration when a 16-bit programmable timer is used to output the TMx clock. For example, when TMx is set as inverted output (OUTINVx = "1"), the output waveform falls with the comparison B signal and it rises with the comparison A signal. Furthermore, the output pin is fixed at high level when PTMx is set to "0" to stop the clock output. When switching the output pin to the I/O port pin and then setting the port to low after the TMx signal falls with the comparison A signal, a high level pulse will be generated if "0" is written to PTMx before setting the port to low. It can be prevented by writing "0" to PTMx after setting the port to low. S1C33L03 FUNCTION PART EPSON B-III-4-25 16TM III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS THIS PAGE IS BLANK. B-III-4-26 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: WATCHDOG TIMER A-1 III-5 WATCHDOG TIMER Configuration of Watchdog Timer The Peripheral Block incorporates a watchdog timer function to detect the CPU's crash. This function is implemented through the use of the 16-bit programmable timer 0. When this function is enabled, an NMI (nonmaskable interrupt) is generated by the comparison B signal from the 16-bit programmable timer 0 (generating intervals can be set through the use of software). The 16-bit programmable timer 0 set in the software so as not to generate the NMI, making it possible to detect a program crash that may not pass through this processing routine. Figure 5.1 shows the block diagram of the watchdog timer. Watchdog timer Clock generator Prescaler 16-bit programmable timer 0 EWD NMI Figure 5.1 Watchdog Timer Block Diagram Control of Watchdog Timer Setting the operating clock and NMI generating interval The watchdog timer is operated by the prescaler's output clock. Therefore, the watchdog timer function cannot be used when the prescaler is inactive. The NMI is generated every time the 16-bit programmable timer 0 is reset by the comparison B setting. Therefore, this interval is determined by the prescaler's P16TS0[2:0] (D[2:0]) / 16-bit timer 0 clock control register (0x40147), and the comparison data B set in CR0B[15:0] (D[F:0]) / 16-bit timer 0 comparison register B (0x48182). B-III The NMI generating interval is calculated using the following equation: NMI generating interval = fPSCIN: pdr: CR0B: CR0B + 1 fPSCIN x pdr [sec.] Prescaler input clock frequency [Hz] Prescaler's division ratio set by the P16TS0 register (1/4096, 1/1024, 1/256, 1/64, 1/16, 1/4, 1/2, 1/1) Set value of the CR0B register (0 to 65,535) For details on how to control the prescaler and the 16-bit programmable timer 0, refer to "Prescaler" and "16Bit Programmable Timers". Setting the watchdog timer function To use the watchdog timer function, enable the NMI that is generated by the comparison B signal from the 16-bit programmable timer 0. For this purpose, use EWD (D1) / Watchdog timer enable register (0x40171). The NMI is enabled by writing "1" to EWD. At initial reset, EWD is set to "0", so generation of the NMI is disabled. To prevent an unwanted NMI from being generated by erroneous writing to EWD, this register is normally write-protected. To write-enable EWD, write "1" to WRWD (D7) / Watchdog timer write-protect register (0x40170). Only one writing to EWD is enabled in this way by the WRWD bit. When data is written to EWD after it is write-enabled, the WRWD bit is reset back to "0", thus making EWD write-protected again. For the 16-bit programmable timer 0, set an appropriate comparison B value to make it start operating. If the watchdog timer function is not to be used, set EWD to "0" and do not change it. S1C33L03 FUNCTION PART EPSON B-III-5-1 WDT III PERIPHERAL BLOCK: WATCHDOG TIMER Resetting the watchdog timer When using the watchdog timer, prepare a routine to reset the 16-bit programmable timer 0 before an NMI is generated in a location where it will be periodically processed. Make sure this routine is processed within the NMI generation interval described above. The 16-bit programmable timer 0 is reset by writing "1" to PRESET0 (D1) / 16-bit timer 0 control register (0x48186). At this point, the timer counter is set to 0, and the timer starts counting the NMI generation interval over again from that point. If the watchdog timer is not reset within the set interval for any reason, the CPU is made to enter trap processing by an NMI and starts executing the processing routine indicated by the NMI vector. The NMI trap vector address is set to 0x0C0001C by default. The trap table base address can be changed using the TTBR registers (0x48134 to 0x48137). Operation in Standby Modes During HALT mode In HALT mode (basic mode or HALT2 mode), the prescaler and watchdog timer are operating. Consequently, if HALT mode continues beyond the NMI generation interval, HALT mode is cleared by the NMI. To disable the watchdog timer in HALT mode, set EWD to "0" before executing the halt instruction or turn off the 16-bit programmable timer 0. If the NMI is disabled by EWD, the 16-bit programmable timer 0 continues counting even in HALT mode. To reenable the NMI after clearing HALT mode, reset the 16-bit programmable timer 0 in advance. If HALT mode was entered after the 16-bit programmable timer 0 was turned off, reset the timer before restarting it. During SLEEP mode In SLEEP mode, the prescaler is turned off. Therefore, the watchdog timer also stops operating. To prevent generation of an unwanted NMI after clearing SLEEP mode, reset the 16-bit programmable timer 0 before executing the slp instruction. In addition, disable generation of the NMI by EWD as necessary. B-III-5-2 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: WATCHDOG TIMER A-1 I/O Memory of Watchdog Timer Table 5.1 shows the control bits of the watchdog timer. Table 5.1 Control Bits of Watchdog Timer Register name Address Bit Name Function Setting Init. R/W Remarks Watchdog 0040170 timer write(B) protect register D7 WRWD D6-0 - EWD write protection - 1 Write enabled 0 Write-protect - 0 - R/W - 0 when being read. Watchdog timer enable register D7-2 - D1 EWD D0 - - Watchdog timer enable - - 1 NMI enabled 0 NMI disabled - - 0 - - 0 when being read. R/W - 0 when being read. 0040171 (B) WRWD: EWD write protection (D7) / Watchdog timer write-protect register (0x40170) Enables writing to the EWD register. Write "1": Writing enabled Write "0": Write-protected Read: Valid The EWD bit is write-protected to prevent unwanted modifications. Writing to this bit is enabled for only one writing by setting WRWD to "1". WRWD is reset back to "0" by writing to EWD, so EWD is write-protected again. If WRWD is reset to "0" when EWD is write-enabled (WRWD = "1"), EWD becomes write-protected again. At initial reset, WRWD is set to "0" (write-protected). EWD: NMI enable (D1) / Watchdog timer enable register (0x40171) Controls the generation of a nonmaskable interrupt (NMI) by the watchdog timer. Write "1": NMI is enabled Write "0": NMI is disabled Read: Valid B-III The watchdog timer's interrupt signal is masked by writing "0" to EWD, so a nonmaskable interrupt (NMI) to the CPU is not generated. If EWD is set to "1", an NMI is generated by the 16-bit programmable timer 0 comparison B signal. Writing to EWD is valid only when WRWD = "1". Even when EWD is set to "0", the 16-bit programmable timer 0 does not stop counting. Therefore, if the NMI has been temporarily disabled, be sure to reset the 16-bit programmable timer 0 before setting the EWD register back to "1". At initial reset, EWD is set to "0" (NMI disabled). Programming Notes (1) If the watchdog timer's NMI is enabled, the watchdog timer must be reset in the software before the 16-bit programmable timer 0 outputs the comparison B signal. (2) Even when EWD is set to "0", the 16-bit programmable timer 0 does not stop counting. Therefore, if the NMI has been temporarily disabled, be sure to reset the 16-bit programmable timer 0 before setting EWD back to "1". S1C33L03 FUNCTION PART EPSON B-III-5-3 WDT III PERIPHERAL BLOCK: WATCHDOG TIMER THIS PAGE IS BLANK. B-III-5-4 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT A-1 III-6 LOW-SPEED (OSC1) OSCILLATION CIRCUIT Configuration of Low-Speed (OSC1) Oscillation Circuit The Peripheral Block has a built-in low-speed (OSC1) oscillation circuit. The low-speed (OSC1) oscillation circuit generates a 32.768-kHz (Typ.) subclock. The OSC1 clock output by this circuit is delivered to the CLG (clock generator) in the Core Block and is used as the source clock for the clock timer. It can also be used as a sub-clock for the low-speed (low-power) operation of the CPU and peripheral circuits (switchable in a program). Figure 6.1 shows the configuration of the clock system. Oscillation SOSC1 ON/OFF OSC1 OSC2 Low-speed (OSC1) oscillation circuit I/O port FOSC1 (P14) CLG CLKCHG OSC3/PLL clock Clock switch Prescaler PF1ON To CPU and BCU To peripheral circuits Clock timer Figure 6.1 Configuration of Clock System The CPU operating clock can be switched to the output (OSC1 clock) of the low-speed (OSC1) oscillation circuit in a program. Furthermore, the oscillation circuit can be stopped in a program. If the OSC3 clock is unnecessary such as when performing clock processing only, set the OSC1 clock for operation of the CPU/peripheral circuits and turn off the high-speed (OSC3) oscillation circuit in order to reduce current consumption. The low-speed (OSC1) oscillation circuit does not stop in SLEEP mode. For the control method when using the OSC1 clock for the operating clock of the peripheral circuits, refer to "Prescaler". B-III I/O Pins of Low-Speed (OSC1) Oscillation Circuit Table 6.1 lists the I/O pins of the low-speed (OSC1) oscillation circuit. OSC1 Table 6.1 I/O Pins of Low-Speed (OSC1) Oscillation Circuit Pin name I/O OSC1 I OSC2 O P14/FOSC1/DCLK I/O S1C33L03 FUNCTION PART Function Low-speed (OSC1) oscillation input pin Crystal oscillation or external clock input Low-speed (OSC1) oscillation output pin Crystal oscillation (open when external clock is used) I/O port / Low-speed (OSC1) oscillation clock output / DCLK signal output EPSON B-III-6-1 III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT Oscillator Types In the low-speed (OSC1) oscillation circuit, either a crystal oscillation or an external clock input can be selected as the type of oscillation circuit. Figure 6.2 shows the structure of the low-speed (OSC1) oscillation circuit. CG1 OSC1 VDD VSS fOSC1 Rf CD1 VSS X'tal1 OSC2 OSC1 fOSC1 External clock N.C. Oscillation circuit control signal Oscillation circuit control signal OSC2 (2) External clock input (1) Crystal oscillation circuit OSC1 Low level Oscillation circuit control signal OSC2 VSS (3) When not used Figure 6.2 Low-Speed (OSC1) Oscillation Circuit When using a crystal oscillation for this circuit, connect a crystal resonator X'tal1 (32.768 kHz, Typ.) and feedback resistor (Rf) between the OSC1 and OSC2 pins, and two capacitors (CG1, CD1) between the OSC1 pin and VSS and the OSC2 pin and VSS, respectively. When an external clock source is used, leave the OSC2 pin open and input a square-wave clock to the OSC1 pin. If the low-speed (OSC1) oscillation circuit is not used, connect the OSC1 pin to VSS and leave the OSC2 pin open. The oscillation frequency is 32.768 kHz (Typ.). Use a crystal resonator or external clock that oscillates at this frequency. No other frequency can be used for clock applications. For details on oscillation characteristics and the external clock input characteristics, refer to "Electrical Characteristics". B-III-6-2 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT A-1 Controlling Oscillation The low-speed (OSC1) oscillation circuit can be turned on or off using SOSC1 (D0) / Power control register (0x40180). The oscillation circuit is turned off by writing "0" to SOSC1 and turned back on again by writing "1". SOSC1 is set to "1" at initial reset, so the oscillation circuit is turned on. Notes: * When the low-speed (OSC1) oscillation circuit is used as the clock source for the CPU operating clock, it cannot be turned off. In this case, writing "0" to SOSC1 is ignored. Note also that writing to SOSC1 is allowed only when the power-control register protection flag is set to "0b10010110". * Immediately after the oscillation circuit is turned on, a certain period of time is required for oscillation to stabilize (3 sec max.). To prevent the device from operating erratically, do not use the clock until its oscillation has stabilized. The low-speed (OSC1) oscillation circuit does not stop when the CPU is set in SLEEP mode. Switching Over the CPU Operating Clock After an initial reset, the CPU starts operating using the OSC3 clock. In cases in which some peripheral circuits (e.g., programmable timer, serial interface, A/D converter, and ports) do not need to be operate or processing in low-speed operation is possible, and the CPU can process its jobs at a low clock speed, the CPU operating clock can be switched to the OSC1 clock, thereby reducing current consumption. Use CLKCHG (D2) / Power control register (0x40180) to switch over the operating clock. Procedure for switching over from the OSC3 clock to the OSC1 clock 1. Turn on the low-speed (OSC1) oscillation circuit (by writing "1" to SOSC1). 2. Wait until the OSC1 oscillation stabilizes (three seconds or more). 3. Change the CPU operating clock (by writing "0" to CLKCHG). 4. Turn off the high-speed (OSC3) oscillation circuit (by writing "0" to SOSC3). Steps 1 and 2 are required only when the low-speed (OSC1) oscillation circuit is inactive. B-III Notes: * Use separate instructions to switch from OSC3 to OSC1 and turn the OSC3 oscillation off. If these operations are processed simultaneously using one instruction, the CPU may operate erratically. * Make sure the operation of the peripheral circuits, such as the programmable timer and serial interface is terminated before the OSC3 oscillation is turned off in order to prevent them from operating erratically or the prescaler clock is set as OSC1. In addition, in order to prevent incorrect operation, a setup of prescaler must be performed before changing the CPU clock. Procedure for switching over from the OSC1 clock to the OSC3 clock 1. Turn on the high-speed (OSC3) oscillation circuit (by writing "1" to SOSC3). 2. Wait until the OSC3 oscillation stabilizes (10 ms or more for a 3.3-V crystal resonator). 3. Switch over the CPU operating clock (by writing "1" to CLKCHG). Note: The operating clock switchover by CLKCHG is effective only when both oscillation circuits are on and the power-control register protection flag is set to "0b10010110". S1C33L03 FUNCTION PART EPSON B-III-6-3 OSC1 III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT Power-Control Register Protection Flag The power-control register (SOSC1, SOSC3, CLKCHG, CLKDT[1:0]) at address 0x40180, which is used to control the oscillation circuits and the CPU operating clock, is normally disabled against writing in order to prevent it from malfunctioning due to unnecessary writing. To enable this register for writing, the power-control register protection flag CLGP[7:0] (D[7:0]) / Power-control protection register (0x4019E) must be set to "0b10010110". Note that this setting allows for the power-control register (0x40180) to be written to only once, so all bits of CLGP[7:0] are cleared to "0" when this address is written to. Therefore, CLGP[7:0] must be set to "0b10010110" each time the power-control register (0x40180) is written to. The flag CLGP[7:0] does not affect the readout from the power-control register (0x40180). Operation in Standby Mode In HALT mode, which is entered by executing the halt instruction, the low-speed (OSC1) oscillation circuits retains its status before HALT mode is entered. Under normal conditions, therefore, there is no need to control the oscillation circuit before entering or after exiting HALT mode. The low-speed (OSC1) oscillation circuit does not stop operating in SLEEP mode set by executing the slp (sleep) instruction. Therefore, if the CPU was operating using the OSC1 clock before SLEEP mode was entered, the CPU keeps operating using the OSC1 clock in SLEEP mode. OSC1 Clock Output to External Devices The low-speed (OSC1) oscillation clock can be output from the FOSC1 (P14) pin to external devices. Table 6.2 OSC1 Clock Output Pin Pin name I/O Function Function select bit P14/FOSC1/ I/O I/O port / Low-speed (OSC1) oscillation DCLK clock output / DCLK signal output CFP14(D4) / P1 function select register (0x402D4) CFEX0 (D0) / Port function extension register (0x402DF) Setting the clock output pin The pin used to output the OSC1 clock to external devices is shared with the P14 I/O port and the debug clock signal DCLK. At cold start, it is set for the DCLK signal output (CFP14 = "0" and CFEX0 = "1"). When using the clock output function, write "1" to CFP14 and "0" to CFEX0 (refer to "I/O Ports"), and also write "1" to IOC14 (0x402D6/D4). At hot start, the pin retains its pre-reset status. Output control To start clock output, write "1" to PF1ON (D0) / Clock option register (0x40190). The clock output is stopped by writing "0". At initial reset, PF1ON is set to "0" (output disabled). PF1ON register 0 1 0 VDD VSS FOSC1(P14) pin output Figure 6.3 OSC1 Clock Output B-III-6-4 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT A-1 I/O Memory of Low-Speed (OSC1) Oscillation Circuit Table 6.3 lists the control bits of the low-speed (OSC1) oscillation circuit. Table 6.3 Control Bits of Low-Speed (OSC1) Oscillation Circuit Register name Address Bit Name Power control register D7 D6 CLKDT1 CLKDT0 System clock division ratio selection D5 D4-3 D2 D1 D0 PSCON - CLKCHG SOSC3 SOSC1 Prescaler On/Off control reserved 1 OSC3 CPU operating clock switch High-speed (OSC3) oscillation On/Off 1 On Low-speed (OSC1) oscillation On/Off 1 On D7-4 D3 D2 D1 D0 - HLT2OP 8T1ON - PF1ON - HALT clock option OSC3-stabilize waiting function reserved OSC1 external output control Clock option register 0040180 (B) 0040190 (B) Function Setting CLKDT[1:0] 1 1 1 0 0 1 0 0 1 On Init. R/W Remarks Division ratio 1/8 1/4 1/2 1/1 0 Off - 0 OSC1 0 Off 0 Off 0 0 R/W 1 0 1 1 1 R/W - Writing 1 not allowed. R/W R/W R/W - - 0 1 0 0 - 0 when being read. R/W R/W - Do not write 1. R/W 1 On 1 Off 0 Off 0 On - 1 On 0 Off Power control 004019E protect register (B) D7 D6 D5 D4 D3 D2 D1 D0 CLGP7 CLGP6 CLGP5 CLGP4 CLGP3 CLGP2 CLGP1 CLGP0 Power control register protect flag Writing 10010110 (0x96) removes the write protection of the power control register (0x40180) and the clock option register (0x40190). Writing another value set the write protection. 0 0 0 0 0 0 0 0 R/W P1 function select register D7 D6 - CFP16 reserved P16 function selection - 0 - 0 when being read. R/W D5 CFP15 P15 function selection 0 R/W D4 CFP14 P14 function selection - 1 EXCL5 0 P16 #DMAEND1 1 EXCL4 0 P15 #DMAEND0 1 FOSC1 0 P14 0 D3 CFP13 P13 function selection 0 P13 0 D2 CFP12 P12 function selection 0 P12 0 R/W D1 CFP11 P11 function selection 0 P11 0 R/W D0 CFP10 P10 function selection 1 EXCL3 T8UF3 1 EXCL2 T8UF2 1 EXCL1 T8UF1 1 EXCL0 T8UF0 R/W Extended functions (0x402DF) R/W 0 P10 0 R/W D7 D6 D5 D4 D3 D2 D1 CFEX7 CFEX6 CFEX5 CFEX4 CFEX3 CFEX2 CFEX1 P07 port extended function P06 port extended function P05 port extended function P04 port extended function P31 port extended function P21 port extended function P10, P11, P13 port extended function 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 R/W R/W R/W R/W R/W R/W R/W D0 CFEX0 P12, P14 port extended function 1 R/W Port function extension register 00402D4 (B) 00402DF (B) S1C33L03 FUNCTION PART EPSON #DMAEND3 #DMAACK3 #DMAEND2 #DMAACK2 #GARD #GAAS DST0 DST1 DPC0 1 DST2 DCLK P07, etc. P06, etc. P05, etc. P04, etc. P31, etc. P21, etc. P10, etc. P11, etc. P13, etc. 0 P12, etc. P14, etc. B-III OSC1 B-III-6-5 III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT SOSC1: Low-speed (OSC1) oscillation control (D0) / Power control register (0x40180) Turns the low-speed (OSC1) oscillation on or off. Write "1": OSC1 oscillation turned on Write "0": OSC1 oscillation turned off Read: Valid The oscillation of the low-speed (OSC1) oscillation circuit is stopped by writing "0" to SOSC1, and started again by writing "1". Since a duration of maximum three seconds is required for oscillation to stabilize after the oscillation has been restarted, at least this length of time must pass before the OSC1 clock can be used. Writing to SOSC1 is allowed only when CLGP[7:0] is set to "0b10010110". Note also that if the CPU is operating using the OSC1 clock, writing "0" to SOSC1 is ignored and the oscillation is not turned off. At initial reset, SOSC1 is set to "1" (OSC1 oscillation turned on). CLKCHG: CPU operating clock switch (D2) / Power control register (0x40180) Selects the CPU operating clock. Write "1": OSC3 clock Write "0": OSC1 clock Read: Valid The OSC3 clock is selected as the CPU operating clock by writing "1" to CLKCHG, and OSC1 is selected by writing "0". The operating clock can be switched over in this way only when both the high-speed (OSC3) and lowspeed (OSC1) oscillation circuits are on. In addition, writing to CLKCHG is effective only when CLGP[7:0] is set to "0b10010110". Immediately after the oscillation circuit has started oscillating, wait for the oscillation to stabilize before switching over the CPU operating clock. At initial reset, CLKCHG is set to "1" (OSC3 clock). For controlling the high-speed (OSC3) oscillation circuit, refer to "CLG (Clock Generator)" in the Core Block. HLT2OP: HALT clock option (D3) / Clock option register (0x40190) Select a HALT condition (basic mode or HALT2 mode). Write "1": HALT2 mode Write "0": Basic mode Read: Valid When "1" is written to HLT2OP, the CPU will enter HALT2 mode when the HALT instruction is executed. When "0" is written, the CPU will enter basic mode. Writing to HLT2OP is allowed only when CLGP[7:0] is set to "0b10010110". At initial reset, HLT2OP is set to "0" (basic mode). B-III-6-6 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT A-1 The following shows the operating status in HALT mode (basic mode and HALT2 mode) and SLEEP mode. Table 6.4 Operating Status in Standby Mode Standby mode HALT mode Basic mode Operating status * * * * * * HALT2 mode * * * * * * SLEEP mode * * * * * The CPU clock is stopped. (CPU stop status) BCU clock is supplied. (BCU run status) DMA clock is not stopped. (DMA run status) Clocks for the peripheral circuits maintain the status before entering HALT mode. (run or stop) The high-speed oscillation circuit maintains the status before entering HALT mode. The low-speed oscillation circuit maintains the status before entering HALT mode. The CPU clock is stopped. (CPU stop status) BCU clock is stopped. (BCU stop status) DMA clock is stopped. (DMA stop status) Clocks for the peripheral circuits maintain the status before entering HALT mode. (run or stop) The high-speed oscillation circuit maintains the status before entering HALT mode. The low-speed oscillation circuit maintains the status before entering HALT mode. The CPU clock is stopped. (CPU stop status) BCU clock is stopped. (BCU stop status) Clocks for the peripheral circuits are stopped. The high-speed oscillation circuit is stopped. The low-speed oscillation circuit maintains the status before entering SLEEP mode. Reactivating factor * Reset, NMI * Enabled (not masked) interrupt factors A restart is possible only in the case of: * Reset, NMI * Enabled (not masked) interrupt factors Note, however, that an interrupt from a peripheral circuit can restart the CPU only when the operating clock is supplied to the peripheral circuit. * Reset, NMI * Enabled (not masked) input port interrupt factors * Clock timer interrupt when the low-speed oscillation circuit is being operated PF1ON: OSC1 external output control (D0) / Clock option register (0x40190) Turns the low-speed (OSC1) clock output to external devices on or off. B-III Write "1": On Write "0": Off Read: Valid The low-speed (OSC1) clock is output from the FOSC1 pin to an external device by writing "1" to PF1ON. However, for this setting to be effective, the P14 pin must be set for the FOSC1 pin by CFP14 and CFEX0, and output must be set by setting IOC14 (D4/0x402D6 <P1 I/O control register>) to "1". The clock output is disabled by writing "0". Writing to PF1ON is allowed only when CLGP[7:0] is set to "0b10010110". At initial reset, PF1ON is set to "0" (Off). CLGP7-CLGP0: Power-control register protection flag ([D[7:0]) / Power control protection register (0x4019E) These bits remove the protection against writing to addresses 0x40180 and 0x40190. Write "0b10010110": Write protection removed Write other than the above: No operation (write-protected) Read: Valid Before writing to address 0x40180 or 0x40190, set CLGP[7:0] to "0b10010110" to remove the protection against writing to that address. This clearing of write protection is effective for only one writing, so the bits are cleared to "0b00000000" by one writing. Therefore, CLGP[7:0] must be set each time the protected address is written to. At initial reset, CLGP is set to "0b00000000" (write-protected). S1C33L03 FUNCTION PART EPSON B-III-6-7 OSC1 III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT CFP14: P14 function selection (D4) / P1 function select register (0x402D4) Selects the pin function of the P14 I/O port. Write "1": OSC1 clock output pin Write "0": I/O port pin Read: Invalid The P14 pin is set for OSC1 clock output (FOSC1) by writing "1" to CFP14. When this pin is used as the FOSC1 output pin, also set IOC14 (D4/0x402D6 <P1 I/O control register>) to "1" (output). At cold start, CFP14 is set to "0" (I/O port pin). At hot start, CFP14 retains its status from before the initial reset. CFEX0: P12, P14 extended function (D0) / Port function extension register (0x402DF) Sets whether the function of the P14 pin is to be extended. Write "1": DCLK output pin Write "0": P14/FOSC1 output pin Read: Invalid When CFEX0 is set to "1", the P14 pin functions as a debug clock DCLK output pin. When CFEX0 = "0", the CFP14 register becomes effective, so the settings of this register determine whether the P14 pin functions as an P14 I/O port or a FOSC1 output pin. At cold start, CFEX0 is set to "1" (DCLK output pin). At hot start, CFEX0 retains its state from prior to the initial reset. Programming Notes (1) Immediately after the low-speed (OSC1) oscillation circuit is turned on, a certain period of time is required for oscillation to stabilize (3 sec max.). To prevent the device from operating erratically, do not use the clock until its oscillation has stabilized. (2) The oscillation circuit used for the CPU operating clock cannot be turned off. (3) The CPU operating clock can only be switched over when both the OSC3 and OSC1 oscillation circuits are on. Furthermore, when turning off an oscillation circuit that has become unnecessary as a result of the CPU operating clock switchover, be sure to use separate instructions for switchover and oscillation turnoff. If these two operations are processed simultaneously using one instruction, the CPU may operate erratically. (4) If the low-speed (OSC1) oscillation circuit is turned off, all peripheral circuits operated using the OSC1 clock will be inactive. (5) If the OSC3 clock is unnecessary, use the OSC1 clock to operate the CPU and turn the high-speed (OSC3) oscillation circuit off. This helps reduce current consumption. (6) When the P14/FOSC1/DCLK pin is used as the FOSC1 output pin, set IOC14 (D4/0x402D6) to "1" (output) in addition to the CFP14 (D4/0x402D4) and CFEX0 (D0/0x402DF) settings. B-III-6-8 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: CLOCK TIMER A-1 III-7 CLOCK TIMER Configuration of Clock Timer The clock timer consists of an 8-bit binary counter that is clocked by a 256-Hz signal derived from the low-speed (OSC1) oscillation clock fOSC1, and second, minute, hour, and day counters, allowing all data (128 Hz to 1 Hz, seconds, minutes, hours, and day) to be read out in a software. It can also generate an interrupt using a 32-Hz, 8-Hz, 2-Hz, or 1-Hz (1-second) signal or when a one-minute, one-hour, or one-day count is up, in addition to generating an alarm at a specified time (minute or hour) or day. The low-speed (OSC1) oscillation circuit and the clock timer can be kept operating even when the CPU and other internal peripheral circuits are placed in standby mode (HALT or SLEEP). Normally, this clock timer should be used for a clock and various other clocking functions. Figure 7.1 shows the structure of the clock timer. Note: Since the clock timer is driven by a clock originating from the low-speed (OSC1) oscillation circuit, this timer cannot be used unless the low-speed (OSC1) oscillation circuit (32.768 kHz, Typ.) is used. Internal data bus OSC1 fOSC1 oscillation circuit 32.768 kHz Divider 256 Hz 128 64 32 16 8 Clock timer Run/Stop Clock timer reset 4 2 1 Hz Hz Hz Hz Hz Hz Hz Hz 6-bit seconds counter 6-bit minutes counter 5-bit hours counter 16-bit day counter Interrupt generation control circuit B-III Interrupt request (to interrupt controller) Interrupt/alarm select circuit Comparator Comparator Comparator Alarm generation control circuit 6-bit minute 5-bit hour 5-bit day comparison comparison comparison data data data Figure 7.1 Structure of Clock Timer S1C33L03 FUNCTION PART EPSON B-III-7-1 CTM III PERIPHERAL BLOCK: CLOCK TIMER Control and Operation of the Clock Timer Initial setting At initial reset, the clock timer's counter data, setup contents of alarms, and control bits including RUN/STOP, are not initialized. (This does not include the CPU core power on/off flag TCHVOF or OSC1 auto-off flag TCAOFF.) Therefore, when using the clock timer, initialize it as follows: 1. Before you start setting up, stop the clock timer and disable the clock timer interrupt. 2. Reset the counters. 3. Preset the minute, hour, and day data (only when necessary). 4. Select an interrupt factor. 5. Select the alarm function. 6. Enable the interrupt. 7. Start the clock timer. The following shows how to set and control each of the above. For details on interrupt control, refer to "Interrupt Function". Resetting the counters Each counter of the clock timer can only be reset to "0" in the software. Note that they are not reset by an initial reset or the auto-off function. To reset the clock timer, write "1" to TCRST (D1) / Clock timer Run/Stop register (0x40151). Note, however, that this reset input is accepted only when the clock timer is inactive, and is ignored when the timer is operating. Notes: * The clock timer reset bit TCRST and the clock timer RUN/STOP control bit TCRUN are located at the same address (0x40151). However, the clock timer cannot be reset at the same time it is set to RUN by writing "1" to both. In this case, the reset input is ignored and the timer starts counting up from the counter values then in effect. Always make sure TCRUN = "0" before resetting the timer. * When the counters are cleared as the clock timer is reset, an interrupt may be generated depending on the timer settings. Therefore, first disable the clock timer interrupt before resetting the clock timer, and after resetting the clock timer, reset the interrupt factor flag, interrupt factor generation flag, and alarm factor generation flag. Presetting minute, hour, and day data The clock timer's minute, hour, and day counters have a data preset function, enabling the desired time and day to be set. Table 7.1 Presetting the Counters Counter Minute counter Hour counter Day counter Data register Preset value TCHD[5:0] (D[5:0]) / Clock timer minute register (0x40155) TCDD[4:0] (D[4:0]) / Clock timer hour register (0x40156) TCND[15:0](D[7:0]) / Clock timer day (high-order) register (0x40158) (D[7:0]) / Clock timer day (low-order) register (0x40157) 0 to 59 0 to 23 0 to 65535 When using the clock timer as an RTC, be sure to set these counter values before starting operating of the clock timer. For the day counter, set a number of days starting from the reference day (e.g., January 1, 1990). B-III-7-2 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: CLOCK TIMER A-1 RUN/STOP the clock timer The clock timer starts counting when "1" is written to TCRUN (D0) / Clock timer Run/Stop register (0x40151) and stops counting when "0" is written. When the clock timer is made to RUN, the 256-Hz clock input is enabled at a falling edge of the low-speed (OSC1) oscillation clock pulse, and the 8-bit binary counter counts up at each falling edge of this 256-Hz clock. Figure 7.2 shows the operation of the 8-bit binary counter. fOSC1/128 256 Hz TCD0 128 Hz TCD1 64 Hz TCD2 32 Hz TCD3 16 Hz TCD4 8 Hz TCD5 4 Hz TCD6 2 Hz TCD7 1 Hz 32 Hz interrupt 8 Hz interrupt 2 Hz interrupt 1 Hz interrupt Figure 7.2 Timing Chart of 8-Bit Binary Counter The 8-bit binary counter outputs a 1-Hz signal in its final stage. The second counter counts the 1-Hz signal thus output. When it counts 60 seconds, the counter outputs a 60second signal and is reset to 0 seconds. Similarly, the minute and hour counters count 60 minutes and 24 hours, respectively, using the signals output by each preceding counter. The day counter is a 16-bit binary counter and can count up to 65,536 days using the 24-hour signal output by the hour counter. One of the following signals output by each counter can be selected to generate an interrupt: 32 Hz, 8 Hz, 2 Hz, 1 Hz (1 second), 1 minute, 1 hour, 1 day B-III If "0" is written to TCRUN, the clock timer is stopped at a rising edge of the low-speed (OSC1) oscillation clock to prevent device malfunction caused by the concurrent termination of counting (falling edge of the 256-Hz clock). Even when the clock timer is stopped, each counter retains the data set at that point. When the timer is made to RUN again while in that state, each counter restarts counting from the retained value. Reading out counter data The data in each counter can be read out in a software as binary data. Table 7.2 Reading Out Counter Data Counter 1 Hz to 128 Hz Second counter Minute counter Hour counter Day counter Counter data TCD[7:0] (D[7:0]) / Clock timer divider register (0x40153) TCMD[5:0] (D[5:0]) / Clock timer second counter (0x40154) TCHD[5:0] (D[5:0]) / Clock timer minute counter (0x40155) TCDD[4:0] (D[4:0]) / Clock timer hour counter (0x40156) TCND[15:0](D[7:0]) / Clock timer day (high-order) counter (0x40158) (D[7:0]) / Clock timer day (low-order) counter (0x40157) Data is read directly from the counter during operation. For this reason, a counter can overflow while reading data from each counter, so the data thus read may not be exact. For example, if the 8-bit binary counter is read at 0xFF and then overflows before reading the next seconds counter, the value of the seconds counter is its count plus the one second that has elapsed since the 8-bit binary counter was read. To prevent this problem, try reading out each counter several times and make sure data has not been modified. S1C33L03 FUNCTION PART EPSON B-III-7-3 CTM III PERIPHERAL BLOCK: CLOCK TIMER Setting alarm function The clock timer has an alarm function, enabling an interrupt to be generated at a specified time and day. This specification can be made in minutes, hours, and days for each alarm or a combination of multiple alarms. Use TCASE[2:0] (D[4:2) / Clock timer interrupt control register (0x40152) for this specification. Table 7.3 Alarm Factor Selection TCASE2 TCASE1 TCASE0 X X 1 0 X 1 X 0 1 X X 0 Alarm factor Minutes alarm Hours alarm Day alarm None For example, if TCASE is set to "001", only a minutes alarm is enabled and an alarm is generated at a specified minute every hour. If TCASE is set to "111", an alarm is generated on each specified day at each specified hour and minute. If alarms are not to be used, set TCASE to "000". An interrupt can be generated every minute, every hour, and every day through the use of the counter's interrupt function instead of the alarm function. To specify a day, hours, and minutes, use the registers shown below: To specify minutes: TCCH[5:0] (D[5:0]) / Minute-comparison data register (0x40159) 0 to 59 minutes* To specify hours: TCCD[4:0] (D[4:0]) / Hour-comparison data register (0x4015A) 0 to 23 hours* To specify day: TCCN[4:0] (D[4:0]) / Day-comparison data register 0x4015B) 0 to 31 days after The minute-comparison data register (6 bits) and hour-comparison data register (5 bits) can be set for up to 63 minutes and 31 hours, respectively. Note that even when the data set in these registers exceeds 59 minutes or 23 hours, the data is not considered invalid. The values set in these registers are compared with those of each counter, and when they match, the alarm factor generation flag TCAF (D0) / Clock timer interrupt control register (0x40152) is set to "1". If clock timer interrupts have been enabled using the interrupt controller, an interrupt is generated when the flag is set. The day-comparison data register is a 5-bit register, and its value is compared with the five low-order bits of the day counter. Therefore, an alarm can be generated for up to 31 days after the register is set. Interrupt Function Clock timer interrupt factors The clock timer can generate an interrupt using a 32-Hz, 8-Hz, 2-Hz, 1-Hz (1-second), 1-minute, 1-hour, or 1day signal. The interrupt factor to be used from among these signals can be selected using the interrupt factor selection bit TCISE[2:0] (D[7:5]) / Clock timer interrupt control register (0x40152). Table 7.4 Selecting Interrupt Factor TCISE2 TCISE1 TCISE0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 Interrupt factor None 1 day 1 hour 1 minute 1 Hz 2 Hz 8 Hz 32 Hz An interrupt factor is generated at intervals of a selected signal (each falling edge of the signal). If interrupts based on these signals are not to be used, set TCISE to "111". When a selected interrupt factor is generated, the interrupt factor generation flag TCIF (D1) / Clock timer interrupt control register (0x40152) is set to "1". At the same time, the clock timer interrupt factor flag FCTM (D1) / Port input 4-7, clock timer, A/D interrupt factor flag register (0x40287) also is set to "1". At this time, if the interrupt conditions set by the interrupt control registers are met, an interrupt to the CPU is generated. B-III-7-4 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: CLOCK TIMER A-1 An interrupt can be generated on a specified alarm day at a specified time as described in the preceding section. Interrupts generated by a signal and those generated by an alarm can both be used. However, since the clock timer has only one interrupt factor flag, it is the same interrupt that is generated by the timer. Therefore, if both types of interrupts are used, when an interrupt occurs, read the interrupt factor generation flag TCIF and alarm factor generation flag TCAF to determine which factor has generated the interrupt. Once the factor generation flag is set to "1", it remains set until it is reset by writing "1" in the software. After confirming that the flag is set, write "1" to reset it. The interrupt factor generation flag TCIF and alarm factor generation flag TCAF should be reset after at least 4 ms have passed from generation of an interrupt or an alarm. Note: To prevent generation of an unwanted interrupt, disable the clock timer interrupt before selecting the interrupt and alarm factors. Then, before reenabling the interrupt, reset each factor generation flag and the interrupt factor flag. Control registers of the interrupt controller The following lists the clock timer interrupt control registers: Interrupt factor flag: FCTM (D1) / Port input 4-7, clock timer, A/D interrupt factor flag register (0x40287) Interrupt enable: ECTM (D1) / Port input 4-7, clock timer, A/D interrupt enable register (0x40277) Interrupt level: PCTM[2:0] (D[2:0]) / Clock timer interrupt priority register (0x4026B) When an interrupt factor occurs, the clock timer sets the interrupt actor flag to "1" as described above. At this time, if the interrupt enable register bit is set to "1", an interrupt request is generated. Interrupts can be disabled by leaving the interrupt enable register bit reset to "0". The interrupt factor flag is always set to "1" when an interrupt factor is generated, regardless of the setting of the interrupt enable register (even when it is set to "0"). The interrupt priority register sets the priority levels (0 to 7) of interrupts. An interrupt request to the CPU is accepted on the condition that no other interrupt request has been generated that is of a higher priority. It is only when the PSR's IE bit = "1" (interrupts enabled) and the set value of the IL is smaller than the clock timer interrupt level set by the interrupt priority register that a clock timer interrupt request is actually accepted by the CPU. For details on these interrupt control registers, as well as the device operation when an interrupt has occurred, refer to "ITC (Interrupt Controller)". Note that the clock timer interrupt factor does not have a function to invoke an intelligent DMA. B-III Trap vectors The trap vector addresses for the clock-timer interrupt by default are set to 0x0C00104. CTM The trap table base address can be changed using the TTBR registers (0x48134 to 0x48137). S1C33L03 FUNCTION PART EPSON B-III-7-5 III PERIPHERAL BLOCK: CLOCK TIMER Examples of Use of Clock Timer The following shows examples of use of the clock timer and how to control the timer in each case. To use the clock timer as a timer/counter Example in which while the CPU is inactive, the clock timer is kept operating in order to start again the CPU after a specified length of time has elapsed (e.g., three days): 1. Make sure the low-speed (OSC1) oscillation circuit is oscillating stably (SOSC1 = "1"). Wait for approximately three seconds after the oscillation starts for its oscillation to stabilize. 2. Disable the clock timer interrupt using the interrupt controller (ECTM = "0"). 3. Stop the clock timer and set "3 days" in the day-comparison register (TCRUN = "0", TCCN = "3"). 4. Choose a "day-specified alarm" using the alarm-factor select bit and set "none" in the interrupt-factor select bit (TCASE = "100", TCISE = "111"). 5. Reset the interrupt factor and alarm factor generation flags (FCTM = "0", TCAF = "0"). 6. Reenable the clock timer interrupt using the interrupt controller (ECTM = "1"). 7. Switch the CPU operating clock to the low-speed (OSC1) clock (CLKCHG = "0"). 8. Turn off the high-speed (OSC3) oscillation circuit (SOSC3 = "0"). 9. Reset the clock timer (TCRST = "0"). 10. Start the clock timer (TCRUN = "1"). 11. Execute the halt instruction to stop the CPU. : Wait until an interrupt is generated by a day-specified alarm from the clock timer. When an interrupt occurs, the CPU starts up using the OSC1 clock. : 12. If necessary, turn on the high-speed (OSC3) oscillation circuit and change the CPU operating clock back to the OSC3 clock. In the above example, if the device is reset before a three-day period has elapsed, the device operates as follows: * The CPU starts up using the OSC3 clock. * The clock timer counters are not reset. They remain in the RUN state. The time during which the CPU has been idle can be checked by reading out the clock timer counters. For using the clock timer as RTC Example in which the clock timer is kept operating and an alarm is generated at 10:00 A.M. every day: 1. Disable the clock timer interrupt using the interrupt controller (ECTM = "0"). 2. Stop the clock timer (TCRUN = "0"). 3. Reset the clock timer (TCRST = "1"). 4. Set the current day and time in the minute (TCHD), hour (TCDD), and day (TCND) counters. For the day counter, set a number of days starting from the reference day (e.g., January 1, 1990). When the count is read, it is converted into the current date by the software. 5. Set "10:00" in the hour-compare register (TCCD = "0x0A"). 6. Select an a "hour-specified alarm" using the alarm factor select bit, and set "none" in the interrupt factor select bit (TCASE = "010", TCISE = "111"). 7. Reset the interrupt factor and alarm-factor generation flags (FCTM = "1", TCAF = "0"). 8. Reenable the clock timer interrupt using the interrupt controller (ECTM = "1"). 9. Start the clock timer (TCRUN = "1"). : The clock timer is made to generate an interrupt at 10:00 every day by an hour-specified alarm. : In the above example, if any interrupt factor other than an alarm is selected, an interrupt is also generated by that interrupt factor. To determine which factor caused the interrupt generated, read the interrupt factor generation flag TCIF and alarm factor generation flag TCAF. If TCAF is set to 1, the interrupt has been caused by an alarm. If you select an interrupt factor (other than a 1-day factor) along with the hour-specified alarm, the selected interrupt factor occurs at the same time as the alarm factor. B-III-7-6 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: CLOCK TIMER A-1 I/O Memory of Clock Timer Table 7.5 shows the control bits of the clock timer. Table 7.5 Control Bits of Clock Timer Register name Address Clock timer Run/Stop register 0040151 (B) Clock timer 0040152 interrupt (B) control register Bit Name D7-2 - D1 TCRST D0 TCRUN Function reserved Clock timer reset Clock timer Run/Stop control Setting Init. R/W - 1 Reset 1 Run Remarks - X X - 0 when being read. W 0 when being read. R/W X X X R/W X X X R/W X X R/W Reset by writing 1. R/W Reset by writing 1. Low Low Low Low Low Low Low Low X X X X X X X X R R R R R R R R - X X X X X X - R 0 Invalid 0 Stop D7 D6 D5 TCISE2 TCISE1 TCISE0 D4 D3 D2 TCASE2 TCASE1 TCASE0 D1 D0 TCIF TCAF TCISE[2:0] Interrupt factor 1 1 1 None 1 1 0 Day 1 0 1 Hour 1 0 0 Minute 0 1 1 1 Hz 0 1 0 2 Hz 0 0 1 8 Hz 0 0 0 32 Hz Alarm factor Clock timer alarm factor selection TCASE[2:0] 1 X X Day X 1 X Hour X X 1 Minute 0 0 0 None 1 Generated 0 Not generated Interrupt factor generation flag 1 Generated 0 Not generated Alarm factor generation flag D7 D6 D5 D4 D3 D2 D1 D0 TCD7 TCD6 TCD5 TCD4 TCD3 TCD2 TCD1 TCD0 Clock timer data 1 Hz Clock timer data 2 Hz Clock timer data 4 Hz Clock timer data 8 Hz Clock timer data 16 Hz Clock timer data 32 Hz Clock timer data 64 Hz Clock timer data 128 Hz D7-6 D5 D4 D3 D2 D1 D0 - TCMD5 TCMD4 TCMD3 TCMD2 TCMD1 TCMD0 reserved Clock timer second counter data TCMD5 = MSB TCMD0 = LSB - 0 to 59 seconds Clock timer 0040155 minute register (B) D7-6 D5 D4 D3 D2 D1 D0 - TCHD5 TCHD4 TCHD3 TCHD2 TCHD1 TCHD0 reserved Clock timer minute counter data TCHD5 = MSB TCHD0 = LSB - 0 to 59 minutes - X X X X X X - 0 when being read. R/W Clock timer hour register D7-5 D4 D3 D2 D1 D0 - TCDD4 TCDD3 TCDD2 TCDD1 TCDD0 reserved Clock timer hour counter data TCDD4 = MSB TCDD0 = LSB - 0 to 23 hours - X X X X X - 0 when being read. R/W Clock timer 0040157 day (low-order) (B) register D7 D6 D5 D4 D3 D2 D1 D0 TCND7 TCND6 TCND5 TCND4 TCND3 TCND2 TCND1 TCND0 Clock timer day counter data (low-order 8 bits) TCND0 = LSB 0 to 65535 days (low-order 8 bits) X X X X X X X X R/W Clock timer day (highorder) register D7 D6 D5 D4 D3 D2 D1 D0 TCND15 TCND14 TCND13 TCND12 TCND11 TCND10 TCND9 TCND8 Clock timer day counter data (high-order 8 bits) TCND15 = MSB 0 to 65535 days (high-order 8 bits) X X X X X X X X R/W Clock timer 0040153 divider register (B) Clock timer second register 0040154 (B) 0040156 (B) 0040158 (B) S1C33L03 FUNCTION PART Clock timer interrupt factor selection EPSON 1 1 1 1 1 1 1 1 High High High High High High High High 0 0 0 0 0 0 0 0 0 when being read. B-III CTM B-III-7-7 III PERIPHERAL BLOCK: CLOCK TIMER Register name Address Clock timer minute comparison register 0040159 (B) Clock timer hour comparison register Clock timer day comparison register Bit D7-6 D5 D4 D3 D2 D1 D0 Name - TCCH5 TCCH4 TCCH3 TCCH2 TCCH1 TCCH0 Function reserved Clock timer minute comparison data TCCH5 = MSB TCCH0 = LSB Setting Init. R/W Remarks - 0 to 59 minutes (Note) Can be set within 0-63. - X X X X X X - 0 when being read. R/W 004015A D7-5 - (B) D4 TCCD4 D3 TCCD3 D2 TCCD2 D1 TCCD1 D0 TCCD0 reserved - 0 to 23 hours Clock timer hour comparison data (Note) Can be set within 0-31. TCCD4 = MSB TCCD0 = LSB - X X X X X - 0 when being read. R/W 004015B D7-5 - (B) D4 TCCN4 D3 TCCN3 D2 TCCN2 D1 TCCN1 D0 TCCN0 reserved Clock timer day comparison data TCCN4 = MSB TCCN0 = LSB - 0 to 31 days - X X X X X - 0 when being read. R/W Compared with TCND[4:0]. - 0 to 7 - X X X - Writing 1 not allowed. R/W - - 0 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W R/W - X X X X X X - 0 when being read. R/W R/W R/W R/W R/W R/W Clock timer 004026B D7-3 - interrupt (B) D2 PCTM2 priority register D1 PCTM1 D0 PCTM0 reserved Clock timer interrupt level Port input 4-7, 0040277 clock timer, (B) A/D interrupt enable register D7-6 D5 D4 D3 D2 D1 D0 - EP7 EP6 EP5 EP4 ECTM EADE reserved Port input 7 Port input 6 Port input 5 Port input 4 Clock timer A/D converter Port input 4-7, 0040287 clock timer, A/D (B) interrupt factor flag register D7-6 D5 D4 D3 D2 D1 D0 - FP7 FP6 FP5 FP4 FCTM FADE reserved Port input 7 Port input 6 Port input 5 Port input 4 Clock timer A/D converter 1 Enabled 0 Disabled - 1 Factor is generated 0 No factor is generated TCRST: Clock timer reset (D1) / Clock timer Run/Stop register (0x40151) Resets the clock timer. Write "1": The clock timer is reset Write "0": Invalid Read: Always "0" The clock timer is reset by writing "1" to TCRST when the timer is inactive. All timer counters are cleared to "0". The clock timer cannot be reset when in the RUN state, nor can it be reset at the same time it is made to RUN through the execution of one write to address 0x40151. (The clock timer is started, but not reset.) In this case, first reset the clock timer and then use another instruction to RUN the clock timer. When the counters are cleared as the clock timer is reset, an interrupt may be generated, depending on the register settings. Therefore, before resetting the clock timer, first disable the clock timer interrupt, and after resetting the clock timer, reset the interrupt factor flag and the interrupt factor and alarm factor generation flags. Writing "0" to TCRST results in No Operation. Since this TCRST is a write-only bit, its value when read is always "0". The clock timer is not reset by an initial reset. B-III-7-8 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: CLOCK TIMER A-1 TCRUN: Clock timer RUN/STOP control (D0) / Clock timer Run/Stop register (0x40151) Controls the RUN/STOP of the clock timer. Write "1": RUN Write "0": STOP Read: Valid The clock timer is made to start counting by writing "1" to the TCRUN register and made to stop by writing "0". The timer data is retained even in the STOP state. The timer can also be made to start counting from the retained data by changing its state from STOP to RUN. The TCRUN register is not initialized at initial reset. TCD7-TCD0: TCMD5-TCMD0: TCHD5-TCHD0: TCDD4-TCDD0: TCND15-TCND0: 1-128 Hz counter data (D[7:0]) / Clock timer divider register (0x40153) Second counter data (D[5:0]) / Clock timer second register (0x40154) Minute counter data (D[5:0]) / Clock timer minute register (0x40155) Hour counter data (D[4:0]) / Clock timer hour register (0x40156) Day counter data (D[7:0]) / Clock timer day (high-order) register (0x40158) (D[7:0]) / Clock timer day (low-order) register (0x40157) Data can be read out from each counter. The minute, hour, and day counters allow data to be written to, in addition to being read out. The 1-128 Hz counter and seconds counter are read-only, so writing to these registers is ignored. The unused high-order bits at each address of the second, minute, and hour counter data are always "0" when read out. The counter data is not initialized at initial reset. TCCH5-TCCH0: Minute-comparison data (D[5:0]) / Clock timer minute-comparison register (0x40159) TCCD4-TCCD0: Hour-comparison data (D[4:0]) / Clock timer hour-comparison register (0x4015A) TCCN4-TCCN0: Day-comparison data (D[4:0]) / Clock timer day-comparison register (0x4015B) Set a day on which and a time at which an alarm is to be generated. The comparison data register corresponding to the alarm factor selected using the TCASE register is compared with the counter data, and when the data matches, an alarm interrupt request is generated. The day-comparison data is compared with the 5 low-order bits of the day counter. Each register can be read out. These registers are not initialized at initial reset. TCISE2-TCISE0: Interrupt factor selection (D[7:5]) / Clock timer interrupt control register (0x40152) Selects the factor for which the clock timer interrupt is to be generated. CTM Table 7.6 Selecting Interrupt Factor TCISE2 TCISE1 TCISE0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 Interrupt factor None 1 day 1 hour 1 minute 1 Hz 2 Hz 8 Hz 32 Hz When the clock timer interrupt is enabled, an interrupt is generated cyclically at each falling edge of the selected signal. If you the interrupt caused by these factors is not be used set TCISE to "111". TCISE is not initialized at initial reset. S1C33L03 FUNCTION PART EPSON B-III B-III-7-9 III PERIPHERAL BLOCK: CLOCK TIMER TCASE2-TCASE0: Alarm factor select register (D[4:2]) / Clock timer interrupt control register (0x40152) Selects the factor for which an alarm is to be generated. Table 7.7 Selecting Alarm Factor TCASE2 TCASE1 TCASE0 X X 1 0 X 1 X 0 1 X X 0 Alarm factor Minute alarm Hour alarm Day alarm None Use the TCASE2, TCASE1, and TCASE0 bits to select a day, hour, and minute alarm, respectively. It is therefore possible to select multiple alarm factors. When one of these bits is set to "1", the contents of the comparison data register that corresponds to the selected alarm factor is compared with the counter. If the comparison data of all selected alarm factors matches the counter data, an alarm interrupt request is generated. The comparison data register from which the alarm factor is unselected by writing "0" is not compared with the counter data. TCASE is not initialized at initial reset. TCIF: Interrupt factor generation flag (D1) / Clock timer interrupt control register (0x40152) Indicates whether an interrupt factor has occurred. Read "1": Read "0": Write "1": Write "0": Interrupt factor has occurred No interrupt factor has occurred Flag is reset Invalid TCIF is set to "1" when an interrupt factor selected using TCISE occurs. Since there is only one source for the clock timer interrupt, use this flag to differentiate it from interrupts caused by an alarm. Once set to "1", TCIF remains set until it is reset by writing "1". TCIF is not initialized at initial reset. This bit does not affect generation of an interrupt even if it is set to "1" or "0". TCAF: Alarm factor generation flag (D0) / Clock timer interrupt control register (0x40152) Indicates whether an alarm factor has occurred. Read "1": Read "0": Write "1": Write "0": Alarm factor has occurred No alarm factor has occurred Flag is reset Invalid TCAF is set to "1" when all alarm factors selected using the TCASE register occur. Since there is only one source for the clock timer interrupt, use this flag to differentiate it from interrupts due to other interrupt factors. Once set to "1", TCAF remains set until it is reset by writing "1". TCAF is not initialized at initial reset. This bit does not affect generation of an alarm even if it is set to "1" or "0". PCTM2-PCTM0: Clock timer interrupt level (D[2:0]) / Clock timer interrupt priority register (0x4026B) Sets the priority level of the clock timer interrupt between 0 and 7. At initial reset, PCTM becomes indeterminate. B-III-7-10 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: CLOCK TIMER A-1 ECTM: Clock timer interrupt enable (D1) / Port input 4-7, clock timer, A/D interrupt enable register (0x40277) Enables or disables generation of an interrupt to the CPU. Write "1": Interrupt enabled Write "0": Interrupt disabled Read: Valid This bit controls the clock timer interrupt. The interrupt is enabled by setting ECTM to "1" and is disabled by setting it to "0". At initial reset, ECTM is set to "0" (interrupt disabled). FCTM: Clock timer interrupt factor flag (D1) / Port input 4-7, clock timer, A/D interrupt factor flag register (0x40287) Indicates whether the clock timer interrupt factor has occurred. When read Read "1": Interrupt factor has occurred Read "0": No interrupt factor has occurred When written using the reset-only method (default) Write "1": Interrupt factor flag is reset Write "0": Invalid When written using the read/write method Write "1": Interrupt flag is set Write "0": Interrupt flag is reset FCTM is set to "1" when the selected interrupt factor or alarm factor occurs. At this time, if the following conditions are met, an interrupt to the CPU is generated: 1. The corresponding interrupt enable register bit is set to "1". 2. No other interrupt request of a higher interrupt priority is generated. 3. The IE bit of the PSR is set to "1" (interrupt enabled). 4. The corresponding interrupt priority register is set to a value higher than the CPU interrupt level (IL). The interrupt factor flag is always set to "1" when an interrupt factor occurs, no matter how the interrupt enable and interrupt priority registers are set. For the next interrupt to be accepted after an interrupt has occurred, it is necessary that the interrupt factor flag be reset, and that the PSR be set again (by setting the IE bit to "1" after setting the IL to a value lower than the level indicated by the interrupt priority register, or by executing the reti instruction). The interrupt factor flag can be reset only by writing to it in the software. Note that if the PSR is set again to accept generated interrupts (or if the reti instruction is executed) without the interrupt factor flag being reset, the same interrupt occurs again. Note also that the value to be written to reset the flag is "1" when the reset-only method (RSTONLY = "1") is used, and "0" when the read/write method (RSTONLY = "0") is used. The FCTM flag becomes indeterminate at initial reset, so be sure to reset it in the software. S1C33L03 FUNCTION PART EPSON B-III-7-11 B-III CTM III PERIPHERAL BLOCK: CLOCK TIMER Programming Notes (1) The low-speed (OSC1) oscillation circuit, which is the clock source for the clock timer, requires a muxmum of three seconds for its oscillation to stabilize after it is started up. Therefore, immediately after power-on, wait until the oscillation stabilizes before starting the clock timer. (2) At initial reset, the clock timer counter data, the setup contents of alarms, and control bits, including RUN/STOP, are not initialized. Therefore, always initialize the clock timer in the software following poweron. (3) The clock timer reset bit TCRST and the clock timer RUN/STOP control bit TCRUN are located at the same address (0x40151). However, the clock timer cannot be reset at the same time it is set to RUN by writing "1" to both. In this case, the reset input is ignored and the timer starts counting up from the counter values then in effect. When resetting the timer, always make sure TCRUN = "0" (timer stopped). (4) When the counters are cleared as the clock timer is reset, an interrupt may be generated depending on the register settings. Therefore, before resetting the clock timer, first disable the clock timer interrupt and, after resetting the clock timer, reset the interrupt factor flag and the interrupt factor generation and alarm factor generation flags. (5) To prevent generation of an unwanted interrupt, disable the clock timer interrupt before selecting the interrupt and alarm factors. Then, before reenabling the interrupt, reset each factor generation flag and the interrupt factor flag. (6) The interrupt factor flag (FCTM) becomes indeterminate at initial reset. To prevent generation of an unwanted interrupt, be sure to reset the flag in a program. (7) To prevent regeneration of interrupts with the same factor after an interrupt has occurred, be sure to reset the interrupt factor flag (FCTM) before setting the PSR again or executing the reti instruction. B-III-7-12 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 III-8 SERIAL INTERFACE Configuration of Serial Interfaces Features of Serial Interfaces The Peripheral Block contains four channels (Ch.0, Ch.1, Ch.2 and Ch.3) of serial interfaces, the features of which are described below. The functions of these four serial interfaces are the same. * A clock-synchronized or asynchronous mode can be selected for the transfer method. Clock-synchronized mode Data length: 8 bits, fixed (No start, stop, and parity bits) Receive error: An overrun error can been detected. Asynchronous mode Data length: 7 or 8 bits, selectable Receive error: Overrun, framing, or parity errors can been detected. Start bit: 1 bit, fixed Stop bit: 1 or 2 bits, selectable Parity bit: Even, odd, or none; selectable Since the transmit and receive units are independent, full-duplex communication is possible. * Baud-rate setting: Any desired baud rate can be set by selecting the prescaler's division ratio, setting the 8-bit programmable timer, or using external clock input (asynchronous mode only). * The receive and transmit units are constructed with a double-buffer structure, allowing for successive receive and transmit operations. * Data transfers using IDMA or HSDMA are possible. * Three types of interrupts (transmit data empty, receive data full, and receive error) can be generated. Figure 8.1 shows the configuration of the serial interface (one channel). B-III Internal data bus Control registers Transmit unit Receive unit SOUTx Serial output control circuit Data buffer and shift register Data buffer and shift register SINx Serial input control circuit Transmit data buffer empty interrupt request Interrupt control circuit Receive error interrupt request Ready signal control circuit Start bit detection circuit Clock control circuit Receive data buffer full interrupt request #SRDYx SIF 8-bit programmable timer output #SCLKx Figure 8.1 Configuration of Serial Interface Note: Ch.0 to Ch.3 have the same configuration and the same function. The signal and control bit names are suffixed by a 0, 1, 2, or 3 to indicate the channel number, enabling discrimination between channels 0 to 3. In this manual, however, channel numbers 0 to 3 are replaced with "x" unless discrimination is necessary, because explanations are common to all four channels. S1C33L03 FUNCTION PART EPSON B-III-8-1 III PERIPHERAL BLOCK: SERIAL INTERFACE I/O Pins of Serial Interface Table 8.1 lists the I/O pins used by the serial interface. Table 8.1 Serial-Interface Pin Configuration Pin name I/O P00/SIN0 P01/SOUT0 P02/#SCLK0 P03/#SRDY0 P04/SIN1/ #DMAACK2 P05/SOUT1/ #DMAEND2 P06/#SCLK1/ #DMAACK3 P07/#SRDY1/ #DMAEND3 P27/TM5/SIN2 I/O I/O I/O I/O I/O P26/TM4/SOUT2 I/O P25/TM3/#SCLK2 I/O P24/TM2/#SRDY2 I/O P33/#DMAACK1/ SIN3 P16/EXCL5/ #DMAAND1/ SOUT3 P15/EXCL4/ #DMAAND0/ #SCLK3 P32/#DMAACK0/ #SRDY3 I/O I/O I/O I/O I/O I/O Function Function select bit I/O port / Serial IF Ch.0 data input I/O port / Serial IF Ch.0 data output I/O port / Serial IF Ch.0 clock input/output I/O port / Serial IF Ch.0 ready input/output I/O port / Serial IF Ch.1 data input / #DMAACK2 signal output I/O port / Serial IF Ch.1 data output / #DMAEND2 signal output I/O port / Serial IF Ch.1 clock input/output / #DMAACK3 signal output I/O port / Serial IF Ch.1 ready input/output / #DMAEND3 signal output I/O port / Serial IF Ch.2 data input CFP00(D0)/P0 function select register(0x402D0) CFP01(D1)/P0 function select register(0x402D0) CFP02(D2)/P0 function select register(0x402D0) CFP03(D3)/P0 function select register(0x402D0) CFP04(D4)/P0 function select register(0x402D0) CFEX4(D4)/Port function extension register(0x402DF) CFP05(D5)/P0 function select register(0x402D0) CFEX5(D5)/Port function extension register(0x402DF) CFP06(D6)/P0 function select register(0x402D0) CFEX6(D6)/Port function extension register(0x402DF) CFP07(D7)/P0 function select register(0x402D0) CFEX7(D7)/Port function extension register(0x402DF) CFP27(D7)/Function select register(0x402D8) SSIN2(D0)/Function select register(0x402DB) I/O port / Serial IF Ch.2 data output CFP26(D6)/Function select register(0x402D8) SSOUT2(D1)/Function select register(0x402DB) I/O port / Serial IF Ch.2 serial clock input/output CFP25(D5)/Function select register(0x402D8) SSCLK2(D2)/Function select register(0x402DB) I/O port / Serial IF Ch.2 ready input/output CFP24(D4)/Function select register(0x402D8) SSRDY2(D3)/Function select register(0x402DB) I/O port / Serial IF Ch.3 data input CFP33(D3)/Function select register(0x402DC) SSIN3(D0)/Function select register(0x402D7) I/O port / Serial IF Ch.3 data output CFP16(D6)/Function select register(0x402D4) SSOUT3(D1)/Function select register(0x402D7) I/O I/O port / Serial IF Ch.3 serial clock input/output CFP15(D5)/Function select register(0x402D4) SSCLK3(D2)/Function select register(0x402D7) I/O I/O port / Serial IF Ch.3 ready input/output CFP32(D2)/Function select register(0x402DC) SSRDY3(D3)/Function select register(0x402D7) SINx (serial-data input pin) This pin is used to input serial data to the device, regardless of the transfer mode. SOUTx (serial-data output pin) This pin is used to output serial data from the device, regardless of the transfer mode. #SCLKx (clock input/output pin) This pin is used to input or output a clock. In the clock-synchronized slave mode, it is used as a clock input pin; in the clock-synchronized master mode, it is used as a clock output pin. In the asynchronous mode, this pin is used as clock input when an external clock is used. This pin is not used when the internal clock is used, so it can be used as an I/O port. #SRDYx (ready-signal input/output pin) This pin is used to input or output the ready signal that is used in the clock-synchronized mode. In the clock-synchronized slave mode, it is used as a ready-signal output pin; in the clock-synchronized master mode, it is used as a ready-signal input pin. This pin is not used in the asynchronous mode, so it can be used as an I/O port. Method for setting the serial-interface input/output pins All of the pins used in the serial interface are shared with I/O ports. At cold start, they are all set for I/O port pins P0x (function select bit Pxx, CFPxx = "0"). When using the serial interface, make function select bit settings for the pins used, according to the channel and transfer mode to be used. At hot start, the pins retain their status from prior to the reset. B-III-8-2 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 Setting Transfer Mode The transfer mode of the serial interface can be set using SMDx[1:0] individually for each channel as shown in Table 8.2 below. Table 8.2 Transfer Mode SMDx1 SMDx0 Transfer mode 1 1 0 0 1 0 1 0 8-bit asynchronous mode 7-bit asynchronous mode Clock-synchronized slave mode Clock-synchronized master mode At initial reset, SMDx becomes indeterminate, so be sure to initialize it in the software. When using the IrDA interface, set the transfer mode for the asynchronous 7-bit or asynchronous 8-bit mode. The input/output pins are configured differently, depending on the transfer mode. The pin configuration in each mode is shown in Table 8.3. Table 8.3 Pin Configuration by Transfer Mode Transfer mode SINx SOUTx #SCLKx #SRDYx 8-bit asynchronous 7-bit asynchronous Clock-synchronized slave Clock-synchronized master Data input Data input Data input Data input Data output Data output Data output Data output Clock input/P port Clock input/P port Clock input Clock output P port P port Ready output Ready input All four pins are used in the clock-synchronized mode. In the asynchronous mode, since #SRDYx is unused, P03 (or P07, P24, P23) can be used as an I/O (P) port. In addition, when an external clock is not used, P02 (or P06, P25, P15) can also be used as an I/O port. The I/O control and data registers for the I/O ports used in the serial interface can be used as general-purpose read/write registers. B-III Note: To enable the IrDA interface to be set, IRMDx[1:0] (D[1:0]) / Serial I/F IrDA register (Ch.0: 0x401E4, Ch.1: 0x401E9, Ch.2: 0x401F4, Ch.3: 0x401F9) is provided. Since these bits become indeterminate at initial reset, be sure to initialize them by writing "00" when using as the normal interface or "10" when using as the IrDA interface. SIF S1C33L03 FUNCTION PART EPSON B-III-8-3 III PERIPHERAL BLOCK: SERIAL INTERFACE Clock-Synchronized Interface Outline of Clock-Synchronized Interface In the clock-synchronized transfer mode, 8 bits of data are synchronized to the common clock on both the transmit and receive sides when the data is transferred. Since the transmit and receive units both have a double-buffer structure, successive transmit and receive operations are possible. Since the clock line is shared between the transmit and receive units, the communication mode is half-duplex. Master and slave modes Either the clock-synchronized master mode or the clock-synchronized slave mode can be selected using SMDx[1:0]. Clock-synchronized master mode (SMDx[1:0] = "00") In this mode, clock-synchronized 8-bit serial transfers, in which the serial interface functions as the master, can be performed using the internal clock to synchronize the operation of the internal shift registers. The synchronizing clock is output from the #SCLKx pin, enabling an external (slave side) serial input/output device to be controlled. The #SRDYx pin is also used to input a signal that indicates whether the external serial input/output device is ready to transmit or receive (when ready in a low level). Clock-synchronized slave mode (SMDx[1:0] = "01") In this mode, clock-synchronized 8-bit serial transfers, in which the serial interface functions as a slave, can be performed using the synchronizing clock that is supplied by an external (master side) serial input/output device. The synchronizing clock is input from the #SCLKx pin for use as the synchronizing clock of the serial interface. In addition, a #SRDYx signal indicating whether the serial interface is ready to transmit or receive (when ready in a low level) is output from the #SRDYx pin. Figure 8.2 shows an example of how the input/output pins are connected in the clock-synchronized mode. S1C33 External serial device SINx S1C33 Data input External serial device SINx Data input SOUTx Data output SOUTx Data output #SCLKx Clock input #SCLKx Clock output #SRDYx Ready output #SRDYx Ready input (1) Master mode (2) Slave mode Figure 8.2 Example of Connection in Clock-Synchronized Mode Clock-synchronized transfer data format In clock-synchronized transfers, the data format is fixed as shown below. Data length: 8 bits Start bit: None Stop bit: None Parity bit: None #SCLKx Data LSB MSB D0 D1 D2 D3 D4 D5 D6 D7 Figure 8.3 Clock-Synchronized Transfer Data Format Serial data is transmitted and received starting with the LSB. B-III-8-4 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 Setting Clock-Synchronized Interface When performing clock-synchronized transfers via the serial interface, the following settings must be made before data transfer is actually begun: 1. Setting input/output pins 2. Setting the interface mode 3. Setting the transfer mode 4. Setting the input clock 5. Setting interrupts and IDMA/HSDMA The following explains the content of each setting. For details on interrupt/DMA settings, refer to "Serial Interface Interrupts and DMA". Note: Always make sure the serial interface is inactive (TXENx and RXENx = "0") before these settings are made. A change of settings during operation may cause a malfunction. Setting input/output pins All four pins--SINx, SOUTx, #SCLKx, and #SRDYx--are used in the clock-synchronized mode. When using Ch.0, set CFP0[3:0] (D[3:0]) / P0 function select register (0x402D0) to "1111" and when using Ch.1, set CFP0[7:4] (D[7:4]) to "1111". When using Ch.2, set D[3:0] / Port SIO function extension register (0x402DB) to "1111", and when using Ch.3, set D[3:0] / Port SIO function extension register (0x402D7) to "1111". (It is possible to use both channels.) Setting the interface mode IRMDx[1:0] (D[1:0]) / Serial I/F Ch.0 IrDA register (0x401E4), Serial I/F Ch.1 IrDA register (0x401E9), Serial I/F Ch.2 IrDA register (0x401F4) or Serial I/F Ch.3 IrDA register (0x401F9) is used to set the interface mode (normal or IrDA interface). Write "00" to IRMDx[1:0] to choose the ordinary interface. Since IRMDx[1:0] becomes indeterminate at initial reset, it must be initialized. B-III Setting the transfer mode Use SMDx to set the transfer mode of the serial interface as described earlier. When using the serial interface as the master for clock-synchronized transfer, set SMDx[1:0] to "00"; when using the serial interface as a slave, set SMDx[1:0] to "01". Setting the input clock * Clock-synchronized master mode This mode operates using an internally derived clock. The clock source for each channel is as follows: Ch.0: A clock output by 8-bit programmable timer 2 Ch.1: A clock output by 8-bit programmable timer 3 Ch.2: A clock output by 8-bit programmable timer 4 Ch.3: A clock output by 8-bit programmable timer 5 SIF Therefore, in order for the serial interface to be used in the clock-synchronized master mode, the following conditions must be met: 1. The prescaler is feeding a clock to 8-bit programmable timer 2 (3). 2. The 8-bit programmable timer 2 (3) is generating a clock. Any desired clock frequency can be selected by setting the division ratio of the prescaler and the reload data of the 8-bit programmable timer as necessary. The relationship between the contents of these settings and the transfer rate is expressed by Eq. 1 below. To ensure that the duty ratio of the clock to be fed to the serial interface is 50%, the 8-bit programmable timer further divides the underflow signal frequency by 2 internally. This 1/2 frequency division is factored into Eq. 1. S1C33L03 FUNCTION PART EPSON B-III-8-5 III PERIPHERAL BLOCK: SERIAL INTERFACE RLD = fPSCIN x pdr - 1 2 x bps RLD: fPSCIN: bps: pdr: (Eq. 1) Reload data register setup value of the 8-bit programmable timer Prescaler input clock frequency (Hz) Transfer rate (bits/second) Division ratio of the prescaler Note: The division ratios selected by the prescaler differ between 8-bit programmable timers 2 and 3, so be careful when setting the ratio. 8-bit programmable timer 2, 4: 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/2048, 1/4096 8-bit programmable timer 3, 5: 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256 For details on how to control the prescaler and 8-bit programmable timers, refer to "Prescaler", and "8-Bit Programmable Timers". The serial-interface control register contains an SSCKx bit to select the clock source used for the asynchronous mode. Although this bit does not affect the clock in the clock-synchronized mode, its content becomes indeterminate at initial reset. Therefore, be sure to initialize this bit by writing "0" (Internal clock), even when using the serial interface in the clock-synchronized master mode. * Clock-synchronized slave mode This mode operates using the clock that is output by the external master. This clock is input from the #SCLK pin. Therefore, there is no need to control the prescaler or 8-bit programmable timer. Initialize SSCKx by writing "1" (#SCLKx). B-III-8-6 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 Control and Operation of Clock-Synchronized Transfer Transmit control (1) Enabling transmit operation Use the transmit-enable bit TXENx for transmit control. Ch.0 transmit-enable: TXEN0 (D7) / Serial I/F Ch.0 control register (0x401E3) Ch.1 transmit-enable: TXEN1 (D7) / Serial I/F Ch.1 control register (0x401E8) Ch.2 transmit-enable: TXEN2 (D7) / Serial I/F Ch.2 control register (0x401F3) Ch.3 transmit-enable: TXEN3 (D7) / Serial I/F Ch.3 control register (0x401F8) When transmit is enabled by writing "1" to this bit, the clock input to the shift register is enabled (ready for input), thus allowing for data to be transmitted. The synchronizing clock input/output of the #SCLKx pin is also enabled (ready for input/output). Transmit is disabled by writing "0" to TXENx. After the function select register is set for the serial interface, the I/O direction of the #SRDY and #SCLK pins are changed at follows: #SRDY: When slave mode is set, a switch is made to output mode. Otherwise, input mode is maintained. #SCLK: When master mode is set, a switch is made to output mode. Otherwise, input mode is maintained. Note: In clock-synchronized transfers, the clock line is shared between the transmit and receive units, so the communication mode is half-duplex. Therefore, TXENx and receive-enable bit RXENx cannot be enabled simultaneously. When transmitting data, fix RXENx at "0" and do not change it during a transmit operation. In addition, make sure TXENx is not set to "0" during a transmit operation. (2) Transmit procedure The serial interface contains a transmit shift register and a transmit data register (transmit data buffer), which are provided independently of those used for a receive operation. Ch.0 transmit data: TXD0[7:0] (D[7:0]) / Serial I/F Ch.0 transmit data register (0x401E0) Ch.1 transmit data: TXD1[7:0] (D[7:0]) / Serial I/F Ch.1 transmit data register (0x401E5) Ch.2 transmit data: TXD2[7:0] (D[7:0]) / Serial I/F Ch.2 transmit data register (0x401F0) Ch.3 transmit data: TXD3[7:0] (D[7:0]) / Serial I/F Ch.3 transmit data register (0x401F5) The serial interface contains a status bit to indicate the status of the transmit data register. Ch.0 transmit data buffer empty: TDBE0 (D1) / Serial I/F Ch.0 status register (0x401E2) Ch.1 transmit data buffer empty: TDBE1 (D1) / Serial I/F Ch.1 status register (0x401E7) Ch.2 transmit data buffer empty: TDBE2 (D1) / Serial I/F Ch.2 status register (0x401F2) Ch.3 transmit data buffer empty: TDBE3 (D1) / Serial I/F Ch.3 status register (0x401F7) This bit is reset to "0" by writing data to the transmit-data register, and set to "1" again (buffer empty) when the data is transferred to the shift register. The serial interface starts transmitting when data is written to the transmit data register. The transfer status can be checked using the transmit-completion flag (TENDx). Ch.0 transmit-completion flag: TEND0 (D5) / Serial I/F Ch.0 status register (0x401E2) Ch.1 transmit-completion flag: TEND1 (D5) / Serial I/F Ch.1 status register (0x401E7) Ch.2 transmit-completion flag: TEND2 (D5) / Serial I/F Ch.2 status register (0x401F2) Ch.3 transmit-completion flag: TEND3 (D5) / Serial I/F Ch.3 status register (0x401F7) This bit goes "1" when data is being transmitted and goes "0" when the transmission has completed. When data is transmitted successively in clock-synchronized master mode, TENDx maintains "1" until all data is transmitted (Figure 8.4). In slave mode, TENDx goes "0" every time 1-byte data is transmitted (Figure 8.5). Following explains transmit operation in both the master and slave modes. S1C33L03 FUNCTION PART EPSON B-III-8-7 B-III SIF III PERIPHERAL BLOCK: SERIAL INTERFACE * Clock-synchronized master mode The timing at which the device starts transmitting in the master mode is as follows: When #SRDY is on a low level while TDBEx = "0" (the transmit-data register contains data written to it) or when TDBEx is set to "0" (data has been written to the transmit-data register) while #SRDY is on a low level. Figure 8.4 shows a transmit timing chart in the clock-synchronized master mode. #SCLKx A #SRDYx SOUTx TDBEx D0 B B D1 D2 C D3 D4 D5 D6 D7 D0 D1 D2 D6 D7 D TENDx Transmit-buffer empty interrupt request Transmit-buffer empty interrupt request A Slave device receives the LSB. B Slave device receives the MSB. C First data is written. D Next data is written. Figure 8.4 Transmit Timing Chart in Clock-Synchronized Master Mode 1. If the #SRDYx signal from the slave is on a high level, the master waits until it is on a low level (ready to receive). 2. If #SRDYx is on a low level, the synchronizing clock input to the serial interface begins. The synchronizing clock is also output from the #SCLKx pin to the slave device. 3. The content of the data register is transferred to the shift register synchronously with the first falling edge of the clock. At the same time, the LSB of the data transferred to the shift register is output from the SOUTx pin. 4. The data in the shift register is shifted 1 bit by the next falling edge of the clock, and the bit following the LSB is output from SOUTx. This operation is repeated until all 8 bits of data are transmitted. The slave device must take in each bit synchronously with the rising edges of the synchronizing clock. * Clock-synchronized slave mode Figure 8.5 shows a transmit timing chart in the clock-synchronized slave mode. #SCLKx SOUTx D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D6 D7 #SRDYx TDBEx A B TENDx Transmit-buffer empty interrupt request Transmit-buffer empty interrupt request A First data is written. B Next data is written. Figure 8.5 Transmit Timing Chart in Clock-Synchronized Slave Mode 1. After setting the #SRDYx signal to a low level (ready to transmit), the slave waits for clock input from the master. 2. When the synchronizing clock is input from the #SCLKx pin, the content of the data register is transferred to the shift register synchronously with the first falling edge of the clock. At the same time, the LSB of the data transferred to the shift register is output from the SOUTx pin. The #SRDYx signal is returned to a high level at this point. B-III-8-8 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 3. The data in the shift register is shifted 1 bit by the next falling edge of the clock, and the bit following the LSB is output from SOUTx. This operation is repeated until all 8 bits of data are transmitted. 4. The #SRDYx signal is set to a low level when the last bit (8th bit) is output from the SOUTx pin. The master device must take in each bit synchronously with the rising edges of the synchronizing clock. * Successive transmit operations When the data in the transmit data register is transferred to the shift register, TDBEx is reset to "1" (buffer empty). Once this occurs, the next transmit data can be written to the transmit data register, even during data transmission. This allows data to be transmitted successively. The transmit procedure is described above. When TDBEx is set to "1", a transmit-data empty interrupt factor occurs. Since an interrupt can be generated as set by the interrupt controller, the next piece of transmit data can be written using an interrupt processing routine. In addition, since this interrupt factor can be used to invoke DMA, the data prepared in memory can be transmitted successively to the transmit-data register through DMA transfers. For details on how to control interrupts and DMA requests, refer to "Serial Interface Interrupts and DMA". (3) Terminating transmit operation Upon completion of data transmission, write "0" to the transmit-enable bit TXENx to disable transmit operation. Receive control (1) Enabling receive operation Use the receive-enable bit RXENx for receive control. Ch.0 receive-enable: RXEN0 (D6) / Serial I/F Ch.0 control register (0x401E3) Ch.1 receive-enable: RXEN1 (D6) / Serial I/F Ch.1 control register (0x401E8) Ch.2 receive-enable: RXEN2 (D6) / Serial I/F Ch.2 control register (0x401F3) Ch.3 receive-enable: RXEN3 (D6) / Serial I/F Ch.3 control register (0x401F8) When receive operations are enabled by writing "1" to this bit, clock input to the shift register is enabled (ready for input), thereby starting a data-receive operation. The synchronizing clock input/output on the #SCLKx pin also is enabled (ready for input/output). Receive operations are disabled by writing "0" to RXENx. B-III After the function select register is set for the serial interface, the I/O direction of the #SRDY and #SCLK pins are changed at follows: #SRDY: When slave mode is set, a switch is made to output mode. Otherwise, input mode is maintained. #SCLK: When master mode is set, a switch is made to output mode. Otherwise, input mode is maintained. Note: In clock-synchronized transfers, the clock line is shared between the transmit and receive units, so the communication mode is half-duplex. Therefore, RXENx and transmit-enable bit TXENx cannot be enabled simultaneously. When receiving data, fix TXENx at "0" and do not change it during a receive operation. In addition, make sure RXENx is not set to "0" during a receive operation. (2) Receive procedure This serial interface has a receive shift register and a receive data register (receive data buffer) that are provided independently of those used for transmit operations. Ch.0 receive data: RXD0[7:0] (D[7:0]) / Serial I/F Ch.0 receive data register (0x401E1) Ch.1 receive data: RXD1[7:0] (D[7:0]) / Serial I/F Ch.1 receive data register (0x401E6) Ch.2 receive data: RXD2[7:0] (D[7:0]) / Serial I/F Ch.2 receive data register (0x401F1) Ch.3 receive data: RXD3[7:0] (D[7:0]) / Serial I/F Ch.3 receive data register (0x401F6) The receive data can be read out from this register. S1C33L03 FUNCTION PART EPSON B-III-8-9 SIF III PERIPHERAL BLOCK: SERIAL INTERFACE A status bit is also provided that indicates the status of the receive data register. Ch.0 receive data buffer full: RDBF0 (D0) / Serial I/F Ch.0 status register (0x401E2) Ch.1 receive data buffer full: RDBF1 (D0) / Serial I/F Ch.1 status register (0x401E7) Ch.2 receive data buffer full: RDBF2 (D0) / Serial I/F Ch.2 status register (0x401F2) Ch.3 receive data buffer full: RDBF3 (D0) / Serial I/F Ch.3 status register (0x401F7) This bit is set to "1" (buffer full) when the MSB of serial data is received and the data in the shift register is transferred to the receive data register, indicating that the received data can be read out. When the data is read out, the bit is reset to "0". The following describes a receive operation in the master and slave modes. * Clock-synchronized master mode Figure 8.6 shows a receive timing chart in the clock-synchronized master mode. #SCLKx SINx D0 D1 D6 D7 D0 RXDx D1 D6 1st data D7 D0 D1 2nd data A RDBFx #SRDYx Receive-buffer full interrupt request Receive-buffer full interrupt request A First data is read. Figure 8.6 Receive Timing Chart in Clock-Synchronized Master Mode 1. If the #SRDYx signal from the slave is on a high level, the master waits until it turns to a low level (ready to receive). 2. If #SRDYx is on a low level, synchronizing clock input to the serial interface begins. The synchronizing clock is also output from the #SCLKx pin to the slave device. 3. The slave device outputs each bit of data synchronously with the falling edges of the clock. The LSB is output first. 4. This serial interface takes the SIN input into the shift register at the rising edges of the clock. The data in the shift register is sequentially shifted as bits are taken in. This operation is repeated until the MSB of data is received. 5. When the MSB is taken in, the data in the shift register is transferred to the receive data register, enabling the data to be read out. * Clock-synchronized slave mode Figure 8.7 shows a receive timing chart in the clock-synchronized slave mode. #SCLKx SINx D0 D1 D6 D7 D0 RXDx D1 D6 D7 D0 1st data D1 D6 2nd data D7 3rd data A RDBFx B D C #SRDYx Receive-buffer full interrupt request A First data is read. B 3rd data is read. Receive-buffer full interrupt request Receive-buffer full interrupt request C An overrun error occurs because the receive operation has completed when RDBFx = "1". D Send the busy signal to the master device to stop the clock. Figure 8.7 Receive Timing Chart in Clock-Synchronized Slave Mode B-III-8-10 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 1. After setting the #SRDYx signal to a low level (ready to receive), the slave waits for clock input from the master. 2. The master device outputs each bit of data synchronously with the falling edges of the clock. The LSB is output first. 3. This serial interface takes the SIN input into the shift register at the rising edges of the clock that is input from #SCLKx. The data in the shift register is sequentially shifted as bits are taken in. This operation is repeated until the MSB of data is received. 4. When the MSB is taken in, the data in the shift register is transferred to the receive data register, enabling the data to be read out. * Successive receive operations When the data received in the shift register is transferred to the receive data register, RDBFx is set to "1" (buffer full), indicating that the received data can be read out. Since the receive data register can be read out while receiving the next data, data can be received successively. The procedure for receiving is described above. When RDBFx is set to "1", a receive-data full interrupt factor occurs. Since an interrupt can be generated as set by the interrupt controller, the received data can be read by an interrupt processing routine. In addition, since this interrupt factor can be used to invoke DMA, the received data can be received successively in locations prepared in memory through DMA transfers. For details on how to control interrupts/DMA, refer to "Serial Interface Interrupts and DMA". (3) Overrun error If, during successive receive operation, a receive operation for the next data is completed before the receive data register is read out, the receive data register is overwritten with the new data. Therefore, the receive data register must always be read out before a receive operation for the next data is completed. When the receive data register is overwritten, an overrun error is generated and the overrun error flag is set to "1". Ch.0 overrun error flag: OER0 (D2) / Serial I/F Ch.0 status register (0x401E2) Ch.1 overrun error flag: OER1 (D2) / Serial I/F Ch.1 status register (0x401E7) Ch.2 overrun error flag: OER2 (D2) / Serial I/F Ch.2 status register (0x401F2) Ch.3 overrun error flag: OER3 (D2) / Serial I/F Ch.3 status register (0x401F7) Once the overrun error flag is set to "1", it remains set until it is reset by writing "0" to it in the software. The overrun error is one of the receive-error interrupt factors in the serial interface. An interrupt can be generated for this error by setting the interrupt controller as necessary, so that the error can be processed by an interrupt processing routine. (4) #SRDYx in slave mode When receive operations are enabled by writing "1" to RXENx, the #SRDYx signal is turned to a low level, thereby indicating to the master device that the slave is ready to receive. When the LSB of serial data is received, #SRDYx is turned to a high level; when the MSB is received, #SRDYx is returned to a low level, in preparation for the next receive operation. If an overrun error occurs, #SRDYx is turned to a high level (unable to receive) at that point, with receive operations for the following data thus suspended. In this case, #SRDYx is returned to a low by reading out the data overwritten in the receive data register, and if any receive data follows, the slave restarts receiving data. (5) Terminating receive operation Upon completion of a data receive operation, write "0" to the receive-enable bit RXENx to disable receive operations. S1C33L03 FUNCTION PART EPSON B-III-8-11 B-III SIF III PERIPHERAL BLOCK: SERIAL INTERFACE Asynchronous Interface Outline of Asynchronous Interface Asynchronous transfers are performed by adding a start bit and a stop bit to the start and end points of each serialconverted data. With this method, there is no need to use a clock that is fully synchronized on the transmit and receive sides; instead, transfer operations are timed by the start and stop bits added to the start and end points of each data. In the 8-bit asynchronous mode (SMDx[1:0] = "11"), 8 bits of data can be transferred; in the 7-bit asynchronous mode (SMDx[1:0] = "10"), 7 bits of data can be transferred. In either mode, it is possible to select the stop-bit length, add a parity bit, and choose between even and odd parity. The start bit is fixed at "1". The operating clock can be selected between an internal clock generated by an 8-bit programmable timer or an external clock that is input from the #SCLKx pin. Since the transmit and receive units are both constructed with a double-buffer structure, successive transmit and receive operations are possible. Furthermore, since the transmit and receive units are independent, full-duplex communication in which transmit and receive operations are performed simultaneously is also possible. Figure 8.8 shows an example of how input/output pins are connected for transfers in the asynchronous mode. External serial device S1C33 SINx Data input SOUTx #SCLKx S1C33 External serial device SINx Data output Data input SOUTx Data output External clock (1) When external clock is used (2) When internal clock is used Figure 8.8 Example of Connection in Asynchronous Mode When the asynchronous mode is selected, it is possible to use the IrDA interface function. Asynchronous-transfer data format The data format for asynchronous transfer is shown below. Data length: 7 or 8 bits (determined by the selected transfer mode) Start bit: 1 bit, fixed Stop bit: 1 or 2 bits Parity bit: Even or odd parity, or none Sampling clock (for transmitting) 7-bit asynchronous mode (Stop bit: 1 bit, parity: none) s1 D0 D1 D2 D3 D4 D5 D6 s2 (Stop bit: 1 bit, parity: used) s1 D0 D1 D2 D3 D4 D5 D6 p s2 (Stop bit: 2 bits, parity: none) s1 D0 D1 D2 D3 D4 D5 D6 s2 s3 (Stop bit: 2 bits, parity: used) s1 D0 D1 D2 D3 D4 D5 D6 p s2 (Stop bit: 1 bit, parity: none) s1 D0 D1 D2 D3 D4 D5 D6 D7 s2 (Stop bit: 1 bit, parity: used) s1 D0 D1 D2 D3 D4 D5 D6 D7 p s2 (Stop bit: 2 bits, parity: non) s1 D0 D1 D2 D3 D4 D5 D6 D7 s2 s3 (Stop bit: 2 bits, parity: used) s1 D0 D1 D2 D3 D4 D5 D6 D7 p s2 8-bit asynchronous mode s3 s3 s1: start bit, s2 & s3: stop bit, p: parity bit Figure 8.9 Data Format for Asynchronous Transfer Serial data is transmitted and received, starting with the LSB. B-III-8-12 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 Setting Asynchronous Interface When performing asynchronous transfer via the serial interface, the following must be done before data transfer can be started: 1. Setting input/output pins 2. Setting the interface mode 3. Setting the transfer mode 4. Setting the input clock 5. Setting the data format 6. Setting interrupt/IDMA/HSDMA The following describes how to set each of the above. For details on interrupt/DMA settings, refer to "Serial Interface Interrupts and DMA". Note: Always make sure the serial interface is inactive (TXENx and RXENx = "0") before making these settings. A change in settings during operation may result in a malfunction. Setting input/output pins In the asynchronous mode, two pins-SINx and SOUTx-are used. When external clock input is used, one more pin, #SCLKx, is also used. Set CFP0[7:0] (D[7:0]) / P0 function select register (0x402D0) according to the pins used. (Both channels can be used, if necessary.) Since the #SRDYx pin is not used, P03 or P07 can be used as an I/O port. During operation using the internal clock, P03 or P06 can also be used as an I/O port. Setting the interface mode IRMDx[1:0] (D[1:0]) / Serial I/F IrDA register (Ch.0: 0x401E4, Ch.1: 0x401E9, Ch.2: 0x401F4, Ch.3: 0x401F9) is used to set the IrDA interface. Since IRMDx[1:0] becomes indeterminate at initial reset, initialize it by writing "00" when using the serial interface as a normal interface, or "10" when using the serial interface as an IrDA interface. This setting must be made before a transfer mode is set. B-III Setting the transfer mode Use SMDx to set the transfer mode of the serial interface as described earlier. When using the serial interface in the 8-bit asynchronous mode, set SMDx[1:0] to "11", when using the serial interface in the 7-bit asynchronous mode, set SMDx[1:0] to "10". Setting the input clock In the asynchronous mode, the operating clock can be selected between the internal clock and an external clock. Ch.0 input clock selection: SSCK0 (D2) / Serial I/F Ch.0 control register (0x401E3) Ch.1 input clock selection: SSCK1 (D2) / Serial I/F Ch.1 control register (0x401E8) Ch.2 input clock selection: SSCK2 (D2) / Serial I/F Ch.2 control register (0x401F3) Ch.3 input clock selection: SSCK3 (D2) / Serial I/F Ch.3 control register (0x401F8) The external clock is selected (input from the #SCLKx pin) by writing "1" to SSCKx, and an internal clock is selected by writing "0". Note: SSCKx becomes indeterminate at initial reset, so be sure to reset it in the software. * Internal clock When the internal clock is selected, the serial interface is clocked by a clock generated using an 8-bit programmable timer. The clock source for each channel is as follows: Ch.0: Clock output by 8-bit programmable timer 2 Ch.1: Clock output by 8-bit programmable timer 3 Ch.2: Clock output by 8-bit programmable timer 4 Ch.3: Clock output by 8-bit programmable timer 5 Therefore, before the internal clock can be used, the following conditions must be met: 1. The prescaler is outputting a clock to the 8-bit programmable timer 2 (or 3). 2. The 8-bit programmable timer 2 (or 3) is outputting a clock. S1C33L03 FUNCTION PART EPSON B-III-8-13 SIF III PERIPHERAL BLOCK: SERIAL INTERFACE Any desired clock frequency can be obtained by setting the prescaler division ratio and the reload data of the 8-bit programmable timer as necessary. The relationship between the contents of these setting and the transfer rate is expressed by Eq. 2. The 8-bit programmable timer has its underflow signal further divided by 2 internally, in order to ensure that the duty ratio of the clock supplied to the serial interface is 50%. Furthermore, the clock output by the 8-bit programmable timer is divided by 16 or 8 internally in the serial interface, in order to create a sampling clock (refer to "Sampling clock"). This division ratio must also be considered when setting the transfer rate. These division ratios are taken into account in Eq. 2. fPSCIN x pdr x sdr RLD = ---------------- - 1 2 x bps RLD: fPSCIN: bps: pdr: sdr: (Eq. 2) Set value of the 8-bit programmable timer's reload data register Prescaler input clock frequency (Hz) Transfer rate (bits/second) Division ratio of the prescaler Internal division ratio of the serial interface (1/16 or 1/8) Note: The division ratio selected using the prescaler differs between 8-bit programmable timers 2 and 3. Take this into account when setting a division ratio. 8-bit programmable timer 2, 4: 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/2048, 1/4096 8-bit programmable timer 3, 5: 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256 Table 8.4 shows examples of prescaler division ratios and the reload data settings of the programmable timer, in cases in which the internal division ratio of the serial interface is set to 1/16. Table 8.4 Example of Transfer Rate Settings Transfer rate (bps) 300 1200 2400 4800 9600 14400 28800 fPSCIN = 20 MHz RLD pdr Error (%) RLD 129 129 129 64 32 21 10 162 162 162 80 40 13 13 1/16 1/4 1/2 1/2 1/2 1/2 1/2 0.16025 0.16025 0.16025 0.16025 -1.35732 -1.35732 -1.35732 fPSCIN = 25 MHz pdr Error (%) 1/16 1/4 1/2 1/2 1/2 1/4 1/2 RLD -0.14698 -0.14698 -0.14698 -0.46939 -0.75584 -3.11880 -3.11880 216 216 216 108 53 35 17 fPSCIN = 33 MHz pdr Error (%) 1/16 1/4 1/2 1/2 1/2 1/2 1/2 0.00640 0.00640 0.00640 -0.45234 0.46939 0.46939 0.46939 Make sure the error is within 1%. Calculate the error using the following equation: fPSCIN x pdr Error = {-------------------- -1} x 100 [%] (RLD + 1) x 32 x bps For details on how to control the prescaler and 8-bit programmable timers, refer to "Prescaler" and "8-Bit Programmable Timers". * External clock When an external clock is selected, the serial interface is clocked by a clock input from the #SCLKx pin. Therefore, there is no need to control the prescaler and 8-bit programmable timers. Any desired clock frequency can be set. The clock input from the #SCLKx pin is internally divided by 16 or 8 in the serial interface, in order to create a sampling clock (refer to "Sampling clock"). This division ratio must also be considered when setting the transfer rate. B-III-8-14 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 * Sampling clock In the asynchronous mode, TCLK (the clock output by the 8-bit programmable timer or input from the #SCLKx pin) is internally divided in the serial interface, in order to create a sampling clock. A 1/16 division ratio is selected by writing "0" to DIVMDx , and a 1/8 ratio is selected by writing "1". Ch.0 clock division ratio selection: DIVMD0 (D4) / Serial I/F Ch.0 IrDA register (0x401E4) Ch.1 clock division ratio selection: DIVMD1 (D4) / Serial I/F Ch.1 IrDA register (0x401E9) Ch.2 clock division ratio selection: DIVMD2 (D4) / Serial I/F Ch.2 IrDA register (0x401F4) Ch.3 clock division ratio selection: DIVMD3 (D4) / Serial I/F Ch.3 IrDA register (0x401F9) Note: The DIVMDx bit becomes indeterminate at initial reset, so be sure to reset it in the software. Settings of this bit are valid only in the asynchronous mode (and when using the IrDA interface). For receiving Start bit SINx D0 TCLK 1 2 8 16 1 2 8 Sampling clock for receiving 6xTCLK 10xTCLK Sampling of D0 bit Sampling of start bit Figure 8.10 Sampling Clock for Asynchronous Receive Operation (when 1/16 division is selected) As shown in Figure 8.10, the sampling clock is created by dividing TCLK by 16 (or 8). Its duty ratio (low: high ratio) is 6:10 (or 2:6 when divided by 8), and not 50%. Since the receive data is sampled in the middle point of each bit, the sampling clock recognizes the start bit first, and then changes the level from high to low at the second falling edge of TCLK. And at the 8th (4th for 1/8) falling edge of TCLK, it changes the level from low to high. This change in levels is repeated for the following bits of data: Each bit of data is sampled at each rising edge of this sampling clock. When the stop bit is sampled, the sampling clock is fixed at high level until the next start bit is sampled. If the SINx pin is returned to high level at the second falling edge of TCLK when it recognize the start bit, the data is assumed to be noise, and generation of the sampling clock is stopped. If the SINx pin is not on a low level when the start bit is sampled at the 8th (4th for 1/8) clock, such as when the baud rate is not matched between the transmit and receive units, the serial interface stops sampling the following data and returns to a start-bit detection mode. In this case, no error is generated. For transmitting SIF TCLK 1 2 3 ... 16 Sampling clock for transmitting 8xTCLK 8xTCLK Figure 8.11 Sampling Clock for Asynchronous Transmit Operation (when 1/16 division is selected) When transmitting data, a sampling clock of a 50% duty cycle is generated from TCLK by dividing it by 16 (or 8), and each bit of data is output synchronously with this clock. S1C33L03 FUNCTION PART B-III EPSON B-III-8-15 III PERIPHERAL BLOCK: SERIAL INTERFACE Setting the data format In the asynchronous mode, the data length is 7 or 8 bits as determined by the transfer mode set. The start bit is fixed at 1. The stop and parity bits can be set as shown in the Table 8.5 using the following control bits: Ch.0 (Serial I/F Ch.0 control register) Stop-bit selection Parity enable Parity-mode selection STPB0(D3/0x401E3) EPR0(D5/0x401E3) PMD0(D4/0x401E3) Table 8.5 Serial I/F Control Bits Ch.1 (Serial I/F Ch.1 Ch.2 (Serial I/F Ch.2 control register) control register) STPB1(D3/0x401E8) EPR1(D5/0x401E8) PMD1(D4/0x401E8) STPB2(D3/0x401F3) EPR2(D5/0x401F3) PMD2(D4/0x401F3) Ch.3 (Serial I/F Ch.3 control register) STPB3(D3/0x401F8) EPR3(D5/0x401F8) PMD3(D4/0x401F8) Table 8.6 Stop Bit and Parity Bit Settings STPBx EPRx 1 1 0 PMDx Stop bit 1 2 bits 0 2 bits 0 2 bits 1 1 1 bit 0 1 bit 0 1 bit Setting PMDx is invalid when EPRx = "0". Parity bit Odd Even None Odd Even Non Note: These bits become indeterminate at initial reset, so be sure to initialize them in the software. Control and Operation of Asynchronous Transfer Transmit control (1) Enabling transmit operation Use the transmit-enable bit TXENx for transmit control. Ch.0 transmit-enable: TXEN0 (D7) / Serial I/F Ch.0 control register (0x401E3) Ch.1 transmit-enable: TXEN1 (D7) / Serial I/F Ch.1 control register (0x401E8) Ch.2 transmit-enable: TXEN2 (D7) / Serial I/F Ch.2 control register (0x401F3) Ch.3 transmit-enable: TXEN3 (D7) / Serial I/F Ch.3 control register (0x401F8) When transmit is enabled by writing "1" to this bit, the clock input to the shift register is enabled (ready for input), thus allowing data to be transmitted. Transmit is disabled by writing "0" to TXENx. Note: Do not set TXENx to "0" during a transmit operation. (2) Transmit procedure The serial interface has a transmit shift register and a transmit data register (transmit data buffer) that are provided independently of those used for receive operations. Ch.0 transmit data: TXD0[7:0] (D[7:0]) / Serial I/F Ch.0 transmit data register (0x401E0) Ch.1 transmit data: TXD1[7:0] (D[7:0]) / Serial I/F Ch.1 transmit data register (0x401E5) Ch.2 transmit data: TXD2[7:0] (D[7:0]) / Serial I/F Ch.2 transmit data register (0x401F0) Ch.3 transmit data: TXD3[7:0] (D[7:0]) / Serial I/F Ch.3 transmit data register (0x401F5) The serial interface starts a transmit operation by writing data to this register. In the 7-bit asynchronous mode, bit 7 (MSB) in each register is ignored. The serial interface also contains a status bit to indicate the status of the transmit data register. Ch.0 transmit data buffer empty: TDBE0 (D1) / Serial I/F Ch.0 status register (0x401E2) Ch.1 transmit data buffer empty: TDBE1 (D1) / Serial I/F Ch.1 status register (0x401E7) Ch.2 transmit data buffer empty: TDBE2 (D1) / Serial I/F Ch.2 status register (0x401F2) Ch.3 transmit data buffer empty: TDBE3 (D1) / Serial I/F Ch.3 status register (0x401F7) This bit is reset to "0" by writing data to the transmit data register, and set back to "1" (buffer empty) when the data is transferred to the shift register. The transfer begins when the serial interface starts sending the start bit. B-III-8-16 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 The transfer status can be checked using the transmit-completion flag (TENDx). Ch.0 transmit-completion flag: TEND0 (D5) / Serial I/F Ch.0 status register (0x401E2) Ch.1 transmit-completion flag: TEND1 (D5) / Serial I/F Ch.1 status register (0x401E7) Ch.2 transmit-completion flag: TEND2 (D5) / Serial I/F Ch.2 status register (0x401F2) Ch.3 transmit-completion flag: TEND3 (D5) / Serial I/F Ch.3 status register (0x401F7) This bit goes "1" when data is being transmitted and goes "0" when the transmission has completed. When data is transmitted successively in asynchronous mode, TENDx maintains "1" until all data is transmitted. Figure 8.12 shows a transmit timing chart in the asynchronous mode. Example: Data length 8 bits Stop bit 1 bit Parity bit Included Sampling clock SOUTx TDBEx S1 D0 D1 D2 A D3 D4 D5 D6 D7 P S2 S1 D0 P S2 B TENDx Transmit-buffer empty interrupt request S1 Start bit S2 Stop bit P Parity bit Transmit-buffer empty interrupt request A First data is written. B Next data is written. Figure 8.12 Transmit Timing Chart in Asynchronous Mode 1. The contents of the data register are transferred to the shift register synchronously with the first falling edge of the sampling clock. At the same time, the SOUTx pin is setting to a low level to send the start bit. 2. Each bit of data in the shift register is transmitted beginning with the LSB at each falling edge of the subsequent sampling clock. This operation is repeated until all 8 (or 7) bits of data are transmitted. 3. After sending the MSB, the parity bit (if EPRx = "1") and the stop bit are transmitted insuccession. * Successive transmit operation When the data in the transmit data register is transferred to the shift register, TDBEx is reset to "1" (buffer empty). Once this occurs, the next transmit data can be written to the transmit data register, even during data transmission. This allows data to be transmitted successively. The transmit procedure is described above. When TDBEx is set to "1", a transmit-data empty interrupt factor simultaneously occurs. Since an interrupt can be generated as set by the interrupt controller, the next transmit data can be written using an interrupt processing routine. In addition, since this interrupt factor can be used to invoke IDMA, the data prepared in memory can be transmitted successively to the transmit data register through DMA transfers. For details on how to control interrupts and IDMA requests, refer to "Serial Interface Interrupts and DMA". (3) Terminating transmit operations When data transmission is completed, write "0" to the transmit-enable bit TXENx to disable transmit operations. S1C33L03 FUNCTION PART EPSON B-III-8-17 B-III SIF III PERIPHERAL BLOCK: SERIAL INTERFACE Receive control (1) Enabling receive operations Use the receive-enable bit RXENx for receive control. Ch.0 receive-enable: RXEN0 (D6) / Serial I/F Ch.0 control register (0x401E3) Ch.1 receive-enable: RXEN1 (D6) / Serial I/F Ch.1 control register (0x401E8) Ch.2 receive-enable: RXEN2 (D6) / Serial I/F Ch.2 control register (0x401F3) Ch.3 receive-enable: RXEN3 (D6) / Serial I/F Ch.3 control register (0x401F8) When receiving enabled by writing "1" to this bit, clock input to the shift register is enabled (ready for input), meaning that it is ready to receive data. Receive operations are disabled by writing "0" to RXENx. Note: Do not set RXENx to "0" during a receive operation. (2) Receive procedure This serial interface has a receive shift register and a receive data register (receive data buffer) that are provided independently of those used for transmit operations. Ch.0 receive data: RXD0[7:0] (D[7:0]) / Serial I/F Ch.0 receive data register (0x401E1) Ch.1 receive data: RXD1[7:0] (D[7:0]) / Serial I/F Ch.1 receive data register (0x401E6) Ch.2 receive data: RXD2[7:0] (D[7:0]) / Serial I/F Ch.2 receive data register (0x401F1) Ch.3 receive data: RXD3[7:0] (D[7:0]) / Serial I/F Ch.3 receive data register (0x401F6) Receive data can be read out from this register. A status bit is also provided to indicate the status of the receive data register. Ch.0 receive data buffer full: RDBF0 (D0) / Serial I/F Ch.0 status register (0x401E2) Ch.1 receive data buffer full: RDBF1 (D0) / Serial I/F Ch.1 status register (0x401E7) Ch.2 receive data buffer full: RDBF2 (D0) / Serial I/F Ch.2 status register (0x401F2) Ch.3 receive data buffer full: RDBF3 (D0) / Serial I/F Ch.3 status register (0x401F7) This bit is set to "1" (buffer full) when data is transferred from the shift register to the receive data register after the stop bit is sampled (the second bit if two stop bits are used), indicating that the received data can be read out. When the data is read out, the bit is reset to "0". Figure 8.13 shows a receive timing chart in the asynchronous mode. Example: Data length 8 bits Stop bit 1 bit Parity bit Included Sampling clock SOUTx S1 D0 D1 D2 D3 D4 D5 D6 D7 P S2 S1 D0 D1 A RDBFx RXDx 1st data S1 Start bit S2 Stop bit P Parity bit A First data is read. Receive-buffer full interrupt request Figure 8.13 Receive Timing Chart in Asynchronous Mode 1. The serial interface starts sampling when the start bit is input (SINx = low). 2. When the start bit is sampled at the first rising edge of the sampling clock, each bit of receive data is taken into the shift register, beginning with the LSB at each rising edge of the subsequent clock. This operation is repeated until the MSB of data is received. 3. When the MSB is taken in, the parity bit that follows is also taken in (if EPRx = "1"). 4. When the stop bit is sampled, the data in the shift register is transferred to the receive data register, enabling the data to be read out. The parity is checked when data is transferred to the receive data register (if EPRx = "1"). B-III-8-18 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 Note: The receive operation is terminated when the first stop bit is sampled even if the stop bit is configured with two bits. * Successive receive operations When the data received in the shift register is transferred to the receive data register, RDBFx is set to "1" (buffer full), indicating that the received data can be read out. Thereafter, data can be received successively because the receive data register can be read out while the next data is received. The procedure for receiving is described above. When RDBFx is set to "1", a receive-data full interrupt factor occurs. Since an interrupt can be generated as set by the interrupt controller, the received data can be read using an interrupt processing routine. In addition, since this interrupt factor can be used to invoke IDMA, the received data can be received successively in locations prepared in memory through DMA transfers. For details on how to control interrupts and IDMA requests, refer to "Serial Interface Interrupts and DMA". (3) Receive errors Three types of receive errors can be detected when receiving data in the asynchronous mode. Since an interrupt can be generated by setting the interrupt controller, the error can be processed using an interrupt processing routine. For details on receive error interrupts, refer to "Serial Interface Interrupts and DMA". * Parity error If EPRx is set to "1" (parity added), the parity is checked when data is received. This parity check is performed when the data received in the shift register is transferred to the receive data register in order to check conformity with PMDx settings (odd or even parity). If any nonconformity is found in this check, a parity error is assumed and the parity error flag is set to "1". Ch.0 parity error flag: PER0 (D3) / Serial I/F Ch.0 status register (0x401E2) Ch.1 parity error flag: PER1 (D3) / Serial I/F Ch.1 status register (0x401E7) Ch.2 parity error flag: PER2 (D3) / Serial I/F Ch.2 status register (0x401F2) Ch.3 parity error flag: PER3 (D3) / Serial I/F Ch.3 status register (0x401F7) Even when this error occurs, the received data in error is transferred to the receive data register and the receive operation is continued. However, the content of the received data for which a parity error is flagged cannot be guaranteed. The PERx flag is reset to "0" by writing "0". * Framing error If data with a stop bit = "0" is received, the serial interface assumes that the data is out of synchronization and generates a framing error. If two stop bits are used, only the first stop bit is checked. When this error occurs, the framing-error flag is set to "1". Ch.0 framing-error flag: FER0 (D4) / Serial I/F Ch.0 status register (0x401E2) Ch.1 framing-error flag: FER1 (D4) / Serial I/F Ch.1 status register (0x401E7) Ch.2 framing-error flag: FER2 (D4) / Serial I/F Ch.2 status register (0x401F2) Ch.3 framing-error flag: FER3 (D4) / Serial I/F Ch.3 status register (0x401F7) Even when this error occurs, the received data in error is transferred to the receive data register and the receive operation is continued. However, the content of the received data for which a framing error is flagged cannot be guaranteed, even if no framing error is found in the following data received. The FERx flag is reset to "0" by writing "0". S1C33L03 FUNCTION PART EPSON B-III-8-19 B-III SIF III PERIPHERAL BLOCK: SERIAL INTERFACE * Overrun error If during successive receive operations, a receive operation for the next data is completed before the receive data register is read out, the receive data register is overwritten with the new data. Therefore, the receive data register must always be read out before a receive operation for the next data is completed. When the receive data register is overwritten, an overrun error is generated and the overrun-error flag is set to "1". Ch.0 overrun-error flag: OER0 (D2) / Serial I/F Ch.0 status register (0x401E2) Ch.1 overrun-error flag: OER1 (D2) / Serial I/F Ch.1 status register (0x401E7) Ch.2 overrun-error flag: OER2 (D2) / Serial I/F Ch.2 status register (0x401F2) Ch.3 overrun-error flag: OER3 (D2) / Serial I/F Ch.3 status register (0x401F7) Even when this error occurs, the received data in error is transferred to the receive data register and the receive operation is continued. The OERx flag is reset to "0" by writing "0". (4) Terminating receive operation When a data receive operation is completed, write "0" to the receive-enable bit RXENx to disable receive operations. B-III-8-20 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 IrDA Interface Outline of IrDA Interface Each channel of the serial interface contains a PPM modulator circuit, allowing an infrared-ray communication circuit to be configured based on IrDA 1.0 simply by adding a simple external circuit. Infrared communication module S1C33 LED A PPM Modulator SOUTx LED TXD VP1N LED C Serial I/F Photodiode PPM Modulator SINx RXD CX1 VDD Vcc CX2 VSS VP1N GND (Example: HP HSDL-1000) Figure 8.14 Configuration Example of IrDA Interface This IrDA interface function can be used only when the selected transfer mode is an asynchronous mode. Since the contents of the asynchronous mode are applied directly for the serial-interface functions other than the IrDA interface unit, refer to "Asynchronous Interface", for details on how to set and control the data formats and data transfers. B-III Setting IrDA Interface When performing infrared-ray communication, the following settings must be made before communication can be started: 1. Setting input/output pins 2. Selecting the interface mode (IrDA interface function) 3. Setting the transfer mode 4. Setting the input clock 5. Setting the data format 6. Setting the interrupt/IDMA/HSDMA 7. Setting the input/output logic The contents for items 1 through 5 have been explained in connection with the asynchronous interface. For details, refer to "Asynchronous Interface". For details on item 6, refer to "Serial Interface Interrupts and DMA". Note: Before making these settings, always make sure the serial interface is inactive (TXENx and RXENx are both set to "0"), as a change in settings during operation could cause a malfunction. In addition, be sure to set the transfer mode in (3) and the following items before selecting the IrDA interface function in (2). S1C33L03 FUNCTION PART EPSON B-III-8-21 SIF III PERIPHERAL BLOCK: SERIAL INTERFACE Selecting the IrDA interface function To use the IrDA interface function, select it using the control bits shown below and then set the 8-bit (or 7bit) asynchronous mode as the transfer mode. Ch.0 IrDA interface-function selection: IRMD0[1:0] (D[1:0]) / Serial I/F Ch.0 IrDA register (0x401E4) Ch.1 IrDA interface-function selection: IRMD1[1:0] (D[1:0]) / Serial I/F Ch.1 IrDA register (0x401E9) Ch.2 IrDA interface-function selection: IRMD2[1:0] (D[1:0]) / Serial I/F Ch.2 IrDA register (0x401F4) Ch.3 IrDA interface-function selection: IRMD3[1:0] (D[1:0]) / Serial I/F Ch.3 IrDA register (0x401F9) Table 8.7 Setting of IrDA Interface IRMDx1 IRMDx0 1 1 0 0 1 0 1 0 Interface mode Do not set. (reserved) IrDA 1.0 interface Do not set. (reserved) Normal interface Note: The IRMDx bit becomes indeterminate when initially reset, so be sure to initialize it in the software. Setting the input/output logic When using the IrDA interface, the logic of the input/output signals of the PPM modulator circuit can be changed in accordance with the infrared-ray communication module or the circuit connected externally to the chip. The logic of the internal serial interface is "active-low". If the input/output signals are active-high, the logic of these signals must be inverted before they can be used. The input SINx and output SOUTx logic can be set individually through the use of the IRRLx and IRTLx bits, respectively. Table 8.8 IrDA Input/Output Logic Inversion Bits Ch.0 (Serial I/F Ch.0 Ch.1 (Serial I/F Ch.1 Ch.2 (Serial I/F Ch.2 control register) control register) control register) IrDA input logic inversion IrDA output logic inversion Ch.3 (Serial I/F Ch.3 control register) IRRL0(D2/0x401E4) IRRL1(D2/0x401E9) IRRL2(D2/0x401F4) IRRL3(D2/0x401F9) IRTL0(D3/0x401E4) IRTL1(D3/0x401E9) IRTL2(D3/0x401F4) IRTL3(D3/0x401F9) The logic of the input/output signal is inverted by writing "1" to each corresponding bit. Logic is not inverted if the bit is set to "0". When transmitting (1) IRTLx = "0" PPM modulator input (I/F output) PPM modulator output (SOUTx) (2) IRTLx = "1" PPM modulator input (I/F output) PPM modulator output (SOUTx) When receiving (1) IRRLx = "0" PPM modulator input (SINx) PPM modulator output (I/F input) (2) IRRLx = "1" PPM modulator input (SINx) PPM modulator output (I/F input) Figure 8.15 IRRLx and IRTLx Settings Note: The IRRLx and IRTLx bits become indeterminate at initial reset, so be sure to initialize them in the software. B-III-8-22 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 Control and Operation of IrDA Interface The transmit/receive procedures have been explained in the section on the asynchronous interface, so refer to "Control and Operation of Asynchronous Transfer". The following describes the data modulation and demodulation performed using the PPM modulator circuit: When transmitting During data transmission, the pulse width of the serial interface output signal is set to 3/16 before the signal is output from the SOUTx pin. TCLK 1 2 3 8 9 10 11 16 PPM modulator input (I/F output) 16xTCLK PPM modulator output (SOUTx) 3xTCLK Figure 8.16 Data Modulation by PPM Circuit When receiving During data reception, the pulse width of the input signal from SINx is set to 16/3 before the signal is transferred to the serial interface. TCLK 1 2 3 4 16 PPM modulator input (SINx) 3xTCLK PPM modulator output (I/F input) B-III 16xTCLK Figure 8.17 Demodulation by PPM Circuit Note: When using the IrDA interface, set the internal division ratio of the serial interface 1/16 (DIVMDx = "1"), rather than 1/8 (DIVMDx = "0"). SIF S1C33L03 FUNCTION PART EPSON B-III-8-23 III PERIPHERAL BLOCK: SERIAL INTERFACE Serial Interface Interrupts and DMA The serial interface can generate the following three types of interrupts in each channel: * Transmit-buffer empty interrupt * Receive-buffer full interrupt * Receive-error interrupt Transmit-buffer empty interrupt factor This interrupt factor occurs when the transmit data set in the transmit data register is transferred to the shift register, in which case the interrupt factor flag FSTXx is set to "1". At this time, if the interrupt conditions set using the interrupt control register are met, an interrupt to the CPU is generated. Occurrence of this interrupt factor indicates that the next transmit data can be written to the transmit data register. This interrupt factor can also be used to invoke IDMA, enabling transmit data to be written to the register by means of a DMA transfer. Receive-completion interrupt This interrupt factor occurs when a receive operation is completed and the receive data taken into the shift register is transferred to the receive data register, in which case the interrupt factor flag FSRXx is set to "1". At this time, if the interrupt conditions set using the interrupt control register are met, an interrupt to the CPU is generated. Occurrence of this interrupt factor indicates that the received data can be read out. This interrupt factor can also be used to invoke IDMA, enabling the received data to be written into specified memory locations by means of a DMA transfer. Receive-error interrupt This interrupt factor occurs when a parity, framing, or overrun error is detected during data reception, in which case the interrupt factor flag FSERRx is set to "1". At this time, if the interrupt conditions set using the interrupt control register are met, an interrupt to the CPU is generated. Since all three types of errors generate the same interrupt factor, check the error flags PERx (parity error), OERx (overrun error), and FERx (framing error) to identify the type of error that has occurred. In the clocksynchronized mode, parity and framing errors do not occur. Note: If a receive error (parity or framing error) occurs, the receive-error interrupt and receive-buffer full interrupt factors occur simultaneously. However, since the receive-error interrupt has priority over the receive-buffer full interrupt, the receive-error interrupt is processed first. It is therefore necessary for the receive-buffer full interrupt factor flag be cleared through the use of the receiveerror interrupt processing routine. Control registers of the interrupt controller * Ch.0 and Ch.1 Table 8.9 shows the interrupt controller's control registers provided for each interrupt source (channel). Table 8.9 Control Register of Interrupt Controller Channel Ch.0 Interrupt factor Receive-error interrupt Receive-buffer full Transmit-buffer empty Receive-error interrupt Receive-buffer full Transmit-buffer empty Ch.1 Interrupt factor flag FSERR0(D0/0x40286) FSRX0(D1/0x40286) FSTX0(D2/0x40286) FSERR1(D3/0x40286) FSRX1(D4/0x40286) FSTX1(D5/0x40286) Interrupt enable register ESERR0(D0/0x40276) ESRX0(D1/0x40276) ESTX0(D2/0x40276) ESERR1(D3/0x40276) ESRX1(D4/0x40276) ESTX1(D5/0x40276) Interrupt priority register PSIO0[2:0](D[6:4]/0x40269) PSIO1[2:0](D[2:0]/0x4026A) When the interrupt factor described above occurs, the corresponding interrupt factor flag is set to "1". If the interrupt enable register bit for that interrupt factor has been set to "1", an interrupt request is generated. Interrupts caused by an interrupt factor can be disabled by leaving the interrupt enable register bit for that factor set to "0". The interrupt factor flag is set to "1" whenever interrupt conditions are met, regardless of the setting of the interrupt enable register (even if it is set to "0"). B-III-8-24 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 The interrupt priority register sets the interrupt priority level of each interrupt source in a range between 0 and 7. An interrupt request to the CPU is accepted only when no other interrupt request of a higher priority has been generated. In addition, only when the PSR's IE bit = "1" (interrupts enabled) and the set value of the IL is smaller than the input interrupt level set by the interrupt priority register, will the input interrupt request actually be accepted by the CPU. For details on these interrupt control registers, as well as the device operation when an interrupt has occurred, refer to "ITC (Interrupt Controller)". * Ch.2 and Ch.3 Ch.2 and Ch.3 do not have dedicated interrupt signals. Either a port input interrupt or 16-bit timer interrupt is selected, and interrupt handling is performed accordingly. The correspondence between port input interrupt factors and 16-bit timer interrupt factors is shown in Table.8.10. Table 8.10 Correspondence between Interrupt Factors Serial I/F Ch.2, Ch.3/ Port input interrupt 16-bit timer interrupt T8-Ch.4, Ch.5 interrupt factor factor factor T8 Ch.5 UF FPT7 Timer 2 compare A T8 Ch.4 UF FPT5 Timer 2 compare B SIO Ch.3 TXD Emp. FPT6 Timer 4 compare A SIO Ch.3 RXD Full FPT4 Timer 4 compare B SIO Ch.3 RXD Err. FPT2 Timer 3 compare A SIO Ch.2 TXD Emp. FPT3 Timer 5 compare A SIO Ch.2 RXD Full FPT1 Timer 5 compare B SIO Ch.2 RXD Err. FPT0 Timer 3 compare B Switching between the above interrupt factors is performed by means of the interrupt factor FP function switching register (0x402C5) and the interrupt factor TM16 function switching register (0x402CB). For the setting of the interrupt controller in the CPU-core, the setting for the selected interrupt factor is used. Refer to "ITC (Interrupt Controller)" in the Core Block section for details of interrupts, and "Input/Output Ports" and "16-Bit Programmable Timers" in the Peripheral Block section for details of port input interrupt factor and 16-bit timer interrupt factor settings. B-III Intelligent DMA * Ch.0 and Ch.1 The receive-buffer full interrupt and transmit-buffer empty interrupt factors can be used to invoke intelligent DMA (IDMA). This enables successive transmit/receive operations between memory and the transmit/receive-buffer to be performed by means of a DAM transfer. The following shows the IDMA channel numbers set for each interrupt factor: IDMA Ch. Ch.0 receive-buffer full interrupt: 0x17 Ch.0 transmit-buffer empty interrupt: 0x18 Ch.1 receive-buffer full interrupt: 0x19 Ch.1 transmit-buffer empty interrupt: 0x1A The IDMA request and enable bits shown in Table 8.11 must be set to "1" for IDMA to be invoked. Transfer conditions, etc. on the IDMA side must also be set in advance. Table 8.11 Control Bits for IDMA Transfer Channel Ch.0 Ch.1 S1C33L03 FUNCTION PART Interrupt factor Receive-buffer full Transmit-buffer empty Receive-buffer full Transmit-buffer empty IDMA request bit RSRX0(D6/0x40292) RSTX0(D7/0x40292) RSRX1(D0/0x40293) RSTX1(D1/0x40293) EPSON IDMA enable bit DESRX0(D6/0x40296) DESTX0(D7/0x40296) DESRX1(D0/0x40297) DESTX1(D1/0x40297) B-III-8-25 SIF III PERIPHERAL BLOCK: SERIAL INTERFACE If an interrupt factor occurs when the IDMA request and enable bits are set to "1", IDMA is invoked. No interrupt request is generated at that point. An interrupt request is generated upon completion of the DMA transfer. The bits can also be set so as not to generate an interrupt, with only a DAM transfer performed. For details on DMA transfer and how to control interrupts upon completion of DMA transfer, refer to "IDMA (Intelligent DMA)". * Ch.2 and Ch.3 For Ch.2 and Ch.3, either a port input interrupt or 16-bit timer interrupt is selected, and IDMA is initialed by means of that interrupt factor. The correspondence between IDMA channels and Serial I/F Ch.2 and Ch.3 is shown in Table 8.12. Table 8.12 Correspondence to IDMA Channels Serial I/F Ch.2, Ch.3 / Port input / 16-bit timer T8-Ch.4, Ch.5 interrupt factor interrupt factor T8 Ch.5 UF FPT7 Timer 2 compare A T8 Ch.4 UF FPT5 Timer 2 compare B SIO Ch.3 TXD Emp. FPT6 Timer 4 compare A SIO Ch.3 RXD Full FPT4 Timer 4 compare B SIO Ch.3 RXD Err. FPT2 Timer 3 compare A SIO Ch.2 TXD Emp. FPT3 Timer 5 compare A SIO Ch.2 RXD Full FPT1 Timer 5 compare B SIO Ch.2 RXD Err. FPT0 Timer 3 compare B IDMA Ch. 31 12 29 11 30 16 28 15 3 14 4 18 2 17 1 13 For example, when port input interrupts are selected, Serial I/F Ch.2 transmit buffer empty corresponds to port 3, and to IDMA Ch.4. Therefore, IDMA can be invoked by setting both IDMA request bit RP3 (D3/0x40290) and IDMA enable bit DEP3 (D3/0x40294) to "1". High-speed DMA * Ch.0 and Ch.1 The receive-buffer full interrupt and transmit-buffer empty interrupt factors can also invoke high-speed DMA (HSDMA). The following shows the HSDMA channel number and trigger set-up bit corresponding to each channel: Table 8.13 HSDMA Trigger Set-up Bits SIF Ch. HSDMA Ch. 0 1 0 1 0 1 2 3 Trigger set-up bits HSD0S[3:0] (D[3:0]) / HSDMA Ch.0/1 trigger set-up register (0x40298) HSD1S[3:0] (D[7:4]) / HSDMA Ch.0/1 trigger set-up register (0x40298) HSD2S[3:0] (D[3:0]) / HSDMA Ch.2/3 trigger set-up register (0x40299) HSD3S[3:0] (D[7:4]) / HSDMA Ch.2/3 trigger set-up register (0x40299) For HSDMA to be invoked by the receive-buffer full interrupt factor, the trigger set-up bits should be set to "1010". For HSDMA to be invoked by the transmit-buffer empty interrupt factor, the trigger set-up bits should be set to "1011". Transfer conditions, etc. must also be set on the HSDMA side. The HSDMA channel is invoked through generation of the interrupt factor. For details on HSDMA transfer, refer to "HSDMA (High-Speed DMA)". B-III-8-26 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE * Ch.2 and Ch.3 For Ch.2 and Ch.3, either port input interrupts or 16-bit timer interrupts are selected, and HSDMA is invoked by means of those interrupt factor (See Table 8.10). When port input interrupts are selected, Serial I/F Ch.2 receive buffer full corresponds to port 1, and transmit buffer empty to port 3. Therefore, HSDMA can be invoked by setting HSDMA Ch.1 and Ch.3 trigger factor values (D[7:4]/0x40298, D[7:4]/0x40299) of "0011". Similarly, as Serial I/F Ch.3 receive buffer full corresponds to port 4, and transmit buffer empty to port 6, HSDMA can be invoked by setting HSDMA Ch.0 and Ch.2 trigger factor values (D[7:4]/0x40298, D[7:4]/0x40299) of "0100". When 16-bit timer interrupts are selected, the HSDMA trigger factor set values are different for receive buffer full and transmit buffer empty. In the case of Serial I/F Ch.2, receive buffer full corresponds to 16-bit timer 5 compare B, and transmit buffer empty to 16-bit timer 5 compare A. Therefore, to use HSDMA for both transmission and reception, an HSDMA Ch.3trigger factor value (D[7:4]/0x40299) of "1001" must be set when the Ch.1 trigger factor value (D[7:4]/0x40298) has been set to "1000". (HSDMA can also be invoked by the reverse combination of set values.) Similarly, to use 16-bit timer 4 compare A and B on Serial I/F Ch.3, HSDMA can be invoked by setting an HSDMA Ch.2 value of "1001" when the Ch.0 value has been set to "1000". (HSDMA can also be invoked by the reverse combination of set values.) With interrupts other than receive buffer full and transmit buffer empty, also, the above approach can be used to activate the HSDMA channel set for the corresponding port No. or 16-bit timer compare. A-1 Trap vectors * Ch.0 and Ch.1 The trap-vector address of each default interrupt factor is set as follows: Ch.0 receive-error interrupt: Ch.0 receive-buffer full interrupt: Ch.0 transmit-buffer empty interrupt: Ch.1 receive-error interrupt: Ch.1 receive-buffer full interrupt: Ch.1 transmit-buffer empty interrupt: 0x0C000E0 0x0C000E4 0x0C000E8 0x0C000EC 0x0C000F0 0x0C000F4 B-III The base address of the trap table can be changed using the TTBR register (0x48134 to 0x48137). * Ch.2 and Ch.3 Ch.2 and Ch.3 do not have dedicated interrupt signals. Either a port input interrupt or 16-bit timer interrupt is selected, and interrupt handling is performed accordingly. For details, refer to the "Trap Vector" subsection in the "16-Bit Programmable Timers" or "Input/Output Ports" section. S1C33L03 FUNCTION PART EPSON B-III-8-27 SIF III PERIPHERAL BLOCK: SERIAL INTERFACE I/O Memory of Serial Interface Table 8.14 shows the control bits of the serial interface. For details on the I/O memory of the prescaler that is used to set clocks, as well of that of 8-bit programmable timers, refer to "Prescaler" and "8-Bit Programmable Timers", respectively. Table 8.14 Control Bits of Serial Interface Register name Address Bit Name Serial I/F Ch.0 transmit data register 00401E0 (B) D7 D6 D5 D4 D3 D2 D1 D0 TXD07 TXD06 TXD05 TXD04 TXD03 TXD02 TXD01 TXD00 Serial I/F Ch.0 transmit data TXD07(06) = MSB TXD00 = LSB Function 0x0 to 0xFF(0x7F) X X X X X X X X Serial I/F Ch.0 receive data register 00401E1 (B) D7 D6 D5 D4 D3 D2 D1 D0 RXD07 RXD06 RXD05 RXD04 RXD03 RXD02 RXD01 RXD00 Serial I/F Ch.0 receive data RXD07(06) = MSB RXD00 = LSB 0x0 to 0xFF(0x7F) X X X X X X X X R 7-bit asynchronous mode does not use RXD07 (fixed at 0). - - 0 0 0 0 1 0 - R R/W R/W R/W R R 0 when being read. 1 Enabled 0 Disabled 1 Enabled 0 Disabled 1 With parity 0 No parity 1 Odd 0 Even 1 2 bits 0 1 bit 1 #SCLK0 0 Internal clock SMD0[1:0] Transfer mode 1 1 8-bit asynchronous 1 0 7-bit asynchronous Clock sync. Slave 0 1 Clock sync. Master 0 0 0 0 X X X X X X R/W R/W R/W Valid only in R/W asynchronous mode. R/W R/W R/W - - X X X X X - 0 when being read. R/W R/W Valid only in R/W asynchronous mode. R/W R/W 7-bit asynchronous mode does not use TXD17. Serial I/F Ch.0 00401E2 D7-6 - status register (B) D5 TEND0 D4 FER0 D3 PER0 D2 OER0 D1 TDBE0 D0 RDBF0 - Ch.0 transmit-completion flag Ch.0 flaming error flag Ch.0 parity error flag Ch.0 overrun error flag Ch.0 transmit data buffer empty Ch.0 receive data buffer full Serial I/F Ch.0 00401E3 control register (B) Ch.0 transmit enable Ch.0 receive enable Ch.0 parity enable Ch.0 parity mode selection Ch.0 stop bit selection Ch.0 input clock selection Ch.0 transfer mode selection D7 D6 D5 D4 D3 D2 D1 D0 TXEN0 RXEN0 EPR0 PMD0 STPB0 SSCK0 SMD01 SMD00 Setting 1 1 1 1 1 1 Transmitting Error Error Error Empty Buffer full 0 0 0 0 0 0 Init. R/W End Normal Normal Normal Buffer full Empty Serial I/F Ch.0 IrDA register 00401E4 D7-5 - (B) D4 DIVMD0 D3 IRTL0 D2 IRRL0 D1 IRMD01 D0 IRMD00 - Ch.0 async. clock division ratio Ch.0 IrDA I/F output logic inversion Ch.0 IrDA I/F input logic inversion Ch.0 interface mode selection Serial I/F Ch.1 transmit data register 00401E5 (B) D7 D6 D5 D4 D3 D2 D1 D0 TXD17 TXD16 TXD15 TXD14 TXD13 TXD12 TXD11 TXD10 Serial I/F Ch.1 transmit data TXD17(16) = MSB TXD10 = LSB 0x0 to 0xFF(0x7F) X X X X X X X X Serial I/F Ch.1 receive data register 00401E6 (B) D7 D6 D5 D4 D3 D2 D1 D0 RXD17 RXD16 RXD15 RXD14 RXD13 RXD12 RXD11 RXD10 Serial I/F Ch.1 receive data RXD17(16) = MSB RXD10 = LSB 0x0 to 0xFF(0x7F) X X X X X X X X B-III-8-28 EPSON 1 1/8 1 Inverted 1 Inverted IRMD0[1:0] 1 1 1 0 0 1 0 0 0 1/16 0 Direct 0 Direct I/F mode reserved IrDA 1.0 reserved General I/F Remarks R/W 7-bit asynchronous mode does not use TXD07. R Reset by writing 0. Reset by writing 0. Reset by writing 0. 7-bit asynchronous mode does not use RXD17 (fixed at 0). S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 Register name Address Bit Name Function Serial I/F Ch.1 00401E7 D7-6 - status register (B) D5 TEND1 D4 FER1 D3 PER1 D2 OER1 D1 TDBE1 D0 RDBF1 - Ch.1 transmit-completion flag Ch.1 flaming error flag Ch.1 parity error flag Ch.1 overrun error flag Ch.1 transmit data buffer empty Ch.1 receive data buffer full Serial I/F Ch.1 00401E8 control register (B) Ch.1 transmit enable Ch.1 receive enable Ch.1 parity enable Ch.1 parity mode selection Ch.1 stop bit selection Ch.1 input clock selection Ch.1 transfer mode selection D7 D6 D5 D4 D3 D2 D1 D0 TXEN1 RXEN1 EPR1 PMD1 STPB1 SSCK1 SMD11 SMD10 Setting Init. R/W - Remarks - 0 0 0 0 1 0 - R R/W R/W R/W R R 1 Enabled 0 Disabled 1 Enabled 0 Disabled 1 With parity 0 No parity 1 Odd 0 Even 1 2 bits 0 1 bit 1 #SCLK1 0 Internal clock SMD1[1:0] Transfer mode 1 1 8-bit asynchronous 1 0 7-bit asynchronous Clock sync. Slave 0 1 Clock sync. Master 0 0 0 0 X X X X X X R/W R/W R/W Valid only in R/W asynchronous mode. R/W R/W R/W - - X X X X X - 0 when being read. R/W R/W Valid only in R/W asynchronous mode. R/W 1 1 1 1 1 1 Transmitting Error Error Error Empty Buffer full 0 0 0 0 0 0 End Normal Normal Normal Buffer full Empty 0 when being read. Reset by writing 0. Reset by writing 0. Reset by writing 0. Serial I/F Ch.1 IrDA register 00401E9 D7-5 - (B) D4 DIVMD1 D3 IRTL1 D2 IRRL1 D1 IRMD11 D0 IRMD10 - Ch.1 async. clock division ratio Ch.1 IrDA I/F output logic inversion Ch.1 IrDA I/F input logic inversion Ch.1 interface mode selection Serial I/F Ch.2 transmit data register 00401F0 (B) D7 D6 D5 D4 D3 D2 D1 D0 TXD27 TXD26 TXD25 TXD24 TXD23 TXD22 TXD21 TXD20 Serial I/F Ch.2 transmit data TXD27(26) = MSB TXD20 = LSB 0x0 to 0xFF(0x7F) X X X X X X X X R/W Serial I/F Ch.2 receive data register 00401F1 (B) D7 D6 D5 D4 D3 D2 D1 D0 RXD27 RXD26 RXD25 RXD24 RXD23 RXD22 RXD21 RXD20 Serial I/F Ch.2 receive data RXD27(26) = MSB RXD20 = LSB 0x0 to 0xFF(0x7F) X X X X X X X X R D7-6 D5 D4 D3 D2 D1 D0 - TEND2 FER2 PER2 OER2 TDBE2 RDBF2 reserved Ch.2 transmit-completion flag Ch.2 flaming error flag Ch.2 parity error flag Ch.2 overrun error flag Ch.2 transmit data buffer empty Ch.2 receive data buffer full - - 0 0 0 0 1 0 - R R/W R/W R/W R R D7 D6 D5 D4 D3 D2 D1 D0 TXEN2 RXEN2 EPR2 PMD2 STPB2 SSCK2 SMD21 SMD20 Ch.2 transmit enable Ch.2 receive enable Ch.2 parity enable Ch.2 parity mode selection Ch.2 stop bit selection Ch.2 input clock selection Ch.2 transfer mode selection 1 Enabled 0 Disabled 1 Enabled 0 Disabled 1 With parity 0 No parity 1 Odd 0 Even 1 2 bits 0 1 bit 1 #SCLK2 0 Internal clock SMD2[1:0] Transfer mode 1 1 8-bit asynchronous 1 0 7-bit asynchronous Clock sync. Slave 0 1 Clock sync. Master 0 0 0 0 X X X X X X R/W R/W R/W Valid only in R/W asynchronous mode. R/W R/W R/W D7-5 D4 D3 D2 D1 D0 - DIVMD2 IRTL2 IRRL2 IRMD21 IRMD20 reserved Ch.2 async. clock division ratio Ch.2 IrDA I/F output logic inversion Ch.2 IrDA I/F input logic inversion Ch.2 interface mode selection - - X X X X X - 0 when being read. R/W R/W Valid only in R/W asynchronous mode. R/W Serial I/F Ch.2 00401F2 status register (B) Serial I/F Ch.2 00401F3 control register (B) Serial I/F Ch.2 IrDA register 00401F4 (B) S1C33L03 FUNCTION PART EPSON 1 1/8 1 Inverted 1 Inverted IRMD1[1:0] 1 1 1 0 0 1 0 0 1 1 1 1 1 1 0 1/16 0 Direct 0 Direct I/F mode reserved IrDA 1.0 reserved General I/F Transmitting Error Error Error Empty Buffer full 1 1/8 1 Inverted 1 Inverted IRMD2[1:0] 1 1 1 0 0 1 0 0 0 0 0 0 0 0 End Normal Normal Normal Buffer full Empty 0 1/16 0 Direct 0 Direct I/F mode reserved IrDA 1.0 reserved General I/F B-III 0 when being read. Reset by writing 0. Reset by writing 0. Reset by writing 0. B-III-8-29 SIF III PERIPHERAL BLOCK: SERIAL INTERFACE Register name Address Bit Serial I/F Ch.3 transmit data register 00401F5 (B) D7 D6 D5 D4 D3 D2 D1 D0 TXD37 TXD36 TXD35 TXD34 TXD33 TXD32 TXD31 TXD30 Serial I/F Ch.3 transmit data TXD37(36) = MSB TXD30 = LSB 0x0 to 0xFF(0x7F) X X X X X X X X R/W Serial I/F Ch.3 receive data register 00401F6 (B) D7 D6 D5 D4 D3 D2 D1 D0 RXD37 RXD36 RXD35 RXD34 RXD33 RXD32 RXD31 RXD30 Serial I/F Ch.3 receive data RXD37(36) = MSB RXD30 = LSB 0x0 to 0xFF(0x7F) X X X X X X X X R D7-6 D5 D4 D3 D2 D1 D0 - TEND3 FER3 PER3 OER3 TDBE3 RDBF3 reserved Ch.3 transmit-completion flag Ch.3 flaming error flag Ch.3 parity error flag Ch.3 overrun error flag Ch.3 transmit data buffer empty Ch.3 receive data buffer full - - 0 0 0 0 1 0 - R R/W R/W R/W R R D7 D6 D5 D4 D3 D2 D1 D0 TXEN3 RXEN3 EPR3 PMD3 STPB3 SSCK3 SMD31 SMD30 Ch.3 transmit enable Ch.3 receive enable Ch.3 parity enable Ch.3 parity mode selection Ch.3 stop bit selection Ch.3 input clock selection Ch.3 transfer mode selection 1 Enabled 0 Disabled 1 Enabled 0 Disabled 1 With parity 0 No parity 1 Odd 0 Even 1 2 bits 0 1 bit 1 #SCLK3 0 Internal clock SMD3[1:0] Transfer mode 1 1 8-bit asynchronous 1 0 7-bit asynchronous Clock sync. Slave 0 1 Clock sync. Master 0 0 0 0 X X X X X X R/W R/W R/W Valid only in R/W asynchronous mode. R/W R/W R/W D7-5 D4 D3 D2 D1 D0 - DIVMD3 IRTL3 IRRL3 IRMD31 IRMD30 reserved Ch.3 async. clock division ratio Ch.3 IrDA I/F output logic inversion Ch.3 IrDA I/F input logic inversion Ch.3 interface mode selection - - X X X X X - 0 when being read. R/W R/W Valid only in R/W asynchronous mode. R/W D7 D6 D5 D4 D3 D2 D1 D0 - PSIO02 PSIO01 PSIO00 - P8TM2 P8TM1 P8TM0 reserved Serial interface Ch.0 interrupt level - 0 to 7 - 0 when being read. R/W reserved 8-bit timer 0-3 interrupt level - 0 to 7 - X X X - X X X D7 D6 D5 D4 D3 D2 D1 D0 - PAD2 PAD1 PAD0 - PSIO12 PSIO11 PSIO10 reserved A/D converter interrupt level - 0 to 7 - 0 when being read. R/W reserved Serial interface Ch.1 interrupt level - 0 to 7 - X X X - X X X D7-6 D5 D4 D3 D2 D1 D0 - ESTX1 ESRX1 ESERR1 ESTX0 ESRX0 ESERR0 reserved SIF Ch.1 transmit buffer empty SIF Ch.1 receive buffer full SIF Ch.1 receive error SIF Ch.0 transmit buffer empty SIF Ch.0 receive buffer full SIF Ch.0 receive error - 0 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W R/W Serial I/F Ch.3 00401F7 status register (B) Serial I/F Ch.3 00401F8 control register (B) Serial I/F Ch.3 IrDA register 00401F9 (B) 8-bit timer, 0040269 serial I/F Ch.0 (B) interrupt priority register Serial I/F Ch.1, 004026A A/D interrupt (B) priority register Serial I/F 0040276 interrupt (B) enable register B-III-8-30 Name Function EPSON Setting 1 1 1 1 1 1 Transmitting Error Error Error Empty Buffer full 0 0 0 0 0 0 1 1/8 1 Inverted 1 Inverted IRMD3[1:0] 1 1 1 0 0 1 0 0 Init. R/W End Normal Normal Normal Buffer full Empty 0 1/16 0 Direct 0 Direct I/F mode reserved IrDA 1.0 reserved General I/F - 1 Enabled 0 Disabled Remarks 0 when being read. Reset by writing 0. Reset by writing 0. Reset by writing 0. - 0 when being read. R/W - 0 when being read. R/W S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 Register name Address Bit Name Function Serial I/F 0040286 interrupt factor (B) flag register D7-6 D5 D4 D3 D2 D1 D0 - FSTX1 FSRX1 FSERR1 FSTX0 FSRX0 FSERR0 reserved SIF Ch.1 transmit buffer empty SIF Ch.1 receive buffer full SIF Ch.1 receive error SIF Ch.0 transmit buffer empty SIF Ch.0 receive buffer full SIF Ch.0 receive error Setting - 1 Factor is generated 0 No factor is generated Init. R/W Remarks - X X X X X X - 0 when being read. R/W R/W R/W R/W R/W R/W 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA request register 0040292 (B) D7 D6 D5 D4 D3 D2 D1 D0 RSTX0 RSRX0 R8TU3 R8TU2 R8TU1 R8TU0 R16TC5 R16TU5 SIF Ch.0 transmit buffer empty SIF Ch.0 receive buffer full 8-bit timer 3 underflow 8-bit timer 2 underflow 8-bit timer 1 underflow 8-bit timer 0 underflow 16-bit timer 5 comparison A 16-bit timer 5 comparison B 1 IDMA request 0 Interrupt request 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Serial I/F Ch.1, A/D, port input 4-7 IDMA request register 0040293 (B) D7 D6 D5 D4 D3 D2 D1 D0 RP7 RP6 RP5 RP4 - RADE RSTX1 RSRX1 Port input 7 Port input 6 Port input 5 Port input 4 reserved A/D converter SIF Ch.1 transmit buffer empty SIF Ch.1 receive buffer full 1 IDMA request 0 Interrupt request 1 IDMA request 0 Interrupt request 0 0 0 0 - 0 0 0 R/W R/W R/W R/W - 0 when being read. R/W R/W R/W - 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA enable register 0040296 (B) D7 D6 D5 D4 D3 D2 D1 D0 DESTX0 DESRX0 DE8TU3 DE8TU2 DE8TU1 DE8TU0 DE16TC5 DE16TU5 SIF Ch.0 transmit buffer empty SIF Ch.0 receive buffer full 8-bit timer 3 underflow 8-bit timer 2 underflow 8-bit timer 1 underflow 8-bit timer 0 underflow 16-bit timer 5 comparison A 16-bit timer 5 comparison B 1 IDMA enabled 0 IDMA disabled 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Serial I/F Ch.1, A/D, port input 4-7 IDMA enable register 0040297 (B) D7 D6 D5 D4 D3 D2 D1 D0 DEP7 DEP6 DEP5 DEP4 - DEADE DESTX1 DESRX1 Port input 7 Port input 6 Port input 5 Port input 4 reserved A/D converter SIF Ch.1 transmit buffer empty SIF Ch.1 receive buffer full 1 IDMA enabled 0 IDMA disabled 1 IDMA enabled 0 IDMA disabled 0 0 0 0 - 0 0 0 R/W R/W R/W R/W - 0 when being read. R/W R/W R/W D7 D6 T8CH5S0 SIO3TS0 8-bit timer 5 underflow SIO Ch.3 transmit buffer empty 0 FP7 0 FP6 0 0 R/W R/W D5 D4 T8CH4S0 SIO3RS0 8-bit timer 4 underflow SIO Ch.3 receive buffer full 0 FP5 0 FP4 0 0 R/W R/W D3 SIO2TS0 SIO Ch.2 transmit buffer empty 0 FP3 0 R/W D2 SIO3ES0 SIO Ch.3 receive error 0 FP2 0 R/W D1 SIO2RS0 SIO Ch.2 receive buffer full 0 FP1 0 R/W D0 SIO2ES0 SIO Ch.2 receive error 1 T8 Ch.5 UF 1 SIO Ch.3 TXD Emp. 1 T8 Ch.4 UF 1 SIO Ch.3 RXD Full 1 SIO Ch.2 TXD Emp. 1 SIO Ch.3 RXD Err. 1 SIO Ch.2 RXD Full 1 SIO Ch.2 RXD Err. 0 FP0 0 R/W D7 T8CH5S1 8-bit timer 5 underflow 0 R/W D6 T8CH4S1 8-bit timer 4 underflow 0 R/W D5 SIO3ES1 SIO Ch.3 receive error 0 R/W D4 SIO2ES1 SIO Ch.2 receive error 0 R/W D3 SIO3TS1 SIO Ch.3 transmit buffer empty 0 R/W D2 SIO3RS1 SIO Ch.3 receive buffer full 0 R/W D1 SIO2TS1 SIO Ch.2 transmit buffer empty 0 R/W D0 SIO2RS1 SIO Ch.2 receive buffer full 0 R/W Interrupt factor 00402C5 FP function switching register Interrupt factor 00402CB TM16 function switching register S1C33L03 FUNCTION PART EPSON - 1 T8 Ch.5 UF 0 TM16 Ch.2 comp.A 1 T8 Ch.4 UF 0 TM16 Ch.2 comp.B 1 SIO Ch.3 0 TM16 Ch.3 RXD Err. comp.A 1 SIO Ch.2 0 TM16 Ch.3 RXD Err. comp.B 1 SIO Ch.3 0 TM16 Ch.4 TXD Emp. comp.A 1 SIO Ch.3 0 TM16 Ch.4 RXD Full comp.B 1 SIO Ch.2 0 TM16 Ch.5 TXD Emp. comp.A 1 SIO Ch.2 0 TM16 Ch.5 RXD Full comp.B B-III SIF B-III-8-31 III PERIPHERAL BLOCK: SERIAL INTERFACE Register name Address Bit P0 function select register 00402D0 (B) D7 D6 D5 D4 D3 D2 D1 D0 Port SIO function extension register Name CFP07 CFP06 CFP05 CFP04 CFP03 CFP02 CFP01 CFP00 Function Setting P07 function selection P06 function selection P05 function selection P04 function selection P03 function selection P02 function selection P01 function selection P00 function selection 1 1 1 1 1 1 1 1 00402D7 D7-4 - D3 SSRDY3 reserved Serial I/F Ch.3 SRDY selection 1 #SRDY3 D2 SSCLK3 Serial I/F Ch.3 SCLK selection 1 #SCLK3 D1 SSOUT3 Serial I/F Ch.3 SOUT selection 1 SOUT3 D0 SSIN3 Serial I/F Ch.3 SIN selection 1 SIN3 1 1 1 1 Port SIO function extension register 00402DB D7-4 D3 D2 D1 D0 - SSRDY2 SSCLK2 SSOUT2 SSIN2 reserved Serial I/F Ch.2 SRDY selection Serial I/F Ch.2 SCLK selection Serial I/F Ch.2 SOUT selection Serial I/F Ch.2 SIN selection Port function extension register 00402DF (B) D7 D6 D5 D4 D3 D2 D1 CFEX7 CFEX6 CFEX5 CFEX4 CFEX3 CFEX2 CFEX1 P07 port extended function P06 port extended function P05 port extended function P04 port extended function P31 port extended function P21 port extended function P10, P11, P13 port extended function D0 CFEX0 P12, P14 port extended function #SRDY1 #SCLK1 SOUT1 SIN1 #SRDY0 #SCLK0 SOUT0 SIN0 0 0 0 0 0 0 0 0 Init. R/W P07 P06 P05 P04 P03 P02 P01 P00 - 0 P32/ #DMAACK0 0 P15/EXCL4/ #DMAEND0 0 P16/EXCL5/ #DMAEND1 0 P33/ #DMAACK1 - #SRDY2 #SCLK2 SOUT2 SIN2 0 0 0 0 #DMAEND3 #DMAACK3 #DMAEND2 #DMAACK2 #GARD #GAAS DST0 DST1 DPC0 1 DST2 DCLK 0 0 0 0 0 0 0 1 1 1 1 1 1 1 P24/TM2 P25/TM3 P26/TM4 P27/TM5 P07, etc. P06, etc. P05, etc. P04, etc. P31, etc. P21, etc. P10, etc. P11, etc. P13, etc. 0 P12, etc. P14, etc. Remarks 0 0 0 0 0 0 0 0 R/W Extended functions R/W (0x402DF) R/W R/W R/W R/W R/W R/W - 0 - R/W 0 R/W 0 R/W 0 R/W - 0 0 0 0 - R/W R/W R/W R/W 0 0 0 0 0 0 1 R/W R/W R/W R/W R/W R/W R/W 1 R/W CFP07-CFP00: P0[7:0] pin function selection (D[7:0]) / P0 function select register (0x402D0) Selects the pins used for the serial interface. Write "1": Serial-interface input/output pin Write "0": I/O port pin Read: Valid Select the pins used for the serial interface from among P00 through P07 by writing "1" to CFP00 through CFP07. P00-P03 (SIN0, SOUT0, #SCLK0, #SRDY0) are used for channel 0; P04-P07 (SIN1, SOUT1, #SCLK1, #SRDY1) are used for channel 1. If the bit for a pin is set to "0", the pin functions as an I/O port. The necessary input/output pins differ depending on the transfer mode set (see Table 8.3). At cold start, CFP is set to "0" (I/O port). At hot start, CFP retains its state from prior to the initial reset. SSIN3: Serial I/F Ch.3 SIN selection (D0) / Port SIO function extension register (0x402D7) Switches the function of pin P33/#DMAACK1/SIN3. Write "1": SIN3 Write "0": P33/#DMAACK1 Read: Valid To use the pin as SIN3, set SSIN3 (D0 / 0x402D7) to "1" and CFP33 (D3 / 0x402DC) to "0". To use the pin as P33 or #DMAACK1, set this bit to "0". At power-on, this bit is set to "0". B-III-8-32 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 SSOUT3: Serial I/F Ch.3 SOUT selection (D1) / Port SIO function extension register (0x402D7) Switches the function of pin P16/EXCL5/#DMAEND1/SOUT3. Write "1": SOUT3 Write "0": P16/EXCL5/#DMAEND1 Read: Valid To use the pin as SOUT3, set SSOUT3 (D1 / 0x402D7) to "1" and CFP16 (D6 / 0x402D4) to "0". To use the pin as P16, EXCL5, or #DMAEND1, set this bit to "0". At power-on, this bit is set to "0". SSCLK3: Serial I/F Ch.3 SCLK selection (D2) / Port SIO function extension register (0x402D7) Switches the function of pin P15/EXCL4/#DMAEND0/#SCLK3. Write "1": #SCLK3 Write "0": P15/EXCL4/#DMAEND0 Read: Valid To use the pin as #SCLK3, set SSCLK3 (D2 / 0x402D7) to "1" and CFP15 (D5 / 0x402D4) to "0". To use the pin as P15, EXCL4, or #DMAEND0, set this bit to "0". At power-on, this bit is set to "0". SSRDY3: Serial I/F Ch.3 SRDY selection (D3) / Port SIO function extension register (0x402D7) Switches the function of pin P32/#DMAACK0/#SRDY3. Write "1": #SRDY3 Write "0": P32/#DMAACK0 Read: Valid To use the pin as #SRDY3, set SSRDY3 (D3 / 0x402D7) to "1" and CFP32 (D2 / 0x402DC) to "0". To use the pin as P32 or #DMAACK0, set this bit to "0". At power-on, this bit is set to "0". B-III SSIN2: Serial I/F Ch.2 SIN selection (D0) / Port SIO function extension register (0x402DB) Switches the function of pin P27/TM5/SIN2. Write "1": SIN2 Write "0": P27/TM5 Read: Valid To use the pin as SIN2, set SSIN2 (D0 / 0x402DB) to "1" and CFP27 (D7 / 0x402D8) to "0". To use the pin as P27 or TM5, set this bit to "0". At power-on, this bit is set to "0". SIF SSOUT2: Serial I/F Ch.2 SOUT selection (D1) / Port SIO function extension register (0x402DB) Switches the function of pin P26/TM4/SOUT2. Write "1": SOUT2 Write "0": P26/TM4 Read: Valid To use the pin as SOUT2, set SSOUT2 (D1 / 0x402DB) to "1" and CFP26 (D6 / 0x402D8) to "0". To use the pin as P26 or TM4, set this bit to "0". At power-on, this bit is set to "0". S1C33L03 FUNCTION PART EPSON B-III-8-33 III PERIPHERAL BLOCK: SERIAL INTERFACE SSCLK2: Serial I/F Ch.2 SCLK selection (D2) / Port SIO function extension register (0x402DB) Switches the function of pin P25/TM3/#SCLK2. Write "1": #SCLK2 Write "0": P25/TM3 Read: Valid To use the pin as #SCLK2, set SSCLK2 (D2 / 0x402DB) to "1" and CFP25 (D5 / 0x402D8) to "0". To use the pin as P25 or TM3, set this bit to "0". At power-on, this bit is set to "0". SSRDY2: Serial I/F Ch.2 SRDY selection (D3) / Port SIO function extension register (0x402DB) Switches the function of pin P24/TM2/#SRDY2. Write "1": #SRDY2 Write "0": P24/TM2 Read: Valid To use the pin as #SRDY2, set SSRDY2 (D3 / 0x402DB) to "1" and CFP24 (D4 / 0x402D8) to "0". To use the pin as P24 or TM2, set this bit to "0". At power-on, this bit is set to "0". CFEX7-CFEX4: P0[7:4] pin function selection (D[7:4]) / Port function extension register (0x402DF) Selects the extended function of pins P07-P04. Write "1": Function-extended pin Write "0": I/O-port/serial I/O pin Read: Valid When CFEX[7:4] is set to "1", the P07-P04 ports function as DMA signal output ports. When CFEX[7:4] = "0", the CFP0[7:4] bit becomes effective, so the settings of these bits determine whether the P07-P04 ports function as I/O port s or serial interface Ch.1 signal output ports. At cold start, CFEX[7:4] is set to "0" (I/O-port/serial I/O pin). At hot start, CFEX[7:4] retains its state from prior to the initial reset. TXD07-TXD00: Ch.0 transmit data (D[7:0]) / Serial I/F Ch.0 transmit data register (0x401E0) TXD17-TXD10: Ch.1 transmit data (D[7:0]) / Serial I/F Ch.1 transmit data register (0x401E5) TXD27-TXD20: Ch.2 transmit data (D[7:0]) / Serial I/F Ch.2 transmit data register (0x401F0) TXD37-TXD30: Ch.3 transmit data (D[7:0]) / Serial I/F Ch.3 transmit data register (0x401F5) Sets transmit data. When data is written to this register (transmit buffer) after "1" is written to TXENx, a transmit operation is begun. TDBEx is set to "1" (transmit-buffer empty) when the data is transferred to the shift register. A transmit-buffer empty interrupt factor is simultaneously generated. The next transmit data can be written to the buffer at any time thereafter, even when the serial interface is sending data. In the 7-bit asynchronous mode, TXDx7 (MSB) is ignored. The serial-converted data is output from the SOUT pin beginning with the LSB, in which the bits set to "1" are output as high-level signals and those set to "0" output as low-level signals. This register can be read as well as written. At initial reset, the content of TXDx becomes indeterminate. B-III-8-34 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 RXD07-RXD00: Ch.0 receive data (D[7:0]) / Serial I/F Ch.0 receive data register (0x401E1) RXD17-RXD10: Ch.1 receive data (D[7:0]) / Serial I/F Ch.1 receive data register (0x401E6) RXD27-RXD20: Ch.2 receive data (D[7:0]) / Serial I/F Ch.2 receive data register (0x401F1) RXD37-RXD30: Ch.3 receive data (D[7:0]) / Serial I/F Ch.3 receive data register (0x401F6) Stores received data. When a receive operation is completed and the data received in the shift register is transferred to this register (receive buffer), RDBFx is set to "1" (receive buffer full). At the same time, a receive-buffer full interrupt factor is generated. Thereafter, the data can be read out at any time before a receive operation for the next data is completed. If the next data receive operation is completed before this register is read out, the data in it is overwritten with the newly received data, causing an overrun error to occur. In the 7-bit asynchronous mode, "0" is stored in RXDx7. The serial data input from the SINx pin is converted into parallel data beginning with the LSB, with the high-level signals changed to "1"s and the low-level signals changed to "0"s. The resulting data is stored in this buffer. This register is a read-only register, so no data can be written to it. At initial reset, the content of RXDx becomes indeterminate. TEND0: Ch.0 transmit-completion flag (D5) / Serial I/F Ch.0 status register (0x401E2) TEND1: Ch.1 transmit-completion flag (D5) / Serial I/F Ch.1 status register (0x401E7) TEND2: Ch.2 transmit-completion flag (D5) / Serial I/F Ch.2 status register (0x401F2) TEND3: Ch.3 transmit-completion flag (D5) / Serial I/F Ch.3 status register (0x401F7) Indicates the transmission status. Read "1": During transmitting Read "0": End of transmission Write: Invalid TENDx goes "1" when data is being transmitted and goes "0" when the transmission has completed. When data is transmitted successively in clock-synchronized master mode or asynchronous mode, TENDx maintains "1" until all data is transmitted (see Figure 8.4 and Figure 8.12). In clock-synchronized slave mode, TENDx goes "0" every time 1-byte data is transmitted (see Figure 8.5). At initial reset, TENDx is set to "0" (End of transmission). B-III FER0: Ch.0 framing-error flag (D4) / Serial I/F Ch.0 status register (0x401E2) FER1: Ch.1 framing-error flag (D4) / Serial I/F Ch.1 status register (0x401E7) FER2: Ch.2 framing-error flag (D4) / Serial I/F Ch.2 status register (0x401F2) FER3: Ch.3 framing-error flag (D4) / Serial I/F Ch.3 status register (0x401F7) Indicates whether a framing error occurred. Read "1": Read "0": Write "1": Write "0": SIF An error occurred No error occurred Invalid Reset to "0" The FERx flag is an error flag indicating whether a framing error occurred. When an error has occurred, it is set to "1". A framing error occurs when data with a stop bit = "0" is received in the asynchronous mode. The FERx flag is reset by writing "0". At initial reset, as well as when RXENx and TXENx both are set to "0", the FERx flag is set to "0" (no error). S1C33L03 FUNCTION PART EPSON B-III-8-35 III PERIPHERAL BLOCK: SERIAL INTERFACE PER0: Ch.0 parity-error flag (D3) / Serial I/F Ch.0 status register (0x401E2) PER1: Ch.1 parity-error flag (D3) / Serial I/F Ch.1 status register (0x401E7) PER2: Ch.2 parity-error flag (D3) / Serial I/F Ch.2 status register (0x401F2) PER3: Ch.3 parity-error flag (D3) / Serial I/F Ch.3 status register (0x401F7) Indicates whether a parity error occurred. Read "1": Read "0": Write "1": Write "0": An error occurred No error occurred Invalid Reset to "0" The PERx flag is an error flag indicating whether a parity error occurred. When an error has occurred, it is set to "1". Parity checks are valid only in the asynchronous mode with EPRx set to "1" (parity added). This check is performed when the received data is transferred from the shift register to the receive data register. The PERx flag is reset by writing "0". At initial reset, as well as when RXENx and TXENx both are set to "0", PERx is set to "0" (no error). OER0: Ch.0 overrun-error flag (D2) / Serial I/F Ch.0 status register (0x401E2) OER1: Ch.1 overrun-error flag (D2) / Serial I/F Ch.1 status register (0x401E7) OER2: Ch.2 overrun-error flag (D2) / Serial I/F Ch.2 status register (0x401F2) OER3: Ch.3 overrun-error flag (D2) / Serial I/F Ch.3 status register (0x401F7) Indicates whether an overrun error occurred. Read "1": Read "0": Write "1": Write "0": An error occurred No error occurred Invalid Reset to "0" The OERx flag is an error flag indicating whether an overrun error occurred. When an error has occurred, it is set to "1". An overrun error occurs when the next receive operation is completed before the receive data register is read out, resulting in the receive data register being overwritten. The OERx flag is reset by writing "0". At initial reset, as well as when RXENx and TXENx both are set to "0", OERx is set to "0" (no error). TDBE0: Ch.0 transmit data buffer empty (D1) / Serial I/F Ch.0 status register (0x401E2) TDBE1: Ch.1 transmit data buffer empty (D1) / Serial I/F Ch.1 status register (0x401E7) TDBE2: Ch.2 transmit data buffer empty (D1) / Serial I/F Ch.2 status register (0x401F2) TDBE3: Ch.3 transmit data buffer empty (D1) / Serial I/F Ch.3 status register (0x401F7) Indicates the status of the transmit data register (buffer). Read "1": Buffer empty Read "0": Buffer full Write: Invalid TDBEx is set to "0" when transmit data is written to the transmit data register, and is set to "1" when this data is transferred to the shift register (transmit operation started). Transmit data is written to the transmit data register when this bit = "1". At initial reset, TDBEx is set to "1" (buffer empty). B-III-8-36 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 RDBF0: Ch.0 receive data buffer full (D0) / Serial I/F Ch.0 status register (0x401E2) RDBF1: Ch.1 receive data buffer full (D0) / Serial I/F Ch.1 status register (0x401E7) RDBF2: Ch.2 receive data buffer full (D0) / Serial I/F Ch.2 status register (0x401F2) RDBF3: Ch.3 receive data buffer full (D0) / Serial I/F Ch.3 status register (0x401F7) Indicates the status of the receive data register (buffer). Read "1": Buffer full Read "0": Buffer empty Write: Invalid RDBFx is set to "1" when the data received in the shift register is transferred to the receive data register (receive operation completed), indicating that the received data can be read out. This bit is reset to "0" when the data is read out. At initial reset, RDBFx is set to "0" (buffer empty). TXEN0: Ch.0 transmit enable (D7) / Serial I/F Ch.0 control register (0x401E3) TXEN1: Ch.1 transmit enable (D7) / Serial I/F Ch.1 control register (0x401E8) TXEN2: Ch.2 transmit enable (D7) / Serial I/F Ch.2 control register (0x401F3) TXEN3: Ch.3 transmit enable (D7) / Serial I/F Ch.3 control register (0x401F8) Enables each channel for transmit operations. Write "1": Transmit enabled Write "0": Transmit disabled Read: Valid When TXENx for a channel is set to "1", the channel is enabled for transmit operations. When TXENx is set to "0", the channel is disabled for transmit operations. Always make sure the TXENx = "0" before setting the transfer mode and other conditions. At initial reset, TXENx is set to "0" (transmit disabled). B-III RXEN0: Ch.0 receive enable (D6) / Serial I/F Ch.0 control register (0x401E3) RXEN1: Ch.1 receive enable (D6) / Serial I/F Ch.1 control register (0x401E8) RXEN2: Ch.2 receive enable (D6) / Serial I/F Ch.2 control register (0x401F3) RXEN3: Ch.3 receive enable (D6) / Serial I/F Ch.3 control register (0x401F8) Enables each channel for receive operations. Write "1": Receive enabled Write "0": Receive disabled Read: Valid When RXENx for a channel is set to "1", the channel is enabled for receive operations. When RXENx is set to "0", the channel is disabled for receive operations. Always make sure the RXENx = "0" before setting the transfer mode and other conditions. At initial reset, RXENx is set to "0" (receive disabled). S1C33L03 FUNCTION PART EPSON B-III-8-37 SIF III PERIPHERAL BLOCK: SERIAL INTERFACE EPR0: Ch.0 parity enable (D5) / Serial I/F Ch.0 control register (0x401E3) EPR1: Ch.1 parity enable (D5) / Serial I/F Ch.1 control register (0x401E8) EPR2: Ch.2 parity enable (D5) / Serial I/F Ch.2 control register (0x401F3) EPR3: Ch.3 parity enable (D5) / Serial I/F Ch.3 control register (0x401F8) Selects a parity function. Write "1": Parity added Write "0": No parity added Read: Valid EPRx is used to select whether receive data is to be checked for parity, and whether a parity bit is to be added to transmit data. When EPRx is set to "1", the receive data is checked for parity. A parity bit is automatically added to the transmit data. When EPRx is set to "0", parity is not checked and no parity bit is added. The parity function is only valid in the asynchronous mode. Settings of EPRx have no effect in the clocksynchronized mode. At initial reset, EPRx becomes indeterminate. PMD0: Ch.0 parity mode selection (D4) / Serial I/F Ch.0 control register (0x401E3) PMD1: Ch.1 parity mode selection (D4) / Serial I/F Ch.1 control register (0x401E8) PMD2: Ch.2 parity mode selection (D4) / Serial I/F Ch.2 control register (0x401F3) PMD3: Ch.3 parity mode selection (D4) / Serial I/F Ch.3 control register (0x401F8) Selects an odd or even parity. Write "1": Odd parity Write "0": Even parity Read: Valid Odd parity is selected by writing "1" to PMDx, and even parity is selected by writing "0". Parity check and the addition of a parity bit are only effective in asynchronous transfers in which EPRx is set to "1". If EPRx = "0", settings of PMDx do not have any effect. At initial reset, PMDx becomes indeterminate. STPB0: Ch.0 stop bit selection (D3) / Serial I/F Ch.0 control register (0x401E3) STPB1: Ch.1 stop bit selection (D3) / Serial I/F Ch.1 control register (0x401E8) STPB2: Ch.2 stop bit selection (D3) / Serial I/F Ch.2 control register (0x401F3) STPB3: Ch.3 stop bit selection (D3) / Serial I/F Ch.3 control register (0x401F8) Selects a stop-bit length during the performance of an asynchronous transfer. Write "1": 2 bits Write "0": 1 bit Read: Valid STPBx is only valid in an asynchronous transfer. Two stop bits are selected by writing "1" to STPBx , and one stop bit is selected by writing "0". The start bit is fixed at 1 bit. Settings of STPBx are ignored during the performance of a clock-synchronized transfer. At initial reset, STPBx becomes indeterminate. B-III-8-38 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 SSCK0: Ch.0 input clock selection (D2) / Serial I/F Ch.0 control register (0x401E3) SSCK1: Ch.1 input clock selection (D2) / Serial I/F Ch.1 control register (0x401E8) SSCK2: Ch.2 input clock selection (D2) / Serial I/F Ch.2 control register (0x401F3) SSCK3: Ch.3 input clock selection (D2) / Serial I/F Ch.3 control register (0x401F8) Selects the clock source for an asynchronous transfer. Write "1": #SCLK (external clock) Write "0": Internal clock Read: Valid During operation in the asynchronous mode, this bit is used to select the clock source between an internal clock (output by an 8-bit programmable timer) and an external clock (input from the #SCLKx pin). An external clock is selected by writing "1" to this bit, and an internal clock is selected by writing "0". At initial reset, SSCKx becomes indeterminate. SMD01-SMD00: Ch.0 transfer mode selection (D[1:0]) / Serial I/F Ch.0 control register (0x401E3) SMD11-SMD10: Ch.1 transfer mode selection (D[1:0]) / Serial I/F Ch.1 control register (0x401E8) SMD21-SMD20: Ch.2 transfer mode selection (D[1:0]) / Serial I/F Ch.2 control register (0x401F3) SMD31-SMD30: Ch.3 transfer mode selection (D[1:0]) / Serial I/F Ch.3 control register (0x401F8) Sets the transfer mode of the serial interface as shown in Table 8.15 below. Table 8.15 Setting of Transfer Mode SMDx1 SMDx0 Transfer mode 1 1 0 0 1 0 1 0 8-bit asynchronous mode 7-bit asynchronous mode Clock-synchronized slave mode Clock-synchronized master mode The SMDx bit can be read as well as written. When using the IrDA interface, always be sure to set an asynchronous mode for the transfer mode. At initial reset, SMDx becomes indeterminate. B-III DIVMD0: Sampling clock division ratio (D4) / Serial I/F Ch.0 IrDA register (0x401E4) DIVMD1: Sampling clock division ratio (D4) / Serial I/F Ch.1 IrDA register (0x401E9) DIVMD2: Sampling clock division ratio (D4) / Serial I/F Ch.2 IrDA register (0x401F4) DIVMD3: Sampling clock division ratio (D4) / Serial I/F Ch.3 IrDA register (0x401F9) Selects the division ratio of the sampling clock. Write "1": 1/8 Write "0": 1/16 Read: Valid SIF Select the division ratio necessary to generate the sampling clock for asynchronous transfers. When DIVMDx is set to "1", the sampling clock is generated from the input clock of the serial interface (output by an 8-bit programmable timer or input from #SCLKx) by dividing it by 8. When DIVMDx is set to "0", the input clock is divided by 16. At initial reset, DIVMDx becomes indeterminate. S1C33L03 FUNCTION PART EPSON B-III-8-39 III PERIPHERAL BLOCK: SERIAL INTERFACE IRTL0: Ch.0 IrDA output logic inversion (D3) / Serial I/F Ch.0 IrDA register (0x401E4) IRTL1: Ch.1 IrDA output logic inversion (D3) / Serial I/F Ch.1 IrDA register (0x401E9) IRTL2: Ch.2 IrDA output logic inversion (D3) / Serial I/F Ch.2 IrDA register (0x401F4) IRTL3: Ch.3 IrDA output logic inversion (D3) / Serial I/F Ch.3 IrDA register (0x401F9) Inverts the logic of the IrDA output signal. Write "1": Inverted Write "0": Not inverted Read: Valid When using the IrDA interface, set the logic of the SOUTx output signal to suit the infrared-ray communication circuit that is connected external to the chip. If IRTLx is set to "1", a high pulse is output when the output data = "0" (held low-level when the output data = "1"). If IRTLx is set to "0", a low pulse is output when the output data = "0" (held high-level when the output data = "1"). At initial reset, IRTLx becomes indeterminate. IRRL0: Ch.0 IrDA input logic inversion (D2) / Serial I/F Ch.0 IrDA register (0x401E4) IRRL1: Ch.1 IrDA input logic inversion (D2) / Serial I/F Ch.1 IrDA register (0x401E9) IRRL2: Ch.2 IrDA input logic inversion (D2) / Serial I/F Ch.2 IrDA register (0x401F4) IRRL3: Ch.3 IrDA input logic inversion (D2) / Serial I/F Ch.3 IrDA register (0x401F9) Inverts the logic of the IrDA input signal. Write "1": Inverted Write "0": Not inverted Read: Valid When using the IrDA interface, set the logic of the signal that is input from an external infrared-ray communication circuit to the chip to suit the serial interface. If IRRLx is set to "1", a high pulse is input as a logic "0". If IRRLx is set to "0", a low pulse is input as a logic "0". At initial reset, IRRLx becomes indeterminate. IRMD01-IRMD00: Ch.0 IrDA interface mode selection (D[1:0]) / Serial I/F Ch.0 IrDA register (0x401E4) IRMD11-IRMD10: Ch.1 IrDA interface mode selection (D[1:0]) / Serial I/F Ch.1 IrDA register (0x401E9) IRMD21-IRMD20: Ch.2 IrDA interface mode selection (D[1:0]) / Serial I/F Ch.2 IrDA register (0x401F4) IRMD31-IRMD30: Ch.3 IrDA interface mode selection (D[1:0]) / Serial I/F Ch.3 IrDA register (0x401F9) Selects the IrDA interface function. Table 8.16 IrDA Interface Setting IRMDx1 IRMDx0 1 1 0 0 1 0 1 0 Interface mode Do not set. (reserved) IrDA 1.0 interface Do not set. (reserved) Normal interface When using the IrDA interface function, write "10" to IRMDx while setting to an asynchronous mode for the transfer mode. If the IrDA interface function is not to be used, write "00" to IRMDx. At initial reset, IRMDx becomes indeterminate. Note: This selection must always be performed before the transfer mode and other conditions are set. PSIO02-PSIO00: Ch.0 interrupt level (D[6:4]) / 8-bit timer, serial I/F Ch.0 interrupt priority register (0x40269) PSIO12-PSIO10: Ch.1 interrupt level (D[2:0]) / Serial I/F Ch.1, A/D interrupt priority register (0x4026A) Sets the priority level of the serial-interface interrupt. The interrupt priority level can be set for each channel in the range of 0 to 7. At initial reset, PSIOx becomes indeterminate. B-III-8-40 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 ESERR0, ESRX0, ESTX0: Ch.0 interrupt enable (D0,D1,D2) / Serial I/F interrupt enable register (0x40276) ESERR1, ESRX1, ESTX1: Ch.1 interrupt enable (D3,D4,D5) / Serial I/F interrupt enable register (0x40276) Enable or disable interrupt generation to the CPU. Write "1": Interrupt enabled Write "0": Interrupt disabled Read: Valid The ESERRx, ESRXx, and ESTXx bits are interrupt enable bits corresponding to receive-error, receive-buffer full, and transmit-buffer empty interrupt factors, respectively, in each channel. The interrupts for which this bit is set to "1" are enabled, and the interrupts for which this bit is set to "0" are disabled. At initial reset, all these bits are set to "0" (interrupts disabled). FSERR0, FSRX0, FSTX0: Ch.0 interrupt factor flags (D0,D1,D2) / Serial I/F interrupt factor flag register (0x40286) FSERR1, FSRX1, FSTX1: Ch.1 interrupt factor flags (D3,D4,D5) / Serial I/F interrupt factor flag register (0x40286) Indicate the status of serial-interface interrupt generation. When read Read "1": An interrupt factor occurred Read "0": No interrupt factor occurred When written using the reset-only method (default) Write "1": Flag is reset Write "0": Invalid When written using the read/write method Write "1": Flag is set Write "0": Flag is reset The FSERRx, FSRXx, and FSTXx flags are interrupt factor flags corresponding to receive-error, receive-buffer full, and transmit-buffer empty interrupts, respectively, in each channel. The flag is set to "1" when each interrupt factor occurs. A transmit-buffer empty interrupt factor occurs when transmit data is transferred from the transmit data register to the shift register. A receive-buffer full interrupt factor occurs when receive data is transferred from the shift register to the receive data register. A receive-error interrupt factor occurs when a parity, framing, or overrun error is detected during reception of data. At this time, if the following conditions are met, an interrupt to the CPU is generated: 1. The corresponding interrupt enable register bit is set to "1". 2. No other interrupt request of a higher priority has been generated. 3. The PSR's IE bit is set to "1" (interrupts enabled). 4. The set value of the corresponding interrupt priority register is higher than the CPU interrupt level (IL). When using the receive-buffer full or transmit-buffer empty interrupt factor as an IDMA request, the fact that the above conditions are met does not necessarily mean that an interrupt request to the CPU has been output simultaneously when an interrupt factor occurs. An interrupt is generated under the above conditions upon completion of the data transfer by IDMA, provided that interrupts are enabled by settings on the IDMA side. The interrupt factor flag is set to "1" whenever an interrupt factor occurs, regardless of the settings of the interruptenable and interrupt priority registers. If the next interrupt is to be accepted following the occurrence of an interrupt, it is necessary that the interrupt factor flag be reset, and that the PSR be set up again (by setting the IE bit to "1" after setting the IL to a value lower than the level indicated by the interrupt priority register, or by executing the reti instruction). The interrupt factor flag can only be reset by writing to it in the software. Note that if the PSR is set up again to accept interrupts generated (or if the reti instruction is executed) without resetting the interrupt factor flag, the same interrupt occurs again. Note also that the value to be written to reset the flag is "1" when the reset-only method (RSTONLY = "1") is used, and "0" when the read/write method (RSTONLY = "0") is used. At initial reset, all of these flags become indeterminate, so be sure to reset them in the software. S1C33L03 FUNCTION PART EPSON B-III-8-41 B-III SIF III PERIPHERAL BLOCK: SERIAL INTERFACE RSRX0, RSTX0: Ch.0 IDMA request (D6, D7) / 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA request register (0x40292) RSRX1, RSTX1: Ch.1 IDMA request (D0, D1) / Serial I/F Ch.1, A/D IDMA request register (0x40293) Specifies whether to invoke IDMA when an interrupt factor occurs. When using the set-only method (default) Write "1": IDMA request Write "0": Not changed Read: Valid When using the read/write method Write "1": IDMA request Write "0": Interrupt request Read: Valid The RSRXx and RSTXx bits are IDMA request bits corresponding to receive-buffer full and transmit-buffer empty interrupt factors, respectively. If the bit is set to "1", IDMA is invoked when an interrupt factor occurs, thus performing a programmed data transfer. If this bit is set to "0", normal interrupt processing is performed, without invoking IDMA. For details on IDMA, refer to "IDMA (Intelligent DMA)". At initial reset, these bits are set to "0" (interrupt request). DESRX0, DESTX0: Ch.0 IDMA enable (D6, D7) / 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA enable register (0x40296) DESRX1, DESTX1: Ch.1 IDMA enable (D0, D1) / Serial I/F Ch.1, A/D IDMA enable register (0x40297) Enables IDMA transfer by means of an interrupt factor. When using the set-only method (default) Write "1": IDMA enabled Write "0": Not changed Read: Valid When using the read/write method Write "1": IDMA enabled Write "0": IDMA disabled Read: Valid The DESRXx and DESTXx bits are IDMA enable bits corresponding to receive-buffer full and transmit-buffer empty interrupt factors, respectively. If the bit is set to "1", the IDMA request by the interrupt factor is enabled. If the bit is set to "0", the IDMA request is disabled. At initial reset, these bits are set to "0" (IDMA disabled). SIO2ES0: SIO Ch.2 receive error/FP0 interrupt factor switching (D0) / Interrupt factor FP function switching register (0x402C5) Switches the interrupt factor. Write "1": SIO Ch.2 receive error Write "0": FP0 input Read: Valid Set to "1" to use the SIO Ch.2 receive error interrupt. Set to "0" to use the FP0 input interrupt. At power-on, this bit is set to "0". B-III-8-42 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 SIO2RS0: SIO Ch.2 receive-buffer full/FP1 interrupt factor switching (D1) / Interrupt factor FP function switching register (0x402C5) Switches the interrupt factor. Write "1": SIO Ch.2 receive-buffer full Write "0": FP1 input Read: Valid Set to "1" to use the SIO Ch.2 receive-buffer full interrupt. Set to "0" to use the FP1 input interrupt. At power-on, this bit is set to "0". SIO3ES0: SIO Ch.3 receive error/FP2 interrupt factor switching (D2) / Interrupt factor FP function switching register (0x402C5) Switches the interrupt factor. Write "1": SIO Ch.3 receive error Write "0": FP2 input Read: Valid Set to "1" to use the SIO Ch.3 receive error interrupt. Set to "0" to use the FP2 input interrupt. At power-on, this bit is set to "0". SIO2TS0: SIO Ch.2 transmit-buffer empty/FP3 interrupt factor switching (D3) / Interrupt factor FP function switching register (0x402C5) Switches the interrupt factor. Write "1": SIO Ch.2 transmit-buffer empty Write "0": FP3 input Read: Valid B-III Set to "1" to use the SIO Ch.2 transmit-buffer empty interrupt. Set to "0" to use the FP3 input interrupt. At power-on, this bit is set to "0". SIO3RS0: SIO Ch.3 receive-buffer full/FP4 interrupt factor switching (D4) / Interrupt factor FP function switching register (0x402C5) Switches the interrupt factor. Write "1": SIO Ch.3 receive-buffer full Write "0": FP4 input Read: Valid SIF Set to "1" to use the SIO Ch.3 receive-buffer full interrupt. Set to "0" to use the FP4 input interrupt. At power-on, this bit is set to "0". T8CH4S0: 8-bit timer 4 underflow/FP5 interrupt factor switching (D5) / Interrupt factor FP function switching register (0x402C5) Switches the interrupt factor. Write "1": 8-bit timer 4 underflow Write "0": FP5 input Read: Valid Set to "1" to use the 8-bit timer 4 underflow interrupt. Set to "0" to use the FP5 input interrupt. At power-on, this bit is set to "0". S1C33L03 FUNCTION PART EPSON B-III-8-43 III PERIPHERAL BLOCK: SERIAL INTERFACE SIO3TS0: SIO Ch.3 transmit-buffer empty/FP6 interrupt factor switching (D6) / Interrupt factor FP function switching register (0x402C5) Switches the interrupt factor. Write "1": SIO Ch.3 transmit-buffer empty Write "0": FP6 input Read: Valid Set to "1" to use the SIO Ch.3 transmit-buffer empty interrupt. Set to "0" to use the FP6 input interrupt. At power-on, this bit is set to "0". T8CH5S0: 8-bit timer 5 underflow/FP7 interrupt factor switching (D7) / Interrupt factor FP function switching register (0x402C5) Switches the interrupt factor. Write "1": 8-bit timer 5 underflow Write "0": FP7 input Read: Valid Set to "1" to use the 8-bit timer 5 underflow interrupt. Set to "0" to use the FP7 input interrupt. At power-on, this bit is set to "0". SIO2RS1: SIO Ch.2 receive-buffer full/TM16 Ch.5 compare B interrupt factor switching (D0) / Interrupt factor TM16 function switching register (0x402CB) Switches the interrupt factor. Write "1": SIO Ch.2 receive-buffer full Write "0": TM16 Ch.5 compare B Read: Valid Set to "1" to use the SIO Ch.2 receive-buffer full interrupt. Set to "0" to use the TM16 Ch.5 compare B interrupt. At power-on, this bit is set to "0". SIO2TS1: SIO Ch.2 transmit-buffer empty/TM16 Ch.5 compare A interrupt factor switching (D1) / Interrupt factor TM16 function switching register (0x402CB) Switches the interrupt factor. Write "1": SIO Ch.2 transmit-buffer empty Write "0": TM16 Ch.5 compare A Read: Valid Set to "1" to use the SIO Ch.2 transmit-buffer empty interrupt. Set to "0" to use the TM16 Ch.5 compare A interrupt. At power-on, this bit is set to "0". SIO3RS1: SIO Ch.3 receive-buffer full/TM16 Ch.4 compare B interrupt factor switching (D2) / Interrupt factor TM16 function switching register (0x402CB) Switches the interrupt factor. Write "1": SIO Ch.3 receive-buffer full Write "0": TM16 Ch.4 compare B Read: Valid Set to "1" to use the SIO Ch.3 receive-buffer full interrupt. Set to "0" to use the TM16 Ch.4 compare B interrupt. At power-on, this bit is set to "0". B-III-8-44 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE A-1 SIO3TS1: SIO Ch.3 transmit-buffer empty/TM16 Ch.4 compare A interrupt factor switching (D3) / Interrupt factor TM16 function switching register (0x402CB) Switches the interrupt factor. Write "1": SIO Ch.3 transmit-buffer empty Write "0": TM16 Ch.4 compare A Read: Valid Set to "1" to use the SIO Ch.3 transmit-buffer empty interrupt. Set to "0" to use the TM16 Ch.4 compare A interrupt. At power-on, this bit is set to "0". SIO2ES1: SIO Ch.2 receive error/TM16 Ch.3 compare B interrupt factor switching (D4) / Interrupt factor TM16 function switching register (0x402CB) Switches the interrupt factor. Write "1": SIO Ch.2 receive error Write "0": TM16 Ch.3 compare B Read: Valid Set to "1" to use the SIO Ch.2 receive error interrupt. Set to "0" to use the TM16 Ch.3 compare B interrupt. At power-on, this bit is set to "0". SIO3ES1: SIO Ch.3 receive error/TM16 Ch.3 compare A interrupt factor switching (D5) / Interrupt factor TM16 function switching register (0x402CB) Switches the interrupt factor. Write "1": SIO Ch.3 receive error Write "0": TM16 Ch.3 compare A Read: Valid B-III Set to "1" to use the SIO Ch.3 receive error interrupt. Set to "0" to use the TM16 Ch.3 compare A interrupt. At power-on, this bit is set to "0". T8CH4S1: 8-bit timer 4 underflow/TM16 Ch.2 compare B interrupt factor switching (D6) / Interrupt factor TM16 function switching register (0x402CB) Switches the interrupt factor. Write "1": 8-bit timer 4 underflow Write "0": TM16 Ch.2 compare B Read: Valid SIF Set to "1" to use the 8-bit timer 4 underflow interrupt. Set to "0" to use the TM16 Ch.2 compare B interrupt. At power-on, this bit is set to "0". T8CH5S1: 8-bit timer 5 underflow/TM16 Ch.2 compare A interrupt factor switching (D7) / Interrupt factor TM16 function switching register (0x402CB) Switches the interrupt factor. Write "1": 8-bit timer 5 underflow Write "0": TM16 Ch.2 compare A Read: Valid Set to "1" to use the 8-bit timer 5 underflow interrupt. Set to "0" to use the TM16 Ch.2 compare A interrupt. At power-on, this bit is set to "0". S1C33L03 FUNCTION PART EPSON B-III-8-45 III PERIPHERAL BLOCK: SERIAL INTERFACE Programming Notes (1) Before setting various serial-interface parameters, make sure the transmit and receive operations are disabled (TXENx = RXENx = "0"). (2) When the serial interface is transmitting or receiving data, do not set TXENx or RXENx to "0", and do not execute the slp instruction. (3) In clock-synchronized transfers, the mode of communication is half-duplex, in which the clock line is shared between the transmit and receive units. Therefore, RXENx and TXENx cannot be enabled simultaneously. (4) After an initial reset, the interrupt factor flag becomes indeterminate. To prevent generation of an unwanted interrupt or IDMA request, reset this flag in the program. (5) If a receive error occurs, the receive-error interrupt and receive-buffer full interrupt factors occur simultaneously. However, since the receive-error interrupt has priority over the receive-buffer full interrupt, the receive-error interrupt is processed first. Therefore, it is necessary to reset the receive-buffer full interrupt factor flag through the use of the receive-error interrupt processing routine. (6) To prevent the regeneration of interrupts due to the same factor following the occurrence of an interrupt, always be sure to reset the interrupt factor flag before setting the PSR again or executing the reti instruction. (7) Follow the procedure described below to initialize the serial interface. Set IRMDx[1:0] "00"(normal I/F) or "10"(IrDA I/F) Set SMDx[1:0] Transfer mode setting Other settings Data format and clock selection Internal division ratio, IrDA I/O logic and other settings Enable transmitting/receiving Enable transmitting, receiving or both Figure 8.18 Serial Interface Initialize Procedure (8) When transmitting data in the clock-synchronized master mode, transmit data is written to the transmit data register after the initial setting is performed following the flow in item (7). However, the clock generated by the 8-bit timer must be supplied to the serial interface (at least one underflow has had to have occurred in the 8-bit tier) before this writing. Otherwise, 0xFF will be transmitted prior to the written data. (9) The maximum transfer rate of the serial interface is limited to 1 Mbps. (10) If the receive circuit is stopped during reception, set both transmission and reception to the disabled status. (11) When performing data transfer in the clock-synchronized mode, the division ratio of the prescaler and the reload data for the 8-bit programmable timer should be set so that the baud-rate is 1/4 of the system clock frequency or lower. (12) The serial interface operates only when the prescaler is operating. B-III-8-46 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS A-1 III-9 INPUT/OUTPUT PORTS The Peripheral Block has a total of 42 input/output ports. Although each pin is used for input/output from/to the internal peripheral circuits, some pins can be used as general-purpose input/output ports unless they are used for the peripheral circuits. Input Ports (K Ports) Structure of Input Port The Peripheral Block contains 13 bits of input ports (K50 to K54, K60 to K67). Figure 9.1 shows the structure of a typical input port. Input interrupt circuit 2 KxxD Kxx Address VSS Internal data bus VDDE 1 1 AVDDE for K50 and K60-K67 2 Available only for K50-K54 Figure 9.1 Structure of Input Port Each input-port pin is connected directly to the internal data bus via a three-state buffer. The state of the input signal when read at an input port is directly taken into the internal circuit as data. When K50 is used as an input port and K60 to K67 are used as general-purpose input ports, the power supply for the port input buffers is AVDDE. Therefore, when these ports are used as high-level or low-level input ports, the high level must be AVDDE, and the low level VSS. If there is a potential difference between AVDDE and VDDE, in particular, if the level from outside is VDDE, a current may flow in the input buffer (when AVDDE > VDDE) or between VDDE and AVDDE (when AVDDE < VDDE). Therefore, if these ports are not used, when the input level is fixed externally, it should be fixed at VSS or AVDDE. The K50 port is provided with a pull-up resistance that pulls the port up to AVDDE. B-III I/O S1C33L03 FUNCTION PART EPSON B-III-9-1 III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS Input-Port Pins The input pins concurrently serve as the input pins for peripheral circuits, as shown in Table 9.1. Whether they are used as input ports or for peripheral circuits can be set bit-for-bit using a function select register. All pins not used for peripheral circuits can be used as general-purpose input ports that have an interrupt function. Table 9.1 Input Pins Pin name K50/#DMAREQ0 K51/#DMAREQ1 K52/#ADTRG K53/#DMAREQ2 K54/#DMAREQ3 K60/AD0 K61/AD1 K62/AD2 K63/AD3 K64/AD4 K65/AD5 K66/AD6 K67/AD7 I/O Pull-up I I I I I I I I I I I I I Available Available Available Available Available - - - - - - - - Function Input port / High-speed DMA request 0 Input port / High-speed DMA request 1 Input port / AD converter trigger Input port / High-speed DMA request 2 Input port / High-speed DMA request 3 Input port / AD converter input 0 Input port / AD converter input 1 Input port / AD converter input 2 Input port / AD converter input 3 Input port / AD converter input 4 Input port / AD converter input 5 Input port / AD converter input 6 Input port / AD converter input 7 Function select bit CFK50(D0)/K5 function select register(0x402C0) CFK51(D1)/K5 function select register(0x402C0) CFK52(D2)/K5 function select register(0x402C0) CFK53(D3)/K5 function select register(0x402C0) CFK54(D4)/K5 function select register(0x402C0) CFK60(D0)/K6 function select register(0x402C3) CFK61(D1)/K6 function select register(0x402C3) CFK62(D2)/K6 function select register(0x402C3) CFK63(D3)/K6 function select register(0x402C3) CFK64(D4)/K6 function select register(0x402C3) CFK65(D5)/K6 function select register(0x402C3) CFK66(D6)/K6 function select register(0x402C3) CFK67(D7)/K6 function select register(0x402C3) At cold start, all pins are set for input ports Kxx (function select register CFKxx = "0"). When these pins are used for the internal peripheral circuits, write "1" to CFKxx. For details on pin functions in this case, refer to the description of each peripheral circuit in this manual. At hot start, the pins retain their state from prior to the reset. When the ports set for A/D converter input are read, the value obtained is always "0". Notes on Use The input buffers of the K50 and K60 to K67 ports use AVDDE (power voltage for A/D converter) as their power source. Furthermore, the K50 pull-up resistor is connected to AVDDE. Therefore, the following precautions must be taken. 1) When using K50 and K60-K67 as general-purpose input ports, the voltage input to the port must be high level = AVDDE and low level = VSS. 2) When using VDDE as high level similar to other ports, VDDE must be the same voltage level as AVDDE. If the input VDDE level is lower than the AVDDE level, current flows in the input buffer, or if the input VDDE level is higher than the AVDDE level, current flows from the VDDE power supply to the AVDDE power supply. 3) To fix the input level externally when the port is not used, the input pin should be connected to VSS or AVDDE. B-III-9-2 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS A-1 I/O Memory of Input Ports Table 9.2 shows the control bits of the input ports. Table 9.2 Control Bits of Input Ports Register name Address Bit Name Function K5 function select register 00402C0 D7-5 - (B) D4 CFK54 D3 CFK53 D2 CFK52 D1 CFK51 D0 CFK50 reserved K54 function selection K53 function selection K52 function selection K51 function selection K50 function selection K5 input port data register 00402C1 D7-5 - (B) D4 K54D D3 K53D D2 K52D D1 K51D D0 K50D reserved K54 input port data K53 input port data K52 input port data K51 input port data K50 input port data K6 function select register 00402C3 (B) D7 D6 D5 D4 D3 D2 D1 D0 CFK67 CFK66 CFK65 CFK64 CFK63 CFK62 CFK61 CFK60 K6 input port data register 00402C4 (B) D7 D6 D5 D4 D3 D2 D1 D0 K67D K66D K65D K64D K63D K62D K61D K60D Setting Init. R/W - 1 1 1 1 1 #DMAREQ3 #DMAREQ2 #ADTRG #DMAREQ1 #DMAREQ0 0 0 0 0 0 K54 K53 K52 K51 K50 - - R R R R R K67 K66 K65 K64 K63 K62 K61 K60 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 Low - - - - - - - - R R R R R R R R 0 Low K67 function selection K66 function selection K65 function selection K64 function selection K63 function selection K62 function selection K61 function selection K60 function selection 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 K67 input port data K66 input port data K65 input port data K64 input port data K63 input port data K62 input port data K61 input port data K60 input port data 1 High Remarks - 0 when being read. R/W R/W R/W R/W R/W - - - - - - 1 High AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 - 0 0 0 0 0 0 when being read. B-III CFK54-CFK50: K5[4:0] function selection (D[4:0]) / K5 function select register (0x402C0) CFK67-CFK60: K6[7:0] function selection (D[7:0]) / K6 function select register (0x402C3) Selects the function of each input-port pin. Write "1": Used for peripheral circuit Write "0": Input port pin Read: Invalid When a bit of the CFK register is set to "1", the corresponding pin is set for use with the peripheral circuit (see Table 9.1). The pins for which register bits are set to "0" can be used as general-purpose input ports. At cold start, CFK is set to "0" (input port). At hot start, CFK retains its state from prior to the initial reset. I/O K54D-K50D: K5[4:0] input port data (D[4:0]) / K5 input port data register (0x402C1) K67D-K60D: K6[7:0] input port data (D[7:0]) / K6 input port data register (0x402C4) The input data on each input port pin can be read from this register. Read "1": High level Read "0": Low level Write: Invalid The pin voltage of each input port can be read out "1" directly when the voltage is high (VDD) or "0" when the voltage is low (VSS) respectively. Since this register is a read-only register, writing to the register is ignored. When the ports set for A/D converter input are read, the value obtained is always "0". S1C33L03 FUNCTION PART EPSON B-III-9-3 III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS I/O Ports (P Ports) Structure of I/O Port The Peripheral Block contains 29 bits of I/O ports (P00 to P07, P10 to P16, P20 to P27, P30 to P35) that can be directed for input or output through the use of a program. Figure 9.2 shows the structure of a typical I/O port. VDDE Internal data bus I/O control register Peripheral circuit I/O control I/O control signal Function select register Pxx Data register Peripheral circuit output VSS Peripheral circuit input Figure 9.2 Structure of I/O Port I/O Port Pins The I/O ports concurrently serve as the input/output pins for peripheral circuits, as shown in Table 9.3. Whether they are used as I/O ports or for peripheral circuits can be set bit-for-bit using a function select register. All pins not used for peripheral circuits can be used as general-purpose I/O ports. Table 9.3 I/O Pins Pin name P00/SIN0 P01/SOUT0 P02/#SCLK0 P03/#SRDY0 P04/SIN1/ #DMAACK2 P05/SOUT1/ #DMAEND2 P06/#SCLK1/ #DMAACK3 P07/#SRDY1/ #DMAEND3 P10/EXCL0/ T8UF0/DST0 P11/EXCL1/ T8UF1/DST1 P12/EXCL2/ T8UF2/DST2 P13/EXCL3/ T8UF3/DPCO P14/FOSC1/ DCLK P15/EXCL4/ #DMAEND0/ #SCLK3 P16/EXCL5/ #DMAEND1/ SOUT3 I/O I/O I/O I/O I/O I/O Pull-up - - - - - I/O - I/O - I/O - I/O - I/O - I/O - I/O - I/O - I/O - I/O - Function I/O port / Serial IF Ch.0 data input I/O port / Serial IF Ch.0 data output I/O port / Serial IF Ch.0 clock input/output I/O port / Serial IF Ch.0 ready input/output I/O port / Serial IF Ch.1 data input / #DMAACK2 output (Ex) I/O port / Serial IF Ch.1 data output / #DMAEND2 output (Ex) I/O port / Serial IF Ch.1 clock input/output / #DMAACK3 output (Ex) I/O port / Serial IF Ch.1 ready input/output / #DMAEND3 output (Ex) I/O port / 16-bit timer 0 event counter input (I) / 8-bit timer 0 output (O) / DST0 output (Ex) I/O port / 16-bit timer 1 event counter input (I) / 8-bit timer 1 output (O) / DST1 output (Ex) I/O port / 16-bit timer 2 event counter input (I) / 8-bit timer 2 output (O) / DST2 output (Ex) I/O port / 16-bit timer 3 event counter input (I) / 8-bit timer 3 output (O) / DPCO output (Ex) I/O port / Low-speed (OSC1) clock output / DCLK output (Ex) I/O port / 16-bit timer 4 event counter input (I) / #DMAEND0 output (O) / Serial IF Ch.3 clock input/output I/O port / 16-bit timer 5 event counter input (I) / #DMAEND1 output (O) / Serial IF Ch.3 data output Function select bit CFP00(D0)/P0 function select register(0x402D0) CFP01(D1)/P0 function select register(0x402D0) CFP02(D2)/P0 function select register(0x402D0) CFP03(D3)/P0 function select register(0x402D0) CFP04(D4)/P0 function select register(0x402D0) CFEX4(D4)/Port function extension register(0x402DF) CFP05(D5)/P0 function select register(0x402D0) CFEX5(D5)/Port function extension register(0x402DF) CFP06(D6)/P0 function select register(0x402D0) CFEX6(D6)/Port function extension register(0x402DF) CFP07(D7)/P0 function select register(0x402D0) CFEX7(D7)/Port function extension register(0x402DF) CFP10(D0)/P1 function select register(0x402D4) CFEX1(D1)/Port function extension register(0x402DF) CFP11(D1)/P1 function select register(0x402D4) CFEX1(D1)/Port function extension register(0x402DF) CFP12(D2)/P1 function select register(0x402D4) CFEX0(D0)/Port function extension register(0x402DF) CFP13(D3)/P1 function select register(0x402D4) CFEX1(D1)/Port function extension register(0x402DF) CFP14(D4)/P1 function select register(0x402D4) CFEX0(D0)/Port function extension register(0x402DF) CFP15(D5)/P1 function select register(0x402D4) CFP16(D6)/P1 function select register(0x402D4) (I): Input mode, (O): Output mode, (Ex): Extended function : A 3-V system I/O voltage can only be used for the P10-P14 pins. B-III-9-4 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS Pin name P20/#DRD P21/#DWE/ #GAAS P22/TM0 P23/TM1 P24/TM2/ #SRDY2 P25/TM3/ #SCLK2 P26/TM4/ SOUT2 P27/TM5/SIN2 I/O I/O I/O P30/#WAIT/ #CE4&5 P31/#BUSGET/ #GARD P32/#DMAACK0 /#SRDY3 P33/#DMAACK1 /SIN3 P34/#BUSREQ/ #CE6 P35/#BUSACK I/O I/O I/O I/O I/O I/O I/O Pull-up Function - I/O port / #DRD output - I/O port / #DWE output / GA address strobe output (Ex) - I/O port / 16-bit timer 0 output - I/O port / 16-bit timer 1 output - I/O port / 16-bit timer 2 output / Serial IF Ch.2 ready input/output - I/O port / 16-bit timer 3 output / Serial IF Ch.2 clock input/output - I/O port / 16-bit timer 4 output / Serial IF Ch.2 data output - I/O port / 16-bit timer 5 output / Serial IF Ch.2 data input - I/O port / #WAIT input (I) / #CE4&5 output (O) I/O - I/O - I/O - I/O - I/O - I/O port / #BUSGET output / GA read signal output (Ex) I/O port / #DMAACK0 output / Serial IF Ch.3 ready input/output I/O port / #DMAACK1 output / Serial IF Ch.3 data input I/O port / #BUSREQ input (I) / #CE6 output (O) I/O port / #BUSACK output Function select bit CFP20(D0)/P2 function select register(0x402D8) CFP21(D1)/P2 function select register(0x402D8) CFEX2(D2)/Port function extension register(0x402DF) CFP22(D2)/P2 function select register(0x402D8) CFP23(D3)/P2 function select register(0x402D8) CFP24(D4)/P2 function select register(0x402D8) A-1 CFP25(D5)/P2 function select register(0x402D8) CFP26(D6)/P2 function select register(0x402D8) CFP27(D7)/P2 function select register(0x402D8) CFP30(D0)/P3 function select register(0x402DC) CFP31(D1)/P3 function select register(0x402DC) CFEX3(D3)/Port function extension register(0x402DF) CFP32(D2)/P3 function select register(0x402DC) CFP33(D3)/P3 function select register(0x402DC) CFP34(D4)/P3 function select register(0x402DC) CFP35(D5)/P3 function select register(0x402DC) (I): Input mode, (O): Output mode, (Ex): Extended function At cold start, all pins are set for I/O ports Pxx (function select register CFPxx = "0"). When these pins are used for the internal peripheral circuits, write "1" to CFPxx. For details on pin functions in this case, refer to the description of each peripheral circuit in this manual. At hot start, the pins retain their state from prior to the reset. In addition to being an I/O port, the P10-P13, P15-P16, P30 and P34 pins are shared with two types (three types for P10-P13) of peripheral circuits. The type of peripheral circuit for which these pins are used is determined by the direction (input or output) in which the pin is set using an I/O control register, as will be described later. The P04-P07, P10-P14, P21 and P31 ports have extended functions indicated with (Ex) in the table. They can be selected by writing "1" to CFEXx / Port function extension register (0x402DF). The setting of CFEXx has priority over the CFPxx. At cold start, CFEX1 and CFEX0 are set to "1", so the P10-P14 pins are set for debug signal outputs. B-III I/O Control Register and I/O Modes The I/O ports are directed for input or output modes by writing data to an I/O control register corresponding to each port bit. P07-P00 I/O control: IOC0[7:0] (D[7:0]) / P0 I/O control register (0x402D2) P16-P10 I/O control: IOC1[6:0] (D[6:0]) / P1 I/O control register (0x402D6) P27-P20 I/O control: IOC2[7:0] (D[7:0]) / P2 I/O control register (0x402DA) P35-P30 I/O control: IOC3[5:0] (D[5:0]) / P3 I/O control register (0x402DE) To set an I/O port for input, write "0" to the I/O control bit. I/O ports set for input mode are placed in the highimpedance state, and thus function as input ports. In the input mode, the state of the input pin is read directly, so the data is "1" when the pin state is high (VDD level) or "0" when the pin state is low (VSS level). Even in the input mode, data can be written to the data register without affecting the pin state. To set an I/O port for output, write "1" to the I/O control bit. I/O port set for output function as output ports. When the port output data is "1", the port outputs a high level (VDD level); when the data is "0", the port outputs a low level (VSS level). At cold start, the I/O control register is set to "0" (input mode). At hot start, the pins retain their state from prior to the reset. Note: If pins P10-P14, P15-P16, P30 and P34 are set for use with peripheral circuits, their pin functions vary depending on the input/output direction control by the IOC1x register. S1C33L03 FUNCTION PART EPSON B-III-9-5 I/O III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS I/O Memory of I/O Ports Table 9.4 shows the control bits of the I/O ports. Table 9.4 Control Bits of I/O Ports Register name Address Bit Name P0 function select register 00402D0 (B) D7 D6 D5 D4 D3 D2 D1 D0 CFP07 CFP06 CFP05 CFP04 CFP03 CFP02 CFP01 CFP00 P07 function selection P06 function selection P05 function selection P04 function selection P03 function selection P02 function selection P01 function selection P00 function selection Function 1 1 1 1 1 1 1 1 Setting P0 I/O port data 00402D1 register (B) D7 D6 D5 D4 D3 D2 D1 D0 P07D P06D P05D P04D P03D P02D P01D P00D P07 I/O port data P06 I/O port data P05 I/O port data P04 I/O port data P03 I/O port data P02 I/O port data P01 I/O port data P00 I/O port data P0 I/O control register 00402D2 (B) D7 D6 D5 D4 D3 D2 D1 D0 IOC07 IOC06 IOC05 IOC04 IOC03 IOC02 IOC01 IOC00 P1 function select register 00402D4 (B) D7 D6 Remarks 0 0 0 0 0 0 0 0 R/W Extended functions R/W (0x402DF) R/W R/W R/W R/W R/W R/W 1 High 0 Low 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W P07 I/O control P06 I/O control P05 I/O control P04 I/O control P03 I/O control P02 I/O control P01 I/O control P00 I/O control 1 Output 0 Input 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W - CFP16 reserved P16 function selection - 0 - 0 when being read. R/W D5 CFP15 P15 function selection 0 R/W D4 CFP14 P14 function selection - 1 EXCL5 0 P16 #DMAEND1 1 EXCL4 0 P15 #DMAEND0 1 FOSC1 0 P14 0 D3 CFP13 P13 function selection 0 P13 0 D2 CFP12 P12 function selection 0 P12 0 R/W D1 CFP11 P11 function selection 0 P11 0 R/W D0 CFP10 P10 function selection 1 EXCL3 T8UF3 1 EXCL2 T8UF2 1 EXCL1 T8UF1 1 EXCL0 T8UF0 R/W Extended functions (0x402DF) R/W 0 P10 0 R/W P1 I/O port data 00402D5 register (B) D7 D6 D5 D4 D3 D2 D1 D0 - P16D P15D P14D P13D P12D P11D P10D reserved P16 I/O port data P15 I/O port data P14 I/O port data P13 I/O port data P12 I/O port data P11 I/O port data P10 I/O port data - 0 0 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W R/W R/W P1 I/O control register D7 D6 D5 D4 D3 D2 D1 D0 - IOC16 IOC15 IOC14 IOC13 IOC12 IOC11 IOC10 reserved P16 I/O control P15 I/O control P14 I/O control P13 I/O control P12 I/O control P11 I/O control P10 I/O control - 0 0 0 0 0 0 0 - R/W R/W R/W R/W R/W R/W R/W B-III-9-6 0 0 0 0 0 0 0 0 Init. R/W P07 P06 P05 P04 P03 P02 P01 P00 00402D6 (B) #SRDY1 #SCLK1 SOUT1 SIN1 #SRDY0 #SCLK0 SOUT0 SIN0 - 1 High 0 Low - 1 Output EPSON 0 Input This register indicates the values of the I/O control signals of the ports when it is read. (See detailed explanation.) 0 when being read. This register indicates the values of the I/O control signals of the ports when it is read. (See detailed explanation.) S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS A-1 Register name Address Port SIO function extension register Bit Name Function Setting 00402D7 D7-4 - D3 SSRDY3 reserved Serial I/F Ch.3 SRDY selection 1 #SRDY3 D2 SSCLK3 Serial I/F Ch.3 SCLK selection 1 #SCLK3 D1 SSOUT3 Serial I/F Ch.3 SOUT selection 1 SOUT3 D0 SSIN3 Serial I/F Ch.3 SIN selection 1 SIN3 00402D8 (B) D7 D6 D5 D4 D3 D2 D1 D0 CFP27 CFP26 CFP25 CFP24 CFP23 CFP22 CFP21 CFP20 P27 function selection P26 function selection P25 function selection P24 function selection P23 function selection P22 function selection P21 function selection P20 function selection 1 1 1 1 1 1 1 1 P2 I/O port data 00402D9 register (B) D7 D6 D5 D4 D3 D2 D1 D0 P27D P26D P25D P24D P23D P22D P21D P20D P27 I/O port data P26 I/O port data P25 I/O port data P24 I/O port data P23 I/O port data P22 I/O port data P21 I/O port data P20 I/O port data P2 I/O control register 00402DA (B) D7 D6 D5 D4 D3 D2 D1 D0 IOC27 IOC26 IOC25 IOC24 IOC23 IOC22 IOC21 IOC20 P27 I/O control P26 I/O control P25 I/O control P24 I/O control P23 I/O control P22 I/O control P21 I/O control P20 I/O control Port SIO function extension register 00402DB D7-4 D3 D2 D1 D0 - SSRDY2 SSCLK2 SSOUT2 SSIN2 reserved Serial I/F Ch.2 SRDY selection Serial I/F Ch.2 SCLK selection Serial I/F Ch.2 SOUT selection Serial I/F Ch.2 SIN selection P2 function select register P3 function 00402DC D7-6 - select register (B) D5 CFP35 D4 CFP34 D3 D2 D1 D0 CFP33 CFP32 CFP31 CFP30 reserved P35 function selection P34 function selection P33 function selection P32 function selection P31 function selection P30 function selection P3 I/O port data 00402DD D7-6 - register (B) D5 P35D D4 P34D D3 P33D D2 P32D D1 P31D D0 P30D reserved P35 I/O port data P34 I/O port data P33 I/O port data P32 I/O port data P31 I/O port data P30 I/O port data P3 I/O control register reserved P35 I/O control P34 I/O control P33 I/O control P32 I/O control P31 I/O control P30 I/O control 00402DE D7-6 - (B) D5 IOC35 D4 IOC34 D3 IOC33 D2 IOC32 D1 IOC31 D0 IOC30 S1C33L03 FUNCTION PART Init. R/W - - 0 - R/W 0 R/W 0 R/W 0 R/W P27 P26 P25 P24 P23 P22 P21 P20 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W Ext. func.(0x402DF) R/W 1 High 0 Low 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 1 Output 0 Input 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W P24/TM2 P25/TM3 P26/TM4 P27/TM5 - 0 0 0 0 - R/W R/W R/W R/W P35 P34 - 0 0 - 0 when being read. R/W R/W P33 P32 P31 P30 0 0 0 0 R/W R/W R/W Ext. func.(0x402DF) R/W - 0 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W R/W - 0 0 0 0 0 0 - R/W R/W R/W R/W R/W R/W 0 P32/ #DMAACK0 0 P15/EXCL4/ #DMAEND0 0 P16/EXCL5/ #DMAEND1 0 P33/ #DMAACK1 TM5 TM4 TM3 TM2 TM1 TM0 #DWE #DRD 0 0 0 0 0 0 0 0 - 1 1 1 1 #SRDY2 #SCLK2 SOUT2 SIN2 0 0 0 0 - 1 #BUSACK 0 1 #BUSREQ 0 #CE6 1 #DMAACK1 0 1 #DMAACK0 0 1 #BUSGET 0 1 #WAIT 0 #CE4/#CE5 - 1 High 0 Low - 1 Output EPSON Remarks 0 Input This register indicates the values of the I/O control signals of the ports when it is read. (See detailed explanation.) B-III 0 when being read. This register indicates the values of the I/O control signals of the ports when it is read. (See detailed explanation.) B-III-9-7 I/O III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS Register name Address Bit Port function extension register D7 D6 D5 D4 D3 D2 D1 CFEX7 CFEX6 CFEX5 CFEX4 CFEX3 CFEX2 CFEX1 P07 port extended function P06 port extended function P05 port extended function P04 port extended function P31 port extended function P21 port extended function P10, P11, P13 port extended function D0 CFEX0 P12, P14 port extended function 00402DF (B) Name Function Setting 1 1 1 1 1 1 1 #DMAEND3 #DMAACK3 #DMAEND2 #DMAACK2 #GARD #GAAS DST0 DST1 DPC0 1 DST2 DCLK 0 0 0 0 0 0 0 P07, etc. P06, etc. P05, etc. P04, etc. P31, etc. P21, etc. P10, etc. P11, etc. P13, etc. 0 P12, etc. P14, etc. Init. R/W 0 0 0 0 0 0 1 R/W R/W R/W R/W R/W R/W R/W 1 R/W Remarks CFP07-CFP00: P0[7:0] function selection (D[7:0]) / P0 function select register (0x402D0) CFP16-CFP10: P1[6:0] function selection (D[6:0]) / P1 function select register (0x402D4) CFP27-CFP20: P2[7:0] function selection (D[7:0]) / P2 function select register (0x402D8) CFP35-CFP30: P3[5:0] function selection (D[5:0]) / P3 function select register (0x402DC) Selects the function of each I/O port pin. Write "1": Used for peripheral circuit Write "0": I/O port pin Read: Valid When a bit of the CFP register is set to "1", the corresponding pin is set for use with peripheral circuits (see Table 9.3). The pins for which register bits are set to "0" can be used as general-purpose I/O ports. At cold start, CFP is set to "0" (I/O port). At hot start, CFP retains its state from prior to the initial reset. P07D-P00D: P0[7:0] I/O port data (D[7:0]) / P0 I/O port data register (0x402D1) P16D-P10D: P1[6:0] I/O port data (D[6:0]) / P1 I/O port data register (0x402D5) P27D-P20D: P2[7:0] I/O port data (D[7:0]) / P2 I/O port data register (0x402D9) P35D-P30D: P3[5:0] I/O port data (D[5:0]) / P3 I/O port data register (0x402DD) This register reads data from I/O-port pins or sets output data. When writing data Write "1": High level Write "0": Low level When an I/O port is set for output, the data written to it is directly output to the I/O port pin. If the data written to the port is "1", the port pin is set high (VDD and VDDE level); if the data is "0", the port pin is set low (VSS level). Even in the input mode, data can be written to the port data register. When reading data Read "1": High level Read "0": Low level The voltage level on the port pin is read out regardless of whether an I/O port is set for input or output mode. If the pin voltage is high (VDD and VDDE level), "1" is read out as input data; if the pin voltage is low (VSS level), "0" is read out as input data. At cold start, all data bits are set to "0". At hot start, they retain their state from prior to the initial reset. B-III-9-8 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS A-1 IOC07-IOC00: P0[7:0] port I/O control (D[7:0]) / P0 port I/O control register (0x402D2) IOC16-IOC10: P1[6:0] port I/O control (D[6:0]) / P1 port I/O control register (0x402D6) IOC27-IOC20: P2[7:0] port I/O control (D[7:0]) / P2 port I/O control register (0x402DA) IOC35-IOC30: P3[5:0] port I/O control (D[5:0]) / P3 port I/O control register (0x402DE) Directs an I/O port for input or output and indicates the I/O control signal value of the port. When writing data Write "1": Output mode Write "0": Input mode This I/O control register corresponds bit-for-bit to each I/O port. When an IOC bit is set to "1", the corresponding I/O port is directed for output; if it is set to "0", the I/O port is directed for input. At cold start, all IOC bits are set to "0" (input). At hot start, IOC retains its state from prior to the initial reset. If pins P10-P13, P15-P16, P30 and P34 are set for use with peripheral circuits, their pin functions vary depending on the input/output direction control by the IOC1x register. When reading data Read "1": I/O control signal (output) Read "0": I/O control signal (input) The I/O control signal value for the port pin is read from this register. When I/O port function is selected using the CFEX and CFP registers, the value written to the IOC register is read out as is. When peripheral function is selected, the read value depends on the peripheral circuit status and may not indicate the value written to the IOC register. However, the read values of the IOC bits for P10-P13, P15-P16, P30, and P34 are the same as the written value even if the peripheral function is selected. SSIN3: Serial I/F Ch.3 SIN selection (D0) / Port SIO function extension register (0x402D7) Switches the function of pin P33/#DMAACK1/SIN3. B-III Write "1": SIN3 Write "0": P33/#DMAACK1 Read: Valid To use the pin as SIN3, set SSIN3 (D0 / 0x402D7) to "1" and CFP33 (D3 / 0x402DC) to "0". To use the pin as P33 or #DMAACK1, set this bit to "0". At power-on, this bit is set to "0". SSOUT3: Serial I/F Ch.3 SOUT selection (D1) / Port SIO function extension register (0x402D7) Switches the function of pin P16/EXCL5/#DMAEND1/SOUT3. Write "1": SOUT3 Write "0": P16/EXCL5/#DMAEND1 Read: Valid I/O To use the pin as SOUT3, set SSOUT3 (D1 / 0x402D7) to "1" and CFP16 (D6 / 0x402D4) to "0". To use the pin as P16, EXCL5, or #DMAEND1, set this bit to "0". At power-on, this bit is set to "0". SSCLK3: Serial I/F Ch.3 SCLK selection (D2) / Port SIO function extension register (0x402D7) Switches the function of pin P15/EXCL4/#DMAEND0/#SCLK3. Write "1": #SCLK3 Write "0": P15/EXCL4/#DMAEND0 Read: Valid To use the pin as #SCLK3, set SSCLK3 (D2 / 0x402D7) to "1" and CFP15 (D5 / 0x402D4) to "0". To use the pin as P15, EXCL4, or #DMAEND0, set this bit to "0". At power-on, this bit is set to "0". S1C33L03 FUNCTION PART EPSON B-III-9-9 III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS SSRDY3: Serial I/F Ch.3 SRDY selection (D3) / Port SIO function extension register (0x402D7) Switches the function of pin P32/#DMAACK0/#SRDY3. Write "1": #SRDY3 Write "0": P32/#DMAACK0 Read: Valid To use the pin as #SRDY3, set SSRDY3 (D3 / 0x402D7) to "1" and CFP32 (D2 / 0x402DC) to "0". To use the pin as P32 or #DMAACK0, set this bit to "0". At power-on, this bit is set to "0". SSIN2: Serial I/F Ch.2 SIN selection (D0) / Port SIO function extension register (0x402DB) Switches the function of pin P27/TM5/SIN2. Write "1": SIN2 Write "0": P27/TM5 Read: Valid To use the pin as SIN2, set SSIN2 (D0 / 0x402DB) to "1" and CFP27 (D7 / 0x402D8) to "0". To use the pin as P27 or TM5, set this bit to "0". At power-on, this bit is set to "0". SSOUT2: Serial I/F Ch.2 SOUT selection (D1) / Port SIO function extension register (0x402DB) Switches the function of pin P26/TM4/SOUT2. Write "1": SOUT2 Write "0": P26/TM4 Read: Valid To use the pin as SOUT2, set SSOUT2 (D1 / 0x402DB) to "1" and CFP26 (D6 / 0x402D8) to "0". To use the pin as P26 or TM4, set this bit to "0". At power-on, this bit is set to "0". SSCLK2: Serial I/F Ch.2 SCLK selection (D2) / Port SIO function extension register (0x402DB) Switches the function of pin P25/TM3/#SCLK2. Write "1": #SCLK2 Write "0": P25/TM3 Read: Valid To use the pin as #SCLK2, set SSCLK2 (D2 / 0x402DB) to "1" and CFP25 (D5 / 0x402D8) to "0". To use the pin as P25 or TM3, set this bit to "0". At power-on, this bit is set to "0". SSRDY2: Serial I/F Ch.2 SRDY selection (D3) / Port SIO function extension register (0x402DB) Switches the function of pin P24/TM2/#SRDY2. Write "1": #SRDY2 Write "0": P24/TM2 Read: Valid To use the pin as #SRDY2, set SSRDY2 (D3 / 0x402DB) to "1" and CFP24 (D4 / 0x402D8) to "0". To use the pin as P24 or TM2, set this bit to "0". At power-on, this bit is set to "0". B-III-9-10 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS A-1 CFEX0: P12, P14 function extension (D0) / Port function extension register (0x402DF) CFEX1: P10, P11, P13 function extension (D1) / Port function extension register (0x402DF) CFEX2: P21 function extension (D2) / Port function extension register (0x402DF) CFEX3: P31 function extension (D3) / Port function extension register (0x402DF) CFEX4: P04 function extension (D4) / Port function extension register (0x402DF) CFEX5: P05 function extension (D5) / Port function extension register (0x402DF) CFEX6: P06 function extension (D6) / Port function extension register (0x402DF) CFEX7: P07 function extension (D7) / Port function extension register (0x402DF) Sets whether the function of an I/O-port pin is to be extended. Write "1": Function-extended pin Write "0": I/O-port/peripheral-circuit pin Read: Valid When CFEXx is set to "1", the corresponding pin is set to the extended function input/output pin. When CFEXx = "0", the corresponding CFP bit becomes effective. At cold start, CFEX0 and CFEX1 are set to "1" (function-extended pin) and other bits are set to "0" (I/Oport/peripheral-circuit pin). At hot start, CFEX retains its state from prior to the initial reset. B-III I/O S1C33L03 FUNCTION PART EPSON B-III-9-11 III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS Input Interrupt The input ports and the I/O ports support eight system of port input interrupts and two systems of key input interrupts. Port Input Interrupt The port input interrupt circuit has eight interrupt systems (FPT7-FPT0) and a port can be selected for generating each interrupt factor. The interrupt condition can also be selected from between input signal edge and input signal level. Figure 9.3 shows the configuration of the port input interrupt circuit. K67 P33 P07 P27 Interrupt request FPT7 FPT6 FPT5 FPT4 FPT3 FPT2 FPT1 FPT0 Interrupt signal generation Internal data bus Input port selection SPT7 Input polarity selection SPPT7 Address Edge/level selection SEPT7 Address FPT7 FPT6 FPT5 FPT4 FPT3 FPT2 FPT1 FPT0 Figure 9.3 Configuration of Port Input Interrupt Circuit Selecting input pins The interrupt factors allows selection of an input pin from the four predefined pins independently. Table 9.5 shows the control bits and the selectable pins for each factor. Table 9.5 Selecting Pins for Port Input Interrupts Interrupt factor FPT7 FPT6 FPT5 FPT4 FPT3 FPT2 FPT1 FPT0 B-III-9-12 Control bit 11 SPT7[1:0] (D[7:6])/Port input interrupt select register 2 (0x402C7) SPT6[1:0] (D[5:4])/Port input interrupt select register 2 (0x402C7) SPT5[1:0] (D[3:2])/Port input interrupt select register 2 (0x402C7) SPT4[1:0] (D[1:0])/Port input interrupt select register 2 (0x402C7) SPT3[1:0] (D[7:6])/Port input interrupt select register 1 (0x402C6) SPT2[1:0] (D[5:4])/Port input interrupt select register 1 (0x402C6) SPT1[1:0] (D[3:2])/Port input interrupt select register 1 (0x402C6) SPT0[1:0] (D[1:0])/Port input interrupt select register 1 (0x402C6) EPSON P27 P26 P25 P24 P23 P22 P21 P20 SPT settings 10 01 P07 P06 P05 P04 P03 P02 P01 P00 P33 P32 P31 K54 K53 K52 K51 K50 00 K67 K66 K65 K64 K63 K62 K61 K60 S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS A-1 Conditions for port input-interrupt generation Each port input interrupt can be generated by the edge or level of the input signal. The SEPTx bit of the edge/level select register (0x402C9) is used for this selection. When SEPTx is set to "1", the FPTx interrupt will be generated at the signal edge. When SEPTx is set to "0", the FPTx interrupt will be generated by the input signal level. Furthermore, the signal polarity can be selected using the SPPTx bit of the input porarity select register (0x402C8). With these registers, the port input interrupt condition is decided as shown in Table 9.6. Table 9.6 Port Input Interrupt Condition SEPTx SPPTx 1 1 0 0 1 0 1 0 FPTx interrupt condition Rising edge Falling edge High level Low level When the input signal goes to the selected status, the interrupt factor flag FP is set to "1" and, if other interrupt conditions set by the interrupt controller are met, an interrupt is generated. B-III I/O S1C33L03 FUNCTION PART EPSON B-III-9-13 III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS Key Input Interrupt The key input interrupt circuit has two interrupt systems (FPK1 and FPK0) and a port group can be selected for generating each interrupt factor. The interrupt condition can also be set by software. Figure 9.4 shows the configuration of the port input interrupt circuit. FPK0 system K50 K60 P00 P20 Input port selection SPPK0 Interrupt signal generation FPK0 Interrupt request Interrupt signal generation FPK1 Interrupt request Input comparison register SCPK0 Address Input mask register SMPK0 Internal data bus Address K50, K60, P00, P20 K51, K61, P01, P21 K52, K62, P02, P22 K53, K63, P03, P23 K54, K64, P04, P24 FPK1 system K60 K64 P04 P24 Input port selection SPPK1 Input comparison register SCPK1 Address Input mask register SMPK1 Address K60, K64, P04, P24 K61, K65, P05, P25 K62, K66, P06, P26 K63, K67, P07, P27 Figure 9.4 Configuration of Key Input Interrupt Circuit B-III-9-14 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS A-1 Selecting input pins For the FPK1 interrupt system, a four-bit input pin group can be selected from the four predefined groups. For the FPK0 system, a five-bit input pin group can be selected. Table 9.7 shows the control bits and the selectable groups for each factor. Table 9.7 Selecting Pins for Key Input Interrupts Interrupt factor FPK1 FPK0 Control bit 11 SPPK1[1:0] (D[3:2])/Key input interrupt select register (0x402CA) SPPK0[1:0] (D[1:0])/Key input interrupt select register (0x402CA) P2[7:4] P2[4:0] SPPK settings 10 01 P0[7:4] P0[4:0] K6[7:4] K6[4:0] 00 K6[3:0] K5[4:0] Conditions for key input-interrupt generation The key input interrupt circuit has two input mask registers (SMPK0[4:0] for FPK0 and SMPK1[3:0] for FPK1) and two input comparison registers (SCPK0[4:0] for FPK0 and SCPK0[3:0] for FPK1) to set inputinterrupt conditions. The input mask register SMPK is used to mask the input pin that is not used for an interrupt. This register masks each input pin, whereas the interrupt enable register of the interrupt controller masks the interrupt factor for each interrupt group. The input comparison register SCPK is used to select whether an interrupt for each input port is to be generated at the rising or falling edge of the input. A change in state occurs so that the input pin enabled for interrupt by the interrupt mask register SMPK and the content of the input comparison register SCPK become unmatched after being matched, the interrupt factor flag FK is set to "1" and, if other interrupt conditions are met, an interrupt is generated. Figure 9.5 shows cases in which a FPK0 interrupt is generated. Here, it is assumed that the K5[4:0] pins are selected for the input-pin group and the control register of the interrupt controller is set so as to enable generation of a FPK0 interrupt. B-III Intput mask register SMPK0 SMPK04 SMPK03 SMPK02 SMPK01 SMPK00 1 1 1 1 0 Input comparison register SCPK0 SCPK04 SCPK03 SCPK02 SCPK01 SCPK00 1 1 0 1 0 With the settings shown above, FPK0 interrupt is generated under the condition shown below. Input port K5 (1) K54 K53 K52 K51 K50 1 1 0 1 0 (2) K54 1 K53 1 K52 0 K51 1 K50 1 (3) K54 1 K53 0 K52 0 K51 1 K50 0 K54 K53 K52 K51 K50 1 0 1 1 0 (4) I/O (Initial value) Interrupt generation Because interrupt has been disabled for K50, interrupt will be generated when nonconformity occurs between the contents of the four bits K51-K54 and the four bits input comparison register SCPK0[4:1]. Figure 9.5 FPK0 Interrupt Generation Example (when K5[4:0] is selected by SPPK[1:0]) S1C33L03 FUNCTION PART EPSON B-III-9-15 III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS Since K50 is masked from interrupt by SMPK00, no interrupt occurs at that point (2) above. Next, because K53 becomes "0" at (3), an interrupt is generated due to the lack of a match between the data of the input pin K5[4:1] that is enabled for interrupt and that of the input comparison register SCPK0[4:1]. Since only a change in states in which the input data and the content of the input comparison register SCPK become unmatched after being matched constitutes an interrupt generation condition as described above, no interrupt is generated when a change in states from one unmatched state to another, as in (4), occurs. Consequently, if another interrupt is to be generated again following the occurrence of an interrupt, the state of the input pin must be temporarily restored to the same content as that of the input comparison register SCPK, or the input comparison register SCPK must be set again. Note that the input pins masked from interrupt by the SMPK register do not affect interrupt generation conditions. An interrupt is generated for FPK1 in the same way as described above. Control Registers of the Interrupt Controller Table 9.8 shows the control registers of the interrupt controller that are provided for each input-interrupt system. Table 9.8 Control Registers of Interrupt Controller System FPT7 FPT6 FPT5 FPT4 FPT3 FPT2 FPT1 FPT0 FPK1 FPK0 Interrupt factor flag FP7(D5/0x40287) FP6(D4/0x40287) FP5(D3/0x40287) FP4(D2/0x40287) FP3(D3/0x40280) FP2(D2/0x40280) FP1(D1/0x40280) FP0(D0/0x40280) FK1(D5/0x40280) FK0(D4/0x40280) Interrupt enable register EP7(D5/0x40277) EP6(D4/0x40277) EP5(D3/0x40277) EP4(D2/0x40277) EP3(D3/0x40270) EP2(D2/0x40270) EP1(D1/0x40270) EP0(D0/0x40270) EK1(D5/0x40270) EK0(D4/0x40270) Interrupt priority register PP7L[2:0](D[6:4]/0x4026D) PP6L[2:0](D[2:0]/0x4026D) PP5L[2:0](D[6:4]/0x4026C) PP4L[2:0](D[2:0]/0x4026C) PP3L[2:0](D[6:4]/0x40261) PP2L[2:0](D[2:0]/0x40261) PP1L[2:0](D[6:4]/0x40260) PP0L[2:0](D[2:0]/0x40260) PK1L[2:0](D[6:4]/0x40262) PK0L[2:0](D[2:0]/0x40262) When the interrupt generation condition described above is met, the corresponding interrupt factor flag is set to "1". If the interrupt enable register bit for that interrupt factor has been set to "1", an interrupt request is generated. Interrupts due to an interrupt factor can be disabled by leaving the interrupt enable register bit for that factor set to "0". The interrupt factor flag is set to "1" whenever interrupt generation conditions are met, regardless of the setting of the interrupt enable register. The interrupt priority register sets the interrupt priority level (0 to 7) for each interrupt system. An interrupt request to the CPU is accepted only when no other interrupt request of a higher priority has been generated. In addition, only when the PSR's IE bit = "1" (interrupts enabled) and the set value of the IL is smaller than the input interrupt level set using the interrupt priority register will the input interrupt request actually be accepted by the CPU. For details on these interrupt control registers, as well as the device operation when an interrupt has occurred, refer to "ITC (Interrupt Controller)". Intelligent DMA The port input interrupt system can invoke an intelligent DMA (IDMA) through the use of its interrupt factor. This enables the port inputs to be used as a trigger to perform DMA transfer. The following shows the IDMA channel numbers assigned to each interrupt factor: IDMA Ch. IDMA Ch. FPT0 input interrupt: 1 FPT4 input interrupt: 28 FPT1 input interrupt: 2 FPT5 input interrupt: 29 FPT2 input interrupt: 3 FPT6 input interrupt: 30 FPT3 input interrupt: 4 FPT7 input interrupt: 31 For IDMA to be invoked, the IDMA request and IDMA enable bits shown in Table 9.9 must be set to "1" in advance. Transfer conditions, etc. must also be set on the IDMA side in advance. B-III-9-16 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS A-1 Table 9.9 Control Bits for IDMA Transfer System IDMA request bit IDMA enable bit FPT7 FPT6 FPT5 FPT4 FPT3 FPT2 FPT1 FPT0 RP7(D7/0x40293) RP6(D6/0x40293) RP5(D5/0x40293) RP4(D4/0x40293) RP3(D3/0x40290) RP2(D2/0x40290) RP1(D1/0x40290) RP0(D0/0x40290) DEP7(D7/0x40297) DEP6(D6/0x40297) DEP5(D5/0x40297) DEP4(D4/0x40297) DEP3(D3/0x40294) DEP2(D2/0x40294) DEP1(D1/0x40294) DEP0(D0/0x40294) If the IDMA request and enable bits are set to "1", IDMA is invoked through generation of an interrupt factor. No interrupt request is generated at that point. An interrupt request is generated after the DMA transfer is completed. The registers can also be set so as not to generate an interrupt, with only DMA transfers performed. For details on IDMA transfers and interrupt control upon completion of IDMA transfer, refer to "IDMA (Intelligent DMA)". Trap vectors The trap-vector address of each input default interrupt factor is set as follows: FPT0 input interrupt: FPT1 input interrupt: FPT2 input interrupt: FPT3 input interrupt: FPK0 input interrupt: FPK1 input interrupt: FPT4 input interrupt: FPT5 input interrupt: FPT6 input interrupt: FPT7 input interrupt: 0x0C00040 0x0C00044 0x0C00048 0x0C0004C 0x0C00050 0x0C00054 0x0C00110 0x0C00114 0x0C00118 0x0C0011C B-III The base address of the trap table can be changed using the TTBR register (0x48134 to 0x48137). I/O S1C33L03 FUNCTION PART EPSON B-III-9-17 III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS I/O Memory for Input Interrupts Table 9.10 shows the control bits for the port input and key input interrupts. Table 9.10 Control Bits for Input Interrupts Register name Address Bit Port input 0/1 0040260 interrupt (B) priority register D7 D6 D5 D4 D3 D2 D1 D0 - PP1L2 PP1L1 PP1L0 - PP0L2 PP0L1 PP0L0 reserved Port input 1 interrupt level - 0 to 7 reserved Port input 0 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - PP3L2 PP3L1 PP3L0 - PP2L2 PP2L1 PP2L0 reserved Port input 3 interrupt level - 0 to 7 reserved Port input 2 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - PK1L2 PK1L1 PK1L0 - PK0L2 PK0L1 PK0L0 reserved Key input 1 interrupt level - 0 to 7 reserved Key input 0 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - PP5L2 PP5L1 PP5L0 - PP4L2 PP4L1 PP4L0 reserved Port input 5 interrupt level - 0 to 7 reserved Port input 4 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - PP7L2 PP7L1 PP7L0 - PP6L2 PP6L1 PP6L0 reserved Port input 7 interrupt level - 0 to 7 reserved Port input 6 interrupt level - 0 to 7 Port input 2/3 0040261 interrupt (B) priority register Key input 0040262 interrupt (B) priority register Port input 4/5 004026C interrupt (B) priority register Port input 6/7 004026D interrupt (B) priority register Name Function Key input, 0040270 port input 0-3 (B) interrupt enable register D7-6 D5 D4 D3 D2 D1 D0 - EK1 EK0 EP3 EP2 EP1 EP0 reserved Key input 1 Key input 0 Port input 3 Port input 2 Port input 1 Port input 0 Port input 4-7, 0040277 clock timer, (B) A/D interrupt enable register D7-6 D5 D4 D3 D2 D1 D0 - EP7 EP6 EP5 EP4 ECTM EADE reserved Port input 7 Port input 6 Port input 5 Port input 4 Clock timer A/D converter Key input, 0040280 port input 0-3 (B) interrupt factor flag register D7-6 D5 D4 D3 D2 D1 D0 - FK1 FK0 FP3 FP2 FP1 FP0 reserved Key input 1 Key input 0 Port input 3 Port input 2 Port input 1 Port input 0 B-III-9-18 Setting - 1 Enabled 0 Disabled - 1 Enabled 0 Disabled - 1 Factor is generated EPSON 0 No factor is generated Init. R/W Remarks - X X X - X X X - 0 when being read. R/W - X X X - X X X - 0 when being read. R/W - X X X - X X X - 0 when being read. R/W - X X X - X X X - 0 when being read. R/W - X X X - X X X - 0 when being read. R/W - 0 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W R/W - 0 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W R/W - X X X X X X - 0 when being read. R/W R/W R/W R/W R/W R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS A-1 Register name Address Bit Port input 4-7, 0040287 clock timer, A/D (B) interrupt factor flag register D7-6 D5 D4 D3 D2 D1 D0 Name Function - FP7 FP6 FP5 FP4 FCTM FADE reserved Port input 7 Port input 6 Port input 5 Port input 4 Clock timer A/D converter Setting Init. R/W - 1 Factor is generated 0 No factor is generated Remarks - X X X X X X - 0 when being read. R/W R/W R/W R/W R/W R/W Port input 0-3, high-speed DMA Ch. 0/1, 16-bit timer 0 IDMA request register 0040290 (B) D7 D6 D5 D4 D3 D2 D1 D0 R16TC0 R16TU0 RHDM1 RHDM0 RP3 RP2 RP1 RP0 16-bit timer 0 comparison A 16-bit timer 0 comparison B High-speed DMA Ch.1 High-speed DMA Ch.0 Port input 3 Port input 2 Port input 1 Port input 0 1 IDMA request 0 Interrupt request 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Serial I/F Ch.1, A/D, port input 4-7 IDMA request register 0040293 (B) D7 D6 D5 D4 D3 D2 D1 D0 RP7 RP6 RP5 RP4 - RADE RSTX1 RSRX1 Port input 7 Port input 6 Port input 5 Port input 4 reserved A/D converter SIF Ch.1 transmit buffer empty SIF Ch.1 receive buffer full 1 IDMA request 0 Interrupt request 1 IDMA request 0 Interrupt request 0 0 0 0 - 0 0 0 R/W R/W R/W R/W - 0 when being read. R/W R/W R/W - Port input 0-3, high-speed DMA Ch. 0/1, 16-bit timer 0 IDMA enable register 0040294 (B) D7 D6 D5 D4 D3 D2 D1 D0 DE16TC0 DE16TU0 DEHDM1 DEHDM0 DEP3 DEP2 DEP1 DEP0 16-bit timer 0 comparison A 16-bit timer 0 comparison B High-speed DMA Ch.1 High-speed DMA Ch.0 Port input 3 Port input 2 Port input 1 Port input 0 1 IDMA enabled 0 IDMA disabled 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Serial I/F Ch.1, A/D, port input 4-7 IDMA enable register 0040297 (B) D7 D6 D5 D4 D3 D2 D1 D0 DEP7 DEP6 DEP5 DEP4 - DEADE DESTX1 DESRX1 Port input 7 Port input 6 Port input 5 Port input 4 reserved A/D converter SIF Ch.1 transmit buffer empty SIF Ch.1 receive buffer full 1 IDMA enabled 0 IDMA disabled 0 0 0 0 - 0 0 0 R/W R/W R/W R/W - 0 when being read. R/W R/W R/W D7 D6 D5 D4 D3 D2 D1 D0 SPT31 SPT30 SPT21 SPT20 SPT11 SPT10 SPT01 SPT00 FPT3 interrupt input port selection D7 D6 D5 D4 D3 D2 D1 D0 SPT71 SPT70 SPT61 SPT60 SPT51 SPT50 SPT41 SPT40 FPT7 interrupt input port selection Port input 00402C6 interrupt select (B) register 1 Port input 00402C7 interrupt select (B) register 2 FPT2 interrupt input port selection FPT1 interrupt input port selection FPT0 interrupt input port selection FPT6 interrupt input port selection FPT5 interrupt input port selection FPT4 interrupt input port selection - 1 IDMA enabled 11 P23 11 P22 11 P21 11 P20 10 P03 10 P02 10 P01 10 P00 01 K53 01 K52 01 K51 01 K50 00 K63 00 K62 00 K61 00 K60 0 0 0 0 0 0 0 0 R/W 11 P27 11 P26 11 P25 11 P24 10 P07 10 P06 10 P05 10 P04 01 P33 01 P32 01 P31 01 K54 00 K67 00 K66 00 K65 00 K64 0 0 0 0 0 0 0 0 R/W Low level or Falling edge 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Port input interrupt input polarity select register 00402C8 (B) D7 D6 D5 D4 D3 D2 D1 D0 SPPT7 SPPT6 SPPT5 SPPT4 SPPT3 SPPT2 SPPT1 SPPT0 FPT7 input polarity selection FPT6 input polarity selection FPT5 input polarity selection FPT4 input polarity selection FPT3 input polarity selection FPT2 input polarity selection FPT1 input polarity selection FPT0 input polarity selection 1 Port input interrupt edge/level select register 00402C9 (B) D7 D6 D5 D4 D3 D2 D1 D0 SEPT7 SEPT6 SEPT5 SEPT4 SEPT3 SEPT2 SEPT1 SEPT0 FPT7 edge/level selection FPT6 edge/level selection FPT5 edge/level selection FPT4 edge/level selection FPT3 edge/level selection FPT2 edge/level selection FPT1 edge/level selection FPT0 edge/level selection 1 Edge S1C33L03 FUNCTION PART EPSON 0 IDMA disabled High level 0 or Rising edge 0 Level B-III R/W R/W R/W I/O R/W R/W R/W B-III-9-19 III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS Function Setting Key input 00402CA D7-4 - interrupt select (B) D3 SPPK11 register D2 SPPK10 D1 SPPK01 D0 SPPK00 Register name Address Bit Name reserved FPK1 interrupt input port selection - Key input interrupt (FPK0) input comparison register Init. R/W Remarks 11 10 01 00 P2[7:4] P0[7:4] K6[7:4] K6[3:0] FPK0 interrupt input port selection 11 10 01 00 P2[4:0] P0[4:0] K6[4:0] K5[4:0] - 0 0 0 0 - 0 when being read. R/W 00402CC D7-5 - (B) D4 SCPK04 D3 SCPK03 D2 SCPK02 D1 SCPK01 D0 SCPK00 reserved FPK04 input comparison FPK03 input comparison FPK02 input comparison FPK01 input comparison FPK00 input comparison - 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W Key input interrupt (FPK1) input comparison register 00402CD D7-4 - (B) D3 SCPK13 D2 SCPK12 D1 SCPK11 D0 SCPK10 reserved FPK13 input comparison FPK12 input comparison FPK11 input comparison FPK10 input comparison - 0 0 0 0 - 0 when being read. R/W R/W R/W R/W Key input interrupt (FPK0) input mask register 00402CE D7-5 - (B) D4 SMPK04 D3 SMPK03 D2 SMPK02 D1 SMPK01 D0 SMPK00 reserved FPK04 input mask FPK03 input mask FPK02 input mask FPK01 input mask FPK00 input mask - 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W Key input interrupt (FPK1) input mask register 00402CF D7-4 - (B) D3 SMPK13 D2 SMPK12 D1 SMPK11 D0 SMPK10 reserved FPK13 input mask FPK12 input mask FPK11 input mask FPK10 input mask - 0 0 0 0 - 0 when being read. R/W R/W R/W R/W - 1 High 0 Low - 1 High 0 Low - 1 Interrupt enabled 0 Interrupt disabled - 1 Interrupt enabled SPT71-SPT70: FPT7 interrupt input port selection (D[7:6]) SPT61-SPT60: FPT6 interrupt input port selection (D[5:4]) SPT51-SPT50: FPT5 interrupt input port selection (D[3:2]) SPT41-SPT40: FPT4 interrupt input port selection (D[1:0]) SPT31-SPT30: FPT3 interrupt input port selection (D[7:6]) SPT21-SPT20: FPT2 interrupt input port selection (D[5:4]) SPT11-SPT10: FPT1 interrupt input port selection (D[3:2]) SPT01-SPT00: FPT0 interrupt input port selection (D[1:0]) Select an input pin for port interrupt generation. / Port input / Port input / Port input / Port input / Port input / Port input / Port input / Port input 0 Interrupt disabled interrupt interrupt interrupt interrupt interrupt interrupt interrupt interrupt R/W select register select register select register select register select register select register select register select register 2 (0x402C7) 2 (0x402C7) 2 (0x402C7) 2 (0x402C7) 1 (0x402C6) 1 (0x402C6) 1 (0x402C6) 1 (0x402C6) Table 9.11 Selecting Pins for Port Input Interrupts Interrupt system 11 FPT7 FPT6 FPT5 FPT4 FPT3 FPT2 FPT1 FPT0 P27 P26 P25 P24 P23 P22 P21 P20 SPT settings 10 01 P07 P06 P05 P04 P03 P02 P01 P00 P33 P32 P31 K54 K53 K52 K51 K50 00 K67 K66 K65 K64 K63 K62 K61 K60 At cold start, SPT is set to "00". At hot start, SPT retains its state from prior to the initial reset. B-III-9-20 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS A-1 SPPT7-SPPT0: Input polarity selection (D[7:0]) / Port interrupt input polarity select register (0x402C8) Selects input signal porarity for port interrupt generation. Write "1": High level or Rising edge Write "0": Low level or Falling edge Read: Valid SPPTx is the input polarity select bit corresponding to the FPTx interrupt. When SPPTx is set to "1", the FPTx interrupt will be generated by a high level input or at the rising edge. When SPPTx is set to "0", the interrupt will be generated by a low level input or at the falling edge. An edge or a level interrupt is selected by the SEPTx bit. At cold start, SPPT is set to "0" (low level). At hot start, SPPT retains its state from prior to the initial reset. SEPT7-SEPT0: Edge/level selection (D[7:0]) / Port interrupt edge/level select register (0x402C9) Selects an edge trigger or a level trigger for port interrupt generation. Write "1": Edge Write "0": Level Read: Valid SEPTx is the edge/level select bit corresponding to the FPTx interrupt. When SEPTx is set to "1", the FPTx interrupt will be generated at the signal edge. Either falling edge or rising edge can be selected by the SPPTx bit. When SEPTx is set to "0", the interrupt will be generated by the level (high or low) specified with the SPPTx bit. At cold start, SEPT is set to "0" (level). At hot start, SEPT retains its state from prior to the initial reset. SPPK11-SPPK10: FPK1 interrupt input port selection (D[3:2]) / Key input interrupt select register (0x402CA) SPPK01-SPPK00: FPK0 interrupt input port selection (D[1:0]) / Key input interrupt select register (0x402CA) Select an input-pin group for key interrupt generation. Table 9.12 Selecting Pins for Key Input Interrupts Interrupt system 11 FPK1 FPK0 P2[7:4] P2[4:0] SPPK settings 10 01 P0[7:4] P0[4:0] K6[7:4] K6[4:0] B-III 00 K6[3:0] K5[4:0] At cold start, SPPK is set to "00". At hot start, SPPK retains its state from prior to the initial reset. SCPK13-SCPK10: FPK1 input comparison (D[3:0]) / FPK1 input comparison register (0x402CD) SCPK04-SCPK00: FPK0 input comparison (D[4:0]) / FPK0 input comparison register (0x402CC) Sets the conditions for key-input interrupt generation (timing of interrupt generation). Write "1": Generated at falling edge Write "0": Generated at rising edge Read: Valid I/O SCPK0[4:0] is compared with the input state of five bits of the FPK0 input ports, and SCPK1[3:0] is compared with the input state of four bits of the FPK1 input ports, and when a change in states from a matched to an unmatched state occurs in either, an interrupt is generated (except for the inputs disabled from interrupt by the SMPK register). At cold start, SCPK is set to "0" (rising edge). At hot start, SCPK retains its state from prior to the initial reset. S1C33L03 FUNCTION PART EPSON B-III-9-21 III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS SMPK13-SMPK10: FPK1 input mask (D[3:0]) / FPK1 input mask register (0x402CF) SMPK04-SMPK00: FPK0 input mask (D[4:0]) / FPK0 input mask register (0x402CE) Sets conditions for key-input interrupt generation (interrupt enabled/disabled). Write "1": Interrupt enabled Write "0": Interrupt disabled Read: Valid SMPK is an input mask register for each key-input interrupt system. Interrupts for bits set to "1" are enabled, and interrupts for bits set to "0" are disabled. A change in the state of an input pin that is disabled from interrupt does not affect interrupt generation. At cold start, SMPK is set to "0" (interrupt disabled). At hot start, SMPK retains its state from prior to the initial reset. PP0L2-PP0L0: Port input 0 interrupt level (D[2:0]) / Port input 0/1 interrupt priority register (0x40260) PP1L2-PP1L0: Port input 1 interrupt level (D[6:4]) / Port input 0/1 interrupt priority register (0x40260) PP2L2-PP2L0: Port input 2 interrupt level (D[2:0]) / Port input 2/3 interrupt priority register (0x40261) PP3L2-PP3L0: Port input 3 interrupt level (D[6:4]) / Port input 2/3 interrupt priority register (0x40261) PP4L2-PP4L0: Port input 4 interrupt level (D[2:0]) / Port input 4/5 interrupt priority register (0x4026C) PP5L2-PP5L0: Port input 5 interrupt level (D[6:4]) / Port input 4/5 interrupt priority register (0x4026C) PP6L2-PP6L0: Port input 6 interrupt level (D[2:0]) / Port input 6/7 interrupt priority register (0x4026D) PP7L2-PP7L0: Port input 7 interrupt level (D[6:4]) / Port input 6/7 interrupt priority register (0x4026D) PK0L2-PK0L0: Key input 0 interrupt level (D[2:0]) / Key input interrupt priority register (0x40262) PK1L2-PK1L0: Key input 1 interrupt level (D[6:4]) / Key input interrupt priority register (0x40262) Sets the priority level of the input interrupt. PPxL and PKxL are interrupt priority registers corresponding to each port-input interrupt and key-input interrupt, respectively. The priority level can be set for each interrupt group in the range of 0 to 7. At initial reset, these registers becomes indeterminate. EP3-EP0: Port input 3-0 interrupt enable (D[3:0]) / Key input, port input 0-3 interrupt enable register (0x40270) EP7-EP4: Port input 7-4 interrupt enable (D[5:2]) / Port input 4-7, clock timer, A/D interrupt enable register (0x40277) EK1, EK0: Key input 1, 0 interrupt enable (D[5:4]) / Key input, port input 0-3 interrupt enable register (0x40270) Enables or disables the generation of an interrupt to the CPU. Write "1": Interrupt enabled Write "0": Interrupt disabled Read: Valid EP and EK are interrupt enable bits corresponding to the port-input interrupt and the key-input interrupt, respectively. Interrupts for input systems set to "1" are enabled, and interrupts for input systems set to "0" are disabled. At initial reset, these bits are set to "0" (interrupt disabled). B-III-9-22 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS A-1 FP3-FP0: Port input 3-0 interrupt factor flag (D[3:0]) / Key input, port input 0-3 interrupt factor flag register (0x40280) FP7-FP4: Port input 7-4 interrupt factor flag (D[5:2]) / Port input 4-7, clock timer, A/D interrupt factor flag register (0x40287) FK1, FK0: Key input 1, 0 interrupt factor flag (D[5:4]) / Key input, port input 0-3 interrupt factor flag register (0x40280) Indicates the status of an input interrupt factor generated. When read Read "1": Interrupt factor has occurred Read "0": No interrupt factor has occurred When written using the reset-only method (default) Write "1": Interrupt factor flag is reset Write "0": Invalid When written using the read/write method Write "1": Interrupt flag is set Write "0": Interrupt flag is reset FP and FK are an interrupt factor flags corresponding to the port-input interrupt and the key-input interrupt, respectively. The flag is set to "1" when interrupt generation conditions are met. At this time, if the following conditions are met, an interrupt to the CPU is generated: 1. The corresponding interrupt enable register bit is set to "1". 2. No other interrupt request of a higher priority has been generated. 3. The IE bit of the PSR is set to "1" (interrupts enabled). 4. The value set in the corresponding interrupt priority register is higher than the interrupt level (IL) of the CPU. When using the interrupt factor of the port-input to request IDMA, note that even when the above conditions are met, no interrupt request to the CPU is generated for the interrupt factor that has occurred. If interrupts are enabled at the setting of IDMA, an interrupt is generated under the above conditions after the data transfer by IDMA is completed. The interrupt factor flag is set to "1" whenever interrupt generation conditions are met, regardless of how the interrupt enable and interrupt priority registers are set. If the next interrupt is to be accepted after an interrupt has occurred, it is necessary that the interrupt factor flag be reset, and that the PSR be set again (by setting the IE bit to "1" after setting the IL to a value lower than the level indicated by the interrupt priority register, or by executing the reti instruction). The interrupt factor flag can be reset only by writing to it in the software. Note that if the PSR is set again to accept interrupts generated (or if the reti instruction is executed) without resetting the interrupt factor flag, the same interrupt occurs again. Note also that the value to be written to reset the flag is "1" when the reset-only method (RSTONLY = "1") is used, and "0" when the read/write method (RSTONLY = "0") is used. At initial reset, all the flags become indeterminate, so be sure to reset them in the software. S1C33L03 FUNCTION PART EPSON B-III-9-23 B-III I/O III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS RP3-RP0: Port input 3-0 IDMA request (D[3:0]) / Port input 0-3, high-speed DMA, 16-bit timer 0 IDMA request register (0x40290) RP7-RP4: Port input 7-4 IDMA request (D[7:4]) / Serial I/F Ch.1, A/D, Port input 4-7 IDMA request register (0x40293) Specifies whether to invoke IDMA when an interrupt factor occurs. When using the set-only method (default) Write "1": IDMA request Write "0": Not changed Read: Valid When using the read/write method Write "1": IDMA request Write "0": Interrupt request Read: Valid RP7 to RP0 are IDMA request bits corresponding to the port-input 7 to 0 interrupts, respectively. If the bit is set to "1", IDMA is invoked when an interrupt factor occurs, thereby performing a programmed data transfer. If the bit is set to "0", normal interrupt processing is performed, without invoking IDMA. For details on IDMA, refer to "IDMA (Intelligent DMA)". At initial reset, RP is set to "0" (interrupt request). DEP3-DEP0: Port input 3-0 IDMA enable (D[3:0]) / Port input 0-3, high-speed DMA, 16-bit timer 0 IDMA enable register (0x40294) DEP7-DEP4: Port input 7-4 IDMA enable (D[7:4]) / Serial I/F Ch.1, A/D, Port input 4-7 IDMA enable register (0x40297) Enables IDMA transfer by means of an interrupt factor. When using the set-only method (default) Write "1": IDMA enabled Write "0": Not changed Read: Valid When using the read/write method Write "1": IDMA enabled Write "0": IDMA disabled Read: Valid If DEP is set to "1", the IDMA request by the interrupt factor is enabled. If the register bit is set to "0", the IDMA request is disabled. After an initial reset, DEP is set to "0" (IDMA disabled). B-III-9-24 EPSON S1C33L03 FUNCTION PART III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS A-1 Programming Notes (1) After an initial reset, the interrupt factor flags become indeterminate. To prevent generation of an unwanted interrupt or IDMA request, be sure to reset the flags in a program. (2) To prevent regeneration of interrupts due to the same factor following the occurrence of an interrupt, always be sure to reset the interrupt factor flag before resetting the PSR or executing the reti instruction. (3) The input/output ports operate only when the prescaler is operating. (4) When restarting from the SLEEP or HALT2 state, interrupt input from a port can be used as a trigger, but functionally, this interrupt input operates as level input. Therefore, a level input based restart is performed even in the case of set edge input. Restart operation is as follows for rising and falling edges. In case of rising edge interrupt setting: Restarted by high level input. In case of falling edge interrupt setting: Restarted by low level input. In normal operation, a restart begins following the elapse of a given time after execution of the SLP instruction, but when restart by a falling (rising) level (edge) is set, the operation is as follows. * The restart is effected immediately after execution of the SLP instruction. * As ports are already at the low level when the SLP instruction is executed, there is no falling (rising) edge, and therefore the SLEEP state is entered only momentarily, and the restart is effected immediately afterwards. There was a synchronization circuit using a clock signal in the port input circuit, and as the clock is stopped in the SLEEP state and the clock can be stopped in the HALT2 state, the configuration provided for this synchronization circuit to be bypassed when restarting. Therefore, a restart is effected when the input level from a port is active by level. Consequently, the system design should assume that a restart by means of port input from the SLEEP state or HALT2 state is performed by level. B-III I/O S1C33L03 FUNCTION PART EPSON B-III-9-25 III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS THIS PAGE IS BLANK. B-III-9-26 EPSON S1C33L03 FUNCTION PART S1C33L03 FUNCTION PART IV ANALOG BLOCK IV ANALOG BLOCK: INTRODUCTION A-1 IV-1 INTRODUCTION The analog block consists of an A/D converter with 8 input channels. C33 DMA Block C33 SDRAM Controller Block C33 LCD Controller Block C33_DMA C33_SDRAMC C33_LCDC (IDMA, HSDMA) (SDRAM interface) (LCD panel interface) Pads Internal RAM (Area 0) CORE_PAD C33 Internal Memory Block C33_CORE (CPU, BCU, ITC, CLG, DBG) Internal ROM (Area 10) Pads C33_SBUS C33_ADC C33_PERI (A/D converter) (Prescaler, 8-bit timer, 16-bit timer, Clock timer, Serial interface, Ports) C33 Analog Block PERI_PAD C33 Core Block Pads C33 Peripheral Block Figure 1.1 Analog Block Note: Internal ROM is not provided in the S1C33L03. B-IV Intro S1C33L03 FUNCTION PART EPSON B-IV-1-1 IV ANALOG BLOCK: INTRODUCTION THIS PAGE IS BLANK. B-IV-1-2 EPSON S1C33L03 FUNCTION PART IV ANALOG BLOCK: A/D CONVERTER A-1 IV-2 A/D CONVERTER Features and Structure of A/D Converter The Analog Block contains an A/D converter with the following features: * Conversion method: Successive comparison * Resolution: 10 bits * Input channels: Maximum of 8 * Conversion time: Maximum of 10 s (when a 2-MHz input clock is selected) * Conversion range: Between VSS and AVDDE * Two conversion modes can be selected: Normal mode: Conversion is completed in one operation. Continuous mode: Conversion is continuous and terminated through software control. Continuous conversion of multiple channels can be performed in each mode. * Four types of A/D-conversion start triggers can be selected: Triggered by the external pin (#ADTRG) Triggered by the compare match B of the 16-bit programmable timer 0 Triggered by the underflow of the 8-bit programmable timer 0 Triggered by the software * A/D conversion results can be read out from a 10-bit data register. * An interrupt is generated upon completion of A/D conversion. Figure 2.1 shows the structure of the A/D converter. AVDDE VSS Control registers AD0 AD1 Analog input decoder Analog block Successive approximation block Data register Internal data bus AD2 AD3 AD4 AD5 Control circuit AD6 AD7 #ADTRG 8-bit timer 0 16-bit timer 0 Interrupt control circuit B-IV Clock generator Prescaler Interrupt request Figure 2.1 Structure of A/D Converter S1C33L03 FUNCTION PART EPSON B-IV-2-1 A/D IV ANALOG BLOCK: A/D CONVERTER I/O Pins of A/D Converter Table 2.1 shows the pins used by the A/D converter. Table 2.1 I/O Pins of A/D Converter Pin name K52/#ADTRG K60/AD0 K61/AD1 K62/AD2 K63/AD3 K64/AD4 K65/AD5 K66/AD6 K67/AD7 AVDDE I/O I I I I I I I I I - Function Function select bit Input port / AD trigger Input port / AD converter input 0 Input port / AD converter input 1 Input port / AD converter input 2 Input port / AD converter input 3 Input port / AD converter input 4 Input port / AD converter input 5 Input port / AD converter input 6 Input port / AD converter input 7 Analog reference voltage (+) CFK52(D2)/K5 function select register(0x402C0) CFK60(D0)/K6 function select register(0x402C3) CFK61(D1)/K6 function select register(0x402C3) CFK62(D2)/K6 function select register(0x402C3) CFK63(D3)/K6 function select register(0x402C3) CFK64(D4)/K6 function select register(0x402C3) CFK65(D5)/K6 function select register(0x402C3) CFK66(D6)/K6 function select register(0x402C3) CFK67(D7)/K6 function select register(0x402C3) - AVDDE (analog power-supply pin) AVDDE is the power-supply pin for the analog circuit. The voltage level supplied to this pin must be AVDDE = VDDE. Note: When the A/D converter is set to enabled state, a current flows between AVDDE and VSS, and power is consumed, even when A/D operations are not performed. Therefore, when the A/D converter is not used, it must be set to the disabled state (default "0" setting of ADE (D2) in the A/D enable register (0x40244)). AD[7:0] (analog-signal input pins) The analog input pins AD7 (Ch.7) through AD0 (Ch.0) are shared with input port pins K67 through K60. Therefore, when these pins are used for analog input, they must be set for use with the A/D converter in the software. This setting can be made individually for each pin. At cold start, all these pins are set for input ports. The analog input voltage AVIN can be input in the range of VSS AVIN AVDDE. #ADTRG (external-trigger input pin) This pin is used to input a trigger signal to start A/D conversion from an external source. Since this pin is shared with input port K52, it must be set for use with the A/D converter in the software before an external trigger can be applied to the pin. At cold start, this pin is set for an input port. Method for setting A/D-converter input pins At cold start, the #ADTRG and AD[7:0] pins all are set for input ports Kxx (function select bit CFKxx = "0"). When using these pins for the A/D converter, write "1" to the function select bit CFKxx. At hot start, these pins retain their state from prior to the reset. B-IV-2-2 EPSON S1C33L03 FUNCTION PART IV ANALOG BLOCK: A/D CONVERTER A-1 Setting A/D Converter When the A/D converter is used, the following settings must be made before an A/D conversion can be performed: 1. Setting analog input pins 2. Setting the input clock 3. Selecting the analog-conversion start and end channels 4. Setting the A/D conversion mode 5. Selecting a trigger 6. Setting the sampling time 7. Setting interrupt/IDMA/HSDMA The following describes how to set each item. For details on how to set the analog input pins, refer to the preceding section. For details on how to set interrupt/DMA, refer to "A/D Converter Interrupt and DMA". Note: Before making these settings, make sure the A/D converter is disabled (ADE (D2) / A/D enable register (0x40244) = "0"). Changing the settings while the A/D converter is enabled could cause a malfunction. Setting the input clock As explained in "Prescaler", the A/D conversion clock can be selected from among the eight types shown in Table 2.2 below. Use PSAD[2:0] (D[2:0]) / A/D clock control register (0x4014F) for this selection. Table 2.2 Input Clock Selection PSAD2 PSAD1 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 PSAD0 Division ratio 1 fPSCIN/256 0 fPSCIN/128 1 fPSCIN/64 0 fPSCIN/32 1 fPSCIN/16 0 fPSCIN/8 1 fPSCIN/4 0 fPSCIN/2 fPSCIN: Prescaler input clock frequency The selected clock is output from the prescaler to the A/D converter by writing "1" to PSONAD (D3) / A/D clock control register (0x4014F). Notes: * The A/D converter operates only when the prescaler is operating. * The recommended input clock frequency is a maximum of 2 MHz. * Do not start an A/D conversion when the clock output from the prescaler to the A/D converter is turned off, and do not turn off the prescaler's clock output when an A/D conversion is underway. This could cause the A/D converter to operate erratically. B-IV Selecting analog-conversion start and end channels Select the channel in which the A/D conversion is to be performed from among the pins (channels) that have been set for analog input. To enable A/D conversions in multiple channels to be performed successively through one convert operation, specify the conversion start and conversion end channels. Conversion start channel: CS[2:0] (D[2:0]) / A/D channel register (0x40243) Conversion end channel: CE[2:0] (D[5:3]) / A/D channel register (0x40243) S1C33L03 FUNCTION PART EPSON B-IV-2-3 A/D IV ANALOG BLOCK: A/D CONVERTER Table 2.3 Relationship between CS/CE and Input Channel CS2/CE2 CS1/CE1 CS0/CE0 Channel selected 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Example: Operation of one A/D conversion CS[2:0] = "0", CE[2:0] = "0": Converted only in AD0 CS[2:0] = "0", CE[2:0] = "3": Converted in the following order: AD0AD1AD2AD3 CS[2:0] = "5", CE[2:0] = "1": Converted in the following order: AD5AD6AD7AD0AD1 Note: Only conversion-channel input pins that have been set for use with the A/D converter can be set using the CS and CE bits. Setting the A/D conversion mode The A/D converter can operate in one of the following two modes. This operation mode is selected using MS (D5) / A/D trigger register (0x40242). 1. Normal mode (MS = "0") All inputs in the range of channels set using the CS and CE bits are A/D converted once and then stopped. 2. Continuous mode (MS = "1") A/D conversions in the range of channels set using the CS and CE bits are executed successively until stopped by the software. At initial reset, the normal mode is selected. Selecting a trigger Use TS[1:0] (D[4:3]) / A/D trigger register (0x40242) to select a trigger to start A/D conversion from among the four types shown in Table 2.4. Table 2.4 Trigger Selection TS1 TS0 1 1 0 0 1 0 1 0 Trigger External trigger (K52/#ADTRG) 8-bit programmable timer 0 16-bit programmable timer 0 Software 1. External trigger The signal input to the #ADTRG pin is used as a trigger. When this trigger is used, the K52 pin must be set for #ADTRG in advance by writing "1" to CFK52 (D2) / K5 function select register (0x402C0). A/D conversion is started at a falling edge of the #ADTRG signal. 2. Programmable timer The underflow signal of 8-bit programmable timer 0 or the comarison match B signal of the 16-bit programmable timer 0 is used as a trigger. Since the cycle can be programmed using each timer, this trigger is effective when cyclic A/D conversions are required. For details on how to set a timer, refer to the explanation of each programmable timer in this manual. 3. Software trigger Writing "1" to ADST (D1) / A/D enable register (0x40244) in the software serves as a trigger to start A/D conversion. B-IV-2-4 EPSON S1C33L03 FUNCTION PART IV ANALOG BLOCK: A/D CONVERTER A-1 Setting the sampling time The A/D converter contains ST[1:0] (D[1:0]) / A/D sampling register (0x40245) that allows the analog-signal input sampling time to be set in four steps (3, 5, 7, or 9 times the input clock period). However, this register should be used as set by default (ST = "11"; x9 clock periods). Control and Operation of A/D Conversion Figure 2.2 shows the operation of the A/D converter. ADE Trigger ADST A/D operation (When AD0 to AD2 are converted) Sampling Conversion Sampling Conversion Sampling Conversion AD0 AD0 AD1 AD1 AD2 AD2 AD0 converted data ADD AD1 converted data AD2 converted data ADD is overwritten ADF Conversion-result read OWE Interrupt request (1) Normal mode ADE Trigger ADST A/D operation Reset in software (When only AD0 is converted) Sampling Conversion Sampling Conversion AD0-1 AD0-1 AD0-2 AD0-2 Sampling Conversion AD0-3 invalid AD0-1 converted data AD0-2 converted data ADD ADF Conversion-result read OWE Interrupt request (2) Continuous mode B-IV Figure 2.2 Operation of A/D Converter Starting up the A/D converter circuit A/D After the settings specified in the preceding section have been made, write "1" to ADE (D2) / A/D enable register (0x40244) to enable the A/D converter. The A/D converter is thereby readied to accept a trigger to start A/D conversion. To set the A/D converter again, or if it is not be used, set ADE to "0". Starting A/D conversion When a trigger is input while ADE = "1", A/D conversion is started. If a software trigger has been selected, A/D conversion is started by writing "1" to ADST (D1) / A/D enable register (0x40244). Only the trigger selected using TS[1:0] (D[4:3]) / A/D trigger register (0x40242) are valid; no other trigger is accepted. S1C33L03 FUNCTION PART EPSON B-IV-2-5 IV ANALOG BLOCK: A/D CONVERTER When a trigger is input, the A/D converter samples and A/D-converts the analog input signal, beginning with the conversion start channel selected by CS[2:0]. Upon completion of the A/D conversion in that channel, the A/D converter stores the conversion result, in 10bit data registers ADD[9:0] (ADD[9:8] = D[1:0]/0x40241, ADD[7:0] = D[7:0]/0x40240), and sets the conversion-complete flag ADF (D3) / A/D enable register (0x40244) and interrupt factor flag FADE (D0) / Port input 4-7, clock timer and A/D interrupt factor flag register (0x40287). If multiple channels are specified using CS[2:0] and CE[2:0], A/D conversions in the subsequent channels are performed in succession. The ADST used for the software trigger is set to "1" during A/D conversion, even when it is started by some other trigger, so it can be used as an A/D-conversion status bit. The channel in which conversion is underway can be identified by reading CH[2:0] (D[2:0]) / A/D trigger register (0x40242). Reading out A/D conversion results As explained earlier, the results of A/D conversion are stored in the ADD[9:0] register each time conversion in one channel is completed. Since an interrupt can be generated simultaneously, this interrupt is normally used to read out the converted data. In addition, be sure to reset the interrupt factor flag (by writing "0") to prepare the A/D converter for the next operation. Since the interrupt factor of the A/D converter can also be used to invoke DMA, the conversion results can automatically be transferred to a specified memory location. If multiple A/D conversion channels are specified, the conversion results in one channel must be read out prior to completion of conversion in the next channel. If the A/D conversion currently under way is completed before the previous conversion results are read out, the ADD[9:0] register is overwritten with the new conversion results. If ADD[9:0] is updated when the conversion-complete flag ADF = "1" (before the converted data is read out), the overwrite-error flag OWE (D0) / A/D enable register (0x40244) is set to "1". The conversion-complete flag ADF is reset to "0" when the converted data is read out. If ADD[9:0] is updated when ADF = "0", OWE remains at "0", indicating that the operation has been completed normally. When reading out data, also read the OWE flag also to make sure the data is valid. Once OWE is set, it remains set until it is reset to "0" in the software. Note also that if OWE is set, ADF also is set. In this case, read out the converted data and reset ADF. Terminating A/D conversion * For normal mode (MS = "1") In the normal mode, A/D conversion is performed successively from the conversion start channel specified using CS[2:0] to the conversion end channel specified using CE[2:0], and is completed after these conversions are executed in one operation. ADST is reset to "0" upon completion of the conversion. * For continuous mode (MS = "0") In the continuous mode, A/D conversion from the conversion-start to the conversion-end channels is executed repeatedly, without being stopped in the hardware. To terminate conversion, therefore, ADST must be reset to "0" in the software. However, the A/D conversion being executed will be completed normally or forcibly stopped depending on the timing of writing "0" to ADST. When the A/D conversion has completed normally, ADF is set to "1" and the conversion results can be obtained. If it is forcibly stopped, ADF maintains its previous status, therefore, conversion results cannot be obtained. * Forced termination In the continuous mode, A/D conversion is immediately terminated by writing "0" to ADST. The results of the conversion then under-way cannot be obtained. In the normal mode, writing "0" to ADST cannot terminate A/D conversion. Note that writing "0" to ADE cannot terminate the A/D conversion under-way (ADST = "1"). Note: Once A/D conversion ends, further A/D conversion will not be performed correctly if restarted within an interval shorter than one cycle of the A/D converter operating clock set by the prescaler. B-IV-2-6 EPSON S1C33L03 FUNCTION PART IV ANALOG BLOCK: A/D CONVERTER A-1 A/D Converter Interrupt and DMA Upon completion of A/D conversion in each channel, the A/D converter generates an interrupt and invokes the DMA if necessary. Control registers of the interrupt controller The following shows the interrupt control registers available for the A/D converter: Interrupt factor flag: FADE (D0) / Port input 4-7, clock timer, A/D interrupt factor flag register (0x40287) Interrupt enable: EADE (D0) / Port input 4-7, clock timer, A/D interrupt enable register (0x40277) Interrupt level: PAD[2:0] (D[6:4]) / Serial I/F Ch.1, A/D interrupt priority register (0x4026A) The A/D converter sets the interrupt factor flag to "1" when A/D conversion in one channel is completed, and the conversion results are stored in the ADD register. At this time, if the interrupt enable register bit has been set to "1", an interrupt request is generated. Interrupts can be disabled by leaving the interrupt enable register bit set to "0". The interrupt factor flag is set to "1" upon completion of A/D conversion in each channel, regardless of the setting of the interrupt enable register (even when it is set to "0"). The interrupt priority register sets the priority level (0 to 7) of an interrupt. An interrupt request to the CPU is accepted no other interrupt request of a higher priority has been generated. In addition, it is only when the PSR's IE bit = "1" (interrupts enabled) and the set value of the IL is smaller than the A/D-converter interrupt level set by the interrupt priority register, that the A/D converter's interrupt request is actually accepted by the CPU. For details on these interrupt control registers, as well as the device operation when an interrupt has occurred, refer to "ITC (Interrupt Controller)". Intelligent DMA The A/D converter can invoke the intelligent DMA (IDMA) through the use of its interrupt factor. This allows the conversion results to be transferred to a specified memory location with no need to execute an interrupt processing routine. The IDMA channel number assigned to the A/D converter is 0x1B. Before IDMA can be invoked, the IDMA request and IDMA enable bits must be set to "1". Transfer conditions on the IDMA side must also be set in advance. IDMA request: RADE (D2) / Serial I/F Ch.1, A/D, Port input 4-7 IDMA request register (0x40293) IDMA enable: DEADE (D2) / Serial I/F Ch.1, A/D, Port input 4-7 IDMA enable register (0x40297) If an interrupt factor occurs when the IDMA request and IDMA enable bits are set to "1", IDMA is invoked. No interrupt request is generated at that point. An interrupt request is generated upon completion of the DMA transfer. Otherwise, the bit can be set so as not to generate an interrupt, with only a DMA transfer performed. For details on DMA transfers and how to control interrupts upon completion of a DMA transfer, refer to "IDMA (Intelligent DMA)". B-IV High-speed DMA The A/D interrupt factor can also invoke high-speed DMA (HSDMA). The following shows the HSDMA channel number and trigger set-up bit: A/D Table 2.5 HSDMA Trigger Set-up Bits HSDMA channel 0 1 2 3 Trigger set-up bits HSD0S[3:0] (D[3:0]) / HSDMA Ch.0/1 trigger set-up register (0x40298) HSD1S[3:0] (D[7:4]) / HSDMA Ch.0/1 trigger set-up register (0x40298) HSD2S[3:0] (D[3:0]) / HSDMA Ch.2/3 trigger set-up register (0x40299) HSD3S[3:0] (D[7:4]) / HSDMA Ch.2/3 trigger set-up register (0x40299) For HSDMA to be invoked, the trigger set-up bits should be set to "1100" in advance. Transfer conditions, etc. must also be set on the HSDMA side. If the A/D interrupt factor is selected as the HSDMA trigger, the HSDMA channel is invoked through generation of the interrupt factor. For details on HSDMA transfer, refer to "HSDMA (High-Speed DMA)". S1C33L03 FUNCTION PART EPSON B-IV-2-7 IV ANALOG BLOCK: A/D CONVERTER Trap vector The A/D converter's interrupt trap-vector default address is set to 0x0C00100. The base address of the trap table can be changed using the TTBR register (0x48134 to 0x48137). B-IV-2-8 EPSON S1C33L03 FUNCTION PART IV ANALOG BLOCK: A/D CONVERTER A-1 I/O Memory of A/D Converter Table 2.6 shows the control bits of the A/D converter. For details on the I/O memory of the prescaler used to set clocks, refer to "Prescaler". For details on the I/O memory of the programmable timers used for a trigger, refer to "8-Bit Programmable Timers" or "16-Bit Programmable Timers". Table 2.6 Control Bits of A/D Converter Register name Address Bit A/D conversion 0040240 result (low(B) order) register D7 D6 D5 D4 D3 D2 D1 D0 Name ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 Function 0 0 0 0 0 0 0 0 R - 0x0 to 0x3FF (high-order 2 bits) - 0 0 - R - - 0 0 0 D7-2 - D1 ADD9 D0 ADD8 - A/D converted data (high-order 2 bits) ADD9 = MSB A/D trigger register D7-6 D5 D4 D3 - MS TS1 TS0 - A/D conversion mode selection A/D conversion trigger selection D2 D1 D0 CH2 CH1 CH0 A/D conversion channel status D7-6 D5 D4 D3 - CE2 CE1 CE0 - A/D converter end channel selection D2 D1 D0 CS2 CS1 CS0 A/D converter start channel selection A/D channel register 0040243 (B) A/D enable register 0040244 (B) D7-4 D3 D2 D1 D0 A/D sampling register 0040245 (B) D7-2 - D1 ST1 D0 ST0 S1C33L03 FUNCTION PART - ADF ADE ADST OWE Init. R/W 0x0 to 0x3FF (low-order 8 bits) A/D conversion 0040241 result (high(B) order) register 0040242 (B) Setting A/D converted data (low-order 8 bits) ADD0 = LSB - Conversion-complete flag A/D enable A/D conversion control/status Overwrite error flag - Input signal sampling time setup EPSON 1 Continuous TS[1:0] 1 1 1 0 0 1 0 0 CH[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 CE[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 CS[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 1 1 1 1 Completed Enabled Start/Run Error ST[1:0] 1 1 1 0 0 1 0 0 0 Normal Trigger #ADTRG pin 8-bit timer 0 16-bit timer 0 Software Channel AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 0 0 0 Remarks 0 when being read. - 0 when being read. R/W R/W R - End channel AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Start channel AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 - 0 0 0 - 0 when being read. R/W 0 0 0 R/W - - 0 0 0 0 - 0 when being read. R Reset when ADD is read. R/W R/W R/W Reset by writing 0. - 1 1 - 0 when being read. R/W Use with 9 clocks. 0 0 0 0 Run/Standby Disabled Stop Normal - Sampring time 9 clocks 7 clocks 5 clocks 3 clocks B-IV A/D B-IV-2-9 IV ANALOG BLOCK: A/D CONVERTER Register name Address Bit Serial I/F Ch.1, 004026A A/D interrupt (B) priority register D7 D6 D5 D4 D3 D2 D1 D0 Name Function reserved A/D converter interrupt level - 0 to 7 reserved Serial interface Ch.1 interrupt level - 0 to 7 Port input 4-7, 0040277 clock timer, (B) A/D interrupt enable register D7-6 D5 D4 D3 D2 D1 D0 - EP7 EP6 EP5 EP4 ECTM EADE reserved Port input 7 Port input 6 Port input 5 Port input 4 Clock timer A/D converter Port input 4-7, 0040287 clock timer, A/D (B) interrupt factor flag register D7-6 D5 D4 D3 D2 D1 D0 - FP7 FP6 FP5 FP4 FCTM FADE reserved Port input 7 Port input 6 Port input 5 Port input 4 Clock timer A/D converter D7 D6 D5 D4 D3 D2 D1 D0 RP7 RP6 RP5 RP4 - RADE RSTX1 RSRX1 D7 D6 D5 D4 D3 D2 D1 D0 DEP7 DEP6 DEP5 DEP4 - DEADE DESTX1 DESRX1 Serial I/F Ch.1, A/D, port input 4-7 IDMA request register Serial I/F Ch.1, A/D, port input 4-7 IDMA enable register 0040293 (B) 0040297 (B) Setting - PAD2 PAD1 PAD0 - PSIO12 PSIO11 PSIO10 Init. R/W - 1 Enabled 0 Disabled - 1 Factor is generated 0 No factor is generated Port input 7 Port input 6 Port input 5 Port input 4 reserved A/D converter SIF Ch.1 transmit buffer empty SIF Ch.1 receive buffer full 1 IDMA request 0 Interrupt request 1 IDMA request 0 Interrupt request Port input 7 Port input 6 Port input 5 Port input 4 reserved A/D converter SIF Ch.1 transmit buffer empty SIF Ch.1 receive buffer full 1 IDMA enabled 0 IDMA disabled - - 1 IDMA enabled 0 IDMA disabled - 0 when being read. R/W - 0 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W R/W - X X X X X X - 0 when being read. R/W R/W R/W R/W R/W R/W 0 0 0 0 - 0 0 0 R/W R/W R/W R/W - 0 when being read. R/W R/W R/W 0 0 0 0 - 0 0 0 R/W R/W R/W R/W - 0 when being read. R/W R/W R/W - 0 when being read. R/W K5 function select register 00402C0 D7-5 - (B) D4 CFK54 D3 CFK53 D2 CFK52 D1 CFK51 D0 CFK50 reserved K54 function selection K53 function selection K52 function selection K51 function selection K50 function selection 1 1 1 1 1 #DMAREQ3 #DMAREQ2 #ADTRG #DMAREQ1 #DMAREQ0 0 0 0 0 0 K54 K53 K52 K51 K50 - 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W K6 function select register 00402C3 (B) K67 function selection K66 function selection K65 function selection K64 function selection K63 function selection K62 function selection K61 function selection K60 function selection 1 1 1 1 1 1 1 1 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 0 0 0 0 0 0 0 0 K67 K66 K65 K64 K63 K62 K61 K60 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W D7 D6 D5 D4 D3 D2 D1 D0 CFK67 CFK66 CFK65 CFK64 CFK63 CFK62 CFK61 CFK60 - Remarks - X X X - X X X CFK52: K52 pin function selection (D2) / K5 function select register (0x402C0) CFK67-CFK60: K6[7:0] pin function selection (D[7:0]) / K6 function select register (0x402C3) Selects the pins used by the A/D converter. Write "1": A/D converter Write "0": Input port Read: Valid When an external trigger is used, write "1" to CFK52 to set the K52 pin for external trigger input #ADTRG. Select the pin used for analog input from among K60 (AD0) through K67 (AD7) by writing "1" to CFK60 through CFK67. If the function select bit for a pin is set to "0", the pin is set for an input port. At cold start, CFK is set to "0" (input port). At hot start, CFK retains its state from prior to the initial reset. B-IV-2-10 EPSON S1C33L03 FUNCTION PART IV ANALOG BLOCK: A/D CONVERTER A-1 ADD9-ADD0: A/D converted data (D[1:0]) / A/D conversion result (high-order) register (0x40241) (D[7:0]) / A/D conversion result (low-order) register (0x40240) Stores the results of A/D conversion. The LSB is stored in ADD0, and the MSB is stored in ADD9. ADD0 and ADD1 are mapped to bits D0 and D1 at the address 0x40241, but bits D2 through D7 are always 0 when read. This is a read-only register, so writing to this register is ignored. At initial reset, the data in this register is cleared to "0". MS: A/D conversion mode selection (D5) / A/D trigger register (0x40242) Selects an A/D conversion mode. Write "1": Continuous mode Write "0": Normal mode Read: Valid The A/D converter is set for the continuous mode by writing "1" to MS. In this mode, A/D conversions in the range of the channels selected using CS and CE are executed continuously until stopped in the software. When MS = "0", the A/D converter operates in the normal mode. In this mode, A/D conversion is completed after all inputs in the range of the channels selected by CS and CE are converted in one operation. At initial reset, MS is set to "0" (normal mode). TS1-TS0: Trigger selection (D[4:3]) / A/D trigger register (0x40242) Selects a trigger to start A/D conversion. Table 2.7 Trigger Selection TS1 TS0 Trigger 1 1 0 0 1 0 1 0 External trigger (K52/#ADTRG) 8-bit programmable timer 0 16-bit programmable timer 0 Software When an external trigger is used, use the CFK52 bit to set the K52 pin for #ADTRG. When a programmable timer is used, since its underflow signal (8-bit timer) or comparison match B signal (16-bit timer) serves as a trigger, set the cycle and other parameters for the programmable timer. At initial reset, TS is set to "0" (software trigger). CH2-CH0: Conversion channel status (D[2:0]) / A/D trigger register (0x40242) Indicates the channel number (0 to 7) currently being A/D-converted. When A/D conversion is performed in multiple channels, read this bit to identify the channel in which conversion is underway. At initial reset, CH is set to "0" (AD0). CE2-CE0: Conversion end-channel setup (D[5:3]) / A/D channel register (0x40243) Sets the conversion end channel by selecting a channel number from 0 to 7. Analog inputs can be A/D-converted successively from the channel set using CS to the channel set using this bit in one operation. If only one channel is to be A/D converted, set the same channel number in both the CS and CE bits. At initial reset, CE is set to "0" (AD0). CS2-CS0: Conversion start-channel setup (D[2:0]) / A/D channel register (0x40243) Sets the conversion start channel by selecting a channel number from 0 to 7. Analog inputs can be A/D-converted successively from the channel set using this bit to the channel set using CE in one operation. If only one channel is to be A/D converted, set the same channel number in both the CS and CE bits. At initial reset, CS is set to "0" (AD0). S1C33L03 FUNCTION PART EPSON B-IV-2-11 B-IV A/D IV ANALOG BLOCK: A/D CONVERTER ADF: Conversion-complete flag (D3) / A/D enable register (0x40244) Indicates that A/D conversion has been completed. Read "1": Conversion completed Read "0": Being converted or standing by Write: Invalid This flag is set to "1" when A/D conversion is completed, and the converted data is stored in the data register and is reset to "0" when the converted data is read out. When A/D conversion is performed in multiple channels, if the next A/D conversion is completed while ADF = "1" (before the converted data is read out), the data register is overwritten with the new conversion results, causing an overrun error to occur. Therefore, ADF must be reset by reading out the converted data before the next A/D conversion is completed. At initial reset, ADF is set to "0" (being converted or standing by). ADE: A/D enable (D2) / A/D enable register (0x40244) Enables the A/D converter (readied for conversion). Write "1": Enabled Write "0": Disabled Read: Valid When ADE is set to "1", the A/D converter is enabled, meaning it is ready to start A/D conversion (i.e., ready to accept a trigger). When ADE = "0", the A/D converter is disabled, meaning it is unable to accept a trigger. Before setting the conversion mode, start/end channels, etc. for the A/D converter, be sure to reset ADE to "0". This helps to prevent the A/D converter from operating erratically. At initial reset, ADE is set to "0" (disabled). ADST: A/D conversion control/status (D1) / A/D enable register (0x40244) Controls A/D conversion. Write "1": Software trigger Write "0": A/D conversion is stopped Read: Valid If A/D conversion is to be started by a software trigger, set ADST to "1". If any other trigger is used, ADST is automatically set to "1" by the hardware. ADST remains set while A/D conversion is underway. In normal mode, upon completion of A/D conversion in selected channels, ADST is reset to "0" and the A/D conversion circuit is turned off. To stop A/D conversion during operation in continuous mode, reset ADST by writing "0". When ADE = "0" (A/D conversion disabled), ADST is fixed to "0", with no trigger accepted. However, when "0" is written to ADE during A/D conversion, A/D conversion cannot be terminated. At initial reset, ADST is set to "0" (A/D conversion stopped). OWE: Overwrite-error flag (D0) / A/D enable register (0x40244) Indicates that the converted data has been overwritten. Read "1": Read "0": Write "1": Write "0": Overwritten Normal Invalid Flag is set During A/D conversion in multiple channels, if the conversion results for the next channel are written to the converted-data register (overwritten) before the converted data is read out to reset the conversion-complete flag ADF that has been set through conversion of the preceding channel, OWE is set to "1". When ADF is reset, because this means that the converted data has been read out, OWE is not set. Once OWE is set to "1", it remains set until it is reset by writing "0" in the software. At initial reset, OWE is set to "0" (normal). B-IV-2-12 EPSON S1C33L03 FUNCTION PART IV ANALOG BLOCK: A/D CONVERTER A-1 ST1-ST0: Sampling-time setup (D[1:0]) / A/D sampling register (0x40245) Sets the analog input sampling time. Table 2.8 Sampling Time ST1 ST0 Sampling Time 1 1 9-clock period 1 0 7-clock period 0 1 5-clock period 0 0 3-clock period The A/D converter input clock is used for counting. At initial reset, ST is set to "11" (9-clock period). To maintain the conversion accuracy, use ST as set by default (9-clock period). PAD2-PAD0: A/D converter interrupt level (D[6:4]) / Serial I/F Ch.1, A/D interrupt priority register (0x4026A) Sets the priority level of the A/D-converter interrupt in the range of 0 to 7. At initial reset, PAD becomes indeterminate. EADE: A/D converter interrupt enable (D0) / Port input 4-7, clock timer, A/D interrupt enable register (0x40277) Enables or disables an interrupt to the CPU generated by the A/D converter. Write "1": Interrupt enabled Write "0": Interrupt disabled Read: Valid EADE is an interrupt enable bit to control the A/D converter interrupt. When EADE is set to "1", the A/D converter interrupt is enabled. When EADE is set to "0", the A/D-converter interrupt is disabled. At initial reset, EADE is set to "0" (interrupt disabled). FADE: A/D converter interrupt factor flag (D0) / Port input 4-7, clock timer, A/D interrupt factor flag register (0x40287) Indicates the status of an A/D-converter interrupt factor generated. When read Read "1": Interrupt factor has occurred Read "0": No interrupt factor has occurred When written using the reset-only method (default) Write "1": Interrupt factor flag is reset Write "0": Invalid When written using the read/write method Write "1": Interrupt flag is set Write "0": Interrupt flag is reset B-IV FADE is the interrupt factor flag of the A/D converter. It is set to "1" upon completion of A/D conversion in one channel (i.e., when the conversion results are written into the ADD register). At this time, if the following conditions are met, an interrupt to the CPU is generated: 1. The corresponding interrupt enable register bit is set to "1". 2. No other interrupt request of a higher priority has been generated. 3. The IE bit of the PSR is set to "1" (interrupts enabled). 4. The value set in the corresponding interrupt priority register is higher than the interrupt level (IL) of the CPU. When using the interrupt factor of the A/D converter to request IDMA, note that even when the above conditions are met, no interrupt request to the CPU is generated for the interrupt factor that has occurred. If interrupts are enabled at the setting of IDMA, an interrupt is generated under the above conditions after the data transfer by IDMA is completed. S1C33L03 FUNCTION PART EPSON B-IV-2-13 A/D IV ANALOG BLOCK: A/D CONVERTER The interrupt factor flag is set to "1" whenever interrupt generation conditions are met, regardless of how the interrupt enable and interrupt priority registers are set. If the next interrupt is to be accepted after an interrupt has occurred, it is necessary that the interrupt factor flag be reset, and that the PSR be set again (by setting the IE bit to "1" after setting the IL to a value lower than the level indicated by the interrupt priority register, or by executing the reti instruction). The interrupt factor flag can be reset only by writing to it in the software. Note that if the PSR is set again to accept interrupts generated (or if the reti instruction is executed) without resetting the interrupt factor flag, the same interrupt occurs again. Note also that the value to be written to reset the flag is "1" when the reset-only method (RSTONLY = "1") is used, and "0" when the read/write method (RSTONLY = "0") is used. At initial reset, the content of FADE becomes indeterminate, so be sure to reset it in the software. RADE: A/D converter IDMA request (D2) / Serial I/F Ch.1, A/D, port input 4-7 IDMA request register (0x40293) Specifies whether to invoke IDMA when an interrupt factor occurs. When using the set-only method (default) Write "1": IDMA request Write "0": Not changed Read: Valid When using the read/write method Write "1": IDMA request Write "0": Interrupt request Read: Valid When RADE is set to "1", IDMA is invoked when an interrupt factor occurs, thereby performing a programmed data transfer. If RADE is set to "0", normal interrupt processing is performed, without invoking IDMA. For details on IDMA, refer to "IDMA (Intelligent DMA)". At initial reset, RADE is set to "0" (interrupt request). DEADE: A/D converter IDMA enable (D2) / Serial I/F Ch.1, A/D, port input 4-7 IDMA enable register (0x40297) Enables IDMA transfer by means of an interrupt factor. When using the set-only method (default) Write "1": IDMA enabled Write "0": Not changed Read: Valid When using the read/write method Write "1": IDMA enabled Write "0": IDMA disabled Read: Valid If DEADE is set to "1", the IDMA request by the interrupt factor is enabled. If this bit is set to "0", the IDMA request is disabled. After an initial reset, DEADE is set to "0" (IDMA disabled). B-IV-2-14 EPSON S1C33L03 FUNCTION PART IV ANALOG BLOCK: A/D CONVERTER A-1 Programming Notes (1) Before setting the conversion mode, start/end channels, etc. for the A/D converter, be sure to disable the A/D converter (ADE (D2) / A/D enable register (0x40244) = "0"). A change in settings while the A/D converter is enabled could cause it to operate erratically. (2) The A/D converter operates only when the prescaler is operating. When the A/D converter registers are set up, the prescaler must be operating. Therefore, start the prescaler first and make sure the A/D converter is supplied with its operating clock before setting up the A/D converter registers. In consideration of the conversion accuracy, we recommend that the A/D converter operating clock be min. 32 kHz to max. 2 MHz. (3) Do not start an A/D conversion when the clock supplied from the prescaler to the A/D converter is turned off, and do not turn off the prescaler's clock output when an A/D conversion is underway, as doing so could cause the A/D converter to operate erratically. (4) After an initial reset, the interrupt factor flag (FADE) becomes indeterminate. To prevent generation of an unwanted interrupt or IDMA request, be sure to reset this flag and register in a program. (5) To prevent the regeneration of interrupts due to the same factor following the occurrence an interrupt, always be sure to reset the interrupt factor flag before setting the PSR again or executing the reti instruction. (6) When the A/D converter is set to enabled state, a current flows between AVDDE and VSS, and power is consumed, even when A/D operations are not performed. Therefore, when the A/D converter is not used, it must be set to the disabled state (default "0" setting of ADE (D2) in the A/D enable register (0x40244)). (7) Once A/D conversion ends, further A/D conversion will not be performed correctly if restarted within an interval shorter than one cycle of the A/D converter operating clock set by the prescaler. (8) When the 8-bit programmable timer 0 underflow signal or the 16-bit programmable timer 0 compare match B signal is used as a trigger factor, the division ratio of the prescaler used by the relevant timer must not be set to /1. (9) ADD[9:0] (A/D conversion results) is read twice, once in the low-order 8 bits and once in the high-order 2 bits. (The hardware loads the results in this manner even if the software reads the register in 16 bits.) In continuous mode or when two or more channels are converted successively in normal mode, ADD[9:0] may be overwritten with the new conversion results between reading of the low-order 8 bits and high-order 2 bits. In this case, correct conversion results cannot be obtained because the low-order 8 bits and the highorder 2 bits are not the results of the same conversion. At the 1st reading of the conversion results after an A/D conversion has completed (when the conversioncomplete flag ADF is set to "1"), the overwrite-error flag OWE is set to "1" if ADD[9:0] is overwritten between reading of the low-order 8 bits and high-order 2 bits. Note, however, that OWE is not set to "1" even if ADD[9:0] is overwritten when the same conversion results have already been read (when ADF is reset to "0"). This may occur when the program reads the same results twice or more for verification or other purposes. S1C33L03 FUNCTION PART EPSON B-IV-2-15 B-IV A/D IV ANALOG BLOCK: A/D CONVERTER THIS PAGE IS BLANK. B-IV-2-16 EPSON S1C33L03 FUNCTION PART S1C33L03 FUNCTION PART V DMA BLOCK V DMA BLOCK: INTRODUCTION A-1 V-1 INTRODUCTION The DMA Block is configured with two types of DMA controllers: HSDMA (High-Speed DMA) that has onchip registers for controlling DMA command information and IDMA (Intelligent DMA) that uses a memory area for storing DMA command information. C33 DMA Block C33 SDRAM Controller Block C33 LCD Controller Block C33_DMA C33_SDRAMC C33_LCDC (IDMA, HSDMA) (SDRAM interface) (LCD panel interface) Pads Internal RAM (Area 0) CORE_PAD C33 Internal Memory Block C33_CORE (CPU, BCU, ITC, CLG, DBG) Internal ROM (Area 10) Pads C33_SBUS C33_ADC C33_PERI (A/D converter) (Prescaler, 8-bit timer, 16-bit timer, Clock timer, Serial interface, Ports) C33 Analog Block PERI_PAD C33 Core Block Pads C33 Peripheral Block Figure 1.1 DMA Block Note: Internal ROM is not provided in the S1C33L03. B-V Intro S1C33L03 FUNCTION PART EPSON B-V-1-1 V DMA BLOCK: INTRODUCTION THIS PAGE IS BLANK. B-V-1-2 EPSON S1C33L03 FUNCTION PART V DMA BLOCK: HSDMA (High-Speed DMA) A-1 V-2 HSDMA (High-Speed DMA) Functional Outline of HSDMA The DMA Block contains four channels of HSDMA (High-Speed DMA) circuits that support dual-address transfer and single-address transfer methods. Since the control registers required for the DMA function are built into the chip, DMA requests for data transfer can be responded to instantaneously. Dual-address transfer In this method, a source address and a destination address for DMA transfer can be specified and a DMA transfer is performed in two phases. The first phase reads data at the source address into the on-chip temporary register. The second phase writes the temporary register data to the destination address. Unlike IDMA (Intelligent DMA), which has transfer information in memory, this DMA method does not support a DMA link function but allows high-speed data transfers because it is not necessary to read transfer information from a memory. Address bus BCU Data bus Data transfer (2) High-speed DMA #DMAREQx #DMAENDx (1) Memory, I/O Memory, I/O Destination DMA request End of DMA Source Figure 2.1 Dual-Address Transfer Method Single-address transfer In this method, data transfers that are normally accomplished by executing data read and write operations back-to-back are executed on the external bus collectively at one time, thus further speeding up the transfer operation. The #DMAACKx and #DMAENDx signals are used to control data transfer. Unlike dual-address transfer, this method does not allow memory to memory data transfer but data transfers can be performed in minimum cycles. Bus control signals BCU Memory I/O Address bus Data bus Data transfer B-V High-speed DMA External I/O #RD/#WR #DMAREQx #DMAACKx #DMAENDx DMA request DMA reception End of DMA Note: Single-address mode does not allow data transfer between memory devices. HSDMA Figure 2.2 Single-Address Transfer Method Notes: * Channels 0 to 3 are configured in the same way and have the same functionality. Signal and control bit names are assigned channel numbers 0 to 3 to distinguish them from other channels. In this manual, however, channel numbers 0 to 3 are designated with an "x" except where they must be distinguished, as the explanation is the same for all channels. * The single-address transfer method does not allow data transfer to/from the SDRAM. S1C33L03 FUNCTION PART EPSON B-V-2-1 V DMA BLOCK: HSDMA (High-Speed DMA) I/O Pins of HSDMA Table 2.1 lists the I/O pins used for HSDMA. Table 2.1 I/O Pins of HSDMA Pin name K50/#DMAREQ0 K51/#DMAREQ1 K53/#DMAREQ2 K54/#DMAREQ3 P04/SIN1/ #DMAACK2 P05/SOUT1/ #DMAEND2 P06/#SCLK1/ #DMAACK3 P07/#SRDY1/ #DMAEND3 P15/EXCL4/ #DMAEND0 P16/EXCL5/ #DMAEND1 P32/#DMAACK0 P33/#DMAACK1 I/O I I I I I/O I/O I/O I/O I/O I/O I/O I/O Function Function select bit Input port / High-speed DMA request 0 Input port / High-speed DMA request 1 Input port / High-speed DMA request 2 Input port / High-speed DMA request 3 I/O port / Serial IF Ch.1 data input / #DMAACK2 output (Ex) I/O port / Serial IF Ch.1 data output / #DMAEND2 output (Ex) I/O port / Serial IF Ch.1 clock input/output / #DMAACK3 output (Ex) I/O port / Serial IF Ch.1 ready input/output / #DMAEND3 output (Ex) I/O port / 16-bit timer 4 event counter input (I) / #DMAEND0 output (O) I/O port / 16-bit timer 5 event counter input (I) / #DMAEND1 output (O) I/O port / #DMAACK0 output I/O port / #DMAACK1 output CFK50(D0)/K5 function select register(0x402C0) CFK51(D1)/K5 function select register(0x402C0) CFK53(D3)/K5 function select register(0x402C0) CFK54(D4)/K5 function select register(0x402C0) CFEX4(D4)/Port function extension register(0x402DF) CFEX5(D5)/Port function extension register(0x402DF) CFEX6(D6)/Port function extension register(0x402DF) CFEX7(D7)/Port function extension register(0x402DF) CFP15(D5)/P1 function select register(0x402D4) CFP16(D6)/P1 function select register(0x402D4) CFP32(D2)/P3 function select register(0x402DC) CFP33(D3)/P3 function select register(0x402DC) (I): Input mode, (O): Output mode, (Ex): Extended function #DMAREQx (DMA request input pin) This pin is used to input a DMA request signal from an external peripheral circuit. One data transfer operation is performed by this trigger (either the rising edge or the falling edge of the signal can be selected). The #DMAREQ0 to #DMAREQ3 pins correspond to channel 0 to channel 3, respectively. In addition to this external input, software trigger or an interrupt factor can be selected for the HSDMA trigger factor using the register in the interrupt controller. #DMAACKx (DMA acknowledge signal output pin for single-address mode) This signal is output to indicate that a DMA request has been acknowledged by the DMA controller. In single-address mode, the I/O device that is the source or destination of transfer outputs data to the external bus or takes in data from the external data synchronously with this signal. The #DMAACK0 to #DMAACK3 pins correspond to channel 0 to channel 3, respectively. This signal is not output in dual-address mode. #DMAENDx (End-of-transfer signal output pin) This signal is output to indicate that the number of data transfer operations that is set in the control register have been completed. The #DMAEND0 to #DMAEND3 pins correspond to channel 0 to channel 3, respectively. Method for setting HSDMA I/O pins As shown in Table 2.1, the pins used for HSDMA are shared with input ports and I/O ports. At cold start, all of these are set as input and I/O port pins (function select register = "0"). According to the signals to be used, set the corresponding pin function select bit by writing "1". At hot start, the register retains the previous status before a reset. The #DMAEND3, #DMAACK3, #DMAEND2 and #DMAACK2 outputs are the extended functions of the P04 to P07 ports. When using these signals, the extended function bit (CFEX[7:4]) must be set to "1". In addition, setup of the #DMAEND0 pin or #DMAEND1 pin further requires setting the I/O port's I/O control bit IOC15 (D5) or IOC16 (D6) / P1 I/O control register (0x402D6) by writing "1" in order to direct the pin for output. If this pin is directed for input, it functions as a 16-bit programmable timer's event counter input and cannot be used to output the #DMAENDx signal. At cold start, this pin is set for input. At hot start, it retains the previous status. B-V-2-2 EPSON S1C33L03 FUNCTION PART V DMA BLOCK: HSDMA (High-Speed DMA) A-1 Programming Control Information The HSDMA operates according to the control information set in the registers. Note that some control bits change their functions according to the address mode. The following explains how to set the contents of control information. Before using HSDMA, make each the settings described below. Setting the Registers in Dual-Address Mode Make sure that the HSDMA channel is disabled (HSx_EN = "0") before setting the control information. Address mode The address mode select bit DUALMx should be set to "1" (dual-address mode). This bit is set to "0" (singleaddress mode) at initial reset. DUALM0: Ch. 0 address mode selection (DF) / HSDMA Ch. 0 control register (0x48222) DUALM1: Ch. 1 address mode selection (DF) / HSDMA Ch. 1 control register (0x48232) DUALM2: Ch. 2 address mode selection (DF) / HSDMA Ch. 2 control register (0x48242) DUALM3: Ch. 3 address mode selection (DF) / HSDMA Ch. 3 control register (0x48252) Transfer mode A transfer mode should be set using the DxMOD[1:0] bits. D0MOD[1:0]: Ch. 0 transfer mode (D[F:E]) / HSDMA Ch. 0 high-order destination address set-up register (0x4822A) D1MOD[1:0]: Ch. 1 transfer mode (D[F:E]) / HSDMA Ch. 1 high-order destination address set-up register (0x4823A) D2MOD[1:0]: Ch. 2 transfer mode (D[F:E]) / HSDMA Ch. 2 high-order destination address set-up register (0x4824A) D3MOD[1:0]: Ch. 3 transfer mode (D[F:E]) / HSDMA Ch. 3 high-order destination address set-up register (0x4825A) The following three transfer modes are available: Single transfer mode (DxMOD = "00", default) In this mode, a transfer operation invoked by one trigger is completed after transferring one unit of data of the size set by DATSIZEx. If data transfer need to be performed a number of times as set by the transfer counter, an equal number of triggers are required. Successive transfer mode (DxMOD = "01") In this mode, data transfer operations are performed by one trigger a number of times as set by the transfer counter. The transfer counter is decremented to 0 each time data is transferred. Block transfer mode (DxMOD = "10") In this mode, a transfer operation invoked by one trigger is completed after transferring one block of data of the size set by BLKLENx. If a block transfer need to be performed a number of times as set by the transfer counter, an equal number of triggers are required. Transfer data size The DATSIZEx bit is used to set the unit size of data to be transferred. A half-word size (16 bits) is assumed if this bit is "1" and a byte size (8 bits) is assumed if this bit is "0" (default). DATSIZE0: Ch. 0 transfer data size (DE) / HSDMA Ch. 0 high-order source address set-up register (0x48226) DATSIZE1: Ch. 1 transfer data size (DE) / HSDMA Ch. 1 high-order source address set-up register (0x48236) DATSIZE2: Ch. 2 transfer data size (DE) / HSDMA Ch. 2 high-order source address set-up register (0x48246) DATSIZE3: Ch. 3 transfer data size (DE) / HSDMA Ch. 3 high-order source address set-up register (0x48256) S1C33L03 FUNCTION PART EPSON B-V HSDMA B-V-2-3 V DMA BLOCK: HSDMA (High-Speed DMA) Block length When using block transfer mode (DxMOD = "10"), the data block length (in units of DATSIZEx) should be set using the BLKLENx[7:0] bits. BLKLEN0[7:0]: Ch. 0 block length (D[7:0]) / HSDMA Ch. 0 transfer counter register (0x48220) BLKLEN1[7:0]: Ch. 1 block length (D[7:0]) / HSDMA Ch. 1 transfer counter register (0x48230) BLKLEN2[7:0]: Ch. 2 block length (D[7:0]) / HSDMA Ch. 2 transfer counter register (0x48240) BLKLEN3[7:0]: Ch. 3 block length (D[7:0]) / HSDMA Ch. 3 transfer counter register (0x48250) Note: The block size thus set is decremented according to the transfers performed. If the block size is set to 0, it is decremented to all Fs by the first transfer performed. This means that you have set the maximum value that is determined by the number of bits available. In single transfer and successive transfer modes, these bits are used as the bits7-0 of the transfer counter. Transfer counter Block transfer mode In block transfer mode, up to 16 bits of transfer count can be specified. TC0_L[7:0]: Ch. 0 transfer counter [7:0] (D[F:8]) / HSDMA Ch. 0 transfer counter register (0x48220) TC1_L[7:0]: Ch. 1 transfer counter [7:0] (D[F:8]) / HSDMA Ch. 1 transfer counter register (0x48230) TC2_L[7:0]: Ch. 2 transfer counter [7:0] (D[F:8]) / HSDMA Ch. 2 transfer counter register (0x48240) TC3_L[7:0]: Ch. 3 transfer counter [7:0] (D[F:8]) / HSDMA Ch. 3 transfer counter register (0x48250) TC0_H[7:0]: Ch. 0 transfer counter [15:8] (D[7:0]) / HSDMA Ch. 0 control register (0x48222) TC1_H[7:0]: Ch. 1 transfer counter [15:8] (D[7:0]) / HSDMA Ch. 1 control register (0x48232) TC2_H[7:0]: Ch. 2 transfer counter [15:8] (D[7:0]) / HSDMA Ch. 2 control register (0x48242) TC3_H[7:0]: Ch. 3 transfer counter [15:8] (D[7:0]) / HSDMA Ch. 3 control register (0x48252) Single transfer and successive transfer modes In single transfer and successive transfer modes, up to 24 bits of transfer count can be specified. BLKLEN0[7:0]: Ch. 0 transfer counter [7:0] (D[7:0]) / HSDMA Ch.0 transfer counter register (0x48220) BLKLEN1[7:0]: Ch. 1 transfer counter [7:0] (D[7:0]) / HSDMA Ch.1 transfer counter register (0x48230) BLKLEN2[7:0]: Ch. 2 transfer counter [7:0] (D[7:0]) / HSDMA Ch.2 transfer counter register (0x48240) BLKLEN3[7:0]: Ch. 3 transfer counter [7:0] (D[7:0]) / HSDMA Ch.3 transfer counter register (0x48250) TC0_L[7:0]: Ch. 0 transfer counter [15:8] (D[F:8]) / HSDMA Ch. 0 transfer counter register (0x48220) TC1_L[7:0]: Ch. 1 transfer counter [15:8] (D[F:8]) / HSDMA Ch. 1 transfer counter register (0x48230) TC2_L[7:0]: Ch. 2 transfer counter [15:8] (D[F:8]) / HSDMA Ch. 2 transfer counter register (0x48240) TC3_L[7:0]: Ch. 3 transfer counter [15:8] (D[F:8]) / HSDMA Ch. 3 transfer counter register (0x48250) TC0_H[7:0]: Ch. 0 transfer counter [23:16] (D[7:0]) / HSDMA Ch. 0 control register (0x48222) TC1_H[7:0]: Ch. 1 transfer counter [23:16] (D[7:0]) / HSDMA Ch. 1 control register (0x48232) TC2_H[7:0]: Ch. 2 transfer counter [23:16] (D[7:0]) / HSDMA Ch. 2 control register (0x48242) TC3_H[7:0]: Ch. 3 transfer counter [23:16] (D[7:0]) / HSDMA Ch. 3 control register (0x48252) Note: The transfer count thus set is decremented according to the transfers performed. If the transfer count is set to 0, it is decremented to all Fs by the first transfer performed. This means that you have set the maximum value that is determined by the number of bits available. Source and destination addresses In dual-address mode, a source address and a destination address for DMA transfer can be specified. S0ADRL[15:0]: Ch. 0 source address [15:0] (D[F:0]) / Ch. 0 low-order source address set-up register (0x48224) S1ADRL[15:0]: Ch. 1 source address [15:0] (D[F:0]) / Ch. 1 low-order source address set-up register (0x48234) S2ADRL[15:0]: Ch. 2 source address [15:0] (D[F:0]) / Ch. 2 low-order source address set-up register (0x48244) S3ADRL[15:0]: Ch. 3 source address [15:0] (D[F:0]) / Ch. 3 low-order source address set-up register (0x48254) S0ADRH[11:0]: Ch. 0 source address [27:16] (D[B:0]) / Ch. 0 high-order source address set-up register (0x48226) S1ADRH[11:0]: Ch. 1 source address [27:16] (D[B:0]) / Ch. 1 high-order source address set-up register (0x48236) S2ADRH[11:0]: Ch. 2 source address [27:16] (D[B:0]) / Ch. 2 high-order source address set-up register (0x48246) S3ADRH[11:0]: Ch. 3 source address [27:16] (D[B:0]) / Ch. 3 high-order source address set-up register (0x48256) B-V-2-4 EPSON S1C33L03 FUNCTION PART V DMA BLOCK: HSDMA (High-Speed DMA) A-1 D0ADRL[15:0]: D1ADRL[15:0]: D2ADRL[15:0]: D3ADRL[15:0]: D0ADRH[11:0]: D1ADRH[11:0]: D2ADRH[11:0]: D3ADRH[11:0]: Ch. 0 destination address [15:0] (D[F:0]) / Ch. 0 low-order destination address set-up register (0x48228) Ch. 1 destination address [15:0] (D[F:0]) / Ch. 1 low-order destination address set-up register (0x48238) Ch. 2 destination address [15:0] (D[F:0]) / Ch. 2 low-order destination address set-up register (0x48248) Ch. 3 destination address [15:0] (D[F:0]) / Ch. 3 low-order destination address set-up register (0x48258) Ch. 0 destination address [27:16] (D[B:0]) / Ch. 0 high-order destination address set-up register (0x4822A) Ch. 1 destination address [27:16] (D[B:0]) / Ch. 1 high-order destination address set-up register (0x4823A) Ch. 2 destination address [27:16] (D[B:0]) / Ch. 2 high-order destination address set-up register (0x4824A) Ch. 3 destination address [27:16] (D[B:0]) / Ch. 3 high-order destination address set-up register (0x4825A) Address increment/decrement control The source and/or destination addresses can be incremented or decremented when one data transfer is completed. The SxIN[1:0] bits (for source address) and DxIN[1:0] bits (for destination address) are used to set this function. S0IN[1:0]: Ch. 0 source address control (D[D:C]) / Ch. 0 high-order source address set-up register (0x48226) S1IN[1:0]: Ch. 1 source address control (D[D:C]) / Ch. 1 high-order source address set-up register (0x48236) S2IN[1:0]: Ch. 2 source address control (D[D:C]) / Ch. 2 high-order source address set-up register (0x48246) S3IN[1:0]: Ch. 3 source address control (D[D:C]) / Ch. 3 high-order source address set-up register (0x48256) D0IN[1:0]: Ch. 0 destination address control (D[D:C]) / Ch. 0 high-order destination address set-up register (0x4822A) D1IN[1:0]: Ch. 1 destination address control (D[D:C]) / Ch. 1 high-order destination address set-up register (0x4823A) D2IN[1:0]: Ch. 2 destination address control (D[D:C]) / Ch. 2 high-order destination address set-up register (0x4824A) D3IN[1:0]: Ch. 3 destination address control (D[D:C]) / Ch. 3 high-order destination address set-up register (0x4825A) SxIN/DxIN = "00": address fixed (default) The address is not changed by a data transfer performed. Even when transferring multiple data, the transfer data is always read/write from/to the same address. SxIN/DxIN = "01": address decremented without initialization The address is decremented by an amount equal to the data size set by DATSIZEx when one data transfer is completed. The address that has been decremented during transfer does not return to the initial value. SxIN/DxIN = "10": address incremented with initialization If this function is selected in single and successive transfer modes, the address is incremented by an amount equal to the data size set by DATSIZEx when one data transfer is completed. The address that has been incremented during transfer does not return to the initial value. In block transfer mode too, the address is incremented when one data unit is transferred. However, the address that has been incremented during a block transfer recycles returns to the initial value when the block transfer is completed. SxIN/DxIN = "11": address incremented without initialization The address is incremented by an amount equal to the data size set by DATSIZEx when one data transfer is completed. The address that has been incremented during transfer does not return to the initial value. B-V HSDMA S1C33L03 FUNCTION PART EPSON B-V-2-5 V DMA BLOCK: HSDMA (High-Speed DMA) Setting the Registers in Single-Address Mode Make sure that the HSDMA channel is disabled (HSx_EN = "0") before seffing the control information. Address mode The address mode select bit DUALMx should be set to "0" (single-address mode). This bit is set to "0" at initial reset. Transfer mode A transfer mode should be set using the DxMOD[1:0] bits. * Single transfer mode (DxMOD = "00", default) * Successive transfer mode (DxMOD = "01") * Block transfer mode (DxMOD = "10") Refer to the explanation in "Setting the Registers in Dual-Address Mode". Direction of transfer The direction of data transfer should be set using DxDIR. D0DIR: Ch. 0 transfer direction control (DE) / HSDMA Ch. 0 control register (0x48222) D1DIR: Ch. 1 transfer direction control (DE) / HSDMA Ch. 1 control register (0x48232) D2DIR: Ch. 2 transfer direction control (DE) / HSDMA Ch. 2 control register (0x48242) D3DIR: Ch. 3 transfer direction control (DE) / HSDMA Ch. 3 control register (0x48252) Memory write operations (data transfer from I/O device to memory) are specified by writing "1" and memory read operations (data transfer from memory to I/O device) are specified by writing "0". Transfer data size The DATSIZEx bit is used to set the unit size of data to be transferred. A half-word size (16 bits) is assumed if this bit is "1" and a byte size (8 bits) is assumed if this bit is "0" (default). Block length When using block transfer mode (DxMOD = "10"), the data block length (in units of DATSIZEx) should be set using the BLKLENx[7:0] bits. In single transfer and successive transfer modes, BLKLENx[7:0] is used as the bits7-0 of the transfer counter. Transfer counter Block transfer mode In block transfer mode, up to 16 bits of transfer count can be specified using TCx_L[7:0] and TCx_H[7:0]. Single transfer and successive transfer modes In single transfer and successive transfer modes, up to 24 bits of transfer count can be specified using BLKLENx[7:0], TCx_L[7:0] and TCx_H[7:0]. Memory address In single-address mode, SxADRL[15:0] and SxADRH[11:0] are used to specify a memory address. S0ADRL[15:0]: Ch. 0 memory address [15:0] (D[F:0]) / Ch. 0 low-order source address set-up register (0x48224) S0ADRH[11:0]: Ch. 0 memory address [27:16] (D[B:0]) / Ch. 0 high-order source address set-up register (0x48226) S1ADRL[15:0]: Ch. 1 memory address [15:0] (D[F:0]) / Ch. 1 low-order source address set-up register (0x48234) S1ADRH[11:0]: Ch. 1 memory address [27:16] (D[B:0]) / Ch. 1 high-order source address set-up register (0x48236) S2ADRL[15:0]: Ch. 2 memory address [15:0] (D[F:0]) / Ch. 2 low-order source address set-up register (0x48244) S2ADRH[11:0]: Ch. 2 memory address [27:16] (D[B:0]) / Ch. 2 high-order source address set-up register (0x48246) S3ADRL[15:0]: Ch. 3 memory address [15:0] (D[F:0]) / Ch. 3 low-order source address set-up register (0x48254) S3ADRH[11:0]: Ch. 3 memory address [27:16] (D[B:0]) / Ch. 3 high-order source address set-up register (0x48256) B-V-2-6 EPSON S1C33L03 FUNCTION PART V DMA BLOCK: HSDMA (High-Speed DMA) A-1 In single-address mode, data transfer is performed between the memory connected to the system interface and an external I/O device. The I/O device is accessed directly by the #DMAACKx signal, so it is unnecessary to specify an address. DxADRL[15:0] and DxADRH[11:0] are not used in single-address mode. Address increment/decrement control The memory addresses can be incremented or decremented when one data transfer is completed. SxIN[1:0] is used to set this function. S0IN[1:0]: Ch. 0 memory address control (D[D:C]) / Ch. 0 high-order source address set-up register (0x48226) S1IN[1:0]: Ch. 1 memory address control (D[D:C]) / Ch. 1 high-order source address set-up register (0x48236) S2IN[1:0]: Ch. 2 memory address control (D[D:C]) / Ch. 2 high-order source address set-up register (0x48246) S3IN[1:0]: Ch. 3 memory address control (D[D:C]) / Ch. 3 high-order source address set-up register (0x48256) SxIN = "00": address fixed (default) SxIN = "01": address decremented without initialization SxIN = "10": address incremented with initialization SxIN = "11": address incremented without initialization Refer to the explanation in "Setting the Registers in Dual-Address Mode". DxIN[1:0] is not used in single-address mode. Enabling/Disabling DMA Transfer The HSDMA transfer is enabled by writing "1" to the enable bit HSx_EN. HS0_EN: Ch. 0 enable (D0) / Ch. 0 enable register (0x4822C) HS1_EN: Ch. 1 enable (D0) / Ch. 1 enable register (0x4823C) HS2_EN: Ch. 2 enable (D0) / Ch. 2 enable register (0x4824C) HS3_EN: Ch. 3 enable (D0) / Ch. 3 enable register (0x4825C) However, the control information must always be set correctly before enabling a DMA transfer. Note that the control information cannot be set when HSx_EN = "1". When HSx_EN is set to "0", HSDMA requests are no longer accepted. When a DMA transfer is completed (transfer counter = 0), HSx_EN is reset to "0" to disable the following trigger inputs. B-V HSDMA S1C33L03 FUNCTION PART EPSON B-V-2-7 V DMA BLOCK: HSDMA (High-Speed DMA) Trigger Factor A HSDMA tigger factor can be selected from among 13 types using the HSDMA trigger set-up register for each channel. This function is supported by the interrupt controller. HSD0S[3:0]: Ch. 0 trigger set-up (D[3:0]) / HSDMA Ch. 0/1 trigger set-up register (0x40298) HSD1S[3:0]: Ch. 1 trigger set-up (D[7:4]) / HSDMA Ch. 0/1 trigger set-up register (0x40298) HSD2S[3:0]: Ch. 2 trigger set-up (D[3:0]) / HSDMA Ch. 2/3 trigger set-up register (0x40299) HSD3S[3:0]: Ch. 3 trigger set-up (D[7:4]) / HSDMA Ch. 2/3 trigger set-up register (0x40299) Table 2.2 shows the setting value and the corresponding trigger factor. Table 2.2 HSDMA Trigger Factor Value Ch.0 trigger factor Ch.1 trigger factor Ch.2 trigger factor Ch.3 trigger factor 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 Software trigger K50 port input (falling edge) K50 port input (rising edge) Port 0 input Port 4 input 8-bit timer 0 underflow 16-bit timer 0 compare B 16-bit timer 0 compare A 16-bit timer 4 compare B 16-bit timer 4 compare A Serial I/F Ch.0 Rx buffer full Serial I/F Ch.0 Tx buffer empty A/D conversion completion Software trigger K51 port input (falling edge) K51 port input (rising edge) Port 1 input Port 5 input 8-bit timer 1 underflow 16-bit timer 1 compare B 16-bit timer 1 compare A 16-bit timer 5 compare B 16-bit timer 5 compare A Serial I/F Ch.1 Rx buffer full Serial I/F Ch.1 Tx buffer empty A/D conversion completion Software trigger K53 port input (falling edge) K53 port input (rising edge) Port 2 input Port 6 input 8-bit timer 2 underflow 16-bit timer 2 compare B 16-bit timer 2 compare A 16-bit timer 4 compare B 16-bit timer 4 compare A Serial I/F Ch.0 Rx buffer full Serial I/F Ch.0 Tx buffer empty A/D conversion completion Software trigger K54 port input (falling edge) K54 port input (rising edge) Port 3 input Port 7 input 8-bit timer 3 underflow 16-bit timer 3 compare B 16-bit timer 3 compare A 16-bit timer 5 compare B 16-bit timer 5 compare A Serial I/F Ch.1 Rx buffer full Serial I/F Ch.1 Tx buffer empty A/D conversion completion By selecting an interrupt factor with the HSDMA trigger set-up register, the HSDMA channel is invoked when the selected interrupt factor occurs. The interrupt control bits (interrupt factor flag, interrupt enable register, IDMA request register, interrupt priority register) do not affect this invocation. The interrupt factor that invokes HSDMA sets the interrupt factor flag. and HSDMA does not reset the flag. Consequently, when the DMA transfer is completed (even if the transfer counter is not 0), an interrupt request to the CPU will be generated if the interrupt has been enabled. To generate an interrupt only when the transfer counter reaches 0, disable the interrupt by the interrupt factor that invokes HSDMA and use the HSDMA transfer completion interrupt. When software trigger is selected, the HSDMA channel can be invoked by writing "1" to the HSTx bit. HST0: Ch. 0 software trigger (D0) / HSDMA software trigger register (0x4029A) HST1: Ch. 1 software trigger (D1) / HSDMA software trigger register (0x4029A) HST2: Ch. 2 software trigger (D2) / HSDMA software trigger register (0x4029A) HST3: Ch. 3 software trigger (D3) / HSDMA software trigger register (0x4029A) When the selected trigger factor occurs, the trigger flag is set to "1" to invoke the HSDMA channel. The HSDMA starts a DMA transfer if it has been enabled and the trigger flag is cleared by the hardware at the same time. This makes it possible to queue the HSDMA triggers that have been generated. The trigger flag can be read and cleared using the HSx_TF bit. HS0_TF: Ch. 0 trigger flag status/clear (D0) / Ch. 0 trigger flag register (0x4822E) HS1_TF: Ch. 1 trigger flag status/clear (D0) / Ch. 1 trigger flag register (0x4823E) HS2_TF: Ch. 2 trigger flag status/clear (D0) / Ch. 2 trigger flag register (0x4824E) HS3_TF: Ch. 3 trigger flag status/clear (D0) / Ch. 3 trigger flag register (0x4825E) By writing "1" to this bit, the set trigger flag can be cleared if the DMA transfer has not been started. When this bit is read, "1" indicates that the flag is set and "0" indicates that the flag is cleared. B-V-2-8 EPSON S1C33L03 FUNCTION PART V DMA BLOCK: HSDMA (High-Speed DMA) A-1 Operation of HSDMA An HSDMA channel starts data transfer by the selected trigger factor. Make sure that transfer conditions and a trigger factor are set and the HSDMA channel is enabled before starting a DMA transfer. Operation in Dual-Address Mode In dual-address mode, both the source and destination addresses are accessed according to the bus condition set by the BCU. HSDMA has three transfer modes, in each of which data transfer operates differently. The following describes the operation of HSDMA in each transfer mode. Single transfer mode The channel for which DxMOD in control information is set to "00" operates in single transfer mode. In this mode, a transfer operation invoked by one trigger is completed after transferring one data unit of the size set by DATSIZEx. If a data transfer needs to be performed a number of times as set by the transfer counter, an equal number of triggers are required. The operation of HSDMA in single transfer mode is shown by the flow chart in Figure 2.3. START Clear trigger flag HSx_TF to accept next trigger Data read from source (1 byte or 1 half word) Data write to destination (1 byte or 1 half word) Increment/decrement address : according to SxIN/DxIN settings Transfer counter - 1 Transfer counter = 0 N Y Clear HSDMA enable bit HSx_EN Set interrupt factor flag FHDMx END B-V Figure 2.3 Operation Flow in Single Transfer Mode (1) When a trigger is accepted, the trigger flag HSx_TF is cleared and then data of the size set in the control information is read from the source address. (2) The read data is written to the destination address. (3) The addresses are incremented or decremented according to the SxIN/DxIN settings. (4) The transfer counter is decremented. (5) The HSDMA enable bit HSx_EN is cleared and HSDMA interrupt factor flag in ITC is set when the transfer counter reaches 0 (when DINTENx = "1"). S1C33L03 FUNCTION PART EPSON B-V-2-9 HSDMA V DMA BLOCK: HSDMA (High-Speed DMA) Successive transfer mode The channel for which DxMOD in control information is set to "01" operates in successive transfer mode. In this mode, a data transfer is performed by one trigger a number of times as set by the transfer counter. The transfer counter is decremented to "0" by one transfer executed. The operation of HSDMA in successive transfer mode is shown by the flow chart in Figure 2.4. START Clear trigger flag HSx_TF to accept next trigger Data read from source (1 byte or 1 half word) Data write to destination (1 byte or 1 half word) Increments/decrements address : according to SxIN/DxIN settings Transfer counter - 1 N Transfer counter = 0 Y Clear HSDMA enable bit HSx_EN Set interrupt factor flag FHDMx END Figure 2.4 Operation Flow in Successive Transfer Mode (1) When a trigger is accepted, the trigger flag HSx_TF is cleared and then data of the size set in the control information is read from the source address. (2) The read data is written to the destination address. (3) The addresses are incremented or decremented according to the SxIN/DxIN settings. (4) The transfer counter is decremented. (5) Steps (1) to (4) are repeated until the transfer counter reaches 0. (6) The HSDMA enable bit HSx_EN is cleared and HSDMA interrupt factor flag in ITC is set when the transfer counter reaches 0 (when DINTENx = "1"). B-V-2-10 EPSON S1C33L03 FUNCTION PART V DMA BLOCK: HSDMA (High-Speed DMA) A-1 Block transfer mode The channel for which DxMOD in control information is set to "10" operates in block transfer mode. In this mode, a transfer operation invoked by one trigger is completed after transferring one block of data of the size set by BLKLENx. If a block transfer needs to be performed a number of times as set by the transfer counter, an equal number of triggers are required. The operation of HSDMA in block transfer mode is shown by the flow chart in Figure 2.5. START Clear trigger flag HSx_TF to accept next trigger Data read from source (1 byte or 1 half word) Data write to destination (1 byte or 1 half word) Increments/decrements address : according to SxIN/DxIN settings Block size - 1 N Block size = 0 1-block transfer Y Restores initial values to block size and address : according to SxIN/DxIN settings Transfer counter - 1 Transfer counter = 0 N Y Clear HSDMA enable bit HSx_EN Set interrupt factor flag FHDMx END Figure 2.5 Operation Flow in Block Transfer Mode (1) When a trigger is accepted, the trigger flag HSx_TF is cleared and then data of the size set in the control information is read from the source address. (2) The read data is written to the destination address. (3) The address is incremented or decremented and BLKLENx is decremented. (4) Steps (1) to (3) are repeated until BLKLEN reaches 0. (5) If SxIN or DxIN is "10", the address is recycled to the initial value. (6) The transfer counter is decremented. (7) The HSDMA enable bit HSx_EN is cleared and HSDMA interrupt factor flag in ITC is set when the transfer counter reaches 0 (when DINTENx = "1"). S1C33L03 FUNCTION PART EPSON B-V-2-11 B-V HSDMA V DMA BLOCK: HSDMA (High-Speed DMA) Operation in Single-Address Mode The operation of each transfer mode is almost the same as that of dual-address mode (see the previous section). However, data read/write operation is performed simultaneously in single-address mode. The following explains the data transfer operation different from dual-address mode. #DMAACKx signal output and bus operation When the HSDMA circuit accepts the DMA request, it outputs a low-level pulse from the #DMAACKx pin and starts bus operation for the memory at the same time. The contents of this bus operation are as follows: * Data transfer from I/O device to memory The address that has been set in the memory address register is output to the address bus. A write operation is performed under the interface conditions set on the area to which the memory at the destination of transfer belongs. The data bus is left floating. The external I/O device outputs the transfer data onto the data bus using the #DMAACKx signal as the read signal. The memory takes in this data using the write signal. * Data transfer from memory to an I/O device The address that has been set in the memory address register is output to the address bus. A read operation is performed under the interface conditions set on the area to which the memory at the source of transfer belongs. The memory outputs the transfer data onto the data bus using the read signal. The external I/O device takes in the data from the data bus using the #DMAACKx signal as the write signal. If the transfer data size is 16 bits and the I/O device is an 8-bit device, two bus operations are performed. Otherwise, transfer is completed in one bus operation. #DMAENDx signal output When the transfer counter reaches 0, the end-of-transfer signal is output from the #DMAENDx pin indicating that a specified number of transfers has been completed. At the same time, the interrupt factor for the completion of HSDMA is generated. B-V-2-12 EPSON S1C33L03 FUNCTION PART V DMA BLOCK: HSDMA (High-Speed DMA) A-1 Timing Chart Dual-address mode (1) SRAM Example: When 2 (RD)/1 (WR) wait cycles are inserted Read cycle Write cycle source address destination address BCLK A[23:0] #CE(src) ;;; ;;; #CE(dst) #RD #WRH/#WRL #DMAEND Figure 2.6 #DMAEND Signal Output Timing (SRAM) (2) DRAM Example: Page mode, RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle Read cycle Write cycle BCLK A[11:0] ROW #RASx COL #1 COL #2 ;;;; ;;;; ROW COL #1 COL #2 ;;;; ;;;; #HCAS/ #LCAS #RD #WR #DMAEND Figure 2.7 #DMAEND Signal Output Timing (DRAM) B-V HSDMA S1C33L03 FUNCTION PART EPSON B-V-2-13 V DMA BLOCK: HSDMA (High-Speed DMA) Single-address mode (1) SRAM Example: When 2 (RD)/1 (WR) wait cycles are inserted BCLK ;;; ;;; addr A[23:0] #CExx #RD #WRH/#WRL #DMAACK #DMAEND Figure 2.8 #DMAACK/#DMAEND Signal Output Timing (SRAM) (2) Burst ROM Example: When 4-consecutive-burst and 2-wait cycles are set during the first access BCLK addr[23:2] A[23:2] "00" A[1:0] #CE10(9) D[15:0] #RD "01" "10" "11" ;;; ;;; ;;; ;;; ;;;;;;;;;;;;;; ;;;;;;;;;;;;;; ;;;; ;;;; ;;;; ;;;; ;;;; ;;;; #DMAACK #DMAEND Figure 2.9 #DMAACK/#DMAEND Signal Output Timing (Burst ROM) (3) DRAM Example: Page mode, RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle BCLK A[11:0] ROW COL #1 COL #2 #RASx ;;;;;;; ;;;;;;; #HCAS/ #LCAS #RD #WR #DMAACK #DMAEND Figure 2.10 #DMAACK/#DMAEND Signal Output Timing (DRAM) Note: The single-address transfer method does not allow data transfer to/from the SDRAM. B-V-2-14 EPSON S1C33L03 FUNCTION PART V DMA BLOCK: HSDMA (High-Speed DMA) A-1 Interrupt Function of HSDMA The DMA controller can generate an interrupt when the transfer counter in each HSDMA channel reaches 0. Furthermore, channels 0 and 1 can invoke IDMA using their interrupt factor. Control registers of the interrupt controller Table 2.3 shows the control registers of the interrupt controller that are provided for each channel. Table 2.3 Control Registers of Interrupt Controller Channel Ch. 0 Ch. 1 Ch. 2 Ch. 3 Interrupt factor flag FHDM0(D0/0x40281) FHDM1(D1/0x40281) FHDM2(D2/0x40281) FHDM3(D3/0x40281) Interrupt enable register EHDM0(D0/0x40271) EHDM1(D1/0x40271) EHDM2(D2/0x40271) EHDM3(D3/0x40271) Interrupt priority register PHSD0L[2:0](D[2:0]/0x40263) PHSD1L[2:0](D[6:4]/0x40263) PHSD2L[2:0](D[2:0]/0x40264) PHSD3L[2:0](D[6:4]/0x40264) The HSDMA controller sets the HSDMA interrupt factor flag to "1" when the transfer counter reaches 0 after completing a series of HSDMA transfers. If the corresponding bit of the interrupt enable register is set to "1" at this time, an interrupt request is generated. Interrupts can be disabled by leaving the interrupt enable register bit set to "0". The HSDMA interrupt factor flag is always set to "1" when the data transfer in each channel is completed no matter what value the interrupt enable register bit is set to. (This is true even when it is set to "0".) The interrupt priority register sets an interrupt priority level (0 to 7). An interrupt request to the CPU is accepted only when there is no other interrupt request of higher priority. Furthermore, it is only when the PSR's IE bit = "1" (interrupt enable) and the set value of IL is smaller than the HSDMA interrupt level which is set in the interrupt priority register that the CPU actually accepts a HSDMA interrupt. For details about the interrupt control register and for the device operation when an interrupt occurs, refer to "ITC (Interrupt Controller)". B-V HSDMA S1C33L03 FUNCTION PART EPSON B-V-2-15 V DMA BLOCK: HSDMA (High-Speed DMA) Intelligent DMA Intelligent DMA (IDMA) can be invoked by the end-of-transfer interrupt factor of channels 0 and 1 of HSDMA. The following shows the IDMA channels set in HSDMA: IDMA channel Channel 0 end-of-transfer interrupt: 0x05 Channel 1 end-of-transfer interrupt: 0x06 Before IDMA can be invoked, the corresponding bits of the IDMA request and IDMA enable registers must be set to "1". Settings of transfer conditions on the IDMA side are also required. Table 2.4 Control Bits for IDMA Transfer Channel Ch. 0 Ch. 1 IDMA request bit RHDM0(D4/0x40290) RHDM1(D5/0x40290) IDMA enable bit DEHDM0(D4/0x40294) DEHDM1(D5/0x40294) If the IDMA request and enable bits are set to "1", IDMA is invoked through generation of an interrupt factor. No interrupt request is generated at that point. An interrupt request is generated after the DMA transfer is completed. The registers can also be set so as not to generate an interrupt, with only a DMA transfer performed. For details on IDMA transfers and interrupt control upon completion of IDMA transfer, refer to "IDMA (Intelligent DMA)". Trap vector The trap vector addresses for interrupt factors in each channel are set by default as follows: Channel 0 end-of-transfer interrupt: Channel 1 end-of-transfer interrupt: Channel 2 end-of-transfer interrupt: Channel 3 end-of-transfer interrupt: 0x0C00058 0x0C0005C 0x0C00060 0x0C00064 Note that the trap table base address can be modified using the TTBR registers (0x48134 to 0x48137). B-V-2-16 EPSON S1C33L03 FUNCTION PART V DMA BLOCK: HSDMA (High-Speed DMA) A-1 I/O Memory of HSDMA Table 2.5 shows the control bits of HSDMA. Table 2.5 Control Bits of HSDMA Register name Address Bit High-speed 0040263 DMA Ch.0/1 (B) interrupt priority register D7 D6 D5 D4 D3 D2 D1 D0 - PHSD1L2 PHSD1L1 PHSD1L0 - PHSD0L2 PHSD0L1 PHSD0L0 reserved High-speed DMA Ch.1 interrupt level - 0 to 7 reserved High-speed DMA Ch.0 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - PHSD3L2 PHSD3L1 PHSD3L0 - PHSD2L2 PHSD2L1 PHSD2L0 reserved High-speed DMA Ch.3 interrupt level - 0 to 7 reserved High-speed DMA Ch.2 interrupt level - 0 to 7 High-speed 0040264 DMA Ch.2/3 (B) interrupt priority register Name Function DMA interrupt 0040271 enable register (B) D7-5 D4 D3 D2 D1 D0 - EIDMA EHDM3 EHDM2 EHDM1 EHDM0 reserved IDMA High-speed DMA Ch.3 High-speed DMA Ch.2 High-speed DMA Ch.1 High-speed DMA Ch.0 DMA interrupt factor flag register 0040281 (B) D7-5 D4 D3 D2 D1 D0 - FIDMA FHDM3 FHDM2 FHDM1 FHDM0 reserved IDMA High-speed DMA Ch.3 High-speed DMA Ch.2 High-speed DMA Ch.1 High-speed DMA Ch.0 Port input 0-3, high-speed DMA Ch. 0/1, 16-bit timer 0 IDMA request register 0040290 (B) D7 D6 D5 D4 D3 D2 D1 D0 R16TC0 R16TU0 RHDM1 RHDM0 RP3 RP2 RP1 RP0 Port input 0-3, high-speed DMA Ch. 0/1, 16-bit timer 0 IDMA enable register 0040294 (B) D7 D6 D5 D4 D3 D2 D1 D0 DE16TC0 DE16TU0 DEHDM1 DEHDM0 DEP3 DEP2 DEP1 DEP0 Setting - 1 Enabled 0 Disabled - Init. R/W Remarks - X X X - X X X - 0 when being read. R/W - X X X - X X X - 0 when being read. R/W - 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W - X X X X X - 0 when being read. R/W R/W R/W R/W R/W - 0 when being read. R/W - 0 when being read. R/W 1 Factor is generated 0 No factor is generated 16-bit timer 0 comparison A 16-bit timer 0 comparison B High-speed DMA Ch.1 High-speed DMA Ch.0 Port input 3 Port input 2 Port input 1 Port input 0 1 IDMA request 0 Interrupt request 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 16-bit timer 0 comparison A 16-bit timer 0 comparison B High-speed DMA Ch.1 High-speed DMA Ch.0 Port input 3 Port input 2 Port input 1 Port input 0 1 IDMA enabled 0 IDMA disabled 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W B-V HSDMA S1C33L03 FUNCTION PART EPSON B-V-2-17 V DMA BLOCK: HSDMA (High-Speed DMA) Register name Address Bit Name High-speed DMA Ch.0/1 trigger set-up register D7 D6 D5 D4 HSD1S3 HSD1S2 HSD1S1 HSD1S0 High-speed DMA Ch.1 trigger set-up D3 D2 D1 D0 HSD0S3 HSD0S2 HSD0S1 HSD0S0 High-speed DMA Ch.0 trigger set-up D7 D6 D5 D4 HSD3S3 HSD3S2 HSD3S1 HSD3S0 High-speed DMA Ch.3 trigger set-up D3 D2 D1 D0 HSD2S3 HSD2S2 HSD2S1 HSD2S0 High-speed DMA Ch.2 trigger set-up High-speed DMA Ch.2/3 trigger set-up register 0040298 (B) 0040299 (B) Function High-speed 004029A D7-4 - DMA software (B) D3 HST3 trigger register D2 HST2 D1 HST1 D0 HST0 reserved HSDMA Ch.3 software trigger HSDMA Ch.2 software trigger HSDMA Ch.1 software trigger HSDMA Ch.0 software trigger K5 function select register reserved K54 function selection K53 function selection K52 function selection K51 function selection K50 function selection B-V-2-18 00402C0 D7-5 - (B) D4 CFK54 D3 CFK53 D2 CFK52 D1 CFK51 D0 CFK50 EPSON Setting Init. R/W 0 1 2 3 4 5 6 7 8 9 A B C 0 1 2 3 4 5 6 7 8 9 A B C Software trigger K51 input (falling edge) K51 input (rising edge) Port 1 input Port 5 input 8-bit timer Ch.1 underflow 16-bit timer Ch.1 compare B 16-bit timer Ch.1 compare A 16-bit timer Ch.5 compare B 16-bit timer Ch.5 compare A SI/F Ch.1 Rx buffer full SI/F Ch.1 Tx buffer empty A/D conversion completion Software trigger K50 input (falling edge) K50 input (rising edge) Port 0 input Port 4 input 8-bit timer Ch.0 underflow 16-bit timer Ch.0 compare B 16-bit timer Ch.0 compare A 16-bit timer Ch.4 compare B 16-bit timer Ch.4 compare A SI/F Ch.0 Rx buffer full SI/F Ch.0 Tx buffer empty A/D conversion completion 0 0 0 0 R/W 0 0 0 0 R/W 0 1 2 3 4 5 6 7 8 9 A B C 0 1 2 3 4 5 6 7 8 9 A B C Software trigger K54 input (falling edge) K54 input (rising edge) Port 3 input Port 7 input 8-bit timer Ch.3 underflow 16-bit timer Ch.3 compare B 16-bit timer Ch.3 compare A 16-bit timer Ch.5 compare B 16-bit timer Ch.5 compare A SI/F Ch.1 Rx buffer full SI/F Ch.1 Tx buffer empty A/D conversion completion Software trigger K53 input (falling edge) K53 input (rising edge) Port 2 input Port 6 input 8-bit timer Ch.2 underflow 16-bit timer Ch.2 compare B 16-bit timer Ch.2 compare A 16-bit timer Ch.4 compare B 16-bit timer Ch.4 compare A SI/F Ch.0 Rx buffer full SI/F Ch.0 Tx buffer empty A/D conversion completion 0 0 0 0 R/W 0 0 0 0 R/W - 0 0 0 0 - W W W W - 1 Trigger 0 Invalid - 1 1 1 1 1 #DMAREQ3 #DMAREQ2 #ADTRG #DMAREQ1 #DMAREQ0 0 0 0 0 0 K54 K53 K52 K51 K50 - 0 0 0 0 0 Remarks 0 when being read. - 0 when being read. R/W R/W R/W R/W R/W S1C33L03 FUNCTION PART V DMA BLOCK: HSDMA (High-Speed DMA) A-1 Register name Address Bit P1 function select register D7 D6 - CFP16 reserved P16 function selection D5 CFP15 P15 function selection D4 CFP14 P14 function selection D3 CFP13 P13 function selection D2 CFP12 P12 function selection D1 CFP11 P11 function selection D0 CFP10 P10 function selection D7 D6 D5 D4 D3 D2 D1 D0 - IOC16 IOC15 IOC14 IOC13 IOC12 IOC11 IOC10 reserved P16 I/O control P15 I/O control P14 I/O control P13 I/O control P12 I/O control P11 I/O control P10 I/O control P1 I/O control register 00402D4 (B) 00402D6 (B) Name P3 function 00402DC D7-6 - select register (B) D5 CFP35 D4 CFP34 Port function extension register High-speed DMA Ch.0 transfer counter register 00402DF (B) 0048220 (HW) Function Setting Init. R/W - 1 EXCL5 0 P16 #DMAEND1 1 EXCL4 0 P15 #DMAEND0 1 FOSC1 0 P14 - 0 - 0 when being read. R/W 0 R/W 0 1 EXCL3 T8UF3 1 EXCL2 T8UF2 1 EXCL1 T8UF1 1 EXCL0 T8UF0 0 P13 0 R/W Extended functions (0x402DF) R/W 0 P12 0 R/W 0 P11 0 R/W 0 P10 0 R/W - 0 0 0 0 0 0 0 - R/W R/W R/W R/W R/W R/W R/W P35 P34 - 0 0 - 0 when being read. R/W R/W P33 P32 P31 P30 0 0 0 0 R/W R/W R/W Ext. func.(0x402DF) R/W 0 0 0 0 0 0 1 R/W R/W R/W R/W R/W R/W R/W 1 R/W X X X X X X X X X X X X X X X X R/W - 1 Output reserved P35 function selection P34 function selection 0 Input - 1 #BUSACK 0 1 #BUSREQ 0 #CE6 1 #DMAACK1 0 1 #DMAACK0 0 1 #BUSGET 0 1 #WAIT 0 #CE4/#CE5 D3 D2 D1 D0 CFP33 CFP32 CFP31 CFP30 P33 function selection P32 function selection P31 function selection P30 function selection D7 D6 D5 D4 D3 D2 D1 CFEX7 CFEX6 CFEX5 CFEX4 CFEX3 CFEX2 CFEX1 P07 port extended function P06 port extended function P05 port extended function P04 port extended function P31 port extended function P21 port extended function P10, P11, P13 port extended function D0 CFEX0 P12, P14 port extended function DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC0_L7 TC0_L6 TC0_L5 TC0_L4 TC0_L3 TC0_L2 TC0_L1 TC0_L0 BLKLEN07 BLKLEN06 BLKLEN05 BLKLEN04 BLKLEN03 BLKLEN02 BLKLEN01 BLKLEN00 Ch.0 transfer counter[7:0] (block transfer mode) Ch.0 transfer counter[15:8] (single/successive transfer mode) Ch.0 block length (block transfer mode) Ch.0 transfer counter[7:0] (single/successive transfer mode) Remarks 1 1 1 1 1 1 1 #DMAEND3 #DMAACK3 #DMAEND2 #DMAACK2 #GARD #GAAS DST0 DST1 DPC0 1 DST2 DCLK 0 0 0 0 0 0 0 P07, etc. P06, etc. P05, etc. P04, etc. P31, etc. P21, etc. P10, etc. P11, etc. P13, etc. 0 P12, etc. P14, etc. 0 when being read. This register indicates the values of the I/O control signals of the ports when it is read. (See detailed explanation.) R/W B-V HSDMA S1C33L03 FUNCTION PART EPSON B-V-2-19 V DMA BLOCK: HSDMA (High-Speed DMA) Register name Address Bit Name High-speed 0048222 DMA Ch.0 (HW) control register DF DE DUALM0 D0DIR DD-8 D7 D6 D5 D4 D3 D2 D1 D0 - TC0_H7 TC0_H6 TC0_H5 TC0_H4 TC0_H3 TC0_H2 TC0_H1 TC0_H0 Note: D) Dual address mode S) Single address mode High-speed 0048224 DMA Ch.0 (HW) low-order source address set-up register Note: D) Dual address mode S) Single address mode High-speed 0048226 DMA Ch.0 (HW) high-order source address set-up register Note: D) Dual address mode S) Single address mode High-speed 0048228 DMA Ch.0 (HW) low-order destination address set-up register Note: D) Dual address mode S) Single address mode B-V-2-20 Function Ch.0 address mode selection D) Invalid S) Ch.0 transfer direction control reserved Ch.0 transfer counter[15:8] (block transfer mode) Setting 1 Dual addr 0 Single addr - 1 Memory WR 0 Memory RD - Ch.0 transfer counter[23:16] (single/successive transfer mode) Init. R/W R/W - R/W - Undefined in read. R/W X X X X X X X X X X X X X X X X R/W - 0 0 0 - R/W R/W DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S0ADRL15 D) Ch.0 source address[15:0] S0ADRL14 S) Ch.0 memory address[15:0] S0ADRL13 S0ADRL12 S0ADRL11 S0ADRL10 S0ADRL9 S0ADRL8 S0ADRL7 S0ADRL6 S0ADRL5 S0ADRL4 S0ADRL3 S0ADRL2 S0ADRL1 S0ADRL0 DF DE DD DC - DATSIZE0 S0IN1 S0IN0 DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S0ADRH11 D) Ch.0 source address[27:16] S0ADRH10 S) Ch.0 memory address[27:16] S0ADRH9 S0ADRH8 S0ADRH7 S0ADRH6 S0ADRH5 S0ADRH4 S0ADRH3 S0ADRH2 S0ADRH1 S0ADRH0 X X X X X X X X X X X X R/W DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D0ADRL15 D) Ch.0 destination address[15:0] D0ADRL14 S) Invalid D0ADRL13 D0ADRL12 D0ADRL11 D0ADRL10 D0ADRL9 D0ADRL8 D0ADRL7 D0ADRL6 D0ADRL5 D0ADRL4 D0ADRL3 D0ADRL2 D0ADRL1 D0ADRL0 X X X X X X X X X X X X X X X X R/W reserved Ch.0 transfer data size D) Ch.0 source address control S) Ch.0 memory address control EPSON - 1 Half word S0IN[1:0] 1 1 1 0 0 1 0 0 0 Byte Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed Remarks 0 - 0 - X X X X X X X X S1C33L03 FUNCTION PART V DMA BLOCK: HSDMA (High-Speed DMA) A-1 Register name Address Bit Name High-speed 004822A DMA Ch.0 (HW) high-order destination address set-up register DF DE D0MOD1 D0MOD0 Ch.0 transfer mode DD DC D0IN1 D0IN0 D) Ch.0 destination address control S) Invalid DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D0ADRH11 D) Ch.0 destination D0ADRH10 address[27:16] D0ADRH9 S) Invalid D0ADRH8 D0ADRH7 D0ADRH6 D0ADRH5 D0ADRH4 D0ADRH3 D0ADRH2 D0ADRH1 D0ADRH0 Note: D) Dual address mode S) Single address mode Function High-speed 004822C DF-1 - DMA Ch.0 (HW) D0 HS0_EN enable register reserved High-speed DMA Ch.0 trigger flag register 004822E DF-1 - (HW) D0 HS0_TF reserved High-speed DMA Ch.1 transfer counter register 0048230 (HW) High-speed 0048232 DMA Ch.1 (HW) control register Note: D) Dual address mode S) Single address mode Setting D0MOD[1:0] 1 1 1 0 0 1 0 0 D0IN[1:0] 1 1 1 0 0 1 0 0 Mode Invalid Block Successive Single Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed - Ch.0 enable 1 Enable 0 Disable - Ch.0 trigger flag clear (writing) Ch.0 trigger flag status (reading) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC1_L7 TC1_L6 TC1_L5 TC1_L4 TC1_L3 TC1_L2 TC1_L1 TC1_L0 BLKLEN17 BLKLEN16 BLKLEN15 BLKLEN14 BLKLEN13 BLKLEN12 BLKLEN11 BLKLEN10 Ch.1 transfer counter[7:0] (block transfer mode) DF DE DUALM1 D1DIR DD-8 D7 D6 D5 D4 D3 D2 D1 D0 - TC1_H7 TC1_H6 TC1_H5 TC1_H4 TC1_H3 TC1_H2 TC1_H1 TC1_H0 Ch.1 address mode selection D) Invalid S) Ch.1 transfer direction control reserved Ch.1 transfer counter[15:8] (block transfer mode) 1 Clear 1 Set 0 No operation 0 Cleared Ch.1 transfer counter[15:8] (single/successive transfer mode) Ch.1 block length (block transfer mode) Ch.1 transfer counter[7:0] (single/successive transfer mode) Ch.1 transfer counter[23:16] (single/successive transfer mode) 1 Dual addr 0 Single addr - 1 Memory WR 0 Memory RD - Init. R/W Remarks 0 0 R/W 0 0 R/W X X X X X X X X X X X X R/W - - 0 R/W - - 0 R/W X X X X X X X X X X X X X X X X R/W 0 - 0 - X X X X X X X X R/W - R/W - Undefined in read. R/W Undefined in read. Undefined in read. R/W B-V HSDMA S1C33L03 FUNCTION PART EPSON B-V-2-21 V DMA BLOCK: HSDMA (High-Speed DMA) Register name Address Bit High-speed 0048234 DMA Ch.1 (HW) low-order source address set-up register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1ADRL15 D) Ch.1 source address[15:0] S1ADRL14 S) Ch.1 memory address[15:0] S1ADRL13 S1ADRL12 S1ADRL11 S1ADRL10 S1ADRL9 S1ADRL8 S1ADRL7 S1ADRL6 S1ADRL5 S1ADRL4 S1ADRL3 S1ADRL2 S1ADRL1 S1ADRL0 DF DE DD DC - DATSIZE1 S1IN1 S1IN0 DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Note: D) Dual address mode S) Single address mode High-speed 0048236 DMA Ch.1 (HW) high-order source address set-up register Note: D) Dual address mode S) Single address mode High-speed 0048238 DMA Ch.1 (HW) low-order destination address set-up register Note: D) Dual address mode S) Single address mode B-V-2-22 Name Function Setting Init. R/W X X X X X X X X X X X X X X X X R/W - 0 0 0 - R/W R/W S1ADRH11 D) Ch.1 source address[27:16] S1ADRH10 S) Ch.1 memory address[27:16] S1ADRH9 S1ADRH8 S1ADRH7 S1ADRH6 S1ADRH5 S1ADRH4 S1ADRH3 S1ADRH2 S1ADRH1 S1ADRH0 X X X X X X X X X X X X R/W D1ADRL15 D) Ch.1 destination address[15:0] D1ADRL14 S) Invalid D1ADRL13 D1ADRL12 D1ADRL11 D1ADRL10 D1ADRL9 D1ADRL8 D1ADRL7 D1ADRL6 D1ADRL5 D1ADRL4 D1ADRL3 D1ADRL2 D1ADRL1 D1ADRL0 X X X X X X X X X X X X X X X X R/W reserved Ch.1 transfer data size D) Ch.1 source address control S) Ch.1 memory address control EPSON - 1 Half word S1IN[1:0] 1 1 1 0 0 1 0 0 0 Byte Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed Remarks S1C33L03 FUNCTION PART V DMA BLOCK: HSDMA (High-Speed DMA) A-1 Register name Address Bit Name High-speed 004823A DMA Ch.1 (HW) high-order destination address set-up register DF DE D1MOD1 D1MOD0 Ch.1 transfer mode DD DC D1IN1 D1IN0 D) Ch.1 destination address control S) Invalid DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D1ADRH11 D) Ch.1 destination D1ADRH10 address[27:16] D1ADRH9 S) Invalid D1ADRH8 D1ADRH7 D1ADRH6 D1ADRH5 D1ADRH4 D1ADRH3 D1ADRH2 D1ADRH1 D1ADRH0 Note: D) Dual address mode S) Single address mode Function High-speed 004823C DF-1 - DMA Ch.1 (HW) D0 HS1_EN enable register reserved High-speed DMA Ch.1 trigger flag register 004823E DF-1 - (HW) D0 HS1_TF reserved High-speed DMA Ch.2 transfer counter register 0048240 (HW) High-speed 0048242 DMA Ch.2 (HW) control register Note: D) Dual address mode S) Single address mode Setting D1MOD[1:0] 1 1 1 0 0 1 0 0 D1IN[1:0] 1 1 1 0 0 1 0 0 Mode Invalid Block Successive Single Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed - Ch.1 enable 1 Enable 0 Disable - Ch.1 trigger flag clear (writing) Ch.1 trigger flag status (reading) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC2_L7 TC2_L6 TC2_L5 TC2_L4 TC2_L3 TC2_L2 TC2_L1 TC2_L0 BLKLEN27 BLKLEN26 BLKLEN25 BLKLEN24 BLKLEN23 BLKLEN22 BLKLEN21 BLKLEN20 Ch.2 transfer counter[7:0] (block transfer mode) DF DE DUALM2 D2DIR DD-8 D7 D6 D5 D4 D3 D2 D1 D0 - TC2_H7 TC2_H6 TC2_H5 TC2_H4 TC2_H3 TC2_H2 TC2_H1 TC2_H0 Ch.2 address mode selection D) Invalid S) Ch.2 transfer direction control reserved Ch.2 transfer counter[15:8] (block transfer mode) 1 Clear 1 Set 0 No operation 0 Cleared Ch.2 transfer counter[15:8] (single/successive transfer mode) Ch.2 block length (block transfer mode) Ch.2 transfer counter[7:0] (single/successive transfer mode) Ch.2 transfer counter[23:16] (single/successive transfer mode) 1 Dual addr 0 Single addr - 1 Memory WR 0 Memory RD - Init. R/W Remarks 0 0 R/W 0 0 R/W X X X X X X X X X X X X R/W - - 0 R/W - - 0 R/W X X X X X X X X X X X X X X X X R/W 0 - 0 - X X X X X X X X R/W - R/W - Undefined in read. R/W Undefined in read. Undefined in read. R/W B-V HSDMA S1C33L03 FUNCTION PART EPSON B-V-2-23 V DMA BLOCK: HSDMA (High-Speed DMA) Register name Address Bit High-speed 0048244 DMA Ch.2 (HW) low-order source address set-up register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S2ADRL15 D) Ch.2 source address[15:0] S2ADRL14 S) Ch.2 memory address[15:0] S2ADRL13 S2ADRL12 S2ADRL11 S2ADRL10 S2ADRL9 S2ADRL8 S2ADRL7 S2ADRL6 S2ADRL5 S2ADRL4 S2ADRL3 S2ADRL2 S2ADRL1 S2ADRL0 DF DE DD DC - DATSIZE2 S2IN1 S2IN0 DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Note: D) Dual address mode S) Single address mode High-speed 0048246 DMA Ch.2 (HW) high-order source address set-up register Note: D) Dual address mode S) Single address mode High-speed 0048248 DMA Ch.2 (HW) low-order destination address set-up register Note: D) Dual address mode S) Single address mode B-V-2-24 Name Function Setting Init. R/W X X X X X X X X X X X X X X X X R/W - 0 0 0 - R/W R/W S2ADRH11 D) Ch.2 source address[27:16] S2ADRH10 S) Ch.2 memory address[27:16] S2ADRH9 S2ADRH8 S2ADRH7 S2ADRH6 S2ADRH5 S2ADRH4 S2ADRH3 S2ADRH2 S2ADRH1 S2ADRH0 X X X X X X X X X X X X R/W D2ADRL15 D) Ch.2 destination address[15:0] D2ADRL14 S) Invalid D2ADRL13 D2ADRL12 D2ADRL11 D2ADRL10 D2ADRL9 D2ADRL8 D2ADRL7 D2ADRL6 D2ADRL5 D2ADRL4 D2ADRL3 D2ADRL2 D2ADRL1 D2ADRL0 X X X X X X X X X X X X X X X X R/W reserved Ch.2 transfer data size D) Ch.2 source address control S) Ch.2 memory address control EPSON - 1 Half word S2IN[1:0] 1 1 1 0 0 1 0 0 0 Byte Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed Remarks S1C33L03 FUNCTION PART V DMA BLOCK: HSDMA (High-Speed DMA) A-1 Register name Address Bit Name High-speed 004824A DMA Ch.2 (HW) high-order destination address set-up register DF DE D2MOD1 D2MOD0 Ch.2 transfer mode DD DC D2IN1 D2IN0 D) Ch.2 destination address control S) Invalid DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D2ADRH11 D) Ch.2 destination D2ADRH10 address[27:16] D2ADRH9 S) Invalid D2ADRH8 D2ADRH7 D2ADRH6 D2ADRH5 D2ADRH4 D2ADRH3 D2ADRH2 D2ADRH1 D2ADRH0 Note: D) Dual address mode S) Single address mode Function High-speed 004824C DF-1 - DMA Ch.2 (HW) D0 HS2_EN enable register reserved High-speed DMA Ch.2 trigger flag register 004824E DF-1 - (HW) D0 HS2_TF reserved High-speed DMA Ch.3 transfer counter register 0048250 (HW) High-speed 0048252 DMA Ch.3 (HW) control register Note: D) Dual address mode S) Single address mode Setting D2MOD[1:0] 1 1 1 0 0 1 0 0 D2IN[1:0] 1 1 1 0 0 1 0 0 Mode Invalid Block Successive Single Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed - Ch.2 enable 1 Enable 0 Disable - Ch.2 trigger flag clear (writing) Ch.2 trigger flag status (reading) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC3_L7 TC3_L6 TC3_L5 TC3_L4 TC3_L3 TC3_L2 TC3_L1 TC3_L0 BLKLEN37 BLKLEN36 BLKLEN35 BLKLEN34 BLKLEN33 BLKLEN32 BLKLEN31 BLKLEN30 Ch.3 transfer counter[7:0] (block transfer mode) DF DE DUALM3 D3DIR DD-8 D7 D6 D5 D4 D3 D2 D1 D0 - TC3_H7 TC3_H6 TC3_H5 TC3_H4 TC3_H3 TC3_H2 TC3_H1 TC3_H0 Ch.3 address mode selection D) Invalid S) Ch.3 transfer direction control reserved Ch.3 transfer counter[15:8] (block transfer mode) 1 Clear 1 Set 0 No operation 0 Cleared Ch.3 transfer counter[15:8] (single/successive transfer mode) Ch.3 block length (block transfer mode) Ch.3 transfer counter[7:0] (single/successive transfer mode) Ch.3 transfer counter[23:16] (single/successive transfer mode) 1 Dual addr 0 Single addr - 1 Memory WR 0 Memory RD - Init. R/W Remarks 0 0 R/W 0 0 R/W X X X X X X X X X X X X R/W - - 0 R/W - - 0 R/W X X X X X X X X X X X X X X X X R/W 0 - 0 - X X X X X X X X R/W - R/W - Undefined in read. R/W Undefined in read. Undefined in read. R/W B-V HSDMA S1C33L03 FUNCTION PART EPSON B-V-2-25 V DMA BLOCK: HSDMA (High-Speed DMA) Register name Address Bit High-speed 0048254 DMA Ch.3 (HW) low-order source address set-up register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S3ADRL15 D) Ch.3 source address[15:0] S3ADRL14 S) Ch.3 memory address[15:0] S3ADRL13 S3ADRL12 S3ADRL11 S3ADRL10 S3ADRL9 S3ADRL8 S3ADRL7 S3ADRL6 S3ADRL5 S3ADRL4 S3ADRL3 S3ADRL2 S3ADRL1 S3ADRL0 DF DE DD DC - DATSIZE3 S3IN1 S3IN0 DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Note: D) Dual address mode S) Single address mode High-speed 0048256 DMA Ch.3 (HW) high-order source address set-up register Note: D) Dual address mode S) Single address mode High-speed 0048258 DMA Ch.3 (HW) low-order destination address set-up register Note: D) Dual address mode S) Single address mode B-V-2-26 Name Function Setting Init. R/W X X X X X X X X X X X X X X X X R/W - 0 0 0 - R/W R/W S3ADRH11 D) Ch.3 source address[27:16] S3ADRH10 S) Ch.3 memory address[27:16] S3ADRH9 S3ADRH8 S3ADRH7 S3ADRH6 S3ADRH5 S3ADRH4 S3ADRH3 S3ADRH2 S3ADRH1 S3ADRH0 X X X X X X X X X X X X R/W D3ADRL15 D) Ch.3 destination address[15:0] D3ADRL14 S) Invalid D3ADRL13 D3ADRL12 D3ADRL11 D3ADRL10 D3ADRL9 D3ADRL8 D3ADRL7 D3ADRL6 D3ADRL5 D3ADRL4 D3ADRL3 D3ADRL2 D3ADRL1 D3ADRL0 X X X X X X X X X X X X X X X X R/W reserved Ch.3 transfer data size D) Ch.3 source address control S) Ch.3 memory address control EPSON - 1 Half word S3IN[1:0] 1 1 1 0 0 1 0 0 0 Byte Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed Remarks S1C33L03 FUNCTION PART V DMA BLOCK: HSDMA (High-Speed DMA) A-1 Register name Address Bit Name High-speed 004825A DMA Ch.3 (HW) high-order destination address set-up register DF DE D3MOD1 D3MOD0 Ch.3 transfer mode DD DC D3IN1 D3IN0 D) Ch.3 destination address control S) Invalid DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D3ADRH11 D) Ch.3 destination D3ADRH10 address[27:16] D3ADRH9 S) Invalid D3ADRH8 D3ADRH7 D3ADRH6 D3ADRH5 D3ADRH4 D3ADRH3 D3ADRH2 D3ADRH1 D3ADRH0 Note: D) Dual address mode S) Single address mode Function High-speed 004825C DF-1 - DMA Ch.3 (HW) D0 HS3_EN enable register reserved High-speed DMA Ch.3 trigger flag register reserved 004825E DF-1 - (HW) D0 HS3_TF Setting D3MOD[1:0] 1 1 1 0 0 1 0 0 D3IN[1:0] 1 1 1 0 0 1 0 0 Mode Invalid Block Successive Single Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed - Ch.3 enable 1 Enable 0 Disable - Ch.3 trigger flag clear (writing) Ch.3 trigger flag status (reading) 1 Clear 1 Set 0 No operation 0 Cleared Init. R/W 0 0 R/W 0 0 R/W X X X X X X X X X X X X R/W - - 0 R/W - - 0 R/W Remarks Undefined in read. Undefined in read. CFK51-CFK50: K5[1:0] pin function selection (D[1:0]) / K5 function select register (0x402C0) CFK54-CFK53: K5[4:3] pin function selection (D[4:3]) / K5 function select register (0x402C0) Set the #DMAREQx pin of HSDMA. Write "1": #DMAREQx input Write "0": Input port Read: Valid CFK50, CFK51, CFK53 and CFK54 are the function select bits for K50 (#DMAREQ0), K51 (#DMAREQ1), K53 (#DMAREQ2) and K54 (#DMAREQ3), respectively. When using the #DMAREQx signal, write "1" to CFK5x to set the K5x port for inputting the signal. If this bit is set to "0", the pin is set for an input port. At cold start, CFK5x is set to "0" (input port). At hot start, CFK5x retains the previous status before an initial reset. CFP16-CFP15: P1[6:5] pin function selection (D[6:5]) / P1 function select register (0x402D4) Set the #DMAENDx pin of HSDMA. Write "1": #DMAENDx output Write "0": I/O port Read: Valid B-V When using the #DMAEND0 signal, set the P15 pin for the #DMAEND0 output pin by writing "1" to CFP15. Similarly, when using the #DMAEND1 signal, set the P16 pin for the #DMAEND1 output pin by writing "1" to CFP16. Furthermore, direct these pins for output by writing "1" to the corresponding I/O control register. If CFP1x is set to "0", the pin is set for an I/O port. At cold start, CFP1x is set to "0" (I/O port). At hot start, CFP1x retains the previous status before an initial reset. S1C33L03 FUNCTION PART EPSON B-V-2-27 HSDMA V DMA BLOCK: HSDMA (High-Speed DMA) IOC16-IOC15: P1[6:5] port I/O control (D[6:5]) / P1 I/O control register (0x402D6) Directs P15 and P16 for input or output and indicates the I/O control signal value of the port. When writing data Write "1": Output mode Write "0": Input mode To use the #DMAEND0 pin (channel 0), direct the pin for output by writing "1" to IOC15; to use the #DMAEND1 pin (channel 1), direct the pin for output by writing "1" to IOC16. If these pins are set for input, the P15 and P16 pins do not function as the #DMAENDx output pins even when CFP15 and CFP16 are set to "1". When reading data Read "1": I/O control signal (output) Read "0": I/O control signal (input) The I/O control signal value for the port pin is read from this register. When I/O port function is selected using the CFP1x register, the value written to the IOC register is read out as is. When peripheral function is selected, the read value depends on the peripheral circuit status and may not indicate the value written to the IOC register. At cold start, IOC1x is set to "0" (input mode). At hot start, the bit retains its state from prior to the initial reset. CFP33-CFP32: P3[3:2] pin function selection (D[3:2]) / P3 function select register (0x402DC) Set the #DMAACKx pin of HSDMA. Write "1": #DMAACKx output Write "0": I/O port Read: Valid When using the #DMAACK0 signal, set the P32 pin for the #DMAACK0 output pin by writing "1" to CFP32. Similarly, when using the #DMAACK1 signal, set the P33 pin for the #DMAACK1 output pin by writing "1" to CFP33. If CFP3x is set to "0", the pin is set for an I/O port. At cold start, CFP3x is set to "0" (I/O port). At hot start, CFP3x retains the previous status before an initial reset. CFEX7-CFEX4: P0[7:4] pin function extension (D[7:4]) / Port function extension register (0x402DF) Set the #DMAACKx and #DMAENDx pins of HSDMA. Write "1": HSDMA output Write "0": I/O-port/serial interface I/O Read: Valid CFEX4, CFEX5, CFEX6 and CFEX7 are the function extention bits for P04 (#DMAACK2), P05 (#DMAEND2), P06 (#DMAACK3) and P07 (#DMAEND3), respectively. When using the HSDMA signal, write "1" to CFEXx to set the P0x port for outputting the signal. When CFEXx is set to "0", the corresponding CFP bit becomes effective. At cold start, these bits are set to "0" (I/O-port/serial interface I/O pin). At hot start, these bits retain the previous status before an initial reset. B-V-2-28 EPSON S1C33L03 FUNCTION PART V DMA BLOCK: HSDMA (High-Speed DMA) A-1 HSD0S3-HSD0S0: Ch. 0 trigger set-up (D[3:0]) / HSDMA Ch. 0/1 trigger set-up register (0x40298) HSD1S3-HSD1S0: Ch. 1 trigger set-up (D[7:4]) / HSDMA Ch. 0/1 trigger set-up register (0x40298) HSD2S3-HSD2S0: Ch. 2 trigger set-up (D[3:0]) / HSDMA Ch. 2/3 trigger set-up register (0x40299) HSD3S3-HSD3S0: Ch. 3 trigger set-up (D[7:4]) / HSDMA Ch. 2/3 trigger set-up register (0x40299) Select a trigger factor for each HSDMA channel. Table 2.6 HSDMA Trigger Factor Value Ch.0 trigger factor Ch.1 trigger factor Ch.2 trigger factor Ch.3 trigger factor 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 Software trigger K50 port input (falling edge) K50 port input (rising edge) Port 0 input Port 4 input 8-bit timer 0 underflow 16-bit timer 0 compare B 16-bit timer 0 compare A 16-bit timer 4 compare B 16-bit timer 4 compare A Serial I/F Ch.0 Rx buffer full Serial I/F Ch.0 Tx buffer empty A/D conversion completion Software trigger K51 port input (falling edge) K51 port input (rising edge) Port 1 input Port 5 input 8-bit timer 1 underflow 16-bit timer 1 compare B 16-bit timer 1 compare A 16-bit timer 5 compare B 16-bit timer 5 compare A Serial I/F Ch.1 Rx buffer full Serial I/F Ch.1 Tx buffer empty A/D conversion completion Software trigger K53 port input (falling edge) K53 port input (rising edge) Port 2 input Port 6 input 8-bit timer 2 underflow 16-bit timer 2 compare B 16-bit timer 2 compare A 16-bit timer 4 compare B 16-bit timer 4 compare A Serial I/F Ch.0 Rx buffer full Serial I/F Ch.0 Tx buffer empty A/D conversion completion Software trigger K54 port input (falling edge) K54 port input (rising edge) Port 3 input Port 7 input 8-bit timer 3 underflow 16-bit timer 3 compare B 16-bit timer 3 compare A 16-bit timer 5 compare B 16-bit timer 5 compare A Serial I/F Ch.1 Rx buffer full Serial I/F Ch.1 Tx buffer empty A/D conversion completion At initial reset, HSDxS is set to "0000" (software trigger). HST0: Ch. 0 software trigger (D0) / HSDMA software trigger register (0x4029A) HST1: Ch. 1 software trigger (D1) / HSDMA software trigger register (0x4029A) HST2: Ch. 2 software trigger (D2) / HSDMA software trigger register (0x4029A) HST3: Ch. 3 software trigger (D3) / HSDMA software trigger register (0x4029A) Start a DMA transfer. Write "1": Trigger Write "0": Invalid Read: Invalid Writing "1" to HSTx generates a trigger pulse that starts a DMA transfer. HSTx is effective only when software trigger is selected as the trigger factor of the HSDMA channel by the HSDxS bits. At initial reset, HSTx is set to "0". HS0_TF: Ch. 0 trigger flag clear/status (D0) / HSDMA Ch. 0 trigger flag register (0x4822E) HS1_TF: Ch. 1 trigger flag clear/status (D0) / HSDMA Ch. 1 trigger flag register (0x4823E) HS2_TF: Ch. 2 trigger flag clear/status (D0) / HSDMA Ch. 2 trigger flag register (0x4824E) HS3_TF: Ch. 3 trigger flag clear/status (D0) / HSDMA Ch. 3 trigger flag register (0x4825E) These bits are used to check and clear the trigger flag status. Write "1": Write "0": Read "1": Read "0": Trigger flag clear Invalid Trigger flag has been set Trigger flag has been cleared B-V The trigger flag is set when the trigger factor is input to the HSDMA channel and is cleared when the HSDMA channel starts a data transfer. By reading HSx_TF, the flag status can be checked. Writing "1" to HSx_TF clears the trigger flag if the DMA transfer has not been started. At initial reset, HSx_TF is set to "0". S1C33L03 FUNCTION PART EPSON B-V-2-29 HSDMA V DMA BLOCK: HSDMA (High-Speed DMA) HS0_EN: Ch. 0 enable (D0) / HSDMA Ch. 0 enable register (0x4822C) HS1_EN: Ch. 1 enable (D0) / HSDMA Ch. 1 enable register (0x4823C) HS2_EN: Ch. 2 enable (D0) / HSDMA Ch. 2 enable register (0x4824C) HS3_EN: Ch. 3 enable (D0) / HSDMA Ch. 3 enable register (0x4825C) Enable a DMA transfer. Write "1": Enabled Write "0": Disabled Read: Valid DMA transfer is enabled by writing "1" to this bit. HSDMA is placed in a state ready to accept a DMA request from the #DMAREQx pin or by the selected trigger factor. DMA transfer is disabled by writing "0" to this bit. When DMA transfers are completed (transfer counter = 0), HSx_EN is cleared by the hardware. Be sure to disable DMA transfers (HSx_EN = "0") before setting the transfer condition. At initial reset, HSx_EN is set to "0" (disabled). DUALM0: Ch. 0 address mode selection (DF) / HSDMA Ch. 0 control register (0x48222) DUALM1: Ch. 1 address mode selection (DF) / HSDMA Ch. 1 control register (0x48232) DUALM2: Ch. 2 address mode selection (DF) / HSDMA Ch. 2 control register (0x48242) DUALM3: Ch. 3 address mode selection (DF) / HSDMA Ch. 3 control register (0x48252) Select an address mode. Write "1": Dual-address mode Write "0": Single-address mode Read: Valid When "1" is written to DUALMx, the HSDMA channel enters dual-address mode that allows specification of source and destination addresses. When "0" is written, the HSDMA channel enters single-address mode for highspeed data transfer between the external memory and an I/O device. At initial reset, DUALMx is set to "0" (single-address mode). D0DIR: Ch. 0 transfer direction control (DE) / HSDMA Ch.0 control register (0x48222) D1DIR: Ch. 1 transfer direction control (DE) / HSDMA Ch.1 control register (0x48232) D2DIR: Ch. 2 transfer direction control (DE) / HSDMA Ch.2 control register (0x48242) D3DIR: Ch. 3 transfer direction control (DE) / HSDMA Ch.3 control register (0x48252) Control the direction of data transfer in single-address mode. Write "1": Memory write (I/O to memory) Write "0": Memory read (memory to I/O) Read: Valid Data transfer from an external I/O device to external memory is performed by writing "1" to DxDIR. Data transfer from external memory to an external I/O is performed by writing "0". At initial reset, DxDIR is set to "0" (memory to I/O). This bit is effective only in single-address mode. B-V-2-30 EPSON S1C33L03 FUNCTION PART V DMA BLOCK: HSDMA (High-Speed DMA) A-1 D0MOD1-D0MOD0: Ch. 0 transfer mode (D[F:E]) / Ch. 0 high-order destination address set-up register (0x4822A) D1MOD1-D1MOD0: Ch. 1 transfer mode (D[F:E]) / Ch. 1 high-order destination address set-up register (0x4823A) D2MOD1-D2MOD0: Ch. 2 transfer mode (D[F:E]) / Ch. 2 high-order destination address set-up register (0x4824A) D3MOD1-D3MOD0: Ch. 3 transfer mode (D[F:E]) / Ch. 3 high-order destination address set-up register (0x4825A) Select a transfer mode. Table 2.7 Transfer Mode DxMOD1 DxMOD0 1 1 0 0 1 0 1 0 Mode Invalid Block transfer mode Successive transfer mode Single transfer mode In single transfer mode, a transfer operation invoked by one trigger is completed after transferring one unit of data of the size set by DATSIZEx. In successive transfer mode, data transfer operations are performed by one trigger a number of times as set by the transfer counter. In block transfer mode, a transfer operation invoked by one trigger is completed after transferring one block of data of the size set by BLKLENx. At initial reset, DxMOD is set to "00" (single transfer mode). DATSIZE0: Ch. 0 transfer data size (DE) / Ch. 0 high-order source address register (0x48226) DATSIZE1: Ch. 1 transfer data size (DE) / Ch. 1 high-order source address register (0x48236) DATSIZE2: Ch. 2 transfer data size (DE) / Ch. 2 high-order source address register (0x48246) DATSIZE3: Ch. 3 transfer data size (DE) / Ch. 3 high-order source address register (0x48256) Select the data size to be transferred. Write "1": Half-word (16 bits) Write "0": Byte (8 bits) Read: Valid The transfer data size is set to 16 bits by writing "1" to DATSIZEx and set to 8 bits by writing "0". At initial reset, DATSIZEx is set to "0" (8 bits). S0IN1-S0IN0: Ch. 0 source address control (D[D:C]) / Ch. 0 high-order source address set-up register (0x48226) S1IN1-S1IN0: Ch. 1 source address control (D[D:C]) / Ch. 1 high-order source address set-up register (0x48236) S2IN1-S2IN0: Ch. 2 source address control (D[D:C]) / Ch. 2 high-order source address set-up register (0x48246) S3IN1-S3IN0: Ch. 3 source address control (D[D:C]) / Ch. 3 high-order source address set-up register (0x48256) Control the incrementing or decrementing of the memory address. Table 2.8 Address Control SxIN1 SxIN0 1 1 0 0 1 0 1 0 Address control Increment without initialization Increment with initialization Decrement without initialization Fixed In dual-address mode, this setting applies to the source address. In single-address mode, this setting applies to the external memory address. When "address fixed" (00) is selected, the source address is not changed by a data transfer performed. Even when transferring multiple data, the transfer data is always read from the same address. When "address increment" (11 or 10) is selected in single and successive transfer modes, the source address is incremented by an amount equal to the data size set by DATSIZEx when one data transfer is completed. When "address decrement" (01) is selected, the source address is decremented in the same way. In block transfer mode too, the source address is incremented or decremented when one data unit is transferred. However, if SxIN is set to "10", the source address that has been incremented during a block transfer recycles back to the initial value when the block transfer is completed. At initial reset, SxIN is set to "00" (Fixed). S1C33L03 FUNCTION PART EPSON B-V-2-31 B-V HSDMA V DMA BLOCK: HSDMA (High-Speed DMA) D0IN1-D0IN0: Ch. 0 destination address control (D[D:C]) / Ch. 0 high-order destination address set-up register (0x4822A) D1IN1-D1IN0: Ch. 1 destination address control (D[D:C]) / Ch. 1 high-order destination address set-up register (0x4823A) D2IN1-D2IN0: Ch. 2 destination address control (D[D:C]) / Ch. 2 high-order destination address set-up register (0x4824A) D3IN1-D3IN0: Ch. 3 destination address control (D[D:C]) / Ch. 3 high-order destination address set-up register (0x4825A) Control the incrementing or decrementing of the memory address. Table 2.9 Address Control DxIN1 DxIN0 1 1 0 0 1 0 1 0 Address control Increment without initialization Increment with initialization Decrement without initialization Fixed In dual-address mode, this setting applies to the destination address. In single-address mode, these bits are not used. When "address fixed" (00) is selected, the destination address is not changed by a data transfer performed. Even when transferring multiple data, the transfer data is always written to the same address. When "address increment" (11 or 10) is selected in single and successive transfer modes, the destination address is incremented by an amount equal to the data size set by DATSIZEx when one data transfer is completed. When "address decrement" (01) is selected, the destination address is decremented in the same way. In block transfer mode too, the destination address is incremented or decremented when one data unit is transferred. However, if DxIN is set to "10", the destination address that has been incremented during a block transfer recycles back to the initial value when the block transfer is completed. At initial reset, DxIN is set to "00" (Fixed). BLKLEN07-BLKLEN00: Ch. 0 block length/transfer counter[7:0] (D[7:0]) / Ch. 0 transfer counter register (0x48220) BLKLEN17-BLKLEN10: Ch. 1 block length/transfer counter[7:0] (D[7:0]) / Ch. 1 transfer counter register (0x48230) BLKLEN27-BLKLEN20: Ch. 2 block length/transfer counter[7:0] (D[7:0]) / Ch. 2 transfer counter register (0x48240) BLKLEN37-BLKLEN30: Ch. 3 block length/transfer counter[7:0] (D[7:0]) / Ch. 3 transfer counter register (0x48250) In block transfer mode, these bits are used to specify a transfer block size. A transfer operation invoked by one trigger is completed after transferring one block of data of the size set by BLKLENx. In single or successive transfer mode, these bits are used to specifythe 8 low-order bits of the transfer counter. At initial reset, these bits are not initialized. TC0_L7-TC0_L0: TC0_H7-TC0_H0: TC1_L7-TC1_L0: TC1_H7-TC1_H0: TC2_L7-TC2_L0: TC2_H7-TC2_H0: TC3_L7-TC3_L0: TC3_H7-TC3_H0: Ch. 0 transfer counter[7:0]/[15:8] (D[F:8]) / Ch. 0 transfer counter register (0x48220) Ch. 0 transfer counter[15:8]/[23:16] (D[7:0]) / Ch. 0 control register (0x48222) Ch. 1 transfer counter[7:0]/[15:8] (D[F:8]) / Ch. 1 transfer counter register (0x48230) Ch. 1 transfer counter[15:8]/[23:16] (D[7:0]) / Ch. 1 control register (0x48232) Ch. 2 transfer counter[7:0]/[15:8] (D[F:8]) / Ch. 2 transfer counter register (0x48240) Ch. 2 transfer counter[15:8]/[23:16] (D[7:0]) / Ch. 2 control register (0x48242) Ch. 3 transfer counter[7:0]/[15:8] (D[F:8]) / Ch. 3 transfer counter register (0x48250) Ch. 3 transfer counter[15:8]/[23:16] (D[7:0]) / Ch. 3 control register (0x48252) Set the data transfer count. In block transfer mode, TCx_L[7:0] is bits[7:0] of the transfer counter, and TCx_H[7:0] is bits[15:8] of the transfer counter. In single or successive transfer mode, TCx_L[7:0] is bits[15:8] of the transfer counter, and TCx_H[7:0] is bits[23:16] of the transfer counter. The 8 low-order bits are specified by BLKLENx[7:0]. This counter is decremented each time a DMA transfer in the corresponding channel is performed. When the counter reaches 0, an interrupt factor is generated. In single-address mode, the end-of-transfer signal is output from the #DMAENDx pin at the same time. Even when the counter is 0, a DMA request is accepted and the counter is decremented to "0xFFFF" (or "0xFFFFFF"). Be sure to disable DMA transfers (HSx_EN = "0") before writing and reading to and from the counter. At initial reset, these bits are not initialized. B-V-2-32 EPSON S1C33L03 FUNCTION PART V DMA BLOCK: HSDMA (High-Speed DMA) A-1 S0ADRL15-S0ADRL0: Ch. 0 source address[15:0] (D[F:0]) / Ch. 0 low-order source address set-up register (0x48224) S0ADRH11-S0ADRH0: Ch. 0 source address[27:16] (D[B:0]) / Ch. 0 high-order source address set-up register (0x48226) S1ADRL15-S1ADRL0: Ch. 1 source address[15:0] (D[F:0]) / Ch. 1 low-order source address set-up register (0x48234) S1ADRH11-S1ADRH0: Ch. 1 source address[27:16] (D[B:0]) / Ch. 1 high-order source address set-up register (0x48236) S2ADRL15-S2ADRL0: Ch. 2 source address[15:0] (D[F:0]) / Ch. 2 low-order source address set-up register (0x48244) S2ADRH11-S2ADRH0: Ch. 2 source address[27:16] (D[B:0]) / Ch. 2 high-order source address set-up register (0x48246) S3ADRL15-S3ADRL0: Ch. 3 source address[15:0] (D[F:0]) / Ch. 3 low-order source address set-up register (0x48254) S3ADRH11-S3ADRH0: Ch. 3 source address[27:16] (D[B:0]) / Ch. 3 high-order source address set-up register (0x48256) In dual-address mode, these bits are used to specify a source address. In single-address mode, an external memory address at the destination or source of transfer is specified. Use SxADRL to set the 16 low-order bits of the address and SxADRH to set the 12 high-order bits. Be sure to disable DMA transfers (HSx_EN = "0") before writing or reading to and from these registers. The address is incremented or decremented (as set by SxIN) according to the transfer data size each time a DMA transfer in the corresponding channel is performed. At initial reset, these bits are not initialized. D0ADRL15-D0ADRL0: Ch. 0 destination address[15:0] (D[F:0]) / Ch. 0 low-order destination address set-up register (0x48228) D0ADRH11-D0ADRH0: Ch. 0 destination address[27:16] (D[B:0]) / Ch. 0 high-order destination address set-up register (0x4822A) D1ADRL15-D1ADRL0: Ch. 1 destination address[15:0] (D[F:0]) / Ch. 1 low-order destination address set-up register (0x48238) D1ADRH11-D1ADRH0: Ch. 1 destination address[27:16] (D[B:0]) / Ch. 1 high-order destination address set-up register (0x4823A) D2ADRL15-D2ADRL0: Ch. 2 destination address[15:0] (D[F:0]) / Ch. 2 low-order destination address set-up register (0x48248) D2ADRH11-D2ADRH0: Ch. 2 destination address[27:16] (D[B:0]) / Ch. 2 high-order destination address set-up register (0x4824A) D3ADRL15-D3ADRL0: Ch. 3 destination address[15:0] (D[F:0]) / Ch. 3 low-order destination address set-up register (0x48258) D3ADRH11-D3ADRH0: Ch. 3 destination address[27:16] (D[B:0]) / Ch. 3 high-order destination address set-up register (0x4825A) In dual-address mode, these bits are used to specify a destination address. In single-address mode, these bits are not used. Be sure to disable DMA transfers (HSx_EN = "0") before writing or reading to and from these registers. The address is incremented or decremented (as set by DxIN) according to the transfer data size each time a DMA transfer in the corresponding channel is performed. At initial reset, these bits are not initialized. PHSD0L2-PHSD0L0: Ch. 0 interrupt level (D[2:0]) / HSDMA Ch. 0/1 interrupt priority register (0x40263) PHSD1L2-PHSD1L0: Ch. 1 interrupt level (D[6:4]) / HSDMA Ch. 0/1 interrupt priority register (0x40263) PHSD2L2-PHSD2L0: Ch. 2 interrupt level (D[2:0]) / HSDMA Ch. 2/3 interrupt priority register (0x40264) PHSD3L2-PHSD3L0: Ch. 3 interrupt level (D[6:4]) / HSDMA Ch. 2/3 interrupt priority register (0x40264) Set the priority level of an end-of-DMA interrupt in the range of 0 to 7. At initial reset, these registers become indeterminate. S1C33L03 FUNCTION PART EPSON B-V-2-33 B-V HSDMA V DMA BLOCK: HSDMA (High-Speed DMA) EHDM0: Ch. 0 interrupt enable (D0) / DMA interrupt enable register (0x40271) EHDM1: Ch. 1 interrupt enable (D1) / DMA interrupt enable register (0x40271) EHDM2: Ch. 2 interrupt enable (D2) / DMA interrupt enable register (0x40271) EHDM3: Ch. 3 interrupt enable (D3) / DMA interrupt enable register (0x40271) Enable or disable interrupt generation to the CPU. Write "1": Interrupt enabled Write "0": Interrupt disabled Read: Valid EHDMx is the interrupt enable bit for HSDMA channel x. The interrupt is enabled when EHDMx is set to "1" and disabled when EHDMx is set to "0". At initial reset, EHDMx is set to "0" (interrupt disabled). FHDM0: Ch. 0 interrupt factor flag (D0) / DMA interrupt factor flag register (0x40281) FHDM1: Ch. 1 interrupt factor flag (D1) / DMA interrupt factor flag register (0x40281) FHDM2: Ch. 2 interrupt factor flag (D2) / DMA interrupt factor flag register (0x40281) FHDM3: Ch. 3 interrupt factor flag (D3) / DMA interrupt factor flag register (0x40281) Indicate the occurrence status of HSDMA interrupt factor. When read Read "1": Interrupt factor generated Read "0": No interrupt factor generated When written using the reset-only method (default) Write "1": Factor flag is reset Write "0": Invalid When written using the read/write method Write "1": Factor flag is set Write "0": Factor flag is reset FHDMx is the interrupt factor flag for HSDMA channel x. These flags are set to "1" when the transfer counter reaches 0. An interrupt to the CPU is generated if the following conditions are met at this time: 1. The corresponding interrupt enable register is set to "1". 2. No other interrupt request of higher priority is generated. 3. The IE bit of the PSR is set to "1" (interrupt enable). 4. The corresponding interrupt priority register is set to a level higher than the CPU's interrupt level (IL). When using an interrupt factor to request IDMA, note that even when the above conditions are met, no interrupt request to the CPU is generated for the interrupt factor that has occurred. If interrupts are enabled at the setting of the IDMA side, an interrupt is generated under the above conditions after the data transfer by IDMA is completed. The interrupt factor flag is always set to "1" when an interrupt factor occurs no matter how the interrupt enable and interrupt priority registers are set. In order for the next interrupt to be accepted after interrupt generation, the interrupt factor flag must be reset and the PSR must be set up again (by setting the IL below the level indicated by the interrupt priority register and setting the IE bit to "1" or executing the reti instruction). The interrupt factor flag can only be reset by a write instruction in the software application. If the PSR is again set up to accept interrupts (or the reti instruction is executed) without resetting the interrupt factor flag, the same interrupt may occur again. Note also that the value to be written to reset the flag is "1" when using the reset-only method (RSTONLY = "1") and "0" when using the read/write method (RSTONLY = "0"). Be careful not to confuse these two cases. The FHDMx flag becomes indeterminate when initially reset, so be sure to reset the flag in the software application. B-V-2-34 EPSON S1C33L03 FUNCTION PART V DMA BLOCK: HSDMA (High-Speed DMA) A-1 RHDM0: Ch.0 IDMA request (D4) / Port input 0-3, HSDMA, 16-bit timer 0 IDMA request register (0x40290) RHDM1: Ch.1 IDMA request (D5) / Port input 0-3, HSDMA, 16-bit timer 0 IDMA request register (0x40290) Specify whether IDMA need to be invoked when an interrupt factor occurs. When using the set-only method (default) Write "1": IDMA request Write "0": Not changed Read: Valid When using the read/write method Write "1": IDMA request Write "0": Interrupt request Read: Valid RHDM0 and RHDM1 are the IDMA request bits for HSDMA channels 0 and 1, respectively. If the bit is set to "1", IDMA is invoked when an interrupt factor occurs, thus performing a programmed data transfer. If the register is set to "0", regular interrupt processing is performed without ever invoking IDMA. For details on IDMA, refer to "IDMA (Intelligent DMA)". At initial reset, RHDMx is set to "0" (interrupt request). DEHDM0: Ch.0 IDMA enable (D4) / Port input 0-3, HSDMA, 16-bit timer 0 IDMA enable register (0x40294) DEHDM1: Ch.1 IDMA enable (D5) / Port input 0-3, HSDMA, 16-bit timer 0 IDMA enable register (0x40294) Enables IDMA transfer by means of an interrupt factor. When using the set-only method (default) Write "1": IDMA enabled Write "0": Not changed Read: Valid When using the read/write method Write "1": IDMA enabled Write "0": IDMA disabled Read: Valid DEHDM0 and DEHDM1 are the IDMA enable bits for HSDMA channels 0 and 1, respectively. If DEHDMx is set to "1", the IDMA request by the interrupt factor is enabled. If the bit is set to "0", the IDMA request is disabled. At initial reset, DEHDMx is set to "0" (IDMA disabled). B-V HSDMA S1C33L03 FUNCTION PART EPSON B-V-2-35 V DMA BLOCK: HSDMA (High-Speed DMA) Programming Notes (1) When setting the transfer conditions, always make sure the DMA controller is inactive (HSx_EN = "0"). (2) After an initial reset, the interrupt factor flag (FHDMx) becomes indeterminate. Always be sure to reset the flag to prevent interrupts or IDMA requests from being generated inadvertently. (3) To prevent an interrupt from being generated repeatedly for the same factor, be sure to reset the interrupt factor flag before setting up the PSR again or executing the reti instruction. (4) HSDMA is given higher priority over IDMA (intelligent DMA) and the CPU. However, since HSDMA and IDMA share the same circuit, HSDMA cannot gain the bus ownership while an IDMA transfer is under way. Requests for HSDMA invocation that have occurred during an IDMA transfer are kept pending until the IDMA transfer is completed. A request for IDMA invocation or an interrupt request that has occurred during a HSDMA transfer are accepted after completion of the HSDMA transfer. (5) In HALT mode, since the DMA and BCU clocks operate, if the next operation is performed in HALT mode, not HALT2 mode, with a setting of 0 in clock option register HLT2OP (D3/0x40190), that operation will be an unpredictable erroneous operation. If a DMA trigger occurs and DMA is invoked while the CPU is stopped after HALT mode execution, erroneous operation will result. Ensure that DMA is not invoked in HALT mode. In HALT2 mode, DMA is not invoked since the DMA and BCU clocks are stopped. B-V-2-36 EPSON S1C33L03 FUNCTION PART V DMA BLOCK: IDMA (Intelligent DMA) A-1 V-3 IDMA (Intelligent DMA) Functional Outline of IDMA The DMA Block contains an intelligent DMA (IDMA), a function that allows control information to be programmed in RAM. Up to 128 channels can be programmed, including 31 channels that are invoked by an interrupt factor that occurs in some internal peripheral circuit. Although an additional overhead for loading and storing control information in RAM may be incurred, this intelligent DMA supports such functions as successive transfers, block transfers, and linking to another IDMA. IDMA is invoked by an interrupt factor that occurs in some internal peripheral circuit or a software trigger, thereby performing a data transfer according to the control information in RAM. When the transfer is completed, IDMA can generate an interrupt or invoke another IDMA according to link settings. Programming Control Information The intelligent DMA operates according to the control information prepared in RAM. The control information can be stored in either internal RAM or external RAM should the necessary area be allocated. The control information is 3 words (12 bytes) per channel in size, and must be located at contiguous addresses beginning with the base address that is set in the software application as the starting address of channel 0. Consequently, an area of 384 words (1,536 bytes) in RAM is required in order for all of 128 channels to be used. The following explains how to set the base address and the contents of control information. Before using IDMA, make each the settings described below. Setting the base address Set the starting address of control information (starting address of channel 0) in the IDMA base address register. 16 low-order bits: DBASEL[15:0] (D[F:0]) / IDMA base address low-order register (0x48200) 12 high-order bits: DBASEH[11:0] (D[B:0]) / IDMA base address high-order register (0x48202) When initially reset, the base address is set to 0x0C003A0. Notes: * The address you set in the IDMA base address register must always be a word (32-bit) boundary address. * Be sure to disable DMA transfers (IDMAEN = "0") before setting the base address. Writing to the IDMA base address register is ignored when the DMA transfer is enabled (IDMAEN = "1"). When the register is read, the read data is indeterminate. Control information Write the control information for the IDMA channels used to RAM. The addresses at which the control information of each channel is placed are determined by the base address and a channel number. Starting address of channel = base address + (channel number x 12 [bytes]) B-V Note: The control information must be written only when the channel to be set does not start a DMA transfer. If a DMA transfer starts when the control information is being written to the RAM, proper transfer cannot performed. Reading the control information can always be done. S1C33L03 FUNCTION PART EPSON B-V-3-1 IDMA V DMA BLOCK: IDMA (Intelligent DMA) The contents of control information (3 words) in each channel are shown in the table below. Table 3.1 IDMA Control Information Word 1st Bit D31 D30-24 D23-8 D7-0 2nd 3rd D31 D30 D29-28 D27-0 D31-30 D29-28 D27-0 Name Function LNKEN IDMA link enable "1" = Enabled, "0" = Disabled LNKCHN[6:0] IDMA link field TC[15:0] Transfer counter (block transfer mode) Transfer counter - high-order 16 bits (single or successive transfer mode) BLKLEN[7:0] Block size (block transfer mode) Transfer counter - low-order 8 bits (single or successive transfer mode) DINTEN End-of-transfer interrupt enable "1" = Enabled, "0" = Disabled DATSIZ Data size control "1" = Half-word, "0" = Byte SRINC[1:0] Source address control SRINC1 SRINC0 Setting contents 1 1 Address incremented (In block transfer mode, the transfer address is updated without reset using the initial value.) 1 0 Address incremented (In block transfer mode, the transfer address is updated with the initial value.) 0 1 Address decremented (In block transfer mode, the transfer address is updated without reset using the initial value.) 0 0 Address fixed SRADR[27:0] Source address DMOD[1:0] Transfer mode (Do not set to "11".) DMOD1 DMOD0 Setting contents 1 0 Block transfer mode 0 1 Successive transfer mode 0 0 Single transfer mode DSINC[1:0] Destination address control DSINC1 DSINC0 Setting contents 1 1 Address incremented (In block transfer mode, the transfer address is updated without reset using the initial value.) 1 0 Address incremented (In block transfer mode, the transfer address is updated with the initial value.) 0 1 Address decremented (In block transfer mode, the transfer address is updated without reset using the initial value.) 0 0 Address fixed DSADR[27:0] Destination address LNKEN: IDMA link enable (D31/1st Word) If this bit remains set (= "1"), the IDMA channel that is set in the IDMA link field is invoked after the completion of a DMA transfer in this channel. DMA transfers in multiple channels can be performed successively by merely triggering the first channel to be executed. There is no limit to the number of channels linked. Set this link in order of the IDMA channels you want to be executed. If this bit is "0", IDMA is completed by merely executing a DMA transfer in this channel. LNKCHN[6:0]: IDMA link field (D[30:24]/1st Word) If you want IDMA to be linked, set the channel numbers (0 to 127) to be executed next. The data in this field is valid only when LINKEN = "1". TC[15:0]: Transfer counter (D[23:8]/1st Word) In block transfer mode, a transfer count can be specified using up to 16 bits. Set this value here. In single transfer and successive transfer modes, a transfer count can be specified using up to 24 bits. Set a 16-bit highorder value here. B-V-3-2 EPSON S1C33L03 FUNCTION PART V DMA BLOCK: IDMA (Intelligent DMA) BLKLEN[7:0]: Block size/transfer counter (D[7:0]/1st Word) In block transfer mode, set the size of a block that is transferred in one operation (in units of DATSIZ). In single transfer and successive transfer modes, set an 8-bit low-order value for the transfer count here. A-1 Note: The transfer count and block size thus set are decremented according to the transfers performed. If the transfer count or block size is set to 0, it is decremented to all Fs by the first transfer performed. This means that you have set the maximum value that is determined by the number of bits available. DINTEN: End-of-transfer interrupt enable (D31/2nd Word) If this bit is left set (= "1"), when the transfer counter reaches 0, an interrupt request to the CPU is generated based on the interrupt factor flag by which IDMA has been invoked. If this bit is "0", no interrupt request to the CPU is generated even when the transfer counter has reached 0. DATSIZ: Data size control (D30/2nd Word) Set the unit size of data to be transferred. A half-word size (16 bits) is assumed if this bit is "1" and a byte size (8 bits) is assumed if this bit is "0". SRINC[1:0]: Source address control (D[29:28]/2nd Word) Set the source address updating format. If the format is set for "address fixed" (00), the source address is not changed by a data transfer performed. Even when transferring multiple data, the transfer data is always read from the same address. If the format is set for "address increment" (11 or 10) in single and successive transfer modes, the source address is incremented by an amount equal to the data size set by DATSIZ when one data transfer is completed. If the format is set for "address decrement" (01), the source address is decremented in the same way. In block transfer mode too, the source address is incremented or decremented when one data unit is transferred. However, if the set format is "10", the source address that has been incremented during a block transfer recycles back to the initial value when the block transfer is completed. SRADR[27:0]: Source address (D[27:0]/2nd Word) Use these bits to set the starting address at the source of transfer. The content set here is updated according to the setting of SRINC. DMOD[1:0]: Transfer mode (D[31:30]/3rd Word) Use these bits to set the desired transfer mode. The transfer modes are outlined below (to be detailed later): * Single transfer mode (00) In this mode, a transfer operation invoked by one trigger is completed after transferring one unit of data of the size set by DATSIZ. If data transfer need to be performed a number of times as set by the transfer counter, an equal number of triggers are required. * Successive transfer mode (01) In this mode, data transfer operations are performed by one trigger a number of times as set by the transfer counter. The transfer counter is decremented to 0 each time data is transferred. * Block transfer mode (10) In this mode, a transfer operation invoked by one trigger is completed after transferring one block of data of the size set by BLKLEN. If a block transfer need to be performed a number of times as set by the transfer counter, an equal number of triggers are required. S1C33L03 FUNCTION PART EPSON B-V-3-3 B-V IDMA V DMA BLOCK: IDMA (Intelligent DMA) DSINC[1:0]: Destination address control (D[29:28]/3rd Word) Set the destination address update format. If the format is set for "address fixed" (00), the destination address is not changed by the performance of a data transfer operation. Even when transferring multiple data, the transfer data is always written to the same address. If the format is set for "address increment" (11 or 10) in single and successive transfer modes, the destination address is incremented by an amount equal to the data size set by DATSIZ when one data transfer is completed. If the format is set for "address decrement" (01), the destination address is decremented in the same way. In block transfer mode as well, the destination address is incremented or decremented when one data unit is transferred. However, if the set format is "10", the destination address that has been incremented during a block transfer recycles back to the initial value when the block transfer is completed. DSADR[27:0]: Destination address (D[27:0]/3rd Word) Use these bits to set the starting address at the destination of transfer. The content set here is updated according to the setting of DSINC. Since the control information is placed in RAM, it can be rewritten. However, before rewriting the content of this information, make sure that no DMA transfer is generated in the channel whose information you are going to rewrite. B-V-3-4 EPSON S1C33L03 FUNCTION PART V DMA BLOCK: IDMA (Intelligent DMA) A-1 IDMA Invocation The triggers by which IDMA is invoked have the following three causes: 1. Interrupt factor in an internal peripheral circuit 2. Trigger in the software application 3. Link setting Enabling/disabling DMA transfer The IDMA controller is enabled by writing "1" to the IDMA enable bit IDMAEN (D0) / IDMA enable register (0x48205), and is ready to accept the triggers described above. However, before enabling a DMA transfer, be sure to set the base address and the control information for the channel to be invoked correctly. If IDMAEN is set to "0", no IDMA invocation request is accepted. IDMA invocation by an interrupt factor in internal peripheral circuits Some internal peripheral circuits that have an interrupt generating function can invoke IDMA by an interrupt factor in that circuit. The IDMA channel numbers corresponding to such IDMA invocation are predetermined. The relationship between the interrupt factors that have this function and the IDMA channels is shown in Table 3.2. Table 3.2 Interrupt Factors Used to Invoke IDMA Peripheral circuit Ports Interrupt factor Port input 0 Port input 1 Port input 2 Port input 3 High-speed DMA Ch.0, end of transfer Ch.1, end of transfer 16-bit programmable Timer 0 comparison B timer Timer 0 comparison A Timer 1 comparison B Timer 1 comparison A Timer 2 comparison B Timer 2 comparison A Timer 3 comparison B Timer 3 comparison A Timer 4 comparison B Timer 4 comparison A Timer 5 comparison B Timer 5 comparison A 8-bit programmable Timer 0 underflow timer Timer 1 underflow Timer 2 underflow Timer 3 underflow Serial interface Ch.0 receive buffer full Ch.0 transmit buffer empty Ch.1 receive buffer full Ch.1 transmit buffer empty A/D converter End of A/D conversion Ports Port input 4 Port input 5 Port input 6 Port input 7 S1C33L03 FUNCTION PART IDMA Ch. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 EPSON IDMA request bit RP0 (D0/0x40290) RP1 (D1/0x40290) RP2 (D2/0x40290) RP3 (D3/0x40290) RHDM0 (D4/0x40290) RHDM1 (D5/0x40290) R16TU0 (D6/0x40290) R16TC0 (D7/0x40290) R16TU1 (D0/0x40291) R16TC1 (D1/0x40291) R16TU2 (D2/0x40291) R16TC2 (D3/0x40291) R16TU3 (D4/0x40291) R16TC3 (D5/0x40291) R16TU4 (D6/0x40291) R16TC4 (D7/0x40291) R16TU5 (D0/0x40292) R16TC5 (D1/0x40292) R8TU0 (D2/0x40292) R8TU1 (D3/0x40292) R8TU2 (D4/0x40292) R8TU3 (D5/0x40292) RSRX0 (D6/0x40292) RSTX0 (D7/0x40292) RSRX1 (D0/0x40293) RSTX1 (D1/0x40293) RADE (D2/0x40293) RP4 (D4/0x40293) RP5 (D5/0x40293) RP4 (D6/0x40293) RP7 (D7/0x40293) IDMA enable bit DEP0 (D0/0x40294) DEP1 (D1/0x40294) DEP2 (D2/0x40294) DEP3 (D3/0x40294) DEHDM0 (D4/0x40294) DEHDM1 (D5/0x40294) DE16TU0 (D6/0x40294) DE16TC0 (D7/0x40294) DE16TU1 (D0/0x40295) DE16TC1 (D1/0x40295) DE16TU2 (D2/0x40295) DE16TC2 (D3/0x40295) DE16TU3 (D4/0x40295) DE16TC3 (D5/0x40295) DE16TU4 (D6/0x40295) DE16TC4 (D7/0x40295) DE16TU5 (D0/0x40296) DE16TC5 (D1/0x40296) DE8TU0 (D2/0x40296) DE8TU1 (D3/0x40296) DE8TU2 (D4/0x40296) DE8TU3 (D5/0x40296) DESRX0 (D6/0x40296) DESTX0 (D7/0x40296) DESRX1 (D0/0x40297) DESTX1 (D1/0x40297) DEADE (D2/0x40297) DEP4 (D4/0x40297) DEP5 (D5/0x40297) DEP4 (D6/0x40297) DEP7 (D7/0x40297) B-V-3-5 B-V IDMA V DMA BLOCK: IDMA (Intelligent DMA) These interrupt factors are used in common for interrupt requests and IDMA invocation requests. To invoke IDMA upon the occurrence of an interrupt factor, set the corresponding bits of the IDMA request and IDMA enable registers shown in the table by writing "1". Then when an interrupt factor occurs, an interrupt request to the CPU is kept pending and the corresponding IDMA channel is invoked. The interrupt factor flag that has been set to "1" remains set until the DMA transfer invoked by it is completed. If the following two conditions are met when one DMA transfer is completed, an interrupt request is generated without resetting the interrupt factor flag. * The transfer counter has reached 0. * DINTEN in control information is set to "1" (interrupt enabled). In this case, the IDMA request register is cleared to "0". Therefore, if IDMA needs to be invoked when an interrupt factor occurs next time, this register must be set up again. To prevent unwanted IDMA requests from being generated, this setting must be performed before enabling interrupts and after resetting the interrupt factor flag. The IDMA enable bit is not cleared and remains set to "1". If the transfer counter is not 0, the interrupt factor flag is reset when the DMA transfer is completed, so that no interrupt is generated. In this case, the IDMA request bit and IDMA enable bit are not cleared and remain set to "1". When DINTEN in control information has been set to "0", the interrupt factor flag is reset even if the transfer counter reaches 0, so that no interrupt is generated. In this case, the IDMA request bit is not cleared but the IDMA enable bit is cleared. If the IDMA request register bit is left reset to "0", the relevant interrupt factor generates an interrupt request and not a IDMA request. The control registers (interrupt enable register and interrupt priority register) corresponding to the interrupt factor do not affect IDMA invocation. IDMA can be invoked even if the interrupt enable bit in ITC is set to "0" (interrupt disabled). However, these register must be set to enable the interrupt when generating the interrupt after completing the DMA transfer. IDMA invocation by a trigger in the software application All IDMA channels for which control information is set, including those corresponding to interrupt factors described above, can be invoked by a trigger in the software application. The following bits are used for this control: IDMA channel number set-up: DCHN[6:0] (D[6:0]) / IDMA start register (0x48204) IDMA start control: DSTART (D7) / IDMA start register (0x48204) When the IDMA channel number to be invoked (0 to 127) is written to DCHN and DSTART is set to "1", the specified IDMA channel starts a DMA transfer. DSTART remains set (= "1") during a DMA transfer and is reset to "0" in hardware when one DMA transfer operation is completed. Do not modify these bits during a DMA transfer. If DINTEN is set to "1" (interrupt enabled), an interrupt factor for the completion of IDMA transfer is generated when one DMA transfer is completed. IDMA invocation by link setting If LNKEN in the control information is set to "1" (link enabled), the IDMA channel that is set in the IDMA link field "LNKCHN" is invoked successively after a DMA transfer in the link-enabled channel is completed. The interrupt request by the first channel is generated after transfers in all linked channels are completed if the interrupt conditions are met. To generate an interrupt at the end of an IDMA transfer, the DINTEN (end-of-transfer interrupt enable) bits in the IDMA control information for the first IDMA channel to be invoked and all the channels to be linked must be set to "1". B-V-3-6 EPSON S1C33L03 FUNCTION PART V DMA BLOCK: IDMA (Intelligent DMA) A-1 IDMA invocation request during a DMA transfer An IDMA invocation request to another channel that is generated during a DMA transfer is kept pending until the DMA transfer that was being executed at the time is completed. Since an invocation request is not cleared, new requests will be accepted when the DMA transfer under execution is completed. An IDMA invocation request to the same channel canot be accepted while the channel is executing a DMA transfer because the same interrupt factor is used. Therefore, an interval longer than the DMA transfer period is required when invoking the same channel. IDMA invocation request when DMA transfer is disabled An IDMA invocation request generated when IDMAEN is "0" (DMA transfer disabled) is kept pending until IDMAEN is set to "1". Since an invocation request is not cleared, it is accepted when DMA transfer is enabled. Simultaneous generation of a software trigger and a hardware trigger When a software trigger and the hardware trigger for the same channel are generated simultaneously, the software trigger starts IDMA transfer. The IDMA transfer by the hardware trigger is not executed since the interrupt factor is reset when the DMA transfer is completed. However, an operation like this cannot be recommended. B-V IDMA S1C33L03 FUNCTION PART EPSON B-V-3-7 V DMA BLOCK: IDMA (Intelligent DMA) Operation of IDMA IDMA has three transfer modes, in each of which data transfer operates differently. Furthermore, an interrupt factor is processed differently depending on the type of trigger. The following describes the operation of IDMA in each transfer mode and how an interrupt factor is processed for each type of trigger. Single transfer mode The channels for which DMOD in control information is set to "00" operate in single transfer mode. In this mode, a transfer operation invoked by one trigger is completed after transferring one data unit of the size set by DATSIZ. If a data transfer needs to be performed a number of times as set by the transfer counter, an equal number of triggers are required. The operation of IDMA in single transfer mode is shown by the flow chart in Figure 3.1. START A Base address + (Channel number x 12) Calculates address of control information Loads channel control information B (3 words) Transfers one unit of data C (Data read from source of transfer) D (Data write to destination of transfer) Transfer counter - 1 E Saves channel control information F (3 words) Transfer counter = 0 N Y IDMA interrupt processing (if interrupt is enabled) END Trigger A B1 B2 B3 C D E F1 F2 F3 Figure 3.1 Operation Flow in Single Transfer Mode (1) When a trigger is accepted, the address for control information is calculated from the base address and channel number. (2) Control information is read from the calculated address into the internal temporary register. (3) Data of the size set in the control information is read from the source address. (4) The read data is written to the destination address. (5) The address is incremented or decremented and the transfer counter is decremented. (6) The modified control information is written to RAM. (7) In the case of a hardware trigger, the interrupt control bits are processed before completing IDMA. B-V-3-8 Condition Interrupt factor flag IDMA request bit IDMA enable bit Transfer counter "0": Transfer counter = "0", DINTEN = "1": Transfer counter = "0", DINTEN = "0": Reset ("0") Not changed ("1") Reset ("0") Not changed ("1") Reset ("0") Not changed ("1") Not changed ("1") Not changed ("1") Reset ("0") EPSON S1C33L03 FUNCTION PART V DMA BLOCK: IDMA (Intelligent DMA) A-1 Successive transfer mode The channels for which DMOD in control information is set to "01" operate in successive transfer mode. In this mode, a data transfer is performed by one trigger a number of times as set by the transfer counter. The transfer counter is decremented to "0" by one transfer executed. The operation of IDMA in successive transfer mode is shown by the flow chart in Figure 3.2. START Calculates address of control information Loads channel control information Transfers one unit of data Transfer counter - 1 A Base address + (Channel number x 12) B (3 words) C (Data read from source of transfer) D (Data write to destination of transfer) E Transfer counter = 0 N Y Saves channel control information F (3 words) IDMA interrupt processing (if interrupt is enabled) END Trigger A B1 B2 B3 C1 D1 E1 Cn Dn En F1 F2 F3 Figure 3.2 Operation Flow in Successive Transfer Mode (1) When a trigger is accepted, the address for control information is calculated from the base address and channel number. (2) Control information is read from the calculated address into the internal temporary register. (3) Data of the size set in the control information is read from the source address. (4) The read data is written to the destination address. (5) The address is incremented or decremented and the transfer counter is decremented. (6) Steps (3) to (5) are repeated until the transfer counter reaches 0. (7) The modified control information is written to RAM. (8) In the case of a hardware trigger, the interrupt control bits are processed before completing IDMA. Condition Interrupt factor flag IDMA request bit IDMA enable bit Transfer counter "0": Transfer counter = "0", DINTEN = "1": Transfer counter = "0", DINTEN = "0": Reset ("0") Not changed ("1") Reset ("0") Not changed ("1") Reset ("0") Not changed ("1") Not changed ("1") Not changed ("1") Reset ("0") B-V IDMA S1C33L03 FUNCTION PART EPSON B-V-3-9 V DMA BLOCK: IDMA (Intelligent DMA) Block transfer mode The channels for which DMOD in control information is set to "10" operate in block transfer mode. In this mode, a transfer operation invoked by one trigger is completed after transferring one block of data of the size set by BLKLEN. If a block transfer needs to be performed a number of times as set by the transfer counter, an equal number of triggers are required. The operation of IDMA in block transfer mode is shown by the flow chart in Figure 3.3. START A Base address + (Channel number x 12) Calculates address of control information Loads channel control information B (3 words) C (Data read from source of transfer) D (Data write to destination of transfer) Transfers one unit of data Block size - 1 E Block size = 0 N 1-block transfer Y : according to SRINC/DSINC settings Restores initial values to block size and address F Transfer counter - 1 G Saves channel control information H (3 words) Transfer counter = 0 N Y IDMA interrupt processing (if interrupt is enabled) END F Trigger A B1 B2 B3 C1 D1 E1 G Cn Dn En H1 H2 H3 Figure 3.3 Operation Flow in Block Transfer Mode (1) When a trigger is accepted, the address for control information is calculated from the base address and channel number. (2) Control information is read from the calculated address into the internal temporary register. (3) Data of the size set in the control information is read from the source address. (4) The read data is written to the destination address. (5) The address is incremented or decremented and BLKLEN is decremented. (6) Steps (3) to (5) are repeated until BLKLEN reaches 0. (7) If SRINC and DSINC are "10", the address is recycled to the initial value. (8) The transfer counter is decremented. (9) The modified control information is written to RAM. (10) In the case of a hardware trigger, the interrupt control bits are processed before completing IDMA. B-V-3-10 Condition Interrupt factor flag IDMA request bit IDMA enable bit Transfer counter "0": Transfer counter = "0", DINTEN = "1": Transfer counter = "0", DINTEN = "0": Reset ("0") Not changed ("1") Reset ("0") Not changed ("1") Reset ("0") Not changed ("1") Not changed ("1") Not changed ("1") Reset ("0") EPSON S1C33L03 FUNCTION PART V DMA BLOCK: IDMA (Intelligent DMA) A-1 Processing of interrupt factors by type of trigger * When invoked by an interrupt factor The interrupt factor flag by which IDMA has been invoked remains set even during a DMA transfer. If the transfer counter is decremented to 0 and DINTEN = "1" (interrupt enabled) when one DMA transfer is completed, the interrupt factor that has invoked IDMA is not reset and an interrupt request is generated. At the same time, the IDMA request register is cleared to "0". The IDMA enable bit is not cleared and remains set to "1". If the transfer counter is not 0, the interrupt factor flag is reset when the DMA transfer is completed, so that no interrupt is generated. In this case, the IDMA request bit and IDMA enable bit are not cleared and remain set to "1". When DINTEN has been set to "0" (interrupt disabled), the interrupt factor flag is reset even if the transfer counter reaches 0, so that no interrupt is generated. In this case, the IDMA request bit is not cleared but the IDMA enable bit is cleared. Trigger by interrupt factor Data transfer 2 Transfer counter 1 0 1 0 DINTEN IDMA request bit IDMA enable bit Interrupt factor flag Interrupt request Figure 3.4 Operation when Invoked by Interrupt Factor When IDMA is invoked by the software trigger, the IDMA interrupt factor flag FIDMA (D4)/DMA interrupt factor flag register (0x40281) will not be set. * When invoked by a software trigger If the transfer counter is decremented to 0 and DINTEN = "1" (interrupt enabled) when one DMA transfer is completed, the IDMA interrupt factor flag FIDMA (D4)/DMA interrupt factor flag register (0x40281) is set, thereby generating an interrupt request. If the transfer counter is not 0 or DINTEN = "0" (interrupt disabled), the FIDMA flag is not set. If the interrupt factor flag for the same channel is set during a software-triggered transfer, the IDMA invocation request by that interrupt factor flag is kept pending. However, the interrupt factor flag will be reset when the current execution is completed, so there will be no DMA transfer by the interrupt factor flag. Software trigger B-V Data transfer Transfer counter 2 1 0 1 0 IDMA DINTEN FIDMA (D4/0x40281) Interrupt request Figure 3.5 Operation when Invoked by Software Trigger S1C33L03 FUNCTION PART EPSON B-V-3-11 V DMA BLOCK: IDMA (Intelligent DMA) Linking If the IDMA channel number to be executed next is set in the IDMA link field "LNKCHN" of control information and LNKEN is set to "1" (link enabled), DMA successive transfer in that IDMA channel can be performed. An example of link setting is shown in Figure 3.6. Trigger After transfer Ch.3 Ch.5 Ch.7 LNKEN = 1 LNKCHN = 5 DMOD = 01 DINTEN = 1 TC = 1024 LNKEN = 1 LNKCHN = 7 DMOD = 00 DINTEN = 1 TC = 8 LNKEN = 0 LNKCHN = 9 DMOD = 10 DINTEN = 1 TC = 1 TC = 0 TC = 7 TC = 0 Figure 3.6 Example of Link Setting For the above example, IDMA operates as described below. * For trigger in hardware (1) The IDMA channel 3 is invoked by an interrupt factor and the DMA transfer that is set is performed. Since the IDMA is operating in successive transfer mode and the transfer counter is decremented to 0 and DINTEN is set to "1", the interrupt factor flag by which the channel 3 has been invoked remains set. (2) Next, a DMA transfer is performed via the linked IDMA channel 5. Channel 5 is set for single transfer mode and the transfer counter in this transfer is decremented by 1. (3) Finally, a DMA transfer in IDMA channel 7 is performed. Although the channel 7 is set for block transfer mode, the transfer counter is decremented to 0 when the transfer is completed because the number of transfers to be performed is 1. (4) Since the interrupt factor flag that has invoked IDMA channel 3 in (1) remains set, an interrupt is generated when the IDMA transfer (channel 7) in (3) is completed. The transfer result does not affect the interrupt factor flag of channel 3. To generate an interrupt at the end of an IDMA transfer, the DINTEN (end-of-transfer interrupt enable) bits in the IDMA control information for the first IDMA channel to be invoked and all the channels to be linked must be set to "1". * For trigger in the software application (1) The IDMA channel 3 is invoked by a trigger in the software application and the DMA transfer that is set is performed. Since the IDMA is operating in successive transfer mode and the transfer counter is decremented to 0 and DINTEN is set to "1", the IDMA interrupt factor flag FIDMA (D4)/DMA interrupt factor flag register (0x40281) is set when the transfer is completed. (2) Next, a DMA transfer is performed in the linked IDMA channel 5. The channel 5 is set for the single transfer mode and the transfer counter in this transfer is decremented by 1. (3) Finally, a DMA transfer in IDMA channel 7 is performed. Although channel 7 is set for the block transfer mode, the transfer counter is decremented to 0 when the transfer is completed because the number of transfers to be performed is 1. The completion of this transfer also causes the FIDMA flag to be set to "1". However, the FIDMA flag has already been set when the transfer is completed in (1) above. (4) Since the FIDMA flag is set, an interrupt request is generated here. In cases when IDMA has been invoked by a trigger in the software application, if the transfer counter in any one of the linked channels is decremented to 0 and DINTEN for that channel is set to "1", an interrupt request for the completion of IDMA transfer is generated when a transfer operation in each of the linked channels is completed. The channel in which an interrupt request has been generated can be verified by reading out the transfer counter. Transfer operations in each channel are performed as described earlier. B-V-3-12 EPSON S1C33L03 FUNCTION PART V DMA BLOCK: IDMA (Intelligent DMA) A-1 Interrupt Function of Intelligent DMA IDMA can generate an interrupt that causes invocation of IDMA and an interrupt for the completion of IDMA transfer itself. Interrupt when invoked by an interrupt factor If the corresponding bits of the IDMA request and interrupt enable registers are left set (= "1"), assertion of an interrupt request is kept pending even when the enabled interrupt factor has occurred and the IDMA channel assigned to that interrupt factor is invoked. If the transfer counter is decremented to 0 and DINTEN = "1" (interrupt enabled) when one DMA transfer is completed, the interrupt factor that has invoked IDMA is not reset and an interrupt request is generated. At the same time, the IDMA request register is cleared to "0". The IDMA enable bit is not cleared and remains set to "1". If the transfer counter is not 0, the interrupt factor flag is reset when the DMA transfer is completed, so that no interrupt is generated. In this case, the IDMA request bit and IDMA enable bit are not cleared and remain set to "1". When DINTEN has been set to "0" (interrupt disabled), the interrupt factor flag is reset even if the transfer counter reaches 0, so that no interrupt is generated. In this case, the IDMA request bit is not cleared but the IDMA enable bit is cleared. When IDMA is invoked by the software trigger, the IDMA interrupt factor flag FIDMA (D4)/DMA interrupt factor flag register (0x40281) will not be set. For details about the interrupt factors that can be used to invoke IDMA and the interrupt control registers, refer to the descriptions of the peripheral circuits in this manual. Note that the priority levels of interrupt factors are set by the interrupt priority register. Refer to "ITC (Interrupt Controller)". However, when compared between IDMA and interrupt requests, IDMA is given higher priority over the other. Consequently, even when an interrupt factor occurring during an IDMA transfer has higher priority than the interrupt factor that invoked the IDMA transfer, an interrupt request for it or a new IDMA invocation request is not accepted until after the current IDMA transfer is completed. Software-triggered interrupts If the transfer counter is decremented to 0 and DINTEN = "1" (interrupt enabled) when one DMA transfer operation is completed, the IDMA interrupt factor flag FIDMA (D4)/DMA interrupt factor flag register (0x40281) is set, thereby generating an interrupt request. If the transfer counter is not 0 or DINTEN = "0" (interrupt disabled), the FIDMA flag is not set. IDMA interrupt control register in the interrupt controller The following registers are used to control an interrupt for the completion of IDMA transfer: Interrupt factor flag: FIDMA (D4) / DMA interrupt factor flag register (0x40281) Interrupt enable: EIDMA (D4) / DMA interrupt enable register (0x40271) Interrupt level: PDM[2:0] (D[2:0]) / IDMA interrupt priority register (0x40265) When a DMA transfer in the IDMA channel invoked by a trigger in the software application or subsequent link is completed and the transfer counter is decremented to 0, the interrupt factor flag for the completion of IDMA transfer is set to "1". However, this requires as a precondition that interrupt be enabled (DINTEN = "1") in the control information for that channel. If the interrupt enable register bit remains set (= "1") when the flag is set, an interrupt request is generated. Interrupts can be disabled by leaving the interrupt enable register bit cleared (= "0"). Use the interrupt priority register to set interrupt priority levels (0 to 7). An interrupt request to the CPU is accepted on condition that no other interrupt request of higher priority is generated. Furthermore, it is only when the PSR's IE bit = "1" (interrupt enabled) and the set value of IL is smaller than the IDMA interrupt level which is set by the interrupt priority register that the CPU actually accepts an IDMA interrupt request. For details about these interrupt control registers, and for information on device operation when an interrupt occurs, refer to "ITC (Interrupt Controller)". S1C33L03 FUNCTION PART EPSON B-V-3-13 B-V IDMA V DMA BLOCK: IDMA (Intelligent DMA) Trap vector The trap vector address for an interrupt upon completion of IDMA transfer by default is set to 0x0C00068. The trap table base address can be changed using the TTBR registers (0x48134 to 0x48137). I/O Memory of Intelligent DMA Table 3.3 shows the control bits of IDMA. Table 3.3 Control Bits of IDMA Register name Address Bit IDMA interrupt 0040265 priority register (B) D7-3 D2 D1 D0 - PDM2 PDM1 PDM0 reserved IDMA interrupt level DMA interrupt 0040271 enable register (B) D7-5 D4 D3 D2 D1 D0 - EIDMA EHDM3 EHDM2 EHDM1 EHDM0 reserved IDMA High-speed DMA Ch.3 High-speed DMA Ch.2 High-speed DMA Ch.1 High-speed DMA Ch.0 DMA interrupt factor flag register 0040281 (B) D7-5 D4 D3 D2 D1 D0 - FIDMA FHDM3 FHDM2 FHDM1 FHDM0 reserved IDMA High-speed DMA Ch.3 High-speed DMA Ch.2 High-speed DMA Ch.1 High-speed DMA Ch.0 IDMA base address loworder register 0048200 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 IDMA base address high-order register 0048202 DF-C - (HW) DB DBASEH11 DA DBASEH10 D9 DBASEH9 D8 DBASEH8 D7 DBASEH7 D6 DBASEH6 D5 DBASEH5 D4 DBASEH4 D3 DBASEH3 D2 DBASEH2 D1 DBASEH1 D0 DBASEH0 reserved IDMA base address high-order 12 bits (Initial value: 0x0C003A0) IDMA start register 0048204 (B) D7 DSTART D6-0 DCHN IDMA start IDMA channel number 1 IDMA start 0 Stop 0 to 127 IDMA enable register 0048205 (B) D7-1 - D0 IDMAEN reserved IDMA enable 1 Enabled B-V-3-14 Name Function Setting Remarks - X X X - 0 when being read. R/W - - 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W - X X X X X - 0 when being read. R/W R/W R/W R/W R/W 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 R/W - 0 0 0 0 1 1 0 0 0 0 0 0 - Undefined in read. R/W 0 0 R/W R/W - 0 - R/W 1 Enabled 0 Disabled - 1 Factor is generated 0 No factor is generated DBASEL15 IDMA base address DBASEL14 low-order 16 bits DBASEL13 (Initial value: 0x0C003A0) DBASEL12 DBASEL11 DBASEL10 DBASEL9 DBASEL8 DBASEL7 DBASEL6 DBASEL5 DBASEL4 DBASEL3 DBASEL2 DBASEL1 DBASEL0 - - EPSON Init. R/W - 0 to 7 0 Disabled S1C33L03 FUNCTION PART V DMA BLOCK: IDMA (Intelligent DMA) A-1 DBASEL[15:0]: IDMA base address [15:0] (D[F:0]) / IDMA base address low-order register (0x48200) DBASEH[11:0]: IDMA base address [27:16] (D[B:0]) / IDMA base address high-order register (0x48202) Specify the starting address of the control information to be placed in RAM. Use DBASEL to set the 16 low-order bits of the address and DBASEH to set the 12 high-order bits. The address to be set in these registers must always be a word (32-bit) boundary address. These registers cannot be read or written in bytes. The registers must be accessed in words for read/write operations to address 0x48200, and in half-words for read/write operations to addresses 0x48200 and 0x48202. Write operations in half-words must be performed in order of 0x48200 and 0x48202. Read operations in halfwords may be performed in any order. Write operations to the IDMA base address registers during a DMA transfer are ignored. When the register is read during a DMA transfer, the read data is indeterminate. At initial reset, the base address is set to 0xC003A0. IDMAEN: DMA enable (D0) / DMA enable register (0x48205) Enable a IDMA transfer. Write "1": Enabled Write "0": Disabled Read: Valid A data transfer operation by intelligent DMA is enabled by writing "1" to IDMAEN. IDMA transfer is disabled by writing "0" to IDMAEN. At initial reset, IDMAEN is set to "0" (disabled). DCHN[6:0]: IDMA channel number (D[6:0]) / IDMA start register (0x48204) Set the channel numbers (0 to 127) to be invoked by a trigger in the software application. At initial reset, DCHN is set to "0". DSTART: IDMA start (D7) / IDMA start register (0x48204) Use this register for a trigger in the software application and for monitoring the operation of IDMA. When written Write "1": IDMA started Write "0": Invalid When read Read "1": IDMA operating (only when invoked by software trigger) Read "0": IDMA inactive When DSTART is set to "1", it functions as a trigger in the software application, invoking the IDMA channel that is set in the DCHN register. At initial reset, DSTART is set to "0". PDM2-PDM0: IDMA interrupt level (D[2:0]) / IDMA interrupt priority register (0x40265) Set the priority level of the interrupt upon completion of IDMA transfer in the range of 0 to 7. At initial reset, the contents of this register are indeterminate. B-V EIDMA: IDMA interrupt enable (D4) / DMA interrupt enable register (0x40271) Enable or disable occurrence of an interrupt to the CPU. IDMA Write "1": Interrupt enabled Write "0": Interrupt disabled Read: Valid This bit controls the interrupt generated upon completion of IDMA transfer. The interrupt is enabled by setting this bit to "1" and disabled by setting this bit to "0". At initial reset, EIDMA is set to "0" (interrupt disable). S1C33L03 FUNCTION PART EPSON B-V-3-15 V DMA BLOCK: IDMA (Intelligent DMA) FIDMA: IDMA interrupt factor flag (D4) / DMA interrupt factor flag register (0x40281) Indicate the occurrence status of an IDMA interrupt request. When read Read "1": Interrupt factor occurred Read "0": No interrupt factor occurred When written using reset-only method (default) Write "1": Interrupt factor flag is reset Write "0": Invalid When written using the read/write method Write "1": Interrupt factor flag is set Write "0": Interrupt factor flag is reset This flag is set to "1" when one DMA transfer initiated by a software trigger or subsequent link is completed and the transfer counter is decremented to 0. However, this requires as a precondition that interrupts be enabled in control information (DINTEN = "1"). At this time, an interrupt to the CPU is generated if the following conditions are met: 1. The corresponding interrupt enable register bit is set to "1". 2. No interrupt request of higher priority is generated. 3. The IE bit of the PSR is set to "1" (interrupt enable). 4. The corresponding interrupt priority register is set to a level higher than the CPU's interrupt level (IL). In order for the next interrupt to be accepted after interrupt generation, the interrupt factor flag must be reset and the PSR must be set up again (by setting the IL below the level indicated by the interrupt priority register and setting the IE bit to "1" or executing a reti instruction). The interrupt factor flag can only be reset by a write instruction in the software application. If the PSR is set up again to accept interrupts (or the reti instruction is executed) without resetting the interrupt factor flag, the same interrupt may occur again. Note also that the value to be written to reset the flag is "1" when using the reset-only method (RSTONLY = "1") and "0" when using the read/write method (RSTONLY = "0"). Be careful not to confuse these two cases. This flag becomes indeterminate when initially reset, so be sure to reset it in the software application. B-V-3-16 EPSON S1C33L03 FUNCTION PART V DMA BLOCK: IDMA (Intelligent DMA) A-1 Programming Notes (1) Before setting the IDMA base address, be sure to disable DMA transfers (IDMAEN = "0"). Writing to the IDMA base address register is ignored when the DMA transfer is enabled (IDMAEN = "1"). Also, when the register is read during a DMA transfer, the data is indeterminate. When setting or rewriting control information for each channel, make sure that DMA transfers will not occur in any channel. (2) The address that is set in the IDMA base address register must always be a word (32-bit) boundary address. (3) After an initial reset, the interrupt factor flag (FIDMA) becomes indeterminate. To prevent unwanted interrupts from occurring, be sure to reset the flag in a program. (4) Once an interrupt occurs, be sure to reset the interrupt factor flag (FIDMA) before setting up the PSR again or executing the reti instruction. This ensures that an interrupt will not be generated for the same factor. (5) If all the following conditions are met, the transfer counter value becomes invalid during IDMA transfer so data cannot be transferred properly. 1. The IDMA control information (source/destination addresses, transfer counter, etc.) is placed in the external EDO DRAM. 2. The DRAM access timing condition is set to EDO mode by the BCU register. 3. The bus clock is set to x2 speed mode (#X2SPD pin = "0"). When placing the control information in the EDO DRAM in x2 speed mode, the DRAM access timing condition must be set to high-speed page mode. Or place the control information in the internal RAM. Using the internal RAM increases the performance because the overhead during IDMA transfer is decreased to 6 cycles on both load/store operations. (6) In HALT mode, since the DMA and BCU clocks operate, if the next operation is performed in HALT mode, not HALT2 mode, with a setting of 0 in clock option register HLT2OP (D3/0x40190), that operation will be an unpredictable erroneous operation. If a DMA trigger occurs and DMA is invoked while the CPU is stopped after HALT mode execution, erroneous operation will result. Ensure that DMA is not invoked in HALT mode. In HALT2 mode, DMA is not invoked since the DMA and BCU clocks are stopped. B-V IDMA S1C33L03 FUNCTION PART EPSON B-V-3-17 V DMA BLOCK: IDMA (Intelligent DMA) THIS PAGE IS BLANK. B-V-3-18 EPSON S1C33L03 FUNCTION PART S1C33L03 FUNCTION PART VI SDRAM CONTROLLER BLOCK VI SDRAM CONTROLLER BLOCK: INTRODUCTION A-1 VI-1 INTRODUCTION The SDRAM controller block provides a SDRAM interface that allows direct connection of external SDRAM chips via the BCU. C33 DMA Block C33 SDRAM Controller Block C33 LCD Controller Block C33_DMA C33_SDRAMC C33_LCDC (IDMA, HSDMA) (SDRAM interface) (LCD panel interface) Pads Internal RAM (Area 0) CORE_PAD C33 Internal Memory Block C33_CORE (CPU, BCU, ITC, CLG, DBG) Internal ROM (Area 10) Pads C33_SBUS C33_ADC C33_PERI (A/D converter) (Prescaler, 8-bit timer, 16-bit timer, Clock timer, Serial interface, Ports) C33 Analog Block PERI_PAD C33 Core Block Pads C33 Peripheral Block Figure 1.1 SDRAM Controller Block Note: Internal ROM is not provided in the S1C33L03. B-VI Intro S1C33L03 FUNCTION PART EPSON B-VI-1-1 VI SDRAM CONTROLLER BLOCK: INTRODUCTION THIS PAGE IS BLANK. B-VI-1-2 EPSON S1C33L03 FUNCTION PART VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE A-1 VI-2 SDRAM INTERFACE The SDRAM controller allows up to 32MB of SDRAM to be connected directly to areas 7 and 8 or areas 13 and 14. This chapter describes how to control the SDRAM interface, and how it operates. For the conditions and parameters used to configure the external bus except for the SDRAM interface, refer to Chapter II-4, "BCU (Bus Control Unit)". Outline of SDRAM Interface The following shows the main features and specifications of the SDRAM interface. * Supports 8 or 16-bit SDRAM. * Two SDRAM areas (areas 7 and 8 or areas 13 and 14) The following SDRAM configuration (maximum) is possible, connected directly to each area. - 16M x 16 bits x 1 chip - 8M x 16 bits x 2 chips - 32M x 8 bits x 1 chip - 16M x 8 bits x 2 chips * Supports 2 or 4-bank SDRAM (BA1 and BA0 outputs). Row address range: 2K (A10-A0), 4K (A11-A0), or 8K (A12-A0) Column address range: 256 (A7-A0), 512 (A8-A0), or 1K (A9-A0) * Incorporates a programmable 12-bit auto refresh counter. The SDRAM can be refreshed as necessary, irrespective of the clock frequency used. * Intelligent self-refresh mode for low-power operation * Two power-up options: - Precharge Refresh Mode Register Set - Precharge Mode Register Set Refresh * CAS latency: 2 * Burst length: Can be set to 1, 2, 4, or 8 words. SDRAM Controller Block Diagram Figure 2.1 shows the block diagram of the SDRAM controller. Note that the signals described in the figure are internal use, not external signals. User logic signals Data[15:0] D[15:0] Bus multiplex Address[23:0] addr[23:0] Bus Size Bus Mode Internal #CE6 Internal #CE7/13 Internal #CE8/14 Bus command decoder Internal #WAIT OSC3 clock Control registers SDRAM state control SDA[12:11], SDA[9:0] SDRAM command decoder SDA10, SDCKE, #SDCE0/1 #SDCAS, #SDRAS #SDWE, HDQM, LDQM B-VI Refresh counter SDRAM Figure 2.1 SDRAM Controller Block Diagram S1C33L03 FUNCTION PART EPSON B-VI-2-1 VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE I/O Pins and Connection I/O Pins Table 2.1 lists the pins used for the SDRAM interface. Table 2.1 I/O Pin List Pin name I/O Function A[13:12]/SDA[12:11], O Address bus A[10:1]/SDA[9:0] A[15:14]/SDBA[1:0] O SDRAM bank select signals D[15:0] I/O Data bus (D0-D15) #CE8/#RAS1/#CE14/#RAS3/#SDCE1 O Area 8/14 chip enable / DRAM Row strobe / SDRAM chip enable 1 #CE7/#RAS0/#CE13/#RAS2/#SDCE0 O Area 7/13 chip enable / DRAM Row strobe / SDRAM chip enable 0 #HCAS/#SDCAS O DRAM column address strobe (High-byte) / SDRAM column address strobe #LCAS/#SDRAS O DRAM column address strobe (Low-byte) / SDRAM row address strobe BCLK/SDCLK O Bus clock output / SDRAM operating clock P20/#DRD/SDCKE I/O I/O port / DRAM read / SDRAM clock enable P21/#DWE/#GAAS/#SDWE I/O I/O port / DRAM write (Low-byte) / Area address strobe output for GA / SDRAM write P33/#DMAACK1/SIN3/SDA10 I/O I/O port / HSDMA Ch. 1 acknowledge output / Serial I/F Ch. 3 data input / SDRAM address bus 10 P32/#DMAACK0/#SRDY3/HDQM I/O I/O port / HSDMA Ch. 0 acknowledge output / Serial I/F Ch. 3 ready signal output / SDRAM data (High-byte) input/output mask signal output P15/EXCL4/#DMAEND0/#SCLK3/ I/O I/O port / 16-bit timer 4 event counter input / HSDMA Ch. 0 end-of-transfer LDQM signal output / Serial I/F Ch. 3 clock input/output / SDRAM data (Low-byte) input/output mask signal output Connection Examples Figures 2.2 and 2.3 show examples of how to connect 16-bit SDRAMs to the S1C33. Figure 2.4 shows an example of how to connect an 8-bit SDRAM to the S1C33. S1C33 256M SDRAM (4M x 16 bits x 4 banks) SDA[12:11](A[13:12]) SDA10(P33) SDA[9:0](A[10:1]) SDBA[1:0](A[15:14]) D[15:0] A[12:11] A10 A[9:0] BA[1:0] DQ[15:0] BCLK SDCKE(P20) #SDCE0/1(#CE7/8) #SDCAS(#HCAS) #SDRAS(#LCAS) #SDWE(P21) HDQM(P32) LDQM(P15) CLK CKE #CS #CAS #RAS #WE DQMU DQML Figure 2.2 Connecting a 16-bit SDRAM (32MB) B-VI-2-2 EPSON S1C33L03 FUNCTION PART VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE A-1 S1C33 128M SDRAM (2M x 16 bits x 4 banks) SDA11(A12) SDA10(P33) SDA[9:0](A[10:1]) SDBA[1:0](A[15:14]) D[15:0] A11 A10 A[9:0] BA[1:0] DQ[15:0] BCLK SDCKE(P20) #SDCE0(#CE7) #SDCE1(#CE8) #SDCAS(#HCAS) #SDRAS(#LCAS) #SDWE(P21) HDQM(P32) LDQM(P15) CLK CKE #CS #CAS #RAS #WE DQMU DQML 128M SDRAM (2M x 16 bits x 4 banks) A11 A10 A[9:0] BA[1:0] DQ[15:0] CLK CKE #CS #CAS #RAS #WE DQMU DQML Figure 2.3 Connecting two 16-bit SDRAMs (32MB) S1C33 128M SDRAM (4M x 8 bits x 4 banks) SDA[12:11](A[13:12]) SDA10(P33) SDA[9:0](A[10:1]) SDBA[1:0](A[15:14]) D[7:0] A[12:11] A10 A[9:0] BA[1:0] DQ[7:0] BCLK SDCKE(P20) #SDCE0/1(#CE7/8) #SDCAS(#HCAS) #SDRAS(#LCAS) #SDWE(P21) LDQM(P15) CLK CKE #CS #CAS #RAS #WE DQM For little endian S1C33 128M SDRAM (4M x 8 bits x 4 banks) SDA[12:11](A[13:12]) SDA10(P33) SDA[9:0](A[10:1]) SDBA[1:0](A[15:14]) D[15:8] A[12:11] A10 A[9:0] BA[1:0] DQ[7:0] BCLK SDCKE(P20) #SDCE0/1(#CE7/8) #SDCAS(#HCAS) #SDRAS(#LCAS) #SDWE(P21) HDQM(P32) B-VI CLK CKE #CS #CAS #RAS #WE DQM SDRAM For big endian Figure 2.4 Connecting an 8-bit SDRAM (16MB) S1C33L03 FUNCTION PART EPSON B-VI-2-3 VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE Notes: * Because the SDRAM address bus pins differ in bit numbers from ordinary external address pin names, care must be taken when connecting an SDRAM to the S1C33. (SDRAM address SDA0 is output from the A1 pin, and SDA12 is output from the A13 pin.) Furthermore, the SDA10 signal with a special function is assigned to the P33 pin, and not to the address bus A11. * If designated pins (e.g., CKE and DQM[1:0] pins) must be driven high before the SDRAM can be powered on, add external pull-up resistors or use a separate power supply for the SDRAM. * To prevent a malfunction, take measures against noise when designing the board patterns for the SDRAM. Table 2.2 lists several examples of SDRAM chip configurations. All of these examples use only one area of the S1C33. If your design uses two areas, the same type of memory needs to be used in each area because SDRAMrelated settings are common to both areas. Table 2.2 Chip Configuration Example (when one area only is used) SDRAM 256M (4M x 16 bits x 4 banks) 256M (8M x 8 bits x 4 banks) 128M (2M x 16 bits x 4 banks) 128M (4M x 8 bits x 4 banks) 64M (1M x 16 bits x 4 banks) 64M (2M x 8 bits x 4 banks) 16M (512 x 16 bits x 2 banks) 16M (1M x 8 bits x 2 banks) B-VI-2-4 EPSON Number of devices Memory size 1 1 1 1 2 1 1 2 1 1 2 32M bytes 32M bytes 16M bytes 16M bytes 32M bytes 8M bytes 8M bytes 16M bytes 2M bytes 2M bytes 4M bytes S1C33L03 FUNCTION PART VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE A-1 SDRAM Controller Configuration Setting PLL When using the SDRAM controller, always enable the PLL. Refer to "PLL" in Section II-6, "CLG (Clock Generator)", for setting the PLL. The following shows the operating range of the SDRAM controller when the PLL is enabled. #X2SPD pin = "1" (x1 speed mode): 25 MHz max. (CPU operating frequency = 25 MHz), voltage 3.30.3 V #X2SPD pin = "0" (x2 speed mode): 17.5 MHz max. (CPU operating frequency = 20 MHz), voltage 3.30.3 V BCU Configuration The SDRAM interface control registers are allocated to addresses 0x39FFC0-0x39FFCA in area 6. Therefore, before the control registers can be accessed, the BCU must be set up following the procedure described below. 1. CEFUNC[1:0] (D[A:9])/DRAM timing set-up register (0x48130) = "00" (default) or "01" Set CEFUNC[1:0] = "00" to use SDRAM in areas 7/8 or CEFUNC[1:0] = "01" to use SDRAM in areas 13/14. Table 2.3 Switching of #CE Output Pin #CE7/#SDCE0 #CE8/#SDCE1 CEFUNC = "00" #CE7/#SDCE0 #CE8/#SDCE1 CEFUNC = "01" CEFUNC = "1x" #CE13/#SDCE0 #CE13/#SDCE0 #CE14/#SDCE1 #CE14/#SDCE1 (Default: CEFUNC = "00") 2. A6IO (D9)/Access control register (0x48132) = "1" This ensures that the internal devices are accessed in area 6. 3. A6WT[2:0] (D[A:8])/Areas 6-4 set-up register (0x4812A) = "010" This causes two wait cycles to be inserted when accessing area 6. With a different number of wait cycles, data may not be written to the control registers normally. 4. SWAITE (D0)/Bus control register (0x4812E) = "1" This enables the #WAIT signal. The IC's internal #WAIT signal is used when powering up the SDRAM. 5. A6EC (D1)/Access control register (0x48132) = LCDCEC (D0)/LCDC system control register (0x39FFFD) Use these registers to match endian types when reading out area 6 and SDRAMC/LCDC. Both bits select little endian when "0" or big endian when "1". When the above settings are finished, the SDRAM control registers in area 6 can be accessed. Next, set areas 7/8 or areas 13/14 in which SDRAMs are connected. A. When using areas 7/8 (CEFUNC = "00") Note: The same settings as those shown above are omitted. A-1. A8IO (DA)/Access control register (0x48132) = "1" This sets areas 7/8 for internal access. A-2. A8WT[2:0] (D[2:0])/Areas 8-7 set-up register (0x48128) = "000" This sets areas 7/8 for no-wait access. A-3. A8SZ (D6)/Areas 8-7 set-up register (0x48128) = SDRSZ (D6)/SDRAM advanced control register (0x39FFC9) Use these registers to ensure that the device size of areas 7/8 and that of the SDRAM controller are the same, and are matched to the SDRAM data width. Both bits select 16 bits when "0" or 8 bits when "1". A-4. A8DF[1:0] (D[5:4])/Areas 8-7 set-up register (0x48128) If the system has an external memory device other than an SDRAM connected to it and accesses that memory device and SDRAM in succession, set the output disable delay time of areas 7/8 to 2.5 cycles (A8DF[1:0] = "10"). When only the SDRAM is read and no other external device is accessed, set the output disable delay time of areas 7/8 to 0.5 cycles (A8DF[1:0] = "00") in order to reduce the SDRAM access time. S1C33L03 FUNCTION PART EPSON B-VI-2-5 B-VI SDRAM VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE B. When using areas 13/14 (CEFUNC = "01") B-1. A14IO (DD)/Access control register (0x48132) = "1" This sets areas 13/14 for internal access. B-2. A14WT[2:0] (D[2:0])/Areas 14-13 set-up register (0x48122) = "000" This sets areas 13/14 for no-wait access. B-3. A14SZ (D6)/Areas 14-13 set-up register (0x48122) = SDRSZ (D6)/SDRAM advanced control register (0x39FFC9) Use these registers to ensure that the device size of areas 13/14 and that of the SDRAM controller are the same, and are matched to the SDRAM data width. Both bits select 16 bits when "0" or 8 bits when "1". B-4. A14DF[1:0] (D[5:4])/Areas 14-13 set-up register (0x48122) If the system has an external memory device other than an SDRAM connected to it and accesses that memory device and SDRAM in succession, set the output disable delay time of areas 13/14 to 2.5 cycles (A14DF[1:0] = "10"). When only the SDRAM is read and no other external device is accessed, set the output disable delay time of areas 13/14 to 0.5 cycles (A14DF[1:0] = "00") in order to reduce the SDRAM access time. This completes the BCU settings necessary to access the SDRAM. Make sure the BCU parameters other than those discussed above are set appropriately for the system. SDRAM Setting Conditions The SDRAM interface allows the following conditions to be selected. Although SDRAM can be used in areas 7 and 8 or areas 13 and 14, these conditions are applied to all four areas and cannot be set individually for each area. Table 2.4 SDRAM Interface Parameters Parameter Selectable condition Initial setting Area 7/13 configuration Area 8/14 configuration #CE7/13 pin configuration #CE8/14 pin configuration Page size SDRAM or Another SDRAM or Another #SDCE0 or #CE7/13 #SDCE1 or #CE8/14 256, 512 or 1K Another device Another device #CE7/13 #CE8/14 256 Row addressing range 2K, 4K or 8K 2K Number of banks 4 or 2 2 Initial command sequence 1. Precharge 2. Refresh 3. Mode register Burst length CAS latency tRAS 1. Precharge 2. Refresh 3. Mode register or 1. Precharge 2. Mode register 3. Refresh 1, 2, 4 or 8 2 1 to 8 clocks 8 -* 8 clocks tRP 1 to 4 clocks 4 clocks tRC 1 to 8 clocks 8 clocks tRCD 1 to 4 clocks 4 clocks tRSC tRRD 1 or 2 clocks 1 to 4 clocks 2 clocks 4 clocks Control bits SDRAR0(D7)/SDRAM area configuration register(0x39FFC0) SDRAR1(D6)/SDRAM area configuration register(0x39FFC0) SDRPC0(D3)/SDRAM area configuration register(0x39FFC0) SDRPC1(D2)/SDRAM area configuration register(0x39FFC0) SDRCA[1:0](D[6:5]) /SDRAM address configuration register(0x39FFC2) SDRRA[1:0](D[3:2]) /SDRAM address configuration register(0x39FFC2) SDRBA(D1) /SDRAM address configuration register(0x39FFC2) SDRIS(D4)/SDRAM control register(0x39FFC1) SDRBL[1:0](D[3:2])/SDRAM mode set-up register(0x39FFC3) SDRCL[1:0](D[6:5])/SDRAM mode set-up register(0x39FFC3) SDRTRAS[2:0](D[7:5])/SDRAM timing set-up register 1 (0x39FFC4) SDRTRP[1:0](D[4:3])/SDRAM timing set-up register 1 (0x39FFC4) SDRTRC[2:0](D[2:0])/SDRAM timing set-up register 1 (0x39FFC4) SDRTRCD[1:0](D[7:6])/SDRAM timing set-up register 2 (0x39FFC5) SDRTRSC(D5)/SDRAM timing set-up register 2 (0x39FFC5) SDRTRRD[1:0](D[4:3])/SDRAM timing set-up register 2 (0x39FFC5) Always set CAS latency to 2. B-VI-2-6 EPSON S1C33L03 FUNCTION PART VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE A-1 Memory Configuration Use the registers described below to select the area in which SDRAMs are connected and the chip enable output pin to be used for SDRAMs. Selecting areas Area 7 or 13: SDRAR0 (D7)/SDRAM area configuration register (0x39FFC0) Area 8 or 14: SDRAR1 (D6)/SDRAM area configuration register (0x39FFC0) Writing "1" to SDRARx sets the corresponding area for SDRAM use. When SDRARx = "0" (default), the area is used for devices other than SDRAM that are controlled only by the BCU. Selecting chip enable #SDCE0(#CE7/13): SDRPC0 (D3)/SDRAM area configuration register (0x39FFC0) #SDCE1(#CE8/14): SDRPC1 (D2)/SDRAM area configuration register (0x39FFC0) Writing "1" to SDRPCx sets the corresponding pin for SDRAM chip enable output. When SDRPCx = "0" (default), the pin is used for devices other than SDRAM that are controlled only by the BCU. Although #SDCE0 and #SDCE1 are assigned to the #CE7 and #CE8 pins, respectively, they are not necessarily fixed to either area. For example, even when using area 7 or 13 for SDRAMs, the chip enable used for the SDRAM can be #SDCE1 (#CE8/14). Table 2.5 lists the chip enable address ranges and the SDRAM sizes that can be connected when the area(s) and chip enable are selected according to the above. Table 2.5 Chip Enable Configuration CEFUNC XX 00 (default) 01 10 11 SDRAR0 SDRAR1 SDRPC0 SDRPC1 #SDCE0 address range #SDCE1 address range SDRAM size (16-bit) 0 X 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 1 1 1 0 X 0 0 0 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 X 0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 X 0 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 N/A N/A Area 7 N/A Area 7 Area 8 N/A N/A Area 7&8 N/A Area 7 Area 13 N/A Area 13 Area 14 N/A N/A Area 13&14 N/A Area 13 N/A N/A N/A Area 7 N/A N/A Area 8 Area 8 N/A Area 7&8 Area 8 N/A Area 13 N/A N/A Area 14 Area 14 N/A Area 13&14 Area 14 0 0 2MB 2MB 2MB 2MB 2MB 2MB 4MB 4MB 2MB x 2 16MB 16MB 16MB 16MB 16MB 16MB 32MB 32MB 16MB x 2 Area 7 = 0x400000-0x5FFFFF, Area 8 = 0x600000-0x7FFFFF, Area 7&8 = 0x400000-0x7FFFFF Area 13 = 0x2000000-0x2FFFFFF, Area 14 = 0x3000000-0x3FFFFFF, Area 13&14 = 0x2000000-0x3FFFFFF B-VI SDRAM S1C33L03 FUNCTION PART EPSON B-VI-2-7 VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE Bank, row, and column address configuration An SDRAM memory array consists of two or four banks, with each bank divided into pages. For this reason, SDRAMs have a bank select pin which is not found in asynchronous DRAMs. Inside the Bank, the Column (Page) address and the Row address are selected by #CAS and #RAS, respectively, in the same way as with asynchronous DRAMs. For the SDRAM addresses to be generated correctly, it is necessary that the bank size and the column and row address ranges be set in the SDRAM controller according to the SDRAMs used. For these settings, use the registers shown below. Bank size: SDRBA (D1)/SDRAM address configuration register (0x39FFC2) Column addressing range: SDRCA[1:0] (D[6:5])/SDRAM address configuration register (0x39FFC2) Row addressing range: SDRRA[1:0] (D[3:2])/SDRAM address configuration register (0x39FFC2) Table 2.6 Setting Bank Size SDRBA Number of banks Bank address (pin) used 0 1 2 4 SDBA0 (default) SDBA0-SDBA1 Table 2.7 Setting Column Addressing Range (Page Size) SDRCA1 SDRCA0 Column size Column address (pin) used 0 0 1 1 0 1 0 1 256 512 1,024 - SDA0-SDA7 (default) SDA0-SDA8 SDA0-SDA9 - SDRRA1 SDRRA0 Row size Row address (pin) used 0 0 1 1 0 1 0 1 2K 4K 8K - SDA0-SDA10 (default) SDA0-SDA11 SDA0-SDA12 - Table 2.8 Setting Row Addressing Range The SDRAM controller uses only the lower 24 bits of the 28-bit address bus. The relationship between the CPU addresses and the Bank, Column, and Row addresses is shown below. 16-bit SDRAM interface (SDRSZ = "1") A(m+n+p) A(m+n+1) Bank address A(m+n) *** A(m+1) Row address A(m) *** Column address A1 A0 DQM When reading/writing byte data, the SDRAM controller decodes A0/BSL and WRH/BSH into LDQM and HDQM. 8-bit SDRAM interface (SDRSZ = "0") A(m+n+p-1) A(m+n) Bank address A(m+n-1) *** Row address A(m) A(m-1) *** Column address A0 m: Column address size (number of bits) n: Row address size (number of bits) p: Bank address size (number of bits) Upper address bits that are not used (depending on memory size) are all set to 0s. In cases when two areas are selected (SDRAR[1:0] = "11") and only one chip enable is enabled (SDRPC[1:0] = "01" or "10"), the MSB of the bank address (A(m+n+p) for 16 bits or A(m+n+p-1) for 8 bits) is replaced with the value shown below. * Value is "0" when accessing area 7/13 * Value is "1" when accessing area 8/14 B-VI-2-8 EPSON S1C33L03 FUNCTION PART VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE A-1 Selecting initialization sequence The SDRAM command sequence that is run immediately after SDRAM power-up can be selected to suit the specifications of the SDRAM used. For this setting, use the SDRIS (D4)/SDRAM control register (0x39FFC1). SDRIS = "0": 1. Precharge 2. Refresh 3. Mode Register Set SDRIS = "1": 1. Precharge 2. Mode Register Set 3. Refresh If no problems are incurred in either setting, SDRIS = "1" is recommended. Burst length The burst length can be selected using the SDRBL[1:0] (D[3:2])/SDRAM mode set-up register (0x39FFC3). Table 2.9 Setting Burst Length SDRBL1 SDRBL0 Burst length (word) 0 0 1 1 0 1 0 1 1 2 4 8 (default) Notes: * Burst transfers are effective only when reading data from SDRAM. When writing to SDRAM, data are always written in a single operation, not in bursts, no matter what burst length is selected. * The SDRAM controller is designed in such a way that when one cycle of burst read is finished, it automatically issues the READ command to continue with transfers. Therefore, unless SDRBL[1:0] = "00", the speed at which SDRAM is accessed does not vary with the burst length involved. Setting CAS latency The CAS latency is defined by the number of clock cycles before data is output from SDRAM after issuing the READ command and this SDRAM controller supports only 2 clocks of CAS latency. Set the SDRCL[1:0] (D[6:5])/SDRAM mode set-up register (0x39FFC3) to "10" (CAS latency = 2) before accessing the SDRAM. BCLK Command NOP ACTV NOP READ NOP SDCKE #SDCEx #SDRAS #SDCAS #SDWE SDBA[1:0] BA BA SDA[12:0] ROW COL DATA DQ[15:0] tRCD CAS latency = 2 Figure 2.5 CAS Latency B-VI SDRAM S1C33L03 FUNCTION PART EPSON B-VI-2-9 VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE Enabling/disabling bank interleaved access A bank cannot be accessed at the same time it is being precharged, so another bank may be accessed during that period, which results in increased access speed. For this purpose, the SDRAM controller supports a feature known as Bank Interleaved Access. Specify whether or not to use this feature with the SDRBI (D5)/SDRAM advanced control register (0x39FFC9). SDRBI = "1": Bank interleaved access function is used SDRBI = "0": Bank interleaved access function is not used (one bank only is accessed at a time) When SDRBI = "0" (CAS latency = 2, tRCD = 2) BCLK Command SDCKE ACTV READ NOP PRE NOP ACTV NOP READ NOP PRE NOP ACTV H #SDCEx #SDRAS #SDCAS #SDWE SDBA[1:0] BA1 SDA[10] ROW1 SDA[12:11, 9:0] ROW1 BA1 BA1 BA2 BA2 BA2 ROW2 COLn BA1 ROW3 CONm ROW2 ROW3 LDQM/HDQM DQ[15:0] D(n) Bank 1 Active Read D(m) Precharge Bank 2 Read Active When SDRBI = "1" Precharge (CAS latency = 2, tRCD = 2) BCLK Command ACTV ACTV BA1 BA2 SDA[10] ROW1 ROW2 SDA[12:11, 9:0] ROW1 ROW2 SDCKE READ NOP READ NOP PRE NOP ACTV NOP READ NOP H #SDCEx #SDRAS #SDCAS #SDWE SDBA[1:0] BA1 BA2 BA1 BA1 BA1 ROW3 COLn COLm COLl ROW3 LDQM/HDQM DQ[15:0] Bank 1 D(n) Active Read Bank 2 D(l) Precharge Read Active tRRD D(m) CAS latency =2 tRP (Bank 1 cannot be accessed) Figure 2.6 Bank Interleaved Access When SDRBI is set to "0", the SDRAM controller issues the precharge command every time the bank to be accessed is changed. This reduces current consumption than that of the bank interleaved access, so set SDRBI to "0" if bank is hardly changed through a series of access. B-VI-2-10 EPSON S1C33L03 FUNCTION PART VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE A-1 Timing setup The following parameters can be set in conformity with SDRAM specifications before use. Table 2.10 SDRAM Parameters Symbol tRC Set values (# of clocks) SDRAM parameter tRCD ACTIVE to ACTIVE command period AUTO REFRESH command period Exit SELF REFRESH to ACTIVE command period ACTIVE to PRECHARGE command period Minimum SELF REFRESH period ACTIVE to READ or WRITE delay time tRP PRECHARGE command period 1 to 4 tRRD ACTIVE bank (a) to ACTIVE bank (b) period 1 to 4 tRSC MODE REGISTER SET cycle time 1 or 2 tRAS Control bits 1 to 8 SDRTRC[2:0] (D[2:0])/SDRAM timing set-up register 1 (0x39FFC4) 1 to 8 SDRTRAS[2:0] (D[7:5])/SDRAM timing set-up register 1 (0x39FFC4) SDRTRCD[1:0] (D[7:6])/SDRAM timing set-up register 2 (0x39FFC5) SDRTRP[1:0] (D[4:3])/SDRAM timing set-up register 1 (0x39FFC4) SDRTRRD[1:0] (D[4:3])/SDRAM timing set-up register 2 (0x39FFC5) SDRTRSC (D5)/SDRAM timing setup register 2 (0x39FFC5) 1 to 4 BCLK Command NOP ACTV NOP READ NOP BA BA SDA[12:11, 9:0] ROW COL SDA10 ROW SDBA[1:0] NOP NOP PRE NOP ACTV BA BA ROW BKsel ROW DATA DATA DATA DATA DQ[15:0] tRCD CAS latency tRAS tRP tRC (Burst length = 4) (a) Burst read BCLK Command NOP ACTV NOP READ NOP ACTV NOP READ NOP BAa BAa BAb BAb SDA[12:11, 9:0] ROWa COLa ROWb COLb SDA10 ROWa SDBA[1:0] NOP ROWb Da DQ[15:0] Da+1 tRRD Da+2 Da+3 Db (Burst length = 4) (b) Bank interleaved access Figure 2.7 SDRAM Parameters Note: When the auto-refresh command is executed, the following command may be issued 3 or 4 CPU_CLK cycles from that point regardless of the tRC value set in the SDRTRC[2:0] (D[2:0])/SDRAM timing set-up register 1 (0x39FFC4). Therefore, use SDRAMs with 75 ns or less of tRC. B-VI SDRAM S1C33L03 FUNCTION PART EPSON B-VI-2-11 VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE SDRAM Operation Synchronous Clock The SDRAM controller uses the BCLK pin as it outputs the SDRAM clock. To CPU #X2SPD pin PLLS[1:0] pins Bus clock CLKDT[1:0] CLKCHG CLG High-speed (OSC3) oscillation circuit BCU OSC3_CLK A 1/1-1/8 CPU_CLK BCLKSEL[1:0] 1/1 or 1/2 PLL_CLK PLL BCU_CLK CPU_CLK OSC3_CLK PLL_CLK SDRENA BCLK pin SDRAMC Low-speed (OSC1) oscillation circuit 1/1 or 1/2 SD_CLK Refresh counter Figure 2.8 SDRAM Clock System Normally output from the BCLK pin is a clock selected with the BCU's BCLKSEL[1:0] (D[1:0])/BCLK select register (0x4813A) (which is, by default, the CPU clock). Before SDRAM can be used, the SDRAM clock can be enabled for output by writing "1" to the SDRENA (D7)/SDRAM control register (0x39FFC1). The SDRAM clock has its frequency determined by how the #X2SPD pin is set, as does the BCU operating clock (BCU_CLK). #X2SPD = "1": CPU-SDRAM clock ratio is set to 1 : 1. The SDRAM clock and the CPU system clock will be the same. #X2SPD = "0": CPU-SDRAM clock ratio is set to 2 : 1. The SDRAM clock frequency becomes half of the CPU system clock. While the SDRAM is self-refreshed, the SDRAM clock output can be turned off in order to reduce the chip's current consumption. To set this feature, use the SDRCLK (D3)/SDRAM control register (0x39FFC1). SDRCLK = "1": The BCLK pin always outputs SDRAM clock (default). SDRCLK = "0": The BCLK pin is fixed low while the SDRAM is self-refreshed. It is placed in the highimpedance state while control of the bus is released. When #X2SPD = "1" #SDCEx OSC3 (CPU_CLK) BCLK (BCU_CLK) BCLK (SD_CLK when SDRCLK = "1") BCLK (SD_CLK when SDRCLK = "0") SDCKE Self refresh Access to the SDRAM Access to other external memory Access to the internal memory When #X2SPD = "0" #SDCEx OSC3 (CPU_CLK) BCLK (BCU_CLK) BCLK (SD_CLK when SDRCLK = "1") BCLK (SD_CLK when SDRCLK = "0") SDCKE Self refresh Access to the SDRAM Access to other external memory Access to the internal memory Figure 2.9 SDRAM Clock Operation B-VI-2-12 EPSON S1C33L03 FUNCTION PART VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE A-1 Power-up and Initialization The following describes the processing sequence for powering up the SDRAM. 1. Setting the BCU and SDRAM access conditions Set the BCU and the SDRAM controller as explained in "SDRAM Configuration". 2. SDRENA (D7)/SDRAM control register (0x39FFC1) = "1" This causes the pins shown in Table 2.1 to be switched for SDRAM signal use. (The contents set in the port function select and port function extension registers do not affect this switching.) Also, the BCLK pin starts outputting the SDRAM clock. Until this stage, the SDRAM pins shared with I/O ports are set for general-purpose input and placed in the highimpedance state. If the power to the SDRAM is designed to be turned on simultaneously with the CPU, the SDCKE (P20), HDQM (P32), and LDQM (P15) pins left floating may adversely affect the SDRAM, depending on its specifications. (For example, unnecessary data may be output.) In such a case, these pins must be pulled high, external to the chip. If the CPU and SDRAM are powered from separate power supplies and the power to the SDRAM is turned on after writing "1" to SDRENA, the problem mentioned above does not occur, because the signals for SDRAM use are being output. 3. Wait for 100 s or more after turning on the power to the SDRAM After the power to the SDRAM is turned on, the SDRAM must be held in an NOP state (#SDCEx = high) for at least 100 s. Because the duration of this period varies with each SDRAM, consult the specifications for your SDRAM. 4. SDRINI (D6)/SDRAM control register (0x39FFC1) = "1" This causes the SDRAM controller to output the commands in the order specified by the SDRIS (D4)/SDRAM control register (0x39FFC1) in order to initialize the SDRAM. (Data are not initialized.) SDRIS = "0": 1. Precharge 2. Refresh 3. Mode Register Set SDRIS = "1": 1. Precharge 2. Mode Register Set 3. Refresh Writing "1" to SDRINI has no effect when SDRENA = "0". 5. Checking SDRMRS (D7)/SDRAM status register (0x39FFCA) SDRMRS is reset to "1" after power-on, and is set to "0" by executing the MRS (Mode Register Set) command. Because the MRS command uses an external address bus, no other external devices can be accessed until its output is finished. The SDRAM controller asserts the #WAIT signal provided for the user logic and keeps it active until the MRS command output is finished after writing "1" to SDRINI, thus disabling external access during that time. The CPU also ignores the no-wait access specified by SWAITE (D0/0x4812E) = "0". Before initiating external access, however, be sure to check that SDRMRS is set to "0". In addition to being reset at power-on, SDRMRS is reset to "1" by writing "0" to SDRENA or writing "1" to SDRINI. This completes the SDRAM initialization sequence, allowing access to the SDRAM. B-VI SDRAM S1C33L03 FUNCTION PART EPSON B-VI-2-13 VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE SDRAM power VCC(Min.) BCLK NOP Command PALL MRS REF REF CMD H SDCKE #SDCEx #SDRAS #SDCAS #SDWE H HDQM/LDQM SDRENA bit SDRIS bit SDRINI bit SDRMRS bit Internal #WAIT SDA10 Valid Valid SDBA[1:0] Valid Valid SDA[12:11, 9:0] Valid Valid 100 s min. tRP tRSC tRC tRC Figure 2.10 SDRAM Power-up and Initialization SDRAM Commands The SDRAM is controlled by commands that are comprised of a combination of high or low logic level signals. Table 2.11 lists the commands output by the SDRAM controller. Table 2.11 List of the Supported SDRAM Commands Command Function Bank Active Bank Precharge Precharge All Write Read Mode Register Set Deselect / NOP Auto Refresh Self Refresh Entry Self Refresh Exit Data Write/Output Enable Data Write/Output Disable Symbol SDCKE DQM H/LDQM Bank A[15:14] SDA10 ACTV PRE PALL WRIT READ MRS NOP REF SELF - H H H H H H H H HL LH X X X X X X X X X X V V X V V V X X X X V L H L L V X X X X - H L X - H H X Pins SDA A[13:12] A[10:1] #SDCEx #SDRAS #SDCAS #SDWE V X X V V V X X X X L L L L L L H L L H L L L H H L X L L X H H H L L L X L L X H L L L H L X H H X X X X X X X X X X X X X V = valid, X = don't care, L = low level, H = high level Because all of these commands are output by the SDRAM controller as necessary, they do not need to be controlled by a user program, except for the commencement of initialization by SDRINI. B-VI-2-14 EPSON S1C33L03 FUNCTION PART VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE A-1 Burst Read Cycle Except when the burst length is set to 1 (SDRBL[1:0] "00"), the SDRAM controller always reads data from the SDRAM in bursts. Figure 2.11 shows several examples of timing charts when reading out 4-word data from the same row address in varying burst lengths. Example of parameter settings: CAS latency = 2, tRCD = 2 cycles, tRP = 2 cycles (1) Burst length = 8 BCLK Command SDCKE NOP PRE NOP ACTV NOP READ NOP H #SDCEx #SDRAS #SDCAS #SDWE SDBA[1:0] BA BA BA SDA[10] ROW SDA[12:11, 9:0] ROW COL LDQM/HDQM DQ[15:0] D(1) tRP tRCD D(2) D(3) D(4) D(2) D(3) D(4) D(5) D(6) CAS latency =2 (2) Burst length = 4 BCLK Command SDCKE NOP PRE NOP ACTV NOP READ NOP H #SDCEx #SDRAS #SDCAS #SDWE SDBA[1:0] BA BA BA SDA[10] ROW SDA[12:11, 9:0] ROW COL LDQM/HDQM DQ[15:0] D(1) tRP tRCD CAS latency =2 (3) Burst length = 2 BCLK Command SDCKE NOP PRE NOP ACTV NOP READ NOP READ NOP H #SDCEx #SDRAS #SDCAS #SDWE SDBA[1:0] BA BA SDA[10] ROW SDA[12:11, 9:0] ROW BA BA COL1 COL2 B-VI LDQM/HDQM DQ[15:0] SDRAM D(1-1) D(1-2) D(2-1) D(2-2) tRP tRCD CAS latency CAS latency =2 =2 Figure 2.11 Burst Read in the Same Page S1C33L03 FUNCTION PART EPSON B-VI-2-15 VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE Figure 2.12 shows an example of a timing chart in cases where the row address is varied during burst read. BCLK Command NOP SDCKE PRE NOP ACTV NOP READ NOP PRE NOP ACTV NOP READ NOP H #SDCEx #SDRAS #SDCAS #SDWE SDBA[1:0] BA BA BA SDA[10] ROW1 SDA[12:11, 9:0] ROW1 BA BA BA ROW2 COLn ROW2 COL0 LDQM/HDQM DQ[15:0] D(n) tRP tRCD D(n+1) D(n+2) D(0) tRP CAS latency =2 tRCD D(1) D(2) CAS latency =2 tRAS Figure 2.12 Changing Row Address During Burst Read Single Read/Single Write If the burst length is set to "1" (SDRBL[1:0] = "00"), the SDRAM controller reads data from the SDRAM in a single operation. When writing to the SDRAM, data are always written in a single operation, no matter what burst length is selected. BCLK Command NOP SDCKE PRE NOP ACTV NOP READ NOP PRE NOP ACTV NOP WRIT H #SDCEx #SDRAS #SDCAS #SDWE SDBA[1:0] BA1 BA1 BA1 SDA[10] ROW1 SDA[12:11, 9:0] ROW1 BA2 BA2 BA2 ROW2 COL1 ROW2 COL2 LDQM/HDQM DQ[15:0] D(1) tRP tRCD CAS latency =2 D(2) tRP tRCD Figure 2.13 Single Read to Single Write (different page) BCLK Command NOP SDCKE PRE NOP ACTV NOP READ NOP WRIT NOP PRE NOP H #SDCEx #SDRAS #SDCAS #SDWE SDBA[1:0] BA BA SDA[10] ROW1 SDA[12:11, 9:0] ROW1 BA BA COLn COLm BA LDQM/HDQM DQ[15:0] D(n) tRP tRCD D(n+1) D(n+2) D(m) CAS latency =2 Figure 2.14 Burst Read to Single Write (same page) B-VI-2-16 EPSON S1C33L03 FUNCTION PART VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE A-1 Refresh Mode The SDRAM controller supports two SDRAM refresh modes: auto refresh and self-refresh. Auto refresh The SDRAM controller incorporates a 12-bit auto refresh counter. This counter continues counting on OSC3 clock edges, and when a specified count is reached, commands are sent to the SDRAM that precharges and auto-refreshes all banks. The counter is reset at that time, and starts counting for the next refresh period. The counter is also reset by self-refresh. The auto-refresh period is determined by the OSC3 clock frequency and the count value set in the SDRARFC [11:0] (D[B:0])/Auto refresh count register (0x39FFC6). For SDRARFC, set the appropriate value meeting the specifications of your SDRAM. The count value is obtained by the equation below. RFP SDRARFC -------- x fOSC3 - BL - CL - 2 x tRP - tRCD - 3 ROWS RFP: Maximum refresh period [s] ROWS: Row address size fOSC3: OSC3 clock frequency [Hz] BL: Burst length [word] CL: CAS latency [Number of SD_CLK cycles] PRECHARGE command period [Number of SD_CLK cycles] tRP: tRCD: ACTIVE to READ or WRITE delay time [Number of SD_CLK cycles] If RFP = 64 ms, ROWS = 4,096, fOSC3 = 20 MHz, BL = 8, CL = 3, tRP = 4, and tRCD = 4, for example, the value to set is calculated as follows: 0.064 SDRARFC -------- x 20,000,000 - 8 - 3 - 2 x 4 - 4 - 3 = 286 4,096 Therefore, set any value equal to or less than 286 (0x11E) for SDRARFC. BCLK Command SDCKE NOP PALL NOP REF NOP REF NOP H #SDCEx #SDRAS #SDCAS #SDWE SDBA[1:0] SDA[10] SDA[12:11, 9:0] LDQM/HDQM L DQ[15:0] tRP tRC Figure 2.15 Auto Refresh B-VI SDRAM S1C33L03 FUNCTION PART EPSON B-VI-2-17 VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE Self refresh Self-refresh uses the SDRAM's self-refresh function and does not require clock pulses during the refresh period, thus helping to reduce the chip's power consumption. This self-refresh function is also used for data retention during power-down mode. To cause the SDRAM to be self-refreshed, set the SDRSRF (D5)/SDRAM control register (0x39FFC1) to "1". This enables the SDRAM controller to send the self-refresh command (which sets the SDCKE output to low) to the SDRAM. The command is actually sent a certain time after accessing or auto-refreshing the SDRAM, so the SDRAM controller contains a 4-bit self-refresh counter to count this time. The counter counts on SDRAM clock (SD_CLK) edges, and when the designated count is reached, the SDRAM controller sends the refresh command to the SDRAM. When an SDRAM access or auto-refresh command is issued, the counter is reset and starts counting again. The designated value for the counter can be specified in a range of 2 to 15 by using the SDRSRFC[3:0] (D[3:0])/SDRAM self refresh count register (0x39FFC8). Always set the SDRAM self refresh count register to 2 or more. If it is set to less than 2, the SDRAM cannot exit self-refresh mode. When an SDRAM access occurs during self-refresh mode, SDCKE is returned high and the SDRAM is taken out of self-refresh mode. The SDRAM clock stops when SDRCLK = "0". BCLK Command NOP PALL NOP SELF NOP SDCKE #SDCEx #SDRAS #SDCAS #SDWE SDBA[1:0] SDA[10] SDA[12:11, 9:0] LDQM/HDQM L DQ[15:0] SDRSRM tRP 1 clock cycle Self refresh mode Enters self refresh mode Exits self refresh mode Figure 2.16 Self Refresh During self-refresh (while SDCKE = low), the SDRSRM (D6)/SDRAM status register (0x39FFCA) remains "0". Therefore, it is possible to determine whether or not self-refresh is in operation by reading this status register. Furthermore, SDRAM clock output during self-refresh can be turned off in order to reduce the chip's power consumption by setting the SDRCLK (D3)/SDRAM control register (0x39FFC1) to "0". B-VI-2-18 EPSON S1C33L03 FUNCTION PART VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE A-1 Power-down Mode The SDRAM controller supports three power-down modes for the S1C33 Core (HALT, HALT2, and SLEEP). In HALT mode, the bus clock is not turned off. Therefore, this mode can be set at any time. In HALT2 and SLEEP modes, the SDRAM's auto-refresh function is disabled. Therefore, the SDRAM must be placed in self-refresh mode before entering HALT2 or SLEEP mode, by following the procedure described below. 1. Set SDRSRF (D5/0x39FFC1) to "1" in order to enable the SDRAM's self-refresh function. 2. Check to see that SDRSRM (D6/0x39FFCA) = "0" (i.e., SDRAM is being self-refreshed). 3. Execute the HALT or SLP instruction. Because the OSC3 clock is required for the SDRAM controller to be able to operate, the SDRAM must also be placed in self-refresh mode following the above procedure before switching the CPU clock to OSC1 or turning the OSC3 clock off. Note: Because the SDRAM is taken out of self-refresh mode when accessed, steps 2 and 3 of the above procedure must be executed on other memory than SDRAMs. Bus Release Procedure When the CPU releases the external bus, all of the SDRAM signal input/output pins, except for BCLK output when SDRCLK = "1", are placed in the high-impedance state or set for input mode. As a result, another device acting as the bus master gains control of the SDRAM. The following illustrates a procedure where control of the SDRAM is switched. BCLK INTX (external device) Synchronization #BUSREQ Synchronization #BUSACK S1C33 terminates the current bus cycle. 1 cycle 1 cycle The external bus master controls bus cycles. 1 cycle S1C33 controls bus cycles. D[15:0] Hi-Z A[23:0], #RD, #WR SDRAM status CKE (external device) Self refresh CMD Self refresh Hi-Z Hi-Z Hi-Z SDCKE (S1C33) SDRAM control (S1C33) CMD SDRAM control (external device) Hi-Z Self refresh Hi-Z Self refresh CMD Self refresh Self refresh Hi-Z Figure 2.17 Bus Release Procedure B-VI SDRAM S1C33L03 FUNCTION PART EPSON B-VI-2-19 VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE 1. The device acting as the external bus master prompts the S1C33 to be prepared to release the bus by means of an interrupt or some other means. 2. When the S1C33 becomes ready to release the bus, it sets SDRSRF (D5/0x39FFC1) to "1" to place the SDRAM in self-refresh mode. The S1C33 should stop accessing the SDRAM thereafter. 3. After the SDRAM is placed in self-refresh mode, the external device outputs a bus request. 4. Simultaneously with 3, the external device pulls the SDCKE signal low to ensure that the SDRAM will not be taken out of self-refresh mode when the bus is released. 5. In response to the bus request, the S1C33 releases the external bus. The external bus, including the SDRAM interface pins, goes to a high-impedance state. 6. The external bus master takes over control of the SDRAM. If SDRCLK (D3/0x39FFC1) = "1", a clock for the SDRAM is output from the BCLK pin. Therefore, the external bus master must control the SDRAM synchronously with that clock. If SDRCLK = "0", BCLK also goes to a high-impedance state at the same time the bus is released. Therefore, the external bus master supplies a clock to the SDRAM. Note: If the SDRAM is not accessed after the bus is released, pull the SDRAM's CKE pin down to low to keep the self-refresh mode in order to maintain the SDRAM data while the bus is released. B-VI-2-20 EPSON S1C33L03 FUNCTION PART VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE A-1 I/O Memory of SDRAM Interface Table 2.12 shows the control bits of the SDRAM interface. These registers are mapped into area 6 (0x39FFC0 to 0x39FFCA). Table 2.12 Control Bits of SDRAM Interface Register name Address SDRAM area configuration register 039FFC0 (B) SDRAM 039FFC1 control register (B) Bit Name Area 7/13 configuration Area 8/14 configuration reserved #CE7/13 pin configuration #CE8/14 pin configuration reserved 1 SDRAM 1 SDRAM D7 D6 D5 D4 SDRENA SDRINI SDRSRF SDRIS Enable SDRAM signals Start SDRAM power up Enable SDRAM self-refresh Initial command sequence 1 1 1 1 039FFC2 D7 - (B) D6-5 SDRCA1 SDRCA0 D4 - D3-2 SDRRA1 SDRRA0 D1 D0 SDRAM mode set-up register SDRBA - 039FFC3 D7 - (B) D6-5 SDRCL1 SDRCL0 D4 - D3-2 SDRBL1 SDRBL0 D1-0 - SDRAM timing set-up register 1 Setting SDRAR0 SDRAR1 - SDRPC0 SDRPC1 - D3 SDRCLK D2-0 - SDRAM address configuration register Function D7 D6 D5-4 D3 D2 D1-0 Keep SDCLK during self-refresh reserved reserved SDRAM page size (column range) 0 #CE7/13 0 #CE8/14 - Enabled 0 Start 0 Enabled 0 1 precharge 0 2 set reg. 3 refresh 1 Kept 0 - Disabled - Disabled 1 precharge 2 refresh 3 set reg. Stopped - reserved SDRAM row addressing range Number of SDRAM banks reserved reserved SDRAM CAS latency Page size reserved 1K (SDA[9:0]) 512 (SDA[8:0]) 256 (SDA[7:0]) - SDRRA[1:0] Addressing range 1 1 reserved 1 0 8K (SDA[12:0]) 0 1 4K (SDA[11:0]) 0 0 2K (SDA[10:0]) 1 4 banks 0 2 banks - SDRCL[1:0] 1 0 reserved SDRAM burst length SDRBL[1:0] 1 1 1 0 0 1 0 0 reserved - CAS latency 2 CAS latency - Burst length 8 4 2 1 - SDRTRAS[2:0] Number of clocks 1 1 1 7 1 1 0 6 1 0 1 5 1 0 0 4 0 1 1 3 0 1 0 2 0 0 1 1 0 0 0 8 SDRTRP[1:0] Number of clocks 1 1 3 1 0 2 0 1 1 0 0 4 SDRTRC[2:0] Number of clocks 1 1 1 7 1 1 0 6 1 0 1 5 1 0 0 4 0 1 1 3 0 1 0 2 0 0 1 1 0 0 0 8 SDRAM tRP spec D2-0 SDRTRC2 SDRAM tRC spec SDRTRC1 SDRTRC0 S1C33L03 FUNCTION PART - 1 #SDCE0 1 #SDCE1 SDRCA[1:0] 1 1 1 0 0 1 0 0 039FFC4 D7-5 SDRTRAS2 SDRAM tRAS spec (B) SDRTRAS1 SDRTRAS0 D4-3 SDRTRP1 SDRTRP0 Init. R/W 0 Not SDRAM 0 Not SDRAM EPSON Remarks 0 0 - 0 0 - R/W R/W - 0 when being read. R/W R/W - 0 when being read. 0 0 0 0 R/W R/W 0 when being read. R/W R/W 1 - R/W - 0 when being read. - 0 0 - 0 when being read. R/W - 0 0 - 0 when being read. R/W 0 - R/W - 0 when being read. - 1 1 - 1 1 - 0 when being read. R/W - 0 when being read. R/W - - 0 0 0 R/W 0 0 R/W 0 0 0 R/W 0 when being read. B-VI SDRAM B-VI-2-21 VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE Register name Address SDRAM timing set-up register 2 Bit Name Function 039FFC5 D7-6 SDRTRCD1 SDRAM tRCD spec (B) SDRTRCD0 0 0 0 R/W R/W - - - 0 to 4096 - 1 1 1 1 1 1 1 1 1 1 1 1 - 0 when being read. R/W - 2 to 15 - 1 1 1 1 - 0 when being read. R/W This register must not be set less than "0x02". reserved - 1 8 bits 0 16 bits SDRAM data path bit width SDRAM bank interleaved access 1 Interleaved 0 One bank - reserved - 0 0 - - 0 when being read. R/W R/W - 0 when being read. SDRAM mode register set flag SDRAM current refresh mode reserved 1 1 - reserved 039FFC6 DF-C - reserved (HW) DB SDRARFC11 SDRAM auto refresh count [11:0] DA SDRARFC10 D9 SDRARFC9 D8 SDRARFC8 D7 SDRARFC7 D6 SDRARFC6 D5 SDRARFC5 D4 SDRARFC4 D3 SDRARFC3 D2 SDRARFC2 D1 SDRARFC1 D0 SDRARFC0 SDRAM self refresh count register 039FFC8 D7-4 - reserved (B) D3 SDRSRFC3 SDRAM self refresh count [3:0] D2 SDRSRFC2 D1 SDRSRFC1 D0 SDRSRFC0 SDRAM advanced control register 039FFC9 (B) SDRAM 039FFCA status register (B) - SDRSZ SDRBI - D7 SDRMRS D6 SDRSRM D5-0 - Remarks R/W SDRAM auto refresh count register D7 D6 D5 D4-0 Init. R/W 0 0 D5 SDRTRSC SDRAM tRSC spec D4-3 SDRTRRD1 SDRAM tRRD spec SDRTRRD0 D2-0 - Setting SDRTRCD[1:0] Number of clocks 1 1 3 1 0 2 0 1 1 0 0 4 1 1 clock 0 2 clocks SDRTRRD[1:0] Number of clocks 1 1 3 1 0 2 0 1 1 0 0 4 - 1 Not finished 0 Done 1 Auto refresh 0 Self refresh - R R - 0 when being read. 0 when being read. Note: Do not access addresses 0x039FFCB to 0x039FFCD, because they are reserved for testing the SDRAM controller. B-VI-2-22 EPSON S1C33L03 FUNCTION PART VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE A-1 Register name Address Bit Areas 14-13 0048122 set-up register (HW) DF-9 D8 D7 D6 D5 D4 Areas 8-7 0048128 set-up register (HW) Name Function Setting - A14DRA A13DRA A14SZ A14DF1 A14DF0 reserved Area 14 DRAM selection Area 13 DRAM selection Areas 14-13 device size selection Areas 14-13 output disable delay time - 0 0 0 1 1 - 0 when being read. R/W R/W R/W R/W D3 D2 D1 D0 - A14WT2 A14WT1 A14WT0 reserved Areas 14-13 wait control - 1 Used 0 Not used 1 Used 0 Not used 1 8 bits 0 16 bits A14DF[1:0] Number of cycles 1 1 3.5 1 0 2.5 0 1 1.5 0 0 0.5 - A14WT[2:0] Wait cycles 1 1 1 7 1 1 0 6 1 0 1 5 1 0 0 4 0 1 1 3 0 1 0 2 0 0 1 1 0 0 0 0 - 1 1 1 - 0 when being read. R/W DF-9 D8 D7 D6 D5 D4 - A8DRA A7DRA A8SZ A8DF1 A8DF0 reserved Area 8 DRAM selection Area 7 DRAM selection Areas 8-7 device size selection Areas 8-7 output disable delay time - - 0 0 0 1 1 - 0 when being read. R/W R/W R/W R/W D3 D2 D1 D0 - A8WT2 A8WT1 A8WT0 reserved Areas 8-7 wait control - 1 1 1 - 0 when being read. R/W - 1 1 - 0 when being read. R/W - 1 1 1 - 0 when being read. R/W - 0 1 1 - 0 when being read. R/W R/W - 1 1 1 - 0 when being read. R/W Areas 6-4 004812A DF-E - set-up register (HW) DD A6DF1 DC A6DF0 reserved Area 6 output disable delay time DB DA D9 D8 - A6WT2 A6WT1 A6WT0 reserved Area 6 wait control D7 D6 D5 D4 - A5SZ A5DF1 A5DF0 reserved Areas 5-4 device size selection Areas 5-4 output disable delay time D3 D2 D1 D0 - A5WT2 A5WT1 A5WT0 reserved Areas 5-4 wait control S1C33L03 FUNCTION PART EPSON 1 Used 1 Used 1 8 bits A8DF[1:0] 1 1 1 0 0 1 0 0 0 Not used 0 Not used 0 16 bits Number of cycles 3.5 2.5 1.5 0.5 - A8WT[2:0] Wait cycles 1 1 1 7 1 1 0 6 1 0 1 5 1 0 0 4 0 1 1 3 0 1 0 2 0 0 1 1 0 0 0 0 - Number of cycles 3.5 2.5 1.5 0.5 - A6WT[2:0] Wait cycles 1 1 1 7 1 1 0 6 1 0 1 5 1 0 0 4 0 1 1 3 0 1 0 2 0 0 1 1 0 0 0 0 - 1 8 bits 0 16 bits A5DF[1:0] Number of cycles 1 1 3.5 1 0 2.5 0 1 1.5 0 0 0.5 A6DF[1:0] 1 1 1 0 0 1 0 0 A5WT[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 Wait cycles 7 6 5 4 3 2 1 0 Init. R/W Remarks B-VI SDRAM B-VI-2-23 VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE Register name Address Bit Bus control register DF DE DD DC DB DA RBCLK - RBST8 REDO RCA1 RCA0 D9 D8 D7 D6 D5 RPC2 RPC1 RPC0 RRA1 RRA0 D4 D3 D2 D1 D0 - SBUSST SEMAS SEPD SWAITE 004812E (HW) Name Function BCLK output control reserved Burst ROM burst mode selection DRAM page mode selection Column address size selection B-VI-2-24 0 Enabled Remarks R/W - Writing 1 not allowed. R/W R/W R/W 0 0 0 0 0 R/W R/W R/W R/W 0 0 0 0 0 - Writing 1 not allowed. R/W R/W R/W R/W - 1 Internal ROM 0 Emulation CEFUNC[1:0] #CE output 1 x #CE7/8..#CE17/18 #CE6..#CE17 0 1 #CE4..#CE10 0 0 1 Successive 0 Normal RPRC[1:0] Number of cycles 1 1 4 1 0 3 0 1 2 0 0 1 - CASC[1:0] Number of cycles 1 1 4 1 0 3 0 1 2 0 0 1 - RASC[1:0] Number of cycles 1 1 4 1 0 3 0 1 2 0 0 1 - 1 0 0 - 0 when being read. R/W R/W 0 0 0 R/W R/W - 0 0 - 0 when being read. R/W - 0 0 - 0 when being read. R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W - 0 when being read. R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W D8 D7 D6 CRAS RPRC1 RPRC0 Successive RAS mode setup DRAM RAS precharge cycles selection D5 D4 D3 - CASC1 CASC0 reserved DRAM CAS cycles selection D2 D1 D0 - RASC1 RASC0 reserved DRAM RAS cycles selection DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A18IO A16IO A14IO A12IO - A8IO A6IO A5IO A18EC A16EC A14EC A12EC A10EC A8EC A6EC A5EC Area 18, 17 internal/external access 1 Internal 0 External Area 16, 15 internal/external access access access Area 14, 13 internal/external access Area 12, 11 internal/external access reserved - 0 External Area 8, 7 internal/external access 1 Internal Area 6 internal/external access access access Area 5, 4 internal/external access Area 18, 17 endian control 1 Big endian 0 Little endian Area 16, 15 endian control Area 14, 13 endian control Area 12, 11 endian control Area 10, 9 endian control Area 8, 7 endian control Area 6 endian control Area 5, 4 endian control EPSON Init. R/W 0 0 0 0 0 0 - 1 8-successive 0 4-successive 1 EDO 0 Fast page RCA[1:0] Size 1 1 11 1 0 10 0 1 9 0 0 8 1 Enabled 0 Disabled Refresh enable 1 Self-refresh 0 CBR-refresh Refresh method selection 1 2.0 0 1.0 Refresh RPC delay setup RRA[1:0] Number of cycles Refresh RAS pulse width 1 1 5 selection 1 0 4 0 1 3 0 0 2 - reserved External interface method selection 1 #BSL 0 A0 External bus master setup 1 Existing 0 Nonexistent 1 Enabled 0 Disabled External power-down control 1 Enabled 0 Disabled #WAIT enable DRAM timing 0048130 DF-C - reserved set-up register (HW) DB A3EEN Area 3 emulation DA CEFUNC1 #CE pin function selection D9 CEFUNC0 Access control 0048132 register (HW) Setting 1 Fixed at H S1C33L03 FUNCTION PART VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE A-1 A14SZ: Areas 14-13 device size selection (D6) / Areas 14-13 set-up register (0x48122) A8SZ: Areas 8-7 device size selection (D6) / Areas 8-7 set-up register (0x48128) Select the size of the device connected to each area. Write "1": 8 bits Write "0": 16 bits Read: Valid Set the device size of the area used for an SDRAM in the same manner as that specified for SDRSZ (D6/0x39FFC9). At cold start, these bits are set to "0" (16 bits). At hot start, these bits retain their status before being initialized. A14WT2-A14WT0: Areas 14-13 wait control (D[2:0]) / Areas 14-13 set-up register (0x48122) A8WT2-A8WT0: Areas 8-7 wait control (D[2:0]) / Areas 8-7 set-up register (0x48128) A6WT2-A6WT0: Area 6 wait control (D[A:8]) / Areas 6-4 set-up register (0x4812A) Set the number of wait cycles to be inserted when accessing the internal device. The values 0 through 7 written to the control bits equal the number of wait cycles inserted. Always make sure the number of wait cycles in area 6 (where the SDRAM controller is allocated) is 2 (A6WT = "010"). With any other number of specified wait cycles, data may not be written normally to the SDRAM control registers. The number of wait cycles in areas used for SDRAMs should be set to 0 (A8WT/A14WT = "000"). At cold start, these bits are set to "111" (7 cycles). At hot start, the bits retain their status before being initialized. A14DF1-A14DF0: Areas 14-13 output disable delay time (D[5:4]) / Areas 14-13 set-up register (0x48122) A8DF1-A8DF0: Areas 8-7 output disable delay time (D[5:4]) / Areas 8-7 set-up register (0x48128) Set the output-disable delay time. Table 2.13 Output Disable Delay Time AxxDF1 AxxDF0 Delay time 1 1 0 0 1 0 1 0 3.5 cycles 2.5 cycles 1.5 cycles 0.5 cycles If the system has an external memory device other than the SDRAM connected to it and accesses that memory device and reads the SDRAM in succession, set the output disable delay time for the areas used for the SDRAM to 2.5 cycles (A8DF/A14DF = "10"). Otherwise, set the output disable delay time to 0.5 cycles (A8DF/A14DF = "00") in order to reduce the SDRAM access time. At cold start, these bits are set to "11" (3.5 cycles). At hot start, the bits retain their status before being initialized. SWAITE: #WAIT enable (D0) / Bus control register (0x4812E) Enable or disable wait cycle control. Write "1": Enabled Write "0": Disabled Read: Valid Because the SDRAM controller controls wait cycles internally in the IC, SWAITE must be set to "1". At cold start, SWAITE is set to "0" (disabled). At hot start, SWAITE retains its status before being initialized. B-VI SDRAM S1C33L03 FUNCTION PART EPSON B-VI-2-25 VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE CEFUNC1-CEFUNC0: #CE pin function selection (D[A:9]) / DRAM timing set-up register (0x48130) Select an area for connection with an SDRAM. Table 2.14 #CE Output Assignment Pin #CE7/#SDCE0 #CE8/#SDCE1 CEFUNC = "00" #CE7/#SDCE0 #CE8/#SDCE1 CEFUNC = "01" CEFUNC = "1x" #CE13/#SDCE0 #CE13/#SDCE0 #CE14/#SDCE1 #CE14/#SDCE1 (Default: CEFUNC = "00") Set CEFUNC = "00" to use areas 7/8 for SDRAMs or CEFUNC = "01" to use areas 13/14 for SDRAMs. At cold start, CEFUNC is set to "00". At hot start, CEFUNC retains its status before being initialized. A14IO: Areas 14-13 internal/external access selection (DD) / Access control register (0x48132) A8IO: Areas 8-7 internal/external access selection (DA) / Access control register (0x48132) A6IO: Area 6 internal/external access selection (D9) / Access control register (0x48132) Select either internal access or external access for each area. Write "1": Internal access Write "0": External access Read: Valid Before the SDRAM controller can be used, A6IO must be set to "1" (internal access). Also, set A8IO to "1" to use areas 7/8 for SDRAMs or set A14IO to "1" to use areas 13/14 for SDRAMs. At cold start, these bits are set to "0" (external access). At hot start, these bits retain their status before being initialized. A6EC: Area 6 little/big endian method selection (D1) / Access control register (0x48132) Select either little endian or big endian method for accessing each area. Write "1": Big endian Write "0": Little endian Read: Valid Set this register bit in the same way as set by LCDCEC (D0/0x39FFFD). At cold start, this bit is set to "0" (little endian). At hot start, this bit retains its status before being initialized. SDRAR1: Area 8/14 configuration (D6) / SDRAM area configuration register (0x39FFC0) SDRAR0: Area 7/13 configuration (D7) / SDRAM area configuration register (0x39FFC0) Set the area to be used for an SDRAM. Write "1": For SDRAM Write "0": For other devices Read: Valid SDRAMs can be connected to areas 7/8 or to areas 13/14. Write "1" to SDRAR0 to set area 7 or 13 for SDRAM use. Similarly, write "1" to SDRAR1 to set area 8 or 14 for SDRAM use. Writing a "0" to either bit sets the corresponding area to be used for devices other than an SDRAM. At cold start, these bits are set to "0" (For a device not SDRAM). At hot start, these bits retain their status before being initialized. B-VI-2-26 EPSON S1C33L03 FUNCTION PART VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE A-1 SDRPC1: #CE8/14 pin configuration (D2) / SDRAM area configuration register (0x39FFC0) SDRPC0: #CE7/13 pin configuration (D3) / SDRAM area configuration register (0x39FFC0) Set the chip-enable pin for an SDRAM. Write "1": #SDCEx (for SDRAM) Write "0": #CExx (for other devices) Read: Valid Select the pin to be used as a chip enable for the SDRAM connected to the S1C33. Write "1" to SDRPC0 to set the #CE7/13 pin for SDRAM use (#SDCE0). Similarly, write "1" to SDRPC1 to set the #CE8/14 pin for SDRAM use (#SDCE1). Writing "0" to either bit sets the corresponding pin to be used as chip-enable output for other devices. SDRAMs and the BCU are used differently--with SDRAMS, the areas and the pins used are not associated with each other. Consequently, when using area 7 for an SDRAM, for example, it is possible to use #CE8/14 as the chip-enable pin for the SDRAM. Or while using both areas 7 and 8, it is possible to use only #CE7/13 as the chipenable pin. See Table 2.5 for the combinations of areas and pins used. At cold start, these bits are set to "0" (#CExx). At hot start, these bits retain their status before being initialized. SDRENA: Enable SDRAM signals (D7) / SDRAM control register (0x39FFC1) Enable the pins used for the SDRAM. Write "1": Enabled Write "0": Disabled Read: Valid Writing "1" to SDRENA sets the pins shared with other functions to be used for the SDRAM, with the SDRAM clock output from the BCLK pin. If SDRENA = "0", the shared pins serve other functions. The SDRAM clock output from the BCLK pin is stopped in the HALT2 and the SLEEP modes. At cold start, SDRENA is set to "0" (disabled). At hot start, SDRENA retains its status before being initialized. SDRINI: Initialize SDRAM (D6) / SDRAM control register (0x39FFC1) Initiate the SDRAM initialization sequence. Write "1": Start Write "0": No operation Read: Valid Writing "1" to SDRINI initiates the SDRAM initialization sequence at SDRAM power-up, as specified by SDRIS (D4/0x39FFC1). This operation must be performed after holding the SDRAM in an NOP state for at least 100 s (this varies with each SDRAM) after powering up the SDRAM. At cold or hot start, SDRINI is set to "0". SDRSRF: Enable SDRAM self-refresh (D5) / SDRAM control register (0x39FFC1) Enable the SDRAM's self-refresh control function. Write "1": Enabled Write "0": Disabled Read: Valid Writing "1" to SDRSRF enables the SDRAM controller to start self-refreshing the SDRAM (by setting SDCKE output low). Note that self-refreshing of the SDRAM actually begins a certain time after accessing or autorefreshing the SDRAM. The duration of this elapsed time is defined by the number of clock cycles in SDRSRFC[3:0] (D[3:0]/0x39FFC8). SDRSRF = "0" disables the self-refresh function. At cold start, SDRSRF is set to "0" (disabled). At hot start, SDRSRF retains its status before being initialized. B-VI SDRAM S1C33L03 FUNCTION PART EPSON B-VI-2-27 VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE SDRIS: Initial command sequence (D4) / SDRAM control register (0x39FFC1) Select the SDRAM initialization sequence. Write "1": 1. Precharge 2. Mode Register Set 3. Refresh Write "0": 1. Precharge 2. Refresh 3. Mode Register Set Read: Valid In accordance with the specifications of the SDRAM, select a sequence to determine the order the commands are sent to initialize the SDRAM. Initialization of the SDRAM is initiated by writing "1" to SDRINI (D6/0x39FFC1). At cold start, SDRIS is set to "0" (1. Precharge 2. Refresh 3. Mode Register Set). At hot start, SDRIS retains its status before being initialized. SDRCLK: Keep SDRAM clock during self-refresh (D3) / SDRAM control register (0x39FFC1) Select whether or not to stop the SDRAM clock during self-refresh. Write "1": Kept outputting Write "0": Stopped Read: Valid Writing "0" to SDRCLK causes the SDRAM clock output from the BCLK pin to stop and to remain off while the SDRAM is self-refreshed. This helps to reduce the chip's current consumption. Note that when the bus is released, the BCLK pin goes into a high-impedance state. If SDRCLK = "1", the SDRAM clock is always output from the BCLK pin even while the SDRAM is selfrefreshed or the bus is released. At cold start, SDRCLK is set to "1" (kept outputting). At hot start, SDRCLK retains its status before being initialized. SDRCA1-SDRCA0: SDRAM page size (D[6:5]) / SDRAM address configuration register (0x39FFC2) Set the SDRAM page size (column addressing range). Table 2.15 Setting Column Addressing Range (Page Size) SDRCA1 SDRCA0 Column size Column address (pin) used 0 0 1 1 0 1 0 1 256 512 1,024 - SDA0-SDA7 (default) SDA0-SDA8 SDA0-SDA9 - The contents set here are applied to all of areas 7, 8, 13, and 14 that are set for SDRAM. SDRCA can be read to obtain its set value. At cold start, SDRCA is set to "0" (256). At hot start, SDRCA retain its status before being initialized. SDRRA1-SDRRA0: SDRAM row addressing range (D[3:2]) / SDRAM address configuration register (0x39FFC2) Set the SDRAM row addressing range. Table 2.16 Setting Row Addressing Range SDRRA1 SDRRA0 Row size Row address (pin) used 0 0 1 1 0 1 0 1 2K 4K 8K - SDA0-SDA10 (default) SDA0-SDA11 SDA0-SDA12 - The contents set here are applied to all of areas 7, 8, 13, and 14 that are set for SDRAM. SDRRA can be read to obtain its set value. At cold start, SDRRA is set to "0" (2K). At hot start, SDRRA retain its status before being initialized. B-VI-2-28 EPSON S1C33L03 FUNCTION PART VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE A-1 SDRBA: Number of SDRAM banks (D1) / SDRAM address configuration register (0x39FFC2) Set the number of banks of the SDRAM. Write "1": 4 banks Write "0": 2 banks Read: Valid Set "1" when a SDRAM configured with 4 banks is used or set "0" when a SDRAM configured with 2 banks is used. The contents set here are applied to all of areas 7, 8, 13, and 14 that are set for SDRAM. At cold start, SDRBA is set to "0" (2 banks). At hot start, SDRBA retains its status before being initialized. SDRCL1-SDRCL0: SDRAM CAS latency (D[6:5]) / SDRAM mode set-up register (0x39FFC3) Set the CAS latency of the SDRAM. Table 2.17 Setting CAS Latency SDRCL1 SDRCL0 CAS latency (number of clocks) 1 0 Other settings 2 Not allowed The SDRAM controller does not support CAS latencies other than 2. At cold start, SDRCL is set to "11". Be sure to reset to "10" so that the CAS latency is set to 2. At hot start, SDRCL retain its status before being initialized. SDRBL1-SDRBL0: SDRAM burst length (D[3:2]) / SDRAM mode set-up register (0x39FFC3) Set the burst read length of the SDRAM. Table 2.18 Setting Burst Length SDRBL1 SDRBL0 Burst length (word) 0 0 1 1 0 1 0 1 1 2 4 8 The SDRAM controller does not support burst write, so the set burst length is effective only for read cycles. At cold start, SDRBL is set to "11" (8). At hot start, SDRBL retain its status before being initialized. SDRTRAS2-SDRTRAS0: SDRAM tRAS spec (D[7:5]) / SDRAM timing set-up register 1 (0x39FFC4) Set the tRAS SDRAM parameter (ACTIVE to PRECHARGE command period). In accordance with the specifications of the SDRAM, specify this parameter in terms of the number of SDRAM clock cycles. Specifying 1-7 sets the period to 1-7 clock cycles. Specifying 0 sets the period to 8 clock cycles. At cold start, SDRTRAS is set to "000" (8). At hot start, SDRTRAS retain its status before being initialized. SDRTRP1-SDRTRP0: SDRAM tRP spec (D[4:3]) / SDRAM timing set-up register 1 (0x39FFC4) Set the tRP SDRAM parameter (PRECHARGE command period). In accordance with the specifications of the SDRAM, specify this parameter in terms of the number of SDRAM clock cycles. Specifying 1-3 sets the period to 1-3 clock cycles. Specifying 0 sets the period to 4 clock cycles. At cold start, SDRTRP is set to "00" (4). At hot start, SDRTRP retain its status before being initialized. SDRTRC2-SDRTRC0: SDRAM tRC spec (D[2:0]) / SDRAM timing set-up register 1 (0x39FFC4) Set the tRC SDRAM parameter (ACTIVE to ACTIVE command period). In accordance with the specifications of the SDRAM, specify this parameter in terms of the number of SDRAM clock cycles. Specifying 1-7 sets the period to 1-7 clock cycles. Specifying 0 sets the period to 8 clock cycles. At cold start, SDRTRC is set to "000" (8). At hot start, SDRTRC retain its status before being initialized. SDRAM Note: When the auto-refresh command is executed, the following command may be issued 3 or 4 CPU_CLK cycles from that point regardless of the tRC value set in the SDRTRC register. Therefore, use SDRAMs with 75 ns or less of tRC. S1C33L03 FUNCTION PART EPSON B-VI B-VI-2-29 VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE SDRTRCD1-SDRTRCD0: SDRAM tRCD spec (D[7:6]) / SDRAM timing set-up register 2 (0x39FFC5) Set the tRCD SDRAM parameter (ACTIVE to READ or WRITE delay time). In accordance with the specifications of the SDRAM, specify this parameter in terms of the number of SDRAM clock cycles. Specifying 1-3 sets the period to 1-3 clock cycles. Specifying 0 sets the period to 4 clock cycles. At cold start, SDRTRCD is set to "00" (4). At hot start, SDRTRCD retain its status before being initialized. SDRTRSC: SDRAM tRSC spec (D5) / SDRAM timing set-up register 2 (0x39FFC5) Set the tRSC SDRAM parameter (Mode Register Set cycle time). Write "1": 1 clock Write "0": 2 clocks Read: Valid In accordance with the specifications of the SDRAM, specify this parameter in terms of the number of SDRAM clock cycles. At cold start, SDRTRSC is set to "0" (2). At hot start, SDRTRSC retain its status before being initialized. SDRTRRD1-SDRTRRD0: SDRAM tRRD spec (D[4:3]) / SDRAM timing set-up register 2 (0x39FFC5) Set the tRRD SDRAM parameter (ACTIVE bank (a) to ACTIVE bank (b) period). In accordance with the specifications of the SDRAM, specify this parameter in terms of the number of SDRAM clock cycles. Specifying 1-3 sets the period to 1-3 clock cycles. Specifying 0 sets the period to 4 clock cycles. At cold start, SDRTRRD is set to "00" (4). At hot start, SDRTRRD retain its status before being initialized. SDRARFC11-SDRARFC0: SDRAM auto refresh count (D[B:0]) / SDRAM auto refresh count register (0x39FFC6) Set the auto refresh counter value. The auto-refresh counter counts up on the OSC3 clock edges beginning with 0, and when the count specified here is reached, the SDRAM controller sends an auto-refresh command. The counter is reset at that point, and starts counting the next refresh period. The counter is also reset by self-refresh. The value calculated from the equation below is the maximum count that can be set. RFP SDRARFC -------- x fOSC3 - BL - CL - 2 x tRP - tRCD - 3 ROWS RFP: Maximum refresh period [s] ROWS: Row address size fOSC3: OSC3 clock frequency [Hz] BL: Burst length [word] CL: CAS latency [Number of SD_CLK clocks] PRECHARGE command period [Number of SD_CLK clocks] tRP: tRCD: ACTIVE to READ or WRITE delay time [Number of SD_CLK clocks] At cold start, SDRARFC is set to "0xFFF" (4095). At hot start, SDRARFC retain its status before being initialized. SDRSRFC3-SDRSRFC0: SDRAM self refresh count (D[3:0]) / SDRAM self refresh count register (0x39FFC8) Set the self refresh counter value. If SDRSRF (D5/0x39FFC1) is set to "1" (self-refresh-enabled), the self-refresh counter starts counting up on the SDRAM clock edges beginning with 0 after accessing or auto-refreshing the SDRAM. When the count specified here is reached, the SDCKE output is pulled low, causing the SDRAM to start self-refreshing. If an access to the SDRAM occurs during self-refresh mode, SDCKE is returned high, thereby taking the SDRAM out of self-refresh mode. At cold start, SDRSRFC is set to "0xF" (15). At hot start, SDRSRFC retain its status before being initialized. Note: Always set this register to 2 or more. If it is set to less than 2, the SDRAM cannot exit self-refresh mode. B-VI-2-30 EPSON S1C33L03 FUNCTION PART VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE A-1 SDRSZ: SDRAM data path bit width (D6) / SDRAM advanced control register (0x39FFC9) Select the SDRAM data-path bit width. Write "1": 8 bits Write "0": 16 bits Read: Valid Set SDRSZ to "1" to use an 8-bit SDRAM or to "0" to use a 16-bit SDRAM. At cold start, SDRSZ is set to "0" (16 bits). At hot start, SDRSZ retains its status before being initialized. SDRBI: SDRAM bank interleaved access (D5) / SDRAM advanced control register (0x39FFC9) Enable the SDRAM's bank-interleaved access function. Write "1": Interleaved Write "0": One bank only Read: Valid Writing "1" to SDRBI activates multiple SDRAM banks at the same time, allowing for successive accesses of one bank after another. If SDRBI = "0", multiple banks cannot be activated at the same time. At cold start, SDRBI is set to "0" (one bank only). At hot start, SDRBI retains its status before being initialized. SDRMRS: SDRAM mode register set flag (D7) / SDRAM status register (0x39FFCA) Indicates the execution status of the MRS (Mode Register Set) command. Read "1": Not finished Read "0": Finished Write: Invalid SDRMRS is automatically set to "1" at power-on, and is reset to "0" by executing the MRS command in the SDRAM initialization sequence. As the MRS command uses an external address bus, no other external devices can be accessed until the command execution is finished. To access any external device other than the SDRAM immediately after executing the SDRAM initialization sequence, read SDRMRS to confirm that the MRS command execution is finished before attempting the intended access. At cold start, SDRMRS is set to "1" (Not finished). At hot start, SDRMRS retains its status before being initialized. SDRSRM: SDRAM current refresh mode (D6) / SDRAM status register (0x39FFCA) Indicates the SDRAM refresh mode. Read "1": Auto refresh mode Read "0": Self refresh mode Write: Invalid SDRSRM is "0" while the SDRAM controller holds the SDCKE pin low (i.e., the SDRAM is in self-refresh mode). Otherwise, SDRSRM = "1". Before entering HALT2 or SLEEP mode or releasing the bus, always be sure to read this bit using a program stored elsewhere (i.e., not in the SDRAM) to confirm that the SDRAM is in self-refresh mode. At cold start, SDRSRM is set to "1" (auto refresh mode). At hot start, SDRSRM retains its status before being initialized. B-VI SDRAM S1C33L03 FUNCTION PART EPSON B-VI-2-31 VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE Programming Notes (1) Make sure that two wait cycles are inserted when accessing area 6, where the SDRAM controller is allocated. With any other number of specified wait cycles, data may not be written normally to the SDRAM control registers. (2) Set the area used for an SDRAM for internal access (A8IO (DA/0x48132) = "1" or A14IO (DD/0x48132) = "1"). (3) Before entering HALT2 or SLEEP mode, be sure to place the SDRAM in self-refresh mode, because the SDRAM cannot be auto-refreshed while in those modes. In that case, confirm that SDRSRM (D6/0x39FFCA) = "0" (i.e., that the SDRAM is in self-refresh mode) before executing the HALT or SLP instruction. If an access to the SDRAM occurs while being self-refreshed, the SDRAM is taken out of self-refresh mode; thus always make sure the SDRAM check and the HALT/SLP instruction execution are performed from devices other than the SDRAM. (4) Do not access addresses 0x039FFCB to 0x039FFCD, as the user program will not be able to control the CPU. (5) If the program accesses an area out of the address range set using the address setting register (0x39FFC2), an unintended area is accessed and the stored data may be overwritten. Therefore, do not access an area out of the set range. B-VI-2-32 EPSON S1C33L03 FUNCTION PART VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE A-1 Examples of SDRAM Controller Initialization Program The following shows examples of the initialization program for using SDRAM. Example of initialization routine for 2M words x 16 bits x 4 banks (16MB) of SDRAM INIT_SDRAM_16MB: ;;;----------------------- SDRAM access configuration ----------------------------------;;;***************************************************************** ;;;***************** C33 macro setting part ************************ ;;;***************************************************************** ;;; set CEFUNC to use #CE13/14 (upper area) xld.w %r0,0x48131 bset [%r0],0x1 ... 1 (See "SDRAM Controller Configuration".) ;;; set area 6,13,14 to internal access xld.w %r0,0x48132 xld.w %r1,0x2200 ld.h [%r0], %r1 ... 2, 5, B-1 ;;; area 6 -> output disable 0.5, wait 2 xld.w %r0,0x4812A xld.w %r1,0x0237 ld.h [%r0],%r1 ... 3 ;;; available #WAIT xld.w %r0,0x04812E bset [%r0],0x0 ... 4 ;;; area 13,14 -> 16bit device, output disable 2.5, wait 0 xld.w %r0,0x048122 xld.w %r1,0x30 ld.h [%r0],%r1 ... B-2, B-3, B-4 ;;;***************************************************************** ;;;************** SDRAM Controller REG setting part **************** ;;;***************************************************************** ;;;------------------------------------------------;;;area13 0x2000000 - 0x2FFFFFF(16MB) ;;;area14 0x3000000 - 0x3FFFFFF(16MB) ;;;------------------------------------------------;/////////////////////////////////////////// ;;; SDRAM area configuration register ... (note 1) xld.w %r0,0x39FFC0 ; xld.w %r1,0x88 ; set area13 to SDRAM area, #SDCE0(#CE13) available ld.b [%r0],%r1 ; (16MB area available) ;/////////////////////////////////////////// ;;; SDRAM control register ;;; xld.w %r0,0x39FFC1 ; ;;; xld.w %r1,0xff ; SDRAM self-refresh -> disable, initial sequence ->PRE REF MRS ;;; ld.b %r0],%r1 ; Little endian ;/////////////////////////////////////////// ;;; SDRAM address configuration register ... (note 2) xld.w %r0,0x39FFC2 ; xld.w %r1,0x26 ; col 512 / row 4K / bank 4 -> 128Mb[16MB] available ld.b [%r0],%r1 ; ;/////////////////////////////////////////// ;;; SDRAM mode set-up register xld.w %r0,0x39FFC3 ; xld.w %r1,0x40 ; 2 CAS Latency ,burst length = 1 ld.b [%r0],%r1 ; ;/////////////////////////////////////////// ;;; SDRAM timing set-up register 1 xld.w %r0,0x39FFC4 ; xld.w %r1,0x4A ; Tras=2,Trp=1,Trc=2 ... Recommended setting to operate with ld.b [%r0],%r1 ; 25 MHz clock in x1 speed mode ;/////////////////////////////////////////// ;;; SDRAM timing set-up register 2 xld.w %r0,0x39FFC5 ; xld.w %r1,0x48 ; Trcd=1,Trsc=2,Trrd=1 ld.b [%r0],%r1 ; ;/////////////////////////////////////////// ;;; SDRAM auto refresh count low-order register ;;; xld.w %r0,0x39FFC6 ; ;;; xld.w %r1,0xff ; ;;; ld.b [%r0],%r1 ; ;/////////////////////////////////////////// S1C33L03 FUNCTION PART EPSON B-VI-2-33 B-VI SDRAM VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE ;;; SDRAM auto refresh count high-order register xld.w %r0,0x39FFC7 ; xld.w %r1,0x00 ; ld.b [%r0],%r1 ; ;/////////////////////////////////////////// ;;; SDRAM self refresh count register ;;; xld.w %r0,0x39FFC8 ; ;;; xld.w %r1,0x0f ; ;;; ld.b [%r0],%r1 ; ;/////////////////////////////////////////// ;;; SDRAM advanced control register xld.w %r0,0x39FFC9 ; xld.w %r1,0x20 ; data width -> 16bit, bank interleave -> on ld.b [%r0],%r1 ; ;;;***************************************************************** ;;;***************** SDRAM controller power up ********************* ;;;***************************************************************** xld.w %r0,0x39FFC1 ; SDRAM control register xld.w %r1,0x39FFCA ; SDRAM status register xld.w %r2,0x0 xld.w %r3,0x10 ;;; enable SDRAM signal bset [%r0],0x7 ; set SDRENA[D7/0x39FFC1] SDRAM_SIGNAL_EN: add %r2,0x1 ; SDRAM signal enable waiting loop cmp %r2,%r3 jrne SDRAM_SIGNAL_EN ;;; SDRAM power bset POWER_UP: btst jrne up [%r0],0x6 [%r1],0x7 POWER_UP ; set SDRINI[D6/0x39FFC1] ; SDRAM power-up waiting loop ;;;------------------------ end of SDRAM access configuration --------------------------ret The SDRAM can be accessed after executing the above program. Example of initialization routine for 4M words x 16 bits x 4 banks (32MB) of SDRAM When using a 32MB SDRAM, modify two parts of the above program example indicated with (note 1) and (note 2) as follows: (note 1) ;/////////////////////////////////////////// ;;; SDRAM area configuration register xld.w %r0,0x39FFC0 ; xld.w %r1,0xc8 ; set area13&14 to SDRAM area, #SDCE0(#CE13) available ld.b [%r0],%r1 ; (32MB area available) ;/////////////////////////////////////////// (note 2) ;/////////////////////////////////////////// ;;; SDRAM address configuration register xld.w %r0,0x39FFC2 ; xld.w %r1,0x2a ; col 512 / row 8K / bank 4 -> 256Mb[32MB] available ld.b [%r0],%r1 ; ;/////////////////////////////////////////// B-VI-2-34 EPSON S1C33L03 FUNCTION PART S1C33L03 FUNCTION PART VII LCD CONTROLLER BLOCK VII LCD CONTROLLER BLOCK: INTRODUCTION A-1 VII-1 INTRODUCTION The LCD Controller Block provides LCD control signals for a 4- or 8-bit color/monochrome LCD panel. C33 SDRAM Controller Block C33 LCD Controller Block C33_DMA C33_SDRAMC C33_LCDC (IDMA, HSDMA) (SDRAM interface) (LCD panel interface) C33 DMA Block Pads Internal RAM (Area 0) CORE_PAD C33 Internal Memory Block C33_CORE (CPU, BCU, ITC, CLG, DBG) Internal ROM (Area 10) Pads C33_SBUS C33_ADC C33_PERI (A/D converter) (Prescaler, 8-bit timer, 16-bit timer, Clock timer, Serial interface, Ports) C33 Analog Block PERI_PAD C33 Core Block Pads C33 Peripheral Block Figure 1.1 LCD Controller Block Note: Internal ROM is not provided in the S1C33L03. B-VII Intro S1C33L03 FUNCTION PART EPSON B-VII-1-1 VII LCD CONTROLLER BLOCK: INTRODUCTION THIS PAGE IS BLANK. B-VII-1-2 EPSON S1C33L03 FUNCTION PART VII LCD CONTROLLER BLOCK: LCD CONTROLLER A-1 VII-2 LCD CONTROLLER This section describes the functions and control procedures of the LCD controller. For details on setting the external display memory bus conditions and parameters, refer to Section II-4, "BCU (Bus Control Unit)", and Section VI-2, "SDRAM Interface". Overview Features The features of the LCD controller (LCDC) are described below. S1C33 core CPU interface * The control registers are mapped into the area-6 addresses 0x39FFE0 to 0x39FFFF (an internal #WAIT signal is used). * A dedicated DMA controller is built-in for the transferal of display data. Compatible display types * * * * 4- or 8-bit monochrome LCD panel 4- or 8-bit color LCD panel Single-drive passive display, single panel Typical resolutions 640 x 480 (1-bpp mode) * bpp = bits per pixel 640 x 240 (2-bpp mode) 320 x 240 (4-bpp mode) 240 x 160 (8-bpp mode) Display modes * Portrait display (display screen rotated 90 degrees) is supported in the hardware. * Due to frame rate modulation, grayscale display is possible in up to 16 shades of gray when a monochrome passive LCD panel is used. 1-bpp mode: Two-shade display using a 2 x 4-bit look-up table 2-bpp mode: Four-shade display using a 4 x 4-bit look-up table 4-bpp mode: 16-shade display using a 16 x 4-bit look-up table * Of 4,096 colors, a maximum of 256 colors can be simultaneously displayed on a color passive LCD panel. 1-bpp mode: Two-color display using three 2 x 4-bit look-up tables 2-bpp mode: Four-color display using three 4 x 4-bit look-up tables 4-bpp mode: 16-color display using three 16 x 4-bit look-up tables 8-bpp mode: 256-color display using a 20 x 4-bit look-up table * Two images can be simultaneously displayed on split screens of the LCD panel (landscape display mode). * Virtual display (Images larger than the actual panel size can be displayed by panning or scrolling the screen.) Display frame buffer * A maximum of 256K bytes in memory connected to areas 7/8 or areas 13/14 can be used as a display frame buffer. * SDRAM is also supported by the 16 x 16-bit FIFO. Clock * The PCLK (pixel clock) and MCLK (memory clock) for the LCD controller can be selected from among four clock frequencies derived from the BCU clock by dividing the BCU clock by 1, 2, 3, or 4. * PCLK and MCLK frequencies: Maximum of 25 MHz B-VII LCDC S1C33L03 FUNCTION PART EPSON B-VII-2-1 VII LCD CONTROLLER BLOCK: LCD CONTROLLER Power save * DOZE mode suitable for Epson's self-refresh-type LCD panels * The status of the LCD controller can be checked using the power-save status bit. Other * * * * Inverse display under software control Software power-save mode LCD-panel power-down sequence supported LCD power-supply control B-VII-2-2 EPSON S1C33L03 FUNCTION PART VII LCD CONTROLLER BLOCK: LCD CONTROLLER A-1 Block Diagram User logic signals Bus interface Address[23:0] Data[15:0] #CE6 #BUSREQ #BUSACK #BUSGET #CE7/13(8/14) FIFO Display pipeline Look-up table DMA interface Sequence controller Frame rate modulation LCD interface FPDAT[7:0] FPFRAME FPLINE FPSHIFT DRDY LCDPWR Control registers To SDRAM Controller Figure 2.1 Block Diagram of the LCD Controller Bus interface The LCD controller is mapped into area 6, along with the SDRAM controller. Area 6 is internally accessed for read/write to the control registers. DMA interface The display data is taken in from the display frame buffer by means of a DMA transfer. Address generator This generates the memory addresses for the display data to be taken in by means of a DMA transfer. FIFO This is a 16 x 16-bit FIFO used to write data into the display frame buffer and look-up table. Look-up table This consists of three 16 x 4-bit palettes (red, green, and blue). During grayscale display mode, the grayscale data to be used is set in the green palette with 16 gray levels. During color display mode, the red, green, and blue palettes are used, and the color data to be used is set from among 4,096 colors. Sequence controller The horizontal and vertical display timing is controlled in accordance with the register settings. LCD-panel interface Display on the LCD panel is controlled through frame rate modulation, output-data pattern generation, and the like. B-VII LCDC S1C33L03 FUNCTION PART EPSON B-VII-2-3 VII LCD CONTROLLER BLOCK: LCD CONTROLLER I/O Pins of the LCD Controller Table 2.1 lists the input/output pins of the LCD controller. Table 2.2 shows the pin configurations classified by type of LCD panel. Table 2.1 I/O Pins of the LCD Controller Pin name I/O FPDAT[7:4] Description O 4-bit LCD-panel data bus 8-bit LCD-panel data bus, four high-order bits O 8-bit LCD-panel data bus, four low-order bits General-purpose output when a 4-bit LCD panel is used O Frame-pulse output O Line-pulse output O Shift-clock output O LCD backplane bias (MOD) Shift clock 2 (FPSHIFT2) See Table 2.2. O LCD power-supply control output (active high) I/O GPIO0 See "Control of GPIO pins". I/O port Bus-release-request input Area-6 chip enable I/O GPIO1 See "Control of GPIO pins". I/O port Acknowledge output for bus release request I/O GPIO2 See "Control of GPIO pins". I/O port Bus-status-monitor signal output for bus release request GA-area read signal output FPDAT[3:0] GPO[6:3] FPFRAME FPLINE FPSHIFT DRDY LCDPWR GPIO0 P34 #BUSREQ #CE6 GPIO1 P35 #BUSACK GPIO2 P31 #BUSGET #GARD Table 2.2 Pin Configurations by Type of LCD Panel Monochrome passive panel 4 bits 8 bits Pin name FPFRAME FPLINE DRDY FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT3 FPDAT2 FPDAT1 FPDAT0 MOD D3 D2 D1 D0 GPO6 GPO5 GPO4 GPO3 S1C33 FPDAT[7:0] FPSHIFT FPFRAME FPLINE DRDY MOD D7 D6 D5 D4 D3 D2 D1 D0 LCD panel 4 bits Color passive panel 8-bit format 1 8-bit format 2 FPFRAME FPLINE MOD D3 D2 D1 D0 GPO6 GPO5 GPO4 GPO3 FPSHIFT2 D7 D6 D5 D4 D3 D2 D1 D0 MOD D7 D6 D5 D4 D3 D2 D1 D0 S1C33 D[7:0] FPSHIFT FPDAT[3:0] FPSHIFT FPFRAME FPLINE MOD FPFRAME FPLINE DRDY LCDPWR LCD panel D[3:0] FPSHIFT FPFRAME FPLINE MOD LCDPWR 8-bit passive LCD panel 4-bit passive LCD panel Figure 2.2 Typical LCD-Panel Connections B-VII-2-4 EPSON S1C33L03 FUNCTION PART VII LCD CONTROLLER BLOCK: LCD CONTROLLER A-1 System Settings Setting the BCU The control registers of the LCD controller are mapped into area-6 addresses 0x39FFE0 to 0x39FFFF. Therefore, in order for the control registers to be accessed, the BCU must be set up in accordance with the procedure described below. 1. A6IO (D9)/access control register (0x48132) = "1" This sets area 6 so that the internal device will be accessed. 2. A6WT[2:0] (D[A:8])/areas 6-4 setup register (0x4812A) = "000" This sets area 6 so that it can be accessed with no wait states. 3. SWAITE (D0)/bus control register (0x4812E) = "1" This enables the #WAIT signal. This setting is necessary when SDRAM is used. 4. A6EC (D1)/access control register (0x48132) = LCDCEC (D0)/LCDC system control register (0x39FFFD) Make sure the endian formats on the area 6 and LCDC (and SDRAMC) sides match when data is read. In either register, setting the bit to "0" selects little endian (default), and setting the bit to "1" selects big endian. Display Memory The LCD controller uses as display memory a necessary amount of memory (maximum of 256K bytes), beginning with the start address of area 7 or 8 (or area 13 or 14 if CEFUNC[1:0] (D[A:9]/0x48130) = "01"). Therefore, SDRAM or SRAM must be included for use as the display memory. The memory configurations and bus settings made using the control registers of the LCD controller are described below. Selecting the area Use the VRAMAR (D7)/LCDC system control register (0x39FFFD) to select the area to be used as the display memory. VRAMAR = "1": Area 8 (CEFUNC = "00") or area 14 (CEFUNC = "01") VRAMAR = "0": Area 7 (CEFUNC = "00") or area 13 (CEFUNC = "01") (default) SRAM settings When using SRAM as the display memory, set the interface method for access from the LCD controller (A0/BSL) and the number of wait cycles to be inserted (0-7). Use the LCDCST (D1)/LCDC system control register (0x39FFFD) to select the interface method. LCDCST = "1": BSL method LCDCST = "0": A0 method (default) This bit must be set to the same value as in the SBUSST (D3)/bus control register (0x4812E) for the BCU. Use the VRAMWT[2:0] (D[6:4])/LCDC system control register (0x39FFFD) to select the number of wait cycles. The value set in these three bits (0-7) is the number of wait cycles inserted. When the same SRAM is accessed from the CPU, the wait cycles set on the BCU side become effective and the VRAMWT value is ignored. The LCD controller checks the BCU- and SDRAM-controller settings to determine whether SRAM is used. When the SDRAM controller is set to become effective, the above two register settings are ignored. Settings for prioritized use of the bus The LCD controller reads display data from the display memory via the system bus. Therefore, if the bus is occupied by an external device, the LCD controller cannot update the display. To prevent this problem, the LCD controller can disable DMA requests (#DMAREQx) or bus release requests (#BUSREQ) from outside the chip while it remains enabled (LCDCEN (D5)/LCDC mode register 2 = "1"). B-VII LCDC S1C33L03 FUNCTION PART EPSON B-VII-2-5 VII LCD CONTROLLER BLOCK: LCD CONTROLLER Use the EDMAEN (D3)/LCDC system control register (0x39FFFD) to mask the #DMAREQx signals. EDMAEN = "1": External DMA requests enabled EDMAEN = "0": External DMA requests disabled (default) Use the BREQEN (D2)/LCDC system control register (0x39FFFD) to mask the #BUSREQ signals. BREQEN = "1": External bus release requests enabled BREQEN = "0": External bus release requests disabled (default) Other settings, such as memory specification-related settings, are made using the registers of the BCU and SDRAM controllers. For details, refer to the description of the respective controllers. LCD Controller Setting Procedure Procedure to access the LCDC registers (when using #WAIT signal) 1. A6IO (D9)/access control register (0x48132) = "1" This sets area 6 so that the internal device will be accessed. 2. A6WT[2:0] (D[A:8])/areas 6-4 setup register (0x4812A) = "000" This sets area 6 so that it can be accessed with no wait states. 3. SWAITE (D0)/bus control register (0x4812E) = "1" This enables the #WAIT signal. 4. The LCDC registers can be accessed. Procedure to enable the LCD panel 1. SEMAS (D2)/bus control register (0x4812E) = "1" This enables an external bus master. 2. LCDEN (D5)/LCDC mode register 2 (0x39FFE3) = "1" This enables the LCD controller. 3. CFP3[5:4] (D[5:4])/P3 function select register (0x402DC) = "11" This sets the P35 pin as the #BUSACK output and the P34 pin as the #BUSREQ input. 4. Initializing the LCDC registers Setup the LCDC register as necessary except for the look-up table registers (0x39FFF5, 0x39FFF7) as necessary. 5. LPSAVE[1:0] (D[1:0])/LCDC mode register 2 (0x39FFE3) = "11" This sets the LCD controller in power save mode to normal operation mode. Wait until the LCD controller completes the power-up sequence. 6. Setting the look-up table Setup the look-up table by writing data to the look-up table address register (0x39FFF5) and look-up table data register (0x39FFF7). Setting the number of wait states for accessing the LCDC registers (area 6) when #WAIT signal is disabled * The LCDC registers except for the look-up table data register (0x39FFF7) should be accessed with 4 wait states inserted. * When writing data to the look-up table data register (0x39FFF7), red and green data should be written with 4 wait states inserted (1st and 2nd writes in a sequence), and blue data should be written with 7 wait states inserted (last write in a sequence). Use A6WT[2:0] (D[A:8])/areas 6-4 setup register (0x4812A) to set the number of wait states to be inserted when area 6 is accessed. B-VII-2-6 EPSON S1C33L03 FUNCTION PART VII LCD CONTROLLER BLOCK: LCD CONTROLLER A-1 Clock The LCD controller uses the BCU clock as the source clock for its pixel clock PCLK and display memory clock MCLK. The maximum clock frequency that can be supplied to the LCD controller is 25 MHz. The BCU clock divide ratios can be set using the LCLKSEL[2:0] (D[2:0])/FIFO control register (0x39FFF4), as shown in Table 2.3 below. To CPU Bus clock #X2SPD pin LCLKSEL[2:0] CLG BCU 1/1 or 1/2 CPU_CLK 1/1 1/2 1/3 1/4 BCU_CLK LCDC clock (PCLK, MCLK) Figure 2.3 LCDC Clocks Table 2.3 Selection of LCDC Clocks LCLKSEL2 LCLKSEL1 LCLKSEL0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 LCDC clock Turned off Turned off Turned off Reserved (not allowed) BCU_CLK BCU_CLK/2 BCU_CLK/3 BCU_CLK/4 B-VII LCDC S1C33L03 FUNCTION PART EPSON B-VII-2-7 VII LCD CONTROLLER BLOCK: LCD CONTROLLER Setting the LCD Panel Types of Panels The LCD controller supports the following types of single-LCD panels. * 4- or 8-bit monochrome passive LCD panel * 4- or 8-bit color passive LCD panel Dual panels are not supported. The type of LCD panel used must be set in the LCD controller in advance, using the control bits described below. Selecting between color and monochrome Use LDCOLOR (D5)/LCDC mode register 0 (0x39FFE1) to select the type of LCD panel, either color or monochrome. LDCOLOR = "1": Color panel selected LDCOLOR = "0": Monochrome panel selected (default) Selecting the data width Use LDDW[1:0] (D[1:0])/LCDC mode register 0 (0x39FFE1) to select the data width and format. Table 2.4 Selection of the LCD Panel LDCOLOR LDDW1 LDDW0 LCD panel 0 0 0 1 0 1 0 1 0 1 Mono Single 4-bit passive LCD Mono Single 8-bit passive LCD Reserved Reserved Color Single 4-bit passive LCD Color Single 8-bit passive LCD format 1 Reserved Color Single 8-bit passive LCD format 2 1 1 0 1 Resolution Set the resolution of the LCD panel in accordance with the procedure specified below. Horizontal resolution Set the value shown below in the LDHSIZE[5:0] (D[5:0])/horizontal panel size register (0x39FFE4). Horizontal resolution (number of pixels) LDHSIZE[5:0] = ------------------------------------ - 1 16 For example, if the LCD panel has a horizontal resolution of 320 dots, set 19 (= 0x13) in LDHSIZE. Note: Do not set a value less than 1 in LDHSIZE. Vertical resolution Set the value shown below in LDVSIZE[9:0] (D[9:0])/vertical panel size register (0x39FFE6, 0x39FFE5). LDVSIZE[9:0] = Vertical resolution (number of lines) - 1 For example, if the LCD panel has a vertical resolution of 240 lines, set 239 (= 0xEF) in LDVSIZE. B-VII-2-8 EPSON S1C33L03 FUNCTION PART VII LCD CONTROLLER BLOCK: LCD CONTROLLER A-1 Display Modes The number of gray levels in grayscale display and the number of colors in color display are determined by the number of bits representing each pixel (bpp = bits per pixel). Write this bpp value to BPP[1:0] (D[7:6])/LCDC mode register 1 (0x39FFE2) in order to set the display mode (number of gray levels/colors displayed). Table 2.5 Specification of Display Modes LDCOLOR BPP1 BPP0 Display mode 0 0 0 1 0 1 0 1 0 1 2 gray levels 1 bit-per-pixel 4 gray levels 2 bit-per-pixel 16 gray levels 4 bit-per-pixel Reserved 2 colors 1 bit-per-pixel 4 colors 2 bit-per-pixel 16 colors 4 bit-per-pixel 256 colors 8 bit-per-pixel 1 1 0 1 (1) 1-bpp (2-gray-level/2-color) mode One pixel is represented by 1 bit, displayed in two gray levels or two colors. For monochrome LCD panels, 2-gray-level display can be obtained by assigning two gray levels from among the 16 gray levels available, including black and white, to two entries in the green look-up table (described later) (one each for bits = "0" and "1"). For color LCD panels, two colors from among the 4,096 colors available can be set in advance using two entries for pixel data "0" and "1" in each of the red, green, and blue look-up tables. Data for eight consecutive pixels is stored as one byte in the display memory. (bit 7) Display memory LCD panel (bit 0) P0 P1 P2 P3 P4 P5 P6 P7 P8 Byte 1 A8 A9 A10 A11 A12 A13 A14 A15 Byte 0 A0 A1 A2 A3 A4 A5 A6 A7 Pn = (An) Figure 2.4 Data Format in 1-bpp Mode (2) 2-bpp (4-gray-level/4-color) mode One pixel is represented by 2 bits, displayed in four gray levels or four colors. For monochrome LCD panels, 4-gray-level display can be obtained by assigning four gray levels from among the 16 gray levels available, including black and white, to four entries in the green look-up table (one each for bits = "00" to "11"). For color LCD panels, four colors from among the 4,096 colors available can be set in advance using four entries for pixel data "00" to "11" in each of the red, green, and blue look-up tables. Data for four consecutive pixels is stored as one byte in the display memory. (bit 7) Display memory LCD panel (bit 0) P0 P1 P2 P3 P4 P5 P6 P7 Byte 1 A4 B4 A5 B5 A6 B6 A7 B7 Byte 0 A0 B0 A1 B1 A2 B2 A3 B3 Pn = (An, Bn) Figure 2.5 Data Format in 2-bpp Mode B-VII LCDC S1C33L03 FUNCTION PART EPSON B-VII-2-9 VII LCD CONTROLLER BLOCK: LCD CONTROLLER (3) 4-bpp (16-gray-level/16-color) mode One pixel is represented by 4 bits, displayed in 16 gray levels or 16 colors. For monochrome LCD panels, 16-gray-level display can be obtained by assigning 16 gray levels, including black and white, to 16 entries in the green look-up table (one each for bits = "0000" to "1111"). For color LCD panels, 16 colors from among the 4,096 colors available can be set in advance using 16 entries for pixel data "0000" to "1111" in each of the red, green, and blue look-up tables. Data for two consecutive pixels is stored as one byte in the display memory. (bit 7) Display memory LCD panel (bit 0) P0 P1 P2 P3 P4 P5 P6 P7 Byte 2 A4 B4 C4 D4 A5 B5 C5 D5 Byte 1 A2 B2 C2 D2 A3 B3 C3 D3 Byte 0 A0 B0 C0 D0 A1 B1 C1 D1 Pn = (An, Bn, Cn, Dn) Figure 2.6 Data Format in 4-bpp Mode (4) 8-bpp (256-color) mode One pixel is represented by 8 bits, displayed in 256 colors. This mode is not available for grayscale display. In this mode, 256 discrete combinations are configured using eight entries in each of the red and green lookup tables, and four entries in the blue look-up table. Data for one pixel is stored as one byte in the display memory. (bit 7) Display memory LCD panel (bit 0) P0 P1 P2 P3 P4 P5 P6 P7 Byte 2 R22 R2 R2 G22 G21 G20 B21 B20 Byte 1 R12 R11 R10 G12 G11 G10 B11 B10 Byte 0 R02 R01 R00 G02 G01 G00 B01 B00 Pn = (Rn2, Rn1, Rn0, Gn2, Gn1, Gn0, Bn1, Bn0) Figure 2.7 Data Format in 8-bpp Mode B-VII-2-10 EPSON S1C33L03 FUNCTION PART VII LCD CONTROLLER BLOCK: LCD CONTROLLER A-1 Look-up Tables The LCD controller contains a look-up table consisting of 16 4-bit entries, one for each of the RGB color elements (red, green, and blue). Red look-up table Pixel data The pixel data selects an LUT entry. 0 1 2 3 : : 14 15 4-bit luminance data 4-bit display data (R) Green look-up table Pixel data 0 1 2 3 : : 14 15 Pixel data 0 1 2 3 : : 14 15 4-bit luminance data 4-bit display data (G or Gray) Blue look-up table 4-bit luminance data 4-bit display data (B) Figure 2.8 Configuration of the Look-up Tables The pixel data in the display memory is used as an index to the look-up tables, so that luminance data is generated based on the values in the entries indicated by the pixel data, before being output to the LCD panel. The LCD controller can control reversal of the display. This control is exercised on the output of the look-up tables. B-VII LCDC S1C33L03 FUNCTION PART EPSON B-VII-2-11 VII LCD CONTROLLER BLOCK: LCD CONTROLLER Grayscale-mode look-up tables In grayscale mode, the LCD controller uses only the green look-up table. For display in grayscale mode, select the data to be written to the look-up table from the 16 gray levels represented by 4 bits. The data 0x0, 0x1, 0x8, and 0xF represent black, 93.75% gray, 50% gray, and white, respectively. The differences in configuration between display modes are shown below. (1) 1-bpp (2-gray-level) mode Use the first two entries of the green look-up table. Select two pieces of data from the 16 gray levels, and write them to the respective entries. The data in entry 0 is output for pixel data "0", and the data in entry 1 is output for pixel data "1". For monochrome display, write 0x0 to entry 0 and 0xF to entry 1 before using the LCD panel. 1-bit pixel data "0" "1" Index Green look-up table 0 1 2 : 15 4-bit grayscale data for pixel data "0" 4-bit grayscale data for pixel data "1" 4-bit display data Unused Figure 2.9 Look-up Table in 1-bpp (2-Gray-Level) Mode Table 2.6 shows an example of the basic data setting. Table 2.6 Example of Look-up-Table Settings in 1-bpp (2-Gray-Level) Mode Index R look-up table G look-up table B look-up table 0 1 2-15 0 0 0 0 0xF 0 0 0 0 (2) 2-bpp (4-gray-level) mode Use the first four entries of the green look-up table. Select four pieces of data from the 16 gray levels, and write them to the respective entries. The data in entry 0 is output for pixel data "00", and the data in entry 3 is output for pixel data "11". "00" 2-bit pixel data "01" "10" "11" Index Green look-up table 0 1 2 3 4 : 15 4-bit grayscale data for pixel data "00" 4-bit grayscale data for pixel data "01" 4-bit grayscale data for pixel data "10" 4-bit grayscale data for pixel data "11" 4-bit display data Unused Figure 2.10 Look-up Table in 2-bpp (4-Gray-Level) Mode Table 2.7 shows an example of the basic data setting. Table 2.7 Example of Look-up-Table Settings in 2-bpp (4-Gray-Level) Mode B-VII-2-12 Index R look-up table G look-up table B look-up table 0 1 2 3 4-15 0 0 0 0 0 0 5 0xA 0xF 0 0 0 0 0 0 EPSON S1C33L03 FUNCTION PART VII LCD CONTROLLER BLOCK: LCD CONTROLLER (3) 4-bpp (16-gray-level) mode Use all entries of the green look-up table. All 16 gray levels can be assigned to the look-up table. The data in entry 0 is output for pixel data "0x0", and the data in entry 15 is output for pixel data "0xF". 0x0 0x1 0x2 4-bit pixel data 0x3 : 0xE 0xF Index Green look-up table 0 1 2 3 : 14 15 4-bit grayscale data for pixel data 0x0 4-bit grayscale data for pixel data 0x1 4-bit grayscale data for pixel data 0x2 4-bit grayscale data for pixel data 0x3 : 4-bit grayscale data for pixel data 0xE 4-bit grayscale data for pixel data 0xF A-1 4-bit display data Figure 2.11 Look-up Table in 4-bpp (16-Gray-Level) Mode Table 2.8 shows an example of the basic data setting. Table 2.8 Example of Look-up-Table Settings in 4-bpp (16-Gray-Level) Mode Index R look-up table G look-up table B look-up table 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 0xA 0xB 0xC 0xD 0xE 0xF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B-VII LCDC S1C33L03 FUNCTION PART EPSON B-VII-2-13 VII LCD CONTROLLER BLOCK: LCD CONTROLLER Color-mode look-up tables In color mode, the LCD controller uses the red (R), green (G), and blue (B) look-up tables. Each color element is represented by 4-bit data. RGB = 000 is black, RGB = F00 is red, RGB = 080 is 50% luminance green, RGB = F0F is magenta, RGB = FFF is white, and so on. In this way, colors are determined by the proportions of the three color elements. If the luminance of each color element is represented by 4 bits, then we obtain 16 x 16 x 16 = 4,096 colors. Of these, select as many pieces of color data as can be used for the available display mode (2, 4, 16, or 256 colors), and write them to the valid entries of the look-up tables before using the LCD panel. In personal-computer applications, the luminance of each color element is generally represented by 8 bits (0x00 to 0xFF). To set up the LCD panel by referring to those colors, write the 4 high-order bits of that data to the look-up tables. The differences in configurations between display modes are shown below. (1) 1-bpp (2-color) mode Use the first two entries of each look-up table. Select 2-color data from among the 4,096 colors, and write it to the respective entries. The RGB data in entry 0 is output for pixel data "0", and the RGB data in entry 1 is output for pixel data "1". For monochrome display, write 0x0 to entry 0 and 0xF to entry 1 in each of the red, green, and blue look-up tables before using the LCD panel. 1-bit pixel data "0" "1" Index Red look-up table 0 1 2 : 15 4-bit R data for pixel data "0" 4-bit R data for pixel data "1" 4-bit R display data Unused Index Green look-up table 0 1 2 : 15 4-bit G data for pixel data "0" 4-bit G data for pixel data "1" 4-bit G display data Unused Index Blue look-up table 0 1 2 : 15 4-bit B data for pixel data "0" 4-bit B data for pixel data "1" 4-bit B display data Unused Figure 2.12 Look-up Table in 1-bpp (2-Color) Mode Table 2.9 shows an example of the basic data setting. Table 2.9 Example of Look-up-Table Settings in 1-bpp (2-Color) Mode B-VII-2-14 Index R look-up table G look-up table B look-up table 0 1 2-15 0 0xF 0 0 0xF 0 0 0xF 0 EPSON S1C33L03 FUNCTION PART VII LCD CONTROLLER BLOCK: LCD CONTROLLER (2) 2-bpp (4-color) mode Use the first four entries of each look-up table. Select 4-color data from among the 4,096 colors, and write it to the respective entries. The RGB data in entry 0 is output for pixel data "00", and the RGB data in entry 3 is output for pixel data "11". "00" 2-bit pixel data "01" "10" "11" Index Red look-up table 0 1 2 3 4 : 15 4-bit R data for pixel data "00" 4-bit R data for pixel data "01" 4-bit R data for pixel data "10" 4-bit R data for pixel data "11" A-1 4-bit R display data Unused Index Green look-up table 0 1 2 3 4 : 15 4-bit G data for pixel data "00" 4-bit G data for pixel data "01" 4-bit G data for pixel data "10" 4-bit G data for pixel data "11" 4-bit G display data Unused Index Blue look-up table 0 1 2 3 4 : 15 4-bit B data for pixel data "00" 4-bit B data for pixel data "01" 4-bit B data for pixel data "10" 4-bit B data for pixel data "11" 4-bit B display data Unused Figure 2.13 Look-up Table in 2-bpp (4-Color) Mode Table 2.10 shows an example of the basic data setting. Table 2.10 Example of Look-up-Table Settings in 2-bpp (4-Color) Mode Index R look-up table G look-up table B look-up table 0 1 2 3 4-15 0 7 0xA 0xF 0 0 7 0xA 0xF 0 0 7 0xA 0xF 0 B-VII LCDC S1C33L03 FUNCTION PART EPSON B-VII-2-15 VII LCD CONTROLLER BLOCK: LCD CONTROLLER (3) 4-bpp (16-color) mode Use all entries of each look-up table. Select 16-color data from among the 4,096 colors, and write it to the respective entries. The RGB data in entry 0 is output for pixel data "0x0", and the RGB data in entry 15 is output for pixel data "0xF". 0x0 0x1 0x2 4-bit pixel data 0x3 : 0xE 0xF Index Red look-up table 0 1 2 3 : 14 15 4-bit R data for pixel data 0x0 4-bit R data for pixel data 0x1 4-bit R data for pixel data 0x2 4-bit R data for pixel data 0x3 : 4-bit R data for pixel data 0xE 4-bit R data for pixel data 0xF Index Green look-up table 0 1 2 3 : 14 15 4-bit G data for pixel data 0x0 4-bit G data for pixel data 0x1 4-bit G data for pixel data 0x2 4-bit G data for pixel data 0x3 : 4-bit G data for pixel data 0xE 4-bit G data for pixel data 0xF Index Blue look-up table 0 1 2 3 : 14 15 4-bit B data for pixel data 0x0 4-bit B data for pixel data 0x1 4-bit B data for pixel data 0x2 4-bit B data for pixel data 0x3 : 4-bit B data for pixel data 0xE 4-bit B data for pixel data 0xF 4-bit R display data 4-bit G display data 4-bit B display data Figure 2.14 Look-up Table in 4-bpp (16-Color) Mode Table 2.11 shows an example of the basic data setting. Table 2.11 Example of Look-up-Table Settings in 4-bpp (16-Color) Mode (VGA 16-Color-Mode Compatible) B-VII-2-16 Index R look-up table G look-up table B look-up table 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0xA 0xA 0xA 0xA 0 0 0 0 0xF 0xF 0xF 0xF 0 0 0xA 0xA 0 0 0xA 0xA 0 0 0xF 0xF 0 0 0xF 0xF 0 0xA 0 0xA 0 0xA 0 0xA 0 0xF 0 0xF 0 0xF 0 0xF EPSON S1C33L03 FUNCTION PART VII LCD CONTROLLER BLOCK: LCD CONTROLLER (4) 8-bpp (256-color) mode One pixel is represented by 8 bits, displayed in 256 colors. This mode is not available for grayscale display. In this mode, 256 discrete combinations are configured using eight entries in each of the red and green lookup tables, and four entries in the blue look-up table. Bits 5-7 in one byte of pixel data are used as an index to the red look-up table, while bits 2-4 and bits 0-1 are used as indices to the green and blue look-up tables, respectively. A-1 (bit 7) Pixel data (bit 0) R2 R1 R0 G2 G1 G0 B1 B0 Index Red look-up table 0 1 2 3 4 5 6 7 4-bit R data for R pixel data "000" 4-bit R data for R pixel data "001" 4-bit R data for R pixel data "010" 4-bit R data for R pixel data "011" 4-bit R data for R pixel data "100" 4-bit R data for R pixel data "101" 4-bit R data for R pixel data "110" 4-bit R data for R pixel data "111" "000" "001" "010" "011" "100" "101" "110" "111" 3-bit R pixel data Index Green look-up table 0 1 2 3 4 5 6 7 4-bit G data for G pixel data "000" 4-bit G data for G pixel data "001" 4-bit G data for G pixel data "010" 4-bit G data for G pixel data "011" 4-bit G data for G pixel data "100" 4-bit G data for G pixel data "101" 4-bit G data for G pixel data "110" 4-bit G data for G pixel data "111" "000" "001" "010" "011" "100" "101" "110" "111" 3-bit G pixel data 2-bit B pixel data Index Blue look-up table 0 1 2 3 4-bit B data for B pixel data "00" 4-bit B data for B pixel data "01" 4-bit B data for B pixel data "10" 4-bit B data for B pixel data "11" "00" "01" "10" "11" 4-bit R display data 4-bit G display data 4-bit B display data Figure 2.15 Look-up Table in 8-bpp (256-Color) Mode Table 2.12 shows an example of the basic data setting, using the display colors shown in Table 2.13. Table 2.12 Example of Look-up-Table Settings in 8-bpp (256-Color) Mode Index R look-up table G look-up table B look-up table 0 1 2 3 4 5 6 7 8-15 0 3 5 7 9 0xB 0xD 0xF 0 0 3 5 7 9 0xB 0xD 0xF 0 0 5 0xA 0xF 0 0 0 0 0 Table 2.13 Display Colors in the Above Setup Example Pixel data 000 000 00 000 000 10 000 100 00 000 100 10 100 000 00 100 000 10 100 100 00 100 100 10 Color Pixel data Black Dark blue Dark green Dark cyan Dark red Dark magenta Dark yellow Gray 000 000 00 000 000 11 000 111 00 000 111 11 111 000 00 111 000 11 111 111 00 111 111 11 Color Black Bright blue Bright green Bright cyan Bright red Bright magenta Bright yellow White B-VII LCDC S1C33L03 FUNCTION PART EPSON B-VII-2-17 VII LCD CONTROLLER BLOCK: LCD CONTROLLER Setting data in the look-up tables To set data in the look-up tables, use the look-up-table address register (0x39FFF5) and the look-up-table data register (0x39FFF7). Follow the procedure specified below in programming. 1. To the look-up-table address register (0x39FFF5), write the index (address) at which setting is to be started. When programming newly, write 0x0. When reading or writing to this register, be sure to access it bytewise. Writing any value to this register selects the specified index in the red look-up table. When 0x0 is written, for example, the beginning entry R[0] of the red look-up table is selected. 2. Write the 4-bit data in the entry R[0] specified in step 1 to LUTDT[3:0] (D[7:4])/look-up-table data register (0x39FFF7). The data corresponds to the 4 high-order bits of the register. Write 0 to the 4 loworder bits of the register. For grayscale mode, write 0x0 to this register. Writing any value to this register moves the internal pointer to the next entry, G[0]. The pointer moves in the following order each time data is written: R[0] G[0] B[0] R[1] G[1] B[1] When the index (address) changes, the look-up-table address register (0x39FFF5) is automatically incremented. 3. Write all necessary data in order of RGB. Notes: * Upon completion of writing all RGB data (4 bits x 3) in the same index to the look-up-table data register (0x39FFF7), the data is actually set in the look-up table. Therefore, even when only the green look-up table is used for display in grayscale mode, always be sure to write 0x0 to the red and blue look-up tables. * If the look-up-table address register (0x39FFF5) is set newly again during writing to any look-up table, the red look-up table is always selected. B-VII-2-18 EPSON S1C33L03 FUNCTION PART VII LCD CONTROLLER BLOCK: LCD CONTROLLER A-1 Frame Rates The frame rate is calculated from the LCD panel's resolution, non-display period, and pixel clock frequency, as shown below. fPCLK Frame rate = -------------------------------- (HDP + HNDP) x (VDP + VNDP) fPCLK: PCLK frequency (Hz) This is the input clock frequency for the LCD controller derived by dividing the BCU clock. The BCU-clock division ratio can be set to 1/1, 1/2, 1/3, or 1/4 using the LCLKSEL[2:0] (D[2:0])/FIFO control register (0x39FFF4). The LCD controller supports a PCLK clock of up to 25 MHz. HDP: Horizontal display period This is the LCD panel's horizontal resolution (in pixels). From the set value of LDHSIZE[5:0] (D[5:0])/horizontal panel size register (0x39FFE4), the horizontal display period is calculated as follows: Horizontal display period = (LDHSIZE[5:0] + 1) x 16 (Ts) where Ts = PCLK clock cycle HNDP: Horizontal non-display period This is a non-display period before the LCD panel starts displaying the next line after it has finished displaying all pixels in one line. Set a value in 8 pixel units in the HNDP[4:0] (D[4:0])/horizontal non-display period register (0x39FFE7). Horizontal non-display period = (HNDP[4:0] + 4) x 8 (Ts) The value HDP described above plus HNDP comprises the number of PCLK clock cycles per one-line period (FPLINE pulse period). VDP: Vertical display period This is the LCD panel's vertical resolution (number of display lines). From the set value of the LDVSIZE[9:0] (D[9:0])/vertical panel size register (0x39FFE6, 0x39FFE5), the vertical display period is calculated as follows: Vertical display period = LDVSIZE[9:0] + 1 (lines) VNDP: Vertical non-display period This is a non-display period before the LCD panel starts displaying the next frame after it has finished displaying all display lines in one frame. Set this period based on the number of lines in the VNDP[5:0] (D[5:0])/vertical non-display period register (0x39FFEA). Vertical non-display period = VNDP[5:0] (lines) From the above parameters, we obtain the number of PCLK clock cycles required for the display of one frame, as determined by (HDP + HNDP) x (VDP + VNDP). The frame rate is calculated by dividing the PCLK clock frequency by this value. B-VII LCDC S1C33L03 FUNCTION PART EPSON B-VII-2-19 VII LCD CONTROLLER BLOCK: LCD CONTROLLER Other Settings FPSHIFT mask When a color passive LCD panel is used, FPSHIFT (shift clock) can be turned on or off during the nondisplay period using FPSMASK (D2)/LCDC mode register 0 (0x39FFE1). FPSMASK = "1": Turned off FPSMASK = "0": Turned on (default) FPSMASK can only be set when LDCOLOR (D5)/LCDC mode register 0 (0x39FFE1) = "1" (color panel). Otherwise, FPSMASK has no effect. MOD rate The period during which the MOD signal is switched can be set using the MODRATE[5:0] (D[5:0])/MOD rate register (0x39FFEB). MODRATE = "0x0": MOD signal switched at a period of the FPFRAME signal (default) MODRATE = other than "0x0": Switched at a period of MODRATE + 1 FPLINE pulses Repeating of the FRM pattern This setup item is provided for EL panels. Whether the frame-rate modulation pattern is to be repeated every 0x40000 frames (counted by the internal frame counter) can be set using FRMRPT (D2)/LCDC mode register 1 (0x39FFE2). FRMRPT = "1": FRM pattern repeated FRMRPT = "0": FRM pattern not repeated (default) B-VII-2-20 EPSON S1C33L03 FUNCTION PART VII LCD CONTROLLER BLOCK: LCD CONTROLLER A-1 Display Control Controlling LCD Power Up/Down The LCD controller is activated to start up and generate LCD signals by setting LCDCEN (D5)/LCDC mode register 2 (0x39FFE3) to "1". Setting LCDCEN to "0" causes the LCD controller to stop operating, with the LCD signal output dropped low. For the LCD controller to start display correctly, the LCD-panel parameters and display data must be set before LCDCEN is set to "1". If the power to the LCD panel is turned on or off while LCD signals are not being correctly output, the panel may be damaged. Therefore, the power to the LCD panel must be turned on only after the LCD panel starts controlling LCD signals. The signal used to control the power to the LCD panel for this purpose is LCDPWR. Once the output pin for it is enabled, LCDPWR output is controlled in the hardware during the LCD power-up and power-down sequences of the LCD controller. When LCD signals have no effect, the LCDPWR signal goes low; when LCD signals become effective, the LCDPWR signal goes high. Controlling the power to the LCD panel using this signal ensures that the LCD panel is powered up and powered down safely. Control of the LCDPWR pin by the LCD controller is enabled by setting LPWREN (D4)/LCDC mode register 2 (0x39FFE3) to "1". Following power-on, the LCD controller is set in such a way that LCDCEN = "0" and power-save mode is on. Setting LCDCEN to "1" does not immediately cause the LCD panel to initiate a power-up sequence and start displaying data. The LCD panel is placed in power-save mode, with all LCD signal output pins fixed low. The LCDPWR signal is also fixed low, and the power to the LCD panel does not turn on. To change the LCD controller from power-save mode back into normal mode, set LPSAVE[1:0] (D[1:0])/LCDC mode register 2 (0x39FFE3) to "0b11". The LCD controller starts a power-up sequence from that point, and outputs LCD signals while driving the LCDPWR signal high (to turn on the power to the LCD panel). This powerup sequence requires a one-frame period. Conversely, to change from normal mode to power-save mode, set LPSAVE to "0b00". The LCD controller starts a power-down sequence from that point, and pulls the LCDPWR signal low a one-frame period later (to turn off the power to the LCD panel) while driving the LCD signals low. In power-save mode, furthermore, although the LCD control registers can be set, the look-up tables cannot be accessed. Before setting the look-up tables following power-on, place the LCD controller in normal mode. The procedure for initializing the LCD at power-on is summarized below. 1. Set the BCU, clock, and display memory area (refer to "System Settings"). 2. Set the LCD-panel parameters and display mode (refer to "Setting the LCD Panel"). 3. Write display data to the display memory. 4. Set the display start address (refer to "Setting the Display Start Address"). 5. Enable control of the LCDPWR signal (LPWREN = "1"). 6. Enable the LCD controller (LCDCEN = "1"). 7. Place the LCD controller in normal mode (LPSAVE = "0b11"). 8. The LCD controller starts a power-up sequence and the power to the LCD panel turns on a one-frame period later. 9. Set the look-up tables (refer to "Look-up Tables"). Thus, the above is the basic operation for starting up the display. B-VII LCDC S1C33L03 FUNCTION PART EPSON B-VII-2-21 VII LCD CONTROLLER BLOCK: LCD CONTROLLER The following is the power-down procedure. 1. Place the LCD controller in power-save mode (LPSAVE = "0b00"). 2. The LCD controller starts a power-down sequence and turns off the power to the LCD panel a one-frame period later, then pulls LCD signals low. 3. Because the bus clock is turned off during HALT2 or SLEEP mode, the one-frame period described above must elapse before the chip can be placed in standby mode. The number of frames can be counted by reading VNDPF (D7)/vertical non-display period register (0x39FFEA) repeatedly. VNDPF is set to "1" during the vertical non-display period (set to "0" during the display period). Depending on the power supply for the LCD panel, it may be necessary to secure more than one frame of power-on time, otherwise electricity may not be fully discharged within a one-frame period following power-off. In such a case, exclusive power-up/power-down sequences may be programmed. Control examples are shown below. Example of a power-up sequence (for controlling the length of time before the LCD power turns on after LCD signals are asserted) 1. Set LPWREN to "0". The LCDPWR signal is fixed low, with control by a power-up sequence disabled. 2. Release power-save mode (LPSAVE = "0b11"). 3. The LCD signals go active a one-frame period after step 2. 4. Allow for a wait time until the power turns on. To set the wait time in terms of the number of frames, count the occurrences of VNDPF = "1" (vertical non-display period). 5. Set LPWREN to "1" a specified length of time later. The LCDPWR pin goes high, causing the power to the LCD panel to turn ON. Example of a power-down sequence (for controlling the length of time before LCD signals are deasserted after the LCD power turns off) 1. Set LPWREN to "0". The LCDPWR pin goes low, and the power to the LCD panel turns off. 2. Allow for a wait time until LCD signals are deasserted. To set the wait time in terms of the number of frames, count the occurrences of VNDPF = "1" (vertical non-display period). 3. Set power-save mode a specified length of time later (LPSAVE = "0b00"). 4. LCD signals are deasserted a one-frame period after step 3. Reading/Writing Display Data The LCD controller contains an exclusive DMA interface, allowing data to be taken in from the display memory by means of DMA transfer. The display data read from the display memory is buffered in the internal 16 x 16-bit FIFO, preventing the bus efficiency from decreasing. If the data in the FIFO decreases to (0xf - FIFOEO[3:0]) words or less, the LCD controller outputs a DMA request to the CPU requesting that the data be read. Although any value from 0 to 0xf can be written to FIFOEO[3:0] (D[6:3])/FIFO control register (0x39FFF4), we recommend setting the value 8. There are no timing limitations when data is written to the display memory by a user program using the above DMA transfer. Data can be written asynchronously with the display. Setting the Display Start Address The LCD controller is initially set in such a way that data is displayed beginning with the initial address of the display memory (the area selected by the VRAMAR bit). Because the display memory address from which to start display can be changed as desired using the screen 1 start address register (0x39FFEC-0x39FFED, D0/0x39FFF0), it is possible to set a virtual screen for panning or scrolling, as will be described later. The start address set in the screen 1 start address register corresponds to the upper left edge of the LCD panel. The value that should actually be set in this register is an offset address from the beginning of the area in which the display memory exists. When area 7 is used, for example, the start address of the display memory is 0x0, rather than 0x400000. Be aware that the address set here is a halfword address (byte address for portrait mode; described later). B-VII-2-22 EPSON S1C33L03 FUNCTION PART VII LCD CONTROLLER BLOCK: LCD CONTROLLER A-1 Split-Screen Display The LCD controller supports a split-screen function, allowing different images to be displayed on two vertically split screens on the LCD panel. To discriminate between these two screens, the upper half of the LCD panel is referred to as "screen 1" and the lower half is referred to as "screen 2". Display memory LCD panel Screen 2 data Screen 1 Screen 2 start address S1VSIZE + 1 (lines) LDVSIZE + 1 (lines) Screen 1 data Screen 2 Screen 1 start address (LDHSIZE + 1) x 16 (pixels) Figure 2.16 Split-Screen Display A register similar to the screen 1 start address register described above is provided; it is called the "screen 2 start address register (0x39FFEE, 0x39FFEF)". Use this register to set the start address of screen 2. In the initial state, the start address of screen 2 is set to 0x0, as with screen 1. Use the number of lines on screen 1 to specify the position at which to divide between the two screens. To evenly split an LCD panel with 240 lines of vertical resolution into upper and lower halves, for example, set the value 119 in S1VSIZE[9:0] (D[9:0])/screen 1 vertical size register (0x39FFF3, 0x39FFF2). The LCD panel is separated into screen 1 consisting of lines 0-119, and screen 2 consisting of lines 120-239. In the initial state, S1VSIZE[9:0] is set to 0. As a result, screen 1 is nonexistent and screen 2 is displayed over the entire panel. To display only screen 1, set the same value in S1VSIZE[9:0] as that set in the LDVSIZE[9:0] (D[9:0])/vertical panel size register (0x39FFE6, 0x39FFE5). The entire screen can be changed instantaneously to different images by switching between S1VSIZE = LDVSIZE and S1VSIZE = 0. Virtual Screen and View Port The LCD controller has a virtual-screen function that allows any necessary portion of the screen to be displayed through panning or scrolling, by holding in memory than that required to achieve the resolution. However, because a virtual screen is configured within the display memory, it is limited in size to a maximum of 256K bytes. The area corresponding to the actual LCD panel size is referred to as a view port, and can be relocated within the virtual screen by changing the display start address. Virtual screen View port (LCD panel size) Figure 2.17 Virtual Screen and View Port The procedure for setting a virtual screen and panning or scrolling the view port is explained below, assuming that screen 1 is used. Because the view port than that required to achieve the resolution size is equal to that required to achieve the resolution of the LCD panel, the values set in the horizontal panel size register (0x39FFE4) and vertical panel size register (0x39FFE6, 0x39FFE5) are applied directly as they are. B-VII LCDC S1C33L03 FUNCTION PART EPSON B-VII-2-23 VII LCD CONTROLLER BLOCK: LCD CONTROLLER The starting position of the view port is changed by modifying the screen 1 start address register described above. For example, when the start address is incremented by 16 bits, the pixel displayed at the 17th dot on line 1 moves to the beginning of the line, and the 16 leading pixels move off the screen. This is the basic operation for panning an image. However, when this operation is performed, the 16 leading pixels on line 2 are normally displayed at the end of line 1, resulting in dislocation of the image. To prevent this problem, set an address offset between the last piece of pixel data on a line and the first piece of pixel data on the next line. Virtual screen Virtual screen Offset A (HW) B C View port (LCD panel size) View port (LCD panel size) Horizontal panel size Horizontal panel size B + C = A (HW) Figure 2.18 Offsets Comprising a Virtual Screen Set the offset value in the MADOFS[7:0] (D[7:0])/memory address offset register (0x39FFF1) as a halfword address. Be aware that if this address is calculated from the number of pixels, the offset value may change depending on the display mode. When configuring a 248-pixel virtual screen on a horizontal 200-pixel LCD panel, for example, an offset of 48 pixels is required. The offset value in 1-bpp mode is 3, whereas that in 8-bpp mode is 24. This setting allows the view port to be moved horizontally (panned) by an amount equal to the offset, by changing the screen 1 start address register. The values set in the screen 1 start address register are halfword addresses. Therefore, the view port is moved in 16-pixel units in 1-bpp mode, in 8-pixel units in 2-bpp mode, in 4-pixel units in 4-bpp mode, and in 2-pixel units in 8-bpp mode. Movement of the virtual screen in the vertical direction is determined by the installed memory capacity, which is limited to a maximum of 256K bytes of display memory. To scroll the view port down by one line, set a one-lineequivalent address plus an offset address in the screen 1 start address register. To scroll the view port up, decrement the register value. The view port can also be moved in a diagonal direction by controlling addresses. To scroll the view port in only the horizontal direction, do not add an offset (leave it at 0). Even when a virtual screen is used, the split-screen display described above is possible. Screen 2 can be panned or scrolled in the same way as for screen 1. Figure 2.19 shows an LCD-panel configuration when a virtual screen and split-screen display are used. Virtual screen in the display memory LCD panel Screen 1 start address Screen 1 view port Screen 1 Image 1 Screen 2 start address S1VSIZE + 1 (lines) LDVSIZE + 1 (lines) Screen 2 (LDHSIZE + 1) x 16 (pixels) Screen 2 view port Image 2 (LDHSIZE+1) x 16 / BPP (HW) Offset (HW) BPP = 1, 2, 4, or 8 (bpp) Figure 2.19 Virtual Screen and Split-Screen Display Note: In portrait mode (described later), the memory address offset register (0x39FFF1) has no effect. B-VII-2-24 EPSON S1C33L03 FUNCTION PART VII LCD CONTROLLER BLOCK: LCD CONTROLLER A-1 Inverting and Blanking the Display The display can be blanked (the entire screen turned black) without rewriting the contents of the display memory. Setting DBLANK (D3)/LCDC mode register 1 (0x39FFE2) to "1" causes the FPDAT signal to go low, blanking the display. Setting it to "0" turns the display back on. Furthermore, the display can be inverted simply by manipulating bits. Setting INVDISP (D0)/LCDC mode register 1 (0x39FFE2) to "1" inverts the display, and setting it to "0" returns the display to normal. This is accomplished by inverting the display data output from the look-up tables, rather than by inverting the pixel data in the display memory. The screen can be made to blink using these operations. Make sure switching takes place within the vertical nondisplay period (VNDPF = "1"). Portrait Mode Depending on the applications used, the LCD panel may normally be used while positioned horizontally, and may sometimes need to be used after being turned 90 degrees into a vertical position. Generally, image data should be rotated by software, which, however, adversely affects not only the display performance but also the performance of the entire system. The LCD controller supports this function in the hardware, enabling images to be rotated 90 degrees without increasing the load on the CPU. This function can be accomplished by setting the LCD controller to portrait mode. Depending on differences in memory usage and performance, two types of portrait modes (default and alternate portrait modes) are available. Default portrait mode Although inferior to alternate portrait mode in terms of display performance, default portrait mode is superior in terms of current consumption, as it enables the use of a slower clock. In this mode, the horizontal size of images must be increased by the power of 2. To display a horizontal 240-pixel image in default portrait mode, for example, memory must be available for 256 pixels (28) equivalent of horizontal size. 256 pixels 240 pixels E Line 1 320 pixels D B E A B Physical memory start address Screen 1 start address Line 240 C D 240 lines Unused area A C Image Image 320 lines Display memory LCD panel Figure 2.20 Image Rotation in Default Portrait Mode Figure 2.20 shows the relationship between the display memory and the LCD panel in cases in which a 320 x 240-pixel LCD panel is rotated 90 degrees to display a 240 x 320-pixel image. The control procedure described below is based on the assumption that the LCD panel is used in 8-bpp mode. 1. Make settings necessary to use an LCD panel consisting of 320 pixels horizontally and 240 lines vertically. If necessary, set it for display in normal (landscape) mode. 2. To switch from landscape mode to portrait mode, temporarily clear the display memory in advance. If switched over without clearing the display memory, the display may be distorted for a certain period. 3. If the LCD panel was split into two screens in landscape mode, reset the S1VSIZE[9:0] (D[9:0])/screen 1 vertical size register (0x39FFF3, 0x39FFF2) by setting a new value above the vertical resolution of the LCD panel. In portrait mode, the LCD panel cannot be split for display on screen 2. B-VII LCDC S1C33L03 FUNCTION PART EPSON B-VII-2-25 VII LCD CONTROLLER BLOCK: LCD CONTROLLER 4. Write a portrait-mode display image into memory, such as A B ... C D. 5. In the line byte-count register (0x39FFFC) for portrait-mode use, set the number of bytes equivalent to one virtual line of portrait display (256 pixels). For 8-bpp mode, with one pixel per byte, it is 256 bytes (0x100). Write 0x0 to the line byte-count register (0x39FFFC) for a one-byte line count. The value 0x0 is assumed to be 256 bytes per line. Therefore, the horizontal size of an image that can be displayed in 8bpp portrait mode is 256 pixels at maximum. For 4-bpp mode, with 2 pixels per byte, the byte count is 256/2 = 128 (0x80). This value indicates the distance in memory between one piece of pixel data and the next piece of pixel data when an image is displayed in portrait form. 6. Write the display memory address at which pixel B exists to the screen 1 start address register (0x39FFEC, 0x39FFED, D0/0x39FFF0). Although halfword addresses are set in this register in landscape mode, addresses must be set in byte units in portrait mode. In the example discussed here, because pixel A is at 0x0, the offset from A to B is 240 - 1 = 239 (0xEF) bytes. For 4-bpp mode, this is 240/2 - 1 = 119 (0x77) bytes. 7. If necessary, select the pixel clock frequency for use in portrait mode by using the PMODCLK[1:0] (D[1:0])/portrait mode register (0x39FFFB). This clock division circuit is provided specifically for portrait display on a small LCD panel. If the pixel clock frequency is changed here, the frame rate must be reviewed, including resetting of the non-display-period parameters. Table 2.14 Clock Settings for Default Portrait Mode PMODCLK1 PMODCLK0 Pixel clock PCLK Memory clock MCLK 0 0 1 1 0 1 0 1 CLK CLK/2 CLK/4 CLK/8 CLK CLK/2 CLK/4 CLK/8 CLK denotes the LCDC clock selected using the LCLKSEL[2:0] (D[2:0])/FIFO control register (0x39FFF4). 8. Set default portrait mode. PMODEN (D7)/portrait mode register (0x39FFFB) = "1" PMODSEL (D6)/portrait mode register (0x39FFFB) = "0" Upon completion of the above setting, the display mode is switched to portrait mode. In the example discussed here, the display memory contains blank space equivalent to 16 horizontal pixels. This portion can be used in the same way as a memory address offset, which is set in order to configure a virtual screen in landscape mode. Therefore, images can be panned within the scope of this number of pixels. The image displayed on the screen is moved to the left or right by incrementing or decrementing the screen 1 start address register in 1-byte units. Note that settings of the memory-address offset register have no effect in portrait mode. Images can also be scrolled in the vertical direction by changing the screen 1 start address register. Note: In default portrait mode, the screen cannot be scrolled in the vertical direction one line at a time. Always make sure the screen is scrolled two lines at a time. To this end, increment or decrement the screen 1 start address register by an amount equal to twice the number of bytes set in the line byte count register (0x39FFFC) in step 5. B-VII-2-26 EPSON S1C33L03 FUNCTION PART VII LCD CONTROLLER BLOCK: LCD CONTROLLER A-1 Alternate portrait mode Alternate portrait mode does not require extra display memory as in default portrait mode. To display the same horizontal 240-pixel image as in the above example, the display memory requires byte counts for only 240 pixels per line. Although alternate portrait mode provides higher display performance than default portrait mode, it requires a clock twice as fast at the same frame rate, resulting in larger current consumption. 240 pixels Screen 1 start address 320 pixels Line 1 D B B A D Line 240 Display memory 240 lines C C Image Image 320 lines A Physical memory start address LCD panel Figure 2.21 Image Rotation in Alternate Portrait Mode Figure 2.21 shows the relationship between the display memory and the LCD panel in cases in which a 320 x 240-pixel LCD panel is rotated 90 degrees to display a 240 x 320-pixel image. The control procedure described below assumes that the LCD panel is used in 8-bpp mode. 1. Make settings necessary to use an LCD panel consisting of 320 pixels horizontally and 240 lines vertically. If necessary, set it for display in normal (landscape) mode. 2. To switch from landscape mode to portrait mode, temporarily clear the display memory in advance. If switched over without clearing the display memory, the display may be distorted for a certain period. 3. If the LCD panel was split into two screens in landscape mode, reset the S1VSIZE[9:0] (D[9:0])/screen 1 vertical size register (0x39FFF2) by setting a new value above the vertical resolution of the LCD panel in it. In portrait mode, the LCD panel cannot be split for display on screen 2. 4. Write a portrait-mode display image into memory, such as A B ... C D. 5. In the line byte-count register (0x39FFFC) for portrait-mode use, set the number of bytes equivalent to one line of portrait display (240 pixels). For 8-bpp mode, with one pixel per byte, it is 240 bytes (0xF0). Write 0xF0 to the line byte-count register (0x39FFFC) for one-byte line count. Even in the case of alternate portrait mode, the horizontal size of an image that can be displayed in 8-bpp portrait mode is maximum of 256 pixels. For 4-bpp mode, with 2 pixels per byte, the byte count is 240/2 = 120 (0x78). This value indicates the distance in memory between one piece of pixel data and the next piece of pixel data when displayed in portrait mode. 6. Write the display memory address at which pixel B exists to the screen 1 start address register (0x39FFEC, 0x39FFED, D0/0x39FFF0). Although halfword addresses are set in this register in landscape mode, addresses must be set in byte units in portrait mode. In the example discussed here, because pixel A is at 0x0, the offset from A to B is 240 - 1 = 239 (0xEF) bytes. For 4-bpp mode, this is 240/2 - 1 = 119 (0x77) bytes. B-VII LCDC S1C33L03 FUNCTION PART EPSON B-VII-2-27 VII LCD CONTROLLER BLOCK: LCD CONTROLLER 7. If necessary, select the pixel clock frequency for use in portrait mode by using the PMODCLK[1:0] (D[1:0])/portrait mode register (0x39FFFB). Note that, in alternate portrait mode, the pixel clock frequency is halved compared to that in landscape mode, without specifically changing register settings. Therefore, the frame rate must be reviewed, including resetting of the non-display-period parameter. For details on calculating the frame rate, refer to "Frame Rate". Table 2.15 Clock Settings for Alternate Portrait Mode PMODCLK1 PMODCLK0 Pixel clock PCLK Memory clock MCLK 0 0 1 1 0 1 0 1 CLK/2 CLK/2 CLK/4 CLK/8 CLK CLK CLK/2 CLK/4 CLK denotes the LCDC clock selected using the LCLKSEL[2:0] (D[2:0])/FIFO control register (0x39FFF4). 8. Set alternate portrait mode. PMODEN (D7)/portrait-mode register (0x39FFFB) = "1" PMODSEL (D6)/portrait-mode register (0x39FFFB) = "1" Upon completion of the above setting, the display mode is switched to portrait mode. When using an LCD panel with a vertical resolution of less than 256 lines, a virtual screen similar to the one in default portrait mode can be configured. The screen can be panned or scrolled by setting a value (including offset) in the line byte count register, and then controlling the screen 1 start address register. In alternate portrait mode, the screen can be scrolled in the vertical direction one line at a time. Comparison of portrait modes The differences between default portrait mode and alternate portrait mode are summarized in Table 2.16. Table 2.16 Differences between Portrait Modes Parameter Display memory Clock Power consumption Vertical scroll Display performance B-VII-2-28 Default portrait mode Alternate portrait mode Sufficient display memory must be available so that the horizontal size following rotation is the original value to the power of 2. In many cases, that value differs from the LCD panel size, and an unused area occurs unless the value is used as a virtual screen. To display a 240 x 320-pixel image by rotating a 320 x 240-pixel LCD panel 90 degrees, for example, as much display memory as for a horizontal size of 28 = 256 pixels must be available. For 8-bpp mode, this is normally 320 x 240 = 76,800 bytes, but for portrait display, 256 x 320 = 81,920 bytes are required. MCLK for display memory access and the pixel clock PCLK for LCD display may be used at the same speed. The LCD controller can operate at low power. Can be scrolled two lines at a time. Standard performance. If a virtual screen is not being configured, no memory area other than that for the image size is required. EPSON MCLK must be twice as fast as PCLK. PCLK cannot be set to above 12.5 MHz. A greater amount of power than in default portrait mode is consumed. Can be scrolled one line at a time. Higher performance than default portrait mode. S1C33L03 FUNCTION PART VII LCD CONTROLLER BLOCK: LCD CONTROLLER A-1 Power Save The LCD controller has two types of power-save modes. Use LPSAVE[1:0] (D[1:0])/LCDC mode register 2 (0x39FFE3) to set power-save modes. Table 2.17 Settings of Power-Save Modes LPSAVE1 LPSAVE0 0 0 1 1 0 1 0 1 Mode Power-save mode Reserved Doze mode Normal operation Power-save mode When the LCD controller enters this mode, all LCD signal output pins, including the LCDPWR pin, are dropped low, with the LCD panel placed in power-down mode. All operations of the LCD controller, other than accessing of its control registers, are disabled. The look-up tables cannot be accessed. The LCD controller is placed in power-save mode by setting LPSAVE to "00", thereby executing a powerdown sequence. The LCDPWR signal goes low a one-frame period later, and LCD signals are deasserted. Note: Because the bus clock is turned off in HALT2 or SLEEP mode, the one-frame period described above must elapse before the chip can be placed in standby mode. The number of frames can be counted by reading the VNDPF (D7)/vertical non-display period register (0x39FFEA) repeatedly. VNDPF is set to "1" during the vertical non-display period (set to "0" during the display period). The LCD controller is taken out of power-save mode by setting LPSAVE to "11", thereby executing a powerup sequence. The LCD signal output is enabled and the LCDPWR signal goes high a one-frame period after power-save mode is released. The above power-up/power-down sequences can be controlled with a user's desired timing by using LPWREN (D4)/LCDC mode register 2 (0x39FFE3). For details on the control procedure, refer to "Controlling LCD Power Up/Down". Doze mode Doze mode is a power-save mode designed for use with Epson's MLS LCD drivers. When MLS LCD drivers are used, there is no need to send data constantly in order to refresh the display of the same image. The LCD controller can be set in doze mode during this period. In doze mode, the FPDAT and FPSHIFT signals are fixed low so that no access to the display memory occurs. Although the power-saving effects are not as significant as in power-save mode, this mode helps reduce the current consumption in the LCD panel while keeping the display on. Comparison of power-save modes The differences between power-save modes are summarized in Table 2.18. Table 2.18 Differences between Power-Save Modes Item Accessing IO registers Accessing look-up table Sequence controller in LCDC Display LCDPWR signal FPDAT[7:0], FPSHIFT signals FPLINE, FPFRAME, DRDY signals Doze mode Power-save mode Normal Enabled Enabled Run Display Active Forced low Active Enabled Disabled Stop Blank Inactive Forced low Forced low Enabled Enabled Run Display Active Active Active B-VII LCDC S1C33L03 FUNCTION PART EPSON B-VII-2-29 VII LCD CONTROLLER BLOCK: LCD CONTROLLER Controlling the GPIO Pins The pins described below can be used as general-purpose output (GPO) pins or general-purpose input/output (GPIO) pins, through panel selection or other settings. General-purpose output (GPO) pins The FPDAT[3:0] signal output pins can be used as general-purpose output GPO[6:3] pins when a 4-bit LCD panel (LDDW[1:0] (D[1:0])/0x39FFE1) = "00") is used. The GPO output control bits are listed in Table 2.19. Table 2.19 GOP Control Bits Pin name GPO signal name Output control bit FPDAT0 FPDAT1 FPDAT2 FPDAT3 GPO3 GPO4 GPO5 GPO6 GPO3D (D3)/GPIO status/control register(0x39FFF9) GPO4D (D4)/GPIO status/control register(0x39FFF9) GPO5D (D5)/GPIO status/control register(0x39FFF9) GPO6D (D6)/GPIO status/control register(0x39FFF9) Setting the GPOxD bit to 1 drives the GPOx output high, and setting the GPOxD bit to 0 drives the GPOx output low. Note: In power-save or doze mode, these pins are fixed low. General-purpose input/output (GPIO) pins While the LCD controller is enabled (LCDCEN (D5)/LCDC mode register 2 = "1"), bus release requests (#BUSREQ) from outside the chip can be disabled. When the BREQEN (D2)/LCDC system control register (0x39FFFD) is set to "0" (default), bus release requests from outside will no longer be accepted while LCDCEN = "1". As a result, the pins listed below will not be used for bus-release purposes, and can therefore be used as general-purpose input/output (GPIO) pins. Because these pins are usable only while the LCD controller remains enabled, the control registers in the LCD controller block must be used to control their direction for input or output, as well as to read/write data to and from them. Table 2.20 GPIO Control Bits Pin name GPIO signal name #BUSREQ/P34 GPIO0 #BUSACK/P35 GPIO1 #BUSGET/P31 GPIO2 I/O control bit GPIO0C (D0)/GPIO configuration register(0x39FFF8) GPIO1C (D1)/GPIO configuration register(0x39FFF8) GPIO2C (D2)/GPIO configuration register(0x39FFF8) I/O data GPIO0D (D0)/GPIO status/control register(0x39FFF9) GPIO1D (D1)/GPIO status/control register(0x39FFF9) GPIO2D (D2)/GPIO status/control register(0x39FFF9) Set the GPIOxC bits to "0" (default) when the GPIOx pins are used as input ports, or "1" when the GPIOx pins are used as output ports. When the pins are set for input, it possible to determine their input-voltage level by reading GPIOxD. The value "1" is indicated when the input voltage is high, and "0" indicated when the input voltage is low. When the pins are set for output, write output data to GPIOxD. Setting the GPIOxD bit to "1" drives the GPIOx output high, and setting the GPIOxD bit to "0" drives the GPIOx output low. B-VII-2-30 EPSON S1C33L03 FUNCTION PART VII LCD CONTROLLER BLOCK: LCD CONTROLLER A-1 I/O Memory of LCD Controller Table 2.21 shows the control bits of the LCD controller. These registers are mapped into area 6 (0x39FFE0 to 0x39FFFD). Table 2.21 Control Bits of LCD Controller Register name Address Bit Name Revision code register D7 D6 D5 D4 D3 D2 D1 D0 PCODE5 PCODE4 PCODE3 PCODE2 PCODE1 PCODE0 RCODE1 RCODE0 LCDC mode register 0 LCDC mode register 1 039FFE0 (B) 039FFE2 (B) BPP1 BPP0 Bit-per-pixel select (Display mode) - DBLANK FRMRPT - INVDISP reserved Blank display Frame repeat for EL panel reserved Invert display 039FFE3 D7-6 - (B) D5 LCDCEN D4 LPWREN D3-2 - D1 LPSAVE1 D0 LPSAVE0 Init. R/W Revision code reserved Color/monochrome select reserved Mask FPSHIFT signal LCD data width/format D7 D6 Setting 0b000010 039FFE1 D7-6 - (B) D5 LDCOLOR D4-3 - D2 FPSMASK D1 LDDW1 D0 LDDW0 D5-4 D3 D2 D1 D0 LCDC mode register 2 Function Product code reserved LCD controller enable LCDPWR enable reserved Power save mode - 1 Color 0 Mono - 1 Masked LDDW[1:0] 1 x 0 1 0 0 LDDW[1:0] 1 1 1 0 0 1 0 0 0 Output Monochrome reserved 8 bits 4 bits Color 8 bits/format 2 reserved 8 bits/format 1 4 bits BPP[1:0] 1 1 1 0 0 1 0 0 Mode 8 bpp 4 bpp 2 bpp 1 bpp - 1 Blank 1 Repeated 0 Normal 0 Not repeated - 1 Inverted 0 Normal - 1 Enabled 1 Enabled 0 Disabled 0 Disabled - LPSAVE[1:0] Mode 1 1 Normal operation 1 0 Doze 0 1 reserved 0 0 Power save 0 0 0 0 1 0 0 0 Remarks R R - 0 - 0 0 0 - 0 when being read. R/W - 0 when being read. R/W R/W 0 0 R/W - 0 0 - 0 - 0 when being read. R/W R/W - 0 when being read. R/W - 0 0 - 0 0 - 0 when being read. R/W R/W - 0 when being read. R/W Horizontal panel size register 039FFE4 D7-6 - reserved (B) D5 LDHSIZE5 Horizontal panel size D4 LDHSIZE4 D3 LDHSIZE3 D2 LDHSIZE2 D1 LDHSIZE1 D0 LDHSIZE0 - H resolution (pixels) -1 16 - 0 0 0 0 0 0 - 0 when being read. R/W Vertical panel size register 0 039FFE5 (B) LDVSIZE7 Vertical panel size LDVSIZE6 (low-order 8 bits) LDVSIZE5 LDVSIZE4 LDVSIZE3 LDVSIZE2 LDVSIZE1 LDVSIZE0 V resolution (lines) - 1 0 0 0 0 0 0 0 0 R/W Vertical panel size register 1 039FFE6 D7-2 - reserved (B) D1 LDVSIZE9 Vertical panel size D0 LDVSIZE8 (high-order 2 bits) - V resolution (lines) - 1 - 0 0 - 0 when being read. R/W - Non-display period (pixels) -4 8 - 0 0 0 0 0 - 0 when being read. R/W D7 D6 D5 D4 D3 D2 D1 D0 Horizontal 039FFE7 D7-5 - non-display (B) D4 HNDP4 period register D3 HNDP3 D2 HNDP2 D1 HNDP1 D0 HNDP0 S1C33L03 FUNCTION PART reserved Horizontal non-display period EPSON B-VII LCDC B-VII-2-31 VII LCD CONTROLLER BLOCK: LCD CONTROLLER Register name Address Bit Vertical 039FFEA non-display (B) period register D7 D6 D5 D4 D3 D2 D1 D0 Name VNDPF - VNDP5 VNDP4 VNDP3 VNDP2 VNDP1 VNDP0 Function Setting Vertical non-display period status 1 VNDP 0 Display - reserved Non display period (lines) Vertical non-display period - Init. R/W Remarks 0 - 0 0 0 0 0 0 R - 0 when being read. R/W - 0 0 0 0 0 0 - 0 when being read. R/W MOD rate register 039FFEB D7-6 - reserved (B) D5 MODRATE5 MOD rate D4 MODRATE4 D3 MODRATE3 D2 MODRATE2 D1 MODRATE1 D0 MODRATE0 Screen 1 start address register 0 039FFEC (B) D7 D6 D5 D4 D3 D2 D1 D0 S1ADDR7 S1ADDR6 S1ADDR5 S1ADDR4 S1ADDR3 S1ADDR2 S1ADDR1 S1ADDR0 Screen 1 start address (low-order 8 bits) 0 0 0 0 0 0 0 0 R/W Screen 1 start address register 1 039FFED (B) D7 D6 D5 D4 D3 D2 D1 D0 S1ADDR15 Screen 1 start address S1ADDR14 (high-order 8 bits) S1ADDR13 S1ADDR12 S1ADDR11 S1ADDR10 S1ADDR9 S1ADDR8 0 0 0 0 0 0 0 0 R/W Screen 2 start address register 0 039FFEE (B) D7 D6 D5 D4 D3 D2 D1 D0 S2ADDR7 S2ADDR6 S2ADDR5 S2ADDR4 S2ADDR3 S2ADDR2 S2ADDR1 S2ADDR0 Screen 2 start address (low-order 8 bits) 0 0 0 0 0 0 0 0 R/W Screen 2 start address register 1 039FFEF (B) D7 D6 D5 D4 D3 D2 D1 D0 S2ADDR15 Screen 2 start address S2ADDR14 (high-order 8 bits) S2ADDR13 S2ADDR12 S2ADDR11 S2ADDR10 S2ADDR9 S2ADDR8 0 0 0 0 0 0 0 0 R/W Screen 1 start address register 2 039FFF0 D7-1 - reserved (B) D0 S1ADDR16 Screen 1 start address (MSB) (for portrait mode; fix at 0 in landscape mode) - 0 - 0 when being read. R/W - Memory 039FFF1 address offset (B) register D7 D6 D5 D4 D3 D2 D1 D0 MADOFS7 Memory address offset MADOFS6 MADOFS5 MADOFS4 MADOFS3 MADOFS2 MADOFS1 MADOFS0 0 0 0 0 0 0 0 0 R/W Screen 1 vertical size register 0 D7 D6 D5 D4 D3 D2 D1 D0 S1VSIZE7 S1VSIZE6 S1VSIZE5 S1VSIZE4 S1VSIZE3 S1VSIZE2 S1VSIZE1 S1VSIZE0 0 0 0 0 0 0 0 0 R/W B-VII-2-32 039FFF2 (B) Screen 1 vertical size (low-order 8 bits) EPSON S1C33L03 FUNCTION PART VII LCD CONTROLLER BLOCK: LCD CONTROLLER A-1 Register name Address Bit Name Screen 1 vertical size register 1 039FFF3 D7-2 - (B) D1 S1VSIZE9 D0 S1VSIZE8 FIFO control register 039FFF4 (B) D7 D6 D5 D4 D3 D2 D1 D0 Function Setting reserved Screen 1 vertical size (high-order 2 bits) - reserved FIFOEO3 FIFO empty offset FIFOEO2 FIFOEO1 FIFOEO0 LCLKSEL2 LCDC clock select LCLKSEL1 LCLKSEL0 - 0 0 - 0 when being read. R/W - Fix at 8 (0b1000) - 0 0 0 0 0 0 0 - 0 when being read. R/W - 0 0 0 0 - 0 when being read. R/W 0 0 0 0 - R/W 0 Input 0 Input 0 Input - 0 0 0 - 0 when being read. R/W R/W R/W 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 R/W 0 0 - 0 0 R/W R/W - 0 when being read. R/W 0 0 0 0 0 0 0 0 R/W LCLKSEL[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 LCDC clock BCU_CLK/4 BCU_CLK/3 BCU_CLK/2 BCU_CLK reserved Stop Stop Stop 039FFF5 D7-4 - reserved (B) D3 LUTADDR3 Look-up table address D2 LUTADDR2 D1 LUTADDR1 D0 LUTADDR0 Look-up table data register 039FFF7 (B) reserved - GPIO configuration register 039FFF8 D7-3 - (B) D2 GPIO2C D1 GPIO1C D0 GPIO0C reserved GPIO2 configuration GPIO1 configuration GPIO0 configuration - 1 Output 1 Output 1 Output GPIO status/control register 039FFF9 (B) D7 D6 D5 D4 D3 D2 D1 D0 - GPO6D GPO5D GPO4D GPO3D GPIO2D GPIO1D GPIO0D reserved GPO6 data GPO5 data GPO4 data GPO3 data GPIO2 data GPIO1 data GPIO0 data 1 1 1 1 1 1 1 Scratch pad register 039FFFA (B) D7 D6 D5 D4 D3 D2 D1 D0 SP1A7 SP1A6 SP1A5 SP1A4 SP1A3 SP1A2 SP1A1 SP1A0 Scratch pad Portrait mode register 039FFFB (B) D7 D6 D5-2 D1 D0 PMODEN PMODSEL - PMODCLK1 PMODCLK0 Portrait mode enable Portrait mode select reserved Portrait mode clock select (LCDC clock division ratio) LUTDT3 LUTDT2 LUTDT1 LUTDT0 - Line byte count register for portrait mode 039FFFC (B) D7 D6 D5 D4 D3 D2 D1 D0 - Look-up table data - Division ratio 1: Default mode Division ratio 2: Alternate mode P: Pixel clock, M: Memory clock PMODLBC7 Line byte count PMODLBC6 PMODLBC5 PMODLBC4 PMODLBC3 PMODLBC2 PMODLBC1 PMODLBC0 Remarks - Look-up table address register D7 D6 D5 D4 D3-0 Init. R/W High High High High High High High 1 Portrait 1 Alternate Low Low Low Low Low Low Low 0 Landscape 0 Default - PMODCLK[1:0] Division ratio 1 1 1 P: 1/8, M: 1/8 1 0 P: 1/4, M: 1/4 0 1 P: 1/2, M: 1/2 0 0 P: 1/1, M: 1/1 PMODCLK[1:0] Division ratio 2 1 1 P: 1/8, M: 1/4 1 0 P: 1/4, M: 1/2 0 1 P: 1/2, M: 1/1 0 0 P: 1/2, M: 1/1 R/W - 0 when being read. B-VII LCDC S1C33L03 FUNCTION PART EPSON B-VII-2-33 VII LCD CONTROLLER BLOCK: LCD CONTROLLER Register name Address Bit Name LCDC 039FFFD system control (B) register D7 D6 D5 D4 D3 D2 D1 D0 VRAMAR VRAMWT2 VRAMWT1 VRAMWT0 EDMAEN BREQEN LCDCST LCDCEC Function Setting VRAM area select 1 Area 8 VRAM wait control (number of wait cycles for SRAM) External DMA enable External bus-request enable A0/BSL select Big/little endian select 1 1 1 1 Init. R/W 0 Area 7 0-7 Enabled Enabled BSL Big endian 0 0 0 0 Disabled Disabled A0 Little endian 0 0 0 0 0 0 0 0 Remarks R/W R/W R/W R/W R/W R/W Note: Addresses 0x39FFFE and 0x39FFFF are assigned for the purpose of inspecting the LCD controller. Writing data to these addresses may damage the LCD controller and the LCD panel to which the LCD controller is connected. Therefore, make sure data is never written to that location. PCODE[5:0]: Product code (D[7:2]) / Revision code register (0x39FFE0) The LCD controller's product code (0b000010) is written here. These bits are read-only, and writing to them has no effect. RCODE[1:0]: Revision code (D[1:0]) / Revision code register (0x39FFE0) The LCD controller's revision code (0b00) is written here. These bits are read-only, and writing to them has no effect. LDCOLOR: Color/monochrome select (D5) / LCDC mode register 0 (0x39FFE1) Selects the type of connected LCD panel (color or monochrome). Write "1": Color panel Write "0": Monochrome panel Read: Valid Setting LDCOLOR to "1" selects a color panel drive method, and setting it to "0" selects a monochrome panel drive method. At initial reset, LDCOLOR is set to "0" (monochrome panel). FPSMASK: Mask FPSHIFT signal (D2) / LCDC mode register 0 (0x39FFE1) Selects the FPSHIFT mask (effective only for color LCD panels). Write "1": Masked Write "0": Output Read: Valid When FPSMASK is set to "1", the FPSHIFT signal is masked and is not output during the non-display period. When FPSMASK is set to "0", the FPSHIFT signal is output even during the non-display period. This setting is effective only for color LCD panels (LDCOLOR = "1"). When a monochrome LCD panel is used, the FPSHIFT signal is not masked regardless of the setting of this bit. At initial reset, FPSMASK is set to "0" (output). LDDW[1:0]: LCD data width/format (D[1:0]) / LCDC mode register 0 (0x39FFE1) Selects the LCD panel's data width and format. The contents of selection, including that of LDCOLOR, are listed in Table 2.22. Table 2.22 Selection of LCD Panels LDCOLOR LDDW1 LDDW0 LCD panel 0 0 0 1 0 1 0 1 0 1 Mono Single 4-bit passive LCD Mono Single 8-bit passive LCD Reserved Reserved Color Single 4-bit passive LCD Color Single 8-bit passive LCD format 1 Reserved Color Single 8-bit passive LCD format 2 1 1 0 1 At initial reset, LDDW is set to "0b00" (4-bit panel). B-VII-2-34 EPSON S1C33L03 FUNCTION PART VII LCD CONTROLLER BLOCK: LCD CONTROLLER BPP[1:0]: Bit-per-pixel select (D[7:6]) / LCDC mode register 1 (0x39FFE2) Selects display mode (bpp mode). The contents of selection, including that of LDCOLOR, are listed in Table 2.23. A-1 Table 2.23 Specification of Display Modes LDCOLOR BPP1 BPP0 Display mode 0 0 0 1 0 1 0 1 0 1 2 gray scale 1 bit-per-pixel 4 gray scale 2 bit-per-pixel 16 gray scale 4 bit-per-pixel Reserved 2 colors 1 bit-per-pixel 4 colors 2 bit-per-pixel 16 colors 4 bit-per-pixel 256 colors 8 bit-per-pixel 1 1 0 1 At initial reset, BPP is set to "0b00" (1-bpp mode). DBLANK: Blank display (D3) / LCDC mode register 1 (0x39FFE2) Clears the display (entire screen turned black). Write "1": Blank Write "0": Normal display Read: Valid When DBLANK is set to "1", all FPDAT signals are dropped low to clear the display. When DBLANK is set to "0", data in the display memory is displayed on the LCD panel. This setting does not affect the display memory. At initial reset, DBLANK is set to "0" (normal display). FRMRPT: Frame repeat for EL panel (D2) / LCDC mode register 1 (0x39FFE2) Selects whether to repeat the frame-rate modulation pattern (effective only for EL panels). Write "1": Repeated Write "0": Not repeated Read: Valid When FRMRPT is set to "1", the internal 19-bit frame counter is enabled and starts counting the number of frames. Each time this counter overflows (0x40000 = 0), the frame-rate modulation pattern is repeated. When FRMRPT is set to "0", the counter is disabled and the frame-rate modulation pattern is not repeated. At initial reset, FRMRPT is set to "0" (not repeated). INVDISP: Invert display (D0) / LCDC mode register 1 (0x39FFE2) Inverts the display. Write "1": Inverted Write "0": Normal display Read: Valid When INVDISP is set to "1", the display on the LCD panel is inverted (displayed in inverse video). When INVDISP is set to "0", normal display is maintained. Invers operation is applied to output of the look-up tables, and does not affect the display memory. At initial reset, INVDISP is set to "0" (normal display). LCDCEN: Enable LCDC (D5) / LCDC mode register 2 (0x39FFE3) Enables the LCD controller for use. Write "1": Enabled Write "0": Disabled Read: Valid When LCDCEN is set to "1", the LCD controller is supplied with a clock and starts operating. When LCDCEN is set to "0", the LCD controller stops operating. Note that if the power to the LCD panel turns on while LCD signals are not output correctly, the LCD panel may be degraded or damaged. At initial reset, LCDCEN is set to "0" (disabled). S1C33L03 FUNCTION PART EPSON B-VII-2-35 B-VII LCDC VII LCD CONTROLLER BLOCK: LCD CONTROLLER LPWREN: Enable LCDPWR (D4) / LCDC mode register 2 (0x39FFE3) Enables LCDPWR output control by the LCD controller. Write "1": Enabled Write "0": Disabled Read: Valid When LPWREN is set to "1", the LCDPWR output is controlled by the LCD controller's power-up/down sequence, allowing the power to the LCD panel to be turned ON or OFF using that signal. When LPWREN is set to "0", the LCDPWR pin is fixed low. At initial reset, LPWREN is set to "0" (disabled). LPSAVE[1:0]: Power-save mode (D[1:0]) / LCDC mode register 2 (0x39FFE3) Selects power-save mode. Table 2.24 Settings of Power-Save Modes LPSAVE1 LPSAVE0 0 0 1 1 0 1 0 1 Mode Power-save mode Reserved Doze mode Normal operation When placed in power-save mode, the LCD controller executes a power-down sequence; when taken out of powersave mode, the LCD controller executes a power-up sequence (for details, refer to "Controlling LCD Power Up/Down"). Doze mode can only be selected when Epson's MLS LCD drivers are used. At initial reset, LPSAVE is set to "0b00" (power-save mode). LDHSIZE[5:0]: Horizontal panel size (D[5:0]) / Horizontal panel size register (0x39FFE4) Sets the horizontal resolution of the LCD panel in 16-pixel units. Set the value obtained using the equation below. Horizontal resolution (in pixels) LDHSIZE[5:0] = ---------------------------- - 1 16 For an LCD panel with a horizontal resolution of 320 dots, for example, set 19 (= 0x13) in LDHSIZE. Do not set any value less than 1 in this register. At initial reset, LDHSIZE is set to "0x0". LDVSIZE[9:0]: Vertical panel size (D[9:0]) / Vertical panel size register (D[1:0]/0x39FFE6, 0x39FFE5) Sets the vertical resolution of the LCD panel in units of lines. Set the value obtained using the equation below. LDVSIZE[9:0] = Vertical resolution (in lines) - 1 For an LCD panel with a vertical resolution of 240 lines, for example, set 239 (= 0xEF) in LDVSIZE. At initial reset, LDVSIZE is set to "0x0". HNDP[4:0]: Horizontal non-display period (D[4:0]) / Horizontal non-display period register (0x39FFE7) Sets the horizontal non-display period in 8-pixel units. Set the value obtained using the equation below. Horizontal non-display period (in pixels) HNDP[4:0] = ------------------------------------ - 4 8 At initial reset, HNDP is set to "0x0". VNDP[5:0]: Vertical non-display period (D[5:0]) / Vertical non-display period register (0x39FFEA) Sets the vertical non-display period in units of lines. Set the value obtained using the equation below. VNDP[5:0] = Vertical non-display period (in lines) At initial reset, VNDP is set to "0x0". B-VII-2-36 EPSON S1C33L03 FUNCTION PART VII LCD CONTROLLER BLOCK: LCD CONTROLLER A-1 VNDPF: Vertical non-display status (D7) / Vertical non-display period register (0x39FFEA) Indicates whether the LCD panel is in a vertical non-display period. Read "1": Vertical non-display period Read "0": Vertical display period Write: Invalid VNDPF is set to "1" during a vertical non-display period, and set to "0" during a vertical display period. To count the number of frames in LCD power control, for example, read this bit and count the number of times it is set to "1". On other occasions, such as when images must be switched without causing the screen to flicker, it is possible to switch within a vertical non-display period by reading this bit. At initial reset, VNDPF is set to "0" (vertical display period). MODRATE[5:0]: MOD rate (D[5:0]) / MOD rate register (0x39FFEB) Sets the cycle time at which to switch the MOD signal. When this register is 0x0, the MOD signal switches at the cycle time of the FPFRAME signal. If another period is desired, set the FPLINE pulse-count value. At initial reset, MODRATE is set to "0x0" (FPFRAME period). S1ADDR[16:0]: Screen 1 start address register (D0/0x39FFF0, 0x39FFED, 0x39FFEC) Sets the screen 1 start address. Referencing the beginning of the display memory as address 0x0, write a halfword address in 16-bit units in normal (landscape) mode, or a byte address in portrait mode. S1ADDR16 (D0/0x39FFF0) is provided for use in portrait mode. It is unused in normal (landscape) mode, so fix it to "0". At initial reset, S1ADDR is set to "0x0" (beginning of the display memory). S1VSIZE[9:0]: Screen 1 vertical size register (D[1:0]/0x39FFF3, 0x39FFF2) Sets the vertical size of screen 1 in lines. If any number of lines less than the LCD panel's vertical resolution (LDVSIZE[9:0]) is set in this register, the LCD panel is divided into an upper half from line 1 to line (S1VSIZE 1) as screen 1, and a lower half from that line down as screen 2. When the screen is not to be divided, set any value equal to or greater than LDVSIZE in this register, so that only screen 1 will be displayed. At initial reset, S1VSIZE is set to "0x0". S2ADDR[15:0]: Screen 2 start address register (0x39FFEF, 0x39FFEE) Sets the screen 2 start address. Referencing the beginning of the display memory as address 0x0, write a halfword address in 16-bit units. This register is unused for portrait mode, as split-screen display is not supported in that mode. At initial reset, S2ADDR is set to "0x0" (beginning of the display memory). MADOFS[7:0]: Memory address offset (D[7:0]) / Memory address offset register (0x39FFF1) Sets an address offset in halfword units to configure a virtual screen in normal (landscape) mode. The offset set here is added to the address of the last piece of pixel data on each display line, in order to determine the address at which the next display line starts. The image area is extended in the horizontal direction by a distance equal to this offset, so that the display area can be panned or scrolled by setting the start-address register as necessary. For details, refer to "Virtual Screen and View Port". This register is unused in portrait mode. At initial reset, MADOFS is set to "0x0" (no virtual screen area). FIFOEO[3:0]: FIFO empty offset (D[6:3]) / FIFO control register (0x39FFF4) The LCD controller retrieves data from the display memory into its 16 x 16-bit FIFO by means of a DMA transfer. If the amount of data in this FIFO decreases to (0xf - FIFOEO) words or less, the LCD controller sends a DMA request to the CPU requesting that the data be read. Set the value 8 in FIFOEO. At initial reset, FIFOEO is set to "0x0". B-VII LCDC S1C33L03 FUNCTION PART EPSON B-VII-2-37 VII LCD CONTROLLER BLOCK: LCD CONTROLLER LCLKSEL[2:0]: LCDC clock select (D[2:0]) / FIFO control register (0x39FFF4) Selects the operating clock for the LCD controller. The selected clock is used as the LCD controller's pixel clock PCLK and display memory clock MCLK. The maximum clock frequency that can be supplied to the LCD controller is 25 MHz. Table 2.25 Selection of LCDC Clocks LCLKSEL2 LCLKSEL1 LCLKSEL0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 LCDC clock Turned off Turned off Turned off Reserved (not allowed) BCU_CLK BCU_CLK/2 BCU_CLK/3 BCU_CLK/4 At initial reset, LCLKSEL is set to "0x0" (clock turned off). LUTADDR[3:0]: LUT address (D[3:0]) / Look-up table address register (0x39FFF5) Specifies the initial address (entry) of the look-up table in which to write data. Writing data (0-15) to this register selects an entry (0-15) in the red look-up table. When data is set in the look-up-table data registers in order of red, green, and blue, the data is written to the specified entries in the red, green, and blue look-up tables. LUTADDR is incremented at the same time data is written, indicating the next entry. Once an entry is specified, data can be written to the look-up tables successively. The entry address is also incremented in the same way when data is read from the look-up-table data registers. This register must always be accessed bytewise for both reading and writing. At initial reset, LUTADDR is set to "0x0" (entry 0 in the red look-up table). LUTDT[3:0]: LUT data (D[7:4]) / Look-up table data register (0x39FFF7) Use this register to read or write to the look-up tables. Each time this register is accessed, the look-up-table pointer changes in the order shown below (provided that the look-up-table address register is set to 0x0). R[0]G[0]B[0](LUTADDR incremented)R[1]G[1]B[1] The data set in the look-up tables can be read out by reading this register. When read, the 4 low-order bits of the register are set to 0x0. The data written to this register are set in the look-up tables. Note, however, that no data is set in the look-up tables until data is written to the register three times, in order of red, green, and blue. Write 0x0 to the 4 low-order bits of the register. At initial reset, LUTDT is set to "0x0". GPIO2C: GPIO2 configuration (D2) / GPIO configuration register (0x39FFF8) GPIO1C: GPIO1 configuration (D1) / GPIO configuration register (0x39FFF8) GPIO0C: GPIO0 configuration (D0) / GPIO configuration register (0x39FFF8) Selects the input/output modes of the GPIO[2:0] pins. Write "1": Output mode Write "0": Input mode Read: Valid Setting GPIOxC to "1" directs GPIOx for output, and setting GPIOxC to "0" directs GPIOx for input. The GPIO[2:0] pins are shared with the bus release pins listed below. These pins can only be used as GPIO[2:0] pins when LCDCEN (D5/0x39FFE3) = "1" and BREQEN (D2/0x39FFFD) = "0". GPIO2: #BUSGET/P31 GPIO1: #BUSACK/P35 GPIO0: #BUSREQ/P34 At initial reset, GPIOxC is set to "0" (input mode). B-VII-2-38 EPSON S1C33L03 FUNCTION PART VII LCD CONTROLLER BLOCK: LCD CONTROLLER A-1 GPIO2D: GPIO2 data (D2) / GPIO status/control register (0x39FFF9) GPIO1D: GPIO1 data (D1) / GPIO status/control register (0x39FFF9) GPIO0D: GPIO0 data (D0) / GPIO status/control register (0x39FFF9) Input/output data for GPIO[2:0] pins. In output mode Write "1": High level Write "0": Low level Read: Valid In input mode Read "1": High level Read "0": Low level Write: Invalid When GPIOx is set as the output mode, writing "1" to GPIOxD drives the GPIOx pin high, and writing "0" drives the GPIOx pin low. In input mode, the value "1" is read from GPIOxD when the input-voltage level on the GPIOx pin is high, and the value "0" is read when the input-voltage level is low. At initial reset, GPIOxD is set to "0" (low). GPO6D: GPO6 data (D6) / GPIO status/control register (0x39FFF9) GPO5D: GPO5 data (D5) / GPIO status/control register (0x39FFF9) GPO4D: GPO4 data (D4) / GPIO status/control register (0x39FFF9) GPO3D: GPO3 data (D3) / GPIO status/control register (0x39FFF9) Sets the data to be output from the GPO[6:3] pins. Write "1": High level Write "0": Low level Read: Valid Writing "1" to GPOxD drives the GPOx pin high, and writing "0" drives the GPOx pin low. The GPO[6:3] pins are shared with the LCD signal output pins listed below. These pins can only be used for general-purpose output when a 4-bit LCD panel is selected. GPO6: FPDAT3 GPO5: FPDAT2 GPO4: FPDAT1 GPO3: FPDAT0 At initial reset, GPOxD is set to "0" (low). SP1A[7:0]: Scratch pad (D[7:0]) / Scratch pad register (0x39FFFA) This is a readable/writable 8-bit general-purpose register. It does not affect the operation of the chip, including the LCD controller itself. At initial reset, SP1A is set to "0x0". PMODEN: Enable portrait mode (D7) / Portrait mode register (0x39FFFB) Switches the display to portrait mode. Write "1": Portrait mode Write "0": Landscape (normal) mode Read: Valid Setting PMODEN to "1" places the LCD controller in a type of portrait mode selected by PMODSEL (D6/0x39FFFB), producing a display suitable for a 90-degree-rotated LCD panel. Setting PMODEN to "0" selects normal landscape mode. At initial reset, PMODEN is set to "0" (landscape mode). B-VII LCDC S1C33L03 FUNCTION PART EPSON B-VII-2-39 VII LCD CONTROLLER BLOCK: LCD CONTROLLER PMODSEL: Portrait mode select (D6) / Portrait mode register (0x39FFFB) Selects a type of portrait mode. Write "1": Alternate portrait mode Write "0": Default portrait mode Read: Valid Setting PMODSEL to "1" selects alternate portrait mode, and setting PMODSEL to "0" selects default portrait mode. When PMODEN (D7/0x39FFFB) is set to "1", data is displayed in the selected portrait mode. For details, refer to "Portrait Mode". At initial reset, PMODSEL is set to "0" (default portrait mode). PMODCLK[1:0]: Portrait mode clock select (D[1:0]) / Portrait mode register (0x39FFFB) Selects the clock used in portrait mode. In alternate portrait mode, the MCLK clock used for display memory access must be twice as fast as the pixel clock, PCLK. Therefore, clock settings differ between the alternate and default portrait modes. Table 2.26 Clock Settings for Default Portrait Mode PMODCLK1 PMODCLK0 Pixel clock PCLK Memory clock MCLK 0 0 1 1 0 1 0 1 CLK CLK/2 CLK/4 CLK/8 CLK CLK/2 CLK/4 CLK/8 Table 2.27 Clock Settings for Alternate Portrait Mode PMODCLK1 PMODCLK0 Pixel clock PCLK Memory clock MCLK 0 0 1 1 0 1 0 1 CLK/2 CLK/2 CLK/4 CLK/8 CLK CLK CLK/2 CLK/4 CLK denotes the clock for landscape mode (PCLK = MCLK), which is selected by LCLKSEL[2:0] (D[2:0]/0x39FFF4). At initial reset, PMODCLK is set to "0b00". PMODLBC[7:0]: Line byte count (D[7:0]) / Line byte count register (0x39FFFC) Sets the number of bytes equivalent to one line in portrait mode. For this line byte count, write the number of horizontal pixels converted into the number of bytes available in bpp mode. These horizontal pixels include the number of pixels in a virtual portion of the screen that is not displayed on the LCD panel. At initial reset, PMODLBC is set to "0x0". VRAMAR: VRAM area select (D7) / LCDC system control register (0x39FFFD) Selects the area in which the display memory is located. Write "1": Area 8 (or 14) Write "0": Area 7 (or 13) Read: Valid Setting VRAMAR to "1" selects area 8 (when CEFUNC[1:0] (D[A:9]/0x48130) = "0b00") or area 14 (when CEFUNC = "0b01"), and setting VRAMAR to "0" selects area 7 (when CEFUNC = "0b00") or area 13 (when CEFUNC = "0b01"). At initial reset, VRAMAR is set to "0" (area 7). VRAMWT[2:0]: VRAM wait control (D[6:4]) / LCDC system control register (0x39FFFD) Sets the number of wait cycles (0-7) for display memory access. This setting is effective only when SRAM is used for the display memory. Settings of this register are ignored when SDRAM is used. The number of wait cycles set here is inserted when the LCD controller accesses the display memory. It does not affect display-memory access by the CPU. In that case, the number of wait cycles set for the BCU is inserted. At initial reset, VRAMWT is set to "0x0". B-VII-2-40 EPSON S1C33L03 FUNCTION PART VII LCD CONTROLLER BLOCK: LCD CONTROLLER A-1 EDMAEN: Enable external DMA (D3) / LCDC system control register (0x39FFFD) Enables/disables DMA requests from external devices while the LCD controller is in use. Write "1": Enabled Write "0": Disabled Read: Valid Setting EDMAEN to "1" enables DMA requests from other external devices even while the LCD controller is in use. During a DMA transfer by one of these external devices, the LCD controller cannot access the display memory and therefore cannot update the display. Setting EDMAEN to "0" disables DMA requests from external devices only while the LCD controller is in use (LCDCEN = "1"). At initial reset, EDMAEN is set to "0" (disabled). BREQEN: Enable external bus request (D2) / LCDC system control register (0x39FFFD) Enables/disables bus release requests from external devices while the LCD controller is in use. Write "1": Enabled Write "0": Disabled Read: Valid Setting BREQEN to "1" enables bus release requests from other external devices even while the LCD controller is in use. While the bus is being used by one of these external devices, the LCD controller cannot access the display memory and therefore cannot update the display. Setting BREQEN to "0" disables bus release requests from external devices only while the LCD controller is in use (LCDCEN = "1"). At initial reset, BREQEN is set to "0" (disabled). LCDCST: A0/BSL select (D1) / LCDC system control register (0x39FFFD) Selects the display memory (SRAM) interface method. Write "1": BSL Write "0": A0 Read: Valid This setting is only effective when SRAM is used for the display memory. Set the same value here as set in SBUSST (D3/0x4812E) for the BCU. When SDRAM is used, the settings of this register are ignored. At initial reset, LCDCST is set to "0" (A0). LCDCEC: Big/Little endian select (D0) / LCDC system control register (0x39FFFD) Selects the LCD controller's access format (little or big endian). Write "1": Big endian Write "0": Little endian Read: Valid Setting LCDCEC to "1" causes the LCD controller to be accessed in big endian format, and setting LCDCEC to "0" causes it to be accessed in little endian format. Set the same value here as set in A6EC (D1/0x48132) for area 6. At initial reset, LCDCEC is set to "0" (little endian). B-VII LCDC S1C33L03 FUNCTION PART EPSON B-VII-2-41 VII LCD CONTROLLER BLOCK: LCD CONTROLLER Programming Notes (1) When the chip is set in HALT2 or SLEEP mode after the LCD controller is set in power-save mode, it is necessary to wait until all LCD signals are turned off by the controller's power-down sequence (by default, a one-frame period). If the chip is placed in HALT2 or SLEEP mode while LCD signals are being output, the LCD panel may be damaged due to stoppage of the clock. (2) When LPWREN (D4)/LCDC mode register 2 (0x39FFE3) is used to control the LCDPWR output, be careful to ensure that LCD signals are not turned off while the power to the LCD panel remains on. During a powerdown state in particular, allow a sufficient wait time, after dropping the LCDPWR output low for LCD power-discharging before turning the LCD signals off. (3) I/O-area addresses 0x39FFFE and 0x39FFFF are assigned for use in inspection of the LCD controller. Writing data to these addresses may damage the LCD controller and the LCD panel to which the LCD controller is connected. Therefore, make sure data is never written to that location. Precautions on Using ICD33 Follow the precautions described below when using the ICD33 (S5U1C33000H) for debugging an application, which uses this LCD controller. 1. When #WAIT is enabled, do not dump (including displays using the [Memory] window) or set the contents from/to the LCDC register area (0x39FFE0-0x39FFFF). This operation inserts wait states permanently and the debugger hangs. The same problem results when the target program accesses the LCDC register area during execution. When ICD33 is used for debugging, be sure to disable #WAIT (D0/0x4812E = "0") before the LCDC register area is accessed in a debugging operation or from the target program. 2. When the target program stops execution by a break factor during debugging with the ICD33, the LCD display goes off until the program resumes execution. Therefore, do not use the ICD33 for debugging a target system, which uses an EPSON MLS driver for driving the LCD panel. In this case, use the MON33 (S5U1C330M1D1) for debugging, since the LCD display does not go off in a break state so it allows debugging. B-VII-2-42 EPSON S1C33L03 FUNCTION PART VII LCD CONTROLLER BLOCK: LCD CONTROLLER A-1 Examples of LCD Controller Setting Program (Wait signal = ON) ;****************** ;C33L03 ASM ;****************** ;=================================== .org 0x0 .half 0x0008 .half 0x00c0 .org 0x0008 ;--------------------------;initial ;--------------------------xld.w %r1, 0x1fff ld.w %sp, %r1 ;stack poiter xld.w xld.w ld.b %r5, 0x48126 %r1, 0x0 [%r5], %r1 ;ROM access speed xld.w xld.w ld.b %r5, 0x48128 %r1, 0x00 [%r5], %r1 ;Ram wait cycle 0 access speed xld.w ld.h %r5, 0x4812a [%r5], %r1 ;set area6 wait cycle xld.w xld.w ld.b %r5, 0x4812e %r1, 0x05 [%r5], %r1 ;set bus control register wait enable , a0 mode xld.w xld.w ld.h %r5,0x48132 %r1,0xff00 [%r5],%r1 ;set area6 access control register xld.w xld.w ld.b %r5,0x4813a %r1,0x01 [%r5],%r1 ;select bclk output xld.w xld.w ld.b %r1, 0x39ffe3 %r2, 0x20 [%r1], %r2 ;lcd enable xld.w xld.w ld.b %r5, 0x402dc %r1, 0x30 [%r5], %r1 ;set busack,req,wait ;****************************************************** ;** ;**test color 4/8bit 1/2/4/8 bpp ,video invert, ;** segment ,common landscape mode/virtual image ;** display blank ;****************************************************** ;set landscape mode ;*********************************** ;color ,8bit , 8bpp,segment32 x 3 ;*********************************** xld.w %r1, 0x39ffe1 ; write-- set mono,4-bit xld.w %r2, 0x04 ld.b [%r1], %r2 xld.w xld.w ld.b %r1, 0x39ffe2 %r2, 0x40 [%r1], %r2 ; write-- set 2bpp,no high performance,disable display bland ; no invert video xld.w xld.w ld.b %r1, 0x39ffe4 %r2, 0x01 [%r1], %r2 ; set segment 32 xld.w xld.w ld.b %r1, 0x39ffe5 %r2, 0x01 [%r1], %r2 ; set common B-VII xld.w xld.w %r1, 0x39ffe8 %r2, 0x01 ; set Horizontal Non-display period LCDC S1C33L03 FUNCTION PART EPSON B-VII-2-43 VII LCD CONTROLLER BLOCK: LCD CONTROLLER ld.b [%r1], %r2 xld.w xld.w ld.b %r1, 0x39ffea %r2, 0x01 [%r1], %r2 ; set Vertical Non-displayed Period xld.w xld.w ld.h %r1, 0x39ffec %r2, 0x0000 [%r1], %r2 ; set S1 start address aaaa xld.w xld.w ld.h %r1, 0x39ffee %r2, 0x0000 [%r1], %r2 ; set S2 start address 5555 xld.w xld.w ld.b %r1, 0x39fff1 %r2, 0x00 [%r1], %r2 ; set Memory address offset xld.w xld.w ld.h %r1, 0x39fff2 %r2, 0x0100 [%r1], %r2 ; set S1 Vertical size xld.w xld.w ld.b %r1, 0x39fff4 %r2, 0x04 [%r1], %r2 ; set clk ->osc3 , fifo ->0 00 0x01df lsb ;----------------------------------xld.w %r1, 0x39ffe3 ; LCD power on xld.w %r2, 0x23 ld.b [%r1], %r2 ;****************************************************** ;** Initialize the LUT ;****************************************************** xld.w xld.w xld.w ld.b ld.b ld.b ld.b B-VII-2-44 %r1, 0x39fff5 %r2, 0x39fff7 %r3, 0x00 [%r1], %r3 [%r2], %r3 [%r2], %r3 [%r2], %r3 ; set lut address EPSON S1C33L03 FUNCTION PART S1C33L03 FUNCTION PART Appendix I/O MAP APPENDIX: I/O MAP A-1 Register name Address 8-bit timer 4/5 clock select register 0040140 (B) 8-bit timer 4/5 clock control register 0040145 (B) Bit Name D7-2 - D1 P8TPCK5 D0 P8TPCK4 D7 D6 D5 D4 D3 D2 D1 D0 P8TON5 P8TS52 P8TS51 P8TS50 P8TON4 P8TS42 P8TS41 P8TS40 Function reserved 8-bit timer 5 clock selection 8-bit timer 4 clock selection 8-bit timer 5 clock control 8-bit timer 5 clock division ratio selection 8-bit timer 4 clock control 8-bit timer 4 clock division ratio selection 8-bit timer clock select register 0040146 (B) D7-4 D3 D2 D1 D0 - P8TPCK3 P8TPCK2 P8TPCK1 P8TPCK0 reserved 8-bit timer 3 clock selection 8-bit timer 2 clock selection 8-bit timer 1 clock selection 8-bit timer 0 clock selection 16-bit timer 0 clock control register 0040147 (B) D7-4 D3 D2 D1 D0 - P16TON0 P16TS02 P16TS01 P16TS00 reserved 16-bit timer 0 clock control 16-bit timer 0 clock division ratio selection 16-bit timer 1 clock control register 0040148 (B) D7-4 D3 D2 D1 D0 - P16TON1 P16TS12 P16TS11 P16TS10 reserved 16-bit timer 1 clock control 16-bit timer 1 clock division ratio selection 16-bit timer 2 clock control register 0040149 (B) D7-4 D3 D2 D1 D0 - P16TON2 P16TS22 P16TS21 P16TS20 reserved 16-bit timer 2 clock control 16-bit timer 2 clock division ratio selection Setting Init. - - 0 0 - 0 when being read. R/W : selected by R/W Prescaler clock select register (0x40181) 0 0 0 0 R/W R/W : selected by R/W Prescaler clock select R/W register (0x40181) 1 /1 1 /1 1 On 1 1 1 1 1 0 1 0 0 1 0 1 0 0 0 0 1 On 1 1 1 1 1 0 1 0 0 1 0 1 0 0 0 0 0 Divided clk. 0 Divided clk. 0 Off /256 /128 /64 /32 /16 /8 /4 /2 0 Off /4096 /2048 /64 /32 /16 /8 /4 /2 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 - 1 1 1 1 /1 /1 /1 /1 0 0 0 0 Divided clk. Divided clk. Divided clk. Divided clk. - 1 On P16TS0[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 Off Division ratio /4096 /1024 /256 /64 /16 /4 /2 /1 - 1 On P16TS1[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 Off Division ratio /4096 /1024 /256 /64 /16 /4 /2 /1 - 1 On P16TS2[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 Off Division ratio /4096 /1024 /256 /64 /16 /4 /2 /1 R/W Remarks 8-bit timer 5 can generate the clock for the serial I/F Ch.3. 0 0 0 0 R/W R/W : selected by R/W Prescaler clock select R/W register (0x40181) 8-bit timer 4 can generate the clock for the serial I/F Ch.2. - 0 0 0 0 - R/W R/W R/W R/W 0 when being read. : selected by Prescaler clock select register (0x40181) - 0 0 0 0 - 0 when being read. R/W R/W : selected by Prescaler clock select register (0x40181) 16-bit timer 0 can be used as a watchdog timer. - 0 0 0 0 - 0 when being read. R/W R/W : selected by Prescaler clock select register (0x40181) - 0 0 0 0 - 0 when being read. R/W R/W : selected by Prescaler clock select register (0x40181) (B) in [Address] indicates an 8-bit register and (HW) indicates a 16-bit register. The meaning of the symbols described in [Init.] are listed below: 0, 1: Initial values that are set at initial reset. (However, the registers for the bus and input/output ports are not initialized at hot start.) X: Not initialized at initial reset. -: Not set in the circuit. B-ap S1C33L03 FUNCTION PART EPSON B-APPENDIX-1 APPENDIX: I/O MAP Register name Address Bit Name Function 16-bit timer 3 clock control register 004014A D7-4 - (B) D3 P16TON3 D2 P16TS32 D1 P16TS31 D0 P16TS30 reserved 16-bit timer 3 clock control 16-bit timer 3 clock division ratio selection 16-bit timer 4 clock control register 004014B D7-4 - (B) D3 P16TON4 D2 P16TS42 D1 P16TS41 D0 P16TS40 reserved 16-bit timer 4 clock control 16-bit timer 4 clock division ratio selection 16-bit timer 5 clock control register 004014C D7-4 - (B) D3 P16TON5 D2 P16TS52 D1 P16TS51 D0 P16TS50 reserved 16-bit timer 5 clock control 16-bit timer 5 clock division ratio selection 8-bit timer 0/1 clock control register 004014D (B) 8-bit timer 1 clock control 8-bit timer 1 clock division ratio selection D7 D6 D5 D4 D3 D2 D1 D0 B-APPENDIX-2 P8TON1 P8TS12 P8TS11 P8TS10 P8TON0 P8TS02 P8TS01 P8TS00 8-bit timer 0 clock control 8-bit timer 0 clock division ratio selection EPSON Setting - 1 On P16TS3[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 Off Division ratio /4096 /1024 /256 /64 /16 /4 /2 /1 - 1 On P16TS4[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 Off Division ratio /4096 /1024 /256 /64 /16 /4 /2 /1 - 1 On P16TS5[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 Off Division ratio /4096 /1024 /256 /64 /16 /4 /2 /1 1 On P8TS1[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 1 On P8TS0[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 Off Division ratio /4096 /2048 /1024 /512 /256 /128 /64 /32 0 Off Division ratio /256 /128 /64 /32 /16 /8 /4 /2 Init. R/W Remarks - 0 0 0 0 - 0 when being read. R/W R/W : selected by Prescaler clock select register (0x40181) - 0 0 0 0 - 0 when being read. R/W R/W : selected by Prescaler clock select register (0x40181) - 0 0 0 0 - 0 when being read. R/W R/W : selected by Prescaler clock select register (0x40181) 0 0 0 0 R/W R/W : selected by Prescaler clock select register (0x40181) 8-bit timer 1 can generate the OSC3 oscillation-stabilize waiting period. 0 0 0 0 R/W R/W : selected by Prescaler clock select register (0x40181) 8-bit timer 0 can generate the DRAM refresh clock. S1C33L03 FUNCTION PART APPENDIX: I/O MAP A-1 Register name Address Bit Name 8-bit timer 2/3 clock control register D7 D6 D5 D4 P8TON3 P8TS32 P8TS31 P8TS30 004014E (B) D3 D2 D1 D0 P8TON2 P8TS22 P8TS21 P8TS20 A/D clock 004014F control register (B) D7-4 D3 D2 D1 D0 Clock timer Run/Stop register D7-2 - D1 TCRST D0 TCRUN 0040151 (B) Clock timer 0040152 interrupt (B) control register Clock timer 0040153 divider register (B) Clock timer second register 0040154 (B) - PSONAD PSAD2 PSAD1 PSAD0 Function 8-bit timer 3 clock control 8-bit timer 3 clock division ratio selection 8-bit timer 2 clock control 8-bit timer 2 clock division ratio selection reserved A/D converter clock control A/D converter clock division ratio selection reserved Clock timer reset Clock timer Run/Stop control Setting 1 On P8TS3[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 1 On P8TS2[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 Init. R/W 0 Off Division ratio /256 /128 /64 /32 /16 /8 /4 /2 0 Off Division ratio /4096 /2048 /64 /32 /16 /8 /4 /2 - 8-bit timer 3 can generate the clock for the serial I/F Ch.1. 0 0 0 0 R/W R/W : selected by Prescaler clock select register (0x40181) 8-bit timer 2 can generate the clock for the serial I/F Ch.0. - 0 when being read. R/W R/W : selected by Prescaler clock select register (0x40181) - X X - 0 when being read. W 0 when being read. R/W X X X R/W X X X R/W X X R/W Reset by writing 1. R/W Reset by writing 1. Low Low Low Low Low Low Low Low X X X X X X X X R R R R R R R R - 0 to 59 seconds - X X X X X X - R 0 Off Division ratio /256 /128 /64 /32 /16 /8 /4 /2 - 1 Reset 1 Run 0 Invalid 0 Stop D7 D6 D5 TCISE2 TCISE1 TCISE0 D4 D3 D2 TCASE2 TCASE1 TCASE0 D1 D0 TCIF TCAF TCISE[2:0] Interrupt factor 1 1 1 None 1 1 0 Day 1 0 1 Hour 1 0 0 Minute 0 1 1 1 Hz 0 1 0 2 Hz 0 0 1 8 Hz 0 0 0 32 Hz Alarm factor Clock timer alarm factor selection TCASE[2:0] 1 X X Day X 1 X Hour X X 1 Minute 0 0 0 None 1 Generated 0 Not generated Interrupt factor generation flag 1 Generated 0 Not generated Alarm factor generation flag D7 D6 D5 D4 D3 D2 D1 D0 TCD7 TCD6 TCD5 TCD4 TCD3 TCD2 TCD1 TCD0 Clock timer data 1 Hz Clock timer data 2 Hz Clock timer data 4 Hz Clock timer data 8 Hz Clock timer data 16 Hz Clock timer data 32 Hz Clock timer data 64 Hz Clock timer data 128 Hz - TCMD5 TCMD4 TCMD3 TCMD2 TCMD1 TCMD0 reserved Clock timer second counter data TCMD5 = MSB TCMD0 = LSB D7-6 D5 D4 D3 D2 D1 D0 R/W R/W : selected by Prescaler clock select register (0x40181) - 0 0 0 0 1 On P8TS0[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 Clock timer interrupt factor selection 1 1 1 1 1 1 1 1 0 0 0 0 Remarks High High High High High High High High 0 0 0 0 0 0 0 0 0 when being read. B-ap S1C33L03 FUNCTION PART EPSON B-APPENDIX-3 APPENDIX: I/O MAP Register name Address Bit Clock timer 0040155 minute register (B) D7-6 D5 D4 D3 D2 D1 D0 - TCHD5 TCHD4 TCHD3 TCHD2 TCHD1 TCHD0 reserved Clock timer minute counter data TCHD5 = MSB TCHD0 = LSB Clock timer hour register D7-5 D4 D3 D2 D1 D0 - TCDD4 TCDD3 TCDD2 TCDD1 TCDD0 Clock timer 0040157 day (low-order) (B) register D7 D6 D5 D4 D3 D2 D1 D0 Clock timer day (highorder) register 0040158 (B) Clock timer minute comparison register 0040159 (B) Clock timer hour comparison register Clock timer day comparison register B-APPENDIX-4 Name Function Setting Init. R/W Remarks - 0 to 59 minutes - X X X X X X - 0 when being read. R/W reserved Clock timer hour counter data TCDD4 = MSB TCDD0 = LSB - 0 to 23 hours - X X X X X - 0 when being read. R/W TCND7 TCND6 TCND5 TCND4 TCND3 TCND2 TCND1 TCND0 Clock timer day counter data (low-order 8 bits) TCND0 = LSB 0 to 65535 days (low-order 8 bits) X X X X X X X X R/W D7 D6 D5 D4 D3 D2 D1 D0 TCND15 TCND14 TCND13 TCND12 TCND11 TCND10 TCND9 TCND8 Clock timer day counter data (high-order 8 bits) TCND15 = MSB 0 to 65535 days (high-order 8 bits) X X X X X X X X R/W D7-6 D5 D4 D3 D2 D1 D0 - TCCH5 TCCH4 TCCH3 TCCH2 TCCH1 TCCH0 reserved Clock timer minute comparison data TCCH5 = MSB TCCH0 = LSB - 0 to 59 minutes (Note) Can be set within 0-63. - X X X X X X - 0 when being read. R/W 004015A D7-5 - (B) D4 TCCD4 D3 TCCD3 D2 TCCD2 D1 TCCD1 D0 TCCD0 reserved - 0 to 23 hours Clock timer hour comparison data (Note) Can be set within 0-31. TCCD4 = MSB TCCD0 = LSB - X X X X X - 0 when being read. R/W 004015B D7-5 - (B) D4 TCCN4 D3 TCCN3 D2 TCCN2 D1 TCCN1 D0 TCCN0 reserved Clock timer day comparison data TCCN4 = MSB TCCN0 = LSB - X X X X X - 0 when being read. R/W Compared with TCND[4:0]. 0040156 (B) EPSON - 0 to 31 days S1C33L03 FUNCTION PART APPENDIX: I/O MAP A-1 Register name Address Bit 8-bit timer 0 0040160 control register (B) D7-3 D2 D1 D0 Name Function - PTOUT0 PSET0 PTRUN0 reserved 8-bit timer 0 clock output control 8-bit timer 0 preset 8-bit timer 0 Run/Stop control Setting - 1 On 1 Preset 1 Run 0 Off 0 Invalid 0 Stop Init. R/W Remarks - 0 - 0 - 0 when being read. R/W W 0 when being read. R/W 8-bit timer 0 reload data register 0040161 (B) D7 D6 D5 D4 D3 D2 D1 D0 RLD07 RLD06 RLD05 RLD04 RLD03 RLD02 RLD01 RLD00 8-bit timer 0 reload data RLD07 = MSB RLD00 = LSB 0 to 255 X X X X X X X X R/W 8-bit timer 0 counter data register 0040162 (B) D7 D6 D5 D4 D3 D2 D1 D0 PTD07 PTD06 PTD05 PTD04 PTD03 PTD02 PTD01 PTD00 8-bit timer 0 counter data PTD07 = MSB PTD00 = LSB 0 to 255 X X X X X X X X R - PTOUT1 PSET1 PTRUN1 reserved 8-bit timer 1 clock output control 8-bit timer 1 preset 8-bit timer 1 Run/Stop control - - 0 - 0 - 0 when being read. R/W W 0 when being read. R/W 8-bit timer 1 0040164 control register (B) D7-3 D2 D1 D0 1 On 1 Preset 1 Run 0 Off 0 Invalid 0 Stop 8-bit timer 1 reload data register 0040165 (B) D7 D6 D5 D4 D3 D2 D1 D0 RLD17 RLD16 RLD15 RLD14 RLD13 RLD12 RLD11 RLD10 8-bit timer 1 reload data RLD17 = MSB RLD10 = LSB 0 to 255 X X X X X X X X R/W 8-bit timer 1 counter data register 0040166 (B) D7 D6 D5 D4 D3 D2 D1 D0 PTD17 PTD16 PTD15 PTD14 PTD13 PTD12 PTD11 PTD10 8-bit timer 1 counter data PTD17 = MSB PTD10 = LSB 0 to 255 X X X X X X X X R - PTOUT2 PSET2 PTRUN2 reserved 8-bit timer 2 clock output control 8-bit timer 2 preset 8-bit timer 2 Run/Stop control - - 0 - 0 - 0 when being read. R/W W 0 when being read. R/W 8-bit timer 2 0040168 control register (B) D7-3 D2 D1 D0 1 On 1 Preset 1 Run 0 Off 0 Invalid 0 Stop 8-bit timer 2 reload data register 0040169 (B) D7 D6 D5 D4 D3 D2 D1 D0 RLD27 RLD26 RLD25 RLD24 RLD23 RLD22 RLD21 RLD20 8-bit timer 2 reload data RLD27 = MSB RLD20 = LSB 0 to 255 X X X X X X X X R/W 8-bit timer 2 counter data register 004016A (B) D7 D6 D5 D4 D3 D2 D1 D0 PTD27 PTD26 PTD25 PTD24 PTD23 PTD22 PTD21 PTD20 8-bit timer 2 counter data PTD27 = MSB PTD20 = LSB 0 to 255 X X X X X X X X R B-ap S1C33L03 FUNCTION PART EPSON B-APPENDIX-5 APPENDIX: I/O MAP Register name Address Bit Name Function 8-bit timer 3 004016C D7-3 - control register (B) D2 PTOUT3 D1 PSET3 D0 PTRUN3 reserved 8-bit timer 3 clock output control 8-bit timer 3 preset 8-bit timer 3 Run/Stop control 8-bit timer 3 reload data register 004016D (B) D7 D6 D5 D4 D3 D2 D1 D0 RLD37 RLD36 RLD35 RLD34 RLD33 RLD32 RLD31 RLD30 8-bit timer 3 reload data RLD37 = MSB RLD30 = LSB 8-bit timer 3 counter data register 004016E (B) D7 D6 D5 D4 D3 D2 D1 D0 PTD37 PTD36 PTD35 PTD34 PTD33 PTD32 PTD31 PTD30 8-bit timer 3 counter data PTD37 = MSB PTD30 = LSB - PTOUT4 PSET4 PTRUN4 reserved 8-bit timer 4 clock output control 8-bit timer 4 preset 8-bit timer 4 Run/Stop control 8-bit timer 4 0040174 control register (B) D7-3 D2 D1 D0 Setting - Init. R/W Remarks - 0 - 0 - 0 when being read. R/W W 0 when being read. R/W 0 to 255 X X X X X X X X R/W 0 to 255 X X X X X X X X R - - 0 - 0 - 0 when being read. R/W W 0 when being read. R/W 1 On 1 Preset 1 Run 0 Off 0 Invalid 0 Stop 1 On 1 Preset 1 Run 0 Off 0 Invalid 0 Stop 8-bit timer 4 reload data register 0040175 (B) D7 D6 D5 D4 D3 D2 D1 D0 RLD47 RLD46 RLD45 RLD44 RLD43 RLD42 RLD41 RLD40 8-bit timer 4 reload data RLD47 = MSB RLD40 = LSB 0 to 255 X X X X X X X X R/W 8-bit timer 4 counter data register 0040176 (B) D7 D6 D5 D4 D3 D2 D1 D0 PTD47 PTD46 PTD45 PTD44 PTD43 PTD42 PTD41 PTD40 8-bit timer 4 counter data PTD47 = MSB PTD40 = LSB 0 to 255 X X X X X X X X R - PTOUT5 PSET5 PTRUN5 reserved 8-bit timer 5 clock output control 8-bit timer 5 preset 8-bit timer 5 Run/Stop control - - 0 - 0 - 0 when being read. R/W W 0 when being read. R/W 8-bit timer 5 0040178 control register (B) D7-3 D2 D1 D0 1 On 1 Preset 1 Run 0 Off 0 Invalid 0 Stop 8-bit timer 5 reload data register 0040179 (B) D7 D6 D5 D4 D3 D2 D1 D0 RLD57 RLD56 RLD55 RLD54 RLD53 RLD52 RLD51 RLD50 8-bit timer 5 reload data RLD57 = MSB RLD50 = LSB 0 to 255 X X X X X X X X R/W 8-bit timer 5 counter data register 004017A (B) D7 D6 D5 D4 D3 D2 D1 D0 PTD57 PTD56 PTD55 PTD54 PTD53 PTD52 PTD51 PTD50 8-bit timer 5 counter data PTD57 = MSB PTD50 = LSB 0 to 255 X X X X X X X X R B-APPENDIX-6 EPSON S1C33L03 FUNCTION PART APPENDIX: I/O MAP A-1 Register name Address Bit Name Function Setting Init. R/W Remarks Watchdog 0040170 timer write(B) protect register D7 WRWD D6-0 - EWD write protection - 1 Write enabled 0 Write-protect - 0 - R/W - 0 when being read. Watchdog timer enable register D7-2 - D1 EWD D0 - - Watchdog timer enable - - 1 NMI enabled 0 NMI disabled - - 0 - - 0 when being read. R/W - 0 when being read. 0040171 (B) B-ap S1C33L03 FUNCTION PART EPSON B-APPENDIX-7 APPENDIX: I/O MAP Register name Address Bit Name Power control register D7 D6 CLKDT1 CLKDT0 System clock division ratio selection D5 D4-3 D2 D1 D0 PSCON - CLKCHG SOSC3 SOSC1 Prescaler On/Off control reserved 1 OSC3 CPU operating clock switch High-speed (OSC3) oscillation On/Off 1 On Low-speed (OSC1) oscillation On/Off 1 On 0040180 (B) Function Setting CLKDT[1:0] 1 1 1 0 0 1 0 0 1 On R/W 1 0 1 1 1 R/W - Writing 1 not allowed. R/W R/W R/W - 0 0 - R/W - 0 1 0 0 - 0 when being read. R/W R/W - Do not write 1. R/W 0 0 0 0 0 0 0 0 R/W D7-1 - D0 PSCDT0 reserved Prescaler clock selection Clock option register D7-4 D3 D2 D1 D0 - HLT2OP 8T1ON - PF1ON - HALT clock option OSC3-stabilize waiting function reserved OSC1 external output control CLGP7 CLGP6 CLGP5 CLGP4 CLGP3 CLGP2 CLGP1 CLGP0 Power control register protect flag Writing 10010110 (0x96) removes the write protection of the power control register (0x40180) and the clock option register (0x40190). Writing another value set the write protection. Power control 004019E protect register (B) B-APPENDIX-8 D7 D6 D5 D4 D3 D2 D1 D0 EPSON 1 OSC1 0 OSC3/PLL - 1 On 1 Off 0 Off 0 On - 1 On Remarks 0 0 Prescaler clock 0040181 select register (B) 0040190 (B) Init. R/W Division ratio 1/8 1/4 1/2 1/1 0 Off - 0 OSC1 0 Off 0 Off 0 Off S1C33L03 FUNCTION PART APPENDIX: I/O MAP A-1 Register name Address Bit Name Function Serial I/F Ch.0 transmit data register 00401E0 (B) D7 D6 D5 D4 D3 D2 D1 D0 TXD07 TXD06 TXD05 TXD04 TXD03 TXD02 TXD01 TXD00 Serial I/F Ch.0 transmit data TXD07(06) = MSB TXD00 = LSB 0x0 to 0xFF(0x7F) X X X X X X X X Serial I/F Ch.0 receive data register 00401E1 (B) D7 D6 D5 D4 D3 D2 D1 D0 RXD07 RXD06 RXD05 RXD04 RXD03 RXD02 RXD01 RXD00 Serial I/F Ch.0 receive data RXD07(06) = MSB RXD00 = LSB 0x0 to 0xFF(0x7F) X X X X X X X X R 7-bit asynchronous mode does not use RXD07 (fixed at 0). - - 0 0 0 0 1 0 - R R/W R/W R/W R R 0 when being read. 1 Enabled 0 Disabled 1 Enabled 0 Disabled 1 With parity 0 No parity 1 Odd 0 Even 1 2 bits 0 1 bit 1 #SCLK0 0 Internal clock SMD0[1:0] Transfer mode 1 1 8-bit asynchronous 1 0 7-bit asynchronous Clock sync. Slave 0 1 Clock sync. Master 0 0 0 0 X X X X X X R/W R/W R/W Valid only in R/W asynchronous mode. R/W R/W R/W - - X X X X X - 0 when being read. R/W R/W Valid only in R/W asynchronous mode. R/W Serial I/F Ch.0 00401E2 D7-6 - status register (B) D5 TEND0 D4 FER0 D3 PER0 D2 OER0 D1 TDBE0 D0 RDBF0 - Ch.0 transmit-completion flag Ch.0 flaming error flag Ch.0 parity error flag Ch.0 overrun error flag Ch.0 transmit data buffer empty Ch.0 receive data buffer full Serial I/F Ch.0 00401E3 control register (B) Ch.0 transmit enable Ch.0 receive enable Ch.0 parity enable Ch.0 parity mode selection Ch.0 stop bit selection Ch.0 input clock selection Ch.0 transfer mode selection Serial I/F Ch.0 IrDA register D7 D6 D5 D4 D3 D2 D1 D0 TXEN0 RXEN0 EPR0 PMD0 STPB0 SSCK0 SMD01 SMD00 00401E4 D7-5 - (B) D4 DIVMD0 D3 IRTL0 D2 IRRL0 D1 IRMD01 D0 IRMD00 - Ch.0 async. clock division ratio Ch.0 IrDA I/F output logic inversion Ch.0 IrDA I/F input logic inversion Ch.0 interface mode selection Setting 1 1 1 1 1 1 Transmitting Error Error Error Empty Buffer full 1 1/8 1 Inverted 1 Inverted IRMD0[1:0] 1 1 1 0 0 1 0 0 0 0 0 0 0 0 Init. R/W End Normal Normal Normal Buffer full Empty 0 1/16 0 Direct 0 Direct I/F mode reserved IrDA 1.0 reserved General I/F Remarks R/W 7-bit asynchronous mode does not use TXD07. Reset by writing 0. Reset by writing 0. Reset by writing 0. B-ap S1C33L03 FUNCTION PART EPSON B-APPENDIX-9 APPENDIX: I/O MAP Register name Address Bit Serial I/F Ch.1 transmit data register 00401E5 (B) D7 D6 D5 D4 D3 D2 D1 D0 TXD17 TXD16 TXD15 TXD14 TXD13 TXD12 TXD11 TXD10 Name Serial I/F Ch.1 transmit data TXD17(16) = MSB TXD10 = LSB Function 0x0 to 0xFF(0x7F) X X X X X X X X Serial I/F Ch.1 receive data register 00401E6 (B) D7 D6 D5 D4 D3 D2 D1 D0 RXD17 RXD16 RXD15 RXD14 RXD13 RXD12 RXD11 RXD10 Serial I/F Ch.1 receive data RXD17(16) = MSB RXD10 = LSB 0x0 to 0xFF(0x7F) X X X X X X X X R 7-bit asynchronous mode does not use RXD17 (fixed at 0). - - 0 0 0 0 1 0 - R R/W R/W R/W R R 0 when being read. 1 Enabled 0 Disabled 1 Enabled 0 Disabled 1 With parity 0 No parity 1 Odd 0 Even 1 2 bits 0 1 bit 1 #SCLK1 0 Internal clock SMD1[1:0] Transfer mode 1 1 8-bit asynchronous 1 0 7-bit asynchronous Clock sync. Slave 0 1 Clock sync. Master 0 0 0 0 X X X X X X R/W R/W R/W Valid only in R/W asynchronous mode. R/W R/W R/W - - X X X X X - 0 when being read. R/W R/W Valid only in R/W asynchronous mode. R/W Serial I/F Ch.1 00401E7 D7-6 - status register (B) D5 TEND1 D4 FER1 D3 PER1 D2 OER1 D1 TDBE1 D0 RDBF1 - Ch.1 transmit-completion flag Ch.1 flaming error flag Ch.1 parity error flag Ch.1 overrun error flag Ch.1 transmit data buffer empty Ch.1 receive data buffer full Serial I/F Ch.1 00401E8 control register (B) Ch.1 transmit enable Ch.1 receive enable Ch.1 parity enable Ch.1 parity mode selection Ch.1 stop bit selection Ch.1 input clock selection Ch.1 transfer mode selection D7 D6 D5 D4 D3 D2 D1 D0 TXEN1 RXEN1 EPR1 PMD1 STPB1 SSCK1 SMD11 SMD10 Setting 1 1 1 1 1 1 Transmitting Error Error Error Empty Buffer full 0 0 0 0 0 0 Init. R/W End Normal Normal Normal Buffer full Empty Serial I/F Ch.1 IrDA register 00401E9 D7-5 - (B) D4 DIVMD1 D3 IRTL1 D2 IRRL1 D1 IRMD11 D0 IRMD10 - Ch.1 async. clock division ratio Ch.1 IrDA I/F output logic inversion Ch.1 IrDA I/F input logic inversion Ch.1 interface mode selection Serial I/F Ch.2 transmit data register 00401F0 (B) D7 D6 D5 D4 D3 D2 D1 D0 TXD27 TXD26 TXD25 TXD24 TXD23 TXD22 TXD21 TXD20 Serial I/F Ch.2 transmit data TXD27(26) = MSB TXD20 = LSB 0x0 to 0xFF(0x7F) X X X X X X X X R/W Serial I/F Ch.2 receive data register 00401F1 (B) D7 D6 D5 D4 D3 D2 D1 D0 RXD27 RXD26 RXD25 RXD24 RXD23 RXD22 RXD21 RXD20 Serial I/F Ch.2 receive data RXD27(26) = MSB RXD20 = LSB 0x0 to 0xFF(0x7F) X X X X X X X X R D7-6 D5 D4 D3 D2 D1 D0 - TEND2 FER2 PER2 OER2 TDBE2 RDBF2 reserved Ch.2 transmit-completion flag Ch.2 flaming error flag Ch.2 parity error flag Ch.2 overrun error flag Ch.2 transmit data buffer empty Ch.2 receive data buffer full - - 0 0 0 0 1 0 - R R/W R/W R/W R R Serial I/F Ch.2 00401F2 status register (B) B-APPENDIX-10 EPSON 1 1/8 1 Inverted 1 Inverted IRMD1[1:0] 1 1 1 0 0 1 0 0 1 1 1 1 1 1 Transmitting Error Error Error Empty Buffer full 0 1/16 0 Direct 0 Direct I/F mode reserved IrDA 1.0 reserved General I/F 0 0 0 0 0 0 End Normal Normal Normal Buffer full Empty Remarks R/W 7-bit asynchronous mode does not use TXD17. Reset by writing 0. Reset by writing 0. Reset by writing 0. 0 when being read. Reset by writing 0. Reset by writing 0. Reset by writing 0. S1C33L03 FUNCTION PART APPENDIX: I/O MAP A-1 Register name Address Bit Name Function Serial I/F Ch.2 00401F3 control register (B) D7 D6 D5 D4 D3 D2 D1 D0 TXEN2 RXEN2 EPR2 PMD2 STPB2 SSCK2 SMD21 SMD20 Ch.2 transmit enable Ch.2 receive enable Ch.2 parity enable Ch.2 parity mode selection Ch.2 stop bit selection Ch.2 input clock selection Ch.2 transfer mode selection - DIVMD2 IRTL2 IRRL2 IRMD21 IRMD20 reserved Ch.2 async. clock division ratio Ch.2 IrDA I/F output logic inversion Ch.2 IrDA I/F input logic inversion Ch.2 interface mode selection Setting Init. R/W Remarks 1 Enabled 0 Disabled 1 Enabled 0 Disabled 1 With parity 0 No parity 1 Odd 0 Even 1 2 bits 0 1 bit 1 #SCLK2 0 Internal clock SMD2[1:0] Transfer mode 1 1 8-bit asynchronous 1 0 7-bit asynchronous Clock sync. Slave 0 1 Clock sync. Master 0 0 0 0 X X X X X X R/W R/W R/W Valid only in R/W asynchronous mode. R/W R/W R/W - - X X X X X - 0 when being read. R/W R/W Valid only in R/W asynchronous mode. R/W Serial I/F Ch.2 IrDA register 00401F4 (B) D7-5 D4 D3 D2 D1 D0 Serial I/F Ch.3 transmit data register 00401F5 (B) D7 D6 D5 D4 D3 D2 D1 D0 TXD37 TXD36 TXD35 TXD34 TXD33 TXD32 TXD31 TXD30 Serial I/F Ch.3 transmit data TXD37(36) = MSB TXD30 = LSB 0x0 to 0xFF(0x7F) X X X X X X X X R/W Serial I/F Ch.3 receive data register 00401F6 (B) D7 D6 D5 D4 D3 D2 D1 D0 RXD37 RXD36 RXD35 RXD34 RXD33 RXD32 RXD31 RXD30 Serial I/F Ch.3 receive data RXD37(36) = MSB RXD30 = LSB 0x0 to 0xFF(0x7F) X X X X X X X X R D7-6 D5 D4 D3 D2 D1 D0 - TEND3 FER3 PER3 OER3 TDBE3 RDBF3 reserved Ch.3 transmit-completion flag Ch.3 flaming error flag Ch.3 parity error flag Ch.3 overrun error flag Ch.3 transmit data buffer empty Ch.3 receive data buffer full - - 0 0 0 0 1 0 - R R/W R/W R/W R R D7 D6 D5 D4 D3 D2 D1 D0 TXEN3 RXEN3 EPR3 PMD3 STPB3 SSCK3 SMD31 SMD30 Ch.3 transmit enable Ch.3 receive enable Ch.3 parity enable Ch.3 parity mode selection Ch.3 stop bit selection Ch.3 input clock selection Ch.3 transfer mode selection 1 Enabled 0 Disabled 1 Enabled 0 Disabled 1 With parity 0 No parity 1 Odd 0 Even 1 2 bits 0 1 bit 1 #SCLK3 0 Internal clock SMD3[1:0] Transfer mode 1 1 8-bit asynchronous 1 0 7-bit asynchronous Clock sync. Slave 0 1 Clock sync. Master 0 0 0 0 X X X X X X R/W R/W R/W Valid only in R/W asynchronous mode. R/W R/W R/W D7-5 D4 D3 D2 D1 D0 - DIVMD3 IRTL3 IRRL3 IRMD31 IRMD30 reserved Ch.3 async. clock division ratio Ch.3 IrDA I/F output logic inversion Ch.3 IrDA I/F input logic inversion Ch.3 interface mode selection - - X X X X X - 0 when being read. R/W R/W Valid only in R/W asynchronous mode. R/W Serial I/F Ch.3 00401F7 status register (B) Serial I/F Ch.3 00401F8 control register (B) Serial I/F Ch.3 IrDA register 00401F9 (B) 1 1/8 1 Inverted 1 Inverted IRMD2[1:0] 1 1 1 0 0 1 0 0 1 1 1 1 1 1 0 1/16 0 Direct 0 Direct I/F mode reserved IrDA 1.0 reserved General I/F Transmitting Error Error Error Empty Buffer full 1 1/8 1 Inverted 1 Inverted IRMD3[1:0] 1 1 1 0 0 1 0 0 0 0 0 0 0 0 End Normal Normal Normal Buffer full Empty 0 1/16 0 Direct 0 Direct I/F mode reserved IrDA 1.0 reserved General I/F 0 when being read. Reset by writing 0. Reset by writing 0. Reset by writing 0. B-ap S1C33L03 FUNCTION PART EPSON B-APPENDIX-11 APPENDIX: I/O MAP Register name Address Bit A/D conversion 0040240 result (low(B) order) register D7 D6 D5 D4 D3 D2 D1 D0 Name ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 Function 0 0 0 0 0 0 0 0 R - 0x0 to 0x3FF (high-order 2 bits) - 0 0 - R - - 0 0 0 D7-2 - D1 ADD9 D0 ADD8 - A/D converted data (high-order 2 bits) ADD9 = MSB A/D trigger register D7-6 D5 D4 D3 - MS TS1 TS0 - A/D conversion mode selection A/D conversion trigger selection D2 D1 D0 CH2 CH1 CH0 A/D conversion channel status D7-6 D5 D4 D3 - CE2 CE1 CE0 - A/D converter end channel selection D2 D1 D0 CS2 CS1 CS0 A/D converter start channel selection - ADF ADE ADST OWE - Conversion-complete flag A/D enable A/D conversion control/status Overwrite error flag A/D channel register 0040243 (B) A/D enable register 0040244 (B) D7-4 D3 D2 D1 D0 A/D sampling register 0040245 (B) D7-2 - D1 ST1 D0 ST0 B-APPENDIX-12 Init. R/W 0x0 to 0x3FF (low-order 8 bits) A/D conversion 0040241 result (high(B) order) register 0040242 (B) Setting A/D converted data (low-order 8 bits) ADD0 = LSB - Input signal sampling time setup EPSON 1 Continuous TS[1:0] 1 1 1 0 0 1 0 0 CH[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 CE[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 CS[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 1 1 1 1 Completed Enabled Start/Run Error ST[1:0] 1 1 1 0 0 1 0 0 0 Normal Trigger #ADTRG pin 8-bit timer 0 16-bit timer 0 Software Channel AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 0 0 0 Remarks 0 when being read. - 0 when being read. R/W R/W R - End channel AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Start channel AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 - 0 0 0 - 0 when being read. R/W 0 0 0 R/W - - 0 0 0 0 - 0 when being read. R Reset when ADD is read. R/W R/W R/W Reset by writing 0. - 1 1 - 0 when being read. R/W Use with 9 clocks. 0 0 0 0 Run/Standby Disabled Stop Normal - Sampring time 9 clocks 7 clocks 5 clocks 3 clocks S1C33L03 FUNCTION PART APPENDIX: I/O MAP A-1 Register name Address Bit Port input 0/1 0040260 interrupt (B) priority register D7 D6 D5 D4 D3 D2 D1 D0 - PP1L2 PP1L1 PP1L0 - PP0L2 PP0L1 PP0L0 reserved Port input 1 interrupt level - 0 to 7 reserved Port input 0 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - PP3L2 PP3L1 PP3L0 - PP2L2 PP2L1 PP2L0 reserved Port input 3 interrupt level - 0 to 7 reserved Port input 2 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - PK1L2 PK1L1 PK1L0 - PK0L2 PK0L1 PK0L0 reserved Key input 1 interrupt level - 0 to 7 reserved Key input 0 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - PHSD1L2 PHSD1L1 PHSD1L0 - PHSD0L2 PHSD0L1 PHSD0L0 reserved High-speed DMA Ch.1 interrupt level - 0 to 7 reserved High-speed DMA Ch.0 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - PHSD3L2 PHSD3L1 PHSD3L0 - PHSD2L2 PHSD2L1 PHSD2L0 reserved High-speed DMA Ch.3 interrupt level - 0 to 7 reserved High-speed DMA Ch.2 interrupt level - 0 to 7 - PDM2 PDM1 PDM0 reserved IDMA interrupt level Port input 2/3 0040261 interrupt (B) priority register Key input 0040262 interrupt (B) priority register High-speed 0040263 DMA Ch.0/1 (B) interrupt priority register High-speed 0040264 DMA Ch.2/3 (B) interrupt priority register Name Function Setting - 0 when being read. R/W - X X X - X X X - 0 when being read. R/W - X X X - X X X - 0 when being read. R/W - X X X - X X X - 0 when being read. R/W - X X X - X X X - 0 when being read. R/W - 0 to 7 - X X X - 0 when being read. R/W - X X X - X X X - 0 when being read. R/W - X X X - X X X - 0 when being read. R/W - X X X - X X X - 0 when being read. R/W D7-3 D2 D1 D0 16-bit timer 0/1 0040266 interrupt (B) priority register D7 D6 D5 D4 D3 D2 D1 D0 - P16T12 P16T11 P16T10 - P16T02 P16T01 P16T00 reserved 16-bit timer 1 interrupt level - 0 to 7 reserved 16-bit timer 0 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - P16T32 P16T31 P16T30 - P16T22 P16T21 P16T20 reserved 16-bit timer 3 interrupt level - 0 to 7 reserved 16-bit timer 2 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - P16T52 P16T51 P16T50 - P16T42 P16T41 P16T40 reserved 16-bit timer 5 interrupt level - 0 to 7 reserved 16-bit timer 4 interrupt level - 0 to 7 16-bit timer 4/5 0040268 interrupt (B) priority register Remarks - X X X - X X X IDMA interrupt 0040265 priority register (B) 16-bit timer 2/3 0040267 interrupt (B) priority register Init. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W B-ap S1C33L03 FUNCTION PART EPSON B-APPENDIX-13 APPENDIX: I/O MAP Register name Address Bit 8-bit timer, 0040269 serial I/F Ch.0 (B) interrupt priority register D7 D6 D5 D4 D3 D2 D1 D0 - PSIO02 PSIO01 PSIO00 - P8TM2 P8TM1 P8TM0 reserved Serial interface Ch.0 interrupt level - 0 to 7 reserved 8-bit timer 0-3 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - PAD2 PAD1 PAD0 - PSIO12 PSIO11 PSIO10 reserved A/D converter interrupt level - 0 to 7 reserved Serial interface Ch.1 interrupt level - 0 to 7 Clock timer 004026B D7-3 - interrupt (B) D2 PCTM2 priority register D1 PCTM1 D0 PCTM0 reserved Clock timer interrupt level Port input 4/5 004026C interrupt (B) priority register Serial I/F Ch.1, 004026A A/D interrupt (B) priority register Port input 6/7 004026D interrupt (B) priority register B-APPENDIX-14 Name Function Setting Remarks - X X X - X X X - 0 when being read. R/W - X X X - X X X - 0 when being read. R/W - 0 to 7 - X X X - Writing 1 not allowed. R/W - X X X - X X X - 0 when being read. R/W - X X X - X X X - 0 when being read. R/W D7 D6 D5 D4 D3 D2 D1 D0 - PP5L2 PP5L1 PP5L0 - PP4L2 PP4L1 PP4L0 reserved Port input 5 interrupt level - 0 to 7 reserved Port input 4 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - PP7L2 PP7L1 PP7L0 - PP6L2 PP6L1 PP6L0 reserved Port input 7 interrupt level - 0 to 7 reserved Port input 6 interrupt level - 0 to 7 EPSON Init. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W S1C33L03 FUNCTION PART APPENDIX: I/O MAP A-1 Register name Address Bit Name Function Key input, 0040270 port input 0-3 (B) interrupt enable register D7-6 D5 D4 D3 D2 D1 D0 - EK1 EK0 EP3 EP2 EP1 EP0 reserved Key input 1 Key input 0 Port input 3 Port input 2 Port input 1 Port input 0 DMA interrupt 0040271 enable register (B) D7-5 D4 D3 D2 D1 D0 - EIDMA EHDM3 EHDM2 EHDM1 EHDM0 reserved IDMA High-speed DMA Ch.3 High-speed DMA Ch.2 High-speed DMA Ch.1 High-speed DMA Ch.0 16-bit timer 0/1 0040272 interrupt (B) enable register D7 D6 D5-4 D3 D2 D1-0 E16TC1 E16TU1 - E16TC0 E16TU0 - D7 D6 D5-4 D3 D2 D1-0 Setting - 1 Enabled 0 Disabled - 1 Enabled 0 Disabled 16-bit timer 1 comparison A 16-bit timer 1 comparison B reserved 16-bit timer 0 comparison A 16-bit timer 0 comparison B reserved 1 Enabled 0 Disabled E16TC3 E16TU3 - E16TC2 E16TU2 - 16-bit timer 3 comparison A 16-bit timer 3 comparison B reserved 16-bit timer 2 comparison A 16-bit timer 2 comparison B reserved 1 Enabled D7 D6 D5-4 D3 D2 D1-0 E16TC5 E16TU5 - E16TC4 E16TU4 - 16-bit timer 5 comparison A 16-bit timer 5 comparison B reserved 16-bit timer 4 comparison A 16-bit timer 4 comparison B reserved 1 Enabled 8-bit timer 0040275 interrupt (B) enable register D7-4 D3 D2 D1 D0 - E8TU3 E8TU2 E8TU1 E8TU0 reserved 8-bit timer 3 underflow 8-bit timer 2 underflow 8-bit timer 1 underflow 8-bit timer 0 underflow Serial I/F 0040276 interrupt (B) enable register D7-6 D5 D4 D3 D2 D1 D0 - ESTX1 ESRX1 ESERR1 ESTX0 ESRX0 ESERR0 reserved SIF Ch.1 transmit buffer empty SIF Ch.1 receive buffer full SIF Ch.1 receive error SIF Ch.0 transmit buffer empty SIF Ch.0 receive buffer full SIF Ch.0 receive error Port input 4-7, 0040277 clock timer, (B) A/D interrupt enable register D7-6 D5 D4 D3 D2 D1 D0 - EP7 EP6 EP5 EP4 ECTM EADE reserved Port input 7 Port input 6 Port input 5 Port input 4 Clock timer A/D converter 16-bit timer 2/3 0040273 interrupt (B) enable register 16-bit timer 4/5 0040274 interrupt (B) enable register - 1 Enabled 0 Disabled - 0 Disabled - 1 Enabled 0 Disabled - 0 Disabled - 1 Enabled 0 Disabled - - 1 Enabled 0 Disabled - 1 Enabled 0 Disabled - 1 Enabled 0 Disabled Init. R/W Remarks - 0 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W R/W - 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W 0 0 - 0 0 - R/W R/W - 0 when being read. R/W R/W - 0 when being read. 0 0 - 0 0 - R/W R/W - 0 when being read. R/W R/W - 0 when being read. 0 0 - 0 0 - R/W R/W - 0 when being read. R/W R/W - 0 when being read. - 0 0 0 0 - 0 when being read. R/W R/W R/W R/W - 0 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W R/W - 0 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W R/W B-ap S1C33L03 FUNCTION PART EPSON B-APPENDIX-15 APPENDIX: I/O MAP Register name Address Bit Key input, 0040280 port input 0-3 (B) interrupt factor flag register D7-6 D5 D4 D3 D2 D1 D0 - FK1 FK0 FP3 FP2 FP1 FP0 Name reserved Key input 1 Key input 0 Port input 3 Port input 2 Port input 1 Port input 0 Function DMA interrupt factor flag register 0040281 (B) D7-5 D4 D3 D2 D1 D0 - FIDMA FHDM3 FHDM2 FHDM1 FHDM0 reserved IDMA High-speed DMA Ch.3 High-speed DMA Ch.2 High-speed DMA Ch.1 High-speed DMA Ch.0 16-bit timer 0/1 0040282 interrupt factor (B) flag register D7 D6 D5-4 D3 D2 D1-0 F16TC1 F16TU1 - F16TC0 F16TU0 - D7 D6 D5-4 D3 D2 D1-0 Setting - 1 Factor is generated 0 No factor is generated - 1 Factor is generated 0 No factor is generated 16-bit timer 1 comparison A 16-bit timer 1 comparison B reserved 16-bit timer 0 comparison A 16-bit timer 0 comparison B reserved 1 Factor is generated 0 No factor is generated F16TC3 F16TU3 - F16TC2 F16TU2 - 16-bit timer 3 comparison A 16-bit timer 3 comparison B reserved 16-bit timer 2 comparison A 16-bit timer 2 comparison B reserved 1 Factor is generated D7 D6 D5-4 D3 D2 D1-0 F16TC5 F16TU5 - F16TC4 F16TU4 - 16-bit timer 5 comparison A 16-bit timer 5 comparison B reserved 16-bit timer 4 comparison A 16-bit timer 4 comparison B reserved 1 Factor is generated 8-bit timer 0040285 interrupt factor (B) flag register D7-4 D3 D2 D1 D0 - F8TU3 F8TU2 F8TU1 F8TU0 reserved 8-bit timer 3 underflow 8-bit timer 2 underflow 8-bit timer 1 underflow 8-bit timer 0 underflow Serial I/F 0040286 interrupt factor (B) flag register D7-6 D5 D4 D3 D2 D1 D0 - FSTX1 FSRX1 FSERR1 FSTX0 FSRX0 FSERR0 reserved SIF Ch.1 transmit buffer empty SIF Ch.1 receive buffer full SIF Ch.1 receive error SIF Ch.0 transmit buffer empty SIF Ch.0 receive buffer full SIF Ch.0 receive error Port input 4-7, 0040287 clock timer, A/D (B) interrupt factor flag register D7-6 D5 D4 D3 D2 D1 D0 - FP7 FP6 FP5 FP4 FCTM FADE reserved Port input 7 Port input 6 Port input 5 Port input 4 Clock timer A/D converter 16-bit timer 2/3 0040283 interrupt factor (B) flag register 16-bit timer 4/5 0040284 interrupt factor (B) flag register B-APPENDIX-16 - 1 Factor is generated 0 No factor is generated - 0 No factor is generated - 1 Factor is generated 0 No factor is generated - 0 No factor is generated - 1 Factor is generated 0 No factor is generated - - 1 Factor is generated 0 No factor is generated - 1 Factor is generated 0 No factor is generated - 1 Factor is generated EPSON 0 No factor is generated Init. R/W Remarks - X X X X X X - 0 when being read. R/W R/W R/W R/W R/W R/W - X X X X X - 0 when being read. R/W R/W R/W R/W R/W X X - X X - R/W R/W - 0 when being read. R/W R/W - 0 when being read. X X - X X - R/W R/W - 0 when being read. R/W R/W - 0 when being read. X X - X X - R/W R/W - 0 when being read. R/W R/W - 0 when being read. - X X X X - 0 when being read. R/W R/W R/W R/W - X X X X X X - 0 when being read. R/W R/W R/W R/W R/W R/W - X X X X X X - 0 when being read. R/W R/W R/W R/W R/W R/W S1C33L03 FUNCTION PART APPENDIX: I/O MAP A-1 Register name Address Bit Name Port input 0-3, high-speed DMA Ch. 0/1, 16-bit timer 0 IDMA request register 0040290 (B) D7 D6 D5 D4 D3 D2 D1 D0 R16TC0 R16TU0 RHDM1 RHDM0 RP3 RP2 RP1 RP0 16-bit timer 0 comparison A 16-bit timer 0 comparison B High-speed DMA Ch.1 High-speed DMA Ch.0 Port input 3 Port input 2 Port input 1 Port input 0 1 IDMA request 0 Interrupt request 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 16-bit timer 1-4 0040291 IDMA request (B) register D7 D6 D5 D4 D3 D2 D1 D0 R16TC4 R16TU4 R16TC3 R16TU3 R16TC2 R16TU2 R16TC1 R16TU1 16-bit timer 4 comparison A 16-bit timer 4 comparison B 16-bit timer 3 comparison A 16-bit timer 3 comparison B 16-bit timer 2 comparison A 16-bit timer 2 comparison B 16-bit timer 1 comparison A 16-bit timer 1 comparison B 1 IDMA request 0 Interrupt request 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA request register 0040292 (B) D7 D6 D5 D4 D3 D2 D1 D0 RSTX0 RSRX0 R8TU3 R8TU2 R8TU1 R8TU0 R16TC5 R16TU5 SIF Ch.0 transmit buffer empty SIF Ch.0 receive buffer full 8-bit timer 3 underflow 8-bit timer 2 underflow 8-bit timer 1 underflow 8-bit timer 0 underflow 16-bit timer 5 comparison A 16-bit timer 5 comparison B 1 IDMA request 0 Interrupt request 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Serial I/F Ch.1, A/D, port input 4-7 IDMA request register 0040293 (B) D7 D6 D5 D4 D3 D2 D1 D0 RP7 RP6 RP5 RP4 - RADE RSTX1 RSRX1 Port input 7 Port input 6 Port input 5 Port input 4 reserved A/D converter SIF Ch.1 transmit buffer empty SIF Ch.1 receive buffer full 1 IDMA request 0 Interrupt request 1 IDMA request 0 Interrupt request 0 0 0 0 - 0 0 0 R/W R/W R/W R/W - 0 when being read. R/W R/W R/W 0040294 (B) D7 D6 D5 D4 D3 D2 D1 D0 DE16TC0 DE16TU0 DEHDM1 DEHDM0 DEP3 DEP2 DEP1 DEP0 16-bit timer 0 comparison A 16-bit timer 0 comparison B High-speed DMA Ch.1 High-speed DMA Ch.0 Port input 3 Port input 2 Port input 1 Port input 0 1 IDMA enabled 0 IDMA disabled 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 16-bit timer 1-4 0040295 IDMA enable (B) register D7 D6 D5 D4 D3 D2 D1 D0 DE16TC4 DE16TU4 DE16TC3 DE16TU3 DE16TC2 DE16TU2 DE16TC1 DE16TU1 16-bit timer 4 comparison A 16-bit timer 4 comparison B 16-bit timer 3 comparison A 16-bit timer 3 comparison B 16-bit timer 2 comparison A 16-bit timer 2 comparison B 16-bit timer 1 comparison A 16-bit timer 1 comparison B 1 IDMA enabled 0 IDMA disabled 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA enable register 0040296 (B) D7 D6 D5 D4 D3 D2 D1 D0 DESTX0 DESRX0 DE8TU3 DE8TU2 DE8TU1 DE8TU0 DE16TC5 DE16TU5 SIF Ch.0 transmit buffer empty SIF Ch.0 receive buffer full 8-bit timer 3 underflow 8-bit timer 2 underflow 8-bit timer 1 underflow 8-bit timer 0 underflow 16-bit timer 5 comparison A 16-bit timer 5 comparison B 1 IDMA enabled 0 IDMA disabled 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Serial I/F Ch.1, A/D, port input 4-7 IDMA enable register 0040297 (B) D7 D6 D5 D4 D3 D2 D1 D0 DEP7 DEP6 DEP5 DEP4 - DEADE DESTX1 DESRX1 Port input 7 Port input 6 Port input 5 Port input 4 reserved A/D converter SIF Ch.1 transmit buffer empty SIF Ch.1 receive buffer full 1 IDMA enabled 0 IDMA disabled 0 0 0 0 - 0 0 0 R/W R/W R/W R/W - 0 when being read. R/W R/W R/W Port input 0-3, high-speed DMA Ch. 0/1, 16-bit timer 0 IDMA enable register Function Setting - - 1 IDMA enabled 0 IDMA disabled Init. R/W Remarks B-ap S1C33L03 FUNCTION PART EPSON B-APPENDIX-17 APPENDIX: I/O MAP Register name Address Bit Name High-speed DMA Ch.0/1 trigger set-up register D7 D6 D5 D4 HSD1S3 HSD1S2 HSD1S1 HSD1S0 High-speed DMA Ch.1 trigger set-up D3 D2 D1 D0 HSD0S3 HSD0S2 HSD0S1 HSD0S0 High-speed DMA Ch.0 trigger set-up D7 D6 D5 D4 HSD3S3 HSD3S2 HSD3S1 HSD3S0 High-speed DMA Ch.3 trigger set-up D3 D2 D1 D0 HSD2S3 HSD2S2 HSD2S1 HSD2S0 High-speed DMA Ch.2 trigger set-up High-speed DMA Ch.2/3 trigger set-up register 0040298 (B) 0040299 (B) High-speed 004029A D7-4 - DMA software (B) D3 HST3 trigger register D2 HST2 D1 HST1 D0 HST0 Flag set/reset method select register 004029F (B) B-APPENDIX-18 Function reserved HSDMA Ch.3 software trigger HSDMA Ch.2 software trigger HSDMA Ch.1 software trigger HSDMA Ch.0 software trigger Setting Software trigger K51 input (falling edge) K51 input (rising edge) Port 1 input Port 5 input 8-bit timer Ch.1 underflow 16-bit timer Ch.1 compare B 16-bit timer Ch.1 compare A 16-bit timer Ch.5 compare B 16-bit timer Ch.5 compare A SI/F Ch.1 Rx buffer full SI/F Ch.1 Tx buffer empty A/D conversion completion Software trigger K50 input (falling edge) K50 input (rising edge) Port 0 input Port 4 input 8-bit timer Ch.0 underflow 16-bit timer Ch.0 compare B 16-bit timer Ch.0 compare A 16-bit timer Ch.4 compare B 16-bit timer Ch.4 compare A SI/F Ch.0 Rx buffer full SI/F Ch.0 Tx buffer empty A/D conversion completion 0 0 0 0 R/W 0 0 0 0 R/W 0 1 2 3 4 5 6 7 8 9 A B C 0 1 2 3 4 5 6 7 8 9 A B C Software trigger K54 input (falling edge) K54 input (rising edge) Port 3 input Port 7 input 8-bit timer Ch.3 underflow 16-bit timer Ch.3 compare B 16-bit timer Ch.3 compare A 16-bit timer Ch.5 compare B 16-bit timer Ch.5 compare A SI/F Ch.1 Rx buffer full SI/F Ch.1 Tx buffer empty A/D conversion completion Software trigger K53 input (falling edge) K53 input (rising edge) Port 2 input Port 6 input 8-bit timer Ch.2 underflow 16-bit timer Ch.2 compare B 16-bit timer Ch.2 compare A 16-bit timer Ch.4 compare B 16-bit timer Ch.4 compare A SI/F Ch.0 Rx buffer full SI/F Ch.0 Tx buffer empty A/D conversion completion 0 0 0 0 R/W 0 0 0 0 R/W - 0 0 0 0 - W W W W - 1 - R/W 1 R/W 1 R/W - 1 Trigger 0 Invalid D7-3 - reserved - 0 RD/WR D2 DENONLY IDMA enable register set method 1 Set only selection D1 IDMAONLY IDMA request register set method 1 Set only 0 RD/WR selection D0 RSTONLY Interrupt factor flag reset method 1 Reset only 0 RD/WR selection EPSON Init. R/W 0 1 2 3 4 5 6 7 8 9 A B C 0 1 2 3 4 5 6 7 8 9 A B C Remarks 0 when being read. S1C33L03 FUNCTION PART APPENDIX: I/O MAP A-1 Register name Address Bit Name Function K5 function select register 00402C0 D7-5 - (B) D4 CFK54 D3 CFK53 D2 CFK52 D1 CFK51 D0 CFK50 reserved K54 function selection K53 function selection K52 function selection K51 function selection K50 function selection K5 input port data register 00402C1 D7-5 - (B) D4 K54D D3 K53D D2 K52D D1 K51D D0 K50D reserved K54 input port data K53 input port data K52 input port data K51 input port data K50 input port data K6 function select register 00402C3 (B) D7 D6 D5 D4 D3 D2 D1 D0 CFK67 CFK66 CFK65 CFK64 CFK63 CFK62 CFK61 CFK60 K6 input port data register 00402C4 (B) D7 D6 D5 D4 D3 D2 D1 D0 K67D K66D K65D K64D K63D K62D K61D K60D Setting Init. R/W - 1 1 1 1 1 #DMAREQ3 #DMAREQ2 #ADTRG #DMAREQ1 #DMAREQ0 0 0 0 0 0 K54 K53 K52 K51 K50 - - 0 when being read. R/W R/W R/W R/W R/W - - - - - - - R R R R R K67 K66 K65 K64 K63 K62 K61 K60 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 Low - - - - - - - - R R R R R R R R 1 High 0 Low K67 function selection K66 function selection K65 function selection K64 function selection K63 function selection K62 function selection K61 function selection K60 function selection 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 K67 input port data K66 input port data K65 input port data K64 input port data K63 input port data K62 input port data K61 input port data K60 input port data 1 High AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 - 0 0 0 0 0 Remarks 0 when being read. B-ap S1C33L03 FUNCTION PART EPSON B-APPENDIX-19 APPENDIX: I/O MAP Register name Address Bit Interrupt factor 00402C5 FP function switching register D7 D6 T8CH5S0 SIO3TS0 8-bit timer 5 underflow SIO Ch.3 transmit buffer empty D5 D4 T8CH4S0 SIO3RS0 8-bit timer 4 underflow SIO Ch.3 receive buffer full D3 SIO2TS0 SIO Ch.2 transmit buffer empty D2 SIO3ES0 SIO Ch.3 receive error D1 SIO2RS0 SIO Ch.2 receive buffer full D0 SIO2ES0 SIO Ch.2 receive error D7 D6 D5 D4 D3 D2 D1 D0 SPT31 SPT30 SPT21 SPT20 SPT11 SPT10 SPT01 SPT00 FPT3 interrupt input port selection D7 D6 D5 D4 D3 D2 D1 D0 SPT71 SPT70 SPT61 SPT60 SPT51 SPT50 SPT41 SPT40 FPT7 interrupt input port selection Port input 00402C6 interrupt select (B) register 1 Port input 00402C7 interrupt select (B) register 2 Name Function FPT2 interrupt input port selection FPT1 interrupt input port selection FPT0 interrupt input port selection FPT6 interrupt input port selection FPT5 interrupt input port selection FPT4 interrupt input port selection Setting 1 T8 Ch.5 UF 1 SIO Ch.3 TXD Emp. 1 T8 Ch.4 UF 1 SIO Ch.3 RXD Full 1 SIO Ch.2 TXD Emp. 1 SIO Ch.3 RXD Err. 1 SIO Ch.2 RXD Full 1 SIO Ch.2 RXD Err. Init. R/W 0 FP7 0 FP6 0 0 R/W R/W 0 FP5 0 FP4 0 0 R/W R/W 0 FP3 0 R/W 0 FP2 0 R/W 0 FP1 0 R/W 0 FP0 0 R/W 11 P23 11 P22 11 P21 11 P20 10 P03 10 P02 10 P01 10 P00 01 K53 01 K52 01 K51 01 K50 00 K63 00 K62 00 K61 00 K60 0 0 0 0 0 0 0 0 R/W 11 P27 11 P26 11 P25 11 P24 10 P07 10 P06 10 P05 10 P04 01 P33 01 P32 01 P31 01 K54 00 K67 00 K66 00 K65 00 K64 0 0 0 0 0 0 0 0 R/W Low level or Falling edge 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Port input interrupt input polarity select register 00402C8 (B) D7 D6 D5 D4 D3 D2 D1 D0 SPPT7 SPPT6 SPPT5 SPPT4 SPPT3 SPPT2 SPPT1 SPPT0 FPT7 input polarity selection FPT6 input polarity selection FPT5 input polarity selection FPT4 input polarity selection FPT3 input polarity selection FPT2 input polarity selection FPT1 input polarity selection FPT0 input polarity selection 1 High level 0 or Rising edge Port input interrupt edge/level select register 00402C9 (B) D7 D6 D5 D4 D3 D2 D1 D0 SEPT7 SEPT6 SEPT5 SEPT4 SEPT3 SEPT2 SEPT1 SEPT0 FPT7 edge/level selection FPT6 edge/level selection FPT5 edge/level selection FPT4 edge/level selection FPT3 edge/level selection FPT2 edge/level selection FPT1 edge/level selection FPT0 edge/level selection 1 Edge 0 Level Remarks R/W R/W R/W R/W R/W R/W Key input 00402CA D7-4 - interrupt select (B) D3 SPPK11 register D2 SPPK10 D1 SPPK01 D0 SPPK00 reserved FPK1 interrupt input port selection - 11 10 01 00 P2[7:4] P0[7:4] K6[7:4] K6[3:0] FPK0 interrupt input port selection 11 10 01 00 P2[4:0] P0[4:0] K6[4:0] K5[4:0] - 0 0 0 0 - 0 when being read. R/W Interrupt factor 00402CB TM16 function switching register 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W B-APPENDIX-20 D7 T8CH5S1 8-bit timer 5 underflow D6 T8CH4S1 8-bit timer 4 underflow D5 SIO3ES1 SIO Ch.3 receive error D4 SIO2ES1 SIO Ch.2 receive error D3 SIO3TS1 SIO Ch.3 transmit buffer empty D2 SIO3RS1 SIO Ch.3 receive buffer full D1 SIO2TS1 SIO Ch.2 transmit buffer empty D0 SIO2RS1 SIO Ch.2 receive buffer full EPSON 1 T8 Ch.5 UF 0 TM16 Ch.2 comp.A 1 T8 Ch.4 UF 0 TM16 Ch.2 comp.B 1 SIO Ch.3 0 TM16 Ch.3 RXD Err. comp.A 1 SIO Ch.2 0 TM16 Ch.3 RXD Err. comp.B 1 SIO Ch.3 0 TM16 Ch.4 TXD Emp. comp.A 1 SIO Ch.3 0 TM16 Ch.4 RXD Full comp.B 1 SIO Ch.2 0 TM16 Ch.5 TXD Emp. comp.A 1 SIO Ch.2 0 TM16 Ch.5 RXD Full comp.B R/W S1C33L03 FUNCTION PART APPENDIX: I/O MAP A-1 Register name Address Bit Name Function Key input interrupt (FPK0) input comparison register 00402CC D7-5 - (B) D4 SCPK04 D3 SCPK03 D2 SCPK02 D1 SCPK01 D0 SCPK00 reserved FPK04 input comparison FPK03 input comparison FPK02 input comparison FPK01 input comparison FPK00 input comparison Key input interrupt (FPK1) input comparison register 00402CD D7-4 - (B) D3 SCPK13 D2 SCPK12 D1 SCPK11 D0 SCPK10 reserved FPK13 input comparison FPK12 input comparison FPK11 input comparison FPK10 input comparison Key input interrupt (FPK0) input mask register 00402CE D7-5 - (B) D4 SMPK04 D3 SMPK03 D2 SMPK02 D1 SMPK01 D0 SMPK00 reserved FPK04 input mask FPK03 input mask FPK02 input mask FPK01 input mask FPK00 input mask Key input interrupt (FPK1) input mask register 00402CF D7-4 - (B) D3 SMPK13 D2 SMPK12 D1 SMPK11 D0 SMPK10 reserved FPK13 input mask FPK12 input mask FPK11 input mask FPK10 input mask P0 function select register 00402D0 (B) D7 D6 D5 D4 D3 D2 D1 D0 CFP07 CFP06 CFP05 CFP04 CFP03 CFP02 CFP01 CFP00 P0 I/O port data 00402D1 register (B) D7 D6 D5 D4 D3 D2 D1 D0 P0 I/O control register 00402D2 (B) P1 function select register 00402D4 (B) P1 I/O port data 00402D5 register (B) Setting Init. R/W - 1 High - 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W - 0 0 0 0 - 0 when being read. R/W R/W R/W R/W - 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W - 0 0 0 0 - 0 when being read. R/W R/W R/W R/W P07 P06 P05 P04 P03 P02 P01 P00 0 0 0 0 0 0 0 0 R/W Extended functions R/W (0x402DF) R/W R/W R/W R/W R/W R/W 0 Low - 1 High 0 Low - 1 Interrupt enabled Remarks 0 Interrupt disabled - 1 Interrupt enabled 0 Interrupt disabled P07 function selection P06 function selection P05 function selection P04 function selection P03 function selection P02 function selection P01 function selection P00 function selection 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 P07D P06D P05D P04D P03D P02D P01D P00D P07 I/O port data P06 I/O port data P05 I/O port data P04 I/O port data P03 I/O port data P02 I/O port data P01 I/O port data P00 I/O port data 1 High 0 Low 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W D7 D6 D5 D4 D3 D2 D1 D0 IOC07 IOC06 IOC05 IOC04 IOC03 IOC02 IOC01 IOC00 P07 I/O control P06 I/O control P05 I/O control P04 I/O control P03 I/O control P02 I/O control P01 I/O control P00 I/O control 1 Output 0 Input 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W D7 D6 - CFP16 reserved P16 function selection - 0 - 0 when being read. R/W D5 CFP15 P15 function selection 0 R/W D4 CFP14 P14 function selection - 1 EXCL5 0 P16 #DMAEND1 1 EXCL4 0 P15 #DMAEND0 1 FOSC1 0 P14 0 D3 CFP13 P13 function selection 0 P13 0 D2 CFP12 P12 function selection 0 P12 0 R/W D1 CFP11 P11 function selection 0 P11 0 R/W D0 CFP10 P10 function selection 1 EXCL3 T8UF3 1 EXCL2 T8UF2 1 EXCL1 T8UF1 1 EXCL0 T8UF0 R/W Extended functions (0x402DF) R/W 0 P10 0 R/W D7 D6 D5 D4 D3 D2 D1 D0 - P16D P15D P14D P13D P12D P11D P10D reserved P16 I/O port data P15 I/O port data P14 I/O port data P13 I/O port data P12 I/O port data P11 I/O port data P10 I/O port data - 0 0 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W R/W R/W #SRDY1 #SCLK1 SOUT1 SIN1 #SRDY0 #SCLK0 SOUT0 SIN0 - 1 High 0 Low This register indicates the values of the I/O control signals of the ports when it is read. (See detailed explanation.) B-ap S1C33L03 FUNCTION PART EPSON B-APPENDIX-21 APPENDIX: I/O MAP Register name Address Bit P1 I/O control register 00402D6 (B) D7 D6 D5 D4 D3 D2 D1 D0 Port SIO function extension register 00402D7 D7-4 - D3 SSRDY3 reserved Serial I/F Ch.3 SRDY selection 1 #SRDY3 D2 SSCLK3 Serial I/F Ch.3 SCLK selection 1 #SCLK3 D1 SSOUT3 Serial I/F Ch.3 SOUT selection 1 SOUT3 D0 SSIN3 Serial I/F Ch.3 SIN selection 1 SIN3 00402D8 (B) D7 D6 D5 D4 D3 D2 D1 D0 CFP27 CFP26 CFP25 CFP24 CFP23 CFP22 CFP21 CFP20 P27 function selection P26 function selection P25 function selection P24 function selection P23 function selection P22 function selection P21 function selection P20 function selection 1 1 1 1 1 1 1 1 P2 I/O port data 00402D9 register (B) D7 D6 D5 D4 D3 D2 D1 D0 P27D P26D P25D P24D P23D P22D P21D P20D P27 I/O port data P26 I/O port data P25 I/O port data P24 I/O port data P23 I/O port data P22 I/O port data P21 I/O port data P20 I/O port data P2 I/O control register 00402DA (B) D7 D6 D5 D4 D3 D2 D1 D0 IOC27 IOC26 IOC25 IOC24 IOC23 IOC22 IOC21 IOC20 P27 I/O control P26 I/O control P25 I/O control P24 I/O control P23 I/O control P22 I/O control P21 I/O control P20 I/O control Port SIO function extension register 00402DB D7-4 D3 D2 D1 D0 - SSRDY2 SSCLK2 SSOUT2 SSIN2 reserved Serial I/F Ch.2 SRDY selection Serial I/F Ch.2 SCLK selection Serial I/F Ch.2 SOUT selection Serial I/F Ch.2 SIN selection P2 function select register Name - IOC16 IOC15 IOC14 IOC13 IOC12 IOC11 IOC10 P3 function 00402DC D7-6 - select register (B) D5 CFP35 D4 CFP34 D3 D2 D1 D0 CFP33 CFP32 CFP31 CFP30 Function reserved P16 I/O control P15 I/O control P14 I/O control P13 I/O control P12 I/O control P11 I/O control P10 I/O control P3 I/O control register reserved P35 I/O control P34 I/O control P33 I/O control P32 I/O control P31 I/O control P30 I/O control 00402DE D7-6 - (B) D5 IOC35 D4 IOC34 D3 IOC33 D2 IOC32 D1 IOC31 D0 IOC30 B-APPENDIX-22 - R/W R/W R/W R/W R/W R/W R/W - 0 - R/W 0 R/W 0 R/W 0 R/W P27 P26 P25 P24 P23 P22 P21 P20 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W Ext. func.(0x402DF) R/W 1 High 0 Low 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 1 Output 0 Input 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W P24/TM2 P25/TM3 P26/TM4 P27/TM5 - 0 0 0 0 - R/W R/W R/W R/W P35 P34 - 0 0 - 0 when being read. R/W R/W P33 P32 P31 P30 0 0 0 0 R/W R/W R/W Ext. func.(0x402DF) R/W - 0 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W R/W - 0 0 0 0 0 0 - R/W R/W R/W R/W R/W R/W 0 Input - 0 P32/ #DMAACK0 0 P15/EXCL4/ #DMAEND0 0 P16/EXCL5/ #DMAEND1 0 P33/ #DMAACK1 TM5 TM4 TM3 TM2 TM1 TM0 #DWE #DRD 0 0 0 0 0 0 0 0 - 1 1 1 1 #SRDY2 #SCLK2 SOUT2 SIN2 0 0 0 0 - 1 #BUSACK 0 1 #BUSREQ 0 #CE6 1 #DMAACK1 0 1 #DMAACK0 0 1 #BUSGET 0 1 #WAIT 0 #CE4/#CE5 - 1 High 0 Low - 1 Output EPSON Remarks - 0 0 0 0 0 0 0 1 Output P33 function selection P32 function selection P31 function selection P30 function selection reserved P35 I/O port data P34 I/O port data P33 I/O port data P32 I/O port data P31 I/O port data P30 I/O port data Init. R/W - reserved P35 function selection P34 function selection P3 I/O port data 00402DD D7-6 - register (B) D5 P35D D4 P34D D3 P33D D2 P32D D1 P31D D0 P30D Setting 0 Input 0 when being read. This register indicates the values of the I/O control signals of the ports when it is read. (See detailed explanation.) This register indicates the values of the I/O control signals of the ports when it is read. (See detailed explanation.) 0 when being read. This register indicates the values of the I/O control signals of the ports when it is read. (See detailed explanation.) S1C33L03 FUNCTION PART APPENDIX: I/O MAP A-1 Register name Address Bit Port function extension register D7 D6 D5 D4 D3 D2 D1 CFEX7 CFEX6 CFEX5 CFEX4 CFEX3 CFEX2 CFEX1 P07 port extended function P06 port extended function P05 port extended function P04 port extended function P31 port extended function P21 port extended function P10, P11, P13 port extended function D0 CFEX0 P12, P14 port extended function DF DE DD DC - A18SZ A18DF1 A18DF0 DB DA D9 D8 - A18WT2 A18WT1 A18WT0 D7 D6 D5 D4 - A16SZ A16DF1 A16DF0 D3 D2 D1 D0 - A16WT2 A16WT1 A16WT0 DF-9 D8 D7 D6 D5 D4 D3 D2 D1 D0 00402DF (B) Areas 18-15 0048120 set-up register (HW) Areas 14-13 0048122 set-up register (HW) Name Function Setting 1 1 1 1 1 1 1 #DMAEND3 #DMAACK3 #DMAEND2 #DMAACK2 #GARD #GAAS DST0 DST1 DPC0 1 DST2 DCLK 0 0 0 0 0 0 0 P07, etc. P06, etc. P05, etc. P04, etc. P31, etc. P21, etc. P10, etc. P11, etc. P13, etc. 0 P12, etc. P14, etc. Init. R/W Remarks 0 0 0 0 0 0 1 R/W R/W R/W R/W R/W R/W R/W 1 R/W reserved - Areas 18-17 device size selection 1 8 bits 0 16 bits Areas 18-17 A18DF[1:0] Number of cycles 1 1 3.5 output disable delay time 1 0 2.5 0 1 1.5 0 0 0.5 - reserved A18WT[2:0] Wait cycles Areas 18-17 wait control 1 1 1 7 1 1 0 6 1 0 1 5 1 0 0 4 0 1 1 3 0 1 0 2 0 0 1 1 0 0 0 0 - reserved Areas 16-15 device size selection 1 8 bits 0 16 bits Areas 16-15 A16DF[1:0] Number of cycles 1 1 3.5 output disable delay time 1 0 2.5 0 1 1.5 0 0 0.5 - reserved A16WT[2:0] Wait cycles Areas 16-15 wait control 1 1 1 7 1 1 0 6 1 0 1 5 1 0 0 4 0 1 1 3 0 1 0 2 0 0 1 1 0 0 0 0 - 0 1 1 - 0 when being read. R/W R/W - 1 1 1 - 0 when being read. R/W - 0 1 1 - 0 when being read. R/W R/W - 1 1 1 - 0 when being read. R/W - A14DRA A13DRA A14SZ A14DF1 A14DF0 reserved Area 14 DRAM selection Area 13 DRAM selection Areas 14-13 device size selection Areas 14-13 output disable delay time - 0 0 0 1 1 - 0 when being read. R/W R/W R/W R/W - A14WT2 A14WT1 A14WT0 reserved Areas 14-13 wait control - 1 1 1 - 0 when being read. R/W - 1 Used 0 Not used 1 Used 0 Not used 1 8 bits 0 16 bits A14DF[1:0] Number of cycles 1 1 3.5 1 0 2.5 0 1 1.5 0 0 0.5 - A14WT[2:0] Wait cycles 1 1 1 7 1 1 0 6 1 0 1 5 1 0 0 4 0 1 1 3 0 1 0 2 0 0 1 1 0 0 0 0 B-ap S1C33L03 FUNCTION PART EPSON B-APPENDIX-23 APPENDIX: I/O MAP Register name Address Bit Areas 12-11 0048124 set-up register (HW) DF-7 D6 D5 D4 - A12SZ A12DF1 A12DF0 D3 D2 D1 D0 - A12WT2 A12WT1 A12WT0 DF DE DD DC Areas 10-9 0048126 set-up register (HW) Areas 8-7 0048128 set-up register (HW) B-APPENDIX-24 Name Function Setting Init. R/W Remarks reserved - Areas 12-11 device size selection 1 8 bits 0 16 bits Areas 12-11 A18DF[1:0] Number of cycles 1 1 3.5 output disable delay time 1 0 2.5 0 1 1.5 0 0 0.5 - reserved A18WT[2:0] Wait cycles Areas 12-11 wait control 1 1 1 7 1 1 0 6 1 0 1 5 1 0 0 4 0 1 1 3 0 1 0 2 0 0 1 1 0 0 0 0 - 0 1 1 - 0 when being read. R/W R/W - 1 1 1 - 0 when being read. R/W - A10IR2 A10IR1 A10IR0 reserved Area 10 internal ROM size selection - 1 1 1 - 0 when being read. R/W DB DA D9 - A10BW1 A10BW0 reserved Areas 10-9 burst ROM burst read cycle wait control - 0 0 - 0 when being read. R/W D8 D7 D6 D5 D4 A10DRA A9DRA A10SZ A10DF1 A10DF0 Area 10 burst ROM selection Area 9 burst ROM selection Areas 10-9 device size selection Areas 10-9 output disable delay time 0 0 0 1 1 R/W R/W R/W R/W D3 D2 D1 D0 - A10WT2 A10WT1 A10WT0 reserved Areas 10-9 wait control - A10BW[1:0] Wait cycles 1 1 3 1 0 2 0 1 1 0 0 0 1 Used 0 Not used 1 Used 0 Not used 1 8 bits 0 16 bits A10DF[1:0] Number of cycles 1 1 3.5 1 0 2.5 0 1 1.5 0 0 0.5 - A10WT[2:0] Wait cycles 1 1 1 7 1 1 0 6 1 0 1 5 1 0 0 4 0 1 1 3 0 1 0 2 0 0 1 1 0 0 0 0 - 1 1 1 - 0 when being read. R/W DF-9 D8 D7 D6 D5 D4 - A8DRA A7DRA A8SZ A8DF1 A8DF0 reserved Area 8 DRAM selection Area 7 DRAM selection Areas 8-7 device size selection Areas 8-7 output disable delay time - - 0 0 0 1 1 - 0 when being read. R/W R/W R/W R/W D3 D2 D1 D0 - A8WT2 A8WT1 A8WT0 reserved Areas 8-7 wait control - 1 1 1 - 0 when being read. R/W EPSON - A10IR[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 1 Used 1 Used 1 8 bits A8DF[1:0] 1 1 1 0 0 1 0 0 ROM size 2MB 1MB 512KB 256KB 128KB 64KB 32KB 16KB 0 Not used 0 Not used 0 16 bits Number of cycles 3.5 2.5 1.5 0.5 - A8WT[2:0] Wait cycles 1 1 1 7 1 1 0 6 1 0 1 5 1 0 0 4 0 1 1 3 0 1 0 2 0 0 1 1 0 0 0 0 S1C33L03 FUNCTION PART APPENDIX: I/O MAP A-1 Register name Address Bit Name Areas 6-4 004812A DF-E - set-up register (HW) DD A6DF1 DC A6DF0 Function reserved Area 6 output disable delay time Setting - Number of cycles 3.5 2.5 1.5 0.5 - A6WT[2:0] Wait cycles 1 1 1 7 1 1 0 6 1 0 1 5 1 0 0 4 0 1 1 3 0 1 0 2 0 0 1 1 0 0 0 0 - 1 8 bits 0 16 bits A5DF[1:0] Number of cycles 1 1 3.5 1 0 2.5 0 1 1.5 0 0 0.5 A6DF[1:0] 1 1 1 0 0 1 0 0 Init. R/W Remarks - 1 1 - 0 when being read. R/W - 1 1 1 - 0 when being read. R/W - 0 1 1 - 0 when being read. R/W R/W - 1 1 1 - 0 when being read. R/W DB DA D9 D8 - A6WT2 A6WT1 A6WT0 reserved Area 6 wait control D7 D6 D5 D4 - A5SZ A5DF1 A5DF0 reserved Areas 5-4 device size selection Areas 5-4 output disable delay time D3 D2 D1 D0 - A5WT2 A5WT1 A5WT0 reserved Areas 5-4 wait control TTBR write 004812D protect register (B) D7 D6 D5 D4 D3 D2 D1 D0 TBRP7 TBRP6 TBRP5 TBRP4 TBRP3 TBRP2 TBRP1 TBRP0 TTBR register write protect Writing 01011001 (0x59) removes the TTBR (0x48134) write protection. Writing other data sets the write protection. 0 0 0 0 0 0 0 0 Bus control register DF DE DD DC DB DA RBCLK - RBST8 REDO RCA1 RCA0 BCLK output control reserved Burst ROM burst mode selection DRAM page mode selection Column address size selection 1 Fixed at H 0 0 0 0 0 0 R/W - Writing 1 not allowed. R/W R/W R/W D9 D8 D7 D6 D5 RPC2 RPC1 RPC0 RRA1 RRA0 0 0 0 0 0 R/W R/W R/W R/W D4 D3 D2 D1 D0 - SBUSST SEMAS SEPD SWAITE 0 0 0 0 0 - Writing 1 not allowed. R/W R/W R/W R/W 004812E (HW) A5WT[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 Wait cycles 7 6 5 4 3 2 1 0 0 Enabled - 1 8-successive 0 4-successive 1 EDO 0 Fast page RCA[1:0] Size 1 1 11 1 0 10 0 1 9 0 0 8 1 Enabled 0 Disabled Refresh enable 1 Self-refresh 0 CBR-refresh Refresh method selection 1 2.0 0 1.0 Refresh RPC delay setup RRA[1:0] Number of cycles Refresh RAS pulse width 1 1 5 selection 1 0 4 0 1 3 0 0 2 - reserved External interface method selection 1 #BSL 0 A0 External bus master setup 1 Existing 0 Nonexistent 1 Enabled 0 Disabled External power-down control 1 Enabled 0 Disabled #WAIT enable W Undefined in read. B-ap S1C33L03 FUNCTION PART EPSON B-APPENDIX-25 APPENDIX: I/O MAP Register name Address Bit Name Function DRAM timing 0048130 DF-C - reserved set-up register (HW) DB A3EEN Area 3 emulation DA CEFUNC1 #CE pin function selection D9 CEFUNC0 Setting Init. R/W Remarks - 1 Internal ROM 0 Emulation CEFUNC[1:0] #CE output 1 x #CE7/8..#CE17/18 #CE6..#CE17 0 1 #CE4..#CE10 0 0 1 Successive 0 Normal RPRC[1:0] Number of cycles 1 1 4 1 0 3 0 1 2 0 0 1 - CASC[1:0] Number of cycles 1 1 4 1 0 3 0 1 2 0 0 1 - RASC[1:0] Number of cycles 1 1 4 1 0 3 0 1 2 0 0 1 - 1 0 0 - 0 when being read. R/W R/W 0 0 0 R/W R/W - 0 0 - 0 when being read. R/W - 0 0 - 0 when being read. R/W D8 D7 D6 CRAS RPRC1 RPRC0 Successive RAS mode setup DRAM RAS precharge cycles selection D5 D4 D3 - CASC1 CASC0 reserved DRAM CAS cycles selection D2 D1 D0 - RASC1 RASC0 reserved DRAM RAS cycles selection Access control 0048132 register (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A18IO A16IO A14IO A12IO - A8IO A6IO A5IO A18EC A16EC A14EC A12EC A10EC A8EC A6EC A5EC Area 18, 17 internal/external access 1 Internal 0 External Area 16, 15 internal/external access access access Area 14, 13 internal/external access Area 12, 11 internal/external access reserved - 0 External Area 8, 7 internal/external access 1 Internal Area 6 internal/external access access access Area 5, 4 internal/external access Area 18, 17 endian control 1 Big endian 0 Little endian Area 16, 15 endian control Area 14, 13 endian control Area 12, 11 endian control Area 10, 9 endian control Area 8, 7 endian control Area 6 endian control Area 5, 4 endian control 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W - 0 when being read. R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TTBR loworder register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TTBR15 TTBR14 TTBR13 TTBR12 TTBR11 TTBR10 TTBR09 TTBR08 TTBR07 TTBR06 TTBR05 TTBR04 TTBR03 TTBR02 TTBR01 TTBR00 Trap table base address [15:10] R/W Trap table base address [9:0] Fixed at 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R 0 when being read. Writing 1 not allowed. DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TTBR33 TTBR32 TTBR31 TTBR30 TTBR2B TTBR2A TTBR29 TTBR28 TTBR27 TTBR26 TTBR25 TTBR24 TTBR23 TTBR22 TTBR21 TTBR20 Trap table base address [31:28] Fixed at 0 R 0 when being read. Writing 1 not allowed. Trap table base address [27:16] 0x0C0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 TTBR highorder register 0048134 (HW) 0048136 (HW) B-APPENDIX-26 EPSON R/W S1C33L03 FUNCTION PART APPENDIX: I/O MAP A-1 Register name Address Bit G/A read signal 0048138 control register (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BCLK select register Name A18AS A16AS A14AS A12AS - A8AS A6AS A5AS A18RD A16RD A14RD A12RD - A8RD A6RD A5RD 004813A D7-4 - (B) D3 A1X1MD D2 - D1 BCLKSEL1 D0 BCLKSEL0 Function Area 18, 17 address strobe signal Area 16, 15 address strobe signal Area 14, 13 address strobe signal Area 12, 11 address strobe signal reserved Area 8, 7 address strobe signal Area 6 address strobe signal Area 5, 4 address strobe signal Area 18, 17 read signal Area 16, 15 read signal Area 14, 13 read signal Area 12, 11 read signal reserved Area 8, 7 read signal Area 6 read signal Area 5, 4 read signal reserved Area 1 access-speed reserved BCLK output clock selection Setting 1 Enabled 0 Disabled - 1 Enabled 0 Disabled 1 Enabled 0 Disabled - 1 Enabled 0 Disabled - 1 2 cycles 0 4 cycles - BCLKSEL[1:0] 1 1 1 0 0 1 0 0 BCLK PLL_CLK OSC3_CLK BCU_CLK CPU_CLK Init. R/W Remarks 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W - 0 when being read. R/W R/W R/W R/W R/W R/W R/W - 0 when being read. R/W R/W R/W 0 0 0 0 0 - 0 when being read. R/W x2 speed mode only - 0 when being read. R/W B-ap S1C33L03 FUNCTION PART EPSON B-APPENDIX-27 APPENDIX: I/O MAP Register name Address Bit Name Function Setting 16-bit timer 0 comparison register A 0048180 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR0A15 CR0A14 CR0A13 CR0A12 CR0A11 CR0A10 CR0A9 CR0A8 CR0A7 CR0A6 CR0A5 CR0A4 CR0A3 CR0A2 CR0A1 CR0A0 16-bit timer 0 comparison data A CR0A15 = MSB CR0A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 0 comparison register B 0048182 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR0B15 CR0B14 CR0B13 CR0B12 CR0B11 CR0B10 CR0B9 CR0B8 CR0B7 CR0B6 CR0B5 CR0B4 CR0B3 CR0B2 CR0B1 CR0B0 16-bit timer 0 comparison data B CR0B15 = MSB CR0B0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 0 counter data register 0048184 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC015 TC014 TC013 TC012 TC011 TC010 TC09 TC08 TC07 TC06 TC05 TC04 TC03 TC02 TC01 TC00 16-bit timer 0 counter data TC015 = MSB TC00 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R 16-bit timer 0 0048186 control register (B) D7 D6 D5 D4 D3 D2 D1 D0 - SELFM0 SELCRB0 OUTINV0 CKSL0 PTM0 PRESET0 PRUN0 reserved 16-bit timer 0 fine mode selection 16-bit timer 0 comparison buffer 16-bit timer 0 output inversion 16-bit timer 0 input clock selection 16-bit timer 0 clock output control 16-bit timer 0 reset 16-bit timer 0 Run/Stop control B-APPENDIX-28 EPSON 1 1 1 1 1 1 1 - Fine mode 0 Enabled 0 Invert 0 External clock 0 On 0 Reset 0 Run 0 Init. R/W Normal Disabled Normal Internal clock Off Invalid Stop 0 0 0 0 0 0 0 0 Remarks - 0 when being read. R/W R/W R/W R/W R/W W 0 when being read. R/W S1C33L03 FUNCTION PART APPENDIX: I/O MAP A-1 Register name Address Bit Name Function Setting 16-bit timer 1 comparison register A 0048188 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 1 comparison register B 004818A (HW) 16-bit timer 1 counter data register CR1A15 CR1A14 CR1A13 CR1A12 CR1A11 CR1A10 CR1A9 CR1A8 CR1A7 CR1A6 CR1A5 CR1A4 CR1A3 CR1A2 CR1A1 CR1A0 16-bit timer 1 comparison data A CR1A15 = MSB CR1A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR1B15 CR1B14 CR1B13 CR1B12 CR1B11 CR1B10 CR1B9 CR1B8 CR1B7 CR1B6 CR1B5 CR1B4 CR1B3 CR1B2 CR1B1 CR1B0 16-bit timer 1 comparison data B CR1B15 = MSB CR1B0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 004818C (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC115 TC114 TC113 TC112 TC111 TC110 TC19 TC18 TC17 TC16 TC15 TC14 TC13 TC12 TC11 TC10 16-bit timer 1 counter data TC115 = MSB TC10 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R 16-bit timer 1 004818E control register (B) D7 D6 D5 D4 D3 D2 D1 D0 - SELFM1 SELCRB1 OUTINV1 CKSL1 PTM1 PRESET1 PRUN1 reserved 16-bit timer 1 fine mode selection 16-bit timer 1 comparison buffer 16-bit timer 1 output inversion 16-bit timer 1 input clock selection 16-bit timer 1 clock output control 16-bit timer 1 reset 16-bit timer 1 Run/Stop control 1 1 1 1 1 1 1 - Fine mode 0 Enabled 0 Invert 0 External clock 0 On 0 Reset 0 Run 0 Init. R/W Normal Disabled Normal Internal clock Off Invalid Stop 0 0 0 0 0 0 0 0 Remarks - 0 when being read. R/W R/W R/W R/W R/W W 0 when being read. R/W B-ap S1C33L03 FUNCTION PART EPSON B-APPENDIX-29 APPENDIX: I/O MAP Register name Address Bit Name Function Setting 16-bit timer 2 comparison register A 0048190 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR2A15 CR2A14 CR2A13 CR2A12 CR2A11 CR2A10 CR2A9 CR2A8 CR2A7 CR2A6 CR2A5 CR2A4 CR2A3 CR2A2 CR2A1 CR2A0 16-bit timer 2 comparison data A CR2A15 = MSB CR2A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 2 comparison register B 0048192 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR2B15 CR2B14 CR2B13 CR2B12 CR2B11 CR2B10 CR2B9 CR2B8 CR2B7 CR2B6 CR2B5 CR2B4 CR2B3 CR2B2 CR2B1 CR2B0 16-bit timer 2 comparison data B CR2B15 = MSB CR2B0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 2 counter data register 0048194 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC215 TC214 TC213 TC212 TC211 TC210 TC29 TC28 TC27 TC26 TC25 TC24 TC23 TC22 TC21 TC20 16-bit timer 2 counter data TC215 = MSB TC20 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R 16-bit timer 2 0048196 control register (B) D7 D6 D5 D4 D3 D2 D1 D0 - SELFM2 SELCRB2 OUTINV2 CKSL2 PTM2 PRESET2 PRUN2 reserved 16-bit timer 2 fine mode selection 16-bit timer 2 comparison buffer 16-bit timer 2 output inversion 16-bit timer 2 input clock selection 16-bit timer 2 clock output control 16-bit timer 2 reset 16-bit timer 2 Run/Stop control B-APPENDIX-30 EPSON 1 1 1 1 1 1 1 - Fine mode 0 Enabled 0 Invert 0 External clock 0 On 0 Reset 0 Run 0 Init. R/W Normal Disabled Normal Internal clock Off Invalid Stop 0 0 0 0 0 0 0 0 Remarks - 0 when being read. R/W R/W R/W R/W R/W W 0 when being read. R/W S1C33L03 FUNCTION PART APPENDIX: I/O MAP A-1 Register name Address Bit Name Function Setting 16-bit timer 3 comparison register A 0048198 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 3 comparison register B 004819A (HW) 16-bit timer 3 counter data register CR3A15 CR3A14 CR3A13 CR3A12 CR3A11 CR3A10 CR3A9 CR3A8 CR3A7 CR3A6 CR3A5 CR3A4 CR3A3 CR3A2 CR3A1 CR3A0 16-bit timer 3 comparison data A CR3A15 = MSB CR3A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR3B15 CR3B14 CR3B13 CR3B12 CR3B11 CR3B10 CR3B9 CR3B8 CR3B7 CR3B6 CR3B5 CR3B4 CR3B3 CR3B2 CR3B1 CR3B0 16-bit timer 3 comparison data B CR3B15 = MSB CR3B0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 004819C (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC315 TC314 TC313 TC312 TC311 TC310 TC39 TC38 TC37 TC36 TC35 TC34 TC33 TC32 TC31 TC30 16-bit timer 3 counter data TC315 = MSB TC30 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R 16-bit timer 3 004819E control register (B) D7 D6 D5 D4 D3 D2 D1 D0 - SELFM3 SELCRB3 OUTINV3 CKSL3 PTM3 PRESET3 PRUN3 reserved 16-bit timer 3 fine mode selection 16-bit timer 3 comparison buffer 16-bit timer 3 output inversion 16-bit timer 3 input clock selection 16-bit timer 3 clock output control 16-bit timer 3 reset 16-bit timer 3 Run/Stop control 1 1 1 1 1 1 1 - Fine mode 0 Enabled 0 Invert 0 External clock 0 On 0 Reset 0 Run 0 Init. R/W Normal Disabled Normal Internal clock Off Invalid Stop 0 0 0 0 0 0 0 0 Remarks - 0 when being read. R/W R/W R/W R/W R/W W 0 when being read. R/W B-ap S1C33L03 FUNCTION PART EPSON B-APPENDIX-31 APPENDIX: I/O MAP Register name Address Bit Name Function Setting 16-bit timer 4 comparison register A 00481A0 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR4A15 CR4A14 CR4A13 CR4A12 CR4A11 CR4A10 CR4A9 CR4A8 CR4A7 CR4A6 CR4A5 CR4A4 CR4A3 CR4A2 CR4A1 CR4A0 16-bit timer 4 comparison data A CR4A15 = MSB CR4A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 4 comparison register B 00481A2 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR4B15 CR4B14 CR4B13 CR4B12 CR4B11 CR4B10 CR4B9 CR4B8 CR4B7 CR4B6 CR4B5 CR4B4 CR4B3 CR4B2 CR4B1 CR4B0 16-bit timer 4 comparison data B CR4B15 = MSB CR4B0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 4 counter data register 00481A4 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC415 TC414 TC413 TC412 TC411 TC410 TC49 TC48 TC47 TC46 TC45 TC44 TC43 TC42 TC41 TC40 16-bit timer 4 counter data TC415 = MSB TC40 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R 16-bit timer 4 00481A6 control register (B) D7 D6 D5 D4 D3 D2 D1 D0 - SELFM4 SELCRB4 OUTINV4 CKSL4 PTM4 PRESET4 PRUN4 reserved 16-bit timer 4 fine mode selection 16-bit timer 4 comparison buffer 16-bit timer 4 output inversion 16-bit timer 4 input clock selection 16-bit timer 4 clock output control 16-bit timer 4 reset 16-bit timer 4 Run/Stop control B-APPENDIX-32 EPSON 1 1 1 1 1 1 1 - Fine mode 0 Enabled 0 Invert 0 External clock 0 On 0 Reset 0 Run 0 Init. R/W Normal Disabled Normal Internal clock Off Invalid Stop 0 0 0 0 0 0 0 0 Remarks - 0 when being read. R/W R/W R/W R/W R/W W 0 when being read. R/W S1C33L03 FUNCTION PART APPENDIX: I/O MAP A-1 Register name Address Bit Name Function Setting 16-bit timer 5 comparison register A 00481A8 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 5 comparison register B 00481AA (HW) 16-bit timer 5 counter data register CR5A15 CR5A14 CR5A13 CR5A12 CR5A11 CR5A10 CR5A9 CR5A8 CR5A7 CR5A6 CR5A5 CR5A4 CR5A3 CR5A2 CR5A1 CR5A0 16-bit timer 5 comparison data A CR5A15 = MSB CR5A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CR5B15 CR5B14 CR5B13 CR5B12 CR5B11 CR5B10 CR5B9 CR5B8 CR5B7 CR5B6 CR5B5 CR5B4 CR5B3 CR5B2 CR5B1 CR5B0 16-bit timer 5 comparison data B CR5B15 = MSB CR5B0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 00481AC (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC515 TC514 TC513 TC512 TC511 TC510 TC59 TC58 TC57 TC56 TC55 TC54 TC53 TC52 TC51 TC50 16-bit timer 5 counter data TC515 = MSB TC50 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R 16-bit timer 5 00481AE control register (B) D7 D6 D5 D4 D3 D2 D1 D0 - SELFM5 SELCRB5 OUTINV5 CKSL5 PTM5 PRESET5 PRUN5 reserved 16-bit timer 5 fine mode selection 16-bit timer 5 comparison buffer 16-bit timer 5 output inversion 16-bit timer 5 input clock selection 16-bit timer 5 clock output control 16-bit timer 5 reset 16-bit timer 5 Run/Stop control 1 1 1 1 1 1 1 - Fine mode 0 Enabled 0 Invert 0 External clock 0 On 0 Reset 0 Run 0 Init. R/W Normal Disabled Normal Internal clock Off Invalid Stop 0 0 0 0 0 0 0 0 Remarks - 0 when being read. R/W R/W R/W R/W R/W W 0 when being read. R/W B-ap S1C33L03 FUNCTION PART EPSON B-APPENDIX-33 APPENDIX: I/O MAP Register name Address Bit IDMA base address loworder register 0048200 (HW) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 IDMA base address high-order register 0048202 DF-C - (HW) DB DBASEH11 DA DBASEH10 D9 DBASEH9 D8 DBASEH8 D7 DBASEH7 D6 DBASEH6 D5 DBASEH5 D4 DBASEH4 D3 DBASEH3 D2 DBASEH2 D1 DBASEH1 D0 DBASEH0 reserved IDMA base address high-order 12 bits (Initial value: 0x0C003A0) IDMA start register 0048204 (B) D7 DSTART D6-0 DCHN IDMA start IDMA channel number 1 IDMA start 0 Stop 0 to 127 IDMA enable register 0048205 (B) D7-1 - D0 IDMAEN reserved IDMA enable 1 Enabled B-APPENDIX-34 Name Function Setting DBASEL15 IDMA base address DBASEL14 low-order 16 bits DBASEL13 (Initial value: 0x0C003A0) DBASEL12 DBASEL11 DBASEL10 DBASEL9 DBASEL8 DBASEL7 DBASEL6 DBASEL5 DBASEL4 DBASEL3 DBASEL2 DBASEL1 DBASEL0 - - EPSON 0 Disabled Init. R/W Remarks 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 R/W - 0 0 0 0 1 1 0 0 0 0 0 0 - Undefined in read. R/W 0 0 R/W R/W - 0 - R/W S1C33L03 FUNCTION PART APPENDIX: I/O MAP A-1 Register name Address Bit Name High-speed DMA Ch.0 transfer counter register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC0_L7 TC0_L6 TC0_L5 TC0_L4 TC0_L3 TC0_L2 TC0_L1 TC0_L0 BLKLEN07 BLKLEN06 BLKLEN05 BLKLEN04 BLKLEN03 BLKLEN02 BLKLEN01 BLKLEN00 Ch.0 transfer counter[7:0] (block transfer mode) DF DE DUALM0 D0DIR DD-8 D7 D6 D5 D4 D3 D2 D1 D0 - TC0_H7 TC0_H6 TC0_H5 TC0_H4 TC0_H3 TC0_H2 TC0_H1 TC0_H0 Ch.0 address mode selection D) Invalid S) Ch.0 transfer direction control reserved Ch.0 transfer counter[15:8] (block transfer mode) 0048220 (HW) High-speed 0048222 DMA Ch.0 (HW) control register Note: D) Dual address mode S) Single address mode High-speed 0048224 DMA Ch.0 (HW) low-order source address set-up register Note: D) Dual address mode S) Single address mode High-speed 0048226 DMA Ch.0 (HW) high-order source address set-up register Note: D) Dual address mode S) Single address mode Function Setting Ch.0 transfer counter[15:8] (single/successive transfer mode) Ch.0 block length (block transfer mode) Ch.0 transfer counter[7:0] (single/successive transfer mode) 1 Dual addr 0 Single addr - 1 Memory WR 0 Memory RD - Ch.0 transfer counter[23:16] (single/successive transfer mode) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S0ADRL15 D) Ch.0 source address[15:0] S0ADRL14 S) Ch.0 memory address[15:0] S0ADRL13 S0ADRL12 S0ADRL11 S0ADRL10 S0ADRL9 S0ADRL8 S0ADRL7 S0ADRL6 S0ADRL5 S0ADRL4 S0ADRL3 S0ADRL2 S0ADRL1 S0ADRL0 DF DE DD DC - DATSIZE0 S0IN1 S0IN0 DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S0ADRH11 D) Ch.0 source address[27:16] S0ADRH10 S) Ch.0 memory address[27:16] S0ADRH9 S0ADRH8 S0ADRH7 S0ADRH6 S0ADRH5 S0ADRH4 S0ADRH3 S0ADRH2 S0ADRH1 S0ADRH0 reserved Ch.0 transfer data size D) Ch.0 source address control S) Ch.0 memory address control - 1 Half word S0IN[1:0] 1 1 1 0 0 1 0 0 0 Byte Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed Init. R/W Remarks X X X X X X X X X X X X X X X X R/W 0 - 0 - X X X X X X X X R/W - R/W - Undefined in read. R/W X X X X X X X X X X X X X X X X R/W - 0 0 0 - R/W R/W X X X X X X X X X X X X R/W R/W B-ap S1C33L03 FUNCTION PART EPSON B-APPENDIX-35 APPENDIX: I/O MAP Register name Address Bit High-speed 0048228 DMA Ch.0 (HW) low-order destination address set-up register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D0ADRL15 D) Ch.0 destination address[15:0] D0ADRL14 S) Invalid D0ADRL13 D0ADRL12 D0ADRL11 D0ADRL10 D0ADRL9 D0ADRL8 D0ADRL7 D0ADRL6 D0ADRL5 D0ADRL4 D0ADRL3 D0ADRL2 D0ADRL1 D0ADRL0 DF DE D0MOD1 D0MOD0 Ch.0 transfer mode DD DC D0IN1 D0IN0 D) Ch.0 destination address control S) Invalid DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D0ADRH11 D) Ch.0 destination D0ADRH10 address[27:16] D0ADRH9 S) Invalid D0ADRH8 D0ADRH7 D0ADRH6 D0ADRH5 D0ADRH4 D0ADRH3 D0ADRH2 D0ADRH1 D0ADRH0 Note: D) Dual address mode S) Single address mode High-speed 004822A DMA Ch.0 (HW) high-order destination address set-up register Note: D) Dual address mode S) Single address mode Name Function High-speed 004822C DF-1 - DMA Ch.0 (HW) D0 HS0_EN enable register reserved High-speed DMA Ch.0 trigger flag register reserved 004822E DF-1 - (HW) D0 HS0_TF B-APPENDIX-36 Setting D0MOD[1:0] 1 1 1 0 0 1 0 0 D0IN[1:0] 1 1 1 0 0 1 0 0 Mode Invalid Block Successive Single Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed - Ch.0 enable 1 Enable 0 Disable - Ch.0 trigger flag clear (writing) Ch.0 trigger flag status (reading) EPSON 1 Clear 1 Set 0 No operation 0 Cleared Init. R/W X X X X X X X X X X X X X X X X R/W 0 0 R/W 0 0 R/W X X X X X X X X X X X X R/W - - 0 R/W - - 0 R/W Remarks Undefined in read. Undefined in read. S1C33L03 FUNCTION PART APPENDIX: I/O MAP A-1 Register name Address Bit Name High-speed DMA Ch.1 transfer counter register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC1_L7 TC1_L6 TC1_L5 TC1_L4 TC1_L3 TC1_L2 TC1_L1 TC1_L0 BLKLEN17 BLKLEN16 BLKLEN15 BLKLEN14 BLKLEN13 BLKLEN12 BLKLEN11 BLKLEN10 Ch.1 transfer counter[7:0] (block transfer mode) DF DE DUALM1 D1DIR DD-8 D7 D6 D5 D4 D3 D2 D1 D0 - TC1_H7 TC1_H6 TC1_H5 TC1_H4 TC1_H3 TC1_H2 TC1_H1 TC1_H0 Ch.1 address mode selection D) Invalid S) Ch.1 transfer direction control reserved Ch.1 transfer counter[15:8] (block transfer mode) 0048230 (HW) High-speed 0048232 DMA Ch.1 (HW) control register Note: D) Dual address mode S) Single address mode High-speed 0048234 DMA Ch.1 (HW) low-order source address set-up register Note: D) Dual address mode S) Single address mode High-speed 0048236 DMA Ch.1 (HW) high-order source address set-up register Note: D) Dual address mode S) Single address mode Function Setting Ch.1 transfer counter[15:8] (single/successive transfer mode) Ch.1 block length (block transfer mode) Ch.1 transfer counter[7:0] (single/successive transfer mode) 1 Dual addr 0 Single addr - 1 Memory WR 0 Memory RD - Ch.1 transfer counter[23:16] (single/successive transfer mode) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1ADRL15 D) Ch.1 source address[15:0] S1ADRL14 S) Ch.1 memory address[15:0] S1ADRL13 S1ADRL12 S1ADRL11 S1ADRL10 S1ADRL9 S1ADRL8 S1ADRL7 S1ADRL6 S1ADRL5 S1ADRL4 S1ADRL3 S1ADRL2 S1ADRL1 S1ADRL0 DF DE DD DC - DATSIZE1 S1IN1 S1IN0 DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1ADRH11 D) Ch.1 source address[27:16] S1ADRH10 S) Ch.1 memory address[27:16] S1ADRH9 S1ADRH8 S1ADRH7 S1ADRH6 S1ADRH5 S1ADRH4 S1ADRH3 S1ADRH2 S1ADRH1 S1ADRH0 reserved Ch.1 transfer data size D) Ch.1 source address control S) Ch.1 memory address control - 1 Half word S1IN[1:0] 1 1 1 0 0 1 0 0 0 Byte Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed Init. R/W Remarks X X X X X X X X X X X X X X X X R/W 0 - 0 - X X X X X X X X R/W - R/W - Undefined in read. R/W X X X X X X X X X X X X X X X X R/W - 0 0 0 - R/W R/W X X X X X X X X X X X X R/W R/W B-ap S1C33L03 FUNCTION PART EPSON B-APPENDIX-37 APPENDIX: I/O MAP Register name Address Bit High-speed 0048238 DMA Ch.1 (HW) low-order destination address set-up register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D1ADRL15 D) Ch.1 destination address[15:0] D1ADRL14 S) Invalid D1ADRL13 D1ADRL12 D1ADRL11 D1ADRL10 D1ADRL9 D1ADRL8 D1ADRL7 D1ADRL6 D1ADRL5 D1ADRL4 D1ADRL3 D1ADRL2 D1ADRL1 D1ADRL0 DF DE D1MOD1 D1MOD0 Ch.1 transfer mode DD DC D1IN1 D1IN0 D) Ch.1 destination address control S) Invalid DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D1ADRH11 D) Ch.1 destination D1ADRH10 address[27:16] D1ADRH9 S) Invalid D1ADRH8 D1ADRH7 D1ADRH6 D1ADRH5 D1ADRH4 D1ADRH3 D1ADRH2 D1ADRH1 D1ADRH0 Note: D) Dual address mode S) Single address mode High-speed 004823A DMA Ch.1 (HW) high-order destination address set-up register Note: D) Dual address mode S) Single address mode Name Function High-speed 004823C DF-1 - DMA Ch.1 (HW) D0 HS1_EN enable register reserved High-speed DMA Ch.1 trigger flag register reserved 004823E DF-1 - (HW) D0 HS1_TF B-APPENDIX-38 Setting D1MOD[1:0] 1 1 1 0 0 1 0 0 D1IN[1:0] 1 1 1 0 0 1 0 0 Mode Invalid Block Successive Single Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed - Ch.1 enable 1 Enable 0 Disable - Ch.1 trigger flag clear (writing) Ch.1 trigger flag status (reading) EPSON 1 Clear 1 Set 0 No operation 0 Cleared Init. R/W X X X X X X X X X X X X X X X X R/W 0 0 R/W 0 0 R/W X X X X X X X X X X X X R/W - - 0 R/W - - 0 R/W Remarks Undefined in read. Undefined in read. S1C33L03 FUNCTION PART APPENDIX: I/O MAP A-1 Register name Address Bit Name High-speed DMA Ch.2 transfer counter register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC2_L7 TC2_L6 TC2_L5 TC2_L4 TC2_L3 TC2_L2 TC2_L1 TC2_L0 BLKLEN27 BLKLEN26 BLKLEN25 BLKLEN24 BLKLEN23 BLKLEN22 BLKLEN21 BLKLEN20 Ch.2 transfer counter[7:0] (block transfer mode) DF DE DUALM2 D2DIR DD-8 D7 D6 D5 D4 D3 D2 D1 D0 - TC2_H7 TC2_H6 TC2_H5 TC2_H4 TC2_H3 TC2_H2 TC2_H1 TC2_H0 Ch.2 address mode selection D) Invalid S) Ch.2 transfer direction control reserved Ch.2 transfer counter[15:8] (block transfer mode) 0048240 (HW) High-speed 0048242 DMA Ch.2 (HW) control register Note: D) Dual address mode S) Single address mode High-speed 0048244 DMA Ch.2 (HW) low-order source address set-up register Note: D) Dual address mode S) Single address mode High-speed 0048246 DMA Ch.2 (HW) high-order source address set-up register Note: D) Dual address mode S) Single address mode Function Setting Ch.2 transfer counter[15:8] (single/successive transfer mode) Ch.2 block length (block transfer mode) Ch.2 transfer counter[7:0] (single/successive transfer mode) 1 Dual addr 0 Single addr - 1 Memory WR 0 Memory RD - Ch.2 transfer counter[23:16] (single/successive transfer mode) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S2ADRL15 D) Ch.2 source address[15:0] S2ADRL14 S) Ch.2 memory address[15:0] S2ADRL13 S2ADRL12 S2ADRL11 S2ADRL10 S2ADRL9 S2ADRL8 S2ADRL7 S2ADRL6 S2ADRL5 S2ADRL4 S2ADRL3 S2ADRL2 S2ADRL1 S2ADRL0 DF DE DD DC - DATSIZE2 S2IN1 S2IN0 DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S2ADRH11 D) Ch.2 source address[27:16] S2ADRH10 S) Ch.2 memory address[27:16] S2ADRH9 S2ADRH8 S2ADRH7 S2ADRH6 S2ADRH5 S2ADRH4 S2ADRH3 S2ADRH2 S2ADRH1 S2ADRH0 reserved Ch.2 transfer data size D) Ch.2 source address control S) Ch.2 memory address control - 1 Half word S2IN[1:0] 1 1 1 0 0 1 0 0 0 Byte Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed Init. R/W Remarks X X X X X X X X X X X X X X X X R/W 0 - 0 - X X X X X X X X R/W - R/W - Undefined in read. R/W X X X X X X X X X X X X X X X X R/W - 0 0 0 - R/W R/W X X X X X X X X X X X X R/W R/W B-ap S1C33L03 FUNCTION PART EPSON B-APPENDIX-39 APPENDIX: I/O MAP Register name Address Bit High-speed 0048248 DMA Ch.2 (HW) low-order destination address set-up register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D2ADRL15 D) Ch.2 destination address[15:0] D2ADRL14 S) Invalid D2ADRL13 D2ADRL12 D2ADRL11 D2ADRL10 D2ADRL9 D2ADRL8 D2ADRL7 D2ADRL6 D2ADRL5 D2ADRL4 D2ADRL3 D2ADRL2 D2ADRL1 D2ADRL0 DF DE D2MOD1 D2MOD0 Ch.2 transfer mode DD DC D2IN1 D2IN0 D) Ch.2 destination address control S) Invalid DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D2ADRH11 D) Ch.2 destination D2ADRH10 address[27:16] D2ADRH9 S) Invalid D2ADRH8 D2ADRH7 D2ADRH6 D2ADRH5 D2ADRH4 D2ADRH3 D2ADRH2 D2ADRH1 D2ADRH0 Note: D) Dual address mode S) Single address mode High-speed 004824A DMA Ch.2 (HW) high-order destination address set-up register Note: D) Dual address mode S) Single address mode Name Function High-speed 004824C DF-1 - DMA Ch.2 (HW) D0 HS2_EN enable register reserved High-speed DMA Ch.2 trigger flag register reserved 004824E DF-1 - (HW) D0 HS2_TF B-APPENDIX-40 Setting D2MOD[1:0] 1 1 1 0 0 1 0 0 D2IN[1:0] 1 1 1 0 0 1 0 0 Mode Invalid Block Successive Single Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed - Ch.2 enable 1 Enable 0 Disable - Ch.2 trigger flag clear (writing) Ch.2 trigger flag status (reading) EPSON 1 Clear 1 Set 0 No operation 0 Cleared Init. R/W X X X X X X X X X X X X X X X X R/W 0 0 R/W 0 0 R/W X X X X X X X X X X X X R/W - - 0 R/W - - 0 R/W Remarks Undefined in read. Undefined in read. S1C33L03 FUNCTION PART APPENDIX: I/O MAP A-1 Register name Address Bit Name High-speed DMA Ch.3 transfer counter register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC3_L7 TC3_L6 TC3_L5 TC3_L4 TC3_L3 TC3_L2 TC3_L1 TC3_L0 BLKLEN37 BLKLEN36 BLKLEN35 BLKLEN34 BLKLEN33 BLKLEN32 BLKLEN31 BLKLEN30 Ch.3 transfer counter[7:0] (block transfer mode) DF DE DUALM3 D3DIR DD-8 D7 D6 D5 D4 D3 D2 D1 D0 - TC3_H7 TC3_H6 TC3_H5 TC3_H4 TC3_H3 TC3_H2 TC3_H1 TC3_H0 Ch.3 address mode selection D) Invalid S) Ch.3 transfer direction control reserved Ch.3 transfer counter[15:8] (block transfer mode) 0048250 (HW) High-speed 0048252 DMA Ch.3 (HW) control register Note: D) Dual address mode S) Single address mode High-speed 0048254 DMA Ch.3 (HW) low-order source address set-up register Note: D) Dual address mode S) Single address mode High-speed 0048256 DMA Ch.3 (HW) high-order source address set-up register Note: D) Dual address mode S) Single address mode Function Setting Ch.3 transfer counter[15:8] (single/successive transfer mode) Ch.3 block length (block transfer mode) Ch.3 transfer counter[7:0] (single/successive transfer mode) 1 Dual addr 0 Single addr - 1 Memory WR 0 Memory RD - Ch.3 transfer counter[23:16] (single/successive transfer mode) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S3ADRL15 D) Ch.3 source address[15:0] S3ADRL14 S) Ch.3 memory address[15:0] S3ADRL13 S3ADRL12 S3ADRL11 S3ADRL10 S3ADRL9 S3ADRL8 S3ADRL7 S3ADRL6 S3ADRL5 S3ADRL4 S3ADRL3 S3ADRL2 S3ADRL1 S3ADRL0 DF DE DD DC - DATSIZE3 S3IN1 S3IN0 DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S3ADRH11 D) Ch.3 source address[27:16] S3ADRH10 S) Ch.3 memory address[27:16] S3ADRH9 S3ADRH8 S3ADRH7 S3ADRH6 S3ADRH5 S3ADRH4 S3ADRH3 S3ADRH2 S3ADRH1 S3ADRH0 reserved Ch.3 transfer data size D) Ch.3 source address control S) Ch.3 memory address control - 1 Half word S3IN[1:0] 1 1 1 0 0 1 0 0 0 Byte Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed Init. R/W Remarks X X X X X X X X X X X X X X X X R/W 0 - 0 - X X X X X X X X R/W - R/W - Undefined in read. R/W X X X X X X X X X X X X X X X X R/W - 0 0 0 - R/W R/W X X X X X X X X X X X X R/W R/W B-ap S1C33L03 FUNCTION PART EPSON B-APPENDIX-41 APPENDIX: I/O MAP Register name Address Bit High-speed 0048258 DMA Ch.3 (HW) low-order destination address set-up register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D3ADRL15 D) Ch.3 destination address[15:0] D3ADRL14 S) Invalid D3ADRL13 D3ADRL12 D3ADRL11 D3ADRL10 D3ADRL9 D3ADRL8 D3ADRL7 D3ADRL6 D3ADRL5 D3ADRL4 D3ADRL3 D3ADRL2 D3ADRL1 D3ADRL0 DF DE D3MOD1 D3MOD0 Ch.3 transfer mode DD DC D3IN1 D3IN0 D) Ch.3 destination address control S) Invalid DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D3ADRH11 D) Ch.3 destination D3ADRH10 address[27:16] D3ADRH9 S) Invalid D3ADRH8 D3ADRH7 D3ADRH6 D3ADRH5 D3ADRH4 D3ADRH3 D3ADRH2 D3ADRH1 D3ADRH0 Note: D) Dual address mode S) Single address mode High-speed 004825A DMA Ch.3 (HW) high-order destination address set-up register Note: D) Dual address mode S) Single address mode Name Function High-speed 004825C DF-1 - DMA Ch.3 (HW) D0 HS3_EN enable register reserved High-speed DMA Ch.3 trigger flag register reserved 004825E DF-1 - (HW) D0 HS3_TF B-APPENDIX-42 Setting D3MOD[1:0] 1 1 1 0 0 1 0 0 D3IN[1:0] 1 1 1 0 0 1 0 0 Mode Invalid Block Successive Single Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed - Ch.3 enable 1 Enable 0 Disable - Ch.3 trigger flag clear (writing) Ch.3 trigger flag status (reading) EPSON 1 Clear 1 Set 0 No operation 0 Cleared Init. R/W X X X X X X X X X X X X X X X X R/W 0 0 R/W 0 0 R/W X X X X X X X X X X X X R/W - - 0 R/W - - 0 R/W Remarks Undefined in read. Undefined in read. S1C33L03 FUNCTION PART APPENDIX: I/O MAP A-1 Register name Address SDRAM area configuration register 039FFC0 (B) SDRAM 039FFC1 control register (B) Bit Name SDRAR0 SDRAR1 - SDRPC0 SDRPC1 - Area 7/13 configuration Area 8/14 configuration reserved #CE7/13 pin configuration #CE8/14 pin configuration reserved 1 SDRAM 1 SDRAM D7 D6 D5 D4 SDRENA SDRINI SDRSRF SDRIS Enable SDRAM signals Start SDRAM power up Enable SDRAM self-refresh Initial command sequence 1 1 1 1 039FFC2 D7 - (B) D6-5 SDRCA1 SDRCA0 D4 - D3-2 SDRRA1 SDRRA0 D1 D0 SDRAM mode set-up register SDRBA - 039FFC3 D7 - (B) D6-5 SDRCL1 SDRCL0 D4 - D3-2 SDRBL1 SDRBL0 D1-0 - SDRAM timing set-up register 1 Setting D7 D6 D5-4 D3 D2 D1-0 D3 SDRCLK D2-0 - SDRAM address configuration register Function Keep SDCLK during self-refresh reserved reserved SDRAM page size (column range) 0 Not SDRAM 0 Not SDRAM - 1 #SDCE0 1 #SDCE1 0 #CE7/13 0 #CE8/14 - Enabled 0 Start 0 Enabled 0 1 precharge 0 2 set reg. 3 refresh 1 Kept 0 - Disabled - Disabled 1 precharge 2 refresh 3 set reg. Stopped - SDRCA[1:0] 1 1 1 0 0 1 0 0 reserved SDRAM row addressing range Number of SDRAM banks reserved reserved SDRAM CAS latency Page size reserved 1K (SDA[9:0]) 512 (SDA[8:0]) 256 (SDA[7:0]) - SDRRA[1:0] Addressing range 1 1 reserved 1 0 8K (SDA[12:0]) 0 1 4K (SDA[11:0]) 0 0 2K (SDA[10:0]) 1 4 banks 0 2 banks - SDRCL[1:0] 1 0 reserved SDRAM burst length SDRBL[1:0] 1 1 1 0 0 1 0 0 reserved 039FFC4 D7-5 SDRTRAS2 SDRAM tRAS spec (B) SDRTRAS1 SDRTRAS0 D4-3 SDRTRP1 SDRTRP0 Init. R/W - CAS latency 2 CAS latency - Burst length 8 4 2 1 - SDRTRAS[2:0] Number of clocks 1 1 1 7 1 1 0 6 1 0 1 5 1 0 0 4 0 1 1 3 0 1 0 2 0 0 1 1 0 0 0 8 SDRTRP[1:0] Number of clocks 1 1 3 1 0 2 0 1 1 0 0 4 SDRTRC[2:0] Number of clocks 1 1 1 7 1 1 0 6 1 0 1 5 1 0 0 4 0 1 1 3 0 1 0 2 0 0 1 1 0 0 0 8 SDRAM tRP spec D2-0 SDRTRC2 SDRAM tRC spec SDRTRC1 SDRTRC0 Remarks 0 0 - 0 0 - R/W R/W - 0 when being read. R/W R/W - 0 when being read. 0 0 0 0 R/W R/W 0 when being read. R/W R/W 1 - R/W - 0 when being read. - 0 0 - 0 when being read. R/W - 0 0 - 0 when being read. R/W 0 - R/W - 0 when being read. - 1 1 - 1 1 - 0 when being read. R/W - 0 when being read. R/W - - 0 0 0 R/W 0 0 R/W 0 0 0 R/W 0 when being read. B-ap S1C33L03 FUNCTION PART EPSON B-APPENDIX-43 APPENDIX: I/O MAP Register name Address SDRAM timing set-up register 2 Bit Name Function 039FFC5 D7-6 SDRTRCD1 SDRAM tRCD spec (B) SDRTRCD0 0 0 0 R/W R/W - - - 0 to 4096 - 1 1 1 1 1 1 1 1 1 1 1 1 - 0 when being read. R/W - 2 to 15 - 1 1 1 1 - 0 when being read. R/W This register must not be set less than "0x02". reserved - 1 8 bits 0 16 bits SDRAM data path bit width SDRAM bank interleaved access 1 Interleaved 0 One bank - reserved - 0 0 - - 0 when being read. R/W R/W - 0 when being read. SDRAM mode register set flag SDRAM current refresh mode reserved 1 1 - reserved 039FFC6 DF-C - reserved (HW) DB SDRARFC11 SDRAM auto refresh count [11:0] DA SDRARFC10 D9 SDRARFC9 D8 SDRARFC8 D7 SDRARFC7 D6 SDRARFC6 D5 SDRARFC5 D4 SDRARFC4 D3 SDRARFC3 D2 SDRARFC2 D1 SDRARFC1 D0 SDRARFC0 SDRAM self refresh count register 039FFC8 D7-4 - reserved (B) D3 SDRSRFC3 SDRAM self refresh count [3:0] D2 SDRSRFC2 D1 SDRSRFC1 D0 SDRSRFC0 SDRAM advanced control register 039FFC9 (B) SDRAM 039FFCA status register (B) B-APPENDIX-44 - SDRSZ SDRBI - D7 SDRMRS D6 SDRSRM D5-0 - Remarks R/W SDRAM auto refresh count register D7 D6 D5 D4-0 Init. R/W 0 0 D5 SDRTRSC SDRAM tRSC spec D4-3 SDRTRRD1 SDRAM tRRD spec SDRTRRD0 D2-0 - Setting SDRTRCD[1:0] Number of clocks 1 1 3 1 0 2 0 1 1 0 0 4 1 1 clock 0 2 clocks SDRTRRD[1:0] Number of clocks 1 1 3 1 0 2 0 1 1 0 0 4 - EPSON 1 Not finished 0 Done 1 Auto refresh 0 Self refresh - R R - 0 when being read. 0 when being read. S1C33L03 FUNCTION PART APPENDIX: I/O MAP A-1 Register name Address Bit Name Revision code register D7 D6 D5 D4 D3 D2 D1 D0 PCODE5 PCODE4 PCODE3 PCODE2 PCODE1 PCODE0 RCODE1 RCODE0 LCDC mode register 0 LCDC mode register 1 039FFE0 (B) Revision code 039FFE2 (B) BPP1 BPP0 Bit-per-pixel select (Display mode) - DBLANK FRMRPT - INVDISP reserved Blank display Frame repeat for EL panel reserved Invert display 039FFE3 D7-6 - (B) D5 LCDCEN D4 LPWREN D3-2 - D1 LPSAVE1 D0 LPSAVE0 Init. R/W 0b000010 reserved Color/monochrome select reserved Mask FPSHIFT signal LCD data width/format D7 D6 Setting Product code 039FFE1 D7-6 - (B) D5 LDCOLOR D4-3 - D2 FPSMASK D1 LDDW1 D0 LDDW0 D5-4 D3 D2 D1 D0 LCDC mode register 2 Function reserved LCD controller enable LCDPWR enable reserved Power save mode - 1 Color 0 Mono - 1 Masked LDDW[1:0] 1 x 0 1 0 0 LDDW[1:0] 1 1 1 0 0 1 0 0 0 Output Monochrome reserved 8 bits 4 bits Color 8 bits/format 2 reserved 8 bits/format 1 4 bits BPP[1:0] 1 1 1 0 0 1 0 0 Mode 8 bpp 4 bpp 2 bpp 1 bpp - 1 Blank 1 Repeated 0 Normal 0 Not repeated - 1 Inverted 0 Normal - 1 Enabled 1 Enabled 0 Disabled 0 Disabled - LPSAVE[1:0] Mode 1 1 Normal operation 1 0 Doze 0 1 reserved 0 0 Power save 0 0 0 0 1 0 0 0 Remarks R R - 0 - 0 0 0 - 0 when being read. R/W - 0 when being read. R/W R/W 0 0 R/W - 0 0 - 0 - 0 when being read. R/W R/W - 0 when being read. R/W - 0 0 - 0 0 - 0 when being read. R/W R/W - 0 when being read. R/W Horizontal panel size register 039FFE4 D7-6 - reserved (B) D5 LDHSIZE5 Horizontal panel size D4 LDHSIZE4 D3 LDHSIZE3 D2 LDHSIZE2 D1 LDHSIZE1 D0 LDHSIZE0 - H resolution (pixels) -1 16 - 0 0 0 0 0 0 - 0 when being read. R/W Vertical panel size register 0 039FFE5 (B) LDVSIZE7 Vertical panel size LDVSIZE6 (low-order 8 bits) LDVSIZE5 LDVSIZE4 LDVSIZE3 LDVSIZE2 LDVSIZE1 LDVSIZE0 V resolution (lines) - 1 0 0 0 0 0 0 0 0 R/W Vertical panel size register 1 039FFE6 D7-2 - reserved (B) D1 LDVSIZE9 Vertical panel size D0 LDVSIZE8 (high-order 2 bits) - V resolution (lines) - 1 - 0 0 - 0 when being read. R/W - Non-display period (pixels) -4 8 - 0 0 0 0 0 - 0 when being read. R/W D7 D6 D5 D4 D3 D2 D1 D0 Horizontal 039FFE7 D7-5 - non-display (B) D4 HNDP4 period register D3 HNDP3 D2 HNDP2 D1 HNDP1 D0 HNDP0 reserved Horizontal non-display period B-ap S1C33L03 FUNCTION PART EPSON B-APPENDIX-45 APPENDIX: I/O MAP Register name Address Bit Vertical 039FFEA non-display (B) period register D7 D6 D5 D4 D3 D2 D1 D0 Name VNDPF - VNDP5 VNDP4 VNDP3 VNDP2 VNDP1 VNDP0 Function Setting Vertical non-display period status 1 VNDP 0 Display - reserved Non display period (lines) Vertical non-display period - Init. R/W Remarks 0 - 0 0 0 0 0 0 R - 0 when being read. R/W - 0 0 0 0 0 0 - 0 when being read. R/W MOD rate register 039FFEB D7-6 - reserved (B) D5 MODRATE5 MOD rate D4 MODRATE4 D3 MODRATE3 D2 MODRATE2 D1 MODRATE1 D0 MODRATE0 Screen 1 start address register 0 039FFEC (B) D7 D6 D5 D4 D3 D2 D1 D0 S1ADDR7 S1ADDR6 S1ADDR5 S1ADDR4 S1ADDR3 S1ADDR2 S1ADDR1 S1ADDR0 Screen 1 start address (low-order 8 bits) 0 0 0 0 0 0 0 0 R/W Screen 1 start address register 1 039FFED (B) D7 D6 D5 D4 D3 D2 D1 D0 S1ADDR15 Screen 1 start address S1ADDR14 (high-order 8 bits) S1ADDR13 S1ADDR12 S1ADDR11 S1ADDR10 S1ADDR9 S1ADDR8 0 0 0 0 0 0 0 0 R/W Screen 2 start address register 0 039FFEE (B) D7 D6 D5 D4 D3 D2 D1 D0 S2ADDR7 S2ADDR6 S2ADDR5 S2ADDR4 S2ADDR3 S2ADDR2 S2ADDR1 S2ADDR0 Screen 2 start address (low-order 8 bits) 0 0 0 0 0 0 0 0 R/W Screen 2 start address register 1 039FFEF (B) D7 D6 D5 D4 D3 D2 D1 D0 S2ADDR15 Screen 2 start address S2ADDR14 (high-order 8 bits) S2ADDR13 S2ADDR12 S2ADDR11 S2ADDR10 S2ADDR9 S2ADDR8 0 0 0 0 0 0 0 0 R/W Screen 1 start address register 2 039FFF0 D7-1 - reserved (B) D0 S1ADDR16 Screen 1 start address (MSB) (for portrait mode; fix at 0 in landscape mode) - 0 - 0 when being read. R/W - Memory 039FFF1 address offset (B) register D7 D6 D5 D4 D3 D2 D1 D0 MADOFS7 Memory address offset MADOFS6 MADOFS5 MADOFS4 MADOFS3 MADOFS2 MADOFS1 MADOFS0 0 0 0 0 0 0 0 0 R/W Screen 1 vertical size register 0 D7 D6 D5 D4 D3 D2 D1 D0 S1VSIZE7 S1VSIZE6 S1VSIZE5 S1VSIZE4 S1VSIZE3 S1VSIZE2 S1VSIZE1 S1VSIZE0 0 0 0 0 0 0 0 0 R/W 039FFF2 (B) B-APPENDIX-46 Screen 1 vertical size (low-order 8 bits) EPSON S1C33L03 FUNCTION PART APPENDIX: I/O MAP A-1 Register name Address Bit Name Screen 1 vertical size register 1 039FFF3 D7-2 - (B) D1 S1VSIZE9 D0 S1VSIZE8 FIFO control register 039FFF4 (B) D7 D6 D5 D4 D3 D2 D1 D0 Function Setting reserved Screen 1 vertical size (high-order 2 bits) - reserved FIFOEO3 FIFO empty offset FIFOEO2 FIFOEO1 FIFOEO0 LCLKSEL2 LCDC clock select LCLKSEL1 LCLKSEL0 - 0 0 - 0 when being read. R/W - Fix at 8 (0b1000) - 0 0 0 0 0 0 0 - 0 when being read. R/W - 0 0 0 0 - 0 when being read. R/W 0 0 0 0 - R/W 0 Input 0 Input 0 Input - 0 0 0 - 0 when being read. R/W R/W R/W 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 R/W 0 0 - 0 0 R/W R/W - 0 when being read. R/W 0 0 0 0 0 0 0 0 R/W LCLKSEL[2:0] 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 LCDC clock BCU_CLK/4 BCU_CLK/3 BCU_CLK/2 BCU_CLK reserved Stop Stop Stop 039FFF5 D7-4 - reserved (B) D3 LUTADDR3 Look-up table address D2 LUTADDR2 D1 LUTADDR1 D0 LUTADDR0 Look-up table data register 039FFF7 (B) reserved - GPIO configuration register 039FFF8 D7-3 - (B) D2 GPIO2C D1 GPIO1C D0 GPIO0C reserved GPIO2 configuration GPIO1 configuration GPIO0 configuration - 1 Output 1 Output 1 Output GPIO status/control register 039FFF9 (B) D7 D6 D5 D4 D3 D2 D1 D0 - GPO6D GPO5D GPO4D GPO3D GPIO2D GPIO1D GPIO0D reserved GPO6 data GPO5 data GPO4 data GPO3 data GPIO2 data GPIO1 data GPIO0 data 1 1 1 1 1 1 1 Scratch pad register 039FFFA (B) D7 D6 D5 D4 D3 D2 D1 D0 SP1A7 SP1A6 SP1A5 SP1A4 SP1A3 SP1A2 SP1A1 SP1A0 Scratch pad Portrait mode register 039FFFB (B) D7 D6 D5-2 D1 D0 PMODEN PMODSEL - PMODCLK1 PMODCLK0 Portrait mode enable Portrait mode select reserved Portrait mode clock select (LCDC clock division ratio) LUTDT3 LUTDT2 LUTDT1 LUTDT0 - Line byte count register for portrait mode 039FFFC (B) D7 D6 D5 D4 D3 D2 D1 D0 - Look-up table data - Division ratio 1: Default mode Division ratio 2: Alternate mode P: Pixel clock, M: Memory clock PMODLBC7 Line byte count PMODLBC6 PMODLBC5 PMODLBC4 PMODLBC3 PMODLBC2 PMODLBC1 PMODLBC0 Remarks - Look-up table address register D7 D6 D5 D4 D3-0 Init. R/W High High High High High High High 1 Portrait 1 Alternate Low Low Low Low Low Low Low 0 Landscape 0 Default - PMODCLK[1:0] Division ratio 1 1 1 P: 1/8, M: 1/8 1 0 P: 1/4, M: 1/4 0 1 P: 1/2, M: 1/2 0 0 P: 1/1, M: 1/1 PMODCLK[1:0] Division ratio 2 1 1 P: 1/8, M: 1/4 1 0 P: 1/4, M: 1/2 0 1 P: 1/2, M: 1/1 0 0 P: 1/2, M: 1/1 R/W - 0 when being read. B-ap S1C33L03 FUNCTION PART EPSON B-APPENDIX-47 APPENDIX: I/O MAP Register name Address Bit Name LCDC 039FFFD system control (B) register D7 D6 D5 D4 D3 D2 D1 D0 VRAMAR VRAMWT2 VRAMWT1 VRAMWT0 EDMAEN BREQEN LCDCST LCDCEC B-APPENDIX-48 Function Setting VRAM area select 1 Area 8 VRAM wait control (number of wait cycles for SRAM) External DMA enable External bus-request enable A0/BSL select Big/little endian select EPSON 1 1 1 1 Init. R/W 0 Area 7 0-7 Enabled Enabled BSL Big endian 0 0 0 0 Disabled Disabled A0 Little endian 0 0 0 0 0 0 0 0 Remarks R/W R/W R/W R/W R/W R/W S1C33L03 FUNCTION PART International Sales Operations AMERICA ASIA EPSON ELECTRONICS AMERICA, INC. EPSON (CHINA) CO., LTD. - HEADQUARTERS - 23F, Beijing Silver Tower 2# North RD DongSanHuan ChaoYang District, Beijing, CHINA Phone: 64106655 Fax: 64107319 150 River Oaks Parkway San Jose, CA 95134, U.S.A. Phone: +1-408-922-0200 Fax: +1-408-922-0238 SHANGHAI BRANCH 7F, High-Tech Bldg., 900, Yishan Road Shanghai 200233, CHINA Phone: 86-21-5423-5577 Fax: 86-21-5423-4677 - SALES OFFICES West 1960 E. Grand Avenue EI Segundo, CA 90245, U.S.A. Phone: +1-310-955-5300 Fax: +1-310-955-5400 Central 101 Virginia Street, Suite 290 Crystal Lake, IL 60014, U.S.A. Phone: +1-815-455-7630 Fax: +1-815-455-7633 EPSON HONG KONG LTD. 20/F., Harbour Centre, 25 Harbour Road Wanchai, Hong Kong Phone: +852-2585-4600 Fax: +852-2827-4346 Telex: 65542 EPSCO HX EPSON TAIWAN TECHNOLOGY & TRADING LTD. Northeast 14F, No. 7, Song Ren Road, Taipei 110 Phone: 02-8786-6688 Fax: 02-8786-6660 301 Edgewater Place, Suite 120 Wakefield, MA 01880, U.S.A. Phone: +1-781-246-3600 Fax: +1-781-246-5443 HSINCHU OFFICE Southeast 3010 Royal Blvd. South, Suite 170 Alpharetta, GA 30005, U.S.A. Phone: +1-877-EEA-0020 Fax: +1-770-777-2637 EUROPE 13F-3, No. 295, Kuang-Fu Road, Sec. 2 HsinChu 300 Phone: 03-573-9900 Fax: 03-573-9169 EPSON SINGAPORE PTE., LTD. No. 1 Temasek Avenue, #36-00 Millenia Tower, SINGAPORE 039192 Phone: +65-6337-7911 Fax: +65-6334-2716 SEIKO EPSON CORPORATION KOREA OFFICE EPSON EUROPE ELECTRONICS GmbH - HEADQUARTERS Riesstrasse 15 80992 Munich, GERMANY Phone: +49-(0)89-14005-0 Fax: +49-(0)89-14005-110 DUSSELDORF BRANCH OFFICE Altstadtstrasse 176 51379 Leverkusen, GERMANY Phone: +49-(0)2171-5045-0 Fax: +49-(0)2171-5045-10 50F, KLI 63 Bldg., 60 Yoido-dong Youngdeungpo-Ku, Seoul, 150-763, KOREA Phone: 02-784-6027 Fax: 02-767-3677 GUMI OFFICE 6F, Good Morning Securities Bldg. 56 Songjeong-Dong, Gumi-City, 730-090, KOREA Phone: 054-454-6027 Fax: 054-454-6093 UK & IRELAND BRANCH OFFICE SEIKO EPSON CORPORATION ELECTRONIC DEVICES MARKETING DIVISION Unit 2.4, Doncastle House, Doncastle Road Bracknell, Berkshire RG12 8PE, ENGLAND Phone: +44-(0)1344-381700 Fax: +44-(0)1344-381701 IC Marketing Department IC Marketing & Engineering Group FRENCH BRANCH OFFICE 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5816 Fax: +81-(0)42-587-5624 1 Avenue de l' Atlantique, LP 915 Les Conquerants Z.A. de Courtaboeuf 2, F-91976 Les Ulis Cedex, FRANCE Phone: +33-(0)1-64862350 Fax: +33-(0)1-64862355 BARCELONA BRANCH OFFICE Barcelona Design Center Edificio Testa, Avda. Alcalde Barrils num. 64-68 E-08190 Sant Cugat del Valles, SPAIN Phone: +34-93-544-2490 Fax: +34-93-544-2491 Scotland Design Center Integration House, The Alba Campus Livingston West Lothian, EH54 7EG, SCOTLAND Phone: +44-1506-605040 Fax: +44-1506-605041 ED International Marketing Department 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5814 Fax: +81-(0)42-587-5117 In pursuit of "Saving" Technology, Epson electronic devices. Our lineup of semiconductors, displays and quartz devices assists in creating the products of our customers' dreams. Epson IS energy savings. S1C33L03 Technical Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epsondevice.com Issue April, 2003 Printed in Japan L B