Technical Manual
CMOS 32-BIT SINGLE CHIP MICROCOMPUTER
S1C33L03 PRODUCT PART
S1C33L03 FUNCTION PART
S1C33L03
MF1574-01
NOTICE
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liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or
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© SEIKO EPSON CORPORATION 2003, All rights reserv ed.
S1C33L03 Technical Manual
This ma nual describes the hardwa re specifications of the Seiko Epson original 32-bit microcomputer S1C33L03.
S1C33L03 PRODUCT PART
Desc ribes the hardware specifications of the S1C33L03 except for details of the peripheral circuits.
S1C33L03 FUNCTION PART
Desc ribes details of all the peripheral circuit blocks for the S1C33 Family microcomputers.
Refer to the "S1C33000 Core CPU Manual" for detai ls of the S1C33000 32-bit RISC CPU.
Configuration of product number
Devices
S1 C 33209 F 00E1
Packing specifications
00 : Besides tape & reel
0A : TCP BL 2 directions
0B : Tape & reel BACK
0C: TCP BR 2 directions
0D: TCP BT 2 directions
0E : TCP BD 2 directions
0F : Tape & reel FRONT
0G: TCP BT 4 directions
0H: TCP BD 4 directions
0J : TCP SL 2 directions
0K : TCP SR 2 directions
0L : Tape & reel LEFT
0M: TCP ST 2 directions
0N: TCP SD 2 directions
0P : TCP ST 4 directions
0Q: TCP SD 4 directions
0R: Tape & reel RIGHT
99 : Specs not fixed
Specification
Package
D: die form; F: QFP
Model number
Model name
C: microcomputer, digital products
Product classification
S1: semiconductor
Development tools
S5U1 C 33000 H2 1
Packing specifications
00: standard packing
Version
1: Version 1
Tool type
Hx : ICE
Dx : Evaluation board
Ex : ROM emulation board
Mx: Emulation memory for external ROM
Tx : A socket for mounting
Cx : Compiler package
Sx : Middleware package
Corresponding model number
33L01: for S1C33L01
Tool classification
C: microcomputer use
Product classification
S5U1: development tool for semiconductor products
00
00
TABLE OF CONTENT S
S1C33L03 TECHNICAL MANUAL EPSON i
S1C33L03 PRODUCT PART
Table of Contents
1Outline.....................................................................................................................................A-1
1.1Features.....................................................................................................................................A-1
1.2Block Diagram...........................................................................................................................A-3
1.3Pin Description ..........................................................................................................................A-4
1.3.1Pin Layout Diagram (plastic package) ......................................................................A-4
1.3.2Pin Functions .............................................................................................................A-5
2Power Supply.......................................................................................................................A-12
2.1Power Supply Pins..................................................................................................................A-12
2.2 Operating Voltage (VDD, V SS).................................................................................................A-12
2.3 Pow er Supply f or I/O Interface (VDDE)....................................................................................A-13
2.4 Power Supply for An alog Cir cuits (AVDDE).............................................................................A-13
3Internal Memory...................................................................................................................A-14
3.1ROM and Boot Address..........................................................................................................A-14
3.2RAM.........................................................................................................................................A-15
4Peripher a l C ir c uits ..............................................................................................................A-16
4.1List of Peripheral Circuits........................................................................................................A-16
4.2I/O Memory Map......................................................................................................................A-17
5Power-Down Control...........................................................................................................A-65
6Basic External Wiring Diagram .........................................................................................A-68
7Precauti ons on Mounting...................................................................................................A-69
8Electrical Characteristics...................................................................................................A-71
8.1Absolute Maximum Rating......................................................................................................A-71
8.2Recommended Operating Conditions ....................................................................................A-72
8.3DC Characteristics ..................................................................................................................A-73
8.4Current Consumption..............................................................................................................A-75
8.5A/D Converter Characteristics................................................................................................A-76
8.6AC Characteristics...................................................................................................................A-78
8.6.1Symbol Descr ipt io n..................................................................................................A -7 8
8.6.2AC Characteristics Measurement Condition...........................................................A-78
8.6.3C33 Block AC Characteristic Tables.......................................................................A-79
8.6.4C33 Block AC Characteristic Timing Charts...........................................................A-87
8.6.5LCD Interface AC Characteristics ...........................................................................A-96
8.7Oscillation Characteristics.................................................................................................... A-107
8.8PLL Characteristics.............................................................................................................. A-108
9Package ..............................................................................................................................A-109
9.1Plastic Package.................................................................................................................... A-109
10 Pad L a y o ut .........................................................................................................................A-110
10.1 Pad Layout Diagram............................................................................................................. A-110
10.2 Pad Coordinate..................................................................................................................... A-111
TABLE OF CONTENT S
ii EPSON S1C33L03 TECHNICAL M ANUAL
Appendix A <Reference> E xternal De vic e Interface T imings.......................................... A-113
A.1DRAM (70ns)........................................................................................................................ A-114
A.2DRAM (60ns)........................................................................................................................ A-117
A.3ROM and Burst ROM........................................................................................................... A-121
A.4SRAM (55ns)........................................................................................................................ A-123
A.5SRAM (70ns)........................................................................................................................ A-125
A.68255A.................................................................................................................................... A-127
Appendix B Pin Characteristics........................................................................................... A-128
TABLE OF CONTENT S
S1C33L03 TECHNICAL MANUAL EPSON iii
S1C33L03 FUNCTION PART
Table of Contents
IOUTLINE
I-1 INTRODUCTION ............................................................................................................ B-I-1-1
I-2 BLOCK DIAGRAM......................................................................................................... B-I-2-1
I-3 LIST OF PINS.................................................................................................................B-I-3-1
List of External I/O Pins...............................................................................................................B-I-3-1
II CORE BLOCK
II-1 INTRODUCTION ........................................................................................................... B-II-1-1
II-2 CPU AND OPERATING MODE ................................................................................... B-II-2-1
CPU ............................................................................................................................................B-II-2-1
Standby Mode.............................................................................................................................B-II-2-2
HALT Mode.....................................................................................................................B-II-2-2
SLEEP Mode ..................................................................................................................B-II-2-2
Notes on Standby Mode.................................................................................................B-II-2-3
Test Mode...................................................................................................................................B-II-2-3
Debug Mode ...............................................................................................................................B-II-2-3
Trap Table...................................................................................................................................B-II-2-4
II-3 INIT I AL R ESET ............................................................................................................. B-II-3-1
Pins for Initial Reset....................................................................................................................B-II-3-1
Cold Start and Hot Start .............................................................................................................B-II-3-1
Power-on Reset..........................................................................................................................B-II-3-2
Reset Pulse.................................................................................................................................B-II-3-2
Boot Address ..............................................................................................................................B-II-3-3
Notes Related to Initial Reset.....................................................................................................B-II-3-3
II-4 BCU (Bus Control Unit)............................................................................................... B-II-4-1
Pin Assignment for External System Interface..........................................................................B-II-4-1
I/O P in List................................................................................................................... ....B-II-4-1
Combination of System Bus Control Signals.................................................................B-II-4-3
Memory Area ..............................................................................................................................B-II-4-4
Memory Map...................................................................................................................B-II-4-4
External Memory Map and Chip Enable........................................................................B-II-4-5
Using Internal Memory on External Memory Area.........................................................B-II-4-7
Exclusive Sig nals fo r Areas............................................................................................B-II -4 -7
Area 10............................................................................................................................B-II-4-8
Area 3..............................................................................................................................B-II-4-9
Setting External Bus Conditions ..............................................................................................B-II-4-10
Setting Dev ic e Type a nd Size......................................................................................B-II -4 -10
Setting SRAM Timing Conditions.................................................................................B-II-4-11
Setting Timing Conditions of Burst ROM.....................................................................B-II-4-12
Bus Operation...........................................................................................................................B-II-4-13
Data Arrangement in Memory ......................................................................................B-II-4-13
Bus Operation of External Memory..............................................................................B-II-4-13
TABLE OF CONTENT S
iv EPSON S1C33L03 TECHNICAL M ANUAL
Bus Clock..................................................................................................................................B-II-4-17
Bus Speed Mode ..........................................................................................................B-II-4-18
Bus Clock Output..........................................................................................................B-II-4-18
Bus Cycles in External System Interface.................................................................................B-II-4-19
SRAM Read Cycles......................................................................................................B-II-4-19
Bus Timing ....................................................................................................................B-II-4-20
SRAM Write Cycles......................................................................................................B-II-4-21
Burst ROM Rea d Cyc le s ..............................................................................................B -II-4 -23
DRAM Direct Interface..............................................................................................................B-II-4-24
Outline of DRAM Interface............................................................................................B-II-4-24
DRAM Setting Conditions.............................................................................................B-II-4-25
DRAM Read/Write Cycles............................................................................................B-II-4-28
DRAM Refresh Cycles..................................................................................................B-II-4-31
Releasing External Bus............................................................................................................B-II-4-32
Power-down Control by External Device.................................................................................B-II-4-33
I/O Memory of BCU ..................................................................................................................B-II-4-34
II-5 ITC (Interrupt Controller).............................................................................................B-II-5-1
Outline of Interrupt Functions.....................................................................................................B-II-5-1
Maskable Interrupts........................................................................................................B-II-5-1
Interrupt Factors and Intelligent DMA............................................................................B-II-5-3
Nonmaskable Interrupt (NMI).........................................................................................B-II-5-3
Interrupt Processing by the CPU....................................................................................B-II-5-3
Clearing Standby Mode by Interrupts.............................................................................B-II-5-3
Trap Table...................................................................................................................................B-II-5-4
Control of Maskable Interrupts...................................................................................................B-II-5-5
Structure of the Interrupt Controller................................................................................B-II-5-5
Processor Status Register (PSR)...................................................................................B-II-5-5
Interrupt Factor Flag and Interrupt Enable Register......................................................B-II-5-6
Interrupt Priority Register and Interrupt Levels..............................................................B-II-5-8
IDMA Invocation .........................................................................................................................B-II-5-9
HSDMA Invocation ...................................................................................................................B-II-5-11
I/O Memory of Interrupt Controller...........................................................................................B-II-5-12
Programming Notes..................................................................................................................B-II-5-25
II-6 CL G (Cl o ck G e n era t o r)................................................................................................B -I I-6-1
Configuration of Clock Generator ..............................................................................................B-II-6-1
I/O Pins of Clock Generator .......................................................................................................B-II-6-2
High-Sp ee d (OS C 3) Osc illa ti on Circuit......................................................................................B -II -6-2
PLL ............................................................................................................................................B-II-6-3
Controlling Oscillation.................................................................................................................B-II-6-3
Setting and Switch in g Ove r th e CPU Operatin g Clo ck.............................................................B -II -6 -4
Power-Control Register Protection Flag....................................................................................B-II-6-5
Operation in Standby Mode .......................................................................................................B-II-6-5
I/O Memory of Clock Generator.................................................................................................B-II-6-6
Programming Notes....................................................................................................................B-II-6-9
II-7 DBG (Debug Unit).........................................................................................................B-II-7-1
Debug Circuit..............................................................................................................................B-II-7-1
I/O Pins of Debug Circuit............................................................................................................B-II-7-1
TABLE OF CONTENT S
S1C33L03 TECHNICAL MANUAL EPSON v
III PERIPHERAL BLOCK
III-1 INTRODUCTION ......................................................................................................... B-III-1-1
III-2 PRESCALER............................................................................................................... B-III-2-1
Configuration of Prescaler.........................................................................................................B-III-2-1
Source Clock .............................................................................................................................B-III-2-1
Selecting Division Ratio and Output Control for Prescaler ......................................................B-III-2-2
Source Clock Output to 8-Bit Programmable Timer.................................................................B-III-2-2
I/O Memory of Prescaler ...........................................................................................................B-III-2-3
Programming Notes...................................................................................................................B-III-2-8
III-3 8-BIT PROGRAMMABLE TIMERS............................................................................ B-III-3-1
Configuration of 8-Bit Programmable Timer.............................................................................B-III-3-1
Output Pins of 8-Bit Programmable Timers..............................................................................B-III-3-1
Uses of 8-Bit Programmable Timers.........................................................................................B-III-3-2
Control and Operation of 8-Bit Programmable Timer...............................................................B-III-3-4
Control of Clock Output.............................................................................................................B-III-3-7
8-Bit Programmable Timer Interrupts and DMA.......................................................................B-III-3-8
I/O Memory of 8-Bit Programmable Timers............................................................................B-III-3-10
Programming Notes.................................................................................................................B-III-3-17
III-4 16-BIT PROGRAMMABLE TIMERS.......................................................................... B-III-4-1
Configuration of 16-Bit Programmable Timer...........................................................................B-III-4-1
I/O Pins of 16-Bit Programmable Timers..................................................................................B-III-4-2
Uses of 16-Bit Programmable Timers.......................................................................................B-III-4-3
Control and Operation of 16-Bit Programmable Timer ............................................................B-III-4-4
Controlling Clock Output ...........................................................................................................B-III-4-7
16-Bit Programmable Timer Interrupts and DMA.....................................................................B-III-4-9
I/O Memory of 16-Bit Programmable Timers..........................................................................B-III-4-12
Programming Notes.................................................................................................................B-III-4-25
III-5 WATCHDOG TIMER................................................................................................... B-III-5-1
Configuration of Watchdog Timer .............................................................................................B-III-5-1
Control of Watchdog Timer .......................................................................................................B-III-5-1
Operation in Standby Modes.....................................................................................................B-III-5-2
I/O Memory of Watchdog Timer................................................................................................B-III-5-3
Programming Notes...................................................................................................................B-III-5-3
III-6 LOW-SPEED (OSC1) OSCILLATION CIRCUIT ....................................................... B-III-6-1
Configuration of Low-Speed (OSC1) Oscillation Circuit ..........................................................B-III-6-1
I/O P in s of L ow-S p ee d (OS C 1) Osc illa ti on Circuit...................................................................B-III-6 -1
Oscillator T yp es.........................................................................................................................B-III-6-2
Controlling Oscillation................................................................................................................B-III-6-3
Switchin g Ove r th e CPU Opera tin g Clo ck................................................................................B -II I-6 -3
Power-Control Register Protection Flag...................................................................................B-III-6-4
Operation in Standby Mode ......................................................................................................B-III-6-4
OSC1 Clock Output to External Devices..................................................................................B-III-6-4
I/O Mem o ry of Low-Sp ee d (OS C 1) Osc illa ti on Circui t.............................................................B-III-6 -5
Programming Notes...................................................................................................................B-III-6-8
TABLE OF CONTENT S
vi EPSON S1C33L03 TECHNICAL M ANUAL
III-7 CLOCK TIMER ............................................................................................................B-III-7-1
Configuration of Clock Timer.....................................................................................................B-III-7-1
Control and Operation of the Clock Timer................................................................................B-III-7-2
Interrupt Function.......................................................................................................................B-III-7-4
Examples of Use of Clock Timer...............................................................................................B-III-7-6
I/O Memory of Clock Timer.......................................................................................................B-III-7-7
Programming Notes.................................................................................................................B-III-7-12
III-8 SERIAL INTERFACE ..................................................................................................B-III-8-1
Configuration of Serial Interfaces..............................................................................................B-III-8-1
Features of Serial Interfaces .........................................................................................B-III-8-1
I/O Pins of Serial Interface.............................................................................................B-III-8-2
Setting Tra ns fe r Mode...................................................................................................B -II I-8 -3
Clock-Synchronized Interface ...................................................................................................B-III-8-4
Outline of Clock-Synchronized Interface.......................................................................B-III-8-4
Setting Clo ck -S yn chro ni ze d Interfa ce...........................................................................B-III-8 -5
Control and Operation of Clock-Synchronized Transfer ..............................................B-III-8-7
Asynchronous Interface...........................................................................................................B-III-8-12
Outline of Asynchronous Interface..............................................................................B-III-8-12
Setting Asy nc hr onou s Inte rfa ce ..................................................................................B -II I-8 -1 3
Control and Operation of Asynchronous Transfer......................................................B-III-8-16
IrDA Interface...........................................................................................................................B-III-8-21
Outline of IrDA Interface..............................................................................................B-III-8-21
Setting Ir DA Inte rfa ce ..................................................................................................B-II I-8 -21
Control and Operation of IrDA Interface .....................................................................B-III-8-23
Serial Interface Interrupts and DMA........................................................................................B-III-8-24
I/O Memory of Serial Interface................................................................................................B-III-8-28
Programming Notes.................................................................................................................B-III-8-46
III-9 INPUT/OUTPUT PORTS.............................................................................................B-III-9-1
Inpu t Por ts (K Ports)..................................................................................................................B-III-9-1
Structure of Input Port....................................................................................................B-III-9-1
Input-Port Pins...............................................................................................................B-III-9-2
Notes on Use .................................................................................................................B-III-9-2
I/O Memory of Input Ports .............................................................................................B-III-9-3
I/O P or ts (P Ports) .....................................................................................................................B-III-9-4
Structure of I/O Port.......................................................................................................B-III-9-4
I/O P or t Pins...................................................................................................................B-III-9-4
I/O C ontr ol R egi s te r and I/O Mode s ..............................................................................B-III-9 -5
I/O Memory of I/O Ports.................................................................................................B-III-9-6
Inpu t In te rru p t ..........................................................................................................................B-III-9-12
Port Input Interrupt.......................................................................................................B-III-9-12
Key Inpu t In te rru p t.......................................................................................................B-II I-9-14
Control R egiste rs o f the Inte rru p t Contr oll er...............................................................B-III-9 -16
I/O Memory for Input Interrupts...................................................................................B-III-9-18
Programming Notes.................................................................................................................B-III-9-25
TABLE OF CONTENT S
S1C33L03 TECHNICAL MANUAL EPSON vii
IV ANALOG BLOCK
IV-1 INTRODUCTION .........................................................................................................B-IV-1-1
IV-2 A/D CONVERTER.......................................................................................................B-IV-2-1
Features and Structure of A/D Converter.................................................................................B-IV-2-1
I/O Pins of A/D Converter..........................................................................................................B-IV-2-2
Setting A/D Conve rt e r ...............................................................................................................B-IV-2-3
Control and Operation of A/D Conversion................................................................................B-IV-2-5
A/D Converter Interrupt and DMA.............................................................................................B-IV-2-7
I/O Memory of A/D Converter....................................................................................................B-IV-2-9
Programming Notes.................................................................................................................B-IV-2-15
VDMA BLOCK
V-1 INTRODUCTION ..........................................................................................................B-V-1-1
V-2 HSDMA (High-Speed DMA) .......................................................................................B-V-2-1
Functional Outline of HSDMA....................................................................................................B-V-2-1
I/O Pins of HSDMA.....................................................................................................................B-V-2-2
Programming Control Information..............................................................................................B-V-2-3
Setting the R egi s te rs in Dual-A d dr es s Mod e .................................................................B -V-2 -3
Setting the R egi s te rs in Sin gle-A d dre s s Mode..............................................................B-V -2 -6
Enabling/Disabling DMA Transfer..............................................................................................B-V-2-7
Trigger F acto r .............................................................................................................................B-V-2-8
Operation of HSDMA..................................................................................................................B-V-2-9
Operation in Dual-Address Mode...................................................................................B-V-2-9
Operation in Single-Address Mode..............................................................................B-V-2-12
Timing Chart..................................................................................................................B-V-2-13
Interrupt Function of HSDMA...................................................................................................B-V-2-15
I/O Memory of HSDMA.............................................................................................................B-V-2-17
Programming Notes..................................................................................................................B-V-2-36
V-3 IDMA (Intelligent DMA)...............................................................................................B-V-3-1
Functional Outline of IDMA ........................................................................................................B-V-3-1
Programming Control Information..............................................................................................B-V-3-1
IDMA Invocation .........................................................................................................................B-V-3-5
Operation of IDMA......................................................................................................................B-V-3-8
Linking.......................................................................................................................................B-V-3-12
Interrupt Function of Intelligent DMA .......................................................................................B-V-3-13
I/O Memory of Intelligent DMA.................................................................................................B-V-3-14
Programming Notes..................................................................................................................B-V-3-17
TABLE OF CONTENT S
viii EPSON S1C33L03 TECHNICAL M ANUAL
VI SDRAM CONTROLLER BLOCK
VI-1 INTRODUCTION......................................................................................................... B-VI-1-1
VI-2 SDRAM INTERFACE ................................................................................................. B-VI-2-1
Outline of SDRAM Interface......................................................................................................B-VI-2-1
SDRAM Controller Blo ck Diagra m............................................................................................ B -VI-2-1
I/O Pins and Connection ...........................................................................................................B-VI-2-2
I/O P in s...........................................................................................................................B-VI-2-2
Connection Exa m ples.................................................................................................... B -V I-2 -2
SDRAM Controller Configuration..............................................................................................B-VI-2-5
Setting PLL .....................................................................................................................B-VI-2-5
BCU Configuration.........................................................................................................B-VI-2-5
SDRAM Setting C ondi tio ns ........................................................................................... B -VI-2 -6
SDRAM Operation...................................................................................................................B-VI-2-12
Synchronous Clock......................................................................................................B-VI-2-12
Power-up and Initi ali za tio n ..........................................................................................B-V I-2 -13
SDRAM Commands ....................................................................................................B-VI-2-14
Burst Read Cyc le.........................................................................................................B-VI-2 -15
Single Read/Single Write.............................................................................................B-VI-2-16
Refresh Mode ..............................................................................................................B-VI-2-17
Power-down Mode.......................................................................................................B-VI-2-19
Bus Release Procedure...............................................................................................B-VI-2-19
I/O Memory of SDRAM Interface ............................................................................................B-VI-2-21
Programming Notes.................................................................................................................B-VI-2-32
Examples of SDRAM Controller Initialization Program..........................................................B-VI-2-33
VII LCD CONTROLLER BLOCK
VII-1 INTRODUCTION........................................................................................................ B-VII-1-1
VII-2 LCD CONTROLLER.................................................................................................. B-VII-2-1
Overview...................................................................................................................................B-VII-2-1
Features........................................................................................................................B-VII-2-1
Block Diagram...............................................................................................................B-VII-2-3
I/O Pins of the LCD Controller..................................................................................................B-VII-2-4
System Settings........................................................................................................................B-VII-2-5
Setting the B CU............................................................................................................B-V II-2-5
Displa y Memo ry............................................................................................................B-VII -2-5
LCD Controll er S et tin g Pro ce du re ................................................................................B-V II-2 -6
Clock .............................................................................................................................B-VII-2-7
Setting the L CD Panel..............................................................................................................B-VII-2-8
Types of Panels............................................................................................................B-VII-2-8
Resolution .....................................................................................................................B-VII-2-8
Displa y Mod e s ..............................................................................................................B-VII-2-9
Look-up Tables.......................................................................................................... B-VII-2-11
Frame Rates .............................................................................................................. B-VII-2-19
Other Settings............................................................................................................ B-VII-2-20
Displa y Con tro l ...................................................................................................................... B-VII-2-21
Controlling LCD Power Up/Down.............................................................................. B-VII-2-21
Reading/Writing Disp la y Dat a ................................................................................... B-VII-2 -22
Setting the D isp la y Sta rt Addre ss ............................................................................. B-V II-2 -22
Split-Screen Display .................................................................................................. B-VII-2-23
TABLE OF CONTENT S
S1C33L03 TECHNICAL MANUAL EPSON ix
Virtual Screen and View Port .................................................................................... B-VII-2-23
Inverting and Blanking the Display............................................................................ B-VII-2-25
Portrait M ode ............................................................................................................. B-V II -2-25
Power Save................................................................................................................ B-VII-2-29
Controlling the GPIO Pins ......................................................................................... B-VII-2-30
I/O Memory of LCD Controller............................................................................................... B-VII-2-31
Programming Notes...............................................................................................................B-VII-2-42
Precautions on Using ICD33................................................................................................. B-VII-2-42
Examples of LCD Controller Setting Program...................................................................... B-VII-2-43
APPENDIX I/O MAP
S1C33L03
PRODUCT PART
1 OUTLINE
S1C33L03 PRODUCT PART EPSON A-1
A-1
1 Outline
The S1C3 3L03 is a Seiko Epson original 32-bit microcomputer with a built-in LCD controller. It features high
speed, low power and low-voltage operation and is most suitable for portable equipment that needs display
function, such as information terminals, E-mail terminals, electronic dictionaries.
The S1C33L03 consists of the S1C33000 32-bit RISC type CPU as the core, a bus control unit, a DMA controller,
an interrupt controller, an LCD controller, an SDRAM controller, timers, serial interface circuits, an A/D converter,
ROM and RAM.
The S1C3 3L03 provides a DSP funct ion, by using the internal MAC (multiplication and accumulation) operation
function with the A/D converter, it makes it possible to design simply speech recognition and voice synthesis
systems.
Table 1.1 Model Lineup
Model Package Internal RAM Internal ROM Data bus I/F
S1C33L0 3F00A 10 0 QFP 20 -144pin 8K by tes Non e CMO S/LVTTL
S1C33L03F00A200 QFP20-144pin
(Pb-free package) 8K by t es Non e CMOS /LVTTL
S1C33L0 3D 00A1 00 C hip 8K by tes Non e CMO S/LVTTL
1.1 Features
Core CPU
Seiko Epson orig ina l 32-bit R IS C CPU S1C33 000 b uil t-in
•Basic instruction set: 105 instructions (16-bit fixed size)
•Sixteen 32-bit g ene ra l-p ur pose register
•32-bit A LU and 8-bit shif ter
•Multiplication/division instructions and MAC (multiplication and accumulation) instruction are available
•20 ns of minimu m instruction execution time at 50 MHz operation
Internal memory
RA M : 8K bytes
Internal peripheral circuits
Oscillation circuit: High-speed (OSC3) oscillation circuit 33 MHz max.
Crystal/ceramic oscillator or external clock input
Low -sp eed (O SC1) oscillation cir cuit 32.768 kHz typ.
Crystal oscillator or external clock input
LC D con troll er: 4 or 8-bit monoch rome/col or LC D interface (based on the S1D1 3705 )
2, 4 or 16-level (1, 2 or 4 bi t-per-pixel) gray-scale display
2, 4, 16 or 256-level (1, 2, 4 or 8 bi t-per-pixel) color display
Resolution exam p les: 640 × 480 pixels with 1-bpp color depth
640 × 240 pixels with 2-bpp color depth
320 × 240 pixels with 4-bpp color depth
240 × 160 pixels with 8-bpp color depth
Timers: 8-bit timer 6 channels
16-bit time r 6 chan ne ls
Watchdog timer (16-b it timer 0's function)
Clock timer 1 channel (with alarm function)
Serial interface: 4 channels (clock-synchronous system, asynchronous system and IrDA
inte rface are sele ctable)
A/D c onverte r: 10 bits × 8 channels
DMA controller: High-speed DMA 4 channels
Intelligent DMA 128 channels
1 OUTLINE
A-2 EPSON S1C33L03 P RODUCT PART
Interrupt controller: Possible to invoke DMA
Input interrupt 10 types (programmable)
DMA controller interrupt 5 types
16-bit programmable timer interrupt 12 types
8-bit programmable timer interrupt 4 types
Serial interfac e in te rrupt 6 type s
A/D c onverte r interrupt 1 type
Clock timer interrupt 1 type
General-purp ose input Shared with the I/O pins for internal peripheral circuits
and output ports: Input port 13 bits
I/O p ort 29 bits
External bus interface
BCU (bus control unit) built-in
•24-bit address bus (i ntern al 2 8-b it p rocessing)
•16-bit data bus
Dat a size is selectable from 8 bits and 16 bits in each area.
•Little-endian memory access; big-endian may be set in each area.
•Memory mapped I/O
•Chip enable and wait control circuits built-in
•DRAM direct in te rfa ce fu nc tion b uil t-i n
Supports fast page mode and EDO page mode.
Suppor ts self-refresh and CAS-before RAS refresh.
•Supports SDRAM.
Supports SD RA M self-refresh.
•Supports burst ROM.
Operating conditions and power consumption
Operating voltage: Core (VDD)1.8 V to 3.6 V
I/O (V DDE)1.8 V to 5.5 V
Operating clock frequency: CPU operating clock frequency
50 MHz max. (core voltage = 3.3 V ±0.3 V)
LCD controller operating clock frequency
25 MHz max. (core voltage = 3.3 V ±0.3 V)
* When the SDRAM controller is used
(core voltage = 3.3 V ±0.3 V and PLL is used),
In x1 speed mode: CP U = Bus = 25 MHz m ax.
In x2 speed mode: CP U = 35 MHz max., Bus = 17.5 M H z ma x.
Operating te m per at ure: -40 to 85°C
Power con sumption: During SLEEP 3.5 µW typ. (3.3 V)
During HALT 100 mW typ. (3.3 V, 50 MHz)
During execution 200 mW typ. (3.3 V, 50 MHz)
Note : The values of powe r consumption during e xecu tion w ere m eas ured w hen a test
program that consisted of 55% load instructions, 23% arithmetic operation
instructions, 1% mac instruction, 12% branch instructions and 9% ext
instruc tio n w as bein g contin uo us l y ex ec uted.
Supply form
QFP20-144pin plastic package, or chip.
1 OUTLINE
S1C33L03 PRODUCT PART EPSON A-3
A-1
1.2 Block Diagram
V
DD
V
SS
V
DDE
A[23:0]
D[15:0]
#RD
#WRL/#WR/#WE
#WRH/#BSH
#HCAS, #LCAS, #RAS[1:0]
#CE10EX, #CE[9:3]
#EMEMRD
#WAIT(P30)
#DRD(P20), #DWE/#SDWE(P21)
#GAAS(P21), #GARD(P31)
#SDCE[1:0]
#SDCAS, #SDRAS
SDA10, SDCKE, HDQM, LDQM
OSC3
OSC4
PLLS[1:0]
PLLC
OSC1
OSC2
FOSC1(P14)
#DMAREQx(K50, K51, K53, K54)
#DMAACKx(P32, P33, P04, P06)
#DMAENDx(P15, P16, P05, P07)
AD0–7(K60–67)
#ADTRG(K52)
AV
DDE
K50–54
K60–67
#RESET
#NMI
#X2SPD
ICEMD
DSIO
EA10MD[1:0]
BCLK
#BUSREQ(P34)
#BUSACK(P35)
#BUSGET(P31)
DST[2:0](P10–12)
DPCO(P13)
DCLK(P14)
T8UFx(P10–13)
SINx(P00, P04, P27, P33)
SOUTx(P01, P05, P26, P16)
#SCLKx(P02, P06, P25, P15)
#SRDYx(P03, P07, P24, P32)
FPDAT[7:4]
FPDAT[3:0]/GPO[6:3]
FPFRAME
FPLINE
FPSHIFT
DRDY(MOD/FPSHIFT2)
LCDPWR
S1C33L03
EXCLx(P10–13, P15, P16)
TMx(P22–27)
16-bit
Programmable
Timer (6 ch.)
P00–07
P10–16
P20–27
P30–35
S1C33000
Bus Control Unit
SDRAM Controller
CPU Core
Interrupt
Controller
Prescaler
OSC3/PLL
OSC1
Clock
Timer
RAM
8KB
I/O Port
Intelligent
DMA (128 ch.)
High-speed
DMA (4 ch.)
8-bit
Programmable
Timer (6 ch.)
Serial Interface
(4 ch.)
A/D Converter
(8 ch.)
Input Port
LCD Controller
Figur e 1. 2.1 S1C33L03 Block Diagram
1 OUTLINE
A-4 EPSON S1C33L03 P RODUCT PART
1.3 Pin D escription
1.3.1 Pin Layout Diagram (plastic package)
QFP20-144pin
73108
37
72
INDEX
361
144
109
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Pin name
P22/TM0
P23/TM1
V
SS
P24/TM2/#SRDY2
P25/TM3/#SCLK2
P26/TM4/SOUT2
P27/TM5/SIN2
V
DD
P07/#SRDY1/#DMAEND3
P06/#SCLK1/#DMAACK3
P05/SOUT1/#DMAEND2
P04/SIN1/#DMAACK2
FPDAT7
FPDAT6
FPDAT5
FPDAT4
FPDAT3/GPO6
FPDAT2/GPO5
FPDAT1/GPO4
FPDAT0/GPO3
V
DDE
DRDY(MOD/FPSHIFT2)
FPFRAME
FPLINE
FPSHIFT
LCDPWR
V
SS
K67/AD7
K66/AD6
K65/AD5
K64/AD4
K63/AD3
K62/AD2
K61/AD1
K60/AD0
AV
DDE
No.
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Pin name
K54/#DMAREQ3
K53/#DMAREQ2
K52/#ADTRG
K51/#DMAREQ1
K50/#DMAREQ0
#WRH/#BSH
#WRL/#WR/#WE
#RD
V
SS
D15
D14
D13
D12
D11
V
DD
D10
D9
D8
D7
D6
D5
D4
V
DDE
D3
D2
D1
D0
#CE8/#RAS1/#CE14/#RAS3/#SDCE1
#CE7/#RAS0/#CE13/#RAS2/#SDCE0
V
SS
OSC2
OSC1
#RESET
P35/#BUSACK/GPIO1
P34/#BUSREQ/#CE6/GPIO0
P33/#DMAACK1/SIN3/SDA10
No.
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
Pin name
P32/#DMAACK0/#SRDY3/HDQM
P31/#BUSGET/#GARD/GPIO2
P30/#WAIT/#CE4&5
#LCAS/#SDRAS
#HCAS/#SDCAS
V
DD
P21/#DWE/#GAAS/#SDWE
P20/#DRD/SDCKE
BCLK/SDCLK
V
SS
P16/EXCL5/#DMAEND1/SOUT3
P15/EXCL4/#DMAEND0/#SCLK3/LDQM
A0/#BSL
A1/SDA0
A2/SDA1
A3/SDA2
A4/SDA3
A5/SDA4
V
DDE
A6/SDA5
A7/SDA6
A8/SDA7
A9/SDA8
A10/SDA9
A11
V
SS
A12/SDA11
A13/SDA12
A14/SDBA0
A15/SDBA1
A16
A17
V
SS
A18
A19
A20
No.
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
Pin name
A21
A22
A23
PLLS1
PLLS0
V
SS
PLLC
V
SS
DSIO
P14/FOSC1/DCLK
P13/EXCL3/T8UF3/DPCO
P12/EXCL2/T8UF2/DST2
P11/EXCL1/T8UF1/DST1
P10/EXCL0/T8UF0/DST0
EA10MD1
EA10MD0
ICEMD
#EMEMRD
V
DD
OSC4
OSC3
#NMI
#CE9/#CE17/#CE17&18
V
DDE
#CE5/#CE15/#CE15&16
N.C.
#CE3
V
SS
#CE10EX/#CE9&10EX
#CE6/#CE7&8
#CE4/#CE11/#CE11&12
#X2SPD
P03/#SRDY0
P02/#SCLK0
P01/SOUT0
P00/SIN0
Figur e 1. 3.1 Pin Layout Diagram (QFP20-144pin)
1 OUTLINE
S1C33L03 PRODUCT PART EPSON A-5
A-1
1.3.2 Pin Functions
Table 1.3.1 List of Pins for Power Supply System
Pin name Pin No. I/O Pull-up Function
VDD 8,51,78,127 – – Power supply (+) for the internal logic
VSS 3,27,45,66,
82,98,105,
114,116,136
––Power supply (-); GND
VDDE 21,59,91,132 – – P ower supply (+) for the I/O block
AVDDE 36 – – An alog system power supply (+); AVDDE = VDDE
Table 1.3.2 List of Pins for External Bus Interface Signals
Pin name Pin No. I/O Pull-up Function
A0
#BSL 85 O – A 0: Address bus (A0) when SBUSST(D3/0x4812E) = "0" (default)
#BSL: Bus strobe (low byte) signal when SBUSST(D3/0x4812E) = "1"
A[10:1]
SDA[9:0] 85–90,92–96 O–A[10:1]: Address bus (A1–A10)
SDA[9:0]: SDRAM address bus (SDA0–SDA9)
A11 97 O – Address bus (A11)
A[13:12]
SDA[12:11] 99,100 O – A[13:12]: Address bus (A12–A13)
SDA[12:11]: SDRAM address bus (SDA11–SDA12)
A[15:14]
SDBA[1:0] 101,102 O – A [15:14]: Address bus (A14–A15)
SDBA[1:0]: SDRAM bank select (SDBA0–SDBA1)
A[23:16] 103,104,
106–111 O–Address bus (A16–A23)
D[15:0] 46–50,52–58,
60–63 I/O – Data bus (D0–D15)
#CE10EX
#CE9&10EX 137 O – Area 10 chip enable for external memory
* When CEFUNC[1:0] = "1x", this pin outputs #CE9+#CE10EX signal.
#CE9
#CE17
#CE17&18
131 O – #CE9: Area 9 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "00" (default)
#CE17: Area 17 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "01"
* When CEFUNC[1:0] = "1x", this pin outputs #CE17+#CE18 signal.
#CE8
#RAS1
#CE14
#RAS3
#SDCE1
64 O – #CE8: Area 8 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "00",
A8DRA(D8/0x48128) = "0" and SDRPC1(D2/0x39FFC0) = "0" (default)
#RAS1: Area 8 DRAM row strobe when CEFUNC[1:0](D[A:9]/0x48130) = "00",
A8DRA(D8/0x48128) = "1" and SDRPC1(D2/0x39FFC0) = "0"
#CE14: Area 14 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "01" or "1x",
A14DRA(D8/0x48122) = "0" and SDRPC1(D2/0x39FFC0) = "0"
#RAS3: Area 14 DRAM row strobe when CEFUNC[1:0](D[A:9]/0x48130) = "01" or
"1x", A14DRA(D8/0x48122) = "1" and SDRPC1(D2/0x39FFC0) = "0"
#SDCE1: SDRAM chip enable 1 when SDRPC1(D2/0x39FFC0) = "1" and
SDRENA(D7/0x39FFC1) = "1"
#CE7
#RAS0
#CE13
#RAS2
#SDCE0
65 O – #CE7: Area 7 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "00",
A7DRA(D7/0x48128) = "0" and SDRPC0(D3/0x39FFC0) = "0" (default)
#RAS0: Area 7 DRAM row strobe when CEFUNC[1:0](D[A:9]/0x48130) = "00",
A7DRA(D7/0x48128) = "1" and SDRPC0(D3/0x39FFC0) = "0"
#CE13: Area 13 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "01" or "1x",
A13DRA(D7/0x48122) = "0" and SDRPC0(D3/0x39FFC0) = "0"
#RAS2: Area 13 DRAM row strobe when CEFUNC[1:0](D[A:9]/0x48130) = "01" or
"1x", A13DRA(D7/0x48122) = "1" and SDRPC0(D3/0x39FFC0) = "0"
#SDCE0: SDRAM chip enable 0 when SDRPC0(D3/0x39FFC0) = "1" and
SDRENA(D7/0x39FFC1) = "1"
#CE6
#CE7&8 138 O – Area 6 chip enable
* When CEFUNC[1:0] = "1x", this pin outputs #CE7+#CE8 signal.
#CE5
#CE15
#CE15&16
133 O – #CE5: Area 5 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "00" (default)
#CE15: Area 15 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "01"
* When CEFUNC[1:0] = "1x", this pin outputs #CE15+#CE16 signal.
#CE4
#CE11
#CE11&12
139 O – #CE4: Area 4 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "00" (default)
#CE11: Area 11 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "01"
* When CEFUNC[1:0] = "1x", this pin outputs #CE11+#CE12 signal.
#CE3 135 O – Area 3 chip enable
#RD 44 O – Read signal
#EMEMRD 126 O – Read signal for internal ROM emulation memory
1 OUTLINE
A-6 EPSON S1C33L03 P RODUCT PART
Pin name Pin No. I/O Pull-up Function
#WRL
#WR
#WE
43 O – #WRL: Write (low byte) signal when SBUSST(D3/0x4812E) = "0" (default)
#WR: Write signal when SBUSST(D3/0x4812E) = "1"
#WE: DRAM write signal
#WRH
#BSH 42 O – #WRH: Write (high byte) signal when SBUSST(D3/0x4812E) = "0" (default)
#BSH: Bus strobe (high byte) signal when SBUSST(D3/0x4812E) = "1"
#HCAS
#SDCAS 77 O – #HCAS: DRAM column address strobe (high byte) signal when
SDRENA(D7/0x39FFC1) = "0" (default)
#SDCAS: SDRAM column address strobe when SDRENA(D7/0x39FFC1) = "1"
#LCAS
#SDRAS 76 O – #LCAS: DRAM column address strobe (low byte) signal when
SDRENA(D7/0x39FFC1) = "0" (default)
#SDRAS: SDRAM row address strobe when SDRENA(D7/0x39FFC1) = "1"
BCLK
SDCLK 81 O – BCLK: Bus clock output when SDRENA(D7/0x39FFC1) = "0" (default)
SDCLK: SDRAM clock output when SDRENA(D7/0x39FFC1) = "1"
P34
#BUSREQ
#CE6
GPIO0
71 I/O – P34: I/O port when CFP34(D4/0x402DC) = "0" (default)
#BUSREQ: Bus release request input when CFP34(D4/0x402DC) = "1"
#CE6: Area 6 chip enable when CFP34(D4/0x402DC) = "1" and
IOC34(D4/0x402DE) = "1"
GPIO0: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and
BREQEN(D2/0x39FFFD) = "0"
P35
#BUSACK
GPIO1
70 I/O – P35: I/O port when CFP35(D5/0x402DC) = "0" (default)
#BUSACK: Bus acknowledge output when CFP35(D5/0x402DC) = "1" and
CFP34(D4/0x402DC) = "1"
GPIO1: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and
BREQEN(D2/0x39FFFD) = "0"
P30
#WAIT
#CE4&5
75 I/O – P30: I/O port when CFP30(D0/0x402DC) = "0" (default)
#WAIT: Wait cycle request input when CFP30(D0/0x402DC) = "1"
#CE4&5: Areas 4&5 chip enable when CFP30(D0/0x402DC) = "1" and
IOC30(D0/0x402DE) = "1"
P20
#DRD
SDCKE
80 I/O – P20: I/O port when CFP20(D0/0x402D8) = "0" and SDRENA(D7/0x39FFC1) =
"0" (default)
#DRD: DRAM read signal output for successive RAS mode when
CFP20(D0/0x402D8) = "1" and SDRENA(D7/0x39FFC1) = "0"
SDCKE: SDRAM clock enable signal when SDRENA(D7/0x39FFC1) = "1"
P21
#DWE
#GAAS
#SDWE
79 I/O – P21: I/O port when CFP21(D1/0x402D8) = "0", CFEX2(D2/0x402DF) = "0" and
SDRENA(D7/0x39FFC1) = "0" (default)
#DWE: DRAM write signal output for successive RAS mode when
CFP21(D1/0x402D8) = "1", CFEX2(D2/0x402DF) = "0" and
SDRENA(D7/0x39FFC1) = "0"
#GAAS: Area address strobe output for GA when CFEX2(D2/0x402DF) = "1" and
SDRENA(D7/0x39FFC1) = "0"
#SDWE: SDRAM write signal when SDRENA(D7/0x39FFC1) = "1"
P31
#BUSGET
#GARD
GPIO2
74 I/O – P31: I/O port when CFP31(D1/0x402DC) = "0" and CFEX3(D3/0x402DF) = "0"
(default)
#BUSGET: Bus status monitor signal output for bus release request when
CFP31(D1/0x402DC) = "1" and CFEX3(D3/0x402DF) = "0"
#GARD: Area read signal output for GA when CFEX3(D3/0x402DF) = "1"
GPIO2: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and
BREQEN(D2/0x39FFFD) = "0"
EA10MD1 123 I Pull-up Area 10 boot mode selection
EA10MD1 EA10MD0 Mode
EA10MD0 124 I – 1 1 External ROM mode
10Internal ROM mode
1 OUTLINE
S1C33L03 PRODUCT PART EPSON A-7
A-1
Table 1.3.3 List of Pins for HSDMA Control Signals
Pin name Pin No. I/ O Pull-up Function
K50
#DMAREQ0 41 I Pull-up K50: Input port when CFK50(D0/0x402C0) = "0" (default)
#DMAREQ0: HSDMA Ch. 0 request input when CFK50(D0/0x402C0) = "1"
K51
#DMAREQ1 40 I Pull-up K51: Input port when CFK51(D1/0x402C0) = "0" (default)
#DMAREQ1: HSDMA Ch. 1 request input when CFK51(D1/0x402C0) = "1"
K53
#DMAREQ2 38 I Pull-up K53: Input port when CFK53(D3/0x402C0) = "0" (default)
#DMAREQ2: HSDMA Ch. 2 request input when CFK53(D3/0x402C0) = "1"
K54
#DMAREQ3 37 I Pull-up K54: Input port when CFK54(D4/0x402C0) = "0" (default)
#DMAREQ3: HSDMA Ch. 3 request input when CFK54(D4/0x402C0) = "1"
P32
#DMAACK0
#SRDY3
HDQM
73 I/O – P32: I/O port when CFP32(D2/0x402DC) = "0" and SDRENA(D7/0x39FFC1) = "0"
(default)
#DMAACK0: HSDMA Ch. 0 acknowledge output when CFP32(D2/0x402DC) = "1" and
SDRENA(D7/0x39FFC1) = "0"
#SRDY3: Serial I/F Ch. 3 ready signal input/output when SSRDY3(D3/0x402D7) =
"1", CFP32(D2/0x402DC) = "0" and SDRENA(D7/0x39FFC1) = "0"
HDQM: SDRAM data (high byte) input/output mask signal when
SDRENA(D7/0x39FFC1) = "1"
P33
#DMAACK1
SIN3
SDA10
72 I/O – P33: I/O port when CFP33(D3/0x402DC) = "0" and SDRENA(D7/0x39FFC1) = "0"
(default)
#DMAACK1: HSDMA Ch. 1 acknowledge output when CFP33(D3/0x402DC) = "1" and
SDRENA(D7/0x39FFC1) = "0"
SIN3:Serial I/F Ch. 3 data input when SSIN3(D0/0x402D7) = "1",
CFP33(D3/0x402DC) = "0" and SDRENA(D7/0x39FFC1) = "0"
SDA10: SDRAM address bus bit 10 when SDRENA(D7/0x39FFC1) = "1"
P04
SIN1
#DMAACK2
12 I/O – P04: I/O port when CFP04(D4/0x402D0) = "0" and CFEX4(D4/0x402DF) = "0"
(default)
SIN1:Serial I/F Ch. 1 data input when CFP04(D4/0x402D0) = "1" and
CFEX4(D4/0x402DF) = "0"
#DMAACK2: HSDMA Ch. 2 acknowledge output when CFEX4(D4/0x402DF) = "1"
P06
#SCLK1
#DMAACK3
10 I/O – P06: I/O port when CFP06(D6/0x402D0) = "0" and CFEX6(D6/0x402DF) = "0"
(default)
#SCLK1: Serial I/F Ch. 1 clock input/output when CFP06(D6/0x402D0) = "1" and
CFEX6(D6/0x402DF) = "0"
#DMAACK3: HSDMA Ch. 3 acknowledge output when CFEX6(D6/0x402DF) = "1"
P15
EXCL4
#DMAEND0
#SCLK3
LDQM
84 I/O – P15: I/O port when CFP15(D5/0x402D4) = "0" and SDRENA(D7/0x39FFC1) = "0"
(default)
EXCL4: 16-bit timer 4 event counter input when CFP15(D5/0x402D4) = "1",
IOC15(D5/0x402D6) = "0" and SDRENA(D7/0x39FFC1) = "0"
#DMAEND0: HSDMA Ch. 0 end-of-transfer signal output when CFP15(D5/0x402D4) =
"1", IOC15(D5/0x402D6) = "1" and SDRENA(D7/0x39FFC1) = "0"
#SCLK3: Serial I/F Ch. 3 clock input/output when SSCLK3(D2/0x402D7) = "1",
CFP15(D5/0x402D4) = "0" and SDRENA(D7/0x39FFC1) = "0"
LDQM: SDRAM data (low byte) input/output mask signal when
SDRENA(D7/0x39FFC1) = "1"
P16
EXCL5
#DMAEND1
SOUT3
83 I/O – P16: I/O port when CFP16(D6/0x402D4) = "0" (default)
EXCL5: 16-bit timer 5 event counter input when CFP16(D6/0x402D4) = "1" and
IOC16(D6/0x402D6) = "0"
#DMAEND1: HSDMA Ch. 1 end-of-transfer signal output when CFP16(D6/0x402D4) = "1"
and IOC16(D6/0x402D6) = "1"
SOUT3: Serial I/F Ch. 3 data output when SSOUT3(D1/0x402D7) = "1" and
CFP16(D6/0x402D4) = "0"
P05
SOUT1
#DMAEND2
11 I/O – P05: I/O port when CFP05(D5/0x402D0) = "0" and CFEX5(D5/0x402DF) = "0"
(default)
SOUT1: Serial I/F Ch. 1 data output when CFP05(D5/0x402D0) = "1" and
CFEX5(D5/0x402DF) = "0"
#DMAEND2: HSDMA Ch. 2 end-of-transfer signal output when CFEX5(D5/0x402DF) = "1"
P07
#SRDY1
#DMAEND3
9I/O – P07: I/O port when CFP07(D7/0x402D0) = "0" and CFEX7(D7/0x402DF) = "0"
(default)
#SRDY1: Serial I/F Ch. 1 ready signal output when CFP07(D7/0x402D0) = "1" and
CFEX5(D5/0x402DF) = "0"
#DMAEND3: HSDMA Ch. 3 end-of-transfer signal output when CFEX7(D7/0x402DF) = "1"
1 OUTLINE
A-8 EPSON S1C33L03 P RODUCT PART
Table 1.3.4 List of Pins for Internal Peripheral Circuits
Pin name Pin No. I/O Pull-up Function
K50
#DMAREQ0 41 I Pull-up K50: Input port when CFK50(D0/0x402C0) = "0" (default)
#DMAREQ0: HSDMA Ch. 0 request input when CFK50(D0/0x402C0) = "1"
K51
#DMAREQ1 40 I Pull-up K51: Input port when CFK51(D1/0x402C0) = "0" (default)
#DMAREQ1: HSDMA Ch. 1 request input when CFK51(D1/0x402C0) = "1"
K52
#ADTRG 39 I Pull-up K52: Input port when CFK52(D2/0x402C0) = "0" (default)
#ADTRG: A/D converter trigger input when CFK52(D2/0x402C0) = "1"
K53
#DMAREQ2 38 I Pull-up K53: Input port when CFK53(D3/0x402C0) = "0" (default)
#DMAREQ2: HSDMA Ch. 2 request input when CFK53(D3/0x402C0) = "1"
K54
#DMAREQ3 37 I Pull-up K54: Input port when CFK54(D4/0x402C0) = "0" (default)
#DMAREQ3: HSDMA Ch. 3 request input when CFK54(D4/0x402C0) = "1"
K60
AD0 35 I – K60: Input port when CFK60(D0/0x402C3) = "0" (default)
AD0: A/D converter Ch. 0 input when CFK60(D0/0x402C3) = "1"
K61
AD1 34 I – K61: Input port when CFK61(D1/0x402C3) = "0" (default)
AD1: A/D converter Ch. 1 input when CFK61(D1/0x402C3) = "1"
K62
AD2 33 I – K62: Input port when CFK62(D2/0x402C3) = "0" (default)
AD2: A/D converter Ch. 2 input when CFK62(D2/0x402C3) = "1"
K63
AD3 32 I – K63: Input port when CFK63(D3/0x402C3) = "0" (default)
AD3: A/D converter Ch. 3 input when CFK63(D3/0x402C3) = "1"
K64
AD4 31 I – K64: Input port when CFK64(D4/0x402C3) = "0" (default)
AD4: A/D converter Ch. 4 input when CFK64(D4/0x402C3) = "1"
K65
AD5 30 I – K65: Input port when CFK65(D5/0x402C3) = "0" (default)
AD5: A/D converter Ch. 5 input when CFK65(D5/0x402C3) = "1"
K66
AD6 29 I – K66: Input port when CFK66(D6/0x402C3) = "0" (default)
AD6: A/D converter Ch. 6 input when CFK66(D6/0x402C3) = "1"
K67
AD7 28 I – K67: Input port when CFK67(D7/0x402C3) = "0" (default)
AD7: A/D converter Ch. 7 input when CFK67(D7/0x402C3) = "1"
P00
SIN0 144 I/O – P00: I/O port when CFP00(D0/0x402D0) = "0" (default)
SIN0:Serial I/F Ch. 0 data input when CFP00(D0/0x402D0) = "1"
P01
SOUT0 143 I/O – P01: I/O port when CFP01(D1/0x402D0) = "0" (default)
SOUT0: Serial I/F Ch. 0 data output when CFP01(D1/0x402D0) = "1"
P02
#SCLK0 142 I/O – P02: I/O port when CFP02(D2/0x402D0) = "0" (default)
#SCLK0: Serial I/F Ch. 0 clock input/output when CFP02(D2/0x402D0) = "1"
P03
#SRDY0 141 I/O – P03: I/O port when CFP03(D3/0x402D0) = "0" (default)
#SRDY0: Serial I/F Ch. 0 ready signal input/output when CFP03(D3/0x402D0) = "1"
P04
SIN1
#DMAACK2
12 I/O – P04: I/O port when CFP04(D4/0x402D0) = "0" and CFEX4(D4/0x402DF) = "0"
(default)
SIN1:Serial I/F Ch. 1 data input when CFP04(D4/0x402D0) = "1" and
CFEX4(D4/0x402DF) = "0"
#DMAACK2: HSDMA Ch. 2 acknowledge output when CFEX4(D4/0x402DF) = "1"
P05
SOUT1
#DMAEND2
11 I/O – P05: I/O port when CFP05(D5/0x402D0) = "0" and CFEX5(D5/0x402DF) = "0"
(default)
SOUT1: Serial I/F Ch. 1 data output when CFP05(D5/0x402D0) = "1" and
CFEX5(D5/0x402DF) = "0"
#DMAEND2: HSDMA Ch. 2 end-of-transfer signal output when
CFEX5(D5/0x402DF) = "1"
P06
#SCLK1
#DMAACK3
10 I/O – P06: I/O port when CFP06(D6/0x402D0) = "0" and CFEX6(D6/0x402DF) = "0"
(default)
#SCLK1: Serial I/F Ch. 1 clock input/output when CFP06(D6/0x402D0) = "1" and
CFEX6(D6/0x402DF) = "0"
#DMAACK3: HSDMA Ch. 3 acknowledge output when CFEX6(D6/0x402DF) = "1"
P07
#SRDY1
#DMAEND3
9I/O – P07: I/O port when CFP07(D7/0x402D0) = "0" and CFEX7(D7/0x402DF) = "0"
(default)
#SRDY1: Serial I/F Ch. 1 ready signal output when CFP07(D7/0x402D0) = "1" and
CFEX5(D5/0x402DF) = "0"
#DMAEND3: HSDMA Ch. 3 end-of-transfer signal output when
CFEX7(D7/0x402DF) = "1"
P10
EXCL0
T8UF0
DST0
122 I/O – P10: I/O port when CFP10(D0/0x402D4) = "0" and CFEX1(D1/0x402DF) = "0"
EXCL0: 16-bit timer 0 event counter input when CFP10(D0/0x402D4) = "1",
IOC10(D0/0x402D6) = "0" and CFEX1(D1/0x402DF) = "0"
T8UF0: 8-bit timer 0 output when CFP10(D0/0x402D4) = "1", IOC10(D0/0x402D6)
= "1" and CFEX1(D1/0x402DF) = "0"
DST0:DST0 signal output when CFEX1(D1/0x402DF) = "1" (default)
1 OUTLINE
S1C33L03 PRODUCT PART EPSON A-9
A-1
Pin name Pin No. I/O Pull-up Function
P11
EXCL1
T8UF1
DST1
121 I/O – P11: I/O port when CFP11(D1/0x402D4) = "0" and CFEX1(D1/0x402DF) = "0"
EXCL1: 16-bit timer 1 event counter input when CFP11(D1/0x402D4) = "1",
IOC11(D1/0x402D6) = "0" and CFEX1(D1/0x402DF) = "0"
T8UF1: 8-bit timer 1 output when CFP11(D1/0x402D4) = "1", IOC11(D1/0x402D6)
= "1" and CFEX1(D1/0x402DF) = "0"
DST1:DST1 signal output when CFEX1(D1/0x402DF) = "1" (default)
P12
EXCL2
T8UF2
DST2
120 I/O – P12: I/O port when CFP12(D2/0x402D4) = "0" and CFEX0(D0/0x402DF) = "0"
EXCL2: 16-bit timer 2 event counter input when CFP12(D2/0x402D4) = "1",
IOC12(D2/0x402D6) = "0" and CFEX0(D0/0x402DF) = "0"
T8UF2: 8-bit timer 2 output when CFP12(D2/0x402D4) = "1", IOC12(D2/0x402D6)
= "1" and CFEX0(D0/0x402DF) = "0"
DST2:DST2 signal output when CFEX0(D0/0x402DF) = "1" (default)
P13
EXCL3
T8UF3
DPCO
119 I/O – P13: I/O port when CFP13(D3/0x402D4) = "0" and CFEX1(D1/0x402DF) = "0"
EXCL3: 16-bit timer 3 event counter input when CFP13(D3/0x402D4) = "1",
IOC13(D3/0x402D6) = "0" and CFEX1(D1/0x402DF) = "0"
T8UF3: 8-bit timer 3 output when CFP13(D3/0x402D4) = "1", IOC13(D3/0x402D6)
= "1" and CFEX1(D1/0x402DF) = "0"
DPCO:DPCO signal output when CFEX1(D1/0x402DF) = "1" (default)
P14
FOSC1
DCLK
118 I/O – P14: I/O port when CFP14(D4/0x402D4) = "0" and CFEX0(D0/0x402DF) = "0"
FOSC1: OSC1 clock output when CFP14(D4/0x402D4) = "1" and
CFEX0(D0/0x402DF) = "0"
DCLK: DCLK signal output when CFEX0(D0/0x402DF) = "1" (default)
P15
EXCL4
#DMAEND0
#SCLK3
LDQM
84 I/O – P15: I/O port when CFP15(D5/0x402D4) = "0" and SDRENA(D7/0x39FFC1)
= "0" (default)
EXCL4: 16-bit timer 4 event counter input when CFP15(D5/0x402D4) = "1",
IOC15(D5/0x402D6) = "0" and SDRENA(D7/0x39FFC1) = "0"
#DMAEND0: HSDMA Ch. 0 end-of-transfer signal output when CFP15(D5/0x402D4)
= "1", IOC15(D5/0x402D6) = "1" and SDRENA(D7/0x39FFC1) = "0"
#SCLK3: Serial I/F Ch. 3 clock input/output when SSCLK3(D2/0x402D7) = "1",
CFP15(D5/0x402D4) = "0" and SDRENA(D7/0x39FFC1) = "0"
LDQM: SDRAM data (low byte) input/output mask signal when
SDRENA(D7/0x39FFC1) = "1"
P16
EXCL5
#DMAEND1
SOUT3
83 I/O – P16: I/O port when CFP16(D6/0x402D4) = "0" (default)
EXCL5: 16-bit timer 5 event counter input when CFP16(D6/0x402D4) = "1" and
IOC16(D6/0x402D6) = "0"
#DMAEND1: HSDMA Ch. 1 end-of-transfer signal output when CFP16(D6/0x402D4) =
"1" and IOC16(D6/0x402D6) = "1"
SOUT3: Serial I/F Ch. 3 data output when SSOUT3(D1/0x402D7) = "1" and
CFP16(D6/0x402D4) = "0"
P20
#DRD
SDCKE
80 I/O – P20: I/O port when CFP20(D0/0x402D8) = "0" and SDRENA(D7/0x39FFC1)
= "0" (default)
#DRD: DRAM read signal output for successive RAS mode when
CFP20(D0/0x402D8) = "1" and SDRENA(D7/0x39FFC1) = "0"
SDCKE: SDRAM clock enable signal when SDRENA(D7/0x39FFC1) = "1"
P21
#DWE
#GAAS
#SDWE
79 I/O – P21: I/O port when CFP21(D1/0x402D8) = "0", CFEX2(D2/0x402DF) = "0" and
SDRENA(D7/0x39FFC1) = "0" (default)
#DWE: DRAM write signal output for successive RAS mode when
CFP21(D1/0x402D8) = "1", CFEX2(D2/0x402DF) = "0" and
SDRENA(D7/0x39FFC1) = "0"
#GAAS: Area address strobe output for GA when CFEX2(D2/0x402DF) = "1" and
SDRENA(D7/0x39FFC1) = "0"
#SDWE: SDRAM write signal when SDRENA(D7/0x39FFC1) = "1"
P22
TM0 1I/O – P22: I/O port when CFP22(D2/0x402D8) = "0" (default)
TM0: 16-bit timer 0 output when CFP22(D2/0x402D8) = "1"
P23
TM1 2I/O – P23: I/O port when CFP23(D3/0x402D8) = "0" (default)
TM1: 16-bit timer 1 output when CFP23(D3/0x402D8) = "1"
P24
TM2
#SRDY2
4I/O – P24: I/O port when CFP24(D4/0x402D8) = "0" (default)
TM2: 16-bit timer 2 output when CFP24(D4/0x402D8) = "1"
#SRDY2: Serial I/F Ch. 2 ready signal input/output when SSRDY2(D3/0x402DB) = "1"
and CFP24(D4/0x402D8) = "0"
P25
TM3
#SCLK2
5I/O – P25: I/O port when CFP25(D5/0x402D8) = "0" (default)
TM3: 16-bit timer 3 output when CFP25(D5/0x402D8) = "1"
#SCLK2: Serial I/F Ch. 2 clock input/output when SSCLK2(D2/0x402DB) = "1" and
CFP25(D5/0x402D8) = "0"
1 OUTLINE
A-10 EPSON S1C33L03 PRODUCT PART
Pin name Pin No. I/O Pull-up Function
P26
TM4
SOUT2
6I/O – P26: I/O port when CFP26(D6/0x402D8) = "0" (default)
TM4: 16-bit timer 4 output when CFP26(D6/0x402D8) = "1"
SOUT2: Serial I/F Ch. 2 data output when SSOUT2(D1/0x402DB) = "1" and
CFP26(D6/0x402D8) = "0"
P27
TM5
SIN2
7I/O – P27: I/O port when CFP27(D7/0x402D8) = "0" (default)
TM5: 16-bit timer 5 output when CFP27(D7/0x402D8) = "1"
SIN2:Serial I/F Ch. 2 data input when SSIN2(D0/0x402DB) = "1" and
CFP27(D7/0x402D8) = "0"
P30
#WAIT
#CE4&5
75 I/O – P30: I/O port when CFP30(D0/0x402DC) = "0" (default)
#WAIT: Wait cycle request input when CFP30(D0/0x402DC) = "1"
#CE4&5: Areas 4&5 chip enable when CFP30(D0/0x402DC) = "1" and
IOC30(D0/0x402DE) = "1"
P31
#BUSGET
#GARD
GPIO2
74 I/O – P31: I/O port when CFP31(D1/0x402DC) = "0" and CFEX3(D3/0x402DF) = "0"
(default)
#BUSGET: Bus status monitor signal output for bus release request when
CFP31(D1/0x402DC) = "1" and CFEX3(D3/0x402DF) = "0"
#GARD: Area read signal output for GA when CFEX3(D3/0x402DF) = "1"
GPIO2: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and
BREQEN(D2/0x39FFFD) = "0"
P32
#DMAACK0
#SRDY3
HDQM
73 I/O – P32: I/O port when CFP32(D2/0x402DC) = "0" and SDRENA(D7/0x39FFC1)
= "0" (default)
#DMAACK0: HSDMA Ch. 0 acknowledge output when CFP32(D2/0x402DC) = "1" and
SDRENA(D7/0x39FFC1) = "0"
#SRDY3: Serial I/F Ch. 3 ready signal input/output when SSRDY3(D3/0x402D7) =
"1", CFP32(D2/0x402DC) = "0" and SDRENA(D7/0x39FFC1) = "0"
HDQM: SDRAM data (high byte) input/output mask signal when
SDRENA(D7/0x39FFC1) = "1"
P33
#DMAACK1
SIN3
SDA10
72 I/O – P33: I/O port when CFP33(D3/0x402DC) = "0" and SDRENA(D7/0x39FFC1)
= "0" (default)
#DMAACK1: HSDMA Ch. 1 acknowledge output when CFP33(D3/0x402DC) = "1" and
SDRENA(D7/0x39FFC1) = "0"
SIN3:Serial I/F Ch. 3 data input when SSIN3(D0/0x402D7) = "1",
CFP33(D3/0x402DC) = "0" and SDRENA(D7/0x39FFC1) = "0"
SDA10: SDRAM address bus bit 10 when SDRENA(D7/0x39FFC1) = "1"
P34
#BUSREQ
#CE6
GPIO0
71 I/O – P34: I/O port when CFP34(D4/0x402DC) = "0" (default)
#BUSREQ: Bus release request input when CFP34(D4/0x402DC) = "1"
#CE6: Area 6 chip enable when CFP34(D4/0x402DC) = "1" and
IOC34(D4/0x402DE) = "1"
GPIO0: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and
BREQEN(D2/0x39FFFD) = "0"
P35
#BUSACK
GPIO1
70 I/O – P35: I/O port when CFP35(D5/0x402DC) = "0" (default)
#BUSACK: Bus acknowledge output when CFP35(D5/0x402DC) = "1" and
CFP34(D4/0x402DC) = "1"
GPIO1: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and
BREQEN(D2/0x39FFFD) = "0"
1 OUTLINE
S1C33L03 PRODUCT PART EPSON A-11
A-1
Table 1.3.5 List of Pins for LCD Controller
Pin name Pin No. I/O Pull-up Function
FPDAT[7:4] 13–16 O – 4 high-order bits of data bus for 8-bit LCD panels
Data bus for 4-bit LCD panels
FPDAT[3:0]
GPO[6:3] 17–20 O – FPDAT[3:0]: 4 low-order bits of data bus for 8-bit LCD panels
GPO[6:3]: General-purpose outputs when a 4-bit LCD panel is used
FPFRAME 23 O – Frame pulse output
FPLINE 24 O – Line pulse output
FPSHIFT 25 O – Shift clock output
DRDY(MOD)
(FPSHIFT2) 22 O – MOD: LCD backplane bias (for panels other than 8-bit color panel format 1)
FPSHIFT2: Second shift clock (for 8-bit color panel format 1)
LCDPWR 26 O – LCD power control output (active high)
Table 1.3.6 List of Pins for Clock Generator
Pin name Pin No. I/O Pull-up Function
OSC1 68 I – Low-speed (OSC1) oscillation input (32 kHz crystal oscillator or external clock input)
OSC2 67 O – Low-speed (OSC1) oscillation output
OSC3 129 I – High-speed (OSC3) oscillation input (crystal/ceramic oscillator or external clock input)
OSC4 128 O – High-speed (OSC3) oscillation output
PLLS[1:0] 112,113 I – PLL set-up pins
PLLS1 PLLS0 fin (fOSC3)fout (fPSCIN)
1110–25MHz 20–50MHz
0110–12.5MHz 40–50MHz
00PLL is not used L
PLLC 115 – – Capacitor connecting pin for PLL
Table 1.3.7 List of Other Pins
Pin name Pin No. I/O Pull-up
/down Function
ICEMD 125 I Pull-
down High-impedance control input pin
When this pin is set to High, all the output pins go into high-impedance state. This makes
it possible to disable the S1C33 chip on the board.
DSIO 117 I/O Pull-up Serial I/O pin for debugging
This pin is used to communicate with the debugging tool S5U1C33000H.
#X2SPD 140 I – Clock doubling mode set-up pin
1: CPU clock = bus clock × 1, 0: CPU clock = bus clock × 2
#NMI 130 I Pull-up NMI request input pin
#RESET 69 I Pull-up Initial reset input pin
Note: "#" in the pin names indicates that the signal is low active.
2 POWER SUPPLY
A-12 EPSON S1C33L03 PRODUCT PART
2 Power Supply
This chapter explains the operating voltage of the S1C33L03.
2.1 Power Supply Pins
The S1C3 3L03 has the power supply pins show n in Table 2.1.1.
Table 2.1.1 Power Supply Pins
Pin name Pin No. Function
VDD 8,51,78,127 Power supply (+) for the internal logic
VSS 3,27,45,66,82,98,105,114,116,136Power supply (-); GND
VDDE 21,59,91,132 Power supply (+) for the I/O block
AVDDE 36 Ana log sys tem po w er supp ly (+) ; AV DDE = VDDE
I/O
interface circuit
CPU core Internal
peripheral
circuit
V
DD
1.8 to 3.6 V
1.8 to 5.5 V
1.8 to 5.5 V
GND
V
DDE
I/O pins
Analog circuits
(A/D converter)
AV
DDE
V
SS
Figur e 2. 1.1 Power Suppl y Sys tem
2.2 Operating Voltage (VDD, VSS)
The core CPU and internal peripheral circuits operate with a voltage supplied between the VDD and VSS pins. The
following operating voltage can be used:
VDD = 1.8 V to 3.6 V (VSS = GND)
Note: The S1 C33L0 3 has 4 VDD pi ns and 10 VSS pins. Be sure to supply the operating voltage to all the
pins. Do not open any of them.
The ope rating clock frequency range (OSC3) is 5 MHz to 50 MHz with this voltage.
2 POWER SUPPLY
S1C33L03 PRODUCT PART EPSON A-13
A-1
A-2
2.3 Power Supply for I/O Interface (VDDE)
The V DDE voltage is used for interfacing with external I/O signals. For the output interface of the S1C33L03, the
VDDE voltage is used as high level and the VSS voltage as low level.
Normally, supply the same voltage level as VDD. It can b e supp li ed separately from VDD for 5 V interface. The VSS
pin is used for the ground common with VDD.
The following voltage is enabled for VDDE:
VDDE = 1.8 V to 5.5 V (VSS = GND)
Notes:•The S1C33L03 has 4 VDDE pins. Be sure t o su ppl y a volta ge to all the pins. Do not open any of
them.
•When an externa l cl ock is input to the OSC1 or OSC3 pin, the clock signal level must be VDD.
•The interface voltage level of the DSIO, P10, P11, P12, P13 and P14 pi ns is VDD.
2.4 Power Supply for Analog Circuits (AVDDE)
The analog power supply pin (AVDDE) is provided separately from the VDD and VDDE pins in order that the digital
circuits do not affect the analog circuit (A/D converter). The AVDDE pin is used to supply an analog power voltage
and the VSS pin is used as the analog ground.
Supply the same voltage level as the VDDE to the AVDDE pin.
AVDDE = VDDE, VSS = GN D
Note: Be sure to supply VDDE to the AVDDE pin even if the analog circuit is not used.
Noise on the analog power lines decrease the A/D converting precision, so use a stabilized power supply and make
the board pattern with consideration given to that.
3 INTERNAL MEMORY
A-14 EPSON S1C33L03 PRODUCT PART
3 Internal Memory
This chapter explains the internal memory configuration.
Figure 3.1 shows the S1C33L 03 memor y map.
Area
Areas 18–11
Area 10
Areas 9–7
Area 6
Areas 5–4
Area 3
Area 2
Area 1
Area 0
Address
0xFFFFFFF
0x1000000
0x0FFFFFF
0x0C00000
0x0BFFFFF
0x0400000
0x03FFFFF
0x0300000
0x02FFFFF
0x0100000
0x00FFFFF
0x0080000
0x007FFFF
0x0060000
0x005FFFF
0x0050000
0x004FFFF
0x0040000
0x003FFFF
0x0030000
0x002FFFF
0x0002000
0x0001FFF
0x0000000
External Memory
External Memory
External Memory
External Memory
(Reserved)
For middleware use
(Reserved)
For CPU, debug mode
(Mirror of internal
peripheral circuits)
(Mirror of internal
peripheral circuits)
Internal peripheral circuits
LCD controller
SDRAM controller
(Mirror of internal RAM)
Internal RAM (8KB)
Figur e 3. 1 Memory Map
Area 2 is use d in debug mo de only and it cannot be accessed in user mode (normal program execution status).
3.1 ROM and Boot Address
The S1C3 3L03 does not have a built- in RO M . The boot address is fixed at 0x0C00 000, and so exter nal ROM/Flas h
should be used in Area 10.
For setting up A rea 10, refer to the "BCU (Bus Control Unit)" in "S1C33L03 FUNCTION PART" in this manual.
3 INTERNAL MEMORY
S1C33L03 PRODUCT PART EPSON A-15
A-1
A-3
3.2 RAM
The S1C3 3L03 has a built- in 8KB RAM. The RAM is allocated to Area 0, addre ss 0x0000000 to address
0x0001FFF.
The internal RAM is a 32-bit sized device and data can be read/written in 1 cycle regardless of data size (byte, half-
word or word).
4 PERIPHERAL CIRCUITS
A-16 EPSON S1C33L03 PRODUCT PART
4 Peripheral Circuits
This chapter lists the built-in peripheral circuits and the I/O memory map. For details of the circuits, refer to the
"S1C33L03 FUNCTION PART".
4.1 List of Peripheral Circuits
The S1C33L03 consists of the C33 Core Block, C33 SDRAM Control ler Bl ock, C33 Per ipheral Block, C33 DMA
Block, C33 Analo g Block, and C33 LCD Control ler Bl ock.
C33 Core Block
CPU S1C33 00 0 3 2-b i t R IS C ty pe CPU
BC U (Bus Control Unit) 24-bit external a ddress bus and 16-bit data bus
All the BCU functions can be used.
ITC (Interrupt Controller) 39 types of interrupts are available.
CLG (Clock Generat or) OSC3 oscillation circuit (33 MHz Max.), PLL and OSC1 oscillation circuit
(32.768 kHz Typ.) built-in
DBG (Debug Unit) Func tional block for debuggin g w i th the S5U 1C 3 30 00H (I n-Circui t D eb ug ger
for S1C33 Family)
C33 SDRAM Controller Block
SD RA M interfac e Up to two 128M-bit SDRAMs or a 256M-bit SDRAM (32M B) can be
connected directly.
C33 Periphera l Block
Prescaler Programmable clock generator for peripheral circuits
8-bit program mable timer 6 channels with clock output function
16-bit programmable timer 6 channels with event counter, clock output and watchdog timer functions
Serial interface 4 channels (asynchronous mo de, clock sync hr onou s mod e an d IrDA are
selectable.)
Input and I/O ports 13 bits of input ports and 29 bits of I/O ports (used for peripheral I/O)
Clock timer 1 channel with alarm function
C33 DMA Block
HSDMA (High-Speed DMA) 4 channels
IDMA (Intelligent DMA) 128 channels
C33 Analog Block
A/D c onverte r 10-bit A/D c onverter with 8 input channels
C33 LCD Cont roller Block
LCD controller 4 or 8-bit monochrome/color LCD interface
2, 4 or 16-level (1, 2 or 4 bi t-per-pixel) gray-scale display
2, 4, 16 or 256-level (1, 2, 4 or 8 bi t-per-pixel) color display
Resolution exam p les: 640 × 480 pi xels with 1bpp color depth
640 × 240 pixels with 2bpp color depth
320 × 240 pixels with 4bpp color depth
240 × 160 pixels with 8bpp color depth
4 PERIPHERAL CIRCUITS
S1C33L03 PRODUCT PART EPSON A-17
A-1
A-4
4.2 I/O Memo ry Ma p
Table 4.2.1 I/O Memory Map
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
P8TPCK5
P8TPCK4
D7–2
D1
D0
reserved
8-bit timer 5 clock selection
8-bit timer 4 clock selection
–
0
0
–
R/W
R/W
0 when being read.
θ: selected by
Prescaler clock select
register (0x40181)
0040140
(B) 1θ/1 0 Divided clk.
1θ/1 0 Divided clk.
8-bit timer 4/5
clock select
register
–
1On 0OffP8TON5
P8TS52
P8TS51
P8TS50
P8TON4
P8TS42
P8TS41
P8TS40
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 5 clock control
8-bit timer 5
clock division ratio selection
8-bit timer 4 clock control
8-bit timer 4
clock division ratio selection
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
θ: selected by
Prescaler clock select
register (0x40181)
8-bit timer 5 can
generate the clock for
the serial I/F Ch.3.
θ: selected by
Prescaler clock select
register (0x40181)
8-bit timer 4 can
generate the clock for
the serial I/F Ch.2.
0040145
(B) 1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
θ/256
θ/128
θ/64
θ/32
θ/16
θ/8
θ/4
θ/2
1On 0Off
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
θ/4096
θ/2048
θ/64
θ/32
θ/16
θ/8
θ/4
θ/2
8-bit timer 4/5
clock control
register
––
P8TPCK3
P8TPCK2
P8TPCK1
P8TPCK0
D7–4
D3
D2
D1
D0
reserved
8-bit timer 3 clock selection
8-bit timer 2 clock selection
8-bit timer 1 clock selection
8-bit timer 0 clock selection
–
0
0
0
0
–
R/W
R/W
R/W
R/W
0 when being read.
θ: selected by
Prescaler clock select
register (0x40181)
0040146
(B) 1θ/1 0 Divided clk.
1θ/1 0 Divided clk.
1θ/1 0 Divided clk.
1θ/1 0 Divided clk.
8-bit timer
clock select
register
––
P16TON0
P16TS02
P16TS01
P16TS00
D7–4
D3
D2
D1
D0
reserved
16-bit timer 0 clock control
16-bit timer 0
clock division ratio selection
–
0
0
0
0
–
R/W
R/W
0 when being read.
θ: selected by
Prescaler clock select
register (0x40181)
16-bit timer 0 can be
used as a watchdog
timer.
0040147
(B) 1On 0Off
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
P16TS0[2:0] Division ratio
θ/4096
θ/1024
θ/256
θ/64
θ/16
θ/4
θ/2
θ/1
16-bit timer 0
clock control
register
––
P16TON1
P16TS12
P16TS11
P16TS10
D7–4
D3
D2
D1
D0
reserved
16-bit timer 1 clock control
16-bit timer 1
clock division ratio selection
–
0
0
0
0
–
R/W
R/W
0 when being read.
θ: selected by
Prescaler clock select
register (0x40181)
0040148
(B) 1On 0Off
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
P16TS1[2:0] Division ratio
θ/4096
θ/1024
θ/256
θ/64
θ/16
θ/4
θ/2
θ/1
16-bit timer 1
clock control
register
––
P16TON2
P16TS22
P16TS21
P16TS20
D7–4
D3
D2
D1
D0
reserved
16-bit timer 2 clock control
16-bit timer 2
clock division ratio selection
–
0
0
0
0
–
R/W
R/W
0 when being read.
θ: selected by
Prescaler clock select
register (0x40181)
0040149
(B) 1On 0Off
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
P16TS2[2:0] Division ratio
θ/4096
θ/1024
θ/256
θ/64
θ/16
θ/4
θ/2
θ/1
16-bit timer 2
clock control
register
(B) in [Address] indicates an 8-bit register and (HW) indicates a 16-bit register.
The meaning of the symbols described in [Init.] are listed below:
0, 1: Initial values that are set at initial reset.
(However, the registers for the bus and input/output ports are not initialized at hot start.)
X: Not initialized at initial reset.
–: N ot s et in the circuit.
4 PERIPHERAL CIRCUITS
A-18 EPSON S1C33L03 PRODUCT PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
––
P16TON3
P16TS32
P16TS31
P16TS30
D7–4
D3
D2
D1
D0
reserved
16-bit timer 3 clock control
16-bit timer 3
clock division ratio selection
–
0
0
0
0
–
R/W
R/W
0 when being read.
θ: selected by
Prescaler clock select
register (0x40181)
004014A
(B) 1 On 0 Off
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
P16TS3[2:0] Division ratio
θ/4096
θ/1024
θ/256
θ/64
θ/16
θ/4
θ/2
θ/1
16-bit timer 3
clock control
register
––
P16TON4
P16TS42
P16TS41
P16TS40
D7–4
D3
D2
D1
D0
reserved
16-bit timer 4 clock control
16-bit timer 4
clock division ratio selection
–
0
0
0
0
–
R/W
R/W
0 when being read.
θ: selected by
Prescaler clock select
register (0x40181)
004014B
(B) 1 On 0 Off
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
P16TS4[2:0] Division ratio
θ/4096
θ/1024
θ/256
θ/64
θ/16
θ/4
θ/2
θ/1
16-bit timer 4
clock control
register
––
P16TON5
P16TS52
P16TS51
P16TS50
D7–4
D3
D2
D1
D0
reserved
16-bit timer 5 clock control
16-bit timer 5
clock division ratio selection
–
0
0
0
0
–
R/W
R/W
0 when being read.
θ: selected by
Prescaler clock select
register (0x40181)
004014C
(B) 1 On 0 Off
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
P16TS5[2:0] Division ratio
θ/4096
θ/1024
θ/256
θ/64
θ/16
θ/4
θ/2
θ/1
16-bit timer 5
clock control
register
1 On 0 OffP8TON1
P8TS12
P8TS11
P8TS10
P8TON0
P8TS02
P8TS01
P8TS00
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 1 clock control
8-bit timer 1
clock division ratio selection
8-bit timer 0 clock control
8-bit timer 0
clock division ratio selection
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
θ: selected by
Prescaler clock select
register (0x40181)
8-bit timer 1 can
generate the OSC3
oscillation-stabilize
waiting period.
θ: selected by
Prescaler clock select
register (0x40181)
8-bit timer 0 can
generate the DRAM
refresh clock.
004014D
(B) 1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
P8TS1[2:0] Division ratio
θ/4096
θ/2048
θ/1024
θ/512
θ/256
θ/128
θ/64
θ/32
1 On 0 Off
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
P8TS0[2:0] Division ratio
θ/256
θ/128
θ/64
θ/32
θ/16
θ/8
θ/4
θ/2
8-bit timer 0/1
clock control
register
4 PERIPHERAL CIRCUITS
S1C33L03 PRODUCT PART EPSON A-19
A-1
A-4
NameAddressRegister name Bit Function Setting Init. R/W Remarks
1 On 0 OffP8TON3
P8TS32
P8TS31
P8TS30
P8TON2
P8TS22
P8TS21
P8TS20
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 3 clock control
8-bit timer 3
clock division ratio selection
8-bit timer 2 clock control
8-bit timer 2
clock division ratio selection
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
θ: selected by
Prescaler clock select
register (0x40181)
8-bit timer 3 can
generate the clock for
the serial I/F Ch.1.
θ: selected by
Prescaler clock select
register (0x40181)
8-bit timer 2 can
generate the clock for
the serial I/F Ch.0.
004014E
(B) 1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
P8TS3[2:0] Division ratio
θ/256
θ/128
θ/64
θ/32
θ/16
θ/8
θ/4
θ/2
1 On 0 Off
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
P8TS2[2:0] Division ratio
θ/4096
θ/2048
θ/64
θ/32
θ/16
θ/8
θ/4
θ/2
8-bit timer 2/3
clock control
register
–
PSONAD
PSAD2
PSAD1
PSAD0
D7–4
D3
D2
D1
D0
reserved
A/D converter clock control
A/D converter clock division ratio
selection
–
0
0
0
0
–
R/W
R/W
0 when being read.
θ: selected by
Prescaler clock select
register (0x40181)
004014F
(B)
A/D clock
control register
1 On 0 Off
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
P8TS0[2:0] Division ratio
θ/256
θ/128
θ/64
θ/32
θ/16
θ/8
θ/4
θ/2
–
–
TCRST
TCRUN
D7–2
D1
D0
reserved
Clock timer reset
Clock timer Run/Stop control
–
X
X
–
W
R/W
0 when being read.
0 when being read.
0040151
(B) 1 Reset 0 Invalid
1 Run 0 Stop
–Clock timer
Run/Stop
register
TCISE2
TCISE1
TCISE0
TCASE2
TCASE1
TCASE0
TCIF
TCAF
D7
D6
D5
D4
D3
D2
D1
D0
Clock timer interrupt factor
selection
Clock timer alarm factor selection
Interrupt factor generation flag
Alarm factor generation flag
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W Reset by writing 1.
Reset by writing 1.
0040152
(B)
1 Generated 0
Not generated
1 Generated 0
Not generated
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
TCISE[2:0] Interrupt factor
None
Day
Hour
Minute
1 Hz
2 Hz
8 Hz
32 Hz
1
X
X
0
X
1
X
0
X
X
1
0
TCASE[2:0] Alarm factor
Day
Hour
Minute
None
Clock timer
interrupt
control register
TCD7
TCD6
TCD5
TCD4
TCD3
TCD2
TCD1
TCD0
D7
D6
D5
D4
D3
D2
D1
D0
Clock timer data 1 Hz
Clock timer data 2 Hz
Clock timer data 4 Hz
Clock timer data 8 Hz
Clock timer data 16 Hz
Clock timer data 32 Hz
Clock timer data 64 Hz
Clock timer data 128 Hz
X
X
X
X
X
X
X
X
R
R
R
R
R
R
R
R
0040153
(B) 1 High 0 Low
1 High 0 Low
1 High 0 Low
1 High 0 Low
1 High 0 Low
1 High 0 Low
1 High 0 Low
1 High 0 Low
Clock timer
divider register
–
TCMD5
TCMD4
TCMD3
TCMD2
TCMD1
TCMD0
D7–6
D5
D4
D3
D2
D1
D0
reserved
Clock timer second counter data
TCMD5 = MSB
TCMD0 = LSB
–
X
X
X
X
X
X
–
R0 when being read.0040154
(B) –
0 to 59 seconds
Clock timer
second
register
4 PERIPHERAL CIRCUITS
A-20 EPSON S1C33L03 PRODUCT PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
TCHD5
TCHD4
TCHD3
TCHD2
TCHD1
TCHD0
D7–6
D5
D4
D3
D2
D1
D0
reserved
Clock timer minute counter data
TCHD5 = MSB
TCHD0 = LSB
–
X
X
X
X
X
X
–
R/W 0 when being read.0040155
(B) –
0 to 59 minutes
Clock timer
minute register
0 to 23 hours
–
TCDD4
TCDD3
TCDD2
TCDD1
TCDD0
D7–5
D4
D3
D2
D1
D0
reserved
Clock timer hour counter data
TCDD4 = MSB
TCDD0 = LSB
–
X
X
X
X
X
–
R/W 0 when being read.0040156
(B)
Clock timer
hour register –
0 to 65535 days
(low-order 8 bits)
TCND7
TCND6
TCND5
TCND4
TCND3
TCND2
TCND1
TCND0
D7
D6
D5
D4
D3
D2
D1
D0
Clock timer day counter data
(low-order 8 bits)
TCND0 = LSB
X
X
X
X
X
X
X
X
R/W0040157
(B)
Clock timer
day (low-order)
register
0 to 65535 days
(high-order 8 bits) X
X
X
X
X
X
X
X
R/WTCND15
TCND14
TCND13
TCND12
TCND11
TCND10
TCND9
TCND8
D7
D6
D5
D4
D3
D2
D1
D0
Clock timer day counter data
(high-order 8 bits)
TCND15 = MSB
0040158
(B)
Clock timer
day (high-
order) register
0 to 59 minutes
(Note) Can be set within 0–63.
–
TCCH5
TCCH4
TCCH3
TCCH2
TCCH1
TCCH0
D7–6
D5
D4
D3
D2
D1
D0
reserved
Clock timer minute comparison
data
TCCH5 = MSB
TCCH0 = LSB
–
X
X
X
X
X
X
–
R/W 0 when being read.0040159
(B) –Clock timer
minute
comparison
register
0 to 23 hours
(Note) Can be set within 0–31.
–
TCCD4
TCCD3
TCCD2
TCCD1
TCCD0
D7–5
D4
D3
D2
D1
D0
reserved
Clock timer hour comparison data
TCCD4 = MSB
TCCD0 = LSB
–
X
X
X
X
X
–
R/W 0 when being read.004015A
(B) –Clock timer
hour
comparison
register
0 to 31 days
–
TCCN4
TCCN3
TCCN2
TCCN1
TCCN0
D7–5
D4
D3
D2
D1
D0
reserved
Clock timer day comparison data
TCCN4 = MSB
TCCN0 = LSB
–
X
X
X
X
X
–
R/W 0 when being read.
Compared with
TCND[4:0].
004015B
(B) –Clock timer
day
comparison
register
4 PERIPHERAL CIRCUITS
S1C33L03 PRODUCT PART EPSON A-21
A-1
A-4
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
PTOUT0
PSET0
PTRUN0
D7–3
D2
D1
D0
reserved
8-bit timer 0 clock output control
8-bit timer 0 preset
8-bit timer 0 Run/Stop control
–
0
–
0
–
R/W
W
R/W
0 when being read.
0 when being read.
0040160
(B) –
1 On 0 Off
1 Preset 0 Invalid
1 Run 0 Stop
8-bit timer 0
control register
0 to 255RLD07
RLD06
RLD05
RLD04
RLD03
RLD02
RLD01
RLD00
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 0 reload data
RLD07 = MSB
RLD00 = LSB
X
X
X
X
X
X
X
X
R/W0040161
(B)
8-bit timer 0
reload data
register
0 to 255PTD07
PTD06
PTD05
PTD04
PTD03
PTD02
PTD01
PTD00
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 0 counter data
PTD07 = MSB
PTD00 = LSB
X
X
X
X
X
X
X
X
R0040162
(B)
8-bit timer 0
counter data
register
–
PTOUT1
PSET1
PTRUN1
D7–3
D2
D1
D0
reserved
8-bit timer 1 clock output control
8-bit timer 1 preset
8-bit timer 1 Run/Stop control
–
0
–
0
–
R/W
W
R/W
0 when being read.
0 when being read.
0040164
(B) –
1 On 0 Off
1 Preset 0 Invalid
1 Run 0 Stop
8-bit timer 1
control register
0 to 255RLD17
RLD16
RLD15
RLD14
RLD13
RLD12
RLD11
RLD10
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 1 reload data
RLD17 = MSB
RLD10 = LSB
X
X
X
X
X
X
X
X
R/W0040165
(B)
8-bit timer 1
reload data
register
0 to 255PTD17
PTD16
PTD15
PTD14
PTD13
PTD12
PTD11
PTD10
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 1 counter data
PTD17 = MSB
PTD10 = LSB
X
X
X
X
X
X
X
X
R0040166
(B)
8-bit timer 1
counter data
register
–
PTOUT2
PSET2
PTRUN2
D7–3
D2
D1
D0
reserved
8-bit timer 2 clock output control
8-bit timer 2 preset
8-bit timer 2 Run/Stop control
–
0
–
0
–
R/W
W
R/W
0 when being read.
0 when being read.
0040168
(B) –
1 On 0 Off
1 Preset 0 Invalid
1 Run 0 Stop
8-bit timer 2
control register
0 to 255RLD27
RLD26
RLD25
RLD24
RLD23
RLD22
RLD21
RLD20
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 2 reload data
RLD27 = MSB
RLD20 = LSB
X
X
X
X
X
X
X
X
R/W0040169
(B)
8-bit timer 2
reload data
register
0 to 255PTD27
PTD26
PTD25
PTD24
PTD23
PTD22
PTD21
PTD20
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 2 counter data
PTD27 = MSB
PTD20 = LSB
X
X
X
X
X
X
X
X
R004016A
(B)
8-bit timer 2
counter data
register
4 PERIPHERAL CIRCUITS
A-22 EPSON S1C33L03 PRODUCT PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
PTOUT3
PSET3
PTRUN3
D7–3
D2
D1
D0
reserved
8-bit timer 3 clock output control
8-bit timer 3 preset
8-bit timer 3 Run/Stop control
–
0
–
0
–
R/W
W
R/W
0 when being read.
0 when being read.
004016C
(B) –
1 On 0 Off
1 Preset 0 Invalid
1 Run 0 Stop
8-bit timer 3
control register
0 to 255RLD37
RLD36
RLD35
RLD34
RLD33
RLD32
RLD31
RLD30
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 3 reload data
RLD37 = MSB
RLD30 = LSB
X
X
X
X
X
X
X
X
R/W004016D
(B)
8-bit timer 3
reload data
register
0 to 255PTD37
PTD36
PTD35
PTD34
PTD33
PTD32
PTD31
PTD30
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 3 counter data
PTD37 = MSB
PTD30 = LSB
X
X
X
X
X
X
X
X
R004016E
(B)
8-bit timer 3
counter data
register
–
PTOUT4
PSET4
PTRUN4
D7–3
D2
D1
D0
reserved
8-bit timer 4 clock output control
8-bit timer 4 preset
8-bit timer 4 Run/Stop control
–
0
–
0
–
R/W
W
R/W
0 when being read.
0 when being read.
0040174
(B) –
1 On 0 Off
1 Preset 0 Invalid
1 Run 0 Stop
8-bit timer 4
control register
0 to 255RLD47
RLD46
RLD45
RLD44
RLD43
RLD42
RLD41
RLD40
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 4 reload data
RLD47 = MSB
RLD40 = LSB
X
X
X
X
X
X
X
X
R/W0040175
(B)
8-bit timer 4
reload data
register
0 to 255PTD47
PTD46
PTD45
PTD44
PTD43
PTD42
PTD41
PTD40
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 4 counter data
PTD47 = MSB
PTD40 = LSB
X
X
X
X
X
X
X
X
R0040176
(B)
8-bit timer 4
counter data
register
–
PTOUT5
PSET5
PTRUN5
D7–3
D2
D1
D0
reserved
8-bit timer 5 clock output control
8-bit timer 5 preset
8-bit timer 5 Run/Stop control
–
0
–
0
–
R/W
W
R/W
0 when being read.
0 when being read.
0040178
(B) –
1 On 0 Off
1 Preset 0 Invalid
1 Run 0 Stop
8-bit timer 5
control register
0 to 255RLD57
RLD56
RLD55
RLD54
RLD53
RLD52
RLD51
RLD50
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 5 reload data
RLD57 = MSB
RLD50 = LSB
X
X
X
X
X
X
X
X
R/W0040179
(B)
8-bit timer 5
reload data
register
0 to 255PTD57
PTD56
PTD55
PTD54
PTD53
PTD52
PTD51
PTD50
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 5 counter data
PTD57 = MSB
PTD50 = LSB
X
X
X
X
X
X
X
X
R004017A
(B)
8-bit timer 5
counter data
register
4 PERIPHERAL CIRCUITS
S1C33L03 PRODUCT PART EPSON A-23
A-1
A-4
NameAddressRegister name Bit Function Setting Init. R/W Remarks
WRWD
–
D7
D6–0 EWD write protection
–0
–R/W
–0 when being read.
0040170
(B) –
1
Write enabled
0
Write-protect
Watchdog
timer write-
protect register
–
–
–
EWD
–
D7–2
D1
D0
–
Watchdog timer enable
–
–
0
–
–
R/W
–
0 when being read.
0 when being read.
0040171
(B) 1
NMI enabled
0
NMI disabled
Watchdog
timer enable
register
4 PERIPHERAL CIRCUITS
A-24 EPSON S1C33L03 PRODUCT PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
CLKDT1
CLKDT0
PSCON
–
CLKCHG
SOSC3
SOSC1
D7
D6
D5
D4–3
D2
D1
D0
System clock division ratio
selection
Prescaler On/Off control
reserved
CPU operating clock switch
High-speed (OSC3) oscillation On/Off
Low-speed (OSC1) oscillation On/Off
1 On 0 Off
1 OSC3 0 OSC1
1 On 0 Off
1 On 0 Off
0
0
1
0
1
1
1
R/W
R/W
–
R/W
R/W
R/W
Writing 1 not allowed.
0040180
(B) 1
1
0
0
1
0
1
0
CLKDT[1:0] Division ratio
1/8
1/4
1/2
1/1
–
Power control
register
–
PSCDT0
D7–1
D0 reserved
Prescaler clock selection 0
0–
R/W
0040181
(B) –Prescaler clock
select register 1 OSC1 0 OSC3/PLL
–
HLT2OP
8T1ON
–
PF1ON
D7–4
D3
D2
D1
D0
–
HALT clock option
OSC3-stabilize waiting function
reserved
OSC1 external output control
–
0
1
0
0
–
R/W
R/W
–
R/W
0 when being read.
Do not write 1.
0040190
(B) 1 On 0 Off
1 Off 0 On
1 On 0 Off
–
–
Clock option
register
Writing 10010110 (0x96)
removes the write protection of
the power control register
(0x40180) and the clock option
register (0x40190).
Writing another value set the
write protection.
CLGP7
CLGP6
CLGP5
CLGP4
CLGP3
CLGP2
CLGP1
CLGP0
D7
D6
D5
D4
D3
D2
D1
D0
Power control register protect flag 0
0
0
0
0
0
0
0
R/W004019E
(B)
Power control
protect register
4 PERIPHERAL CIRCUITS
S1C33L03 PRODUCT PART EPSON A-25
A-1
A-4
NameAddressRegister name Bit Function Setting Init. R/W Remarks
0x0 to 0xFF(0x7F)TXD07
TXD06
TXD05
TXD04
TXD03
TXD02
TXD01
TXD00
D7
D6
D5
D4
D3
D2
D1
D0
Serial I/F Ch.0 transmit data
TXD07(06) = MSB
TXD00 = LSB
X
X
X
X
X
X
X
X
R/W 7-bit asynchronous
mode does not use
TXD07.
00401E0
(B)
Serial I/F Ch.0
transmit data
register
0x0 to 0xFF(0x7F)RXD07
RXD06
RXD05
RXD04
RXD03
RXD02
RXD01
RXD00
D7
D6
D5
D4
D3
D2
D1
D0
Serial I/F Ch.0 receive data
RXD07(06) = MSB
RXD00 = LSB
X
X
X
X
X
X
X
X
R 7-bit asynchronous
mode does not use
RXD07 (fixed at 0).
00401E1
(B)
Serial I/F Ch.0
receive data
register
–
TEND0
FER0
PER0
OER0
TDBE0
RDBF0
D7–6
D5
D4
D3
D2
D1
D0
–
Ch.0 transmit-completion flag
Ch.0 flaming error flag
Ch.0 parity error flag
Ch.0 overrun error flag
Ch.0 transmit data buffer empty
Ch.0 receive data buffer full
–
0
0
0
0
1
0
–
R
R/W
R/W
R/W
R
R
0 when being read.
Reset by writing 0.
Reset by writing 0.
Reset by writing 0.
00401E2
(B) –
1 Error 0 Normal
1
Transmitting
0 End
1 Error 0 Normal
1 Error 0 Normal
1 Empty 0 Buffer full
1 Buffer full 0 Empty
Serial I/F Ch.0
status register
TXEN0
RXEN0
EPR0
PMD0
STPB0
SSCK0
SMD01
SMD00
D7
D6
D5
D4
D3
D2
D1
D0
Ch.0 transmit enable
Ch.0 receive enable
Ch.0 parity enable
Ch.0 parity mode selection
Ch.0 stop bit selection
Ch.0 input clock selection
Ch.0 transfer mode selection 1
1
0
0
1
0
1
0
SMD0[1:0] Transfer mode
8-bit asynchronous
7-bit asynchronous
Clock sync. Slave
Clock sync. Master
0
0
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Valid only in
asynchronous mode.
00401E3
(B) 1 Enabled 0 Disabled
1 Enabled 0 Disabled
1 With parity 0 No parity
1 Odd 0 Even
1 2 bits 0 1 bit
1 #SCLK0 0
Internal clock
Serial I/F Ch.0
control register
–
DIVMD0
IRTL0
IRRL0
IRMD01
IRMD00
D7–5
D4
D3
D2
D1
D0
–
Ch.0 async. clock division ratio
Ch.0 IrDA I/F output logic inversion
Ch.0 IrDA I/F input logic inversion
Ch.0 interface mode selection 1
1
0
0
1
0
1
0
IRMD0[1:0]
–
I/F mode
reserved
IrDA 1.0
reserved
General I/F
–
X
X
X
X
X
–
R/W
R/W
R/W
R/W
0 when being read.
Valid only in
asynchronous mode.
00401E4
(B) 1 1/8 0 1/16
1 Inverted 0 Direct
1 Inverted 0 Direct
Serial I/F Ch.0
IrDA register
4 PERIPHERAL CIRCUITS
A-26 EPSON S1C33L03 PRODUCT PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
0x0 to 0xFF(0x7F)TXD17
TXD16
TXD15
TXD14
TXD13
TXD12
TXD11
TXD10
D7
D6
D5
D4
D3
D2
D1
D0
Serial I/F Ch.1 transmit data
TXD17(16) = MSB
TXD10 = LSB
X
X
X
X
X
X
X
X
R/W 7-bit asynchronous
mode does not use
TXD17.
00401E5
(B)
Serial I/F Ch.1
transmit data
register
0x0 to 0xFF(0x7F)RXD17
RXD16
RXD15
RXD14
RXD13
RXD12
RXD11
RXD10
D7
D6
D5
D4
D3
D2
D1
D0
Serial I/F Ch.1 receive data
RXD17(16) = MSB
RXD10 = LSB
X
X
X
X
X
X
X
X
R 7-bit asynchronous
mode does not use
RXD17 (fixed at 0).
00401E6
(B)
Serial I/F Ch.1
receive data
register
–
TEND1
FER1
PER1
OER1
TDBE1
RDBF1
D7–6
D5
D4
D3
D2
D1
D0
–
Ch.1 transmit-completion flag
Ch.1 flaming error flag
Ch.1 parity error flag
Ch.1 overrun error flag
Ch.1 transmit data buffer empty
Ch.1 receive data buffer full
–
0
0
0
0
1
0
–
R
R/W
R/W
R/W
R
R
0 when being read.
Reset by writing 0.
Reset by writing 0.
Reset by writing 0.
00401E7
(B) –
1 Error 0 Normal
1
Transmitting
0 End
1 Error 0 Normal
1 Error 0 Normal
1 Empty 0 Buffer full
1 Buffer full 0 Empty
Serial I/F Ch.1
status register
TXEN1
RXEN1
EPR1
PMD1
STPB1
SSCK1
SMD11
SMD10
D7
D6
D5
D4
D3
D2
D1
D0
Ch.1 transmit enable
Ch.1 receive enable
Ch.1 parity enable
Ch.1 parity mode selection
Ch.1 stop bit selection
Ch.1 input clock selection
Ch.1 transfer mode selection 1
1
0
0
1
0
1
0
SMD1[1:0] Transfer mode
8-bit asynchronous
7-bit asynchronous
Clock sync. Slave
Clock sync. Master
0
0
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Valid only in
asynchronous mode.
00401E8
(B)
Serial I/F Ch.1
control register 1 Enabled 0 Disabled
1 Enabled 0 Disabled
1 With parity 0 No parity
1 Odd 0 Even
1 2 bits 0 1 bit
1 #SCLK1 0
Internal clock
–
DIVMD1
IRTL1
IRRL1
IRMD11
IRMD10
D7–5
D4
D3
D2
D1
D0
–
Ch.1 async. clock division ratio
Ch.1 IrDA I/F output logic inversion
Ch.1 IrDA I/F input logic inversion
Ch.1 interface mode selection 1
1
0
0
1
0
1
0
IRMD1[1:0]
–
I/F mode
reserved
IrDA 1.0
reserved
General I/F
–
X
X
X
X
X
–
R/W
R/W
R/W
R/W
0 when being read.
Valid only in
asynchronous mode.
00401E9
(B) 1 1/8 0 1/16
1 Inverted 0 Direct
1 Inverted 0 Direct
Serial I/F Ch.1
IrDA register
0x0 to 0xFF(0x7F)TXD27
TXD26
TXD25
TXD24
TXD23
TXD22
TXD21
TXD20
D7
D6
D5
D4
D3
D2
D1
D0
Serial I/F Ch.2 transmit data
TXD27(26) = MSB
TXD20 = LSB
X
X
X
X
X
X
X
X
R/W00401F0
(B)
Serial I/F Ch.2
transmit data
register
0x0 to 0xFF(0x7F)RXD27
RXD26
RXD25
RXD24
RXD23
RXD22
RXD21
RXD20
D7
D6
D5
D4
D3
D2
D1
D0
Serial I/F Ch.2 receive data
RXD27(26) = MSB
RXD20 = LSB
X
X
X
X
X
X
X
X
R00401F1
(B)
Serial I/F Ch.2
receive data
register
–
TEND2
FER2
PER2
OER2
TDBE2
RDBF2
D7–6
D5
D4
D3
D2
D1
D0
reserved
Ch.2 transmit-completion flag
Ch.2 flaming error flag
Ch.2 parity error flag
Ch.2 overrun error flag
Ch.2 transmit data buffer empty
Ch.2 receive data buffer full
–
0
0
0
0
1
0
–
R
R/W
R/W
R/W
R
R
0 when being read.
Reset by writing 0.
Reset by writing 0.
Reset by writing 0.
00401F2
(B) –
1 Error 0 Normal
1
Transmitting
0 End
1 Error 0 Normal
1 Error 0 Normal
1 Empty 0 Buffer full
1 Buffer full 0 Empty
Serial I/F Ch.2
status register
4 PERIPHERAL CIRCUITS
S1C33L03 PRODUCT PART EPSON A-27
A-1
A-4
NameAddressRegister name Bit Function Setting Init. R/W Remarks
TXEN2
RXEN2
EPR2
PMD2
STPB2
SSCK2
SMD21
SMD20
D7
D6
D5
D4
D3
D2
D1
D0
Ch.2 transmit enable
Ch.2 receive enable
Ch.2 parity enable
Ch.2 parity mode selection
Ch.2 stop bit selection
Ch.2 input clock selection
Ch.2 transfer mode selection 1
1
0
0
1
0
1
0
SMD2[1:0] Transfer mode
8-bit asynchronous
7-bit asynchronous
Clock sync. Slave
Clock sync. Master
0
0
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Valid only in
asynchronous mode.
00401F3
(B)
Serial I/F Ch.2
control register 1 Enabled 0 Disabled
1 Enabled 0 Disabled
1 With parity 0 No parity
1 Odd 0 Even
1 2 bits 0 1 bit
1 #SCLK2 0
Internal clock
–
DIVMD2
IRTL2
IRRL2
IRMD21
IRMD20
D7–5
D4
D3
D2
D1
D0
reserved
Ch.2 async. clock division ratio
Ch.2 IrDA I/F output logic inversion
Ch.2 IrDA I/F input logic inversion
Ch.2 interface mode selection 1
1
0
0
1
0
1
0
IRMD2[1:0]
–
I/F mode
reserved
IrDA 1.0
reserved
General I/F
–
X
X
X
X
X
–
R/W
R/W
R/W
R/W
0 when being read.
Valid only in
asynchronous mode.
00401F4
(B) 1 1/8 0 1/16
1 Inverted 0 Direct
1 Inverted 0 Direct
Serial I/F Ch.2
IrDA register
0x0 to 0xFF(0x7F)TXD37
TXD36
TXD35
TXD34
TXD33
TXD32
TXD31
TXD30
D7
D6
D5
D4
D3
D2
D1
D0
Serial I/F Ch.3 transmit data
TXD37(36) = MSB
TXD30 = LSB
X
X
X
X
X
X
X
X
R/W00401F5
(B)
Serial I/F Ch.3
transmit data
register
0x0 to 0xFF(0x7F)RXD37
RXD36
RXD35
RXD34
RXD33
RXD32
RXD31
RXD30
D7
D6
D5
D4
D3
D2
D1
D0
Serial I/F Ch.3 receive data
RXD37(36) = MSB
RXD30 = LSB
X
X
X
X
X
X
X
X
R00401F6
(B)
Serial I/F Ch.3
receive data
register
–
TEND3
FER3
PER3
OER3
TDBE3
RDBF3
D7–6
D5
D4
D3
D2
D1
D0
reserved
Ch.3 transmit-completion flag
Ch.3 flaming error flag
Ch.3 parity error flag
Ch.3 overrun error flag
Ch.3 transmit data buffer empty
Ch.3 receive data buffer full
–
0
0
0
0
1
0
–
R
R/W
R/W
R/W
R
R
0 when being read.
Reset by writing 0.
Reset by writing 0.
Reset by writing 0.
00401F7
(B) –
1 Error 0 Normal
1
Transmitting
0 End
1 Error 0 Normal
1 Error 0 Normal
1 Empty 0 Buffer full
1 Buffer full 0 Empty
Serial I/F Ch.3
status register
TXEN3
RXEN3
EPR3
PMD3
STPB3
SSCK3
SMD31
SMD30
D7
D6
D5
D4
D3
D2
D1
D0
Ch.3 transmit enable
Ch.3 receive enable
Ch.3 parity enable
Ch.3 parity mode selection
Ch.3 stop bit selection
Ch.3 input clock selection
Ch.3 transfer mode selection 1
1
0
0
1
0
1
0
SMD3[1:0] Transfer mode
8-bit asynchronous
7-bit asynchronous
Clock sync. Slave
Clock sync. Master
0
0
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Valid only in
asynchronous mode.
00401F8
(B)
Serial I/F Ch.3
control register 1 Enabled 0 Disabled
1 Enabled 0 Disabled
1 With parity 0 No parity
1 Odd 0 Even
1 2 bits 0 1 bit
1 #SCLK3 0
Internal clock
–
DIVMD3
IRTL3
IRRL3
IRMD31
IRMD30
D7–5
D4
D3
D2
D1
D0
reserved
Ch.3 async. clock division ratio
Ch.3 IrDA I/F output logic inversion
Ch.3 IrDA I/F input logic inversion
Ch.3 interface mode selection 1
1
0
0
1
0
1
0
IRMD3[1:0]
–
I/F mode
reserved
IrDA 1.0
reserved
General I/F
–
X
X
X
X
X
–
R/W
R/W
R/W
R/W
0 when being read.
Valid only in
asynchronous mode.
00401F9
(B) 1 1/8 0 1/16
1 Inverted 0 Direct
1 Inverted 0 Direct
Serial I/F Ch.3
IrDA register
4 PERIPHERAL CIRCUITS
A-28 EPSON S1C33L03 PRODUCT PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
D7
D6
D5
D4
D3
D2
D1
D0
A/D converted data
(low-order 8 bits)
ADD0 = LSB
0x0 to 0x3FF
(low-order 8 bits) 0
0
0
0
0
0
0
0
R0040240
(B)
A/D conversion
result (low-
order) register
0x0 to 0x3FF
(high-order 2 bits)
––
ADD9
ADD8
D7–2
D1
D0
–
A/D converted data
(high-order 2 bits) ADD9 = MSB
–
0
0
–
R0 when being read.0040241
(B)
A/D conversion
result (high-
order) register
–
MS
TS1
TS0
CH2
CH1
CH0
D7–6
D5
D4
D3
D2
D1
D0
–
A/D conversion mode selection
A/D conversion trigger selection
A/D conversion channel status
1
1
0
0
1
0
1
0
TS[1:0]
–
Trigger
#ADTRG pin
8-bit timer 0
16-bit timer 0
Software
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
CH[2:0] Channel
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
–
0
0
0
0
0
0
–
R/W
R/W
R
0 when being read.0040242
(B) 1 Continuous 0 Normal
A/D trigger
register
–
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
CE[2:0] End channel
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
CS[2:0] Start channel
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
–
CE2
CE1
CE0
CS2
CS1
CS0
D7–6
D5
D4
D3
D2
D1
D0
–
A/D converter
end channel selection
A/D converter
start channel selection
–
0
0
0
0
0
0
–
R/W
R/W
0 when being read.0040243
(B)
A/D channel
register
–
ADF
ADE
ADST
OWE
D7–4
D3
D2
D1
D0
–
Conversion-complete flag
A/D enable
A/D conversion control/status
Overwrite error flag
– –
0
0
0
0
–
R
R/W
R/W
R/W
0 when being read.
Reset when ADD is read.
Reset by writing 0.
0040244
(B)
A/D enable
register 1 Enabled 0 Disabled
1 Completed 0
Run/Standby
1 Start/Run 0 Stop
1 Error 0 Normal
–
ST1
ST0
D7–2
D1
D0
–
Input signal sampling time setup –
1
1
0
0
1
0
1
0
ST[1:0] Sampring time
9 clocks
7 clocks
5 clocks
3 clocks
–
1
1
–
R/W 0 when being read.
Use with 9 clocks.
0040245
(B)
A/D sampling
register
4 PERIPHERAL CIRCUITS
S1C33L03 PRODUCT PART EPSON A-29
A-1
A-4
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
0 to 7
0 to 7
–
–
PP1L2
PP1L1
PP1L0
–
PP0L2
PP0L1
PP0L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Port input 1 interrupt level
reserved
Port input 0 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040260
(B)
Port input 0/1
interrupt
priority register
–
0 to 7
0 to 7
–
–
PP3L2
PP3L1
PP3L0
–
PP2L2
PP2L1
PP2L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Port input 3 interrupt level
reserved
Port input 2 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040261
(B)
Port input 2/3
interrupt
priority register
–
0 to 7
0 to 7
–
–
PK1L2
PK1L1
PK1L0
–
PK0L2
PK0L1
PK0L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Key input 1 interrupt level
reserved
Key input 0 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040262
(B)
Key input
interrupt
priority register
–
0 to 7
0 to 7
–
–
PHSD1L2
PHSD1L1
PHSD1L0
–
PHSD0L2
PHSD0L1
PHSD0L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
High-speed DMA Ch.1
interrupt level
reserved
High-speed DMA Ch.0
interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040263
(B)
High-speed
DMA Ch.0/1
interrupt
priority register
–
0 to 7
0 to 7
–
–
PHSD3L2
PHSD3L1
PHSD3L0
–
PHSD2L2
PHSD2L1
PHSD2L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
High-speed DMA Ch.3
interrupt level
reserved
High-speed DMA Ch.2
interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040264
(B)
High-speed
DMA Ch.2/3
interrupt
priority register
–
0 to 7
–
PDM2
PDM1
PDM0
D7–3
D2
D1
D0
reserved
IDMA interrupt level –
X
X
X
–
R/W 0 when being read.0040265
(B)
IDMA interrupt
priority register
–
0 to 7
0 to 7
–
–
P16T12
P16T11
P16T10
–
P16T02
P16T01
P16T00
D7
D6
D5
D4
D3
D2
D1
D0
reserved
16-bit timer 1 interrupt level
reserved
16-bit timer 0 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040266
(B)
16-bit timer 0/1
interrupt
priority register
–
0 to 7
0 to 7
–
–
P16T32
P16T31
P16T30
–
P16T22
P16T21
P16T20
D7
D6
D5
D4
D3
D2
D1
D0
reserved
16-bit timer 3 interrupt level
reserved
16-bit timer 2 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040267
(B)
16-bit timer 2/3
interrupt
priority register
–
0 to 7
0 to 7
–
–
P16T52
P16T51
P16T50
–
P16T42
P16T41
P16T40
D7
D6
D5
D4
D3
D2
D1
D0
reserved
16-bit timer 5 interrupt level
reserved
16-bit timer 4 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040268
(B)
16-bit timer 4/5
interrupt
priority register
4 PERIPHERAL CIRCUITS
A-30 EPSON S1C33L03 PRODUCT PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
0 to 7
0 to 7
–
–
PSIO02
PSIO01
PSIO00
–
P8TM2
P8TM1
P8TM0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Serial interface Ch.0
interrupt level
reserved
8-bit timer 0–3 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040269
(B)
8-bit timer,
serial I/F Ch.0
interrupt
priority register
–
0 to 7
0 to 7
–
–
PAD2
PAD1
PAD0
–
PSIO12
PSIO11
PSIO10
D7
D6
D5
D4
D3
D2
D1
D0
reserved
A/D converter interrupt level
reserved
Serial interface Ch.1
interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
004026A
(B)
Serial I/F Ch.1,
A/D interrupt
priority register
–
0 to 7
–
PCTM2
PCTM1
PCTM0
D7–3
D2
D1
D0
reserved
Clock timer interrupt level –
X
X
X
–
R/W Writing 1 not allowed.004026B
(B)
Clock timer
interrupt
priority register
–
0 to 7
0 to 7
–
–
PP5L2
PP5L1
PP5L0
–
PP4L2
PP4L1
PP4L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Port input 5 interrupt level
reserved
Port input 4 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
004026C
(B)
Port input 4/5
interrupt
priority register
–
0 to 7
0 to 7
–
–
PP7L2
PP7L1
PP7L0
–
PP6L2
PP6L1
PP6L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Port input 7 interrupt level
reserved
Port input 6 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
004026D
(B)
Port input 6/7
interrupt
priority register
4 PERIPHERAL CIRCUITS
S1C33L03 PRODUCT PART EPSON A-31
A-1
A-4
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
EK1
EK0
EP3
EP2
EP1
EP0
D7–6
D5
D4
D3
D2
D1
D0
reserved
Key input 1
Key input 0
Port input 3
Port input 2
Port input 1
Port input 0
– –
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.0040270
(B) 1 Enabled 0 Disabled
Key input,
port input 0–3
interrupt
enable register
–
EIDMA
EHDM3
EHDM2
EHDM1
EHDM0
D7–5
D4
D3
D2
D1
D0
reserved
IDMA
High-speed DMA Ch.3
High-speed DMA Ch.2
High-speed DMA Ch.1
High-speed DMA Ch.0
– –
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
0 when being read.0040271
(B) 1 Enabled 0 Disabled
DMA interrupt
enable register
E16TC1
E16TU1
–
E16TC0
E16TU0
–
D7
D6
D5–4
D3
D2
D1–0
16-bit timer 1 comparison A
16-bit timer 1 comparison B
reserved
16-bit timer 0 comparison A
16-bit timer 0 comparison B
reserved
0
0
–
0
0
–
R/W
R/W
–
R/W
R/W
–
0 when being read.
0 when being read.
0040272
(B) 1 Enabled 0 Disabled
16-bit timer 0/1
interrupt
enable register –
1 Enabled 0 Disabled
–
E16TC3
E16TU3
–
E16TC2
E16TU2
–
D7
D6
D5–4
D3
D2
D1–0
16-bit timer 3 comparison A
16-bit timer 3 comparison B
reserved
16-bit timer 2 comparison A
16-bit timer 2 comparison B
reserved
0
0
–
0
0
–
R/W
R/W
–
R/W
R/W
–
0 when being read.
0 when being read.
0040273
(B) 1 Enabled 0 Disabled
16-bit timer 2/3
interrupt
enable register –
1 Enabled 0 Disabled
–
E16TC5
E16TU5
–
E16TC4
E16TU4
–
D7
D6
D5–4
D3
D2
D1–0
16-bit timer 5 comparison A
16-bit timer 5 comparison B
reserved
16-bit timer 4 comparison A
16-bit timer 4 comparison B
reserved
0
0
–
0
0
–
R/W
R/W
–
R/W
R/W
–
0 when being read.
0 when being read.
0040274
(B) 1 Enabled 0 Disabled
16-bit timer 4/5
interrupt
enable register –
1 Enabled 0 Disabled
–
–
E8TU3
E8TU2
E8TU1
E8TU0
D7–4
D3
D2
D1
D0
reserved
8-bit timer 3 underflow
8-bit timer 2 underflow
8-bit timer 1 underflow
8-bit timer 0 underflow
– –
0
0
0
0
–
R/W
R/W
R/W
R/W
0 when being read.0040275
(B) 1 Enabled 0 Disabled
8-bit timer
interrupt
enable register
–
ESTX1
ESRX1
ESERR1
ESTX0
ESRX0
ESERR0
D7–6
D5
D4
D3
D2
D1
D0
reserved
SIF Ch.1 transmit buffer empty
SIF Ch.1 receive buffer full
SIF Ch.1 receive error
SIF Ch.0 transmit buffer empty
SIF Ch.0 receive buffer full
SIF Ch.0 receive error
– –
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.0040276
(B) 1 Enabled 0 Disabled
Serial I/F
interrupt
enable register
–
EP7
EP6
EP5
EP4
ECTM
EADE
D7–6
D5
D4
D3
D2
D1
D0
reserved
Port input 7
Port input 6
Port input 5
Port input 4
Clock timer
A/D converter
– –
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.0040277
(B) 1 Enabled 0 Disabled
Port input 4–7,
clock timer,
A/D interrupt
enable register
4 PERIPHERAL CIRCUITS
A-32 EPSON S1C33L03 PRODUCT PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
FK1
FK0
FP3
FP2
FP1
FP0
D7–6
D5
D4
D3
D2
D1
D0
reserved
Key input 1
Key input 0
Port input 3
Port input 2
Port input 1
Port input 0
– –
X
X
X
X
X
X
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.0040280
(B) 1 Factor is
generated 0 No factor is
generated
Key input,
port input 0–3
interrupt factor
flag register
–
FIDMA
FHDM3
FHDM2
FHDM1
FHDM0
D7–5
D4
D3
D2
D1
D0
reserved
IDMA
High-speed DMA Ch.3
High-speed DMA Ch.2
High-speed DMA Ch.1
High-speed DMA Ch.0
– –
X
X
X
X
X
–
R/W
R/W
R/W
R/W
R/W
0 when being read.0040281
(B)
DMA interrupt
factor flag
register 1 Factor is
generated 0 No factor is
generated
F16TC1
F16TU1
–
F16TC0
F16TU0
–
D7
D6
D5–4
D3
D2
D1–0
16-bit timer 1 comparison A
16-bit timer 1 comparison B
reserved
16-bit timer 0 comparison A
16-bit timer 0 comparison B
reserved
X
X
–
X
X
–
R/W
R/W
–
R/W
R/W
–
0 when being read.
0 when being read.
0040282
(B) 1 Factor is
generated 0 No factor is
generated
16-bit timer 0/1
interrupt factor
flag register –
1 Factor is
generated 0 No factor is
generated
–
F16TC3
F16TU3
–
F16TC2
F16TU2
–
D7
D6
D5–4
D3
D2
D1–0
16-bit timer 3 comparison A
16-bit timer 3 comparison B
reserved
16-bit timer 2 comparison A
16-bit timer 2 comparison B
reserved
X
X
–
X
X
–
R/W
R/W
–
R/W
R/W
–
0 when being read.
0 when being read.
0040283
(B) 1 Factor is
generated 0 No factor is
generated
16-bit timer 2/3
interrupt factor
flag register –
1 Factor is
generated 0 No factor is
generated
–
F16TC5
F16TU5
–
F16TC4
F16TU4
–
D7
D6
D5–4
D3
D2
D1–0
16-bit timer 5 comparison A
16-bit timer 5 comparison B
reserved
16-bit timer 4 comparison A
16-bit timer 4 comparison B
reserved
X
X
–
X
X
–
R/W
R/W
–
R/W
R/W
–
0 when being read.
0 when being read.
0040284
(B) 1 Factor is
generated 0 No factor is
generated
16-bit timer 4/5
interrupt factor
flag register –
1 Factor is
generated 0 No factor is
generated
–
–
F8TU3
F8TU2
F8TU1
F8TU0
D7–4
D3
D2
D1
D0
reserved
8-bit timer 3 underflow
8-bit timer 2 underflow
8-bit timer 1 underflow
8-bit timer 0 underflow
– –
X
X
X
X
–
R/W
R/W
R/W
R/W
0 when being read.0040285
(B) 1 Factor is
generated 0 No factor is
generated
8-bit timer
interrupt factor
flag register
–
FSTX1
FSRX1
FSERR1
FSTX0
FSRX0
FSERR0
D7–6
D5
D4
D3
D2
D1
D0
reserved
SIF Ch.1 transmit buffer empty
SIF Ch.1 receive buffer full
SIF Ch.1 receive error
SIF Ch.0 transmit buffer empty
SIF Ch.0 receive buffer full
SIF Ch.0 receive error
– –
X
X
X
X
X
X
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.0040286
(B) 1 Factor is
generated 0 No factor is
generated
Serial I/F
interrupt factor
flag register
–
FP7
FP6
FP5
FP4
FCTM
FADE
D7–6
D5
D4
D3
D2
D1
D0
reserved
Port input 7
Port input 6
Port input 5
Port input 4
Clock timer
A/D converter
– –
X
X
X
X
X
X
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.0040287
(B) 1 Factor is
generated 0 No factor is
generated
Port input 4–7,
clock timer, A/D
interrupt factor
flag register
4 PERIPHERAL CIRCUITS
S1C33L03 PRODUCT PART EPSON A-33
A-1
A-4
NameAddressRegister name Bit Function Setting Init. R/W Remarks
R16TC0
R16TU0
RHDM1
RHDM0
RP3
RP2
RP1
RP0
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 0 comparison A
16-bit timer 0 comparison B
High-speed DMA Ch.1
High-speed DMA Ch.0
Port input 3
Port input 2
Port input 1
Port input 0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0040290
(B) 1 IDMA
request 0 Interrupt
request
Port input 0–3,
high-speed
DMA Ch. 0/1,
16-bit timer 0
IDMA request
register
R16TC4
R16TU4
R16TC3
R16TU3
R16TC2
R16TU2
R16TC1
R16TU1
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 4 comparison A
16-bit timer 4 comparison B
16-bit timer 3 comparison A
16-bit timer 3 comparison B
16-bit timer 2 comparison A
16-bit timer 2 comparison B
16-bit timer 1 comparison A
16-bit timer 1 comparison B
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0040291
(B) 1 IDMA
request 0 Interrupt
request
16-bit timer 1–4
IDMA request
register
RSTX0
RSRX0
R8TU3
R8TU2
R8TU1
R8TU0
R16TC5
R16TU5
D7
D6
D5
D4
D3
D2
D1
D0
SIF Ch.0 transmit buffer empty
SIF Ch.0 receive buffer full
8-bit timer 3 underflow
8-bit timer 2 underflow
8-bit timer 1 underflow
8-bit timer 0 underflow
16-bit timer 5 comparison A
16-bit timer 5 comparison B
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0040292
(B) 1 IDMA
request 0 Interrupt
request
16-bit timer 5,
8-bit timer,
serial I/F Ch.0
IDMA request
register
RP7
RP6
RP5
RP4
–
RADE
RSTX1
RSRX1
D7
D6
D5
D4
D3
D2
D1
D0
Port input 7
Port input 6
Port input 5
Port input 4
reserved
A/D converter
SIF Ch.1 transmit buffer empty
SIF Ch.1 receive buffer full
0
0
0
0
–
0
0
0
R/W
R/W
R/W
R/W
–
R/W
R/W
R/W
0 when being read.
0040293
(B) 1 IDMA
request 0 Interrupt
request
1 IDMA
request 0 Interrupt
request
–
Serial I/F Ch.1,
A/D,
port input 4–7
IDMA request
register
DE16TC0
DE16TU0
DEHDM1
DEHDM0
DEP3
DEP2
DEP1
DEP0
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 0 comparison A
16-bit timer 0 comparison B
High-speed DMA Ch.1
High-speed DMA Ch.0
Port input 3
Port input 2
Port input 1
Port input 0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0040294
(B) 1 IDMA
enabled 0 IDMA
disabled
Port input 0–3,
high-speed
DMA Ch. 0/1,
16-bit timer 0
IDMA enable
register
DE16TC4
DE16TU4
DE16TC3
DE16TU3
DE16TC2
DE16TU2
DE16TC1
DE16TU1
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 4 comparison A
16-bit timer 4 comparison B
16-bit timer 3 comparison A
16-bit timer 3 comparison B
16-bit timer 2 comparison A
16-bit timer 2 comparison B
16-bit timer 1 comparison A
16-bit timer 1 comparison B
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0040295
(B) 1 IDMA
enabled 0 IDMA
disabled
16-bit timer 1–4
IDMA enable
register
DESTX0
DESRX0
DE8TU3
DE8TU2
DE8TU1
DE8TU0
DE16TC5
DE16TU5
D7
D6
D5
D4
D3
D2
D1
D0
SIF Ch.0 transmit buffer empty
SIF Ch.0 receive buffer full
8-bit timer 3 underflow
8-bit timer 2 underflow
8-bit timer 1 underflow
8-bit timer 0 underflow
16-bit timer 5 comparison A
16-bit timer 5 comparison B
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0040296
(B) 1 IDMA
enabled 0 IDMA
disabled
16-bit timer 5,
8-bit timer,
serial I/F Ch.0
IDMA enable
register
DEP7
DEP6
DEP5
DEP4
–
DEADE
DESTX1
DESRX1
D7
D6
D5
D4
D3
D2
D1
D0
Port input 7
Port input 6
Port input 5
Port input 4
reserved
A/D converter
SIF Ch.1 transmit buffer empty
SIF Ch.1 receive buffer full
0
0
0
0
–
0
0
0
R/W
R/W
R/W
R/W
–
R/W
R/W
R/W
0 when being read.
0040297
(B) 1 IDMA
enabled 0 IDMA
disabled
1 IDMA
enabled 0 IDMA
disabled
–
Serial I/F Ch.1,
A/D,
port input 4–7
IDMA enable
register
4 PERIPHERAL CIRCUITS
A-34 EPSON S1C33L03 PRODUCT PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
HSD1S3
HSD1S2
HSD1S1
HSD1S0
HSD0S3
HSD0S2
HSD0S1
HSD0S0
D7
D6
D5
D4
D3
D2
D1
D0
High-speed DMA Ch.1
trigger set-up
High-speed DMA Ch.0
trigger set-up
0
0
0
0
0
0
0
0
R/W
R/W
0040298
(B) 0
1
2
3
4
5
6
7
8
9
A
B
C
Software trigger
K51 input (falling edge)
K51 input (rising edge)
Port 1 input
Port 5 input
8-bit timer Ch.1 underflow
16-bit timer Ch.1 compare B
16-bit timer Ch.1 compare A
16-bit timer Ch.5 compare B
16-bit timer Ch.5 compare A
SI/F Ch.1 Rx buffer full
SI/F Ch.1 Tx buffer empty
A/D conversion completion
0
1
2
3
4
5
6
7
8
9
A
B
C
Software trigger
K50 input (falling edge)
K50 input (rising edge)
Port 0 input
Port 4 input
8-bit timer Ch.0 underflow
16-bit timer Ch.0 compare B
16-bit timer Ch.0 compare A
16-bit timer Ch.4 compare B
16-bit timer Ch.4 compare A
SI/F Ch.0 Rx buffer full
SI/F Ch.0 Tx buffer empty
A/D conversion completion
High-speed
DMA Ch.0/1
trigger set-up
register
HSD3S3
HSD3S2
HSD3S1
HSD3S0
HSD2S3
HSD2S2
HSD2S1
HSD2S0
D7
D6
D5
D4
D3
D2
D1
D0
High-speed DMA Ch.3
trigger set-up
High-speed DMA Ch.2
trigger set-up
0
0
0
0
0
0
0
0
R/W
R/W
0040299
(B) 0
1
2
3
4
5
6
7
8
9
A
B
C
Software trigger
K54 input (falling edge)
K54 input (rising edge)
Port 3 input
Port 7 input
8-bit timer Ch.3 underflow
16-bit timer Ch.3 compare B
16-bit timer Ch.3 compare A
16-bit timer Ch.5 compare B
16-bit timer Ch.5 compare A
SI/F Ch.1 Rx buffer full
SI/F Ch.1 Tx buffer empty
A/D conversion completion
0
1
2
3
4
5
6
7
8
9
A
B
C
Software trigger
K53 input (falling edge)
K53 input (rising edge)
Port 2 input
Port 6 input
8-bit timer Ch.2 underflow
16-bit timer Ch.2 compare B
16-bit timer Ch.2 compare A
16-bit timer Ch.4 compare B
16-bit timer Ch.4 compare A
SI/F Ch.0 Rx buffer full
SI/F Ch.0 Tx buffer empty
A/D conversion completion
High-speed
DMA Ch.2/3
trigger set-up
register
–
HST3
HST2
HST1
HST0
D7–4
D3
D2
D1
D0
reserved
HSDMA Ch.3 software trigger
HSDMA Ch.2 software trigger
HSDMA Ch.1 software trigger
HSDMA Ch.0 software trigger
–
0
0
0
0
–
W
W
W
W
0 when being read.004029A
(B) –
1 Trigger 0 Invalid
High-speed
DMA software
trigger
register
–
DENONLY
IDMAONLY
RSTONLY
D7–3
D2
D1
D0
reserved
IDMA enable register set method
selection
IDMA request register set method
selection
Interrupt factor flag reset method
selection
– –
1
1
1
–
R/W
R/W
R/W
004029F
(B)
Flag set/reset
method select
register 1 Set only 0 RD/WR
1 Set only 0 RD/WR
1 Reset only 0 RD/WR
4 PERIPHERAL CIRCUITS
S1C33L03 PRODUCT PART EPSON A-35
A-1
A-4
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
CFK54
CFK53
CFK52
CFK51
CFK50
D7–5
D4
D3
D2
D1
D0
reserved
K54 function selection
K53 function selection
K52 function selection
K51 function selection
K50 function selection
– –
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
0 when being read.00402C0
(B) 1
#DMAREQ3
0 K54
1
#DMAREQ2
0 K53
1 #ADTRG 0 K52
1
#DMAREQ1
0 K51
1
#DMAREQ0
0 K50
K5 function
select register
–
K54D
K53D
K52D
K51D
K50D
D7–5
D4
D3
D2
D1
D0
reserved
K54 input port data
K53 input port data
K52 input port data
K51 input port data
K50 input port data
– –
–
–
–
–
–
–
R
R
R
R
R
0 when being read.00402C1
(B) 1 High 0 Low
K5 input port
data register
CFK67
CFK66
CFK65
CFK64
CFK63
CFK62
CFK61
CFK60
D7
D6
D5
D4
D3
D2
D1
D0
K67 function selection
K66 function selection
K65 function selection
K64 function selection
K63 function selection
K62 function selection
K61 function selection
K60 function selection
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00402C3
(B) 1 AD7 0 K67
1 AD6 0 K66
1 AD5 0 K65
1 AD4 0 K64
1 AD3 0 K63
1 AD2 0 K62
1 AD1 0 K61
1 AD0 0 K60
K6 function
select register
K67D
K66D
K65D
K64D
K63D
K62D
K61D
K60D
D7
D6
D5
D4
D3
D2
D1
D0
K67 input port data
K66 input port data
K65 input port data
K64 input port data
K63 input port data
K62 input port data
K61 input port data
K60 input port data
–
–
–
–
–
–
–
–
R
R
R
R
R
R
R
R
00402C4
(B) 1 High 0 LowK6 input port
data register
4 PERIPHERAL CIRCUITS
A-36 EPSON S1C33L03 PRODUCT PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
T8CH5S0
SIO3TS0
T8CH4S0
SIO3RS0
SIO2TS0
SIO3ES0
SIO2RS0
SIO2ES0
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 5 underflow
SIO Ch.3 transmit buffer empty
8-bit timer 4 underflow
SIO Ch.3 receive buffer full
SIO Ch.2 transmit buffer empty
SIO Ch.3 receive error
SIO Ch.2 receive buffer full
SIO Ch.2 receive error
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00402C5Interrupt factor
FP function
switching
register
1 SIO Ch.3
TXD Emp. 0 FP6
1 SIO Ch.3
RXD Full 0 FP4
1 SIO Ch.2
TXD Emp. 0 FP3
1 SIO Ch.3
RXD Err. 0 FP2
1 SIO Ch.2
RXD Full 0 FP1
1 SIO Ch.2
RXD Err. 0 FP0
1 T8 Ch.5 UF 0 FP7
1 T8 Ch.4 UF 0 FP5
SPT31
SPT30
SPT21
SPT20
SPT11
SPT10
SPT01
SPT00
D7
D6
D5
D4
D3
D2
D1
D0
FPT3 interrupt input port selection
FPT2 interrupt input port selection
FPT1 interrupt input port selection
FPT0 interrupt input port selection
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
00402C6
(B)
Port input
interrupt select
register 1
11 10 01 00
P23 P03 K53 K63
11 10 01 00
P22 P02 K52 K62
11 10 01 00
P21 P01 K51 K61
11 10 01 00
P20 P00 K50 K60
11 10 01 00
P27 P07 P33 K67
11 10 01 00
P26 P06 P32 K66
11 10 01 00
P25 P05 P31 K65
11 10 01 00
P24 P04 K54 K64
SPT71
SPT70
SPT61
SPT60
SPT51
SPT50
SPT41
SPT40
D7
D6
D5
D4
D3
D2
D1
D0
FPT7 interrupt input port selection
FPT6 interrupt input port selection
FPT5 interrupt input port selection
FPT4 interrupt input port selection
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
00402C7
(B)
Port input
interrupt select
register 2
1 High level
or
Rising edge
0 Low level
or
Falling
edge
SPPT7
SPPT6
SPPT5
SPPT4
SPPT3
SPPT2
SPPT1
SPPT0
D7
D6
D5
D4
D3
D2
D1
D0
FPT7 input polarity selection
FPT6 input polarity selection
FPT5 input polarity selection
FPT4 input polarity selection
FPT3 input polarity selection
FPT2 input polarity selection
FPT1 input polarity selection
FPT0 input polarity selection
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00402C8
(B)
Port input
interrupt
input polarity
select register
1 Edge 0 LevelSEPT7
SEPT6
SEPT5
SEPT4
SEPT3
SEPT2
SEPT1
SEPT0
D7
D6
D5
D4
D3
D2
D1
D0
FPT7 edge/level selection
FPT6 edge/level selection
FPT5 edge/level selection
FPT4 edge/level selection
FPT3 edge/level selection
FPT2 edge/level selection
FPT1 edge/level selection
FPT0 edge/level selection
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00402C9
(B)
Port input
interrupt
edge/level
select register
–
SPPK11
SPPK10
SPPK01
SPPK00
D7–4
D3
D2
D1
D0
reserved
FPK1 i
nterrupt input port selection
FPK0 i
nterrupt input port selection
–
0
0
0
0
–
R/W
R/W
0 when being read.00402CA
(B)
Key input
interrupt select
register
–
11 10 01 00
P2[7:4] P0[7:4] K6[7:4] K6[3:0]
11 10 01 00
P2[4:0] P0[4:0] K6[4:0] K5[4:0]
T8CH5S1
T8CH4S1
SIO3ES1
SIO2ES1
SIO3TS1
SIO3RS1
SIO2TS1
SIO2RS1
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 5 underflow
8-bit timer 4 underflow
SIO Ch.3 receive error
SIO Ch.2 receive error
SIO Ch.3 transmit buffer empty
SIO Ch.3 receive buffer full
SIO Ch.2 transmit buffer empty
SIO Ch.2 receive buffer full
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00402CBInterrupt factor
TM16 function
switching
register 1 SIO Ch.3
RXD Err. 0 TM16 Ch.3
comp.A
1 SIO Ch.2
RXD Err. 0 TM16 Ch.3
comp.B
1 SIO Ch.3
TXD Emp. 0 TM16 Ch.4
comp.A
1 SIO Ch.3
RXD Full 0 TM16 Ch.4
comp.B
1 SIO Ch.2
TXD Emp. 0 TM16 Ch.5
comp.A
1 SIO Ch.2
RXD Full 0 TM16 Ch.5
comp.B
1 T8 Ch.5 UF 0 TM16 Ch.2
comp.A
1 T8 Ch.4 UF 0 TM16 Ch.2
comp.B
4 PERIPHERAL CIRCUITS
S1C33L03 PRODUCT PART EPSON A-37
A-1
A-4
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
SCPK04
SCPK03
SCPK02
SCPK01
SCPK00
D7–5
D4
D3
D2
D1
D0
reserved
FPK04 input comparison
FPK03 input comparison
FPK02 input comparison
FPK01 input comparison
FPK00 input comparison
– –
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
0 when being read.00402CC
(B) 1 High 0 Low
Key input
interrupt
(FPK0) input
comparison
register
–
SCPK13
SCPK12
SCPK11
SCPK10
D7–4
D3
D2
D1
D0
reserved
FPK13 input comparison
FPK12 input comparison
FPK11 input comparison
FPK10 input comparison
– –
0
0
0
0
–
R/W
R/W
R/W
R/W
0 when being read.00402CD
(B) 1 High 0 Low
Key input
interrupt
(FPK1) input
comparison
register
–
SMPK04
SMPK03
SMPK02
SMPK01
SMPK00
D7–5
D4
D3
D2
D1
D0
reserved
FPK04 input mask
FPK03 input mask
FPK02 input mask
FPK01 input mask
FPK00 input mask
– –
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
0 when being read.00402CE
(B) 1 Interrupt
enabled 0 Interrupt
disabled
Key input
interrupt
(FPK0) input
mask register
–
SMPK13
SMPK12
SMPK11
SMPK10
D7–4
D3
D2
D1
D0
reserved
FPK13 input mask
FPK12 input mask
FPK11 input mask
FPK10 input mask
– –
0
0
0
0
–
R/W
R/W
R/W
R/W
0 when being read.00402CF
(B) 1 Interrupt
enabled 0 Interrupt
disabled
Key input
interrupt
(FPK1) input
mask register
CFP07
CFP06
CFP05
CFP04
CFP03
CFP02
CFP01
CFP00
D7
D6
D5
D4
D3
D2
D1
D0
P07 function selection
P06 function selection
P05 function selection
P04 function selection
P03 function selection
P02 function selection
P01 function selection
P00 function selection
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Extended functions
(0x402DF)
00402D0
(B) 1 #SRDY1 0 P07
1 #SCLK1 0 P06
1 SOUT1 0 P05
1 SIN1 0 P04
1 #SRDY0 0 P03
1 #SCLK0 0 P02
1 SOUT0 0 P01
1 SIN0 0 P00
P0 function
select register
P07D
P06D
P05D
P04D
P03D
P02D
P01D
P00D
D7
D6
D5
D4
D3
D2
D1
D0
P07 I/O port data
P06 I/O port data
P05 I/O port data
P04 I/O port data
P03 I/O port data
P02 I/O port data
P01 I/O port data
P00 I/O port data
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00402D1
(B) 1 High 0 LowP0 I/O port data
register
IOC07
IOC06
IOC05
IOC04
IOC03
IOC02
IOC01
IOC00
D7
D6
D5
D4
D3
D2
D1
D0
P07 I/O control
P06 I/O control
P05 I/O control
P04 I/O control
P03 I/O control
P02 I/O control
P01 I/O control
P00 I/O control
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
This register
indicates the values
of the I/O control
signals of the ports
when it is read. (See
detailed explanation.)
00402D2
(B) 1 Output 0 InputP0 I/O control
register
–
CFP16
CFP15
CFP14
CFP13
CFP12
CFP11
CFP10
D7
D6
D5
D4
D3
D2
D1
D0
reserved
P16 function selection
P15 function selection
P14 function selection
P13 function selection
P12 function selection
P11 function selection
P10 function selection
–
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.
Extended functions
(0x402DF)
00402D4
(B) 1 EXCL5
#DMAEND1
0 P16
1 EXCL4
#DMAEND0
0 P15
1 EXCL3
T8UF3 0 P13
1 EXCL2
T8UF2 0 P12
1 EXCL1
T8UF1 0 P11
1 EXCL0
T8UF0 0 P10
–P1 function
select register
1 FOSC1 0 P14
–
P16D
P15D
P14D
P13D
P12D
P11D
P10D
D7
D6
D5
D4
D3
D2
D1
D0
reserved
P16 I/O port data
P15 I/O port data
P14 I/O port data
P13 I/O port data
P12 I/O port data
P11 I/O port data
P10 I/O port data
–
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.00402D5
(B) 1 High 0 Low
–
P1 I/O port data
register
4 PERIPHERAL CIRCUITS
A-38 EPSON S1C33L03 PRODUCT PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
IOC16
IOC15
IOC14
IOC13
IOC12
IOC11
IOC10
D7
D6
D5
D4
D3
D2
D1
D0
reserved
P16 I/O control
P15 I/O control
P14 I/O control
P13 I/O control
P12 I/O control
P11 I/O control
P10 I/O control
–
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.
This register
indicates the values
of the I/O control
signals of the ports
when it is read. (See
detailed explanation.)
00402D6
(B) 1Output 0Input
–P1 I/O control
register
–
SSRDY3
SSCLK3
SSOUT3
SSIN3
D7–4
D3
D2
D1
D0
reserved
Serial I/F Ch.3 SRDY selection
Serial I/F Ch.3 SCLK selection
Serial I/F Ch.3 SOUT selection
Serial I/F Ch.3 SIN selection
– –
0
0
0
0
–
R/W
R/W
R/W
R/W
00402D7Port SIO
function
extension
register
1 #SRDY3 0
P32/
#DMAACK0
1 #SCLK3 0
P15/EXCL4/
#DMAEND0
1 SOUT3 0
P16/EXCL5/
#DMAEND1
1 SIN3 0
P33/
#DMAACK1
CFP27
CFP26
CFP25
CFP24
CFP23
CFP22
CFP21
CFP20
D7
D6
D5
D4
D3
D2
D1
D0
P27 function selection
P26 function selection
P25 function selection
P24 function selection
P23 function selection
P22 function selection
P21 function selection
P20 function selection
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W Ext. func.(0x402DF)
00402D8
(B) 1 TM5 0 P27
1 TM4 0 P26
1 TM3 0 P25
1 TM2 0 P24
1 TM1 0 P23
1 TM0 0 P22
1 #DWE 0 P21
1 #DRD 0 P20
P2 function
select register
P27D
P26D
P25D
P24D
P23D
P22D
P21D
P20D
D7
D6
D5
D4
D3
D2
D1
D0
P27 I/O port data
P26 I/O port data
P25 I/O port data
P24 I/O port data
P23 I/O port data
P22 I/O port data
P21 I/O port data
P20 I/O port data
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00402D9
(B) 1 High 0 LowP2 I/O port data
register
IOC27
IOC26
IOC25
IOC24
IOC23
IOC22
IOC21
IOC20
D7
D6
D5
D4
D3
D2
D1
D0
P27 I/O control
P26 I/O control
P25 I/O control
P24 I/O control
P23 I/O control
P22 I/O control
P21 I/O control
P20 I/O control
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
This register
indicates the values
of the I/O control
signals of the ports
when it is read. (See
detailed explanation.)
00402DA
(B) 1 Output 0 InputP2 I/O control
register
–
SSRDY2
SSCLK2
SSOUT2
SSIN2
D7–4
D3
D2
D1
D0
reserved
Serial I/F Ch.2 SRDY selection
Serial I/F Ch.2 SCLK selection
Serial I/F Ch.2 SOUT selection
Serial I/F Ch.2 SIN selection
–
0
0
0
0
–
R/W
R/W
R/W
R/W
00402DB 1 #SRDY2 0 P24/TM2
1 #SCLK2 0 P25/TM3
1 SOUT2 0 P26/TM4
1 SIN2 0 P27/TM5
Port SIO
function
extension
register
–
–
CFP35
CFP34
CFP33
CFP32
CFP31
CFP30
D7–6
D5
D4
D3
D2
D1
D0
reserved
P35 function selection
P34 function selection
P33 function selection
P32 function selection
P31 function selection
P30 function selection
–
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.
Ext. func.(0x402DF)
00402DC
(B) –P3 function
select register 1 #BUSACK 0 P35
1 #BUSREQ
#CE6 0 P34
1
#DMAACK0
0 P32
1 #BUSGET 0 P31
1 #WAIT
#CE4/#CE5 0 P30
1
#DMAACK1
0 P33
–
P35D
P34D
P33D
P32D
P31D
P30D
D7–6
D5
D4
D3
D2
D1
D0
reserved
P35 I/O port data
P34 I/O port data
P33 I/O port data
P32 I/O port data
P31 I/O port data
P30 I/O port data
–
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.00402DD
(B) 1 High 0 Low
–
P3 I/O port data
register
–
IOC35
IOC34
IOC33
IOC32
IOC31
IOC30
D7–6
D5
D4
D3
D2
D1
D0
reserved
P35 I/O control
P34 I/O control
P33 I/O control
P32 I/O control
P31 I/O control
P30 I/O control
–
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.
This register
indicates the values
of the I/O control
signals of the ports
when it is read. (See
detailed explanation.)
00402DE
(B) 1 Output 0 Input
–P3 I/O control
register
4 PERIPHERAL CIRCUITS
S1C33L03 PRODUCT PART EPSON A-39
A-1
A-4
NameAddressRegister name Bit Function Setting Init. R/W Remarks
CFEX7
CFEX6
CFEX5
CFEX4
CFEX3
CFEX2
CFEX1
CFEX0
D7
D6
D5
D4
D3
D2
D1
D0
P07 port extended function
P06 port extended function
P05 port extended function
P04 port extended function
P31 port extended function
P21 port extended function
P10, P11, P13 port extended
function
P12, P14 port extended function
0
0
0
0
0
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00402DF
(B)
Port function
extension
register
1
#DMAEND3
0 P07, etc.
1
#DMAACK3
0 P06, etc.
1
#DMAEND2
0 P05, etc.
1
#DMAACK2
0 P04, etc.
1 #GARD 0 P31, etc.
1 #GAAS 0 P21, etc.
1 DST0
DST1
DPC0
0 P10, etc.
P11, etc.
P13, etc.
1 DST2
DCLK 0 P12, etc.
P14, etc.
–
–
A18SZ
A18DF1
A18DF0
–
A18WT2
A18WT1
A18WT0
–
A16SZ
A16DF1
A16DF0
–
A16WT2
A16WT1
A16WT0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Areas 18–17 device size selection
Areas 18–17
output disable delay time
reserved
Areas 18–17 wait control
reserved
Areas 16–15 device size selection
Areas 16–15
output disable delay time
reserved
Areas 16–15 wait control
–
–
–
1 8 bits 0 16 bits
1 8 bits 0 16 bits –
0
1
1
–
1
1
1
–
0
1
1
–
1
1
1
–
R/W
R/W
–
R/W
–
R/W
R/W
–
R/W
0 when being read.
0 when being read.
0 when being read.
0 when being read.
0048120
(HW)
Areas 18–15
set-up register
1
1
0
0
1
0
1
0
A18DF[1:0] Number of cycles
3.5
2.5
1.5
0.5
1
1
0
0
1
0
1
0
A16DF[1:0] Number of cycles
3.5
2.5
1.5
0.5
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A18WT[2:0] Wait cycles
7
6
5
4
3
2
1
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A16WT[2:0] Wait cycles
7
6
5
4
3
2
1
0
–
A14DRA
A13DRA
A14SZ
A14DF1
A14DF0
–
A14WT2
A14WT1
A14WT0
DF–9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Area 14 DRAM selection
Area 13 DRAM selection
Areas 14–13 device size selection
Areas 14–13
output disable delay time
reserved
Areas 14–13 wait control
–
–
1 Used 0 Not used
1 Used 0 Not used
1 8 bits 0 16 bits
–
0
0
0
1
1
–
1
1
1
–
R/W
R/W
R/W
R/W
–
R/W
0 when being read.
0 when being read.
0048122
(HW)
1
1
0
0
1
0
1
0
A14DF[1:0] Number of cycles
3.5
2.5
1.5
0.5
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A14WT[2:0] Wait cycles
7
6
5
4
3
2
1
0
Areas 14–13
set-up register
4 PERIPHERAL CIRCUITS
A-40 EPSON S1C33L03 PRODUCT PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
A12SZ
A12DF1
A12DF0
–
A12WT2
A12WT1
A12WT0
DF–7
D6
D5
D4
D3
D2
D1
D0
reserved
Areas 12–11 device size selection
Areas 12–11
output disable delay time
reserved
Areas 12–11 wait control
–
–
1 8 bits 0 16 bits –
0
1
1
–
1
1
1
–
R/W
R/W
–
R/W
0 when being read.
0 when being read.
0048124
(HW)
Areas 12–11
set-up register
1
1
0
0
1
0
1
0
A18DF[1:0] Number of cycles
3.5
2.5
1.5
0.5
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A18WT[2:0] Wait cycles
7
6
5
4
3
2
1
0
–
A10IR2
A10IR1
A10IR0
–
A10BW1
A10BW0
A10DRA
A9DRA
A10SZ
A10DF1
A10DF0
–
A10WT2
A10WT1
A10WT0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Area 10 internal ROM size
selection
reserved
Areas 10–9
burst ROM
burst read cycle wait control
Area 10 burst ROM selection
Area 9 burst ROM selection
Areas 10–9 device size selection
Areas 10–9
output disable delay time
reserved
Areas 10–9 wait control
–
–
–
1 Used 0 Not used
1 Used 0 Not used
1 8 bits 0 16 bits
–
1
1
1
–
0
0
0
0
0
1
1
–
1
1
1
–
R/W
–
R/W
R/W
R/W
R/W
R/W
–
R/W
0 when being read.
0 when being read.
0 when being read.
0048126
(HW)
1
1
0
0
1
0
1
0
A10BW[1:0] Wait cycles
3
2
1
0
1
1
0
0
1
0
1
0
A10DF[1:0] Number of cycles
3.5
2.5
1.5
0.5
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A10IR[2:0] ROM size
2MB
1MB
512KB
256KB
128KB
64KB
32KB
16KB
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A10WT[2:0] Wait cycles
7
6
5
4
3
2
1
0
Areas 10–9
set-up register
–
A8DRA
A7DRA
A8SZ
A8DF1
A8DF0
–
A8WT2
A8WT1
A8WT0
DF–9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Area 8 DRAM selection
Area 7 DRAM selection
Areas 8–7 device size selection
Areas 8–7
output disable delay time
reserved
Areas 8–7 wait control
–
–
1 Used 0 Not used
1 Used 0 Not used
1 8 bits 0 16 bits
–
0
0
0
1
1
–
1
1
1
–
R/W
R/W
R/W
R/W
–
R/W
0 when being read.
0 when being read.
0048128
(HW)
Areas 8–7
set-up register
1
1
0
0
1
0
1
0
A8DF[1:0] Number of cycles
3.5
2.5
1.5
0.5
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A8WT[2:0] Wait cycles
7
6
5
4
3
2
1
0
4 PERIPHERAL CIRCUITS
S1C33L03 PRODUCT PART EPSON A-41
A-1
A-4
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
A6DF1
A6DF0
–
A6WT2
A6WT1
A6WT0
–
A5SZ
A5DF1
A5DF0
–
A5WT2
A5WT1
A5WT0
DF–E
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Area 6
output disable delay time
reserved
Area 6 wait control
reserved
Areas 5–4 device size selection
Areas 5–4
output disable delay time
reserved
Areas 5–4 wait control
–
–
–
18 bits 016 bits
–
1
1
–
1
1
1
–
0
1
1
–
1
1
1
–
R/W
–
R/W
–
R/W
R/W
–
R/W
0 when being read.
0 when being read.
0 when being read.
0 when being read.
004812A
(HW)
Areas 6–4
set-up register 1
1
0
0
1
0
1
0
A6DF[1:0] Number of cycles
3.5
2.5
1.5
0.5
1
1
0
0
1
0
1
0
A5DF[1:0] Number of cycles
3.5
2.5
1.5
0.5
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A6WT[2:0] Wait cycles
7
6
5
4
3
2
1
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A5WT[2:0] Wait cycles
7
6
5
4
3
2
1
0
TBRP7
TBRP6
TBRP5
TBRP4
TBRP3
TBRP2
TBRP1
TBRP0
D7
D6
D5
D4
D3
D2
D1
D0
TTBR register write protect 0
0
0
0
0
0
0
0
WUndefined in read.004812D
(B) Writing 01011001 (0x59)
removes the TTBR (0x48134)
write protection.
Writing other data sets the
write protection.
TTBR write
protect register
RBCLK
–
RBST8
REDO
RCA1
RCA0
RPC2
RPC1
RPC0
RRA1
RRA0
–
SBUSST
SEMAS
SEPD
SWAITE
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BCLK output control
reserved
Burst ROM burst mode selection
DRAM page mode selection
Column address size selection
Refresh enable
Refresh method selection
Refresh RPC delay setup
Refresh RAS pulse width
selection
reserved
External interface method selection
External bus master setup
External power-down control
#WAIT enable
–
–
1Fixed at H 0Enabled
1
8-successive
0
4-successive
1Enabled 0Disabled
1Self-refresh 0
CBR-refresh
12.0 01.0
1#BSL 0A0
1Existing 0Nonexistent
1Enabled 0Disabled
1Enabled 0Disabled
1EDO 0Fast page
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
–
R/W
R/W
R/W
R/W
Writing 1 not allowed.
Writing 1 not allowed.
004812E
(HW)
1
1
0
0
1
0
1
0
RCA[1:0] Size
11
10
9
8
1
1
0
0
1
0
1
0
RRA[1:0] Number of cycles
5
4
3
2
Bus control
register
4 PERIPHERAL CIRCUITS
A-42 EPSON S1C33L03 PRODUCT PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
1 Successive 0 Normal
–
A3EEN
CEFUNC1
CEFUNC0
CRAS
RPRC1
RPRC0
–
CASC1
CASC0
–
RASC1
RASC0
DF–C
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Area 3 emulation
#CE pin function selection
Successive RAS mode setup
DRAM
RAS precharge cycles selection
reserved
DRAM
CAS cycles selection
reserved
DRAM
RAS cycles selection
– –
1
0
0
0
0
0
–
0
0
–
0
0
–
R/W
R/W
R/W
R/W
–
R/W
–
R/W
0 when being read.
0 when being read.
0 when being read.
0048130
(HW)
1
0
0
x
1
0
CEFUNC[1:0]
#CE output
#CE7/8..#CE17/18
#CE6..#CE17
#CE4..#CE10
1
1
0
0
1
0
1
0
RPRC[1:0] Number of cycles
4
3
2
1
–
1
1
0
0
1
0
1
0
CASC[1:0] Number of cycles
4
3
2
1
–
1
1
0
0
1
0
1
0
RASC[1:0] Number of cycles
4
3
2
1
DRAM timing
set-up register 1
Internal ROM
0 Emulation
–
1 Internal
access 0 External
access
1 Internal
access 0 External
access
1 Big endian 0
Little endian
A18IO
A16IO
A14IO
A12IO
–
A8IO
A6IO
A5IO
A18EC
A16EC
A14EC
A12EC
A10EC
A8EC
A6EC
A5EC
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Area 18, 17 internal/external access
Area 16, 15 internal/external access
Area 14, 13 internal/external access
Area 12, 11 internal/external access
reserved
Area 8, 7 internal/external
access
Area 6 internal/external
access
Area 5, 4 internal/external
access
Area 18, 17 endian control
Area 16, 15 endian control
Area 14, 13 endian control
Area 12, 11 endian control
Area 10, 9 endian control
Area 8, 7 endian control
Area 6 endian control
Area 5, 4 endian control
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.
0048132
(HW)
Access control
register
TTBR15
TTBR14
TTBR13
TTBR12
TTBR11
TTBR10
TTBR09
TTBR08
TTBR07
TTBR06
TTBR05
TTBR04
TTBR03
TTBR02
TTBR01
TTBR00
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Trap table base address [15:10]
Trap table base address [9:0] Fixed at 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R0 when being read.
Writing 1 not allowed.
0048134
(HW)
TTBR low-
order register
TTBR33
TTBR32
TTBR31
TTBR30
TTBR2B
TTBR2A
TTBR29
TTBR28
TTBR27
TTBR26
TTBR25
TTBR24
TTBR23
TTBR22
TTBR21
TTBR20
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Trap table base address [31:28]
Trap table base address [27:16]
Fixed at 0
0x0C0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
R
R/W
0 when being read.
Writing 1 not allowed.
0048136
(HW)
TTBR high-
order register
4 PERIPHERAL CIRCUITS
S1C33L03 PRODUCT PART EPSON A-43
A-1
A-4
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
1 Enabled 0 Disabled
1 Enabled 0 Disabled
A18AS
A16AS
A14AS
A12AS
–
A8AS
A6AS
A5AS
A18RD
A16RD
A14RD
A12RD
–
A8RD
A6RD
A5RD
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Area 18, 17 address strobe signal
Area 16, 15 address strobe signal
Area 14, 13 address strobe signal
Area 12, 11 address strobe signal
reserved
Area 8, 7 address strobe signal
Area 6 address strobe signal
Area 5, 4 address strobe signal
Area 18, 17 read signal
Area 16, 15 read signal
Area 14, 13 read signal
Area 12, 11 read signal
reserved
Area 8, 7 read signal
Area 6 read signal
Area 5, 4 read signal
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
–
R/W
R/W
R/W
0 when being read.
0 when being read.
0048138
(HW)
G/A read signal
control register
–
1 Enabled 0 Disabled
1 Enabled 0 Disabled
–
A1X1MD
–
BCLKSEL1
BCLKSEL0
D7–4
D3
D2
D1
D0
reserved
Area 1 access-speed
reserved
BCLK output clock selection 1
1
0
0
1
0
1
0
BCLKSEL[1:0]
–
–BCLK
PLL_CLK
OSC3_CLK
BCU_CLK
CPU_CLK
0
0
0
0
0
–
R/W
–
R/W
0 when being read.
x2 speed mode only
0 when being read.
004813A
(B)
BCLK select
register 1 2 cycles 0 4 cycles
4 PERIPHERAL CIRCUITS
A-44 EPSON S1C33L03 PRODUCT PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
0 to 65535CR0A15
CR0A14
CR0A13
CR0A12
CR0A11
CR0A10
CR0A9
CR0A8
CR0A7
CR0A6
CR0A5
CR0A4
CR0A3
CR0A2
CR0A1
CR0A0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 0 comparison data A
CR0A15 = MSB
CR0A0 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048180
(HW)
16-bit timer 0
comparison
register A
0 to 65535CR0B15
CR0B14
CR0B13
CR0B12
CR0B11
CR0B10
CR0B9
CR0B8
CR0B7
CR0B6
CR0B5
CR0B4
CR0B3
CR0B2
CR0B1
CR0B0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 0 comparison data B
CR0B15 = MSB
CR0B0 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048182
(HW)
16-bit timer 0
comparison
register B
0 to 65535TC015
TC014
TC013
TC012
TC011
TC010
TC09
TC08
TC07
TC06
TC05
TC04
TC03
TC02
TC01
TC00
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 0 counter data
TC015 = MSB
TC00 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R0048184
(HW)
16-bit timer 0
counter data
register
–
SELFM0
SELCRB0
OUTINV0
CKSL0
PTM0
PRESET0
PRUN0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
16-bit timer 0 fine mode selection
16-bit timer 0 comparison buffer
16-bit timer 0 output inversion
16-bit timer 0 input clock selection
16-bit timer 0 clock output control
16-bit timer 0 reset
16-bit timer 0 Run/Stop control
0
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
W
R/W
0 when being read.
0 when being read.
0048186
(B) –
1 Enabled 0 Disabled
1 Fine mode 0 Normal
1 Invert 0 Normal
1
External clock
0
Internal clock
1 On 0 Off
1 Reset 0 Invalid
1 Run 0 Stop
16-bit timer 0
control register
4 PERIPHERAL CIRCUITS
S1C33L03 PRODUCT PART EPSON A-45
A-1
A-4
NameAddressRegister name Bit Function Setting Init. R/W Remarks
0 to 65535CR1A15
CR1A14
CR1A13
CR1A12
CR1A11
CR1A10
CR1A9
CR1A8
CR1A7
CR1A6
CR1A5
CR1A4
CR1A3
CR1A2
CR1A1
CR1A0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 1 comparison data A
CR1A15 = MSB
CR1A0 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048188
(HW)
16-bit timer 1
comparison
register A
0 to 65535CR1B15
CR1B14
CR1B13
CR1B12
CR1B11
CR1B10
CR1B9
CR1B8
CR1B7
CR1B6
CR1B5
CR1B4
CR1B3
CR1B2
CR1B1
CR1B0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 1 comparison data B
CR1B15 = MSB
CR1B0 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W004818A
(HW)
16-bit timer 1
comparison
register B
0 to 65535TC115
TC114
TC113
TC112
TC111
TC110
TC19
TC18
TC17
TC16
TC15
TC14
TC13
TC12
TC11
TC10
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 1 counter data
TC115 = MSB
TC10 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R004818C
(HW)
16-bit timer 1
counter data
register
–
SELFM1
SELCRB1
OUTINV1
CKSL1
PTM1
PRESET1
PRUN1
D7
D6
D5
D4
D3
D2
D1
D0
reserved
16-bit timer 1 fine mode selection
16-bit timer 1 comparison buffer
16-bit timer 1 output inversion
16-bit timer 1 input clock selection
16-bit timer 1 clock output control
16-bit timer 1 reset
16-bit timer 1 Run/Stop control
0
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
W
R/W
0 when being read.
0 when being read.
004818E
(B) –
1 Enabled 0 Disabled
1 Fine mode 0 Normal
1 Invert 0 Normal
1
External clock
0
Internal clock
1 On 0 Off
1 Reset 0 Invalid
1 Run 0 Stop
16-bit timer 1
control register
4 PERIPHERAL CIRCUITS
A-46 EPSON S1C33L03 PRODUCT PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
0 to 65535CR2A15
CR2A14
CR2A13
CR2A12
CR2A11
CR2A10
CR2A9
CR2A8
CR2A7
CR2A6
CR2A5
CR2A4
CR2A3
CR2A2
CR2A1
CR2A0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 2 comparison data A
CR2A15 = MSB
CR2A0 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048190
(HW)
16-bit timer 2
comparison
register A
0 to 65535CR2B15
CR2B14
CR2B13
CR2B12
CR2B11
CR2B10
CR2B9
CR2B8
CR2B7
CR2B6
CR2B5
CR2B4
CR2B3
CR2B2
CR2B1
CR2B0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 2 comparison data B
CR2B15 = MSB
CR2B0 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048192
(HW)
16-bit timer 2
comparison
register B
0 to 65535TC215
TC214
TC213
TC212
TC211
TC210
TC29
TC28
TC27
TC26
TC25
TC24
TC23
TC22
TC21
TC20
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 2 counter data
TC215 = MSB
TC20 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R0048194
(HW)
16-bit timer 2
counter data
register
–
SELFM2
SELCRB2
OUTINV2
CKSL2
PTM2
PRESET2
PRUN2
D7
D6
D5
D4
D3
D2
D1
D0
reserved
16-bit timer 2 fine mode selection
16-bit timer 2 comparison buffer
16-bit timer 2 output inversion
16-bit timer 2 input clock selection
16-bit timer 2 clock output control
16-bit timer 2 reset
16-bit timer 2 Run/Stop control
0
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
W
R/W
0 when being read.
0 when being read.
0048196
(B) –
1 Enabled 0 Disabled
1 Fine mode 0 Normal
1 Invert 0 Normal
1
External clock
0
Internal clock
1 On 0 Off
1 Reset 0 Invalid
1 Run 0 Stop
16-bit timer 2
control register
4 PERIPHERAL CIRCUITS
S1C33L03 PRODUCT PART EPSON A-47
A-1
A-4
NameAddressRegister name Bit Function Setting Init. R/W Remarks
0 to 65535CR3A15
CR3A14
CR3A13
CR3A12
CR3A11
CR3A10
CR3A9
CR3A8
CR3A7
CR3A6
CR3A5
CR3A4
CR3A3
CR3A2
CR3A1
CR3A0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 3 comparison data A
CR3A15 = MSB
CR3A0 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048198
(HW)
16-bit timer 3
comparison
register A
0 to 65535CR3B15
CR3B14
CR3B13
CR3B12
CR3B11
CR3B10
CR3B9
CR3B8
CR3B7
CR3B6
CR3B5
CR3B4
CR3B3
CR3B2
CR3B1
CR3B0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 3 comparison data B
CR3B15 = MSB
CR3B0 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W004819A
(HW)
16-bit timer 3
comparison
register B
0 to 65535TC315
TC314
TC313
TC312
TC311
TC310
TC39
TC38
TC37
TC36
TC35
TC34
TC33
TC32
TC31
TC30
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 3 counter data
TC315 = MSB
TC30 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R004819C
(HW)
16-bit timer 3
counter data
register
–
SELFM3
SELCRB3
OUTINV3
CKSL3
PTM3
PRESET3
PRUN3
D7
D6
D5
D4
D3
D2
D1
D0
reserved
16-bit timer 3 fine mode selection
16-bit timer 3 comparison buffer
16-bit timer 3 output inversion
16-bit timer 3 input clock selection
16-bit timer 3 clock output control
16-bit timer 3 reset
16-bit timer 3 Run/Stop control
0
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
W
R/W
0 when being read.
0 when being read.
004819E
(B) –
1 Enabled 0 Disabled
1 Fine mode 0 Normal
1 Invert 0 Normal
1
External clock
0
Internal clock
1 On 0 Off
1 Reset 0 Invalid
1 Run 0 Stop
16-bit timer 3
control register
4 PERIPHERAL CIRCUITS
A-48 EPSON S1C33L03 PRODUCT PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
0 to 65535CR4A15
CR4A14
CR4A13
CR4A12
CR4A11
CR4A10
CR4A9
CR4A8
CR4A7
CR4A6
CR4A5
CR4A4
CR4A3
CR4A2
CR4A1
CR4A0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 4 comparison data A
CR4A15 = MSB
CR4A0 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W00481A0
(HW)
16-bit timer 4
comparison
register A
0 to 65535CR4B15
CR4B14
CR4B13
CR4B12
CR4B11
CR4B10
CR4B9
CR4B8
CR4B7
CR4B6
CR4B5
CR4B4
CR4B3
CR4B2
CR4B1
CR4B0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 4 comparison data B
CR4B15 = MSB
CR4B0 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W00481A2
(HW)
16-bit timer 4
comparison
register B
0 to 65535TC415
TC414
TC413
TC412
TC411
TC410
TC49
TC48
TC47
TC46
TC45
TC44
TC43
TC42
TC41
TC40
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 4 counter data
TC415 = MSB
TC40 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R00481A4
(HW)
16-bit timer 4
counter data
register
–
SELFM4
SELCRB4
OUTINV4
CKSL4
PTM4
PRESET4
PRUN4
D7
D6
D5
D4
D3
D2
D1
D0
reserved
16-bit timer 4 fine mode selection
16-bit timer 4 comparison buffer
16-bit timer 4 output inversion
16-bit timer 4 input clock selection
16-bit timer 4 clock output control
16-bit timer 4 reset
16-bit timer 4 Run/Stop control
0
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
W
R/W
0 when being read.
0 when being read.
00481A6
(B) –
1 Enabled 0 Disabled
1 Fine mode 0 Normal
1 Invert 0 Normal
1
External clock
0
Internal clock
1 On 0 Off
1 Reset 0 Invalid
1 Run 0 Stop
16-bit timer 4
control register
4 PERIPHERAL CIRCUITS
S1C33L03 PRODUCT PART EPSON A-49
A-1
A-4
NameAddressRegister name Bit Function Setting Init. R/W Remarks
0 to 65535CR5A15
CR5A14
CR5A13
CR5A12
CR5A11
CR5A10
CR5A9
CR5A8
CR5A7
CR5A6
CR5A5
CR5A4
CR5A3
CR5A2
CR5A1
CR5A0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 5 comparison data A
CR5A15 = MSB
CR5A0 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W00481A8
(HW)
16-bit timer 5
comparison
register A
0 to 65535CR5B15
CR5B14
CR5B13
CR5B12
CR5B11
CR5B10
CR5B9
CR5B8
CR5B7
CR5B6
CR5B5
CR5B4
CR5B3
CR5B2
CR5B1
CR5B0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 5 comparison data B
CR5B15 = MSB
CR5B0 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W00481AA
(HW)
16-bit timer 5
comparison
register B
0 to 65535TC515
TC514
TC513
TC512
TC511
TC510
TC59
TC58
TC57
TC56
TC55
TC54
TC53
TC52
TC51
TC50
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 5 counter data
TC515 = MSB
TC50 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R00481AC
(HW)
16-bit timer 5
counter data
register
–
SELFM5
SELCRB5
OUTINV5
CKSL5
PTM5
PRESET5
PRUN5
D7
D6
D5
D4
D3
D2
D1
D0
reserved
16-bit timer 5 fine mode selection
16-bit timer 5 comparison buffer
16-bit timer 5 output inversion
16-bit timer 5 input clock selection
16-bit timer 5 clock output control
16-bit timer 5 reset
16-bit timer 5 Run/Stop control
0
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
W
R/W
0 when being read.
0 when being read.
00481AE
(B) –
1 Enabled 0 Disabled
1 Fine mode 0 Normal
1 Invert 0 Normal
1
External clock
0
Internal clock
1 On 0 Off
1 Reset 0 Invalid
1 Run 0 Stop
16-bit timer 5
control register
4 PERIPHERAL CIRCUITS
A-50 EPSON S1C33L03 PRODUCT PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
DBASEL15
DBASEL14
DBASEL13
DBASEL12
DBASEL11
DBASEL10
DBASEL9
DBASEL8
DBASEL7
DBASEL6
DBASEL5
DBASEL4
DBASEL3
DBASEL2
DBASEL1
DBASEL0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
IDMA base address
low-order 16 bits
(Initial value: 0x0C003A0)
0
0
0
0
0
0
1
1
1
0
1
0
0
0
0
0
R/W0048200
(HW)
IDMA base
address low-
order register
––
DBASEH11
DBASEH10
DBASEH9
DBASEH8
DBASEH7
DBASEH6
DBASEH5
DBASEH4
DBASEH3
DBASEH2
DBASEH1
DBASEH0
DF–C
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
IDMA base address
high-order 12 bits
(Initial value: 0x0C003A0)
–
0
0
0
0
1
1
0
0
0
0
0
0
–
R/W Undefined in read.0048202
(HW)
IDMA base
address
high-order
register
0 to 127
DSTART
DCHN
D7
D6–0 IDMA start
IDMA channel number 1 IDMA start 0 Stop 0
0R/W
R/W
0048204
(B)
IDMA start
register
––
IDMAEN
D7–1
D0 reserved
IDMA enable 1 Enabled 0 Disabled –
0–
R/W
0048205
(B)
IDMA enable
register
4 PERIPHERAL CIRCUITS
S1C33L03 PRODUCT PART EPSON A-51
A-1
A-4
NameAddressRegister name Bit Function Setting Init. R/W Remarks
TC0_L7
TC0_L6
TC0_L5
TC0_L4
TC0_L3
TC0_L2
TC0_L1
TC0_L0
BLKLEN07
BLKLEN06
BLKLEN05
BLKLEN04
BLKLEN03
BLKLEN02
BLKLEN01
BLKLEN00
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.0 transfer c
ounter[7:0]
(block transfer mode)
Ch.0 transfer counter[15:8]
(single/successive transfer mode)
Ch.0 block length
(block transfer mode)
Ch.0 transfer counter[7:0]
(single/successive transfer mode)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
0048220
(HW)
High-speed
DMA Ch.0
transfer
counter
register
–
–
DUALM0
D0DIR
–
TC0_H7
TC0_H6
TC0_H5
TC0_H4
TC0_H3
TC0_H2
TC0_H1
TC0_H0
DF
DE
DD–8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.0 address mode selection
D) Invalid
S) Ch.0 transfer direction control
reserved
Ch.0 transfer counter[15:8]
(block transfer mode)
Ch.0 transfer counter[23:16]
(single/successive transfer mode)
1 Dual addr 0 Single addr
1
Memory WR
0
Memory RD
0
–
0
–
X
X
X
X
X
X
X
X
R/W
–
R/W
–
R/W Undefined in read.
0048222
(HW)
High-speed
DMA Ch.0
control register
Note:
D) Dual address
mode
S) Single
address
mode
S0ADRL15
S0ADRL14
S0ADRL13
S0ADRL12
S0ADRL11
S0ADRL10
S0ADRL9
S0ADRL8
S0ADRL7
S0ADRL6
S0ADRL5
S0ADRL4
S0ADRL3
S0ADRL2
S0ADRL1
S0ADRL0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D) Ch.0 source address[15:0]
S) Ch.0 memory address[15:0] X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048224
(HW)
High-speed
DMA Ch.0
low-order
source address
set-up register
Note:
D) Dual address
mode
S) Single
address
mode
–
DATSIZE0
S0IN1
S0IN0
S0ADRH11
S0ADRH10
S0ADRH9
S0ADRH8
S0ADRH7
S0ADRH6
S0ADRH5
S0ADRH4
S0ADRH3
S0ADRH2
S0ADRH1
S0ADRH0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Ch.0 transfer data size
D) Ch.0 source address control
S) Ch.0 memory address control
D) Ch.0 source address[27:16]
S) Ch.0 memory address[27:16]
–
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
–
R/W
R/W
R/W
0048226
(HW) 1 Half word 0 Byte
High-speed
DMA Ch.0
high-order
source address
set-up register
Note:
D) Dual address
mode
S) Single
address
mode
1
1
0
0
1
0
1
0
S0IN[1:0] Inc/dec
Inc.(no init)
Inc.(init)
Dec.(no init)
Fixed
–
4 PERIPHERAL CIRCUITS
A-52 EPSON S1C33L03 PRODUCT PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
D0ADRL15
D0ADRL14
D0ADRL13
D0ADRL12
D0ADRL11
D0ADRL10
D0ADRL9
D0ADRL8
D0ADRL7
D0ADRL6
D0ADRL5
D0ADRL4
D0ADRL3
D0ADRL2
D0ADRL1
D0ADRL0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D) Ch.0 destination address[15:0]
S) Invalid X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048228
(HW)
High-speed
DMA Ch.0
low-order
destination
address set-up
register
Note:
D) Dual address
mode
S) Single
address
mode
D0MOD1
D0MOD0
D0IN1
D0IN0
D0ADRH11
D0ADRH10
D0ADRH9
D0ADRH8
D0ADRH7
D0ADRH6
D0ADRH5
D0ADRH4
D0ADRH3
D0ADRH2
D0ADRH1
D0ADRH0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.0 transfer mode
D) Ch.0 destination address
control
S) Invalid
D) Ch.0 destination
address[27:16]
S) Invalid
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
004822A
(HW)
High-speed
DMA Ch.0
high-order
destination
address set-up
register
Note:
D) Dual address
mode
S) Single
address
mode
1
1
0
0
1
0
1
0
D0MOD[1:0] Mode
Invalid
Block
Successive
Single
1
1
0
0
1
0
1
0
D0IN[1:0] Inc/dec
Inc.(no init)
Inc.(init)
Dec.(no init)
Fixed
––
HS0_EN
DF–1
D0
reserved
Ch.0 enable 1 Enable 0 Disable
–
0
–
R/W
Undefined in read.004822C
(HW)
High-speed
DMA Ch.0
enable register
––
HS0_TF
DF–1
D0
reserved
Ch.0 trigger flag clear (writing)
Ch.0 trigger flag status (reading) 1 Clear 0
No operation
1 Set 0 Cleared
–
0
–
R/W
Undefined in read.004822E
(HW)
High-speed
DMA Ch.0
trigger flag
register
4 PERIPHERAL CIRCUITS
S1C33L03 PRODUCT PART EPSON A-53
A-1
A-4
NameAddressRegister name Bit Function Setting Init. R/W Remarks
TC1_L7
TC1_L6
TC1_L5
TC1_L4
TC1_L3
TC1_L2
TC1_L1
TC1_L0
BLKLEN17
BLKLEN16
BLKLEN15
BLKLEN14
BLKLEN13
BLKLEN12
BLKLEN11
BLKLEN10
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.1 transfer c
ounter[7:0]
(block transfer mode)
Ch.1 transfer counter[15:8]
(single/successive transfer mode)
Ch.1 block length
(block transfer mode)
Ch.1 transfer counter[7:0]
(single/successive transfer mode)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
0048230
(HW)
High-speed
DMA Ch.1
transfer
counter
register
–
–
DUALM1
D1DIR
–
TC1_H7
TC1_H6
TC1_H5
TC1_H4
TC1_H3
TC1_H2
TC1_H1
TC1_H0
DF
DE
DD–8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.1 address mode selection
D) Invalid
S) Ch.1 transfer direction control
reserved
Ch.1 transfer counter[15:8]
(block transfer mode)
Ch.1 transfer counter[23:16]
(single/successive transfer mode)
1 Dual addr 0 Single addr
1
Memory WR
0
Memory RD
0
–
0
–
X
X
X
X
X
X
X
X
R/W
–
R/W
–
R/W Undefined in read.
0048232
(HW)
High-speed
DMA Ch.1
control register
Note:
D) Dual address
mode
S) Single
address
mode
S1ADRL15
S1ADRL14
S1ADRL13
S1ADRL12
S1ADRL11
S1ADRL10
S1ADRL9
S1ADRL8
S1ADRL7
S1ADRL6
S1ADRL5
S1ADRL4
S1ADRL3
S1ADRL2
S1ADRL1
S1ADRL0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D) Ch.1 source address[15:0]
S) Ch.1 memory address[15:0] X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048234
(HW)
High-speed
DMA Ch.1
low-order
source address
set-up register
Note:
D) Dual address
mode
S) Single
address
mode
–
DATSIZE1
S1IN1
S1IN0
S1ADRH11
S1ADRH10
S1ADRH9
S1ADRH8
S1ADRH7
S1ADRH6
S1ADRH5
S1ADRH4
S1ADRH3
S1ADRH2
S1ADRH1
S1ADRH0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Ch.1 transfer data size
D) Ch.1 source address control
S) Ch.1 memory address control
D) Ch.1 source address[27:16]
S) Ch.1 memory address[27:16]
–
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
–
R/W
R/W
R/W
0048236
(HW) 1 Half word 0 Byte
High-speed
DMA Ch.1
high-order
source address
set-up register
Note:
D) Dual address
mode
S) Single
address
mode
1
1
0
0
1
0
1
0
S1IN[1:0] Inc/dec
Inc.(no init)
Inc.(init)
Dec.(no init)
Fixed
–
4 PERIPHERAL CIRCUITS
A-54 EPSON S1C33L03 PRODUCT PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
D1ADRL15
D1ADRL14
D1ADRL13
D1ADRL12
D1ADRL11
D1ADRL10
D1ADRL9
D1ADRL8
D1ADRL7
D1ADRL6
D1ADRL5
D1ADRL4
D1ADRL3
D1ADRL2
D1ADRL1
D1ADRL0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D) Ch.1 destination address[15:0]
S) Invalid X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048238
(HW)
High-speed
DMA Ch.1
low-order
destination
address set-up
register
Note:
D) Dual address
mode
S) Single
address
mode
D1MOD1
D1MOD0
D1IN1
D1IN0
D1ADRH11
D1ADRH10
D1ADRH9
D1ADRH8
D1ADRH7
D1ADRH6
D1ADRH5
D1ADRH4
D1ADRH3
D1ADRH2
D1ADRH1
D1ADRH0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.1 transfer mode
D) Ch.1 destination address
control
S) Invalid
D) Ch.1 destination
address[27:16]
S) Invalid
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
004823A
(HW)
High-speed
DMA Ch.1
high-order
destination
address set-up
register
Note:
D) Dual address
mode
S) Single
address
mode
1
1
0
0
1
0
1
0
D1MOD[1:0] Mode
Invalid
Block
Successive
Single
1
1
0
0
1
0
1
0
D1IN[1:0] Inc/dec
Inc.(no init)
Inc.(init)
Dec.(no init)
Fixed
––
HS1_EN
DF–1
D0
reserved
Ch.1 enable 1 Enable 0 Disable
–
0
–
R/W
Undefined in read.004823C
(HW)
High-speed
DMA Ch.1
enable register
––
HS1_TF
DF–1
D0
reserved
Ch.1 trigger flag clear (writing)
Ch.1 trigger flag status (reading) 1 Clear 0
No operation
1 Set 0 Cleared
–
0
–
R/W
Undefined in read.004823E
(HW)
High-speed
DMA Ch.1
trigger flag
register
4 PERIPHERAL CIRCUITS
S1C33L03 PRODUCT PART EPSON A-55
A-1
A-4
NameAddressRegister name Bit Function Setting Init. R/W Remarks
TC2_L7
TC2_L6
TC2_L5
TC2_L4
TC2_L3
TC2_L2
TC2_L1
TC2_L0
BLKLEN27
BLKLEN26
BLKLEN25
BLKLEN24
BLKLEN23
BLKLEN22
BLKLEN21
BLKLEN20
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.2 transfer c
ounter[7:0]
(block transfer mode)
Ch.2 transfer counter[15:8]
(single/successive transfer mode)
Ch.2 block length
(block transfer mode)
Ch.2 transfer counter[7:0]
(single/successive transfer mode)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
0048240
(HW)
High-speed
DMA Ch.2
transfer
counter
register
–
–
DUALM2
D2DIR
–
TC2_H7
TC2_H6
TC2_H5
TC2_H4
TC2_H3
TC2_H2
TC2_H1
TC2_H0
DF
DE
DD–8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.2 address mode selection
D) Invalid
S) Ch.2 transfer direction control
reserved
Ch.2 transfer counter[15:8]
(block transfer mode)
Ch.2 transfer counter[23:16]
(single/successive transfer mode)
1 Dual addr 0 Single addr
1
Memory WR
0
Memory RD
0
–
0
–
X
X
X
X
X
X
X
X
R/W
–
R/W
–
R/W Undefined in read.
0048242
(HW)
High-speed
DMA Ch.2
control register
Note:
D) Dual address
mode
S) Single
address
mode
S2ADRL15
S2ADRL14
S2ADRL13
S2ADRL12
S2ADRL11
S2ADRL10
S2ADRL9
S2ADRL8
S2ADRL7
S2ADRL6
S2ADRL5
S2ADRL4
S2ADRL3
S2ADRL2
S2ADRL1
S2ADRL0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D) Ch.2 source address[15:0]
S) Ch.2 memory address[15:0] X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048244
(HW)
High-speed
DMA Ch.2
low-order
source address
set-up register
Note:
D) Dual address
mode
S) Single
address
mode
–
DATSIZE2
S2IN1
S2IN0
S2ADRH11
S2ADRH10
S2ADRH9
S2ADRH8
S2ADRH7
S2ADRH6
S2ADRH5
S2ADRH4
S2ADRH3
S2ADRH2
S2ADRH1
S2ADRH0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Ch.2 transfer data size
D) Ch.2 source address control
S) Ch.2 memory address control
D) Ch.2 source address[27:16]
S) Ch.2 memory address[27:16]
–
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
–
R/W
R/W
R/W
0048246
(HW) 1 Half word 0 Byte
High-speed
DMA Ch.2
high-order
source address
set-up register
Note:
D) Dual address
mode
S) Single
address
mode
1
1
0
0
1
0
1
0
S2IN[1:0] Inc/dec
Inc.(no init)
Inc.(init)
Dec.(no init)
Fixed
–
4 PERIPHERAL CIRCUITS
A-56 EPSON S1C33L03 PRODUCT PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
D2ADRL15
D2ADRL14
D2ADRL13
D2ADRL12
D2ADRL11
D2ADRL10
D2ADRL9
D2ADRL8
D2ADRL7
D2ADRL6
D2ADRL5
D2ADRL4
D2ADRL3
D2ADRL2
D2ADRL1
D2ADRL0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D) Ch.2 destination address[15:0]
S) Invalid X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048248
(HW)
High-speed
DMA Ch.2
low-order
destination
address set-up
register
Note:
D) Dual address
mode
S) Single
address
mode
D2MOD1
D2MOD0
D2IN1
D2IN0
D2ADRH11
D2ADRH10
D2ADRH9
D2ADRH8
D2ADRH7
D2ADRH6
D2ADRH5
D2ADRH4
D2ADRH3
D2ADRH2
D2ADRH1
D2ADRH0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.2 transfer mode
D) Ch.2 destination address
control
S) Invalid
D) Ch.2 destination
address[27:16]
S) Invalid
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
004824A
(HW)
High-speed
DMA Ch.2
high-order
destination
address set-up
register
Note:
D) Dual address
mode
S) Single
address
mode
1
1
0
0
1
0
1
0
D2MOD[1:0] Mode
Invalid
Block
Successive
Single
1
1
0
0
1
0
1
0
D2IN[1:0] Inc/dec
Inc.(no init)
Inc.(init)
Dec.(no init)
Fixed
––
HS2_EN
DF–1
D0
reserved
Ch.2 enable 1 Enable 0 Disable
–
0
–
R/W
Undefined in read.004824C
(HW)
High-speed
DMA Ch.2
enable register
––
HS2_TF
DF–1
D0
reserved
Ch.2 trigger flag clear (writing)
Ch.2 trigger flag status (reading) 1 Clear 0
No operation
1 Set 0 Cleared
–
0
–
R/W
Undefined in read.004824E
(HW)
High-speed
DMA Ch.2
trigger flag
register
4 PERIPHERAL CIRCUITS
S1C33L03 PRODUCT PART EPSON A-57
A-1
A-4
NameAddressRegister name Bit Function Setting Init. R/W Remarks
TC3_L7
TC3_L6
TC3_L5
TC3_L4
TC3_L3
TC3_L2
TC3_L1
TC3_L0
BLKLEN37
BLKLEN36
BLKLEN35
BLKLEN34
BLKLEN33
BLKLEN32
BLKLEN31
BLKLEN30
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.3 transfer c
ounter[7:0]
(block transfer mode)
Ch.3 transfer counter[15:8]
(single/successive transfer mode)
Ch.3 block length
(block transfer mode)
Ch.3 transfer counter[7:0]
(single/successive transfer mode)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
0048250
(HW)
High-speed
DMA Ch.3
transfer
counter
register
–
–
DUALM3
D3DIR
–
TC3_H7
TC3_H6
TC3_H5
TC3_H4
TC3_H3
TC3_H2
TC3_H1
TC3_H0
DF
DE
DD–8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.3 address mode selection
D) Invalid
S) Ch.3 transfer direction control
reserved
Ch.3 transfer counter[15:8]
(block transfer mode)
Ch.3 transfer counter[23:16]
(single/successive transfer mode)
1 Dual addr 0 Single addr
1
Memory WR
0
Memory RD
0
–
0
–
X
X
X
X
X
X
X
X
R/W
–
R/W
–
R/W Undefined in read.
0048252
(HW)
High-speed
DMA Ch.3
control register
Note:
D) Dual address
mode
S) Single
address
mode
S3ADRL15
S3ADRL14
S3ADRL13
S3ADRL12
S3ADRL11
S3ADRL10
S3ADRL9
S3ADRL8
S3ADRL7
S3ADRL6
S3ADRL5
S3ADRL4
S3ADRL3
S3ADRL2
S3ADRL1
S3ADRL0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D) Ch.3 source address[15:0]
S) Ch.3 memory address[15:0] X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048254
(HW)
High-speed
DMA Ch.3
low-order
source address
set-up register
Note:
D) Dual address
mode
S) Single
address
mode
–
DATSIZE3
S3IN1
S3IN0
S3ADRH11
S3ADRH10
S3ADRH9
S3ADRH8
S3ADRH7
S3ADRH6
S3ADRH5
S3ADRH4
S3ADRH3
S3ADRH2
S3ADRH1
S3ADRH0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Ch.3 transfer data size
D) Ch.3 source address control
S) Ch.3 memory address control
D) Ch.3 source address[27:16]
S) Ch.3 memory address[27:16]
–
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
–
R/W
R/W
R/W
0048256
(HW) 1 Half word 0 Byte
High-speed
DMA Ch.3
high-order
source address
set-up register
Note:
D) Dual address
mode
S) Single
address
mode
1
1
0
0
1
0
1
0
S3IN[1:0] Inc/dec
Inc.(no init)
Inc.(init)
Dec.(no init)
Fixed
–
4 PERIPHERAL CIRCUITS
A-58 EPSON S1C33L03 PRODUCT PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
D3ADRL15
D3ADRL14
D3ADRL13
D3ADRL12
D3ADRL11
D3ADRL10
D3ADRL9
D3ADRL8
D3ADRL7
D3ADRL6
D3ADRL5
D3ADRL4
D3ADRL3
D3ADRL2
D3ADRL1
D3ADRL0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D) Ch.3 destination address[15:0]
S) Invalid X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048258
(HW)
High-speed
DMA Ch.3
low-order
destination
address set-up
register
Note:
D) Dual address
mode
S) Single
address
mode
D3MOD1
D3MOD0
D3IN1
D3IN0
D3ADRH11
D3ADRH10
D3ADRH9
D3ADRH8
D3ADRH7
D3ADRH6
D3ADRH5
D3ADRH4
D3ADRH3
D3ADRH2
D3ADRH1
D3ADRH0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.3 transfer mode
D) Ch.3 destination address
control
S) Invalid
D) Ch.3 destination
address[27:16]
S) Invalid
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
004825A
(HW)
High-speed
DMA Ch.3
high-order
destination
address set-up
register
Note:
D) Dual address
mode
S) Single
address
mode
1
1
0
0
1
0
1
0
D3MOD[1:0] Mode
Invalid
Block
Successive
Single
1
1
0
0
1
0
1
0
D3IN[1:0] Inc/dec
Inc.(no init)
Inc.(init)
Dec.(no init)
Fixed
––
HS3_EN
DF–1
D0
reserved
Ch.3 enable 1 Enable 0 Disable
–
0
–
R/W
Undefined in read.004825C
(HW)
High-speed
DMA Ch.3
enable register
––
HS3_TF
DF–1
D0
reserved
Ch.3 trigger flag clear (writing)
Ch.3 trigger flag status (reading) 1 Clear 0
No operation
1 Set 0 Cleared
–
0
–
R/W
Undefined in read.004825E
(HW)
High-speed
DMA Ch.3
trigger flag
register
4 PERIPHERAL CIRCUITS
S1C33L03 PRODUCT PART EPSON A-59
A-1
A-4
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
–
SDRAR0
SDRAR1
–
SDRPC0
SDRPC1
–
D7
D6
D5–4
D3
D2
D1–0
Area 7/13 configuration
Area 8/14 configuration
reserved
#CE7/13 pin configuration
#CE8/14 pin configuration
reserved
0
0
–
0
0
–
R/W
R/W
–
R/W
R/W
–
0 when being read.
0 when being read.
039FFC0
(B) 1SDRAM 0
Not SDRAM
1SDRAM 0
Not SDRAM
1#SDCE0 0#CE7/13
1#SDCE1 0#CE8/14
SDRAM area
configuration
register
–
SDRENA
SDRINI
SDRSRF
SDRIS
SDRCLK
–
D7
D6
D5
D4
D3
D2–0
Enable SDRAM signals
Start SDRAM power up
Enable SDRAM self-refresh
Initial command sequence
Keep SDCLK during self-refresh
reserved
0
0
0
0
1
–
R/W
R/W
R/W
R/W
R/W
–
0 when being read.
0 when being read.
039FFC1
(B) 1Enabled 0Disabled
1Start 0 –
11 precharge
2 set reg.
3 refresh
01 precharge
2 refresh
3 set reg.
1Enabled 0Disabled
1Kept 0Stopped
SDRAM
control register
–
–
––
SDRCA1
SDRCA0
–
SDRRA1
SDRRA0
SDRBA
–
D7
D6–5
D4
D3–2
D1
D0
reserved
SDRAM page size
(column range)
reserved
SDRAM row addressing range
Number of SDRAM banks
reserved
–
0
0
–
0
0
0
–
–
R/W
–
R/W
R/W
–
0 when being read.
0 when being read.
0 when being read.
039FFC2
(B)
14 banks 02 banks
SDRAM
address
configuration
register
1
1
0
0
1
0
1
0
SDRRA[1:0] Addressing range
reserved
8K (SDA[12:0])
4K (SDA[11:0])
2K (SDA[10:0])
1
1
0
0
1
0
1
0
SDRCA[1:0] Page size
reserved
1K (SDA[9:0])
512 (SDA[8:0])
256 (SDA[7:0])
–
–
––
SDRCL1
SDRCL0
–
SDRBL1
SDRBL0
–
D7
D6–5
D4
D3–2
D1–0
reserved
SDRAM CAS latency
reserved
SDRAM burst length
reserved
–
1
1
–
1
1
–
–
R/W
–
R/W
–
0 when being read.
0 when being read.
0 when being read.
039FFC3
(B)
SDRAM
mode set-up
register 1 0
SDRCL[1:0] CAS latency
2 CAS latency
1
1
0
0
1
0
1
0
SDRBL[1:0] Burst length
8
4
2
1
SDRTRAS2
SDRTRAS1
SDRTRAS0
SDRTRP1
SDRTRP0
SDRTRC2
SDRTRC1
SDRTRC0
D7–5
D4–3
D2–0
SDRAM t
RAS
spec
SDRAM t
RP
spec
SDRAM t
RC
spec
0
0
0
0
0
0
0
0
R/W
R/W
R/W
039FFC4
(B)
SDRAM
timing set-up
register 1 1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
SDRTRAS[2:0]
Number of clocks
7
6
5
4
3
2
1
8
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
SDRTRC[2:0]
Number of clocks
7
6
5
4
3
2
1
8
1
1
0
0
1
0
1
0
SDRTRP[1:0]
Number of clocks
3
2
1
4
4 PERIPHERAL CIRCUITS
A-60 EPSON S1C33L03 PRODUCT PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
SDRTRCD1
SDRTRCD0
SDRTRSC
SDRTRRD1
SDRTRRD0
–
D7–6
D5
D4–3
D2–0
SDRAM t
RCD
spec
SDRAM t
RSC
spec
SDRAM t
RRD
spec
reserved
0
0
0
0
0
–
R/W
R/W
R/W
–0 when being read.
039FFC5
(B)
SDRAM
timing set-up
register 2 1
1
0
0
1
0
1
0
SDRTRCD[1:0]
Number of clocks
3
2
1
4
1
1
0
0
1
0
1
0
SDRTRRD[1:0]
Number of clocks
3
2
1
4
–
11 clock 02 clocks
–
SDRARFC11
SDRARFC10
SDRARFC9
SDRARFC8
SDRARFC7
SDRARFC6
SDRARFC5
SDRARFC4
SDRARFC3
SDRARFC2
SDRARFC1
SDRARFC0
DF–C
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
SDRAM auto refresh count [11:0] –
1
1
1
1
1
1
1
1
1
1
1
1
–
R/W 0 when being read.039FFC6
(HW)
SDRAM
auto refresh
count register 0 to 4096
–
–
SDRSRFC3
SDRSRFC2
SDRSRFC1
SDRSRFC0
D7–4
D3
D2
D1
D0
reserved
SDRAM self refresh count [3:0] –
1
1
1
1
–
R/W 0 when being read.
This register must
not be set less than
"0x02".
039FFC8
(B)
SDRAM
self refresh
count register 2 to 15
–
–
––
SDRSZ
SDRBI
–
D7
D6
D5
D4–0
reserved
SDRAM data path bit width
SDRAM bank interleaved access
reserved
–
0
0
–
–
R/W
R/W
–
0 when being read.
0 when being read.
039FFC9
(B) 18 bits 016 bits
1Interleaved 0One bank
SDRAM
advanced
control
register
–
SDRMRS
SDRSRM
–
D7
D6
D5–0
SDRAM mode register set flag
SDRAM current refresh mode
reserved
1
1
–
R
R
–0 when being read.
039FFCA
(B) 1Not finished 0Done
1
Auto refresh
0Self refresh
SDRAM
status register
4 PERIPHERAL CIRCUITS
S1C33L03 PRODUCT PART EPSON A-61
A-1
A-4
NameAddressRegister name Bit Function Setting Init. R/W Remarks
PCODE5
PCODE4
PCODE3
PCODE2
PCODE1
PCODE0
RCODE1
RCODE0
D7
D6
D5
D4
D3
D2
D1
D0
Product code
Revision code
0
0
0
0
1
0
0
0
R
R
039FFE0
(B)
Revision code
register 0b000010
–
–
–
LDCOLOR
–
FPSMASK
LDDW1
LDDW0
D7–6
D5
D4–3
D2
D1
D0
reserved
Color/monochrome select
reserved
Mask FPSHIFT signal
LCD data width/format
–
0
–
0
0
0
–
R/W
–
R/W
R/W
0 when being read.
0 when being read.
039FFE1
(B) 1Color 0Mono
1Masked 0Output
LCDC mode
register 0
1
0
0
x
1
0
LDDW[1:0] Monochrome
reserved
8 bits
4 bits
1
1
0
0
1
0
1
0
LDDW[1:0] Color
8 bits/format 2
reserved
8 bits/format 1
4 bits
–
–
BPP1
BPP0
–
DBLANK
FRMRPT
–
INVDISP
D7
D6
D5–4
D3
D2
D1
D0
Bit-per-pixel select
(Display mode)
reserved
Blank display
Frame repeat for EL panel
reserved
Invert display
0
0
–
0
0
–
0
R/W
–
R/W
R/W
–
R/W
0 when being read.
0 when being read.
039FFE2
(B)
1Repeated 0
Not repeated
1Inverted 0Normal
1Blank 0Normal
LCDC mode
register 1 1
1
0
0
1
0
1
0
BPP[1:0] Mode
8 bpp
4 bpp
2 bpp
1 bpp
–
–
–
LCDCEN
LPWREN
–
LPSAVE1
LPSAVE0
D7–6
D5
D4
D3–2
D1
D0
reserved
LCD controller enable
LCDPWR enable
reserved
Power save mode
–
0
0
–
0
0
–
R/W
R/W
–
R/W
0 when being read.
0 when being read.
039FFE3
(B) 1Enabled 0Disabled
1Enabled 0Disabled
LCDC mode
register 2
1
1
0
0
1
0
1
0
LPSAVE[1:0] Mode
Normal operation
Doze
reserved
Power save
–
LDHSIZE5
LDHSIZE4
LDHSIZE3
LDHSIZE2
LDHSIZE1
LDHSIZE0
D7–6
D5
D4
D3
D2
D1
D0
reserved
Horizontal panel size –
0
0
0
0
0
0
–
R/W 0 when being read.039FFE4
(B)
Horizontal
panel size
register
–
H resolution (pixels) - 1
16
LDVSIZE7
LDVSIZE6
LDVSIZE5
LDVSIZE4
LDVSIZE3
LDVSIZE2
LDVSIZE1
LDVSIZE0
D7
D6
D5
D4
D3
D2
D1
D0
Vertical panel size
(low-order 8 bits) 0
0
0
0
0
0
0
0
R/W039FFE5
(B)
Vertical
panel size
register 0
V resolution (lines) - 1
–
LDVSIZE9
LDVSIZE8
D7–2
D1
D0
reserved
Vertical panel size
(high-order 2 bits)
–
0
0
–
R/W 0 when being read.039FFE6
(B)
Vertical
panel size
register 1
–
V resolution (lines) - 1
–
HNDP4
HNDP3
HNDP2
HNDP1
HNDP0
D7–5
D4
D3
D2
D1
D0
reserved
Horizontal non-display period –
0
0
0
0
0
–
R/W 0 when being read.039FFE7
(B)
Horizontal
non-display
period register
–
Non-display period (pixels) - 4
8
4 PERIPHERAL CIRCUITS
A-62 EPSON S1C33L03 PRODUCT PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
VNDPF
–
VNDP5
VNDP4
VNDP3
VNDP2
VNDP1
VNDP0
D7
D6
D5
D4
D3
D2
D1
D0
Vertical non-display period status
reserved
Vertical non-display period
0
–
0
0
0
0
0
0
R
–
R/W 0 when being read.
039FFEA
(B)
Vertical
non-display
period register –
Non display period (lines)
1VNDP 0Display
–
MODRATE5
MODRATE4
MODRATE3
MODRATE2
MODRATE1
MODRATE0
D7–6
D5
D4
D3
D2
D1
D0
reserved
MOD rate –
0
0
0
0
0
0
–
R/W 0 when being read.039FFEB
(B)
MOD rate
register –
S1ADDR7
S1ADDR6
S1ADDR5
S1ADDR4
S1ADDR3
S1ADDR2
S1ADDR1
S1ADDR0
D7
D6
D5
D4
D3
D2
D1
D0
Screen 1 start address
(low-order 8 bits) 0
0
0
0
0
0
0
0
R/W039FFEC
(B)
Screen 1
start address
register 0
S1ADDR15
S1ADDR14
S1ADDR13
S1ADDR12
S1ADDR11
S1ADDR10
S1ADDR9
S1ADDR8
D7
D6
D5
D4
D3
D2
D1
D0
Screen 1 start address
(high-order 8 bits) 0
0
0
0
0
0
0
0
R/W039FFED
(B)
Screen 1
start address
register 1
S2ADDR7
S2ADDR6
S2ADDR5
S2ADDR4
S2ADDR3
S2ADDR2
S2ADDR1
S2ADDR0
D7
D6
D5
D4
D3
D2
D1
D0
Screen 2 start address
(low-order 8 bits) 0
0
0
0
0
0
0
0
R/W039FFEE
(B)
Screen 2
start address
register 0
S2ADDR15
S2ADDR14
S2ADDR13
S2ADDR12
S2ADDR11
S2ADDR10
S2ADDR9
S2ADDR8
D7
D6
D5
D4
D3
D2
D1
D0
Screen 2 start address
(high-order 8 bits) 0
0
0
0
0
0
0
0
R/W039FFEF
(B)
Screen 2
start address
register 1
–
S1ADDR16
D7–1
D0 reserved
Screen 1 start address (MSB)
(for portrait mode;
fix at 0 in landscape mode)
–
0–
R/W 0 when being read.039FFF0
(B)
Screen 1
start address
register 2
–
MADOFS7
MADOFS6
MADOFS5
MADOFS4
MADOFS3
MADOFS2
MADOFS1
MADOFS0
D7
D6
D5
D4
D3
D2
D1
D0
Memory address offset 0
0
0
0
0
0
0
0
R/W039FFF1
(B)
Memory
address offset
register
S1VSIZE7
S1VSIZE6
S1VSIZE5
S1VSIZE4
S1VSIZE3
S1VSIZE2
S1VSIZE1
S1VSIZE0
D7
D6
D5
D4
D3
D2
D1
D0
Screen 1 vertical size
(low-order 8 bits) 0
0
0
0
0
0
0
0
R/W039FFF2
(B)
Screen 1
vertical size
register 0
4 PERIPHERAL CIRCUITS
S1C33L03 PRODUCT PART EPSON A-63
A-1
A-4
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
S1VSIZE9
S1VSIZE8
D7–2
D1
D0
reserved
Screen 1 vertical size
(high-order 2 bits)
–
0
0
–
R/W 0 when being read.039FFF3
(B)
Screen 1
vertical size
register 1
–
–
FIFOEO3
FIFOEO2
FIFOEO1
FIFOEO0
LCLKSEL2
LCLKSEL1
LCLKSEL0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
FIFO empty offset
LCDC clock select
–
0
0
0
0
0
0
0
–
R/W
R/W
0 when being read.039FFF4
(B)
FIFO control
register –
Fix at 8 (0b1000)
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
LCLKSEL[2:0]
LCDC clock
BCU_CLK/4
BCU_CLK/3
BCU_CLK/2
BCU_CLK
reserved
Stop
Stop
Stop
–
LUTADDR3
LUTADDR2
LUTADDR1
LUTADDR0
D7–4
D3
D2
D1
D0
reserved
Look-up table address –
0
0
0
0
–
R/W 0 when being read.039FFF5
(B)
Look-up table
address
register
–
LUTDT3
LUTDT2
LUTDT1
LUTDT0
–
D7
D6
D5
D4
D3–0
Look-up table data
reserved
0
0
0
0
–
R/W
–0 when being read.
039FFF7
(B)
Look-up table
data register
–
–
GPIO2C
GPIO1C
GPIO0C
D7–3
D2
D1
D0
reserved
GPIO2 configuration
GPIO1 configuration
GPIO0 configuration
–
0
0
0
–
R/W
R/W
R/W
0 when being read.039FFF8
(B)
GPIO
configuration
register
–
1Output 0Input
1Output 0Input
1Output 0Input
–
GPO6D
GPO5D
GPO4D
GPO3D
GPIO2D
GPIO1D
GPIO0D
D7
D6
D5
D4
D3
D2
D1
D0
reserved
GPO6 data
GPO5 data
GPO4 data
GPO3 data
GPIO2 data
GPIO1 data
GPIO0 data
–
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.039FFF9
(B)
GPIO
status/control
register
–
1High 0Low
1High 0Low
1High 0Low
1High 0Low
1High 0Low
1High 0Low
1High 0Low
SP1A7
SP1A6
SP1A5
SP1A4
SP1A3
SP1A2
SP1A1
SP1A0
D7
D6
D5
D4
D3
D2
D1
D0
Scratch pad 0
0
0
0
0
0
0
0
R/W039FFFA
(B)
Scratch pad
register
–
PMODEN
PMODSEL
–
PMODCLK1
PMODCLK0
D7
D6
D5–2
D1
D0
Portrait mode enable
Portrait mode select
reserved
Portrait mode clock select
(LCDC clock division ratio)
Division ratio 1: Default mode
Division ratio 2: Alternate mode
P: Pixel clock, M: Memory clock
0
0
–
0
0
R/W
R/W
–
R/W 0 when being read.
039FFFB
(B) 1 Portrait 0 Landscape
1Alternate 0Default
Portrait mode
register
1
1
0
0
1
0
1
0
PMODCLK[1:0]
Division ratio 1
P: 1/8, M: 1/8
P: 1/4, M: 1/4
P: 1/2, M: 1/2
P: 1/1, M: 1/1
1
1
0
0
1
0
1
0
PMODCLK[1:0]
Division ratio 2
P: 1/8, M: 1/4
P: 1/4, M: 1/2
P: 1/2, M: 1/1
P: 1/2, M: 1/1
PMODLBC7
PMODLBC6
PMODLBC5
PMODLBC4
PMODLBC3
PMODLBC2
PMODLBC1
PMODLBC0
D7
D6
D5
D4
D3
D2
D1
D0
Line byte count 0
0
0
0
0
0
0
0
R/W039FFFC
(B)
Line byte
count register
for portrait
mode
4 PERIPHERAL CIRCUITS
A-64 EPSON S1C33L03 PRODUCT PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
VRAMAR
VRAMWT2
VRAMWT1
VRAMWT0
EDMAEN
BREQEN
LCDCST
LCDCEC
D7
D6
D5
D4
D3
D2
D1
D0
VRAM area select
VRAM wait control
(number of wait cycles for SRAM)
External DMA enable
External bus-request enable
A0/BSL select
Big/little endian select
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
039FFFD
(B) 1Area 8 0Area 7
1Enabled 0Disabled
1Enabled 0Disabled
1BSL 0A0
1Big endian 0
Little endian
LCDC
system control
register 0–7
5 POWER-DOWN CONTROL
S1C33L03 PRODUCT PART EPSON A-65
A-1
A-5
5 Power-Down Control
This chapter describes the controls used to reduce power consumption of the device.
Points on power saving
The current consumption of the device varies greatly with the CPU's operation mode, the system clocks used,
and the peripheral circuits operated.
Current consumption low←→high
CPU/BCU SLEEP HALT2 Operating HALT2 HALT(basic) Operating
System clock – OSC1 OSC1 OSC3 OSC3 OSC3
OSC3 oscillation ci r cuit OFF OFF OFF ON ON ON
Prescaler/peripheral circuit STOP RUN
To reduc e power consumption of the device, it is important that as many unnecessary circuits as possible be
turned off. In particular, peripheral circuits operating at a fast-clock rate consume a large amount of current,
so design the program so that these circuits are turned off whenever unnecessary.
Power-saving in standby modes
When CPU processing is unnecessary, such as when waiting for an interrupt from key entries or peripheral
circuits, place the device in standby mode to reduce current consumption.
Standby mode Method to enter the mode Circui ts/fun ctions sto pped
Basic HALT mode Execute the halt instruction after setting HLT2OP
(D3)/Clock option register (0x40190) to "0".
When the #BUSREQ signal is asserted from an
external bus master while SEPD (D1)/Bus control
register (0x4812E) = "1".
CPU (DMA cannot be used.)
HALT 2 m ode Execute the halt instruction after setting HLT2OP
to "1". CPU, BCU, bus clock, and DMA
SLEEP mode Execute the slp instruction. CPU, BCU, bus clock, DMA, high-speed
(OSC3) oscillation circuit, prescaler, and
peripheral circuits that use the prescaler
output clocks
HLT2OP (D3) /Cloc k option register (0x40190) that is used to select a HALT mode is set to "0" (basic HALT
mode ) at initial re se t.
Notes:•In systems in which DRAM or SDRAM is connected directly to the device, the refresh function is
turned off during HALT2 and SLEEP mo des. However, the SD RAM self r efresh function ca n be
used by activating it before t he CPU en ters HALT2 or SL EEP mode.
•The standby mode is cleared by i nterrupt generation (except for the basic HALT m ode, which i s
set using an external bus ma ster). Ther efore, before entering st andb y m ode, set the related
registers to allow an interrupt to be used to clea r th e s tandby m ode to be ge nerated.
•When clearing the standby m ode with an inter rupt f rom po rt input, the inter rupt operates as a
level interrupt regardless of the interrupt trigger setting. When edge trigger is set for the interrupt
trigger, attention must be paid to the port level during sta ndby mode.
The low-speed (O SC1) oscillation circuit and clock timer continue operating even during SLEEP mode. If
they are unnecessary, these circuits can also be turned off.
Function Control bit "1" "0" Default
Low-speed (OSC1) oscillation ON/OFF control SOSC1(D0)/
Power control register(0x40180) ON OFF ON
Switching ov er the system clocks
Normally, the system is clocked by the high-speed (O S C3 ) oscil la ti o n cl ock. If high -speed o peration is
unnecessary, switch the system clock to the low-speed (OSC1) oscillation clock and turn off the high-speed
(OSC3) oscillation circuit. This helps to reduce current consumption. However, if DRAM is connected
directly to the device, note that the refresh function is also turned off.
Even du ring operation using the high-speed (OSC3) oscillation clock, power reduction can also be achieved
through the use of a system clock derived from the OSC3 clock by dividing it (1/1, 1/2, 1/4, or 1/8).
5 POWER-DOWN CONTROL
A-66 EPSON S1C33L03 PRODUCT PART
Function Control bit "1" "0" Default
System clock switch over CLKCHG(D2)/
Power control register(0x40180) OSC3 OSC1 OSC3
High-speed (OSC3) oscillation ON/OFF control SOSC3(D1)/
Power control register(0x40180) ON OFF ON
System clock division ratio selection CLKDT(D[7:6])/
Power control register(0x40180) "11" = 1/8
"10" = 1/4
"01" = 1/2
"00" = 1/1
1/1
Turning off the pres caler and periphera l circuits
Current consumption can be reduced by turning off the peripheral circuits operating at high speed as much as
possible. The peripheral circuits are as follows.
1) Periph er al ci rc uit s usin g the clock g en erated b y the p res caler
• 16-bit programmable timers 0 to 5 (watchdog timer)
• 8-bit programmable timers 0 to 5 (DRAM refresh, serial interface)
• A/D converter
2) Periph er al ci rc uit s usin g th e clock (sou rce clock for p resca ler) su ppli ed to the p res ca ler
• 16-bit programmable timers 0 to 5 (watchdog timer)
• 8-bit programmable timers 0 to 5 (DRAM refresh)
• A/D converter
• Serial interface
• Input/output ports
If none of all circuits of the above 1) and 2) need to be used, turn off the prescaler. If the circuit of the above
1) or 2) need to be used, do not turn off the prescaler. Wh en ope ration of the prescaler is stopped , the clock
supply to the circuits of the above 2) stops. When some these circuits of the above 1) need to be used, turn off
all other unnecessary circuits and stop the clock supply from the prescaler to those circuits.
The prescaler operating control and the clock supply control bits for each peripheral circuit are shown in the
table below.
Function Control bit "1" "0" Default
Prescaler ON/OFF PSCON(D5)/Power control register(0x40180) ON OFF ON
16-bit timer 0 clock control P16TON0(D3)/16-bit timer 0 clock control register(0x40147) ON OFF OFF
16-bit timer 0 Run/Stop PRUN0(D0)/16-bit timer 0 control register(0x48186) RUN STOP STOP
16-bit timer 1 clock control P16TON1(D3)/16-bit timer 1 clock control register(0x40148) ON OFF OFF
16-bit timer 1 Run/Stop PRUN1(D0)/16-bit timer 1 control register(0x4818E) RUN STOP STOP
16-bit timer 2 clock control P16TON2(D3)/16-bit timer 2 clock control register(0x40149) ON OFF OFF
16-bit timer 2 Run/Stop PRUN2(D0)/16-bit timer 2 control register(0x48196) RUN STOP STOP
16-bit timer 3 clock control P16TON3(D3)/16-bit timer 3 clock control register(0x4014A) ON OFF OFF
16-bit timer 3 Run/Stop PRUN3(D0)/16-bit timer 3 control register(0x4819E) RUN STOP STOP
16-bit timer 4 clock control P16TON4(D3)/16-bit timer 4 clock control register(0x4014B) ON OFF OFF
16-bit timer 4 Run/Stop PRUN4(D0)/16-bit timer 4 control register(0x481A6) RUN STOP S TOP
16-bit timer 5 clock control P16TON5(D3)/16-bit timer 5 clock control register(0x4014C) ON OFF OFF
16-bit timer 5 Run/Stop PRUN5(D0)/16-bit timer 5 control register(0x481AE) RUN STOP STOP
8-bit timer 0 clock control P8TON0(D3)/8-bit timer 0/1 clock control register(0x4014D) ON OFF OFF
8-bit timer 0 Run/Stop PTRUN0(D0)/8-bit timer 0 control register(0x40160) RUN STOP STOP
8-bit timer 1 clock control P8TON1(D7)/8-bit timer 0/1 clock control register(0x4014D) ON OFF OFF
8-bit timer 1 Run/Stop PTRUN1(D0)/8-bit timer 1 control register(0x40164) RUN STOP STOP
8-bit timer 2 clock control P8TON2(D3)/8-bit timer 2/3 clock control register(0x4014E) ON OFF OFF
8-bit timer 2 Run/Stop PTRUN2(D0)/8-bit timer 2 control register(0x40168) RUN STOP STOP
8-bit timer 3 clock control P8TON3(D7)/8-bit timer 2/3 clock control register(0x4014E) ON OFF OFF
8-bit timer 3 Run/Stop PTRUN3(D0)/8-bit timer 3 control register(0x4016C) RUN STOP STOP
8-bit timer 4 clock control P8TON4(D3)/8-bit timer 4/5 clock control register(0x40145) ON OFF OFF
8-bit timer 4 Run/Stop PTRUN4(D0)/8-bit timer 4 control register(0x40174) RUN STOP STOP
8-bit timer 5 clock control P8TON5(D7)/8-bit timer 4/5 clock control register(0x40145) ON OFF OFF
8-bit timer 5 Run/Stop PTRUN5(D0)/8-bit timer 5 control register(0x40178) RUN STOP STOP
A/D converter clock control PSONAD(D3)/A/D clock control register(0x4014F) ON OFF OFF
A/D conversion enable ADE(D2)/A/D enable register(0x40244) RUN STOP STOP
5 POWER-DOWN CONTROL
S1C33L03 PRODUCT PART EPSON A-67
A-1
A-5
The same clock source must be used for the prescaler operating clock and the CPU operating clock. Therefore,
when operating the CPU in low-speed with the OSC1 clock, the prescaler input clock must be switched
according to the CPU operating clock. In this case, in order to prevent a malfunction in the peripheral circuit,
the prescaler should be turned off before switching the CPU operating clock. After the CPU operating clock
has been switched, switch the prescaler operating clock and then turn the prescaler on.
Function Control bit "1" "0" Default
Prescaler operating clock
switch over PSCDT0 (D0)/Prescaler clock select register(0x40181) OSC1 OSC3/
PLL OSC3/
PLL
Power-down control of the LCD controller
The LCD controller pr ovi des the pow er s ave mo de on its ow n. Since the pow er save mode can be controlled
by software, set the mode when turning the LCD display off.
Function Control bit "11" "00" Default
Power save mode LPSAVE[1:0] D([1:0])/LCDC mode register 2
(0x39FFE3) Normal
operation Power
save mode Power
save mode
Note:The power save mo de sw itc he s the LCD pa nel pow er contr ol si g nal ( LCDPW R) t o the ina cti ve sta te .
This ma y ca use dam age of the LC D pane l if the clock supply to the LCD co ntrol ler is st oppe d at the
same time.
Ther ef ore , do no t sto p the clo ck supp l y for 1 fra me cy cle s or mo re aft er se t tin g the LCD co nt rol ler to
power save mode.
6 BASIC EXTE RNAL WIRING DIAGRAM
A-68 EPSON S1C33L03 PRODUCT PART
6 Basic External Wiring Diagram
S1C33L03
[The potential of the substrate
(back of the chip) is VSS.]
External
Bus
HSDMA
Serial I/O
A/D input
Input
I/O
Timer
input/output
X'tal1
CG1
CD1
Rf1
X'tal2
CR
CG2
CD2
Rf2
R1
C1
C2
Crystal oscillator
Gate capacitor
Drain capacitor
Feedback resistor
Crystal oscillator
Ceramic oscillator
Gate capacitor
Drain capacitor
Feedback resistor
Resistor
Capacitor
Capacitor
32.768 kHz, CI(Max.) = 34 kΩ
10 pF
10 pF
10 MΩ
33 MHz (Max.)
33 MHz (Max.)
10 pF
10 pF
1 MΩ
4.7 kΩ
100 pF
5 pF
Note: The above table is simply an example, and is not guaranteed to work.
∗1: When the PLL is not used,
leave the PLLC pin open.
VDD
VDDE
AVDDE
DSIO
ICEMD
EA10MD0
EA10MD1
#X2SPD
PLLC
PLLS0
PLLS1
OSC3
OSC4
OSC1
OSC2
#RESET
VSS
C
D2
3.3V
X'tal2
or
CR Rf
2
A[23:0]
D[15:0]
#RD
#EMEMRD
#DRD
#GARD
#GAAS
#WRL/#WR/#WE
#WRH/#BSH
#DWE/#SDWE
#HCAS/#SDCAS
#LCAS/#SDRAS
#CExx/#RASx/#SDCEx
SDA10
SDCKE
HDQM/LDQM
#CE10EX
#WAIT
BCLK
#BUSREQ
#BUSACK
#BUSGET
#NMI
#DMAREQx
#DMAACKx
#DMAENDx
SINx
SOUTx
#SCLKx
#SRDYx
#ADTRG
ADx
EXCLx
TMx
T8UFx
Kxx
Pxx
C
G2
C
2
C
1
R
1
∗1
+
C
D1
X'tal1 Rf
1
C
G1
FPDAT[7:0]
FPSHIFT
FPFRAME
FPLINE
DRDY
LCDPWR
LCD panel
7 PRECAUTIONS ON MOUNTING
S1C33205 PRODUCT PART EPSON A-69
A-1
A-7
7 Precautions o n Mounting
The following shows the precautions when designing the board and mounting the IC.
Oscillation Circuit
•Oscillation characteristics change depending on conditions (board pattern, components used, etc.).
In particular, when a ceramic oscillator or crystal oscillator is used, use the oscillator manufacturer's
recommended values for constants such as capacitance and resistance.
•Disturbances of the oscillation clock due to noise may cause a malfunction. Consider the following points to
prevent this:
(1) Components which are connected to the OSC3 (OSC1), OSC4 (OSC2) and PLLC pins, such as
oscillators, resistors and capacitors, should be connected in the shortest line.
(2) As shown in the figure below, make a VSS pattern as large as possible at circumscription of the OSC3
(OSC1) and OSC4 (OSC2) pins and the components connected to these pins. The same applies to the
PLLC pin.
Furthermore, do not use this VSS pattern to connect other components than the oscillation system.
OSC4
OSC3
V
SS
Sample V
SS
pattern
OSC3 and OSC4
V
SS
PLLC
V
SS
PLLC
(3) When supplying an external clock to the OSC3 (OSC1) pin, the clock source should be connected to the
OSC3 (OSC1) pin in the shortest line.
Furthermore, do not connect anything else to the OSC4 (OSC2) pin.
•In order to prevent unstable operation of the oscillation circuit due to current leak between OSC3 (OSC1) and
VDD, please keep enough distance between OSC3 (OSC1) and VDD or other signals on the bo ard pattern.
Re set Circui t
•The power-on reset signal which is input to the #RESET pin changes depending on conditions (power rise
time, components used, board pattern, etc.). Decide the time constant of the capacitor and resistor after
enough tests have been completed with the application product.
•In order to prevent any occurrences of unnecessary resetting caused by noise during operating, components
such as capacitors and resistors should be connected to the #RESET pin in the shortest line.
Power Supply Circuit
•Sudden power supply variation due to noise may cau se malfunction. Consider the following points to prevent
this:
(1) The power supply should be connected to the VDD, V DDE, V SS and AVDDE pins with patterns as short
and large as possible.
In particular, the power supply for AVDDE affects A/D conversion precision.
7 PRECAUTIONS ON MOUNTING
A-70 EPSON S1C33205 PRODUCT PART
(2) When connecti n g b etw een t h e VDD and VSS pins with a bypass capacitor, the pins should be connected
as short as possible.
V
DD
V
SS
Bypass capacitor connection example
V
DD
V
SS
A/D Co n verter
•When the A/D converter is not used, the power supply pin AVDDE for the analog system should be connected
to VDDE.
Arrangement of Signal Lines
•In order to prevent generation of elect romagnetic induction noise caused by mutual inductance, do not
arrange a large current signal line near the circuits that are sensitive to noise such as the oscillation unit and
analog input unit.
•When a si gn al l i ne is parallel with a high-speed line in long distance or intersects a high-speed line, noise
may gen erated by m utual interference betw een the signals and it may cause a malfunction.
Do not arrange a high-speed signal line especially near circuits that are sensitive to noise such as the
oscillation unit and analog input unit.
K60 (AD0)
Large current signal line
High-speed signal line
OSC4
OSC3
VSS
Large current signal line
High-speed signal line
Prohibited pattern
8 ELECTRICAL CHARACTE RISTICS
S1C33L03 PRODUCT PART EPSON A-71
A-1
A-8
8 Electri cal Characteristi cs
8.1 Absolute Maximum Rating
(VSS=0V)
Item Symbol Condition Rated value Unit ∗
Supply voltage VDD -0.3 to +4.0 V
C33 I/O power voltage VDDE -0.3 to +7.0 V
Input v olt a ge VI-0.3 to VDDE+0.5 V
High-level output current IOH 1 pi n -10 mA
Total of all pins -40 mA
Low -l ev el ou tpu t cur rent IOL 1 pin 10 mA
Total of all pins 40 mA
Analog power voltage AVDDE -0.3 to +7.0 V
Analog input voltage AVIN -0.3 to AVDDE+0.3 V
Storage temperature TSTG -65 to +150 °C
8 ELECTRICAL CHARACTE RISTICS
A-72 EPSON S1C33L03 PRODUCT PART
8.2 Recommended Operating Conditions
1) 3.3 V/5.0 V dual power source (VSS=0V)
Item Symbol Condition Min. Typ. Max. Unit ∗
Supply voltage (hi gh v olta ge) VDDE 4.50 5.00 5.50 V
Supply voltage (lo w volta ge) VDD 2.70 – 3.60 V
Input v olt a ge HVIVSS –VDDE V
LVIVSS –VDD V
CPU operating clock frequency fCPU ––50MHz
External bus operating clock frequency fBUS ––35MHz
Low -speed os cillat ion freq ue ncy fOSC1 –32.768– kHz
Operating temperature Ta -40 25 85 °C
Input rise time (normal input) tri – – 50 ns
Input fall time (normal input) tfi – – 50 ns
Input rise time (schmitt input) tri ––5ms
Input fall time (schmitt input) tfi ––5ms
2) 3.3 V single po w er source (VDDE=VDD, VSS=0V)
Item Symbol Condition Min. Typ. Max. Unit ∗
Supply voltage VDD 2.70 – 3.60 V
Input v olt a ge VIVSS –VDD V
CPU operating clock frequency fCPU ––50MHz
External bus operating clock frequency fBUS ––35MHz
Low -speed os cillat ion freq ue ncy fOSC1 –32.768– kHz
Operating temperature Ta -40 25 85 °C
Input rise time (normal input) tri – – 50 ns
Input fall time (normal input) tfi – – 50 ns
Input rise time (schmitt input) tri ––5ms
Input fall time (schmitt input) tfi ––5ms
3) 2.0 V single po w er source (VDDE=VDD, VSS=0V)
Item Symbol Condition Min. Typ. Max. Unit ∗
Supply voltage VDD 1.80 2.00 2.20 V
Input v olt a ge VIVSS –VDD V
CPU operating clock frequency fCPU ––20MHz
External bus operating clock frequency fBUS ––20MHz
Low -speed os cillat ion freq ue ncy fOSC1 –32.768– kHz
Operating temperature Ta -40 25 85 °C
Input rise time (normal input) tri – – 100 ns
Input fall time (normal input) tfi – – 100 ns
Input rise time (schmitt input) tri – – 10 ms
Input fall time (schmitt input) tfi – – 10 ms
8 ELECTRICAL CHARACTE RISTICS
S1C33L03 PRODUCT PART EPSON A-73
A-1
A-8
8.3 DC Characteristics
1) 3.3 V/5.0 V dual power source
(Unless otherwise specified: VDDE=5V±0.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Condition Min. Typ. Max. Unit ∗
Input leak age cur rent ILI -1 – 1 µA
Off-state leakage current IOZ -1 – 1 µA
High-level output voltage VOH IOH=-3mA (Type1), IOH=-12mA (Type3),
VDDE=Min. VDDE
-0.4 ––V
Low -lev el out pu t volta ge VOL IOL=3mA ( Type1), IOL=12mA (Type3),
VDDE=Min. ––0.4V
High-level input voltage VIH CMOS level, VDDE=Max. 3.5 – –V
Low -lev el in put v olta ge VIL CMOS level, VDDE=Min. ––1.0V
Positive trigger input voltage VT+ CMOS Schmitt 2.0–4.0V
Negative trigger input voltage VT- CMOS Schmitt 0.8–3.1V
Hysteresis voltage VHCMOS Schmitt 0.3 – –V
High-level input voltage VIH2 TTL level, VDDE=Max. 2.0 – –V
Low -lev el in put v olta ge VIL2 TTL level, VDDE=Min. ––0.8V
Pull-up resistor RPU VI=0V 60 120 288 kΩ
Pull-down r esistor RPD VI=VDDE (ICEMD) 30 60 144 kΩ
Input pin capa citance CIf=1MHz, VDDE=0V ––10pF
Output pin capacitance COf=1MHz, VDDE=0V ––10pF
I/O pin capacitance CIO f=1MHz, VDDE=0V ––10pF
2) 3.3 V single po w er source (Unless otherwise specified: VDDE=VDD=2.7V to 3.6V, Ta=-40°C to +85°C)
Item Symbol Condition Min. Typ. Max. Unit ∗
Static current consumption IDDS Static state, Tj=85°C ––90µA
Input leak age cur rent ILI -1 – 1 µA
Off-state leakage current IOZ -1 – 1 µA
High-level output voltage VOH IOH=-2mA (Type1), IOH=-6mA (Type2),
IOH=-12mA (T ype3), VDD=Min. VDD
-0.4 ––V
Low -lev el out pu t volta ge VOL IOL=2mA ( Type1), IOL=6mA (Ty pe2),
IOL=12mA (Type3), VDD=Min. ––0.4V
High-level input voltage VIH CMOS level, VDD=Max. 2.0 – –V
Low -lev el in put v olta ge VIL CMOS level, VDD=Min. ––0.8V
Positive trigger input voltage VT+ LVTTL Schmitt 1.1–2.4V
Negative trigger input voltage VT- LVTTL Sc hmitt 0.6–1.8V
Hysteresis voltage VHLVTTL Schmitt 0.1 – –V
Pull-up resistor RPU VI=0VOther than DSIO 80 200 480 kΩ
DSIO 40 100 240 kΩ
Pull-down r esistor RPD VI=VDD (ICEMD) 40 100 240 kΩ
Input pin capa citance CIf=1MHz, VDD=0V ––10pF
Output pin capacitance COf=1MHz, VDD=0V ––10pF
I/O pin capacitance CIO f=1MHz, VDD=0V ––10pF
Note:See Appendix B for pin characteristics.
8 ELECTRICAL CHARACTE RISTICS
A-74 EPSON S1C33L03 PRODUCT PART
3) 2.0 V single po w er source (Unless otherwise specified: VDDE=VDD=2V±0.2V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Condition Min. Typ. Max. Unit ∗
Static current consumption IDDS Static state, Tj=85°C ––80µA
Input leak age cur rent ILI -1 – 1 µA
Off-state leakage current IOZ -1 – 1 µA
High-level output voltage VOH IOH=-0.6mA (Type1), IOH=-2mA (Type2),
IOH=-4mA (T ype3), VDD=Min. VDD
-0.2 ––V
Low -l ev el ou tput voltage VOL IOL=0.6mA (Type1), IOL=2mA (Type2),
IOL=4mA (Ty pe3), VDD=Min. ––0.2V
High-level input voltage VIH CMOS level, VDD=Max. 1.6 – –V
Low -lev el in put v olta ge VIL CMOS level, VDD=Min. ––0.3V
Positive trigger input voltage VT+ CMOS Schmitt 0.4–1.6V
Negative trigger input voltage VT- CMOS Schmitt 0.3–1.4V
Hysteresis voltage VHCMOS Schmitt 0––V
Pull-up resistor RPU VI=0VOther than DSIO 120 480 1200 kΩ
DSIO 60 240 600 kΩ
Pull-down r esistor RPD VI=VDD (ICEMD) 60 240 600 kΩ
Input pin capa citance CIf=1MHz, VDD=0V ––10pF
Output pin capacitance COf=1MHz, VDD=0V ––10pF
I/O pin capacitance CIO f=1MHz, VDD=0V ––10pF
Note:See Appendix B for pin characteristics.
8 ELECTRICAL CHARACTE RISTICS
S1C33L03 PRODUCT PART EPSON A-75
A-1
A-8
8.4 Current Consump tion
1) 3.3 V power source
(Unless otherwise specified: VDDE=2.7V to 5.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Condition Min. Typ. Max. Unit ∗
Operating current IDD1 When CPU is operating 20MHz – 27 35 mA 1
33MHz – 45 60
50MHz – 65 85
IDD2 HALT mode 20MHz – 13 16 mA 2
33MHz – 22 30
50MHz – 30 40
IDD3 HALT2 mode 20MHz – 6 8 mA 3
33MHz – 9 12
50MHz – 14 18
IDD4 SLEEP mode – 1 30 µA 4
Clock timer operating current IDDCT When clock time r only is operating
OSC1 oscillation: 32kHz –7–µA5
2) 2.0 V power source (Unless otherwise specified: VDDE=VDD=2 .0V±0 .2V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Condition Min. Typ. Max. Unit ∗
Operating current IDD1 When CPU is operating 20MHz – 14 18 mA 1
IDD2 HALT mode 20MHz – 7 10 mA 2
IDD3 HALT2 mode 20MHz – 2.5 4 mA 3
IDD4 SLEEP mode – 1 30 µA 4
Clock timer operating current IDDCT When clock time r only is operating
OSC1 oscillation: 32kHz –1.5–µA5
3) Analog power current (Unless otherwise specified: VSS=0V, Ta=-40°C to +85°C)
Item Symbol Condition Min. Typ. Max. Unit ∗
A/D converter operating current AIDD1 VDD=3.6V, VDDE=AVDDE=5.0V±0.5V – 800 1400 µA 6
VDD=VDDE=AVDDE=2.7V to 3.6V – 500 800
4) LCD co ntroller operating current
(Unless otherwise specified: VDDE=2.7V to 5.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Condition Min. Typ. Max. Unit ∗
LCD controller operating current LIDD1 Display resolution = 320 × 240, 1bpp
LCDC CLK = 25MHz
(VRAM = SRAM)
–6.57mA
LIDD2 Display resolution = 320 × 240, 1bpp
LCDC CLK = 25MHz
(VRAM = SDRAM)
–1213mA
Current consumption measurement condition: VIH=VDD, VIL=0V, output pins are open, VDDE current is not included
∗ note) No. OSC3 OSC1 CPU Clock timer Other peripheral circuits ∗2
1On Off Normal operation ∗1Stop Stop
2On Off HALT mode Stop Stop
3On Off HALT2 mode Stop Stop
4Off O ff SLEEP mode Stop Stop
5Off On HALT mode Run Stop
6On Off HALT mode Stop A/D converter only operated,
conversion clock frequency=2MHz
∗1:The values of current consumption while the CPU is operating were measured when a test program that
consists of 55% load instructions, 23% arithmetic operation instructions, 1% mac instruction, 12% branch
instructions and 9% ext instruction is being executed in the built-in ROM continuously.
∗2:The LCD controller is included.
8 ELECTRICAL CHARACTE RISTICS
A-76 EPSON S1C33L03 PRODUCT PART
8.5 A/D Converter Characteristics
1) 3.3 V/5.0 V dual power source
(Unless otherwise specified: VDDE=AVDDE=4.5V to 5.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C, ST[1:0]=11)
Item Symbol Condition Min. Typ. Max. Unit ∗
Resolution – – 10 – bit
Conversion time – 5––µs1
Zero scale error EZS 024LSB
Full scale error EFS -2 – 2 LSB
Integral linearity error EL-3 – 3 LSB
Differential linearity error ED-3 – 3 LSB
Permissible signal source impedance – – – 5 kΩ
Analog input capacitance – – – 45 pF
∗ note 1) Indicates the minimum value when A/D clock = 4MHz (maximum clock frequency in 5V system).
Indicates the maximum value when A/D clock = 32kHz (minimum clock frequency in 5V system).
2) 3.3 V single po w er source
(Unless otherwise specified: VDDE=AVDDE=VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C, ST[1:0]=11)
Item Symbol Condition Min. Typ. Max. Unit ∗
Resolution – – 10 – bit
Conversion time – 10 – 625 µs 1
Zero scale error EZS 024LSB
Full scale error EFS -2 – 2 LSB
Integral linearity error EL-3 – 3 LSB
Differential linearity error ED-3 – 3 LSB
Permissible signal source impedance – – – 5 kΩ
Analog input capacitance – – – 45 pF
∗ note 1) Indicates the minimum value when A/D clock = 2MHz (maximum clock frequency in 3V system).
Indicates the maximum value when A/D clock = 32kHz (minimum clock frequency in 3V system).
Note:•Be sure to use as VDDE = AVDDE.
•The A/D convert er cannot be us ed when the S1C33L0 3 is used wit h a 2V powe r source.
A/D conversion error
V[000]h = Ideal voltage at zero-scale point (=0.5LSB)
V'[000]h = Actual voltage at zero-scale point
V[3FF]h = Ideal voltage at full-scale point (=1022.5LSB)
V'[3FF]h = Actual voltage at full-scale point
1LSB =
1LSB' =
AV
DDE
- V
SS
2
10
- 1
V'[3FF]h - V'[000]h
2
10
- 2
8 ELECTRICAL CHARACTE RISTICS
S1C33L03 PRODUCT PART EPSON A-77
A-1
A-8
V'[000]h
3FF
3FE
3FD
003
002
001
000V
SS
AV
DDE
Integral linearity error E
L
= [LSB]
V
N
' - V
N
1LSB'
Digital output (hex)
Analog input
Ideal conversion characteristic
Actual conversion characteristic
V'[3FF]h
V'[N]h
V
N
'V
N
V'[N-1]h
N+1
N
N-1
N-2
Integral linearity error
Differential linearity error
Differential linearity error E
D
= - 1 [LSB]
V'[N]h - V'[N-1]h
1LSB'
Digital output (hex)
Analog input
Ideal conversion characteristic
Actual conversion characteristic
V[000]h
(=0.5LSB)
V'[000]h
004
003
002
001
000
V
SS
Zero scale error
Zero scale error E
ZS
= [LSB]
(V'[000]h - 0.5LSB') - (V[000]h - 0.5LSB)
1LSB
Digital output (hex)
Analog input
Ideal conversion characteristic
Actual conversion characteristic
V[3FF]h (=1022.5LSB)
V'[3FF]h
3FF
3FE
3FD
3FC
3FB
AV
DDE
Full scale error
Full scale error E
FS
= [LSB]
(V'[3FF]h + 0.5LSB') - (V[3FF]h + 0.5LSB)
1LSB
Digital output (hex)
Analog input
Ideal conversion characteristic
Actual conversion characteristic
8 ELECTRICAL CHARACTE RISTICS
A-78 EPSON S1C33L03 PRODUCT PART
8.6 AC Characteristics
8.6.1 Symbol Description
tCYC: Bus-clock cycle time
• In x1 mode, tCYC = 50 ns (20 MHz) when the CPU is operated with a 20-MHz clock
tCYC = 30 ns (33 MHz) when the CPU is operated with a 33-MHz clock
• In x2 mode, tCYC = 50 ns (20 MHz) when the CPU is operated with a 40-MHz clock
tCYC = 40 ns (25 MHz) when the CPU is operated with a 50-MHz clock
tCYC = 33 ns (30 MHz) when the CPU is operated with a 60-MHz clock
WC: Numbe r of wait cycles
Up to 7 cycles can be set for the number of cycles using the BCU control register. Furthermore, it can be
extended to a desired number of cycles by setting the #WAIT pin from outside of the IC.
The mini mum numb er of read cycles with no wait (0) inserted is 1 cycle.
The mini mum number of write cycle s with no wait cycle (0) inserted is 2 cycles. It does not change even if
1-wait cycle is set. The write cycle is actually extended when 2 or more wait cycles are set.
When inserting wait cycles by controlling the #WAIT pin from outside of the IC, pay attention to the
timing of the #WAIT signal sampling. Read cycles are terminated at the cycle in which the #WAIT signal
is negated. Write cycles are terminated at the following cycle after the #WAIT signal is negated.
C1, C2, C3, Cn: Cy cl e number
C1 indicates the first cycle when the BCU transfers data from/to an external memory or another device.
Similarly, C2 and Cn indicate the second cycle and nth cycle, respectively.
Cw: Wai t cycle
Indicates that the cycle is wait cycle inserted.
8.6.2 AC Characteris tics Measurement Condition
Signal detection level: Input signal High level VIH = VDDE - 0 .4 V
Low level VIL = 0.4 V
Outp ut signal High level VOH = 1/2 VDDE
Low level VOL = 1/2 VDDE
The f ollowing applies when OSC3 is external clock input:
Input signal High level VIH = 1/2 VDD
Low level VIL = 1/2 VDD
Input signal waveform: Rise time (10% → 90% VDD)5 ns
Fall time (90% → 10 % V DD)5 ns
Outp ut load capacitance: CL = 50 pF
8 ELECTRICAL CHARACTE RISTICS
S1C33L03 PRODUCT PART EPSON A-79
A-1
A-8
8.6.3 C33 Block AC Characteristic Tables
External clock input characteristics
(Note) These AC characteristics apply to input signals from outside the IC.
The OSC3 input clock must be within VDD to VSS voltage range.
1) 3.3 V/5.0 V dual power source
(Unless otherwise specified: VDDE=5.0V±0.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Min. Max. Unit ∗
High-speed clock cycle time tC3 30 ns
OSC3 cl ock input duty tC3ED 45 55 %
OSC3 cl ock input rise time tIF 5ns
OSC3 cl ock input fall time tIR 5ns
BCLK high-level output delay time tCD1 35 ns
BCLK low-level output del ay time tCD2 35 ns
Minimum reset pulse width tRST 6·tCYC ns
2) 3.3 V single po w er source (Unless otherwise specified: VDDE=VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Min. Max. Unit ∗
High-speed clock cycle time tC3 30 ns
OSC3 cl ock input duty tC3ED 45 55 %
OSC3 cl ock input rise time tIF 5ns
OSC3 cl ock input fall time tIR 5ns
BCLK high-level output delay time tCD1 35 ns
BCLK low-level output del ay time tCD2 35 ns
Minimum reset pulse width tRST 6·tCYC ns
3) 2.0 V single po w er source (Unless otherwise specified: VDDE=VDD=2.0V±0.2V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Min. Max. Unit ∗
High-speed clock cycle time tC3 50 ns
OSC3 cl ock input duty tC3ED 45 55 %
OSC3 cl ock input rise time tIF 5ns
OSC3 cl ock input fall time tIR 5ns
BCLK high-level output delay time tCD1 60 ns
BCLK low-level output del ay time tCD2 60 ns
Minimum reset pulse width tRST 6·tCYC ns
BCL K cl ock o u tpu t chara cteristic s
(Note) These AC characteristic values are applied only when the high-speed oscillation circuit is used.
1) 3.3 V/5.0 V dual power source
(Unless otherwise specified: VDDE=5.0V±0.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Min. Max. Unit ∗
BCLK clock output duty tCBD 40 60 %
2) 3.3 V single po w er source (Unless otherwise specified: VDDE=VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Min. Max. Unit ∗
BCLK clock output duty tCBD 40 60 %
3) 2.0 V single po w er source (Unless otherwise specified: VDDE=VDD=2.0V±0.2V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Min. Max. Unit ∗
BCLK clock output duty tCBD 40 60 %
8 ELECTRICAL CHARACTE RISTICS
A-80 EPSON S1C33L03 PRODUCT PART
Common characteristics
1) 3.3 V/5.0 V dual power source
(Unless otherwise specified: VDDE=5.0V±0.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Min. Max. Unit ∗
Address delay time tAD –8ns1
#CEx delay time (1) tCE1 –8ns
#CEx delay time (2) tCE2 –8ns
Wait setup time tWTS 15 – ns
Wait hold time tWTH 0–ns
Read signal delay time (1) tRDD1 8ns2
Read d ata setup time tRDS 12 ns
Read d ata hold time tRDH 0ns
Write signal delay time (1) tWRD1 8ns3
Write data delay time (1) tWDD1 10 ns
Write data delay time (2) tWDD2 010ns
Write data hold tim e tWDH 0ns
2) 3.3 V single po w er source (Unless otherwise specified: VDDE=VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Min. Max. Unit ∗
Address delay time tAD –10ns1
#CEx delay time (1) tCE1 –10ns
#CEx delay time (2) tCE2 –10ns
Wait setup time tWTS 15 – ns
Wait hold time tWTH 0–ns
Read signal delay time (1) tRDD1 10 ns 2
Read d ata setup time tRDS 15 ns
Read d ata hold time tRDH 0ns
Write signal delay time (1) tWRD1 10 ns 3
Write data delay time (1) tWDD1 10 ns
Write data delay time (2) tWDD2 010ns
Write data hold tim e tWDH 0ns
3) 2.0 V single po w er source (Unless otherwise specified: VDDE=VDD=2.0V±0.2V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Min. Max. Unit ∗
Address delay time tAD –20ns1
#CEx delay time (1) tCE1 –20ns
#CEx delay time (2) tCE2 –20ns
Wait setup time tWTS 40 – ns
Wait hold time tWTH 0–ns
Read signal delay time (1) tRDD1 20 ns 2
Read d ata setup time tRDS 40 ns
Read d ata hold time tRDH 0ns
Write signal delay time (1) tWRD1 20 ns 3
Write data delay time (1) tWDD1 20 ns
Write data delay time (2) tWDD2 020ns
Write data hold tim e tWDH 0ns
∗ note1) This applies to the #BSH and #BSL timings.
2) This applies to the #GAAS and #GARD timings.
3) This applies to the #GAAS timing.
8 ELECTRICAL CHARACTE RISTICS
S1C33L03 PRODUCT PART EPSON A-81
A-1
A-8
SRAM read cycle
1) 3.3 V/5.0 V dual power source
(Unless otherwise specified: VDDE=5.0V±0.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Min. Max. Unit ∗
Read signal delay time (2) tRDD2 8ns
Read signal pulse width tRDW tCYC(0.5+WC)-8 ns
Read a ddress access time (1) tACC1 tCYC(1+WC)-20 ns
Chip e nable access time (1) tCEAC1 tCYC(1+WC)-20 ns
Read signal access time (1) tRDAC1 tCYC(0.5+WC)-20 ns
2) 3.3 V single po w er source (Unless otherwise specified: VDDE=VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Min. Max. Unit ∗
Read signal delay time (2) tRDD2 10 ns
Read signal pulse width tRDW tCYC(0.5+WC)-10 ns
Read a ddress access time (1) tACC1 tCYC(1+WC)-25 ns
Chip e nable access time (1) tCEAC1 tCYC(1+WC)-25 ns
Read signal access time (1) tRDAC1 tCYC(0.5+WC)-25 ns
3) 2.0 V single po w er source (Unless otherwise specified: VDDE=VDD=2.0V±0.2V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Min. Max. Unit ∗
Read signal delay time (2) tRDD2 10 ns
Read signal pulse width tRDW tCYC(0.5+WC)-10 ns
Read a ddress access time (1) tACC1 tCYC(1+WC)-60 ns
Chip e nable access time (1) tCEAC1 tCYC(1+WC)-60 ns
Read signal access time (1) tRDAC1 tCYC(0.5+WC)-60 ns
SRAM write cycle
1) 3.3 V/5.0 V dual power source
(Unless otherwise specified: VDDE=5.0V±0.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Min. Max. Unit ∗
Write signal delay time (2) tWRD2 8ns
Write signal pulse width tWRW tCYC(1+WC)-10 ns
2) 3.3 V single po w er source (Unless otherwise specified: VDDE=VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Min. Max. Unit ∗
Write signal delay time (2) tWRD2 10 ns
Write signal pulse width tWRW tCYC(1+WC)-10 ns
3) 2.0 V single po w er source (Unless otherwise specified: VDDE=VDD=2.0V±0.2V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Min. Max. Unit ∗
Write signal delay time (2) tWRD2 20 ns
Write signal pulse width tWRW tCYC(1+WC)-20 ns
8 ELECTRICAL CHARACTE RISTICS
A-82 EPSON S1C33L03 PRODUCT PART
DRAM access cyc le common ch aracteristics
1) 3.3 V/5.0 V dual power source
(Unless otherwise specified: VDDE=5.0V±0.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Min. Max. Unit ∗
#RAS signal delay time (1) tRASD1 10 ns
#RAS signal delay time (2) tRASD2 10 ns
#RAS signal pulse width tRASW tCYC(2+WC)-10 ns
#CAS signal delay time (1) tCASD1 10 ns
#CAS signal delay time (2) tCASD2 10 ns
#CAS signal pulse width tCASW tCYC(0.5+WC)-5 ns
Read signal delay time (3) tRDD3 10 ns
Read signal pulse width (2) tRDW2 tCYC(2+WC)-10 ns
Write signal delay time (3) tWRD3 10 ns
Write signal pulse width (2) tWRW2 tCYC(2+WC)-10 ns
2) 3.3 V single po w er source (Unless otherwise specified: VDDE=VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Min. Max. Unit ∗
#RAS signal delay time (1) tRASD1 10 ns
#RAS signal delay time (2) tRASD2 10 ns
#RAS signal pulse width tRASW tCYC(2+WC)-10 ns
#CAS signal delay time (1) tCASD1 10 ns
#CAS signal delay time (2) tCASD2 10 ns
#CAS signal pulse width tCASW tCYC(0.5+WC)-10 ns
Read signal delay time (3) tRDD3 10 ns
Read signal pulse width (2) tRDW2 tCYC(2+WC)-10 ns
Write signal delay time (3) tWRD3 10 ns
Write signal pulse width (2) tWRW2 tCYC(2+WC)-10 ns
3) 2.0 V single po w er source (Unless otherwise specified: VDDE=VDD=2.0V±0.2V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Min. Max. Unit ∗
#RAS signal delay time (1) tRASD1 20 ns
#RAS signal delay time (2) tRASD2 20 ns
#RAS signal pulse width tRASW tCYC(2+WC)-20 ns
#CAS signal delay time (1) tCASD1 20 ns
#CAS signal delay time (2) tCASD2 20 ns
#CAS signal pulse width tCASW tCYC(0.5+WC)-20 ns
Read signal delay time (3) tRDD3 20 ns
Read signal pulse width (2) tRDW2 tCYC(2+WC)-20 ns
Write signal delay time (3) tWRD3 20 ns
Write signal pulse width (2) tWRW2 tCYC(2+WC)-20 ns
8 ELECTRICAL CHARACTE RISTICS
S1C33L03 PRODUCT PART EPSON A-83
A-1
A-8
DRAM random access cycle and DRAM fast- page cycle
1) 3.3 V/5.0 V dual power source
(Unless otherwise specified: VDDE=5.0V±0.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Min. Max. Unit ∗
Colum n a ddress ac cess tim e tACCF tCYC(1+WC)-25 ns
#RAS access time tRACF tCYC(1.5+WC)-25 ns
#CAS access time tCACF tCYC(0.5+WC)-25 ns
2) 3.3 V single po w er source (Unless otherwise specified: VDDE=VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Min. Max. Unit ∗
Colum n a ddress ac cess tim e tACCF tCYC(1+WC)-25 ns
#RAS access time tRACF tCYC(1.5+WC)-25 ns
#CAS access time tCACF tCYC(0.5+WC)-25 ns
3) 2.0 V single power source (Unless otherwise specified: VDDE=VDD=2.0V±0.2V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Min. Max. Unit ∗
Colum n a ddress ac cess tim e tACCF tCYC(1+WC)-60 ns
#RAS access time tRACF tCYC(1.5+WC)-60 ns
#CAS access time tCACF tCYC(0.5+WC)-60 ns
EDO DRAM random access cyc le and EDO DRAM page cyc le
1) 3.3 V/5.0 V dual power source
(Unless otherwise specified: VDDE=5.0V±0.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Min. Max. Unit ∗
Colum n a ddress ac cess tim e tACCE tCYC(1.5+WC)-25 ns
#RAS access time tRACE tCYC(2+WC)-25 ns
#CAS access time tCACE tCYC(1+WC)-15 ns
Read d ata setup time tRDS2 20 ns
2) 3.3 V single po w er source (Unless otherwise specified: VDDE=VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Min. Max. Unit ∗
Colum n a ddress ac cess tim e tACCE tCYC(1.5+WC)-25 ns
#RAS access time tRACE tCYC(2+WC)-25 ns
#CAS access time tCACE tCYC(1+WC)-20 ns
Read d ata setup time tRDS2 20 ns
3) 2.0 V single po w er source (Unless otherwise specified: VDDE=VDD=2.0V±0.2V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Min. Max. Unit ∗
Colum n a ddress ac cess tim e tACCE tCYC(1.5+WC)-60 ns
#RAS access time tRACE tCYC(2+WC)-60 ns
#CAS access time tCACE tCYC(1+WC)-60 ns
Read d ata setup time tRDS2 20 ns
8 ELECTRICAL CHARACTE RISTICS
A-84 EPSON S1C33L03 PRODUCT PART
SDRAM access cycle
1) #X2SP D = "1" (C PU : SDRAM cl ock = 1 : 1), 3.3 V single power source
(Unless otherwise specified: VDDE=VDD=3.0V to 3.6V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Min. Max. Unit ∗
OSC3 input clock frequency fOSC3 25 MHz
BCLK clock output cycle time t(C3) 40 ns
Address delay time t(AD) 11 ns
SDA10 delay time t(A10D) 11 ns
#SDCEx delay time (1) t(CED)n 11 ns
#SDCEx delay time (2) t(CED)p 11 ns
#SDRAS signal delay time (1) t(RASD)n 12 ns
#SDRAS signal delay time (2) t(RASD)p 11 ns
#SDCAS signal delay time (1) t(CASD)n 11 ns
#SDCAS signal delay time (2) t(CASD)p 11 ns
HDQM, LDQM signal delay time (1) t(DQMD)n 11 ns
HDQM, LDQM signal delay time (2) t(DQMD)p 11 ns
SDCKE signal delay time (1) t(CKED)n 11 ns
SDCKE signal delay time (2) t(CKED)p 11 ns
#SDWE signal delay time (1) t(WED)n 11 ns
#SDWE signal delay time (2) t(WED)p 11 ns
Read d ata setup time t(RDS) (14) ns
Read d ata hold time t(RDH) (0) ns
Write data delay time t(WDD) 11 ns
Write data hold tim e t(WDH) T+11 ns
2) #X2SPD = "0 " (CP U : SD RAM clock = 2 : 1), 3. 3 V single power source
(Unless otherwise specified: VDDE=VDD=3.0V to 3.6V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Min. Max. Unit ∗
OSC3 input clock frequency fOSC3 17.5 MHz
BCLK clock output cycle time t(C3x2) 57 ns
Address delay time t(ADx2) T+11 ns
SDA10 delay time t(A10Dx2) T+11 ns
#SDCEx delay time (1) t(CEDx2)n T+11 ns
#SDCEx delay time (2) t(CEDx2)p T+11 ns
#SDRAS signal delay time (1) t(RASDx2)n T+11 ns
#SDRAS signal delay time (2) t(RASDx2)p T+11 ns
#SDCAS signal delay time (1) t(CASDx2)n T+11 ns
#SDCAS signal delay time (2) t(CASDx2)p T+11 ns
HDQM, LDQM signal delay time (1) t(DQMDx2)n T+11 ns
HDQM, LDQM signal delay time (2) t(DQMDx2)p T+11 ns
SDCKE signal delay time (1) t(CKEDx2)n T+11 ns
SDCKE signal delay time (2) t(CKEDx2)p T+11 ns
#SDWE signal delay time (1) t(WEDx2)n T+11 ns
#SDWE signal delay time (2) t(WEDx2)p T+11 ns
Read d ata setup time t(RDSx2) (14) ns
Read d ata hold time t(RDHx2) (0) ns
Write data delay time t(WDDx2) 11 ns
Write data hold tim e t(WDHx2) T+11 ns
Note:"T" indicates one cycle time of the CPU clock.
8 ELECTRICAL CHARACTE RISTICS
S1C33L03 PRODUCT PART EPSON A-85
A-1
A-8
Burst ROM read cycle
1) 3.3 V/5.0 V dual power source
(Unless otherwise specified: VDDE=5.0V±0.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Min. Max. Unit ∗
Read a ddress access time (2) tACC2 tCYC(1+WC)-20 ns
Chip e nable access time (2) tCEAC2 tCYC(1+WC)-20 ns
Read signal access time (2) tRDAC2 tCYC(0.5+WC)-20 ns
Burst address access time tACCB tCYC(1+WC)-20 ns
2) 3.3 V single po w er source (Unless otherwise specified: VDDE=VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Min. Max. Unit ∗
Read a ddress access time (2) tACC2 tCYC(1+WC)-25 ns
Chip e nable access time (2) tCEAC2 tCYC(1+WC)-25 ns
Read signal access time (2) tRDAC2 tCYC(0.5+WC)-25 ns
Burst addr es s ac ce ss tim e tACCB tCYC(1+WC)-25 ns
3) 2.0 V single po w er source (Unless otherwise specified: VDDE=VDD=2.0V±0.2V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Min. Max. Unit ∗
Read a ddress access time (2) tACC2 tCYC(1+WC)-60 ns
Chip e nable access time (2) tCEAC2 tCYC(1+WC)-60 ns
Read signal access time (2) tRDAC2 tCYC(0.5+WC)-60 ns
Burst addr es s ac ce ss tim e tACCB tCYC(1+WC)-60 ns
External bus master and NMI
1) 3.3 V/5.0 V dual power source
(Unless otherwise specified: VDDE=5.0V±0.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Min. Max. Unit ∗
#BUSREQ signal setup time tBRQS 15 ns
#BUSREQ signal hold time tBRQH 0ns
#BUSACK signal output delay time tBAKD 10 ns
High-impedance → output delay time tZ2E 10 ns
Output → high-impedance delay time tB2Z 10 ns
#NMI pulse width tNMIW 30 ns
2) 3.3 V single po w er source (Unless otherwise specified: VDDE=VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Min. Max. Unit ∗
#BUSREQ signal setup time tBRQS 15 ns
#BUSREQ signal hold time tBRQH 0ns
#BUSACK signal output delay time tBAKD 10 ns
High-impedance → output delay time tZ2E 10 ns
Output → high-impedance delay time tB2Z 10 ns
#NMI pulse width tNMIW 30 ns
3) 2.0 V single po w er source (Unless otherwise specified: VDDE=VDD=2.0V±0.2V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Min. Max. Unit ∗
#BUSREQ signal setup time tBRQS 40 ns
#BUSREQ signal hold time tBRQH 0ns
#BUSACK signal output delay time tBAKD 20 ns
High-impedance → output delay time tZ2E 20 ns
Output → high-impedance delay time tB2Z 20 ns
#NMI pulse width tNMIW 90 ns
8 ELECTRICAL CHARACTE RISTICS
A-86 EPSON S1C33L03 PRODUCT PART
Input, Output and I/O port
1) 3.3 V/5.0 V dual power source
(Unless otherwise specified: VDDE=5.0V±0.5V, VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Min. Max. Unit ∗
Input data setup time tINPS 20 ns
Input dat a hold tim e tINPH 10 ns
Output data delay time tOUTD 20 ns
K-port interrupt SLEEP, HALT2 mode tKINW 30 ns
input pulse width Others 2 × tCYC ns
2) 3.3 V single po w er source (Unless otherwise specified: VDDE=VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Min. Max. Unit ∗
Input data setup time tINPS 20 ns
Input dat a hold tim e tINPH 10 ns
Output data delay time tOUTD 20 ns
K-port interrupt SLEEP, HALT2 mode tKINW 30 ns
input pulse width Others 2 × tCYC ns
3) 2.0 V single po w er source (Unless otherwise specified: VDDE=VDD=2.0V±0.2V, VSS=0V, Ta=-40°C to +85°C)
Item Symbol Min. Max. Unit ∗
Input data setup time tINPS 40 ns
Input dat a hold tim e tINPH 20 ns
Output data delay time tOUTD 30 ns
K-port interrupt SLEEP, HALT2 mode tKINW 90 ns
input pulse width Others 2 × tCYC ns
8 ELECTRICAL CHARACTE RISTICS
S1C33L03 PRODUCT PART EPSON A-87
A-1
A-8
8.6.4 C33 Block AC Characteristic Timing Ch arts
Clock
OSC3
(High-speed clock)
t
C3
BCLK
(Clock output)
t
C3
t
C3H
t
C3ED =
t
C3H/
t
C3
t
CBD =
t
CBH/
t
C3
BCLK
(Clock output)
t
C3
t
CBH
t
CD1
t
CD2
t
IF
t
IR
(1) When an external clock is input (in x1 speed mode):
(2) When the high-speed oscillation circuit is used for the operating clock:
8 ELECTRICAL CHARACTE RISTICS
A-88 EPSON S1C33L03 PRODUCT PART
SRAM read cycle (basic cyc le : 1 cycle)
BCLK
A[23:0]
#CEx
#RD
D[15:0]
#WAIT
t
C3
t
AD
t
CE1
t
CE2
t
RDD2
t
RDD1
t
RDAC1
t
RDS
t
WTS
t
WTH
t
RDH
t
CEAC1
t
ACC1
t
RDW
t
AD
;;;;;;;
;;;;;;;
;;;;;;
;;;;;;
;;;;;;
;;;;;;
;;;;
;;;;
∗1
*1 tRDH is measured with respect to the first signal change (negation) from among the #RD, #CEx and
A[23 :0] sig nals.
SRAM read cycle (when a wait cycle is inserted)
BCLK
A[23:0]
#CEx
#RD
D[15:0]
#WAIT
C1 Cw
(wait cycle)
Cn
(last cycle)
t
AD
t
CE1
t
CE2
t
RDD2
t
RDD1
(C1 only)
t
RDAC1
t
RDS
t
WTS
t
WTH
t
WTS
t
WTH
t
RDH
t
CEAC1
t
ACC1
t
RDW
t
AD
;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;
;;;;;;;;
;;;;;;;
;;;;;;;
;;;;
;;;;
∗1
t
WTS
t
WTH
*1 tRDH is measured with respect to the first signal change (negation) from among the #RD, #CEx and
A[23 :0] sig nals.
8 ELECTRICAL CHARACTE RISTICS
S1C33L03 PRODUCT PART EPSON A-89
A-1
A-8
SRAM write cycle (ba sic cycle: 2 cycles)
BCLK
A[23:0]
#CEx
#WR
D[15:0]
#WAIT
C1 C2
t
AD
t
CE1
t
CE2
t
WRD2
t
WRD1
t
WTS
t
WTH
t
WDD1
t
WDH
t
WRW
t
AD
;;;;;;
;;;;;;
;;;;
;;;;
;;;;
;;;;
SRAM write cycle (when wait cycles are inserted)
BCLK
A[23:0]
#CEx
#WR
D[15:0]
#WAIT
C1 Cw(wait cycle) Cw(wait cycle) Cn(last cycle)
tAD
tCE1 tCE2
tWRD2tWRD1
tWTS tWTH tWTS tWTStWTH tWTH
tWDD1 tWDH
tWRW
tAD
;;;;;;;;;;;;;;
;;;;;;;;;;;;;;
;;;;;
;;;;;
;;;;;
;;;;;
;;;
;;;
Wait cycle follows Last cycle follows
8 ELECTRICAL CHARACTE RISTICS
A-90 EPSON S1C33L03 PRODUCT PART
DRAM random access cycle (basic cycle)
BCLK
A[23:0]
#RAS
#HCAS/
#LCAS
#RD
D[15:0]
#WE
D[15:0]
RAS1
Data transfer #1 Next data transfer
CAS1 PRE1(precharge) RAS1' CAS1'
t
AD
t
AD
t
AD
t
CASD2
t
CASD1
t
RDS
t
ACCF
t
RACF
t
RDH
t
RASD2
t
RASD1
t
RASW
t
RDD3
t
RDD1
t
RDW2
t
WRD3
t
WRD1
t
WRW2
;;;;;;;;;
;;;;;;;;;
;;;;;;;;;;
;;;;;;;;;;
;;;;;;;
;;;;;;;
;;;;;
;;;;;
t
WDD1
t
WDD2
;;;;;
;;;;;
t
CASW
t
CACF
∗1
∗1tRDH is measured with respect to the first signal change (negation) of either the #RD or the A[23:0]
signals.
DRAM fast- pag e access cyc le
BCLK
A[23:0]
#RAS
#HCAS/
#LCAS
#RD
D[15:0]
#WE
D[15:0]
RAS1
Data transfer #1 Data transfer #2 Next data transfer
CAS1 CAS2 PRE1
(precharge)
RAS1'
t
AD
t
AD
t
AD
t
RDS
t
ACCF
t
RACF
t
RDH
t
RASD2
t
RASD1
t
RDD3
t
RDD1
t
WRD3
t
WRD1
;;;;;;;;;
;;;;;;;;;
;;;;;;;;;;
;;;;;;;;;;
;;;;;
;;;;;
;;;;;
;;;;;
t
WDD1
t
WDD2
t
WDD2
;;;;;
;;;;;
t
CACF
t
ACCF
t
RASW
t
RDW2
t
CASD2
t
CASD1
t
RDS
t
RDH
;;;;;
;;;;;
t
CASW
t
WRW2
∗1∗1
∗1tRDH is measured with respect to the first signal change (negation) of either the #RD or the A[23:0] signals.
8 ELECTRICAL CHARACTE RISTICS
S1C33L03 PRODUCT PART EPSON A-91
A-1
A-8
EDO DRAM random access cyc le (basic cycle )
BCLK
A[23:0]
#RAS
#HCAS/
#LCAS
#RD
D[15:0]
#WE
D[15:0]
RAS1
Data transfer #1 Next data transfer
CAS1 PRE1
(precharge)
RAS1' CAS1'
t
AD
t
AD
t
AD
t
CASD2
t
CASD1
t
RDS2
t
ACCE
t
RACE
t
RDH
t
RASD2
t
RASD1
t
RASW
t
RDD3
t
RDD1
t
RDW2
t
WRD3
t
WRD1
t
WRW2
;;;;;;;;;
;;;;;;;;;
;;;;;;;;;;
;;;;;;;;;;
;;;
;;;
t
WDD1
t
WDD2
;;;;;
;;;;;
t
CASW
t
CACE
∗1
∗1tRDH is measured with respect to the first signal change (negation) of either the #RD or the #RASx signals.
EDO DRAM pag e access cyc le
BCLK
A[23:0]
#RAS
#HCAS/
#LCAS
#RD
D[15:0]
#WE
D[15:0]
RAS1
Data transfer #1 Data transfer #2 Next data transfer
CAS1 CAS2 PRE1(precharge) RAS1'
t
AD
t
AD
t
AD
t
RDS
t
ACCE
t
RACE
t
RASD2
t
RASD1
t
RDD3
t
RDD1
t
WRD3
t
WRD1
;;;;;;;;;
;;;;;;;;;
;;;;;;;;;;;;;;
;;;;;;;;;;;;;;
;;;;;
;;;;;
;;;;
;;;;
t
WDD1
t
WDD2
t
WDD2
;;;;;
;;;;;
t
CACE
t
ACCE
t
RASW
t
RDW2
t
CASD2
t
CASD1
;;;;
;;;;
t
CASW
t
WRW2
t
RDH
t
RDS
t
RDH
∗1
∗1tRDH is measured with respect to the first signal change from among the #RD (negation), #RASx (negation)
and #CAS (fall) signals.
8 ELECTRICAL CHARACTE RISTICS
A-92 EPSON S1C33L03 PRODUCT PART
DRAM CAS -b e fo r e-R AS refresh cycle
BCLK
#RAS
#HCAS/
#LCAS
#WE
CBR refresh cycle
C
CBR1
C
CBR2
C
CBR3
t
RASD2
t
RASD1
t
CASD2
t
CASD1
;;;;;;;;
;;;;;;;;
;;;;;;
;;;;;;
;;;;;;;;
;;;;;;;;
;;;;;;
;;;;;;
DRAM self-refresh cycle
BCLK
#RAS
#HCAS/
#LCAS
Self-refresh mode setup Self-refresh mode
tCASD2
;;;;;;;
;;;;;;;
;;;;
;;;;
Self-refresh mode canceration
tRASD2tRASD1
tCASD1
6-cycle precharge
(Fixed)
SDRAM clock
OSC3
(High-speed clock)
BCLK
(SDRAM clock output)
t
C3
t
CBD =
t
CBH/
t
C3
t
CBD =
t
CBH/
t
C3
BCLK
(SDRAM clock output)
t
C3
t
CBH
t
CBH
(1) #X2SPD = high (CPU clock : SDRAM clock = 1 : 1)
(2) #X2SPD = low (CPU clock : SDRAM clock = 2 : 1)
8 ELECTRICAL CHARACTE RISTICS
S1C33L03 PRODUCT PART EPSON A-93
A-1
A-8
SDRAM access cycle
(Bank, Row) (Column)
t
WED2
t
CASD2
BCLK
SDCKE
A[23:0]
SDA10
#SDCEx
#SDRAS
#SDCAS
#SDWE (read)
D[15:0]
HDQM/
LDQM
#SDWE (write)
D[15:0]
Bank active
t
AD
;;;;;;;;;;;;;
;;;;;;;;;;;;;
;;;;
;;;;
;;;
;;;
Read/write nop
H
valid valid valid
t
A10D
t
CED1
t
CED2
t
WED1
t
WED1
t
WED2
t
DQMD1
t
WDH
t
WDD
t
DQMD2
;;;;;;;;;;;;;
;;;;;;;;;;;;;
;;;;
;;;;
;;;
;;;
valid valid valid
;;;;
;;;;
;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;
validvalid
;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;
;;;;;;
;;;;;;
valid
nop Precharge
t
RASD1
t
RASD2
t
CASD1
t
RDH
t
RDS
∗Read: CAS latency = 2, burst length = 2 Write: single write
SDRAM mode-register-set cycle
t
CASD2
BCLK
SDCKE
A[23:0]
SDA10
#SDCEx
#SDRAS
#SDCAS
#SDWE
D[15:0]
HDQM/
LDQM
Mode register set
t
AD
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;
;;;
nop nop
H
valid
t
AD
t
CED1
t
CED2
t
WED1
t
WED2
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;
;;;
valid
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;
nop nop
;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
t
RASD1
t
RASD2
t
CASD1
8 ELECTRICAL CHARACTE RISTICS
A-94 EPSON S1C33L03 PRODUCT PART
SDRAM auto-refresh cycle
t
CASD2
BCLK
SDCKE
A[23:0]
SDA10
#SDCEx
#SDRAS
#SDCAS
#SDWE
D[15:0]
HDQM/
LDQM
Auto refresh nop nop
H
t
CED1
t
CED2
t
WED1
t
WED2
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;
nop nop
;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
t
RASD1
t
RASD2
t
CASD1
∗A precharge cycle is necessary before entering the auto refresh mode.
SDRAM self-refresh cycle
BCLK
SDCKE
A[23:0]
SDA10
#SDCEx
#SDRAS
#SDCAS
#SDWE
D[15:0]
HDQM/
LDQM
t
CED1
t
CED2
t
WED1
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
Exit self refresh modeEnter self refresh mode
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
t
RASD1
t
CASD1
t
CKE1
t
CKE2
;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
∗A precharge cycle is necessary before entering the self refresh mode.
8 ELECTRICAL CHARACTE RISTICS
S1C33L03 PRODUCT PART EPSON A-95
A-1
A-8
Burst ROM read cycle
BCLK
A[23:2]
A[1:0]
#CEx
#RD
D[15:0]
SRAM read cycle Burst cycle Burst cycle Burst cycle
tAD tAD
tAD
tRDS
tRDAC2
tCEAC
tRDH
tCE2tCE1
tRDD2tRDD1
;;;;;
;;;;;
tAD tAD tAD tAD
tACC2
tRDS
tRDH
;;;;;
;;;;;
tACCB
tRDS
tRDH
;;;;;
;;;;;
tACCB
tRDS
tRDH
;;;;;
;;;;;
tACCB
∗1
∗1tRDH is measured with respect to the first signal change (negation) from among the #RD, #CEx and
A[23 :0] sig nals.
#BUSREQ, #BUSACK an d #NMI timing
BCLK
#BUSREQ
#BUSACK
eBUS_OUT signals ∗1
eBUS_OUT signals ∗1
#NMI
t
BRQS
Valid input
t
NMIW
t
BRQH
;;;;;
;;;;;
t
BAKD
t
Z2E
t
B2Z
;;;
;;;
∗1eBUS_OUT indicates the following pins:
A[23:0], #RD, #WRL, #WRH, #H CAS, #LCA S, #CE[17:4], D[ 15:0]
Input, output and I/O port timing
BCLK
Kxx, Pxx
(input: data read
from the port)
Pxx, Rxx (output)
Kxx
(K-port interrupt input)
t
INPS
Valid input
t
KINW
t
INPH
;;;;;
;;;;;
t
OUTD
;;;;
;;;;
8 ELECTRICAL CHARACTE RISTICS
A-96 EPSON S1C33L03 PRODUCT PART
8.6.5 LCD Interface AC Characteristics
Conditions: VDDE=3.3V± 10% or 5.0V±10 % , Ta=-40° C to +85° C, CL=6 0pF (LCD pane l i nterf ace)
Trise and Tfall for all inputs must be less than 5 ns (10%–90%).
Power up/down timing
LCDCEN bit
LPWEREN bit
LPSAVE[1:0] bits
FP signals
LCDPWR signal
ActiveInactive Inactive Active Inactive
t1t1t4t4
t3t5t6t6t2
11 1100 00 00
Symbol Parameter Min. Typ. Max. Unit
t1Power Save inactive to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY
active 1Frame
t2FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY active to LCDPWR
active 0Frame
t3Power Save active to LCDPWR inactive 1 Frame
t4Power Save active to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY
inactive 1Frame
t5LPWREN = "1" to LCDPWR active (when FP signals are active) 0Frame
t6LPWREN = "0" to LCDPWR inactive 0 Frame
8 ELECTRICAL CHARACTE RISTICS
S1C33L03 PRODUCT PART EPSON A-97
A-1
A-8
4-bit single monochrom e panel t iming
FPFRAME
FPLINE
DRDY (MOD)
FPDAT[7:4]
VDP VNDP
FPLINE
DRDY (MOD)
FPSHIFT
FPDAT7
FPDAT6
FPDAT5
FPDAT4
Line 1
1-1 1-5 1-317
1-2 1-6 1-318
1-3 1-7 1-319
1-4 1-8 1-320
Line 2 Line 3 Line 1 Line 2Line 4 Line 239 Line 240
HDP HNDP
∗Diagram drawn with 2 FPLINE vertical blank period
Example tim in g for a 320 × 240 panel
For this timing diagram FPSMASK (D2/0x39FFE1) is set to "1"
VDP = Vertical Display Period = LDVSIZE[9:0] + 1 (lines)
LDVSIZE[9:0] (0x39FFE5, D[1:0]/0x39FFE6)
VNDP = Vertical Non-Dis play Period = VNDP[5:0] (lines)
VNDP[5:0] (D[5:0]/0x39FFEA)
HDP = Horizontal Display Period = (L DHS I ZE[5:0] + 1) × 16 (Ts)
LDHSIZE[5:0] (D[5:0]/0x39FFE4)
HNDP = Horizontal Non-Display Period = (HNDP [4: 0] + 4) × 8 (Ts)
HNDP[4:0] (D[4:0]/0x39FFE7)
8 ELECTRICAL CHARACTE RISTICS
A-98 EPSON S1C33L03 PRODUCT PART
Frame Pulse
Line Pulse
DRDY (MOD)
Sync Timing
21
t2t1
t5
t6t8t9
t7t14 t11 t10
t12 t13
t4t3
Line Pulse
Shift Pulse
FPDAT[7:4]
Data Timing
Note:For this timing diagram FPSMASK (D2/0x39FFE1) is set to "1".
4-bit Singl e Mon ochrom e Panel AC Timing
Symbol Parameter Min. Typ. Max. Unit
t1Frame Pulse setup to Line Pulse falling edge note 2 (note 1)
t2Frame Pulse hold from Line Pulse falling edge 9 Ts
t3Line P ul se period note 3
t4Line P ul se widt h 9 Ts
t5MOD delay from Line Pulse rising edge 1 Ts
t6Shift Pulse falling edge to Line Pulse rising edge note 4
t7Shift Pulse falling edge to Line Pulse falling edge note 5
t8Line Pulse falling edge to Shift Pulse falling edge t14+2 Ts
t9Shift Pulse period 4 Ts
t10 Shift Pulse width low 2 Ts
t11 Shift Pulse width high 2 Ts
t12 FPDAT[7:4] setup to Shift Pulse falling edge 2 Ts
t13 FPDAT[7:4] hold from Shift Pulse falling edge 2 Ts
t14 Line Pulse falling edge to Shift Pulse rising edge 23 Ts
note) 1.Ts = pixel clock period
2.t1min = t3min - 9 (Ts)
3.t3min = (LDHSIZE[5:0] + 1) × 16 + (HNDP[4:0] + 4) × 8 (Ts)
4.t6min = HNDP[4:0] × 8 + 2 (Ts)
5.t7min = HNDP[4:0] × 8 + 11 (Ts)
8 ELECTRICAL CHARACTE RISTICS
S1C33L03 PRODUCT PART EPSON A-99
A-1
A-8
8-bit single monochrom e panel t iming
FPFRAME
FPLINE
DRDY (MOD)
FPDAT[7:0]
VDP VNDP
FPLINE
DRDY (MOD)
FPSHIFT
FPDAT7
FPDAT6
FPDAT5
FPDAT4
FPDAT3
FPDAT2
FPDAT1
FPDAT0
Line 1
1-1 1-9 1-633
1-2 1-10 1-634
1-3 1-11 1-635
1-4 1-12 1-636
1-5 1-13 1-637
1-6 1-14 1-638
1-7 1-15 1-639
1-8 1-16 1-640
Line 2 Line 3 Line 1 Line 2Line 4 Line 479 Line 480
HDP HNDP
∗Diagram drawn with 2 FPLINE vertical blank period
Example tim in g for a 640 × 480 panel
For this timing diagram FPSMASK (D2/0x39FFE1) is set to "1"
VDP = Vertical Display Period = LDVSIZE[9:0] + 1 (lines)
LDVSIZE[9:0] (0x39FFE5, D[1:0]/0x39FFE6)
VNDP = Vertical Non-Dis play Period = VNDP[5:0] (lines)
VNDP[5:0] (D[5:0]/0x39FFEA)
HDP = Horizontal Display Period = (L DHS I ZE[5:0] + 1) × 16 (Ts)
LDHSIZE[5:0] (D[5:0]/0x39FFE4)
HNDP = Horizontal Non-Display Period = (HNDP [4: 0] + 4) × 8 (Ts)
HNDP[4:0] (D[4:0]/0x39FFE7)
8 ELECTRICAL CHARACTE RISTICS
A-100 EPSON S1C33L03 P RODUCT PART
Frame Pulse
Line Pulse
DRDY (MOD)
Sync Timing
21
t2t1
t5
t6t8t9
t7t14 t11 t10
t12 t13
t4t3
Line Pulse
Shift Pulse
FPDAT[7:0]
Data Timing
Note:For this timing diagram FPSMASK (D2/0x39FFE1) is set to "1".
8-bit Singl e Mon ochrom e Panel AC Timing
Symbol Parameter Min. Typ. Max. Unit
t1Frame Pulse setup to Line Pulse falling edge note 2 (note 1)
t2Frame Pulse hold from Line Pulse falling edge 9 Ts
t3Line P ul se period note 3
t4Line P ul se widt h 9 Ts
t5MOD delay from Line Pulse rising edge 1 Ts
t6Shift Pulse falling edge to Line Pulse rising edge note 4
t7Shift Pulse falling edge to Line Pulse falling edge note 5
t8Line Pulse falling edge to Shift Pulse falling edge t14+4 Ts
t9Shift Pulse period 8 Ts
t10 Shift Pulse width low 4 Ts
t11 Shift Pulse width high 4 Ts
t12 FPDAT[7:0] setup to Shift Pulse falling edge 4 Ts
t13 FPDAT[7:0] hold from Shift Pulse falling edge 4 Ts
t14 Line Pulse falling edge to Shift Pulse rising edge 23 Ts
note) 1.Ts = pixel clock period
2.t1min = t3min - 9 (Ts)
3.t3min = (LDHSIZE[5:0] + 1) × 16 + (HNDP[4:0] + 4) × 8 (Ts)
4.t6min = HNDP[4:0] × 8 + 4 (Ts)
5.t7min = HNDP[4:0] × 8 + 13 (Ts)
8 ELECTRICAL CHARACTE RISTICS
S1C33L03 PRODUCT PART EPSON A-101
A-1
A-8
4-bit single color panel timing
FPFRAME
FPLINE
DRDY (MOD)
FPDAT[7:4]
VDP VNDP
FPLINE
DRDY (MOD)
FPSHIFT
FPDAT7
FPDAT6
FPDAT5
FPDAT4
Line 1
1-R1 1-G2
1-B319
1-G1 1-B2
1-R320
1-B1 1-R3
1-G320
1-R2 1-G3
1-B3
1-R4
1-G4
1-B4
1-B320
Line 2 Line 3 Line 1 Line 2Line 4 Line 239 Line 240
HDP HNDP
∗Diagram drawn with 2 FPLINE vertical blank period
Example tim in g for a 320 × 240 panel
VDP = Vertical Display Period = LDVSIZE[9:0] + 1 (lines)
LDVSIZE[9:0] (0x39FFE5, D[1:0]/0x39FFE6)
VNDP = Vertical Non-Dis play Period = VNDP[5:0] (lines)
VNDP[5:0] (D[5:0]/0x39FFEA)
HDP = Horizontal Display Period = (L DHS I ZE[5:0] + 1) × 16 (Ts)
LDHSIZE[5:0] (D[5:0]/0x39FFE4)
HNDP = Horizontal Non-Display Period = (HNDP [4: 0] + 4) × 8 (Ts)
HNDP[4:0] (D[4:0]/0x39FFE7)
8 ELECTRICAL CHARACTE RISTICS
A-102 EPSON S1C33L03 P RODUCT PART
Frame Pulse
Line Pulse
DRDY (MOD)
Sync Timing
21
t2t1
t5
t6t8t9
t7t14 t11 t10
t12 t13
t4t3
Line Pulse
Shift Pulse
FPDAT[7:4]
Data Timing
4-bit Singl e Color Panel AC Timing
Symbol Parameter Min. Typ. Max. Unit
t1Frame Pulse setup to Line Pulse falling edge note 2 (note 1)
t2Frame Pulse hold from Line Pulse falling edge 9 Ts
t3Line P ul se period note 3
t4Line P ul se widt h 9 Ts
t5MOD delay from Line Pulse rising edge 1 Ts
t6Shift Pulse falling edge to Line Pulse rising edge note 4
t7Shift Pulse falling edge to Line Pulse falling edge note 5
t8Line Pulse falling edge to Shift Pulse falling edge t14+0.5 Ts
t9Shift Pulse period 1 Ts
t10 Shift Pulse width low 0.5 Ts
t11 Shift Pulse width high 0.5 Ts
t12 FPDAT[7:4] setup to Shift Pulse falling edge 1.5 Ts
t13 FPDAT[7:4] hold from Shift Pulse falling edge 1.5 Ts
t14 Line Pulse falling edge to Shift Pulse rising edge 24 Ts
note) 1.Ts = pixel clock period
2.t1min = t3min - 9 (Ts)
3.t3min = (LDHSIZE[5:0] + 1) × 16 + (HNDP[4:0] + 4) × 8 (Ts)
4.t6min = HNDP[4:0] × 8 + 1.5 (Ts)
5.t7min = HNDP[4:0] × 8 + 10.5 (Ts)
8 ELECTRICAL CHARACTE RISTICS
S1C33L03 PRODUCT PART EPSON A-103
A-1
A-8
8-bit single color p a nel timing (Format 1)
FPFRAME
FPLINE
FPDAT[7:0]
VDP VNDP
FPLINE
FPSHIFT
FPSHIFT2
FPDAT7
FPDAT6
FPDAT5
FPDAT4
FPDAT3
FPDAT2
FPDAT1
FPDAT0
Line 1
1-R1 1-G1
1-R636
1-B1 1-R2
1-B636
1-G2 1-B2
1-G637
1-R3 1-G3
1-R638
1-B3 1-R4
1-B638
1-G4 1-B4
1-G639
1-R5 1-G5
1-R640
1-B5 1-R6
1-B640
1-G6
1-R7
1-B7
1-G8
1-R9
1-B9
1-G10
1-R11
1-B6
1-G7
1-R8
1-B8
1-G9
1-R10
1-B10
1-G11
1-B11
1-G12
1-R13
1-B13
1-G14
1-R15
1-B15
1-G16
1-R12
1-B12
1-G13
1-R14
1-B14
1-G15
1-R16
1-B16
Line 2 Line 3 Line 1 Line 2Line 4 Line 479 Line 480
HDP HNDP
∗Diagram drawn with 2 FPLINE vertical blank period
Example tim in g for a 640 × 480 panel
VDP = Vertical Display Period = LDVSIZE[9:0] + 1 (lines)
LDVSIZE[9:0] (0x39FFE5, D[1:0]/0x39FFE6)
VNDP = Vertical Non-Dis play Period = VNDP[5:0] (lines)
VNDP[5:0] (D[5:0]/0x39FFEA)
HDP = Horizontal Display Period = (L DHS I ZE[5:0] + 1) × 16 (Ts)
LDHSIZE[5:0] (D[5:0]/0x39FFE4)
HNDP = Horizontal Non-Display Period = (HNDP [4: 0] + 4) × 8 (Ts)
HNDP[4:0] (D[4:0]/0x39FFE7)
8 ELECTRICAL CHARACTE RISTICS
A-104 EPSON S1C33L03 P RODUCT PART
Frame Pulse
Line Pulse
Sync Timing t
2
t
1
t
6b
t
6a
t
8
t
9
t
7a
t
7b
t
14
t
11
t
10
t
12
t
13
t
12
t
13
t
4
t
3
Line Pulse
Shift Pulse 2
Shift Pulse
FPDAT[7:0]
Data Timing
1 2
8-bit Singl e Color Panel AC Timing (Format 1)
Symbol Parameter Min. Typ. Max. Unit
t1Frame Pulse setup to Line Pulse falling edge note 2 (note 1)
t2Frame Pulse hold from Line Pulse falling edge 9 Ts
t3Line P ul se period note 3
t4Line P ul se widt h 9 Ts
t6a Shift Pulse falling edge to Line Pulse rising edge note 4
t6b Shift Pulse 2 falling edge to Line Pulse rising edge note 5
t7a Shift Pulse 2 falling edge to Line Pulse falling edge note 6
t7b Shift Pulse falling edge to Line Pulse falling edge note 7
t8Line Pulse falling edge to Shift Pulse rising, Shift Pulse 2 falling edge t14+2 Ts
t9Shift Pulse 2, Shift Pulse period 4 Ts
t10 Shift Pulse 2, Shift Pulse width low 2 Ts
t11 Shift Pulse 2, Shift Pulse width high 2 Ts
t12 FPDAT[7:0] setup to Shift Pulse 2, Shift Pulse falling edge 1 Ts
t13 FPDAT[7:0] hold from Shift Pulse 2, Shift Pulse falling edge 1 Ts
t14 Line Pulse falling edge to Shift Pulse 2 rising edge 23 Ts
note) 1.Ts = pixel clock period
2.t1min = t3min - 9 (Ts)
3.t3min = (LDHSIZE[5:0] + 1) × 16 + (HNDP[4:0] + 4) × 8 + 1 (Ts)
4.t6amin = HNDP[4:0] × 8 + t13 - t10 + 1 (Ts)
5.t6bmin = HNDP[4:0] × 8 + t13 + 1 (Ts)
6.t7amin = HNDP[4:0] × 8 + 11 (Ts)
7.t7bmin = HNDP[4:0] × 8 + 11 - t10 (Ts)
8 ELECTRICAL CHARACTE RISTICS
S1C33L03 PRODUCT PART EPSON A-105
A-1
A-8
8-bit single color p a nel timing (Format 2)
FPFRAME
FPLINE
DRDY (MOD)
FPDAT[7:0]
VDP VNDP
FPLINE
DRDY (MOD)
FPSHIFT
FPDAT7
FPDAT6
FPDAT5
FPDAT4
FPDAT3
FPDAT2
FPDAT1
FPDAT0
Line 1
1-R1 1-B3
1-G638
1-G1 1-R4
1-B638
1-B1 1-G4
1-R639
1-R2 1-B4
1-G639
1-G2 1-R5
1-B639
1-B2 1-G5
1-R640
1-R3 1-B5
1-G640
1-G3 1-R6
1-G6
1-B6
1-R7
1-G7
1-B7
1-R8
1-G8
1-B8
1-B640
Line 2 Line 3 Line 1 Line 2Line 4 Line 479 Line 480
HDP HNDP
∗Diagram drawn with 2 FPLINE vertical blank period
Example tim in g for a 640 × 480 panel
VDP = Vertical Display Period = LDVSIZE[9:0] + 1 (lines)
LDVSIZE[9:0] (0x39FFE5, D[1:0]/0x39FFE6)
VNDP = Vertical Non-Dis play Period = VNDP[5:0] (lines)
VNDP[5:0] (D[5:0]/0x39FFEA)
HDP = Horizontal Display Period = (L DHS I ZE[5:0] + 1) × 16 (Ts)
LDHSIZE[5:0] (D[5:0]/0x39FFE4)
HNDP = Horizontal Non-Display Period = (HNDP [4: 0] + 4) × 8 (Ts)
HNDP[4:0] (D[4:0]/0x39FFE7)
8 ELECTRICAL CHARACTE RISTICS
A-106 EPSON S1C33L03 P RODUCT PART
Frame Pulse
Line Pulse
DRDY (MOD)
Sync Timing
21
t2t1
t5
t6t8t9
t7t14 t11 t10
t12 t13
t4t3
Line Pulse
Shift Pulse
FPDAT[7:0]
Data Timing
8-bit Singl e Color Panel AC Timing (Format 2)
Symbol Parameter Min. Typ. Max. Unit
t1Frame Pulse setup to Line Pulse falling edge note 2 (note 1)
t2Frame Pulse hold from Line Pulse falling edge 9 Ts
t3Line P ul se period note 3
t4Line P ul se widt h 9 Ts
t5MOD delay from Line Pulse rising edge 1 Ts
t6Shift Pulse falling edge to Line Pulse rising edge note 4
t7Shift Pulse falling edge to Line Pulse falling edge note 5
t8Line Pulse falling edge to Shift Pulse falling edge t14+2 Ts
t9Shift Pulse period 2 Ts
t10 Shift Pulse width low 1 Ts
t11 Shift Pulse width high 1 Ts
t12 FPDAT[7:0] setup to Shift Pulse falling edge 1 Ts
t13 FPDAT[7:0] hold from Shift Pulse falling edge 1 Ts
t14 Line Pulse falling edge to Shift Pulse rising edge 23 Ts
note) 1.Ts = pixel clock period
2.t1min = t3min - 9 (Ts)
3.t3min = (LDHSIZE[5:0] + 1) × 16 + (HNDP[4:0] + 4) × 8 + 1 (Ts)
4.t6min = HNDP[4:0] × 8 + 1 (Ts)
5.t7min = HNDP[4:0] × 8 + 10 (Ts)
8 ELECTRICAL CHARACTE RISTICS
S1C33L03 PRODUCT PART EPSON A-107
A-1
A-8
8.7 Oscillation Characteristics
Oscillation characteristics change depending on conditions (board pattern, components used, etc.). Use the
following characteristics as reference values. In particular, when a ceramic or crystal oscillator is used, use the
oscillator manufacturer recommended values for constants such as capacitance and resistance.
OSC1 crystal oscillation
(Unless otherwise specified: crystal=Q11C02RX#1 32.768kHz, Rf1=20MΩ, CG1=CD1=15pF#2)
Item Symbol Condition Min. Typ. Max. Unit ∗
Operating temperature Ta VDD=2.7V to 3.6V -40 85 °C
VDD=1.9V to 2.2V -40 85 °C
VDD=1.8V to 2.2V 0 70 °C
#1 Q11C02RX: Crystal resonator made by Seiko Epson
#2 "CG1=CD1=15pF" includes board capacitance.
(Unless otherwise specified: VDD=3.3V, VSS=0V, crystal=Q11C02RX#1 32.768kHz,
Rf1=20MΩ, CG1=CD1=15pF#2, Ta=25°C)
Item Symbol Condition Min. Typ. Max. Unit ∗
Oscillation start time tSTA1 3s
External gate/drain capacitance CG1, CD1 CG1=CD1,
including board capacitance 525pF
Frequency/IC deviation ∆f/∆IC -10 10 ppm
Frequency/power voltage deviation ∆f/∆V-1010 ppm/V
Frequency adjustment range ∆f/∆CGCG1=CD1= 5 to 25pF 50 ppm
#1 Q11C02RX: Crystal resonator made by Seiko Epson
#2 "CG1=CD1=15pF" includes board capacitance.
(Unless otherwise specified: VDD=2.0V, VSS=0V, crystal=Q11C02RX#1 32.768kHz,
Rf1=20MΩ, CG1=CD1=15pF#2, Ta=25°C)
Item Symbol Condition Min. Typ. Max. Unit ∗
Oscillation start time tSTA1 20 s
External gate/drain capacitance CG1, CD1 CG1=CD1,
including board capacitance 525pF
Frequency/IC deviation ∆f/∆IC -10 10 ppm
Frequency/power voltage deviation ∆f/∆V-1010 ppm/V
Frequency adjustment range ∆f/∆CGCG1=CD1= 5 to 25pF 50 ppm
#1 Q11C02RX: Crystal resonator made by Seiko Epson
#2 "CG1=CD1=15pF" includes board capacitance.
OSC3 crystal oscillation
Note:A "crystal resonator that uses a fundam ental" should be used fo r th e OSC 3 cryst al oscilla tio n
circuit.
(Unless otherwise specified: VSS=0V, crystal=Q22MA306#1 33.8688MHz,
Rf2=1MΩ, CG1=CD1=15pF#2, Ta=25°C)
Item Symbol Condition Min. Typ. Max. Unit ∗
Oscillation start time tSTA3 VDD=3.3V 10 ms
VDD=2.0V 25 ms
#1 Q22MA306: Crystal resonator made by Seiko Epson
#2 "CG1=CD1=15pF" includes board capacitance.
8 ELECTRICAL CHARACTE RISTICS
A-108 EPSON S1C33L03 P RODUCT PART
OSC3 ceramic osci llation (Unless otherwise specified: VSS=0V, Ta=25°C)
Item Symbol Condition Min. Typ. Max. Unit ∗
Oscillation start time tSTA3 10MH z c e ram i c os ci llat or 10 ms 1
16 MHz c e ram i c os ci llat or 10 ms 2
20 MHz c e ram i c os ci llat or 10 ms 3
25 MHz c e ramic oscillator 5 ms 4
33 MHz c e ram i c os ci llator 5 ms 5
∗ note) No. Ceramic Recommended constants Power voltage Remarks
oscillator CG2 (pF) CD2 (pF) Rf2 (MΩ)range (V) (Manufac t urer )
1CST10.0MTW 30 3011.8 to 2.2 (Murata Mfg. corporation) ∗1
2CST16.00MXW0C1 5 5 1 1.8 to 2.2 (Murata Mfg. corporation)
3CST20.00MXW0H1 5 5 1 1.8 to 2.2 (Murata Mfg. corporation)
4CST25.00MXW0H1 5 5 1 2.7 to 3.6 (Murata Mfg. corporation)
5CST33.00MXZ040 Open Open 1 2.7 to 3.6 (Murata Mfg. corporation)
∗1This oscillator has a tendency to rise to the frequency of 0.3%.
8.8 PLL Characteristics
Setting the PLLS0 and PLLS 1 pins (recommended operating condition)
VDD=2.7V to 3.6V
PLLS1 PLLS0 Mode Fin (OSC3 clock) Fout
11x210 to 25MHz 20 to 50MHz
01x410 to 12.5MHz 40 to 50MHz
00PLL not used – –
VDD=2.0V±0.2V
PLLS1 PLLS0 Mode Fin (OSC3 clock) Fout
11x210MHz20MHz
00PLL not used – –
PLL characteristics (Unless otherwise specified: VDD=2.7V to 3.6V, VSS=0V, crystal oscillator=Q3204DC#1,
R1=4.7kΩ, C1=100pF, C2=5pF, Ta=-40°C to +85°C)
Item Symbol Condition Min. Typ. Max. Unit ∗
Jitter (peak jitter) tpj -1 1 ns
Lo ck up tim e tpll 1 ms
#1 Q3204DC: Crystal oscillator made by Seiko Epson
(Unless otherwise specified: VDD=2.0V±0.2V, VSS=0V, crystal oscillator=Q3204DC#1,
R1=4.7kΩ, C1=100pF, C2=5pF, Ta=-40°C to +85°C)
Item Symbol Condition Min. Typ. Max. Unit ∗
Jitter (peak jitter) tpj -2 2 ns
Lo ck up tim e tpll 2 ms
#1 Q3204DC: Crystal oscillator made by Seiko Epson
9 PACKAGE
S1C33L03 PRODUCT PART EPSON A-109
A-1
A-9
9 Package
9.1 Plastic Package
QFP20-144pin (Unit: mm )
20±0.1
22±0.4
73108
20±0.1
22±0.4
37
72
INDEX
0.2
361
144
109
1.4±0.1
0.1
1.7
max
1
0.5±0.2
0°
10°
0.125
0.5 +0.1
–0.05
+0.05
–0.025
Limit of power consumption
The chip temperature of an LSI rises according to power consumption. The chip temperature can be
calculated from environment temperature (Ta), thermal package resistance (θ) and power consumption (PD).
Chip temperature (Tj) = Ta + (PD × θ) (°C )
As a guide, normally keep the chip temperature (Tj) lower than 85°C.
The the rmal resistance of the QFP20-144pin package is as follows:
Therma l resistance (°C/W) = 11 0 to 120°C (90 to 100°C for Cu lead frame)
This thermal resistance is a value under the condition that the measured device is hanging in the air and has
no air-coo ling. Therma l resistance greatly varies according to the mounting condition on the board and air-
cooling condition.
10 PAD LAYOU T
A-110 EPSON S1C33L03 P RODUCT PART
10 Pa d Layout
10.1 Pad Layout Diagram
X
Y
(0, 0)
15 10 15 20 25 30 35 40
120 115 110 105 100 95 90 85
45
50
55
60
65
70
75
80
160
155
150
145
140
135
130
125
5.97 mm
5.38 mm
Die No.
10 PAD LAYOU T
S1C33L03 PRODUCT PART EPSON A-111
A-1
A-10
10.2 Pad Coordinate
(Unit: µm)
No. Pad name X Y No. Pad name X Y
1P22/TM0 -2310.0 -2549.5 51 #RD 2843.5 -1210.0
2N.C. -2200.0 -2549.5 52 VSS 2843.5 -1100.0
3P23/TM1 -2090.0 -2549.5 53 D15 2843.5 -990.0
4N.C. -1980.0 -2549.5 54 D14 2843.5 -880.0
5VSS -1870.0 -2549.5 55 D13 2843.5 -770.0
6N.C. -1760.0 -2549.5 56 D12 2843.5 -660.0
7P24/TM2/#SRDY2 -1650.0 -2549.5 57 D11 2843.5 -550.0
8N.C. -1540.0 -2549.5 58 VDD 2843.5 -440.0
9P25/TM3/#SCLK2 -1430.0 -2549.5 59 D10 2843.5 -330.0
10 P26/TM4/SOUT2 -1320.0 -2549.5 60 D9 2843.5 -220.0
11 P27/TM5/SIN2 -1210.0 -2549.5 61 D8 2843.5 -110.0
12 VDD -1100.0 -2549.5 62 D7 2843.5 0.0
13 P07/#SRDY1/#DMAEND3 -990.0 -2549.5 63 D6 2843.5 110.0
14 P06/#SCLK1/#DMAACK3 -880.0 -2549.5 64 D5 2843.5 220.0
15 P05/SOUT1/#DMAEND2 -770.0 -2549.5 65 D4 2843.5 330.0
16 P04/SIN1/#DMAACK2 -660.0 -2549.5 66 VDDE 2843.5 440.0
17 FPDAT7 -550.0 -2549.5 67 D3 2843.5 550.0
18 FPDAT6 -440.0 -2549.5 68 D2 2843.5 660.0
19 FPDAT5 -330.0 -2549.5 69 D1 2843.5 770.0
20 FPDAT4 -220.0 -2549.5 70 D0 2843.5 880.0
21 FPDAT3/GPO6 -110.0 -2549.5 71 #CE8/#RAS1/#CE14/#RAS3/#SDCE1 2843.5 990.0
22 FPDAT2/GPO5 0.0 -2549.5 72 #CE7/#RAS0/#CE13/#RAS2/#SDCE0 2843.5 1100.0
23 FPDAT1/GPO4 110.0 -2549.5 73 VSS 2843.5 1210.0
24 FPDAT0/GPO3 220.0 -2549.5 74 OSC2 2843.5 1320.0
25 VDDE 330.0 -2549.5 75 OSC1 2843.5 1430.0
26 DRDY(MOD/FPSHIFT2) 440.0 -2549.5 76 #RESET 2843.5 1540.0
27 FPFRAME 550.0 -2549.5 77 P35/#BUSACK/GPIO1 2843.5 1650.0
28 FPLINE 660.0 -2549.5 78 N.C. 2843.5 1760.0
29 FPSHIFT 770.0 -2549.5 79 P34/#BUSREQ/#CE6/GPIO0 2843.5 1870.0
30 N.C. 880.0 -2549.5 80 P33/#DMAACK1/SIN3/SDA10 2843.5 1980.0
31 LCDPWR 990.0 -2549.5 81 P32/#DMAACK0/#SRDY3/HDQM 2310.0 2549.5
32 N.C. 1100.0 -2549.5 82 N.C. 2200.0 2549.5
33 VSS 1210.0 -2549.5 83 P31/#BUSGET/#GARD/GPIO2 2090.0 2549.5
34 K67/AD7 1320.0 -2549.5 84 N.C. 1980.0 2549.5
35 K66/AD6 1430.0 -2549.5 85 P30/#WAIT/#CE4&5 1870.0 2549.5
36 K65/AD5 1540.0 -2549.5 86 N.C. 1760.0 2549.5
37 K64/AD4 1650.0 -2549.5 87 #LCAS/#SDRAS 1650.0 2549.5
38 K63/AD3 1760.0 -2549.5 88 N.C. 1540.0 2549.5
39 K62/AD2 1870.0 -2549.5 89 #HCAS/#SDCAS 1430.0 2549.5
40 N.C. 1980.0 -2549.5 90 VDD 1320.0 2549.5
41 K61/AD1 2090.0 -2549.5 91 P21/#DWE/#GAAS/#SDWE 1210.0 2549.5
42 K60/AD0 2200.0 -2549.5 92 P20/#DRD/SDCKE 1100.0 2549.5
43 AVDDE 2310.0 -2549.5 93 BCLK/SDCLK 990.0 2549.5
44 K54/#DMAREQ3 2843.5 -1980.0 94 VSS 880.0 2549.5
45 K53/#DMAREQ2 2843.5 -1870.0 95 P16/EXCL5/#DMAEND1/SOUT3 770.0 2549.5
46 K52/#ADTRG 2843.5 -1760.0 96 P15/EXCL4/#DMAEND0/#SCLK3/LDQM 660.0 2549.5
47 K51/#DMAREQ1 2843.5 -1650.0 97 A0/#BSL 550.0 2549.5
48 K50/#DMAREQ0 2843.5 -1540.0 98 A1/SDA0 440.0 2549.5
49 #WRH/#BSH 2843.5 -1430.0 99 A2/SDA1 330.0 2549.5
50 #WRL/#WR/#WE 2843.5 -1320.0 100 A3/SDA2 220.0 2549.5
10 PAD LAYOU T
A-112 EPSON S1C33L03 P RODUCT PART
No. Pad name X Y No. Pad name X Y
101 A4/SDA3 110.0 2549.5 131 VSS -2843.5 1210.0
102 A5/SDA4 0.0 2549.5 132 DSIO -2843.5 1100.0
103 VDDE -110.0 2549.5 133 P14/FOSC1/DCLK -2843.5 990.0
104 A6/SDA5 -220.0 2549.5 134 P13/EXCL3/T8UF3/DPCO -2843.5 880.0
105 A7/SDA6 -330.0 2549.5 135 P12/EXCL2/T8UF2/DST2 -2843.5 770.0
106 A8/SDA7 -440.0 2549.5 136 P11/EXCL1/T8UF1/DST1 -2843.5 660.0
107 A9/SDA8 -550.0 2549.5 137 P10/EXCL0/T8UF0/DST0 -2843.5 550.0
108 A10/SDA9 -660.0 2549.5 138 EA10MD1 -2843.5 440.0
109 A11 -770.0 2549.5 139 EA10MD0 -2843.5 330.0
110 VSS -880.0 2549.5 140 ICEMD -2843.5 220.0
111 A12/SDA11 -990.0 2549.5 141 #EMEMRD -2843.5 110.0
112 A13/SDA12 -1100.0 2549.5 142 VDD -2843.5 0.0
113 A14/SDBA0 -1210.0 2549.5 143 OSC4 -2843.5 -110.0
114 A15/SDBA1 -1320.0 2549.5 144 OSC3 -2843.5 -220.0
115 A16 -1430.0 2549.5 145 #NMI -2843.5 -330.0
116 A17 -1540.0 2549.5 146 #CE9/#CE17/#CE17&18 -2843.5 -440.0
117 VSS -1650.0 2549.5 147 VDDE -2843.5 -550.0
118 N.C. -1760.0 2549.5 148 #CE5/#CE15/#CE15&16 -2843.5 -660.0
119 A18 -1870.0 2549.5 149 N.C. -2843.5 -770.0
120 N.C. -1980.0 2549.5 150 #CE3 -2843.5 -880.0
121 A19 -2090.0 2549.5 151 VSS -2843.5 -990.0
122 N.C. -2200.0 2549.5 152 #CE10EX/#CE9&10EX -2843.5 -1100.0
123 A20 -2310.0 2549.5 153 #CE6/#CE7&8 -2843.5 -1210.0
124 A21 -2843.5 1980.0 154 #CE4/#CE11/#CE11&12 -2843.5 -1320.0
125 A22 -2843.5 1870.0 155 #X2SPD -2843.5 -1430.0
126 A23 -2843.5 1760.0 156 P03/#SRDY0 -2843.5 -1540.0
127 PLLS1 -2843.5 1650.0 157 P02/#SCLK0 -2843.5 -1650.0
128 PLLS0 -2843.5 1540.0 158 N.C. -2843.5 -1760.0
129 VSS -2843.5 1430.0 159 P01/SOUT0 -2843.5 -1870.0
130 PLLC -2843.5 1320.0 160 P00/SIN0 -2843.5 -1980.0
APPENDIX A <REFERENCE> E X TERNAL DEVICE INTERFACE TIMINGS
S1C33L03 PRODUCT PART EPSON A-113
A-1
A-ap
Appendix A <Reference> Extern al D evice Interface Timi ngs
This section shows setup examples for setting timing conditions of the external system interface as a reference
material used when configuring a system with external devices.
Pay attention to t he following precautions when using this material.
•The described A C cha racteristic values of external devices are standard values. They may differ from those of the
devices actually used, so the actual setup values (number of cycles) should be determined by referring the manual
or specification of the device to be used.
•It is necessary to set the timing values allowing ample margin according to the load capacitance of the bus and
signal lines, number of devices to be connected, operating temperature range, I/O levels and other conditions. The
number of cycles descri bed in this section is an exam p le an d th e cond itions are not co ns idered.
•The values described in "Time" column of the tables are simply calculated by multiplying the number of cycles
by the cycle time. Conditions such as the output delay time of the device, delay due to wiring and load
capacitance, and input setup time are not considered.
•The described con tents are reference data and cannot be guaranteed to work.
APPENDIX A <REFERENCE> E X TERNAL DEVICE INTERFACE TIMINGS
A-114 EPSON S1C33L03 P RODUCT PART
A.1 DRAM (70ns)
DRAM interface setup exampl es – 70n s
Operating
frequency RAS precharge
cycle RAS cycle CAS cycle Refresh RAS pulse
width Refresh RPC delay
20MHz 2 1221
25MHz 2 1221
33MHz 2 2331
DRAM interface timing – 70n s
DRAM interface Unit: ns 33MHz 25MHz 20MHz
Parameter Symbol Min. Max. Cycle Time Cycle Time Cycle Time
<Common parameters>
Random read/random write cycle time tRC 130 – 7 21052005250
#RAS precharge time tRP 50 – 2 60 2 80 2 100
#RAS pulse width tRAS 70 10000 5 15031203150
#CAS pulse width tCAS 20 10000 2.5 75 1.5 60 1.5 75
Row address setup time tASR 0–0.5150.520 0.5 25
Row address hold time tRAH 10 – 1.5 45 0.5 20 0.5 25
Column address setup time tASC 0–0.5150.520 0.5 25
#RAS→#CAS delay time tRCD 20 – 2.0 60 1.0 40 1.0 50
#RAS→column address delay time tRAD 15 – 1.5 45 0.5 20 0.5 25
<Rea d- cy cle pa ra meter s>
#RAS access time tRAC –704.51352.51002.5125
#CAS access time tCAC –202.575 1.5 60 1.5 75
Address access time tAA –353.0902.0 80 2.0 100
#OE access time tOAC –204.51352.51002.5125
Output buffer turn-off time tOFF 0202602802100
<Write-cycle parameters>
Data input hold time tDH 15 – 2.5 75 1.5 60 1.5 75
<Fast-page mode>
Fast-page mode cycle time tPC 45 – 3.0 90 2.0 80 2.0 100
Fast-page mode #CAS precharge time tCP 10 – 0.5 15 0.5 20 0.5 25
Access time after #CAS precharge tACP –403.0902.0 80 2.0 100
<Refresh cycle>
#CAS setup time tCSR 10 – 1.0 30 1.0 40 1.0 50
#CAS hold time tCHR 10 – 2.5 75 1.5 60 1.5 75
#RAS precharge→#CAS hold time tPPC 10 – 1.0 30 1.0 40 1.0 50
#RAS pulse width (only in refresh cycle) tRAS 70 10000 3.0 90 2.0 80 2.0 100
APPENDIX A <REFERENCE> E X TERNAL DEVICE INTERFACE TIMINGS
S1C33L03 PRODUCT PART EPSON A-115
A-1
A-ap
DRAM: 70ns, CPU: 33MHz, ra ndom read/write cycl e
2
RAS cycle CAS cycle RAS precharge
3
t
RC
t
RAD
t
RAH
t
RCD
t
RAC
t
OAC
t
AA
t
CAC
t
OFF
t
CAS
t
ASC
t
RAS
t
ASR
t
WP
t
RP
2
BCLK
A[11:0]
#RAS
#CAS
#RD
D[15:0](RD)
#WE
D[15:0](WR)
ROW #1
RD data
;;;;;;;;;
;;;;;;;;;
ROW #2
;;;;;;;;;
;;;;;;;;;
;;;;
;;;;
t
DH
t
DS
WR data
;;;
;;;
COL #1
DRAM : 70ns, CPU: 33MHz, p ag e-mode read/write cycle
2
RAS cycle CAS cycle RAS precharge
3CAS cycle
3
t
PC
t
ACP
t
CP
t
RAS
2
BCLK
A[11:0]
#RAS
#CAS
#RD
D[15:0](RD)
#WE
D[15:0](WR)
ROW #1
RD data
;;;;;;
;;;;;;
;;;;;;;;;
;;;;;;;;;
RD data
;;;;;;;;;
;;;;;;;;;
WR data
;;;
;;;
WR data
COL #1 COL #2
DRAM : 70ns, CPU: 33MH z, CAS-befo re-RAS refr esh cycle
1 1
RPC delay Fixed Refresh RAS pulse width
3RAS precharge
2
t
RPC
t
CSR
t
CHR
t
RAS
BCLK
#RAS
#CAS
APPENDIX A <REFERENCE> E X TERNAL DEVICE INTERFACE TIMINGS
A-116 EPSON S1C33L03 P RODUCT PART
DRAM: 70ns, CPU: 25/20MHz, random read/write cycle
1
RAS cycle CAS cycle RAS precharge
2
t
RAS
2
BCLK
A[11:0]
#RAS
#CAS
#RD
D[15:0](RD)
#WE
D[15:0](WR)
ROW #1
RD data
;;;;;;;;;
;;;;;;;;;
ROW #2
;;;;;
;;;;;
;;
;;
WR data
;;;
;;;
COL #1
DRAM : 70ns, CPU : 25/20MH z, pa ge-mode read/write cycle
1
RAS cycle CAS cycle RAS precharge
2
CAS cycle
2 2
tRAS
BCLK
A[11:0]
#RAS
#CAS
#RD
D[15:0](RD)
#WE
D[15:0](WR)
ROW #1
RD data
;;;;;;;;;
;;;;;;;;;
;;;;;
;;;;;
RD data
;;;;;
;;;;;
WR data
;;;
;;;
WR data
COL #1 COL #2
DRAM : 70ns, CPU: 25/20MHz, CA S-before-RAS refr esh cycle
1 1
RPC delay Fixed Refresh RAS pulse width
2RAS precharge
2
tRPC tCSR tCHR
tRAS
BCLK
#RAS
#CAS
APPENDIX A <REFERENCE> E X TERNAL DEVICE INTERFACE TIMINGS
S1C33L03 PRODUCT PART EPSON A-117
A-1
A-ap
A.2 DRAM (60ns)
DRAM interface setup exampl es – 60n s
Operating
frequency RAS precharge
cycle RAS cycle CAS cycle Refresh RAS pulse
width Refresh RPC delay
20MHz 1 1 221
25MHz 2 1 221
33MHz 2 2 231
DRAM interface timing – 60n s
DRAM interface Unit: ns 33MHz 25MHz 20MHz
Parameter Symbol Min. Max. Cycle Time Cycle Time Cycle Time
<Common parameters>
Random read/random write cycle time tRC 110 – 6 18052004200
#RAS precharge time tRP 40 – 2 60 2 80 1 50
#RAS pulse width tRAS 60 10000 4 12031203150
#CAS pulse width tCAS 15 10000 1.5 45 1.5 60 1.5 75
Row address setup time tASR 0–0.5150.520 0.5 25
Row address hold time tRAH 10 – 1.5 45 0.5 20 0.5 25
Column address setup time tASC 0–0.5150.520 0.5 25
#RAS→#CAS delay time tRCD 20 – 2.0 60 1.0 40 1.0 50
#RAS→column address delay time tRAD 15 – 1.5 45 0.5 20 0.5 25
<Rea d- cy cle pa ra meter s>
#RAS access time tRAC –603.51052.51002.5125
#CAS access time tCAC –151.545 1.5 60 1.5 75
Address access time tAA –302.0602.0 80 2.0 100
#OE access time tOAC –153.51052.51002.5125
Output buffer turn-off time tOFF 015260280150
<Write-cycle parameters>
Data input hold time tDH 10 – 1.5 45 1.5 60 1.5 75
<Fast-page mode>
Fast-page mode cycle time tPC 40 – 2.0 60 2.0 80 2.0 100
Fast-page mode #CAS precharge time tCP 10 – 0.5 15 0.5 20 0.5 25
Access time after #CAS precharge tACP –352.0602.0 80 2.0 100
<Refresh cycle>
#CAS setup time tCSR 10 – 1.0 30 1.0 40 1.0 50
#CAS hold time tCHR 10 – 2.5 75 1.5 60 1.5 75
#RAS precharge→#CAS hold time tPPC 10 – 1.0 30 1.0 40 1.0 50
#RAS pulse width (only in refresh cycle) tRAS 60 10000 3.0 90 2.0 80 2.0 100
APPENDIX A <REFERENCE> E X TERNAL DEVICE INTERFACE TIMINGS
A-118 EPSON S1C33L03 P RODUCT PART
DRAM: 60ns, CPU: 33MHz, ra ndom read/write cycl e
2
RAS cycle CAS cycle RAS precharge
2
t
RC
t
RAD
t
RAH
t
RCD
t
RAC
t
OAC
t
AA
t
CAC
t
OFF
t
CAS
t
ASC
t
RAS
t
ASR
t
WP
t
RP
2
BCLK
A[11:0]
#RAS
#CAS
#RD
D[15:0](RD)
#WE
D[15:0](WR)
ROW #1
RD data
;;;;;;;;;
;;;;;;;;;
ROW #2
;;;;;
;;;;;
;;;;
;;;;
t
DH
t
DS
WR data
;;;
;;;
COL #1
DRAM : 60ns, CPU: 33MHz, p ag e-mode read/write cycle
2
RAS cycle CAS cycle RAS precharge
2CAS cycle
2
t
PC
t
ACP
t
CP
t
RAS
2
BCLK
A[11:0]
#RAS
#CAS
#RD
D[15:0](RD)
#WE
D[15:0](WR)
ROW #1
RD data
;;;;;;
;;;;;;
;;;;;
;;;;;
RD data
;;;;;
;;;;;
WR data
;;;
;;;
WR data
COL #1 COL #2
DRAM : 60ns, CPU: 33MH z, CAS-befo re-RAS refr esh cycle
1 1
RPC delay Fixed Refresh RAS pulse width
3RAS precharge
2
t
RPC
t
CSR
t
CHR
t
RAS
BCLK
#RAS
#CAS
APPENDIX A <REFERENCE> E X TERNAL DEVICE INTERFACE TIMINGS
S1C33L03 PRODUCT PART EPSON A-119
A-1
A-ap
DRAM: 60ns, CPU: 25MHz, ra ndom read/write cycl e
1
RAS cycle CAS cycle RAS precharge
2
t
RAS
2
BCLK
A[11:0]
#RAS
#CAS
#RD
D[15:0](RD)
#WE
D[15:0](WR)
ROW #1
RD data
;;;;;;;;;
;;;;;;;;;
ROW #2
;;;;;
;;;;;
;;
;;
WR data
;;;
;;;
COL #1
DRAM : 60ns, CPU: 25MHz, p ag e-mode read/write cycle
1
RAS cycle CAS cycle RAS precharge
2
CAS cycle
2 2
tRAS
BCLK
A[11:0]
#RAS
#CAS
#RD
D[15:0](RD)
#WE
D[15:0](WR)
ROW #1
RD data
;;;;;;;;;
;;;;;;;;;
;;;;;
;;;;;
RD data
;;;;;
;;;;;
WR data
;;;
;;;
WR data
COL #1 COL #2
DRAM : 60ns, CPU: 25MH z, CAS-befo re-RAS refr esh cycle
1 1
RPC delay Fixed Refresh RAS pulse width
2RAS precharge
2
tRPC tCSR tCHR
tRAS
BCLK
#RAS
#CAS
APPENDIX A <REFERENCE> E X TERNAL DEVICE INTERFACE TIMINGS
A-120 EPSON S1C33L03 P RODUCT PART
DRAM: 60ns, CPU: 20MHz, random read/write cycle
1
RAS cycle CAS cycle RAS precharge
2
tRAS
1
BCLK
A[11:0]
#RAS
#CAS
#RD
D[15:0](RD)
#WE
D[15:0](WR)
ROW #1
RD data
;;;;;
;;;;;
ROW #2
;;;;;
;;;;;
;;
;;
WR data
;;;
;;;
COL #1
DRAM : 60ns, CPU: 20MHz, p ag e-mode read/write cycle
1
RAS cycle CAS cycle RAS precharge
2CAS cycle
2 1
tRAS
BCLK
A[11:0]
#RAS
#CAS
#RD
D[15:0](RD)
#WE
D[15:0](WR)
ROW #1
RD data
;;;;;;
;;;;;;
;;;;;
;;;;;
RD data
;;;;;
;;;;;
WR data
;;;
;;;
WR data
COL #1 COL #2
DRAM : 60ns, CPU: 20MH z, CAS-befo re-RAS refr esh cycle
1 1
RPC delay Fixed Refresh RAS pulse width
2RAS precharge
1
tRPC tCSR tCHR
tRAS
BCLK
#RAS
#CAS
APPENDIX A <REFERENCE> E X TERNAL DEVICE INTERFACE TIMINGS
S1C33L03 PRODUCT PART EPSON A-121
A-1
A-ap
A.3 ROM and Burst ROM
Burs t ROM and mask ROM interface setup examples
Operating Normal read cycle Burst read cycle Output disable
frequency Wait cycle Read cycle Wait cycle Read cycle delay cycle
20MHz 2 3 1 2 1.5
25MHz 3 4 1 2 1.5
33MHz 4 5 2 3 1.5
Burs t ROM and m ask ROM interf ace timing
Burst ROM and mask ROM interface 33MHz 25MHz 20MHz
Parameter Symbol Min. Max. Cycle Time Cycle Time Cycle Time
Access time tACC –100515041603150
#CE output delay time tCE –100515041603150
#OE output delay time tOE –504.51353.51402.5125
Burst access time tBAC –503902802100
Output disable delay time tDF 0401.545 1.5 60 1.5 75
RO M: 100ns , CPU: 33MH z, n o rmal read
t
ACC
t
CE
t
OE
BCLK
A[23:0]
#CE9, 10
#RD
D[15:0]
RD data
;;;;;
;;;;;
;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;
;;;;
;;;;
t
DF
RO M: 100ns , CPU: 33MH z, b ur st read
Normal read cycle Burst read cycle
t
BAC
t
BAC
t
BAC
BCLK
A[23:0]
#CE9, 10
#RD
D[15:0] RD data
;;;
;;;
;;;;;;;;
;;;;;;;;
;;;
;;;
RD data
;;;;;
;;;;;
RD data
;;;;;
;;;;;
RD data
;;;;;
;;;;;
t
DF
APPENDIX A <REFERENCE> E X TERNAL DEVICE INTERFACE TIMINGS
A-122 EPSON S1C33L03 P RODUCT PART
RO M: 100ns , CPU: 25MH z, n o rmal read
BCLK
A[23:0]
#CE9, 10
#RD
D[15:0] RD data
;;;;;
;;;;;
;;;;;;;;;;;
;;;;;;;;;;;
;;;;
;;;;
RO M: 100ns , CPU: 25MH z, b ur st read
Normal read cycle Burst read cycle
BCLK
A[23:0]
#CE9, 10
#RD
D[15:0]
RD data
;;;
;;;
;;;;;;
;;;;;;
;;;
;;;
RD data
;;;
;;;
RD data
;;;
;;;
RD data
;;;
;;;
RO M: 100ns , CPU: 20MH z, n o rmal read
BCLK
A[23:0]
#CE9, 10
#RD
D[15:0] RD data
;;;;;
;;;;;
;;;;;;;
;;;;;;;
;;;;
;;;;
RO M: 100ns , CPU: 20MH z, b ur st read
Normal read cycle Burst read cycle
BCLK
A[23:0]
#CE9, 10
#RD
D[15:0] RD data
;;;
;;;
;;;;
;;;;
;;;
;;;
RD data
;;;
;;;
RD data
;;;
;;;
RD data
;;;
;;;
APPENDIX A <REFERENCE> E X TERNAL DEVICE INTERFACE TIMINGS
S1C33L03 PRODUCT PART EPSON A-123
A-1
A-ap
A.4 SRAM (55ns)
SRAM interface set up exampl es – 55n s
Operating Read cycle Output disable
frequency Wait cycle Read cycle Write cycle delay cycle
20MHz 1 2 2 1.5
25MHz 2 3 3 1.5
33MHz 2 3 3 1.5
SRAM interface timing – 55ns
SRAM interfa ce 33MHz 25MHz 20MHz
Parameter Symbol Min. Max. Cycle Time Cycle Time Cycle Time
<Read cycle>
Read cycle time tRC 55 – 3 90 3 1202100
Address access time tACC –5539031202100
#CE access time tACS –5539031202100
#OE access time tOE –302.5752.5 100 1.5 75
Output disable delay time tOHZ 0301.545 1.5 60 1.5 75
<Write cycle>
Write cycle time tWC 55 – 3 90 3 1202100
Address enable time tAW 50 – 2.5 75 2.5 100 1.5 75
Write pulse width tWP 45 – 2 60 2 80 1 50
Input data setup time tDW 30 – 2 60 2 80 1 50
Input data hold time tDH 0–0.5150.520 0.5 25
SRAM: 55ns , CPU: 33/25MHz, rea d cyc le
tRC
tACC
tACS
tOE
BCLK
A[23:0]
#CEx
#RD
D[15:0] RD data
;;;;;
;;;;;
;;;;;;;;;
;;;;;;;;;
;;;;
;;;;
tOHZ
SRAM: 55ns , CPU: 33/25 MH z, wri te cycle
tWC
tAW
tWP
tDW
BCLK
A[23:0]
#CEx
#WR
D[15:0] WR data
;;;;;
;;;;;
;;;
;;;
tDH
APPENDIX A <REFERENCE> E X TERNAL DEVICE INTERFACE TIMINGS
A-124 EPSON S1C33L03 P RODUCT PART
SRAM: 55ns , CPU: 20MHz, read cycle
BCLK
A[23:0]
#CEx
#RD
D[15:0]
RD data
;;;;;
;;;;;
;;;;;
;;;;;
;;;;
;;;;
SRAM: 55ns , CPU: 20MHz, write cycle
BCLK
A[23:0]
#CEx
#WR
D[15:0]
WR data
;;;;;
;;;;;
;;;
;;;
APPENDIX A <REFERENCE> E X TERNAL DEVICE INTERFACE TIMINGS
S1C33L03 PRODUCT PART EPSON A-125
A-1
A-ap
A.5 SRAM (70ns)
SRAM interface set up exampl es – 70n s
Operating Read cycle Output disable
frequency Wait cycle Read cycle Write cycle delay cycle
20MHz 2 3 3 1.5
25MHz 2 3 3 1.5
33MHz 3 4 4 1.5
SRAM interface timing – 70ns
SRAM interfa ce 33MHz 25MHz 20MHz
Parameter Symbol Min. Max. Cycle Time Cycle Time Cycle Time
<Read cycle>
Read cycle time tRC 70 – 4 120 3 1203150
Address access time tACC –70412031203150
#CE access time tACS –70412031203150
#OE access time tOE –403.51052.51002.5125
Output disable delay time tOHZ 0301.545 1.5 60 1.5 75
<Write cycle>
Write cycle time tWC 70 – 4 120 3 1203150
Address enable time tAW 60 – 3.5 105 2.5 100 2.5 125
Write pulse width tWP 55 – 3 90 2 80 2 100
Input data setup time tDW 30 – 3 90 2 80 2 100
Input data hold time tDH 0–0.5150.520 0.5 25
SRAM: 70ns , CPU: 33MHz, read cycle
t
RC
t
ACC
t
ACS
t
OE
BCLK
A[23:0]
#CEx
#RD
D[15:0] RD data
;;;;;
;;;;;
;;;;;;;;;;;;;
;;;;;;;;;;;;;
;;;;
;;;;
t
OHZ
SRAM: 70ns , CPU: 33MHz, write cycle
tWC
tAW
tWP
tDW
BCLK
A[23:0]
#CEx
#WR
D[15:0] WR data
;;;;;
;;;;;
;;;
;;;
tDH
APPENDIX A <REFERENCE> E X TERNAL DEVICE INTERFACE TIMINGS
A-126 EPSON S1C33L03 P RODUCT PART
SRAM: 70ns , CPU: 25/20MHz, rea d cyc le
BCLK
A[23:0]
#CEx
#RD
D[15:0]
RD data
;;;;;
;;;;;
;;;;;;;;;
;;;;;;;;;
;;;;
;;;;
SRAM: 70ns , CPU: 25/20 MH z, wri te cycle
BCLK
A[23:0]
#CEx
#WR
D[15:0]
WR data
;;;;;
;;;;;
;;;
;;;
APPENDIX A <REFERENCE> E X TERNAL DEVICE INTERFACE TIMINGS
S1C33L03 PRODUCT PART EPSON A-127
A-1
A-ap
A.6 8255A
8255A interface setup exampl es
Operating Read cycle Output disable
frequency Wait cycle Read cycle Write cycle delay cycle
20 MHz 9 ∗110 10 3.5
25MHz 11 12 12 3.5
33MHz 14 15 15 3.5 ∗2
8255A interf ace ti ming
SRAM interfa ce 33MHz 25MHz 20MHz
Parameter Symbol Min. Max. Cycle Time Cycle Time Cycle Time
<Read cycle>
Read cycle time tRC 300 – 15 450 12 480 10 500
Address access time tACC –25015450 12 480 10 500
#CE access time tACS –25015450 12 480 10 500
#OE access time tOE –25014.5435 11.5460 9.5475
Output disable delay time tOHZ 10 150 3.5 105 3.5 140 3.5 175
<Write cycle>
Write cycle time tWC 430 – 15 450 12 480 10 500
Address enable time tAW 400 – 14.5 435 11.5 460 9.5 475
Write pulse width tWP 400 – 14 420 11 440 9 450
Input data setup time tDW 100 – 14 420 11 440 9 450
Input data hold time ∗3tDH 30 – 0.5 15 0.5 20 0.5 25
∗1The S1C33L03 enables up to 7 cycles of wait-cycle insertion. If a number of wait cycles more than 7 cycles
needs to be inserted, input the #WAIT signal from external hardware. Note that the interface must be set for
SR AM type de vices to insert wait cycles using the #WAIT pin. (Refer to "BCU (Bus Control Unit)" in the
"S1C33L03 FUNCTION PART", for more information.)
∗2This setting cannot satisfy the 150 ns of output-disable delay time specification required for the 8255A. When
implementing such a low-speed device in the system, the external bus must be separated by inserting a 3-state
bus buffer at the output sid e (whe n view ed from the CPU) of the external system bus.
∗3If the data hold time that can be set is not sufficient for the device, secure it by connecting a bus repeater to the
external data bus D[15:0] or by inserting a latch at the output side of the external system interface.
APPENDIX B P IN CHARACTE RISTICS
A-128 EPSON S1C33L03 P RODUCT PART
Appendi x B Pi n Char acteristi cs
CharacteristicPin
No. Signal name I/O cell
name Input Output Pull-
up/down Power
supply Remarks
1P22/TM0 XHBH1T CMOS/LVTTL SCHMITT Type1 VDDE
2P23/TM1 XHBH1T CMOS/LVTTL SCHMITT Type1 VDDE
3VSS VSS
4P24/TM2/#SRDY2 XHBH1T CMOS/LVTTL SCHMITT Type1 VDDE
5P25/TM3/#SCLK2 XHBH1T CMOS/LVTTL SCHMITT Type1 VDDE
6P26/TM4/SOUT2 XHBH1T CMOS/LVTTL SCHMITT Type1 VDDE
7P27/TM5/SIN2 XHBH1T CMOS/LVTTL SCHMITT Type1 VDDE
8VDD LVDD
9P07/#SRDY1/#DMAEND3 XHBH1T CMOS/LVTTL SCHMITT Type1 VDDE
10 P06/#SCLK1/#DMAACK3 XHBH1T CMOS/LVTTL SCHMITT Type1 VDDE
11 P05/SOUT1/#DMAEND2 XHBH1T CMOS/LVTTL SCHMITT Type1 VDDE
12 P04/SIN1/#DMAACK2 XHBH1T CMOS/LVTTL SCHM ITT Type1 VDDE
13 FPDAT7 XHBC3BT CMOS/LVTTL Type3 VDDE
14 FPDAT6 XHBC3BT CMOS/LVTTL Type3 VDDE
15 FPDAT5 XHBC3BT CMOS/LVTTL Type3 VDDE
16 FPDAT4 XHBC3BT CMOS/LVTTL Type3 VDDE
17 FPDAT3/GPO6 XHBC3BT CMOS/LVTTL Type3 VDDE
18 FPDAT2/GPO5 XHBC3BT CMOS/LVTTL Type3 VDDE
19 FPDAT1/GPO4 XHBC3BT CMOS/LVTTL Type3 VDDE
20 FPDAT0/GPO3 XHBC3BT CMOS/LVTTL Type3 VDDE
21 VDDE HVDD
22 DRDY(MOD/FPSHIFT2) XHBC3BT CMOS/LVTTL Type3 VDDE
23 FPFRAME XHBC3BT CMOS/LVTTL Type3 VDDE
24 FPLINE XHBC3BT CMOS/LVTTL Type3 VDDE
25 FPSHIFT XHBC3BT CMOS/LVTTL Type3 VDDE
26 LCDPWR XHTB1T Type1 VDDE
27 VSS VSS
28 K67/AD7 XHIBCLINW CMOS/LVTTL AVDDE note 1
29 K66/AD6 XHIBCLINW CMOS/LVTTL AVDDE note 1
30 K65/AD5 XHIBCLINW CMOS/LVTTL AVDDE note 1
31 K64/AD4 XHIBCLINW CMOS/LVTTL AVDDE note 1
32 K63/AD3 XHIBCLINW CMOS/LVTTL AVDDE note 1
33 K62/AD2 XHIBCLINW CMOS/LVTTL AVDDE note 1
34 K61/AD1 XHIBCLINW CMOS/LVTTL AVDDE note 1
35 K60/AD0 XHIBCLINW CMOS/LVTTL AVDDE note 1
36 AVDDE HVDD
37 K54/#DMAREQ3 XHIBHP2 CMOS/LVTTL SCHMITT Pull-up VDDE
38 K53/#DMAREQ2 XHIBHP2 CMOS/LVTTL SCHMITT Pull-up VDDE
39 K52/#ADTRG XHIBHP2 CMOS/LVTTL SCHMITT Pull-up VDDE
40 K51/#DMAREQ1 XHIBHP2 CMOS/LVTTL SCHMITT Pull-up VDDE
41 K50/#DMAREQ0 XHIBHP2 CMOS/LVTTL SCHMITT Pull-up VDDE
42 #WRH/#BSH XHBC1T note 3 Type1 VDDE
43 #WRL/#WR/#WE XHBC1T note 3 Type1 VDDE
44 #RD XHBC1T note 3 Type1 VDDE
45 VSS VSS
46 D15 XHBC1T CMOS/LVTTL Type1 VDDE
47 D14 XHBC1T CMOS/LVTTL Type1 VDDE
48 D13 XHBC1T CMOS/LVTTL Type1 VDDE
49 D12 XHBC1T CMOS/LVTTL Type1 VDDE
50 D11 XHBC1T CMOS/LVTTL Type1 VDDE
APPENDIX B P IN CHARACTE RISTICS
S1C33L03 PRODUCT PART EPSON A-129
A-1
A-ap
CharacteristicPin
No. Signal name I/O cell
name Input Output Pull-
up/down Power
supply Remarks
51 VDD LVDD
52 D10 XHBC1T CMOS/LVTTL Type1 VDDE
53 D9 XHBC1T CMOS/LVTTL Type1 VDDE
54 D8 XHBC1T CMOS/LVTTL Type1 VDDE
55 D7 XHBC1T CMOS/LVTTL Type1 VDDE
56 D6 XHBC1T CMOS/LVTTL Type1 VDDE
57 D5 XHBC1T CMOS/LVTTL Type1 VDDE
58 D4 XHBC1T CMOS/LVTTL Type1 VDDE
59 VDDE HVDD
60 D3 XHBC1T CMOS/LVTTL Type1 VDDE
61 D2 XHBC1T CMOS/LVTTL Type1 VDDE
62 D1 XHBC1T CMOS/LVTTL Type1 VDDE
63 D0 XHBC1T CMOS/LVTTL Type1 VDDE
64 #CE8/#RAS1/#CE14/#RAS3/#SDCE1 XHBC1T note 3 Type1 VDDE
65 #CE7/#RAS0/#CE13/#RAS2/#SDCE0 XHBC1T note 3 Type1 VDDE
66 VSS VSS
67 OSC2 XLLOT VDD
68 OSC1 XLLIN VDD note 2
69 #RESET XHIBHP2 CMOS/LVTTL SCHMITT Pull-up VDDE
70 P35/#BUSACK/GPIO1 XHBH1T CMOS/LVTTL SCHMITT Type1 VDDE
71 P34/#BUSREQ/#CE6/GPIO0 XHBH1T CMOS/LVTTL SCHMITT Type1 VDDE
72 P33/#DMAACK1/SIN3/SDA10 XHBH1T CMOS/LVTTL SCHMITT Type1 VDDE
73 P32/#DMAACK0/#SRDY3/HDQM XHBH1T CMOS/LVTTL SCHMITT Type1 VDDE
74 P31/#BUSGET/#GARD/GPIO2 XHBH1T CMOS/LVTTL SCHMITT Type1 VDDE
75 P30/#WAIT/#CE4&5 XHBH1T CMOS/LVTTL SCHMITT Type1 VDDE
76 #LCAS/#SDRAS XHTB1T Type1 VDDE
77 #HCAS/#SDCAS XHTB1T Type1 VDDE
78 VDD LVDD
79 P21/#DWE/#GAAS/#SDWE XHBH1T CMOS/LVTTL SCHMITT Type1 VDDE
80 P20/#DRD/SDCKE XHBH1T CMOS/LVTTL SCHMITT Type1 VDDE
81 BCLK/SDCLK XHTB1T Type1 VDDE
82 VSS VSS
83 P16/EXCL5/#DMAEND1/SOUT3 XHBH1T CMOS/LVTTL SCH MITT Type1 VDDE
84 P15/EXCL4/#DMAEND0/#SCLK3/LDQM XHBH1T CMOS/LVTTL SCHMITT Type1 V DDE
85 A0/#BSL XHBC1T note 3 Type1 VDDE
86 A1/SDA0 XHBC1T note 3 Type1 VDDE
87 A2/SDA1 XHBC1T note 3 Type1 VDDE
88 A3/SDA2 XHBC1T note 3 Type1 VDDE
89 A4/SDA3 XHBC1T note 3 Type1 VDDE
90 A5/SDA4 XHBC1T note 3 Type1 VDDE
91 VDDE HVDD
92 A6/SDA5 XHBC1T note 3 Type1 VDDE
93 A7/SDA6 XHBC1T note 3 Type1 VDDE
94 A8/SDA7 XHBC1T note 3 Type1 VDDE
95 A9/SDA8 XHBC1T note 3 Type1 VDDE
96 A10/SDA9 XHBC1T note 3 Type1 VDDE
97 A11 XHBC1T note 3 Type1 VDDE
98 VSS VSS
99 A12/SDA11 XHBC1T note 3 Type1 VDDE
100 A13/SDA12 XHBC1T note 3 Type1 VDDE
APPENDIX B P IN CHARACTE RISTICS
A-130 EPSON S1C33L03 P RODUCT PART
CharacteristicPin
No. Signal name I/O cell
name Input Output Pull-
up/down Power
supply Remarks
101 A14/SDBA0 XHBC1T note 3 Type1 VDDE
102 A15/SDBA1 XHBC1T note 3 Type1 VDDE
103 A16 XHBC1T note 3 Type1 VDDE
104 A17 XHBC1T note 3 Type1 VDDE
105 VSS VSS
106 A18 XHBC1T note 3 Type1 VDDE
107 A19 XHBC1T note 3 Type1 VDDE
108 A20 XHBC1T note 3 Type1 VDDE
109 A21 XHBC1T note 3 Type1 VDDE
110 A22 XHBC1T note 3 Type1 VDDE
111 A23 XHBC1T note 3 Type1 VDDE
112 PLLS1 XHIBC CMOS/LVTTL VDDE
113 PLLS0 XHIBC CMOS/LVTTL VDDE
114 VSS VSS
115 PLLC XLLIN VDD note 2
116 VSS VSS
117 DSIO XLBH2P2T CMOS/LVTTL SCHMITT Type2 Pull-up VDD note 2
118 P14/FOSC1/DCLK XLBH2T CMOS/LVTTL SCHMITT Type2 VDD note 2
119 P13/EXCL3/T8UF3/DPCO XLBH2T CMOS/LVTTL SCHMITT Type2 VDD note 2
120 P12/EXCL2/T8UF2/DST2 XLBH2T CMOS/LVTTL SCHMITT Type2 VDD note 2
121 P11/EXCL1/T8UF1/DST1 XLBH2T CMOS/LVTTL SCHMITT Type2 VDD note 2
122 P10/EXCL0/T8UF0/DST0 XLBH2T CMOS/LVTTL SCHMITT Type2 VDD note 2
123 EA10MD1 XHIBCP2 CMOS/LVTTL Pull-up VDDE
124 EA10MD0 XHIBC CMOS/LVTTL VDDE
125 ICEMD XITST1 Pull-down Test pin
126 #EMEMRD XHTB1T Type1 VDDE
127 VDD LVDD
128 OSC4 XLLOT VDD
129 OSC3 XLLIN VDD note 2
130 #NMI XHIBHP2 CMOS/LVTTL SCHMITT Pull-up VDDE
131 #CE9/#CE17/#CE17&18 XHBC1T note 3 Type1 VDDE
132 VDDE HVDD
133 #CE5/#CE15/#CE15&16 XHBC1T note 3 Type1 VDDE
134 N.C.
135 #CE3 XHTB1T Type1 VDDE
136 VSS VSS
137 #CE10EX/#CE9&10EX XHBC1T note 3 Type1 VDDE
138 #CE6/#CE7&8 XHBC1T note 3 Type1 VDDE
139 #CE4/#CE11/#CE11&12 XHBC1T note 3 Type1 VDDE
140 #X2SPD XHIBCCMOS/LVTTL VDDE
141 P03/#SRDY0 XHBH1T CMOS/LVTTL SCHMITT Type1 VDDE
142 P02/#SCLK0 XHBH1T CMOS/LVTTL SCHMITT Type1 VDDE
143 P01/SOUT0 XHBH1T CMOS/LVTTL SCHMITT Type1 VDDE
144 P00/SIN0 XHBH1T CMOS/LVTTL SCH MITT Type1 VDDE
note 1) The voltage applied to this pin must be 0V ≤ VIN ≤ AVDDE.
Note that the input voltage range for the K50 pin differs from other K5x pins.
note 2) The voltage applied to this pin must be 0V ≤ VIN ≤ VDD.
note 3) This pin is set as an input pin during device testing. Normally it is an output pin.
The following table lists output current characteristics.
Output current (IOL/IOH)5.0 V 3.3 V 2.0 V
Type1 3 mA 2 mA 0.6 mA
Type2 –6 mA2 mA
Type3 12 mA 12 mA 4 mA
S1C33L03
FUNCTION PART
S1C33L03 FUNCTION PART
I OUTLINE
I OUTLINE: INTRODUCTION
S1C33L03 FUNCTION PART EPSON B-I-1-1
A-1
B-I
Intro
I-1 INTRODUCTION
The Func tion Part gi ves a detailed descri ption of the various function blocks built into the Seiko Epson original
32-bit microcomputer S1C33L03.
The S1C33L03 employs a RISC type CPU, and has a powerful instruction set capable of compilation into compact
code, despite the small CPU core size.
The S1C3 3L03 has the foll ow ing features:
•Small CPU core: 25K gates
•Fast and high performance: DC to 50 MHz operation
•Strong instruction set: 16-bit fixed length, 105 basic instructions
•Execution cycle: Major instructions are executed in 1 cycle per instruction
•MAC function: 16 bits × 16 bits + 64 bits, 2 clock per MAC (25 MOPS in 50 MHz)
•Registers:32 bits × 16 general regist ers and 32 bits × 5 special registers
•Memory spa ce: 256M bytes (28 bits) linear sp ac e, co de -data - I O sh ar ed type
•External bus I/F: 15 configurable m emory areas
Direct connection to external memory
•Interrupts: Reset, NMI, up to 128 external interrupts, 4 software interrupts, 2 exceptions
•Reset, boot: Cold reset, hot reset
•Power down mode: Sleep, Ha lt
•Others: Little endian (partial big endian can be configured)
Harvard architecture (fetch, load/store parallel execution)
•User logic interface: Programmable wait state (up to 7 cycles)
#WAIT pin hand shake is possible .
Large memory space for the user logic (up to 16M bytes)
BCU configuration registers allow internal use of the external areas (Areas 4 to 18).
Many interrupt requests from the user logic are acceptable.
I OUTLINE: INTRODUCTION
B-I-1-2 EPSON S1C33L03 FUNCTION PART
TH IS PAGE IS BLANK.
I OUTLINE: BLOCK DIAGRAM
S1C33L03 FUNCTION PART EPSON B-I-2-1
A-1
B-I
Block
I-2 BLOCK DIAGRAM
The S1C3 3L03 consists of seven major blocks: C33 Co re Block, C33 Periphe ral Block, C33 Analog Bloc k, C33
DMA Bloc k, C33 SDRAM Co ntrol ler Bl ock, C33 LCD Contr oller Block and C33 Internal Memory Bl ock.
Figure 2.1 shows the configuration of the S1C33 blocks.
CORE_PAD
Pads
C33_SBUS
C33 Core Block
C33 LCD Controller Block
Pads
PERI_PAD
Pads
C33_PERI
(Prescaler, 8-bit timer, 16-bit timer,
Clock timer, Serial interface, Ports)
C33 Peripheral BlockC33 Analog Block
C33_CORE
(CPU, BCU, ITC, CLG, DBG)
C33_ADC
(A/D converter)
C33 Internal Memory Block
Internal RAM
(Area 0)
Internal ROM
(Area 10)
C33 DMA Block
C33_DMA
(IDMA, HSDMA)
C33_SDRAMC
(SDRAM interface)
C33_LCDC
(LCD panel interface)
C33 SDRAM Controller Block
Figur e 2.1 Block Configuration
Note: In te rn al RO M is not prov ided in the S 1C33L03 .
I OUTLINE: BLOCK DIAGRAM
B-I-2-2 EPSON S1C33L03 FUNCTION PART
C33 Core Block
The C33 Core Bloc k consi sts of a functional block C33_CORE including CPU, BCU (Bus Control Unit), ITC
(Interrupt Controller), CLG (Clock Generator) and DBG (Debug Unit), an I/O pad block for external
interface, and an SBUS (Internal Silicon Integration Bus) for interfacing with on-chip Peripheral Macro Cells.
The C33 Co re Block employs the S1C33000 32-bit RISC type CPU as the c ore CPU.
C33 Periphera l Block
The C 33 Pe ripheral Block consists of a prescaler, six channels of 8-bit programmable timer, six channels of
16-bit programmable timer including watchdog timer function, four channels of serial interface, input and I/O
ports, and a cloc k ti mer.
C33 Analog Block
The C33 Ana log Block consists of an A/D con verter with eight input channels.
C33 DMA Block
The C33 DMA Block is configu red with two types of DMA controllers: HSDMA (High-Speed DMA) that
has on-chip registers for controlling DMA command information and IDMA (Intelligent DMA) that uses a
memory area for storing DMA command information.
C33 SDRAM Controller Block
The SDRAM Controller Bloc k provides a SD RA M interface th at allo ws dire ct conn ectio n o f extern al
SD RAM chips via the BCU.
C33 LCD Cont roller Block
The LCD Controlle r Block provides LCD con tr ol signals for a 4- or 8-bit color/monochrome LCD panel.
C33 Memory Block
The S1C3 3L03 contains an 8KB of SRAM as the internal m emor y.
For details of the blocks, refer to the respective section in this manual.
I OUTLINE: LIST OF PINS
S1C33L03 FUNCTION PART EPSON B-I-3-1
A-1
B-I
Pin
I-3 LIST OF PINS
List of External I/O Pins
The following lists the external I/O pins of the C33 Core Block, Peripheral Block and LCD Controller Block. Note
that some pins are listed in two or more tables.
Table 3.1 List of Pins for External Bus Interface Signals
Pin name Pin No. I/O Pull-up Function
A0
#BSL 85 O – A0: Address bus (A0) when SBUSST(D3/0x4812E) = "0" (default)
#BSL: Bus strobe (low byte) signal when SBUSST(D3/0x4812E) = "1"
A[10:1]
SDA[9:0] 85–90,92–96 O–A[10:1]: Address bus (A1–A10)
SDA[9:0]: SDRAM address bus (SDA0–SDA9)
A11 97 O – Address bus (A11)
A[13:12]
SDA[12:11] 99,100 O – A[13:12]: Address bus (A12–A13)
SDA[12:11]: SDRAM address bus (SDA11–SDA12)
A[15:14]
SDBA[1:0] 101,102 O – A[15:14]: Address bus (A14–A15)
SDBA[1:0]: SDRAM bank select (SDBA0–SDBA1)
A[23:16] 103,104,
106–111 O–Address bus (A16–A23)
D[15:0] 46–50,52–58,
60–63 I/O – Data bus (D0–D15)
#CE10EX
#CE9&10EX 137 O – Area 10 chip enable for external memory
* When CEFUNC[1:0] = "1x", this pin outputs #CE9+#CE10EX signal.
#CE9
#CE17
#CE17&18
131 O – #CE9: Area 9 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "00" (default)
#CE17: Area 17 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "01"
* When CEFUNC[1:0] = "1x", this pin outputs #CE17+#CE18 signal.
#CE8
#RAS1
#CE14
#RAS3
#SDCE1
64 O – #CE8: Area 8 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "00",
A8DRA(D8/0x48128) = "0" and SDRPC1(D2/0x39FFC0) = "0" (default)
#RAS1: Area 8 DRAM row strobe when CEFUNC[1:0](D[A:9]/0x48130) = "00",
A8DRA(D8/0x48128) = "1" and SDRPC1(D2/0x39FFC0) = "0"
#CE14: Area 14 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "01" or "1x",
A14DRA(D8/0x48122) = "0" and SDRPC1(D2/0x39FFC0) = "0"
#RAS3: Area 14 DRAM row strobe when CEFUNC[1:0](D[A:9]/0x48130) = "01" or
"1x", A14DRA(D8/0x48122) = "1" and SDRPC1(D2/0x39FFC0) = "0"
#SDCE1: SDRAM chip enable 1 when SDRPC1(D2/0x39FFC0) = "1" and
SDRENA(D7/0x39FFC1) = "1"
#CE7
#RAS0
#CE13
#RAS2
#SDCE0
65 O – #CE7: Area 7 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "00",
A7DRA(D7/0x48128) = "0" and SDRPC0(D3/0x39FFC0) = "0" (default)
#RAS0: Area 7 DRAM row strobe when CEFUNC[1:0](D[A:9]/0x48130) = "00",
A7DRA(D7/0x48128) = "1" and SDRPC0(D3/0x39FFC0) = "0"
#CE13: Area 13 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "01" or "1x",
A13DRA(D7/0x48122) = "0" and SDRPC0(D3/0x39FFC0) = "0"
#RAS2: Area 13 DRAM row strobe when CEFUNC[1:0](D[A:9]/0x48130) = "01" or
"1x", A13DRA(D7/0x48122) = "1" and SDRPC0(D3/0x39FFC0) = "0"
#SDCE0: SDRAM chip enable 0 when SDRPC0(D3/0x39FFC0) = "1" and
SDRENA(D7/0x39FFC1) = "1"
#CE6
#CE7&8 138 O – Area 6 chip enable
* When CEFUNC[1:0] = "1x", this pin outputs #CE7+#CE8 signal.
#CE5
#CE15
#CE15&16
133 O – #CE5: Area 5 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "00" (default)
#CE15: Area 15 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "01"
* When CEFUNC[1:0] = "1x", this pin outputs #CE15+#CE16 signal.
#CE4
#CE11
#CE11&12
139 O – #CE4: Area 4 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "00" (default)
#CE11: Area 11 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "01"
* When CEFUNC[1:0] = "1x", this pin outputs #CE11+#CE12 signal.
#CE3 135 O – Area 3 chip enable
#RD 44 O – Read signal
#EMEMRD 126 O – Read signal for internal ROM emulation memory
#WRL
#WR
#WE
43 O – #WRL: Write (low byte) signal when SBUSST(D3/0x4812E) = "0" (default)
#WR: Write signal when SBUSST(D3/0x4812E) = "1"
#WE: DRAM write signal
#WRH
#BSH 42 O – #WRH: Write (high byte) signal when SBUSST(D3/0x4812E) = "0" (default)
#BSH: Bus strobe (high byte) signal when SBUSST(D3/0x4812E) = "1"
I OUTLINE: LIST OF PINS
B-I-3-2 EPSON S1C33L03 FUNCTION PART
Pin name Pin No. I/O Pull-up Function
#HCAS
#SDCAS 77 O – #HCAS: DRAM column address strobe (high byte) signal when
SDRENA(D7/0x39FFC1) = "0" (default)
#SDCAS: SDRAM column address strobe when SDRENA(D7/0x39FFC1) = "1"
#LCAS
#SDRAS 76 O – #LCAS: DRAM column address strobe (low byte) signal when
SDRENA(D7/0x39FFC1) = "0" (default)
#SDRAS: SDRAM row address strobe when SDRENA(D7/0x39FFC1) = "1"
BCLK
SDCLK 81 O – BCLK: Bus clock output when SDRENA(D7/0x39FFC1) = "0" (default)
SDCLK: SDRAM clock output when SDRENA(D7/0x39FFC1) = "1"
P34
#BUSREQ
#CE6
GPIO0
71 I/O – P34: I/O port when CFP34(D4/0x402DC) = "0" (default)
#BUSREQ: Bus release request input when CFP34(D4/0x402DC) = "1"
#CE6: Area 6 chip enable when CFP34(D4/0x402DC) = "1" and
IOC34(D4/0x402DE) = "1"
GPIO0: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and
BREQEN(D2/0x39FFFD) = "0"
P35
#BUSACK
GPIO1
70 I/O – P35: I/O port when CFP35(D5/0x402DC) = "0" (default)
#BUSACK: Bus acknowledge output when CFP35(D5/0x402DC) = "1" and
CFP34(D4/0x402DC) = "1"
GPIO1: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and
BREQEN(D2/0x39FFFD) = "0"
P30
#WAIT
#CE4&5
75 I/O – P30: I/O port when CFP30(D0/0x402DC) = "0" (default)
#WAIT: Wait cycle request input when CFP30(D0/0x402DC) = "1"
#CE4&5: Areas 4&5 chip enable when CFP30(D0/0x402DC) = "1" and
IOC30(D0/0x402DE) = "1"
P20
#DRD
SDCKE
80 I/O – P20: I/O port when CFP20(D0/0x402D8) = "0" and SDRENA(D7/0x39FFC1) =
"0" (default)
#DRD: DRAM read signal output for successive RAS mode when
CFP20(D0/0x402D8) = "1" and SDRENA(D7/0x39FFC1) = "0"
SDCKE: SDRAM clock enable signal when SDRENA(D7/0x39FFC1) = "1"
P21
#DWE
#GAAS
#SDWE
79 I/O – P21: I/O port when CFP21(D1/0x402D8) = "0", CFEX2(D2/0x402DF) = "0" and
SDRENA(D7/0x39FFC1) = "0" (default)
#DWE: DRAM write signal output for successive RAS mode when
CFP21(D1/0x402D8) = "1", CFEX2(D2/0x402DF) = "0" and
SDRENA(D7/0x39FFC1) = "0"
#GAAS: Area address strobe output for GA when CFEX2(D2/0x402DF) = "1" and
SDRENA(D7/0x39FFC1) = "0"
#SDWE: SDRAM write signal when SDRENA(D7/0x39FFC1) = "1"
P31
#BUSGET
#GARD
GPIO2
74 I/O – P31: I/O port when CFP31(D1/0x402DC) = "0" and CFEX3(D3/0x402DF) = "0"
(default)
#BUSGET: Bus status monitor signal output for bus release request when
CFP31(D1/0x402DC) = "1" and CFEX3(D3/0x402DF) = "0"
#GARD: Area read signal output for GA when CFEX3(D3/0x402DF) = "1"
GPIO2: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and
BREQEN(D2/0x39FFFD) = "0"
EA10MD1 123 I Pull-up Area 10 boot mode selection
EA10MD1 EA10MD0 Mode
EA10MD0 124 I – 1 1 External ROM mode
10Internal ROM mode
I OUTLINE: LIST OF PINS
S1C33L03 FUNCTION PART EPSON B-I-3-3
A-1
B-I
Pin
Table 3.2 List of Pins for HSDMA Control Signals
Pin name Pin No. I/O Pull-up Function
K50
#DMAREQ0 41 I Pull-up K50: Input port when CFK50(D0/0x402C0) = "0" (default)
#DMAREQ0: HSDMA Ch. 0 request input when CFK50(D0/0x402C0) = "1"
K51
#DMAREQ1 40 I Pull-up K51: Input port when CFK51(D1/0x402C0) = "0" (default)
#DMAREQ1: HSDMA Ch. 1 request input when CFK51(D1/0x402C0) = "1"
K53
#DMAREQ2 38 I Pull-up K53: Input port when CFK53(D3/0x402C0) = "0" (default)
#DMAREQ2: HSDMA Ch. 2 request input when CFK53(D3/0x402C0) = "1"
K54
#DMAREQ3 37 I Pull-up K54: Input port when CFK54(D4/0x402C0) = "0" (default)
#DMAREQ3: HSDMA Ch. 3 request input when CFK54(D4/0x402C0) = "1"
P32
#DMAACK0
#SRDY3
HDQM
73 I/O – P32: I/O port when CFP32(D2/0x402DC) = "0" and SDRENA(D7/0x39FFC1) = "0"
(default)
#DMAACK0: HSDMA Ch. 0 acknowledge output when CFP32(D2/0x402DC) = "1" and
SDRENA(D7/0x39FFC1) = "0"
#SRDY3: Serial I/F Ch. 3 ready signal input/output when SSRDY3(D3/0x402D7) =
"1", CFP32(D2/0x402DC) = "0" and SDRENA(D7/0x39FFC1) = "0"
HDQM: SDRAM data (high byte) input/output mask signal when
SDRENA(D7/0x39FFC1) = "1"
P33
#DMAACK1
SIN3
SDA10
72 I/O – P33: I/O port when CFP33(D3/0x402DC) = "0" and SDRENA(D7/0x39FFC1) = "0"
(default)
#DMAACK1: HSDMA Ch. 1 acknowledge output when CFP33(D3/0x402DC) = "1" and
SDRENA(D7/0x39FFC1) = "0"
SIN3:Serial I/F Ch. 3 data input when SSIN3(D0/0x402D7) = "1",
CFP33(D3/0x402DC) = "0" and SDRENA(D7/0x39FFC1) = "0"
SDA10: SDRAM address bus bit 10 when SDRENA(D7/0x39FFC1) = "1"
P04
SIN1
#DMAACK2
12 I/O – P04: I/O port when CFP04(D4/0x402D0) = "0" and CFEX4(D4/0x402DF) = "0"
(default)
SIN1:Serial I/F Ch. 1 data input when CFP04(D4/0x402D0) = "1" and
CFEX4(D4/0x402DF) = "0"
#DMAACK2: HSDMA Ch. 2 acknowledge output when CFEX4(D4/0x402DF) = "1"
P06
#SCLK1
#DMAACK3
10 I/O – P06: I/O port when CFP06(D6/0x402D0) = "0" and CFEX6(D6/0x402DF) = "0"
(default)
#SCLK1: Serial I/F Ch. 1 clock input/output when CFP06(D6/0x402D0) = "1" and
CFEX6(D6/0x402DF) = "0"
#DMAACK3: HSDMA Ch. 3 acknowledge output when CFEX6(D6/0x402DF) = "1"
P15
EXCL4
#DMAEND0
#SCLK3
LDQM
84 I/O – P15: I/O port when CFP15(D5/0x402D4) = "0" and SDRENA(D7/0x39FFC1) = "0"
(default)
EXCL4: 16-bit timer 4 event counter input when CFP15(D5/0x402D4) = "1",
IOC15(D5/0x402D6) = "0" and SDRENA(D7/0x39FFC1) = "0"
#DMAEND0: HSDMA Ch. 0 end-of-transfer signal output when CFP15(D5/0x402D4) =
"1", IOC15(D5/0x402D6) = "1" and SDRENA(D7/0x39FFC1) = "0"
#SCLK3: Serial I/F Ch. 3 clock input/output when SSCLK3(D2/0x402D7) = "1",
CFP15(D5/0x402D4) = "0" and SDRENA(D7/0x39FFC1) = "0"
LDQM: SDRAM data (low byte) input/output mask signal when
SDRENA(D7/0x39FFC1) = "1"
P16
EXCL5
#DMAEND1
SOUT3
83 I/O – P16: I/O port when CFP16(D6/0x402D4) = "0" (default)
EXCL5: 16-bit timer 5 event counter input when CFP16(D6/0x402D4) = "1" and
IOC16(D6/0x402D6) = "0"
#DMAEND1: HSDMA Ch. 1 end-of-transfer signal output when CFP16(D6/0x402D4) = "1"
and IOC16(D6/0x402D6) = "1"
SOUT3: Serial I/F Ch. 3 data output when SSOUT3(D1/0x402D7) = "1" and
CFP16(D6/0x402D4) = "0"
P05
SOUT1
#DMAEND2
11 I/O – P05: I/O port when CFP05(D5/0x402D0) = "0" and CFEX5(D5/0x402DF) = "0"
(default)
SOUT1: Serial I/F Ch. 1 data output when CFP05(D5/0x402D0) = "1" and
CFEX5(D5/0x402DF) = "0"
#DMAEND2: HSDMA Ch. 2 end-of-transfer signal output when CFEX5(D5/0x402DF) = "1"
P07
#SRDY1
#DMAEND3
9I/O – P07: I/O port when CFP07(D7/0x402D0) = "0" and CFEX7(D7/0x402DF) = "0"
(default)
#SRDY1: Serial I/F Ch. 1 ready signal output when CFP07(D7/0x402D0) = "1" and
CFEX5(D5/0x402DF) = "0"
#DMAEND3: HSDMA Ch. 3 end-of-transfer signal output when CFEX7(D7/0x402DF) = "1"
I OUTLINE: LIST OF PINS
B-I-3-4 EPSON S1C33L03 FUNCTION PART
Table 3.3 List of Pins for Internal Peripheral Circuits
Pin name Pin No. I/O Pull-up Function
K50
#DMAREQ0 41 I Pull-up K50: Input port when CFK50(D0/0x402C0) = "0" (default)
#DMAREQ0: HSDMA Ch. 0 request input when CFK50(D0/0x402C0) = "1"
K51
#DMAREQ1 40 I Pull-up K51: Input port when CFK51(D1/0x402C0) = "0" (default)
#DMAREQ1: HSDMA Ch. 1 request input when CFK51(D1/0x402C0) = "1"
K52
#ADTRG 39 I Pull-up K52: Input port when CFK52(D2/0x402C0) = "0" (default)
#ADTRG: A/D converter trigger input when CFK52(D2/0x402C0) = "1"
K53
#DMAREQ2 38 I Pull-up K53: Input port when CFK53(D3/0x402C0) = "0" (default)
#DMAREQ2: HSDMA Ch. 2 request input when CFK53(D3/0x402C0) = "1"
K54
#DMAREQ3 37 I Pull-up K54: Input port when CFK54(D4/0x402C0) = "0" (default)
#DMAREQ3: HSDMA Ch. 3 request input when CFK54(D4/0x402C0) = "1"
K60
AD0 35 I – K60: Input port when CFK60(D0/0x402C3) = "0" (default)
AD0: A/D converter Ch. 0 input when CFK60(D0/0x402C3) = "1"
K61
AD1 34 I – K61: Input port when CFK61(D1/0x402C3) = "0" (default)
AD1: A/D converter Ch. 1 input when CFK61(D1/0x402C3) = "1"
K62
AD2 33 I – K62: Input port when CFK62(D2/0x402C3) = "0" (default)
AD2: A/D converter Ch. 2 input when CFK62(D2/0x402C3) = "1"
K63
AD3 32 I – K63: Input port when CFK63(D3/0x402C3) = "0" (default)
AD3: A/D converter Ch. 3 input when CFK63(D3/0x402C3) = "1"
K64
AD4 31 I – K64: Input port when CFK64(D4/0x402C3) = "0" (default)
AD4: A/D converter Ch. 4 input when CFK64(D4/0x402C3) = "1"
K65
AD5 30 I – K65: Input port when CFK65(D5/0x402C3) = "0" (default)
AD5: A/D converter Ch. 5 input when CFK65(D5/0x402C3) = "1"
K66
AD6 29 I – K66: Input port when CFK66(D6/0x402C3) = "0" (default)
AD6: A/D converter Ch. 6 input when CFK66(D6/0x402C3) = "1"
K67
AD7 28 I – K67: Input port when CFK67(D7/0x402C3) = "0" (default)
AD7: A/D converter Ch. 7 input when CFK67(D7/0x402C3) = "1"
P00
SIN0 144 I/O – P00: I/O port when CFP00(D0/0x402D0) = "0" (default)
SIN0:Serial I/F Ch. 0 data input when CFP00(D0/0x402D0) = "1"
P01
SOUT0 143 I/O – P01: I/O port when CFP01(D1/0x402D0) = "0" (default)
SOUT0: Serial I/F Ch. 0 data output when CFP01(D1/0x402D0) = "1"
P02
#SCLK0 142 I/O – P02: I/O port when CFP02(D2/0x402D0) = "0" (default)
#SCLK0: Serial I/F Ch. 0 clock input/output when CFP02(D2/0x402D0) = "1"
P03
#SRDY0 141 I/O – P03: I/O port when CFP03(D3/0x402D0) = "0" (default)
#SRDY0: Serial I/F Ch. 0 ready signal input/output when CFP03(D3/0x402D0) = "1"
P04
SIN1
#DMAACK2
12 I/O – P04: I/O port when CFP04(D4/0x402D0) = "0" and CFEX4(D4/0x402DF) = "0"
(default)
SIN1:Serial I/F Ch. 1 data input when CFP04(D4/0x402D0) = "1" and
CFEX4(D4/0x402DF) = "0"
#DMAACK2: HSDMA Ch. 2 acknowledge output when CFEX4(D4/0x402DF) = "1"
P05
SOUT1
#DMAEND2
11 I/O – P05: I/O port when CFP05(D5/0x402D0) = "0" and CFEX5(D5/0x402DF) = "0"
(default)
SOUT1: Serial I/F Ch. 1 data output when CFP05(D5/0x402D0) = "1" and
CFEX5(D5/0x402DF) = "0"
#DMAEND2: HSDMA Ch. 2 end-of-transfer signal output when
CFEX5(D5/0x402DF) = "1"
P06
#SCLK1
#DMAACK3
10 I/O – P06: I/O port when CFP06(D6/0x402D0) = "0" and CFEX6(D6/0x402DF) = "0"
(default)
#SCLK1: Serial I/F Ch. 1 clock input/output when CFP06(D6/0x402D0) = "1" and
CFEX6(D6/0x402DF) = "0"
#DMAACK3: HSDMA Ch. 3 acknowledge output when CFEX6(D6/0x402DF) = "1"
P07
#SRDY1
#DMAEND3
9I/O – P07: I/O port when CFP07(D7/0x402D0) = "0" and CFEX7(D7/0x402DF) = "0"
(default)
#SRDY1: Serial I/F Ch. 1 ready signal output when CFP07(D7/0x402D0) = "1" and
CFEX5(D5/0x402DF) = "0"
#DMAEND3: HSDMA Ch. 3 end-of-transfer signal output when
CFEX7(D7/0x402DF) = "1"
P10
EXCL0
T8UF0
DST0
122 I/O – P10: I/O port when CFP10(D0/0x402D4) = "0" and CFEX1(D1/0x402DF) = "0"
EXCL0: 16-bit timer 0 event counter input when CFP10(D0/0x402D4) = "1",
IOC10(D0/0x402D6) = "0" and CFEX1(D1/0x402DF) = "0"
T8UF0: 8-bit timer 0 output when CFP10(D0/0x402D4) = "1", IOC10(D0/0x402D6)
= "1" and CFEX1(D1/0x402DF) = "0"
DST0:DST0 signal output when CFEX1(D1/0x402DF) = "1" (default)
I OUTLINE: LIST OF PINS
S1C33L03 FUNCTION PART EPSON B-I-3-5
A-1
B-I
Pin
Pin name Pin No. I/O Pull-up Function
P11
EXCL1
T8UF1
DST1
121 I/O – P11: I/O port when CFP11(D1/0x402D4) = "0" and CFEX1(D1/0x402DF) = "0"
EXCL1: 16-bit timer 1 event counter input when CFP11(D1/0x402D4) = "1",
IOC11(D1/0x402D6) = "0" and CFEX1(D1/0x402DF) = "0"
T8UF1: 8-bit timer 1 output when CFP11(D1/0x402D4) = "1", IOC11(D1/0x402D6)
= "1" and CFEX1(D1/0x402DF) = "0"
DST1:DST1 signal output when CFEX1(D1/0x402DF) = "1" (default)
P12
EXCL2
T8UF2
DST2
120 I/O – P12: I/O port when CFP12(D2/0x402D4) = "0" and CFEX0(D0/0x402DF) = "0"
EXCL2: 16-bit timer 2 event counter input when CFP12(D2/0x402D4) = "1",
IOC12(D2/0x402D6) = "0" and CFEX0(D0/0x402DF) = "0"
T8UF2: 8-bit timer 2 output when CFP12(D2/0x402D4) = "1", IOC12(D2/0x402D6)
= "1" and CFEX0(D0/0x402DF) = "0"
DST2:DST2 signal output when CFEX0(D0/0x402DF) = "1" (default)
P13
EXCL3
T8UF3
DPCO
119 I/O – P13: I/O port when CFP13(D3/0x402D4) = "0" and CFEX1(D1/0x402DF) = "0"
EXCL3: 16-bit timer 3 event counter input when CFP13(D3/0x402D4) = "1",
IOC13(D3/0x402D6) = "0" and CFEX1(D1/0x402DF) = "0"
T8UF3: 8-bit timer 3 output when CFP13(D3/0x402D4) = "1", IOC13(D3/0x402D6)
= "1" and CFEX1(D1/0x402DF) = "0"
DPCO:DPCO signal output when CFEX1(D1/0x402DF) = "1" (default)
P14
FOSC1
DCLK
118 I/O – P14: I/O port when CFP14(D4/0x402D4) = "0" and CFEX0(D0/0x402DF) = "0"
FOSC1: OSC1 clock output when CFP14(D4/0x402D4) = "1" and
CFEX0(D0/0x402DF) = "0"
DCLK: DCLK signal output when CFEX0(D0/0x402DF) = "1" (default)
P15
EXCL4
#DMAEND0
#SCLK3
LDQM
84 I/O – P15: I/O port when CFP15(D5/0x402D4) = "0" and SDRENA(D7/0x39FFC1)
= "0" (default)
EXCL4: 16-bit timer 4 event counter input when CFP15(D5/0x402D4) = "1",
IOC15(D5/0x402D6) = "0" and SDRENA(D7/0x39FFC1) = "0"
#DMAEND0: HSDMA Ch. 0 end-of-transfer signal output when CFP15(D5/0x402D4)
= "1", IOC15(D5/0x402D6) = "1" and SDRENA(D7/0x39FFC1) = "0"
#SCLK3: Serial I/F Ch. 3 clock input/output when SSCLK3(D2/0x402D7) = "1",
CFP15(D5/0x402D4) = "0" and SDRENA(D7/0x39FFC1) = "0"
LDQM: SDRAM data (low byte) input/output mask signal when
SDRENA(D7/0x39FFC1) = "1"
P16
EXCL5
#DMAEND1
SOUT3
83 I/O – P16: I/O port when CFP16(D6/0x402D4) = "0" (default)
EXCL5: 16-bit timer 5 event counter input when CFP16(D6/0x402D4) = "1" and
IOC16(D6/0x402D6) = "0"
#DMAEND1: HSDMA Ch. 1 end-of-transfer signal output when CFP16(D6/0x402D4) =
"1" and IOC16(D6/0x402D6) = "1"
SOUT3: Serial I/F Ch. 3 data output when SSOUT3(D1/0x402D7) = "1" and
CFP16(D6/0x402D4) = "0"
P20
#DRD
SDCKE
80 I/O – P20: I/O port when CFP20(D0/0x402D8) = "0" and SDRENA(D7/0x39FFC1)
= "0" (default)
#DRD: DRAM read signal output for successive RAS mode when
CFP20(D0/0x402D8) = "1" and SDRENA(D7/0x39FFC1) = "0"
SDCKE: SDRAM clock enable signal when SDRENA(D7/0x39FFC1) = "1"
P21
#DWE
#GAAS
#SDWE
79 I/O – P21: I/O port when CFP21(D1/0x402D8) = "0", CFEX2(D2/0x402DF) = "0" and
SDRENA(D7/0x39FFC1) = "0" (default)
#DWE: DRAM write signal output for successive RAS mode when
CFP21(D1/0x402D8) = "1", CFEX2(D2/0x402DF) = "0" and
SDRENA(D7/0x39FFC1) = "0"
#GAAS: Area address strobe output for GA when CFEX2(D2/0x402DF) = "1" and
SDRENA(D7/0x39FFC1) = "0"
#SDWE: SDRAM write signal when SDRENA(D7/0x39FFC1) = "1"
P22
TM0 1I/O – P22: I/O port when CFP22(D2/0x402D8) = "0" (default)
TM0: 16-bit timer 0 output when CFP22(D2/0x402D8) = "1"
P23
TM1 2I/O – P23: I/O port when CFP23(D3/0x402D8) = "0" (default)
TM1: 16-bit timer 1 output when CFP23(D3/0x402D8) = "1"
P24
TM2
#SRDY2
4I/O – P24: I/O port when CFP24(D4/0x402D8) = "0" (default)
TM2: 16-bit timer 2 output when CFP24(D4/0x402D8) = "1"
#SRDY2: Serial I/F Ch. 2 ready signal input/output when SSRDY2(D3/0x402DB) = "1"
and CFP24(D4/0x402D8) = "0"
P25
TM3
#SCLK2
5I/O – P25: I/O port when CFP25(D5/0x402D8) = "0" (default)
TM3: 16-bit timer 3 output when CFP25(D5/0x402D8) = "1"
#SCLK2: Serial I/F Ch. 2 clock input/output when SSCLK2(D2/0x402DB) = "1" and
CFP25(D5/0x402D8) = "0"
I OUTLINE: LIST OF PINS
B-I-3-6 EPSON S1C33L03 FUNCTION PART
Pin name Pin No. I/O Pull-up Function
P26
TM4
SOUT2
6I/O – P26: I/O port when CFP26(D6/0x402D8) = "0" (default)
TM4: 16-bit timer 4 output when CFP26(D6/0x402D8) = "1"
SOUT2: Serial I/F Ch. 2 data output when SSOUT2(D1/0x402DB) = "1" and
CFP26(D6/0x402D8) = "0"
P27
TM5
SIN2
7I/O – P27: I/O port when CFP27(D7/0x402D8) = "0" (default)
TM5: 16-bit timer 5 output when CFP27(D7/0x402D8) = "1"
SIN2:Serial I/F Ch. 2 data input when SSIN2(D0/0x402DB) = "1" and
CFP27(D7/0x402D8) = "0"
P30
#WAIT
#CE4&5
75 I/O – P30: I/O port when CFP30(D0/0x402DC) = "0" (default)
#WAIT: Wait cycle request input when CFP30(D0/0x402DC) = "1"
#CE4&5: Areas 4&5 chip enable when CFP30(D0/0x402DC) = "1" and
IOC30(D0/0x402DE) = "1"
P31
#BUSGET
#GARD
GPIO2
74 I/O – P31: I/O port when CFP31(D1/0x402DC) = "0" and CFEX3(D3/0x402DF) = "0"
(default)
#BUSGET: Bus status monitor signal output for bus release request when
CFP31(D1/0x402DC) = "1" and CFEX3(D3/0x402DF) = "0"
#GARD: Area read signal output for GA when CFEX3(D3/0x402DF) = "1"
GPIO2: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and
BREQEN(D2/0x39FFFD) = "0"
P32
#DMAACK0
#SRDY3
HDQM
73 I/O – P32: I/O port when CFP32(D2/0x402DC) = "0" and SDRENA(D7/0x39FFC1)
= "0" (default)
#DMAACK0: HSDMA Ch. 0 acknowledge output when CFP32(D2/0x402DC) = "1" and
SDRENA(D7/0x39FFC1) = "0"
#SRDY3: Serial I/F Ch. 3 ready signal input/output when SSRDY3(D3/0x402D7) =
"1", CFP32(D2/0x402DC) = "0" and SDRENA(D7/0x39FFC1) = "0"
HDQM: SDRAM data (high byte) input/output mask signal when
SDRENA(D7/0x39FFC1) = "1"
P33
#DMAACK1
SIN3
SDA10
72 I/O – P33: I/O port when CFP33(D3/0x402DC) = "0" and SDRENA(D7/0x39FFC1)
= "0" (default)
#DMAACK1: HSDMA Ch. 1 acknowledge output when CFP33(D3/0x402DC) = "1" and
SDRENA(D7/0x39FFC1) = "0"
SIN3:Serial I/F Ch. 3 data input when SSIN3(D0/0x402D7) = "1",
CFP33(D3/0x402DC) = "0" and SDRENA(D7/0x39FFC1) = "0"
SDA10: SDRAM address bus bit 10 when SDRENA(D7/0x39FFC1) = "1"
P34
#BUSREQ
#CE6
GPIO0
71 I/O – P34: I/O port when CFP34(D4/0x402DC) = "0" (default)
#BUSREQ: Bus release request input when CFP34(D4/0x402DC) = "1"
#CE6: Area 6 chip enable when CFP34(D4/0x402DC) = "1" and
IOC34(D4/0x402DE) = "1"
GPIO0: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and
BREQEN(D2/0x39FFFD) = "0"
P35
#BUSACK
GPIO1
70 I/O – P35: I/O port when CFP35(D5/0x402DC) = "0" (default)
#BUSACK: Bus acknowledge output when CFP35(D5/0x402DC) = "1" and
CFP34(D4/0x402DC) = "1"
GPIO1: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and
BREQEN(D2/0x39FFFD) = "0"
I OUTLINE: LIST OF PINS
S1C33L03 FUNCTION PART EPSON B-I-3-7
A-1
B-I
Pin
Table 3.4 List of Pins for LCD Controller
Pin name Pin No. I/O Pull-up Function
FPDAT[7:4] 13–16 O – 4 high-order bits of data bus for 8-bit LCD panels
Data bus for 4-bit LCD panels
FPDAT[3:0]
GPO[6:3] 17–20 O – FPDAT[3:0]: 4 low-order bits of data bus for 8-bit LCD panels
GPO[6:3]: General-purpose outputs when a 4-bit LCD panel is used
FPFRAME 23 O – Frame pulse output
FPLINE 24 O – Line pulse output
FPSHIFT 25 O – Shift clock output
DRDY(MOD)
(FPSHIFT2) 22 O – MOD: LCD backplane bias (for panels other than 8-bit color panel format 1)
FPSHIFT2: Second shift clock (for 8-bit color panel format 1)
LCDPWR 26 O – LCD power control output (active high)
Table 3.5 List of Pins for Clock Generator
Pin name Pin No. I/O Pull-up Function
OSC1 68 I – Low-speed (OSC1) oscillation input (32 kHz crystal oscillator or external clock input)
OSC2 67 O – Low-speed (OSC1) oscillation output
OSC3 129 I – High-speed (OSC3) oscillation input (crystal/ceramic oscillator or external clock input)
OSC4 128 O – High-speed (OSC3) oscillation output
PLLS[1:0] 112,113 I – PLL set-up pins
PLLS1 PLLS0 fin (fOSC3)fout (fPSCIN)
1110–25MHz 20–50MHz
0110–12.5MHz 40–50MHz
00PLL is not used L
PLLC 115 – – Capacitor connecting pin for PLL
Table 3.6 List of Other Pins
Pin name Pin No. I/O Pull-up
/down Function
ICEMD 125 I Pull-
down High-impedance control input pin
When this pin is set to High, all the output pins go into high-impedance state. This makes
it possible to disable the S1C33 chip on the board.
DSIO 117 I/O Pull-up Serial I/O pin for debugging
This pin is used to communicate with the debugging tool S5U1C33000H.
#X2SPD 140 I – Clock doubling mode set-up pin
1: CPU clock = bus clock × 1, 0: CPU clock = bus clock × 2
#NMI 130 I Pull-up NMI request input pin
#RESET 69 I Pull-up Initial reset input pin
Note: "#" in the pin names indicates that the signal is low active.
I OUTLINE: LIST OF PINS
B-I-3-8 EPSON S1C33L03 FUNCTION PART
TH IS PAGE IS BLANK.
S1C33L03 FUNCTION PART
II CORE BLOCK
II CORE BLOCK: INTRODUCTION
S1C33L03 FUNCTION PART EPSON B-II-1-1
A-1
B-II
Intro
II-1 INTRODUCTION
The core block cons ists of a func ti o na l bl oc k C 33_C O RE in cluding CPU, BCU (Bus Control Unit), ITC
(Interrupt Controller), CLG (Clock Generator) and DBG (Debug Unit), an I/O pad block for external interface, and
an SBUS (Internal Silicon Integration Bus) for interfacing with on-chip Peripheral Macro Cells.
CORE_PAD
Pads
C33_SBUS
C33 Core Block
C33 LCD Controller Block
Pads
PERI_PAD
Pads
C33_PERI
(Prescaler, 8-bit timer, 16-bit timer,
Clock timer, Serial interface, Ports)
C33 Peripheral BlockC33 Analog Block
C33_CORE
(CPU, BCU, ITC, CLG, DBG)
C33_ADC
(A/D converter)
C33 Internal Memory Block
Internal RAM
(Area 0)
Internal ROM
(Area 10)
C33 DMA Block
C33_DMA
(IDMA, HSDMA)
C33_SDRAMC
(SDRAM interface)
C33_LCDC
(LCD panel interface)
C33 SDRAM Controller Block
Figure 1. 1 Core Block
Note: In te rn al RO M is not prov ided in the S 1C33L03 .
II CORE BLOCK: INTRODUCTION
B-II-1-2 EPSON S1C33L03 FUNCTION PART
TH IS PAGE IS BLANK.
II CORE BLOCK: CPU AND OPERA TING MODE
S1C33L03 FUNCTION PART EPSON B-II-2-1
A-1
B-II
CPU
II-2 CPU AND OPERATING MODE
CPU
The C33 Co re Block employs the S1C33000 32-bit RISC type CPU as the cor e CPU. Since it has a built- in
multiplier, all instructions (105 instructions) in the S1C33000 instruction set including the MAC (multiplication
and ac cu m ula tion ) instr uc tio n an d th e mul tip lic ation /d ivisio n in struc tio ns ar e avai lab le .
All the internal registers of the S1C33000 can be used. The CPU registers and CPU address bus can handle 28-bit
addresses. However, the core block has a 24-bit external address bus (A[0:23]), so the low-order 24 bits of address
data can only be delivere d to the external address bus and the internal address bus which is connected to the User
Logic Block.
Refer to the "S1C33000 Core CPU Manual" for details of the S1C33000.
II CORE BLOCK: CPU AND OPERA TING MODE
B-II-2-2 EPSON S1C33L03 FUNCTION PART
Standby Mode
The CPU supports three standby modes: two HALT modes and a SLEEP mode.
By setting the CPU in the standby mode, power consump t io n ca n great ly be redu ced.
HALT Mode
When the CPU executes the halt instruction, it suspends the program execution and enters the HALT mode.
The CPU supports two types of HALT modes (basic HALT mode and HALT2 mode) and either can be selected
using the HLT2OP (D3) / Clock option register (0x40190).
The CPU s tops operating in ba sic HALT mode, s o the amou nt of current consumption can b e redu ced. T he internal
peripheral circuits maintain t he status (stop/run) before entering HA LT m ode . The DMA function canno t be used.
HA LT2 mode sto ps the external bus control functions including DMA and the bus clock as well as the CPU similar
to basic HALT mo de. Consequently, HALT2 mode realizes more po w er saving than the basic HA LT m ode .
The HALT mo de is canceled by an initial reset or an interrupt including NMI. This mode is useful for saving
power when waiting for an e xternal input or completion of the peripheral circuit operations that do not need to
execute the CPU.
The CPU transits to program execution status through trap processing when the HALT mode is canceled by an
interrupt and executes the interrupt processing routine. The trap processing of the CPU saves the address of the
instruction that follows the executed halt instruction into the stack. Therefore, when the interrupt processing
routine is terminated by the reti instruction, the program flow returns to the instruction that follows the halt
instruction.
Note that the HALT mode cannot be canceled with an interrupt factor except for reset and NMI if the PSR is set
into inte rru pt d isa ble d statu s.
SLEEP Mode
When the CPU executes the slp instruction, it suspends the program execution and enters SLEEP mode.
In SLEEP mode, the CPU and the internal peripheral circuits including the high-speed (OSC3) oscillation circuit
stop operating. Thus SLEEP mode can greatly reduce current consumption in comparison to HALT mode.
Moreover, t he low-speed (OSC1) oscillation circuit and clock timer do not stop operating. The clock function
keeps operating in SLEEP mode.
SL EEP mo de is canceled by an initial reset or an interrupt (NMI, clock timer interrupt, external interrupt such as a
key entry). Note that other interrupts by the internal peripheral circuits that use the OSC3 clock cannot be used for
canceling SLEEP mode.
The CPU transits to program execution status through trap processing when the SLEEP mode is canceled by an
interrupt and executes the interrupt processing routine. The trap processing of the CPU saves the address of the
instruction that follows the executed slp instruction into the stack. Therefore, when the interrupt processing routine
is terminated by the reti instruction, the program flow returns to the instruction that follows the slp instruction.
Note tha t SLEEP m ode cannot be canceled with an interrupt factor except for reset and NMI if the PSR is set into
inte rrupt d isa ble d statu s.
II CORE BLOCK: CPU AND OPERA TING MODE
S1C33L03 FUNCTION PART EPSON B-II-2-3
A-1
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CPU
Notes on Standby Mode
Interrupts
The standby mode can be canceled by an interrupt. Therefore, it is necessary to enable the interrupt to be used
for canceling the standby mode before setting the CPU in the standby mode. It is also necessary to set the IE
(interrupt enable) and IL (interrupt level) bits in the PSR to a condition that can accept the interrupt.
Otherwise, the standby mode cannot be canceled even when an interrupt occurs. Refer to "ITC (Interrupt
Controller)", for interrupt settings.
Oscillation circuit
The high-speed (OSC3) oscillat ion circui t stops in SLEEP mode and restarts oscillating when SLEEP mode is
canceled. If the CPU had operated with the OSC3 clock before entering SLEEP mode, the CPU restarts
operating with the OSC3 clock immediately after canceling SLEEP mode. However, the OSC3 oscillation
needs appropriate stabilization time (10 ms max. under the standard condition in 3.3 V). To restart the CPU
after the oscillation stabilizes, a programmable interval can be inserted between cancellation of SLEEP mode
and starting the CPU operation. Refer to "CLG (Clock Generator)", for details.
The osc illation start time of the high-speed (OSC3) oscillation circuit varies according to the components to
be used, board pattern and operating environmen t. T he interval must be set to allow enough margin.
BCUWhen the CPU enters the standby mode, the BCU (bus control unit) stops after the current bus cycle has
completed. All the chip enable signals are negated.
In basic HALT mode, the BCLK (bus clock) signal is output and DRAM refresh cycles are generated. DMA
also operates.
In HALT2 or SLEEP mode, the BCLK signal stops, therefore DRAM refresh cycles cannot be generated and
DMA stops.
Additional
The con tents of the CPU registers and input/output port status are retained in the standby mode. Almost all
control and data registers of the internal peripheral circuits are also retained, note, however, some registers
may be changed at the transition to SLEEP mode. Refer to the section of each peripheral circuit for other
precautions.
Test Mode
The C33 Co re Block has the ICEM D pin for tes ting the chip. When this pin is set to High, the IC enters the
following state:
•All output pins go into high-impedance state except for the clock output pins (OSC2: H, OSC4 H, PLLC: L).
•Clock inputs are disabled. OSC1, OSC3 and PLL stop operating. OSC2: H, OSC4 H, PL LC: L
•All the pull-up and pull-down resistors enter an inactive state.
Leave this pin open or connect to VSS for normal operation. The ICEMD pin h as a bui lt-in pull-down resistor.
Debug Mo de
The C33 Core Block suppor ts t h e debu g m ode.
The deb ug mode is a CPU function, and realizes single step operation and break functions in the chip itself. Refer
to the "S1C33000 Core CPU Manual" for details of the debug mode and the functions.
Area 2 in the memory map can only be accessed in the debug mode.
In the debug mode, the OSC3 clock is used as the CPU operating clock. Therefore, do not stop the high-speed
(OSC3) oscillation circuit when using the debugging functions. Furthermore, only the CPU and BCU operate in the
debug mode, and other internal peripheral circuits (except the oscillation circuit) stop operating.
II CORE BLOCK: CPU AND OPERA TING MODE
B-II-2-4 EPSON S1C33L03 FUNCTION PART
Trap Table
Table 2.1 shows the trap table in the C33 Core. Refer to the "S1C33000 Core CPU Manual" for details of
exceptions and Section II-5 in this manual, "ITC (Interrupt Controller)", for interrupts.
Serial interface Ch.2 and Ch.3 interrupts share the trap table for port input interrupts and 16-bit timer interrupts.
Refer to Section III-8, "Serial Interface", for details of the settings.
Table 2.1 Trap Table
HEX
No. Vector number
(Hex address) Exception/interrupt name Exception/interrupt factor IDMA
Ch. Priority
00(Base) Reset Low input to the reset pin – High
1–3 reserved – – ↑
44(Base+10) Zero division Division instruction –
55 reserved – –
66(Base+18) Address error exception Memory access instruction –
70x0 or 0x60000 Debugging exception brk instruction, etc. –
88(Base+1C) NMI Low input to the NMI pin –
9–11 reserved – –
C12(Base+30) Software exception 0 int instruction –
D13(Base+34) Software exception 1 int instruction –
E14(Base+38) Software exception 2 int instruction –
F15(Base+3C) Software exception 3 int instruction –
10 16(Base+40) Port input interrupt 0 Edge (rising or falling) or level (High or Low) 1
11 17(Base+44) Port input interrupt 1 Edge (rising or falling) or level (High or Low) 2
12 18(Base+48) Port input interrupt 2 Edge (rising or falling) or level (High or Low) 3
13 19(Base+4C) Port input interrupt 3 Edge (rising or falling) or level (High or Low) 4
14 20(Base+50) Key input interrupt 0 Rising or falling edge –
15 21(Base+54) Key input interrupt 1 Rising or falling edge –
16 22(Base+58) High-speed DMA Ch.0 High-speed DMA Ch.0, end of transfer 5
17 23(Base+5C) High-speed DMA Ch.1 High-speed DMA Ch.1, end of transfer 6
18 24(Base+60) High-speed DMA Ch.2 High-speed DMA Ch.2, end of transfer –
19 25(Base+64) High-speed DMA Ch.3 High-speed DMA Ch.3, end of transfer –
1A 26(Base+68) IDMA Intelligent DMA, end of transfer –
27–29 reserved – –
1E 30(Base+78) 16-bit programmable timer 0 Timer 0 comparison B 7
1F 31(Base+7C) Timer 0 comparison A 8
32–33 reserved – –
22 34(Base+88) 16-bit programmable timer 1 Timer 1 comparison B 9
23 35(Base+8C) Timer 1 comparison A 10
36–37 reserved – –
26 38(Base+98) 16-bit programmable timer 2 Timer 2 comparison B 11
27 39(Base+9C) Timer 2 comparison A 12
40–41 reserved – –
2A 42(Base+A8) 16-bit programmable timer 3 Timer 3 comparison B 13
2B 43(Base+AC) Timer 3 comparison A 14
44–45 reserved – –
2E 46(Base+B8) 16-bit programmable timer 4 Timer 4 comparison B 15
2F 47(Base+BC) Timer 4 comparison A 16
48–49 reserved – –
32 50(Base+C8) 16-bit programmable timer 5 Timer 5 comparison B 17
33 51(Base+CC) Timer 5 comparison A 18
34 52(Base+D0) 8-bit programmable timer Timer 0 underflow 19
35 53(Base+D4) Timer 1 underflow 20
36 54(Base+D8) Timer 2 underflow 21 ↓
37 55(Base+DC) Timer 3 underflow 22 Low
II CORE BLOCK: CPU AND OPERA TING MODE
S1C33L03 FUNCTION PART EPSON B-II-2-5
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CPU
HEX
No. Vector number
(Hex address) Exception/interrupt name Exception/interrupt factor IDMA
Ch. Priority
38 56(Base+E0) Serial interface Ch.0 Receive error – High
39 57(Base+E4) Receive buffer full 23 ↑
3A 58(Base+E8) Transmit buffer empty 24
59 reserved – –
3C 60(Base+F0) Serial interface Ch.1 Receive error –
3D 61(Base+F4) Receive buffer full 25
3E 62(Base+F8) Transmit buffer empty 26
63 reserved – –
40 64(Base+100) A/D converter A/D converter, end of conversion 27
41 65(Base+104) Clock timer Falling edge of 32 Hz, 8 Hz, 2 Hz or 1 Hz signal
1-minuet, 1-hour or specified time count up –
66–67 reserved – –
44 68(Base+110) Port input interrupt 4 Edge (rising or falling) or level (High or Low) 28
45 69(Base+114) Port input interrupt 5 Edge (rising or falling) or level (High or Low) 29
46 70(Base+118) Port input interrupt 6 Edge (rising or falling) or level (High or Low) 30 ↓
47 71(Base+11C) Port input interrupt 7 Edge (rising or falling) or level (High or Low) 31 Low
∗ Base = Set value in the TTBR register (0x48134 to 0x48137); 0xC00000 by default.
II CORE BLOCK: CPU AND OPERA TING MODE
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II CORE BLOCK: INITIAL RESET
S1C33L03 FUNCTION PART EPSON B-II-3-1
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Reset
II-3 INITIAL RES ET
Pins for Initial Reset
Table 3.1 shows the pins used for initial reset.
Table 3.1 Pins for Initial Reset
Pin name I/O Function
#RESET I Initial reset input pin (Low active)
Low: Resets the CPU.
#NMI I NMI request input pin
This pin is also used for selecting a reset method.
High: Cold start
Low: Hot start
The chip is reset when the #RESET pin goes low and starts operating at the rising edge of the reset signal. The
CPU and internal peripheral circuits are initialized while the #RESET pin is low.
Cold Start and Hot Start
The CPU supports two initial reset methods: cold start and hot start. The #NMI pin is used with the #RESET pin to
set this condition.
The differences between cold start and hot start are shown in Table 3.2.
Table 3.2 Differences between Cold Start and Hot Start
Setup contents Cold start Hot start
Reset condition #RESET = low & #NMI = high #RESET = low & #NMI = low
CPU: PC The vector a t the boot address is loaded to the PC.
CPU: PSR All the PSR bits are reset to 0.
CPU: Other registers Undefined
CPU: Op erating clock The CPU operates with the OSC3 clock.
External bus status (0x48120–0x4813F) Initialized Status is retained.
Oscillation circuit Both the OSC1 and OSC3 circuits start oscillating.
I/O pin status (0x402C0–0x402DF) Initialized Status is retained.
Other peripheral circuit Initialized or undefined
Since cold start initializes all the internal peripheral circuits as well as the CPU, it is useful as a power-on reset.
Hot start i n itializes the CPU and peripheral circuits, but does not reset the bus control unit and the input, output and
I/O port status. It is therefore useful as a reset that maintains the external bus and I/O pin status during operation.
The #NMI pin that specifies the reset method should be set following the timing chart shown in Figure 3.1.
(1) Cold start (2) Hot start
#NMI
#RESET
Cold start is generated
(#RESET = low & #NMI = high)
#NMI must be set to high longer than
the reset pulse width.
#NMI
#RESET
Hot start is generated
(#RESET = low & #NMI = low)
#NMI must be set to low longer than
the reset pulse width.
Figure 3.1 Setup of #RESET and #NMI Pins
II CORE BLOCK: INITIAL RESET
B-II-3-2 EPSON S1C33L03 FUNCTION PART
Power-on Reset
Be sure to reset (cold start) the chip after turning on the power to start operating.
Since the #RESET pin is directly connected to an input gate, a power-on reset circuit should be configured outside
the chip.
An initial reset (#RESET = low) turns the high-speed (OSC3) oscillation circuit on. The CPU starts operating with
the OSC3 clock at the rising edge of the reset signal. The high-speed (OSC3) oscillation circuit takes time (10 ms
max. under the standard condition in 3.3 V) for the oscillation to stabilize, therefore initial reset must be released
after an appropriate oscillation-stabilization time has passed in order to start up the CPU without fault. The initial
reset pulse width must be exceeded the oscillation-stabilization time.
Figure 3.2 shows a power-on reset timing chart.
V
DD
#RESET
t
STA3
(OSC3 oscillation start time) or more
3.0 V (V
DD
= 3.3 V)
0.5V
DD
0.1V
DD
Power on
Figur e 3.2 Power-on Reset Timing
Maintain the #RESET pi n at 0.1•VDD or less (low level) after turning the power on until the supply voltage rises at
least to the oscillation start voltage (3.0 V). Furthermore, maintain the #RESET pin at 0.5•VDD or less until the
high-speed (OSC3) oscillation circuit stabilizes oscillating.
Note: The OSC3 oscillation start time varies due to the elements used, board pattern and operating
environmen t, therefo re all ow enough margin for the reset-release time. Refer to "Oscillation
Characteristics", in which an example of oscillation start time is provided.
Reset Pulse
A low pulse can be input to the #RESET pin for resetting the chip being operated.
The m inim um r eset pulse width is provided in "AC Characteristics". Be sure to input a pulse that has a pulse width
longer than the minimum value.
To reset the chip when the high-speed (OSC3) oscillation circuit is in off status, the pulse width must be extended
until the oscillation stabilizes similarly to the power-on reset. Be aware that a short reset pulse may cause an
operation error.
II CORE BLOCK: INITIAL RESET
S1C33L03 FUNCTION PART EPSON B-II-3-3
A-1
B-II
Reset
Boot Addr ess
When the core CPU is initially reset, it reads the reset vector (program start address) from the boot address
(0x0C00000) and loads the vector to the PC (program counter). Then the CPU starts executing the program from
the address when the #RESET pin goes high.
The trap table in which trap vectors for interrupts and other trap factors are written also begins from the boot
address by the default setting. (Refer to the "S1C33000 Core CPU Manual" for details of the trap table.)
The trap table base address can also be changed to a 1KB boundary address using the TTBR register (0x48134 to
0x48137).
Notes Related to Initial Reset
Core CPU
Since the all registers except for the PC and PSR are indeterminate at initial reset, they should be initialized
by a program. In pa rticular , the SP (stack pointer) must be initialized before accessing the stack area. NMI
requests are disabled until any value is written to the SP. The initialization is necessary when the CPU is
cold-started.
Internal RAM
The con tents of the internal RAM are indeterminate at initial reset. Initialize the area to be used if necessary.
High -speed (OSC3) oscilla tion circuit
An initial reset activates the high-speed (OSC3) oscillation circuit and the CPU starts operating with the
OSC3 clock after the initial reset is released. In order to prevent a malfunction of the CPU due to an
unstabilized clock, the #RESET pin must be maintained at low until the OSC3 oscillation stabilizes when
performing a power-on reset or resetting while the high-speed (OSC3) oscillation circuit is stopped.
Low-speed (OSC1) oscillation circuit
A powe r- on reset or an initial reset when the low-speed (OSC1) oscillation circuit is off starts the OSC1
oscillation. The low-speed (OSC1) oscillation circuit takes a longer stabilization time (3 sec max. under the
standard condition) than the high-speed (OSC3) oscillation circuit. In order to prevent a malfunction due to
an unstabilized clock, do not use the OSC1 clock until the stabilization time has passed.
BCU (Bus Cont r o l Unit)
Cold-start initializes the control registers for the BCU (bus control unit). Therefore, it is necessary to set up
all the bus conditions.
Hot-start ret ains the previous bus conditions before an initial reset.
Input/output ports and input/output pins
Cold start initializes the control and data registers for the input and I/O ports.
Hot start r etains the contents of the control registers and input/output pin status before an initial reset.
However, wh en the pi ns are used for the internal peripheral circuits, it is necessary to set up the control
registers of the peripheral circuit because they are initialized by an initial reset.
Other internal peripheral circuits
The con trol and data registers of peripheral circuits other than those listed above are initialized with the
predefined values or become indeterminate regardless of the reset method (cold start or hot start). Therefore,
it is necessary to set up the peripheral circuit conditions.
Refer to the I/O maps or explanation of each peripheral circuit section for initial settings of the peripheral
circuits.
II CORE BLOCK: INITIAL RESET
B-II-3-4 EPSON S1C33L03 FUNCTION PART
TH IS PAGE IS BLANK.
II CORE BLOCK: BCU (Bus Co ntrol Unit )
S1C33L03 FUNCTION PART EPSON B-II-4-1
A-1
B-II
BCU
II-4 BCU (Bus Control Unit)
The BCU (Bus Cont rol Unit) pr ovide s an interface for external devices and on-chip user logic block. The types
and sizes of memory and peripheral I/O devices can be set for each area of the memory map and can be controlled
direct ly by the BCU. This unit also supports a direct interface for DRAM and burst ROM. This chapter describes
how to control the external and internal system interface, and how it operates.
Note: The control r egisters of the external system interf ace sh own in this chapter are mapped to the
inte rn al 1 6-bit I/O area . Ther efore, the addresses of these control r egisters ar e indicated by half-
word (16-bit) addresses unless otherwise specified. Note that the control register s can be
access ed in bytes, half-words, or words.
Pin Assignment for External System Interface
I/O Pin List
External I/O pins
Table 4.1 lists t he pins used for the external system interface.
Table 4.1 I/O Pin List
Pin name I/O Function
A[0]/#BSL O Address bus (A0) / Bus strobe (Low-byte)
A[10:1]/SDA[9:0] OAddress bus (A1–A10) / SDRAM address bus (SDA0–SDA9)
A11 OAddress bus (A11)
A[13:12]/SDA[12:11] OAddress bus (A12–A13) / SDRAM address bus (SDA11–SDA12)
A[15:14]/SDBA[1:0] OAddress bus (A14–A15) / SDRAM bank select (SDBA0–SDBA1)
A[23:16] O Address bus (A16–A23)
D[15:0] I/O Data bus (D0–D15)
#CE10EX/#CE9&10EX O Area 10/(9&10) external memory chip enable
#CE9/#CE17/#CE17&18 O Area 9/17/(17&18) chip enable
#CE8/#RAS1/#CE14/#RAS3/#SDCE1 O Area 8/14 chip enable / DRAM Row strobe / SDRAM chip enable 1
#CE7/#RAS0/#CE13/#RAS2/#SDCE0 O Area 7/13 chip enable / DRAM Row strobe / SDRAM chip enable 0
#CE6/#CE7&8 O Area 6/(7&8) chip enable
#CE5/#CE15/#CE15&16 O Area 5/15/(15&16) chip enable
#CE4/#CE11/#CE11&12 O Area 4/11/(11&12) chip enable
#RD O Read signal
#EMEMRD O Read signal for area 3/10 emulation mode
#WRL/#WR/#WE O Write (Low-byte) / Write / DRAM write
#WRH/#BSH O Write (High-byte) / Bus strobe (High-byte)
#HCAS/#SDCAS O DRAM column address strobe (High-byte) / SDRAM column address strobe
#LCAS/#SDRAS O DRAM column address strobe (Low-byte) / SDRAM row address strobe
BCLK/SDCLK O Bus clock output / SDRAM operating clock
P35/#BUSACK/GPIO1 I/O I/O port / Bus request acknowledge / LCDC general-purpose input/output
P34/#BUSREQ/#CE6/GPIO0 I/O I/O port / Bus release request / Area 6 chip enable / LCDC general-purpose
input/output
P33/#DMAA CK1/SIN3/SDA10 I/O I/O port / HSDMA Ch. 1 acknowledge output / Serial I/F Ch. 3 data input /
SDRAM address bus 10
P32/#DMAACK0/#SRDY3/HDQM I/O I/O port / HSDMA Ch. 0 acknowledge output / Serial I/F Ch. 3 ready signal output /
SDRAM data (high byte) input/output mask signal output
P31/#BUSGET/#GARD/GPIO2 I/O I/O port / Bus status monitor signal output / Area read signal output for GA /
LCDC general-purpose input/output
P30/#WAIT/#CE4&5 I/O I/O port / Wait cycle request / Areas 4&5 chip enable
P21/#DWE/#GAAS/#SDWE I/O I/O port / DRAM write (Low-byte) / Area address strobe output for GA / SDRAM write
P20/#DRD/SDCKE I/O I/O port / DRAM read / SDRAM clock enable
P15/EXCL4/#DMAEND0/#SCLK3/LDQM I/O I/O port / 16-bit timer 4 event counter input / HSDMA Ch. 0 end-of-transfer signal
output / Serial I/F Ch. 3 clock input/output / SDRAM data (low byte) input/output mask
signal output
#X2SPD I CPU - BCLK clock ratio
1: CPU clock = Bus clock, 0: CPU clock = Bus clock x 2
EA10MD[1:0] I Area 10 boot mode selection
11: External ROM, 10: Internal ROM
II CORE BLOCK: BCU (Bus Co ntrol Unit )
B-II-4-2 EPSON S1C33L03 FUNCTION PART
User interface signals
Table 4.2 List of User Interface Signals
Signal name I/O Function
Internal_addr0 O•Address bus (a0) when SBUSST(D3/0x4812E) = "0" (default)
•Bus strobe (low byte) signal (#BSL) when SBUSST(D3/0x4812E) = "1"
Internal_addr[23:1] OAddress bus (a1 to a23)
Internal_dout[15:0] OOutput data bus (dout0 to dout15)
This data bus is used when the CPU writes data to the on-chip user logic.
Internal_din[15:0] IInput data bus (din0 to din15)
This data bus is used when the CPU reads data from the on-chip user logic.
Internal_ce4_x
Internal_ce5_x
Internal_ce6_x
OAreas 6–4 chip enable signals
These signals go low when the CPU accesses the user logic circuits that are mapped to Areas 6–4.
Internal_rd_x ORead signal
This signal goes low when the CPU reads data from the user logic.
Internal_wrl_x O•Write (low byte) signal (#WRL) when SBUSST(D3/0x4812E) = "0" (default)
•Write signal (#WR) when SBUSST(D3/0x4812E) = "1"
This signal goes low when the CPU write 8 low-order bit data to the user logic.
Internal_wrh_x O•Write (high byte) signal (#WRH) when SBUSST(D3/0x4812E) = "0" (default)
•Bus strobe (high byte) signal (#BSH) when SBUSST(D3/0x4812E) = "1"
This signal goes low when the CPU write 8 high-order bit data to the user logic.
Internal_osc3_clk OHigh-speed (OSC3) oscillation clock output
This can be used as a source clock for the user logic.
Internal_pll_clk OPLL output clock
This can be used as a source clock for the user logic.
Internal_wait_x IWait cycle request input
The user logic can request to insert wait cycles by setting this signal to low.
Internal_irrd_x OInstruction fetch indicator signal
This signal goes low when the CPU is in an instruction fetch cycle.
Internal_k60-k67 IInput signals
These signals are connected to the input ports K60–K67. The user logic can request HSDMA, IDMA and
interrupts using these signals. The user logic can also be used as input ports with these signals.
The internal bus signals are available when an internal access area is set using the BCU register.
The bus conditions can be programmed using the BCU registers similar to the external bus.
II CORE BLOCK: BCU (Bus Co ntrol Unit )
S1C33L03 FUNCTION PART EPSON B-II-4-3
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B-II
BCU
Combinatio n of System Bus Control Signals
The bus control signal pins that have two or more functions have their functionality determined when an interface
method is selected by a program. The BCU contains an ordinary external system interface (two interface method
ar e supp or te d) and a D RA M inte rface.
Table 4.3 Interface Selection
Interface type Interface method Control bit
External system interface A0 system (default) SBUSST(D3/0x4812E) = "0"
#BSL system SBUSST(D3/0x4812E) = "1"
DRAM i nterface 2CAS system (fixed) None
SB USST is initialized to "0" at cold start.
When the IC is hot-started, these bits retain their status before the chip was reset.
Table 4.4 shows c om binations of control signals classified by each interface method.
Table 4.4 Combinations of Bus Control Signals
External system interface DRAM interface
A0 system #BSL system 2CAS system
A0 #BSL (little endian) /
#BSH (big endian) ∗1–
#WRL #WR #WE
#WRH #BSH (little endian) /
#BSL (big endian) ∗1–
––#HCAS
––#LCAS
#CEx #CEx #RASx ∗2
∗1In the #BSL system, the A0 and #WRH pin functions change according to the endian selected (little endian
or big endian).
∗2 When using DRAM, the #CE ou tput pins in are as 7–8 (areas 13–14) function as t he #R A S1–2 (#RA S3–4 )
pins.
II CORE BLOCK: BCU (Bus Co ntrol Unit )
B-II-4-4 EPSON S1C33L03 FUNCTION PART
Me mo ry A re a
Me mo ry Map
Figure 4.1 shows the memory map supported by the BCU.
Internal RAM
Internal I/O
(Mirror of internal I/O)
(Mirror of internal I/O)
(Reserved)
For CPU core or debug mode
(Reserved)
For middleware use
0x0BFFFFF
0x0800000
0x07FFFFF
0x0600000
0x05FFFFF
0x0400000
0x03FFFFF
0x0380000
0x037FFFF
0x0300000
0x02FFFFF
0x0200000
0x01FFFFF
0x0100000
0x00FFFFF
0x0080000
0x007FFFF
0x0060000
0x005FFFF
0x0050000
0x004FFFF
0x0040000
0x003FFFF
0x0030000
0x002FFFF
0x0000000
Area
Area 9
SRAM type
Burst ROM type
8 or 16 bits
Area 8
SRAM type
DRAM type
8 or 16 bits
Area 7
SRAM type
DRAM type
8 or 16 bits
Area 6
SRAM type
Area 5
SRAM type
8 or 16 bits
Area 4
SRAM type
8 or 16 bits
Area 3
16 bits
Fixed at 1 cycle
Area 2
16 bits
Fixed at 3 cycles
Area 1
8, 16 bits
2 or 4 cycles
Area 0
32 bits
Fixed at 1 cycle
Address
External memory (1MB)
External memory (1MB)
External memory (2MB)
External memory (2MB)
External memory (4MB)
External memory (4MB)
External I/O (8-bit device)
External I/O (16-bit device)
0xFFFFFFF
0xD000000
0xCFFFFFF
0xC000000
0xBFFFFFF
0x9000000
0x8FFFFFF
0x8000000
0x7FFFFFF
0x7000000
0x6FFFFFF
0x6000000
0x5FFFFFF
0x5000000
0x4FFFFFF
0x4000000
0x3FFFFFF
0x3000000
0x2FFFFFF
0x2000000
0x1FFFFFF
0x1800000
0x17FFFFF
0x1000000
0x0FFFFFF
0x0C00000
Area
Area 18
SRAM type
8 or 16 bits
Area 17
SRAM type
8 or 16 bits
Area 16
SRAM type
8 or 16 bits
Area 15
SRAM type
8 or 16 bits
Area 14
SRAM type
DRAM type
8 or 16 bits
Area 13
SRAM type
DRAM type
8 or 16 bits
Area 12
SRAM type
8 or 16 bits
Area 11
SRAM type
8 or 16 bits
Area 10
SRAM type
Burst ROM type
8 or 16 bits
Address
External memory (8MB)
External memory (8MB)
External memory (16MB)
External memory (16MB)
External memory (16MB)
External memory (16MB)
External memory (16MB)
External memory (16MB)
Figur e 4.1 Memory Map
Basically, Areas 0 to 3 are internal memory areas and Areas 4 to 18 are external memory areas.
Area 0 is nor m ally used for a built-in RAM. The built-in memory is mapped from the beginning of the area.
Area 1 is reserved for the I/O memory of the on-chip functional blocks. Address 0x0040 000 to add ress 0x004FFF F
are used as the control registers and address 0x0050000 to 0x005FFFF are used as the mirror area.
Area 2 is use d in debug mo de only and it cannot be accessed in user mode (normal program execution status).
Area 3 is reserved for S1C33 middlewares.
Area 4 to 18 can also be configured as internal memory areas using the control register and they can be used for
user logic circuits.
Note: Addresses 0x39FFC 0–0x39FFCD in Ar ea 6 are reserved as the internal me m ory area for the
control I/O mem ory of t he SDRAM controller. Pay attent ion to t h is area sin ce it must be acce ssed
when controll ing the SDRAM self- refr esh mode or ot her SDRAM funct ions.
II CORE BLOCK: BCU (Bus Co ntrol Unit )
S1C33L03 FUNCTION PART EPSON B-II-4-5
A-1
B-II
BCU
External Memory Map and Chip Enable
The BCU has a 24- bit external address bus (A[23:0]) and a 16-bit external data bus (D[15:0]), allowing an address
space of up to 16 MB to be accessed with one chip enable signal. By default, the address space is divided into 11
areas (areas 0 to 10) for management purposes. Of these, areas 4 to 10 are open to an external system, each
provided with an independent chip-enable pin (#CE[10:4]).
The C33 Co re Block is limit ed to 24 available pins f or the address bus and 7 pins for t he #CE output due to its
packa ge structure. Howe ver, the #CE[ 4:10] output pins can be sw itched to the high-order area chip enable output
pins as shown in Table 4.5 using softwar e. CEFU NC[ 1:0] (D[A:9]) / DRAM timing set-up register (0x48130) is
used for this switching.
Table 4.5 Switching of #CE Output
PinCEFUNC = "00" CEFUNC = "01" CEFUNC = "1x"
#CE4 #CE4 #CE11 #CE11+#CE12
#CE5 #CE5 #CE15 #CE15+#CE16
#CE6 #CE6 #CE6 #CE7+#CE8
#CE7/#RAS0 #CE7/#RAS0 #CE13/#RAS2 #CE13/#RAS2
#CE8/#RAS1 #CE8/#RAS1 #CE14/#RAS3 #CE14/#RAS3
#CE9 #CE9 #CE17 #CE17+#CE18
#CE10EX #CE10EX #CE10EX #CE9+#CE10EX
(Default: CEFUNC = "00")
The high-order areas that are made available for use by writing "01" to CEFUNC can be larger in size than the
default low-order areas. For example, when using DRAM in default settings, the available space is 4 MB in areas 7
and 8. However, if areas 13 and 14 are used, up to 32 MB of DRAM can be used. The same applies to the other
areas.
Furthermore, when CEFUNC is set to "10" or "11", five chip enable signals are expanded into two area size.
Althoug h the C3 3 Core Block has only 24 add ress output pins, it featur es 28 -bit internal address processing.
Figure 4.2 shows a memory map for an external system.
0x0FFFFFF
0x0C00000
0x0BFFFFF
0x0800000
0x07FFFFF
0x0600000
0x05FFFFF
0x0400000
0x03FFFFF
0x0380000
0x037FFFF
0x0300000
0x02FFFFF
0x0200000
0x01FFFFF
0x0100000
Area
Area 10
(#CE10)
SRAM type
Burst ROM type
8 or 16 bits
Area 9
(#CE9)
SRAM type
Burst ROM type
8 or 16 bits
Area 8
(#CE8/#RAS1)
SRAM type
DRAM type
8 or 16 bits
Area 7
(#CE7/#RAS0)
SRAM type
DRAM type
8 or 16 bits
Area 6
(#CE6)
SRAM type
Area 5
(#CE5)
SRAM type
8 or 16 bits
Area 4
(#CE4)
SRAM type
8 or 16 bits
Area
Area 17
(#CE17)
SRAM type
8 or 16 bits
Area 15
(#CE15)
SRAM type
8 or 16 bits
Area 14
(#CE14/#RAS3)
SRAM type
DRAM type
8 or 16 bits
Area 13
(#CE13/#RAS2)
SRAM type
DRAM type
8 or 16 bits
Area 11
(#CE11)
SRAM type
8 or 16 bits
Area 10
(#CE10)
SRAM type
Burst ROM type
8 or 16 bits
Area 6
(#CE6)
SRAM type
Address
External memory 1 (1MB)
External memory 2 (1MB)
External memory 3 (2MB)
External memory 4 (2MB)
External memory 5 (4MB)
External memory 6 (4MB)
External I/O (8-bit device)
External I/O (16-bit device)
0xBFFFFFF
0x9000000
0x8FFFFFF
0x8000000
0x5FFFFFF
0x5000000
0x4FFFFFF
0x4000000
0x3FFFFFF
0x3000000
0x2FFFFFF
0x2000000
0x17FFFFF
0x1000000
0x0FFFFFF
0x0C00000
0x03FFFFF
0x0380000
0x037FFFF
0x0300000
Address
External memory 3 (16MB)
External memory 4 (16MB)
External memory 5 (16MB)
External memory 6 (16MB)
(Mirror of External memory 6)
(Mirror of External memory 5)
External I/O (8-bit device)
External I/O (16-bit device)
External memory 1 (4MB)
External memory 2 (8MB)
CEFUNC = "00" CEFUNC = "01"
II CORE BLOCK: BCU (Bus Co ntrol Unit )
B-II-4-6 EPSON S1C33L03 FUNCTION PART
Area
Area 17–18
(#CE17+18)
SRAM type
8 or 16 bits
Areas 15–16
(#CE15+16)
SRAM type
8 or 16 bits
Area 14
(#CE14/#RAS3)
SRAM type
DRAM type
8 or 16 bits
Area 13
(#CE13/#RAS2)
SRAM type
DRAM type
8 or 16 bits
Areas 11–12
(#CE11+12)
SRAM type
8 or 16 bits
Areas 9–10
(#CE9+10EX)
SRAM type
Burst ROM type
8 or 16 bits
Areas 7–8
(#CE7+8)
SRAM type
8 or 16 bits
0xFFFFFFF
0xD000000
0xCFFFFFF
0xC000000
0xBFFFFFF
0x9000000
0x8FFFFFF
0x8000000
0x7FFFFFF
0x7000000
0x6FFFFFF
0x6000000
0x5FFFFFF
0x5000000
0x4FFFFFF
0x4000000
0x3FFFFFF
0x3000000
0x2FFFFFF
0x2000000
0x1FFFFFF
0x1000000
0x0FFFFFF
0x0800000
0x07FFFFF
0x0400000
Address
External memory 4 (16MB)
External memory 5 (16MB)
External memory 2 (8MB)
External memory 3 (16MB)
External memory 1 (4MB)
CEFUNC = "10" or "11"
External memory 7 (16MB)
External memory 7' (16MB)
(Mirror of External memory 7')
(Mirror of External memory 7)
External memory 6 (16MB)
External memory 6' (16MB)
(Mirror of External memory 6')
(Mirror of External memory 6)
Figur e 4.2 External System Memory Map
Furthermore, the #CE4+#CE5 and #CE6 signals can be output from the P30 and P34 terminals, respectively.
This fun ction expands the accessible area when CEFUNC is set to "01, "10" or "11".
To output the #CE4+#CE5 sig nal from the P30 terminal:
CFP30 (D 0)/P3 function select register (0x402DC) = "1"
IOC30 (D0)/P3 I/O control register (0x402DE) = "1"
To output the #CE6 signal from the P34 terminal:
CFP34 (D 4)/P3 function select register (0x402DC) = "1"
IOC34 (D4)/P3 I/O control register (0x402DE) = "1"
The P30 a nd P34 terminals are set for the general I/O ports at initial reset.
The P30 a nd P34 terminals are shared with the #WAIT input and the #BUSREQ input, respectively. Therefore,
when using the #WAIT and #BUSREQ signals, these terminals cannot be used for #CE4+#CE5 and #CE6 outputs.
II CORE BLOCK: BCU (Bus Co ntrol Unit )
S1C33L03 FUNCTION PART EPSON B-II-4-7
A-1
B-II
BCU
Using Internal Memory on External Memory Area
The BCU a ll ows using of an internal memory in the external memory areas.
The AxxIO bit in the access control register (0x48132) is used to select either internal access or external access.
When "1" is written, the internal device will be accessed and when "0" is written, the external device is accessed
(external access by default). The bit names and the corresponding areas are as follows:
A18IO (DF): Areas 17 and 18
A16I O (DE): Areas 15 and 16
A14I O (DD): Ar eas 13 and 14
A12I O (DC): Areas 11 and 12
A8IO (DA): Areas 7 and 8
A6IO (D9):Area 6
A5IO (D8):Areas 4 and 5
Exclu sive Sign als for Are as
Areas can be accessed using the exclusive signals (address strobe and read signals) as well as the common control
signals.
To use these exclusive signals, they should be configured using G/A read signal control register (0x48138).
The A xxAS bit is used to enable/disable the address strobe signal, and the AxxRD bit is used to enable/disable the
read signal. When "1" is written to the bit, the exclusive signal for the corresponding area(s) is enabled and when
"0" is written, it is disabled (disabled by default). The bit names and the corresponding areas are as follows:
A18AS (DF), A1 8RD (D7): Areas 17 and 18
A16AS (DE), A16RD (D6): Areas 15 and 16
A14AS (DD) , A14RD (D5): Areas 13 and 14
A12AS (DC) , A12RD (D4): Areas 11 and 12
A8AS (DA), A8RD ( D2): Are as 7 and 8
A6AS (D9), A6RD (D1): Area 6
A5AS (D8), A5RD (D0): Areas 4 and 5
#CE selected with AxxAS (ORed)
#WRH
#WRL
#RD
#CE selected with AxxRD (ORed)
#GAAS P21
#GARD P31
Figure 4.3 #GAAS and #GARD Signals
The add ress strobe signal and the read signal are output from the P21 pin and P31 pin, respectively. Therefore,
when using these signals, the pin(s) must be configured for exclusive signal output using the port function select
register and port function extension register.
To output the exclusive address strobe signal #GAAS:
CFEX2 (D2)/Port function extension register (0x402DF) = "1"
To output the exclusive address strobe signal #GARD:
CFEX3 (D3)/Port function extension register (0x402DF) = "1"
These signals are common used to all the above areas, so when two or more areas are selected to output the
exclusive signal, OR condition is applied.
II CORE BLOCK: BCU (Bus Co ntrol Unit )
B-II-4-8 EPSON S1C33L03 FUNCTION PART
Area 10
Area 10 is an external memory area that includes the boot address (0xC00000). This area supports two boot modes.
Note: In te rn al RO M is not prov ided in the S 1C33L03 .
Area 10 boot mode
The boot mode can be configured using the external pins EA10MD[1:0].
Table 4.6 Area 10 Boot Mode Selection
EA10MD[1:0] pins Area 10 boot mode
10 Internal ROM boot mode
11 External ROM boot mode
Internal ROM boot mode
The CPU boots by the i nternal ROM ma pped to area 10. The internal ROM size should be selected from
among eight types (min. 16 KB, ma x. 2 M B ) using the A 10IR[2:0] (D[E:C])/Areas 10–9 set-up register
(0x48126). This ROM begins with address 0xC00000 and can be read in one cycle the same as that of area 3.
For the remained area within area 10, the external memory will be accessed if it is available.
External ROM boot m ode
The CPU boots by the externa l RO M (ROM, Flash, SRAM , etc.). This mode uses the bus condition set by the
BCU regist ers for area 10.
Setting the internal ROM size
When a boot mode other t han external ROM boot m ode is used, the internal ROM or emulation memory siz e
should be set using A10IR[2:0 ] (D[E:C)/Areas 10–9 set-up register (0x48126).
Table 4.7 Area 10 Internal ROM Size
A10IR2 A10IR1 A10IR0 ROM size
000 16 KB
001 32 KB
010 64 KB
011 128 KB
100 256 KB
101 512 KB
110 1 MB
1112 MB (default)
II CORE BLOCK: BCU (Bus Co ntrol Unit )
S1C33L03 FUNCTION PART EPSON B-II-4-9
A-1
B-II
BCU
Area 10 memory map
Figure 4.4 show s the m emory map of area 10.
Area 10
External ROM boot mode
0x0C00000
0x0FFFFFF
External memory
is accessed.
Set-up example
25 MHz
5 wait
Area 10
Other modes
0x0C00000
0x0FFFFFF
External memory
is accessed.
Set-up example
25 MHz
5 wait
Internal or
emulation memory
is accessed.
Set-up example
25 MHz (#X2SPD = "1")
25 MHz (#X2SPD = "0")
No wait
16KB, 32KB, 64KB, 128KB
256KB, 512KB, 1MB or 2MB
selected by A10IR[2:0]
Figur e 4.4 Area 10 Memory Map
Area 3
Area 3 is reserved for S1C33 middleware. To use this area, external emulation memory is used.
When exte rnal emulation memory is used, A3EEN (DB/0x48 130) m ust be s et to " 1".
Table 4.8 Area 3 Mode Selection
A3EEN Area 3 mode
0Emulation mode
1Unused
II CORE BLOCK: BCU (Bus Co ntrol Unit )
B-II-4-10 EPSON S1C33L03 FUNCTION PART
Setting External Bus Conditions
The type, size, and wait conditions of a device connected to the external bus can be individually set for each area
using the control register (0x48120 to 0x48130). The following explains the available setup conditions individually
for each area. For details on how to set the DRAM interface conditions, refer to "DRAM Direct Interface".
The con trol register used to set bus conditions is initialized at cold start. Therefore, please set up these registers
again using software according to the external device configuration and specifications.
When the IC is hot-started, the setup contents and pins retain their previous status before a reset.
Setting Device Type and Size
Table 4.9 shows t he types of devices that can be connected directly to each area.
Table 4.9 Device Type
Area SRAM type DRAM type Burst ROM type Control bit
18–15 ●XX None
14 ● ● XA14DRA(D8)/Areas 14–13 set-up register(0x48122)
13 ● ● XA13DRA(D7)/Areas 14–13 set-up register(0x48122)
12,11 ●XX None
10 ●X●A10DRA(D8)/Areas 10–9 set-up register(0x48126)
9●X●A9DRA(D7)/Areas 10–9 set -up reg ist er (0x 48126 )
8● ● XA8DRA(D8)/Areas 8–7 set-up register(0x48128)
7● ● XA7DRA(D7)/Areas 8–7 set-up register(0x48128)
6–4 ●XX None
●: Can be connected X: Cannot be connected
When connecting burst ROM or DRAM, write "1" to each corresponding control bit. These control bits are reset to
"0" (SRAM type) at cold start.
The dev ice size can be set to 8 or 16 bit s once eve ry two areas except for area 6. Area 6 alone has its first half
(0x300000–0x37FFFF) fixed to an 8-bit device and the second half (0x380000–0x3FFFFF) fixed to a 16-bit
device.
Table 4.10 Device Size Control Bits
Area Control bit
18, 17 A18SZ(DE)/Areas 18–15 set-up register(0x48120)
16, 15 A16SZ(D6)/Areas 18–15 set-up register(0x48120)
14, 13 A14SZ(D6)/Areas 14–13 set-up register(0x48122)
12, 11 A12SZ(D6)/Areas 12–11 set-up register(0x48124)
10, 9 A 10 S Z(D 6)/ Areas 10–9 s et -up reg ist er (0x 48126)
8, 7 A8SZ(D6)/Areas 8–7 set-up register(0x48128)
5, 4 A5SZ(D6)/Areas 6–4 set-up register(0x4812A)
At c old start, each area by default is set to 16 bits.
When using an 8-bit device, wr ite "1" to the control bit.
Note: The BCU su pp ort s 16 -bi t bur st ROM. Ther efor e , when conn ecti ng bu r st ROM to are a 10 or ar ea 9,
do not set the device size to 8 bits (A10SZ = "1").
For differences in bus operation due to the device size and access data size, refer to "Bus Operation of External
Memory".
II CORE BLOCK: BCU (Bus Co ntrol Unit )
S1C33L03 FUNCTION PART EPSON B-II-4-11
A-1
B-II
BCU
Setting SRAM Timing Conditions
The areas set for the SRAM allow wait cycles and output disable delay time to be set.
Number of wait cycles: 0 to 7 (incremented in units of one cycle)
Output di sable delay tim e: 0.5, 1.5, 2.5, 3.5 cycles
This select ion can be ma de once every two areas except for area 6.
Table 4.11 Timing Condition Setting Bits (for SRAM type)
Area Number of wait cycles Output disable delay time Control register
18, 17 A18WT[2:0](D[A:8]) A18DF[1:0](D[D:C]) Areas 18–15 set-up register(0x48120)
16, 15 A16WT[2:0](D[2:0]) A16DF[1:0](D[5:4]) Areas 18–15 set-up register(0x48120)
14, 13 A14WT[2:0](D[2:0]) A14DF[1:0](D[5:4]) Areas 14–13 set-up register(0x48122)
12, 11 A12WT[2:0](D[2:0]) A12DF[1:0](D[5:4]) Areas 12–11 set-up register(0x48124)
10, 9 A10WT[2:0](D[2:0]) A10DF[1:0](D[5:4]) Areas 10–9 set-up register(0x48126)
8, 7 A8WT[2:0](D[2:0]) A8DF[1:0](D[5:4]) Areas 8–7 set-up register(0x48128)
6A6WT[2:0](D[A:8]) A6DF[1:0](D[D:C]) Areas 6–4 set-up register(0x4812A)
5, 4 A5WT[2:0](D[2:0]) A5DF[1:0](D[5:4]) Areas 6–4 set-up register(0x4812A)
At c old start, the number of wait cycles is set to 7 and the output disable delay time is set to 3.5 cycles. Reset up
these parameters as necessary using software according to specifications of the connected device.
At ho t start, these parameters retain their previous settings before a reset.
Wait cycles
When the number of wa it cycles is set for an area using the control bit, the BCU extends the bus cycle for a
duration equivalent to the wait cycles set when it accesses the area. Set the desired wait cycles according to
the bus clock frequency and the external device's access time. Separately from the wait cycles set here, a wait
request from an external device can also be accepted using the #WAIT pin. Since the settings of wait cycles
using software are m ade onc e every two areas, use this external wait request function if you want the wait
cycles to be controlled individually in each area or if you need 7 or more wait cycles. The #WAIT pin is
shared with the P30 I/O port. For an external wait request to be accepted, write "1" to CFP30 (D0) / P3
function select register (0x402DC [Byte]) and write "1" (default = "0") to SWAITE (D0) / Bus control
register (0x4812E) to enable the #WAIT pin.
For timing charts for bus cycles and when wait cycles are inserted, refer to "Bus Cycles in External System
Interface".
If the number of wait cycles is set to 0 and no external wait is requested, the basic read cycle (read in byte or
half-word) for the SRAM external device consists of one cycle. If wait cycles are set, because these cycles are
added, the bus read cycle consists of [number of wait cycles + 1] (providing that there is no external wait).
On the other hand, the bas ic write cycle consists of at least two cycles. This does not change regardless of
whether zero or one wait cycle is set. If the number of wait cycles set is 2 or more, the bus cycle is actually
extended. In this case, the bus write cycle consists of [number of wait cycles + 1], as in the case of read cycles
(providing that there is no external wait).
II CORE BLOCK: BCU (Bus Co ntrol Unit )
B-II-4-12 EPSON S1C33L03 FUNCTION PART
Output disable delay time
In cases when a device having a long output disable time is connected, if a read cycle for that device is
followed by the next access, contention for the data bus may occur. (Due to the fact the read device's data bus
is not placed in the high-impedance state.) The output disable delay time is provided to prevent such data bus
contention. This is accomplished by inserting a specified number of cycles between a read cycle and the next
bus ope ration. Care i s required with the #CE x signals, howeve r, since di fferent areas may be asserted
consecutively. There are gaps between command signals such as #RD and #WRL/#WRH.
Check the specifications of the device to be connected before setting the output disable delay time.
The out put disable delay time is inserted only in the following cases:
•when a read cycle from the external device that has had an output disable delay time set is followed by a
write cycle performed by the CPU; and
•when a read cycle from the external device that has had an output disable delay time set is followed by a
read cycle for a different area (including the internal device).
Conver sely, no output disable delay t ime is inserted in the following conditions:
•immediately after a write cycle, and
•during a successive read from the same external device.
Setting Timing Co nditions of Burst ROM
Wait cycles
If burst ROM is selected for area 10 or 9, the wait cycles to be inserted in the burst read cycle can be selected
in a range from 0 to 3 cycles. A10BW[1:0] (D[A:9]) / Areas 10–9 set-up register (0x48126) is used for this
selection. This selection is applied simultaneously to areas 10 and 9, so wait cycles can not be chosen
individually for each area. The wait cycles set at cold start is 0.
Even for a burst read, the SRAM settings of wait cycles in the first bus operation are valid. (Refer to
A10WT[2:0] in the foregoing section.)
The wait c ycles set by A10BW[1:0] are inserted into the burst cycles after the first bus operation.
In addition, when burst ROM is selected, no wait cycles can be inserted into the read cycle via the #WAIT
pin.
For writing to an area that has had burst ROM selected, an SRAM write cycle is executed. In this case, both
the SRAM settings of wait cycles and those input via the #WAIT pin are valid.
Burst mode
The bur st mo de can be selected be twe en an eight-co nsecutive-burst and a four-consecu tive-burst m ode .
RBST8 (DD) / Bus con tr ol register (0x4812E) is used for this selection. The eight-consecutive-burst mode is
selected by writing "1" to RBST8 and the four-consecutive-burst mode is selected by setting the bit to "0". At
cold start, the four-consecutive-burst mode is set by default.
II CORE BLOCK: BCU (Bus Co ntrol Unit )
S1C33L03 FUNCTION PART EPSON B-II-4-13
A-1
B-II
BCU
Bus Operation
Data Arrangement in Memory
The S1C3 3 Fami ly of devices ha ndle data in bytes ( 8 bits), half-w ord s (1 6 b its) , and w or ds (3 2 b its) . When
accessing data in memory, it is necessary to specify a boundary address that conforms to the data size involved.
Specification of an invalid address causes an address error exception. For instructions (e.g., stack manipulation or
branch instructions) that rewrite the SP (stack pointer) or PC (program counter), the specified addresses are
forcibly modified to appropriate boundary addresses. Therefore, no address error exception occurs in this type of
instruction. For details about the address error exception, refer to the "S1C33000 Core CPU Manual".
Table 4.12 shows t he data arrangement in memory, classified by data type.
Table 4.12 Data Arrangement in Memory
Data type Arranged location
Byte data Byte boundary address (all addresses)
Half-word data Half-word boundary address (A[0]="0")
Word data Word boundary address (A[1:0]="00")
The half-word and word data in memory area accessed in little-endian format by default. It can be changed to big-
endian format using AxxEC (D[7:0])/Access control register (0x48132). When "1" is written to AxxEC, the
corresponding area is accessed in big-endian method. The bit names and the corresponding areas are as follows:
A18EC (D7): Areas 17 and 18
A16EC (D6): Areas 15 and 16
A14EC (D5): Areas 13 and 14
A12EC (D4): Areas 11 and 12
A10EC (D3): Areas 9 and 10 ... Fixed at "0" (little-endian) for booting.
A8EC (D2):Areas 7 and 8
A6EC (D1):Area 6
A5EC (D0):Areas 4 and 5
To increase memory efficiency, try to locate the same type of data at continuous locations on exact boundary
addresses in order to minimize invalid areas.
Bus Operation of External Memory
The external data bus is 16-bits wide. For thi s reason, more than one bus operation occurs depending on the device
size and the data size of the instruction executed, as shown in Table 4.13.
Table 4.13 Number of Bus Operation Cycles
Data size to
be accessed Devise
size Number of bus
operation cycles Remarks
32 bits 16 bits 2
16 bits 16 bits 1
8 bits 16 bits 1 In little-endian method, the low-order byte is accessed when the LSB of the
address (A[0]) is "0" or the #BSL signal is L. The high-order byte is accessed
when the LSB of the address (A[0]) is "1" or the #BSH signal is H.
In big-endian method, the high-order byte is accessed when the LSB of the
address (A[0]) is "0" or the #BSL signal is L. The low-order byte is accessed
when the LSB of the address (A[0]) is "1" or the #BSH signal is H.
32 bits 8 bits 4 In little-endian method, the 8-bit device must be connected to the low-order 8
bits of the data bus. In big-endian method, the 8-bit device must be connected
to the high-o rder 8 bi ts of th e data bus.
16 bits 8 bits 2 In little-endian method, the 8-bit device must be connected to the low-order 8
bits of the data bus. In big-endian method, the 8-bit device must be
connected to the high-order 8 bits of the data bus.
8 bits 8 bits 1 In little-endian method, the 8-bit device must be connected to the low-order 8
bits of the data bus. In big-endian method, the 8-bit device must be
connected to the high-order 8 bits of the data bus.
These bus operations are shown in the figure below, taking the example of the A0 method.
With the BSL method, the following adjustments should be made when reading the figure.
(1) For data reads, the operation is as shown in the figure below.
(2) For little-endian data writes, read A0 as #BSC, and #WRH as #BSH.
(3) For big-endian data writes, read A0 as #BSL, and #WRL as #BSH.
II CORE BLOCK: BCU (Bus Co ntrol Unit )
B-II-4-14 EPSON S1C33L03 FUNCTION PART
For information on memory connection, see Figure 4.18.
Byte 1
15
Data bus
0#WRL
0
0
#WRH
0
0
A0
0
0
A1
0
1
No.
1
2Byte 0
Byte 3 Byte 2
Byte 3 Byte 2 Byte 1 Byte 0
31 0
A[1:0]=10 A[1:0]=00
15 0
12 150
Source (general-purpose register)
Destination (16-bit device)
Bus operation
Little-endian
Byte 3
15
Data bus
0#WRL
0
0
#WRH
0
0
A0
0
0
A1
0
1
No.
1
2Byte 2
Byte 1 Byte 0
Byte 3 Byte 2 Byte 1 Byte 0
31 0
A[1:0]=00 A[1:0]=10
15 0
21 150
Source (general-purpose register)
Destination (16-bit device)
Bus operation
Big-endian
Figure 4.5 Word Data Writing to a 16-bit Device
Byte 1
15
Data bus
0#WRL
1
1
#WRH
1
1
A0
0
0
A1
0
1
No.
1
2Byte 0
Byte 3 Byte 2
Bus operation
12
Byte 3 Byte 2 Byte 1 Byte 0
31 0
Destination (general-purpose register)
A[1:0]=10 A[1:0]=00
Source (16-bit device)
15 0150
Little-endian
Byte 3
15
Data bus
0#WRL
1
1
#WRH
1
1
A0
0
0
A1
0
1
No.
1
2Byte 2
Byte 1 Byte 0
Bus operation
21
Byte 3 Byte 2 Byte 1 Byte 0
31 0
Destination (general-purpose register)
A[1:0]=00 A[1:0]=10
Source (16-bit device)
15 0150
Big-endian
Figure 4.6 Word Data Reading from a 16-bit Device
Byte 1
15
Data bus
0#WRL
0
#WRH
0
A0
0
A1
∗
No.
1 Byte 0
Byte 3 Byte 2 Byte 1 Byte 0
31 0
A[1:0]=
∗
0
0
1
15
Source (general-purpose register)
Destination (16-bit device)
Bus operation
Little-endian
Byte 1
15
Data bus
0#WRL
0
#WRH
0
A0
0
A1
∗
No.
1 Byte 0
Byte 3 Byte 2 Byte 1 Byte 0
31 0
A[1:0]=
∗
0
0
1
15
Source (general-purpose register)
Destination (16-bit device)
Bus operation
Big-endian
Figur e 4.7 Half-word Data Writing to a 16-bit Device
Byte 1
15
Data bus
0#WRL
1
#WRH
1
A0
0
A1
∗
No.
1 Byte 0
Bus operation
1
Sign or Zero extension Byte 1 Byte 0
31 0
Destination (general-purpose register)
A[1:0]=
∗
0
Source (16-bit device)
015
Little-endian
Byte 1
15
Data bus
0#WRL
1
#WRH
1
A0
0
A1
∗
No.
1 Byte 0
Bus operation
1
Sign or Zero extension Byte 1 Byte 0
31 0
Destination (general-purpose register)
A[1:0]=
∗
0
Source (16-bit device)
015
Big-endian
Figur e 4.8 Half-word Data Reading from a 16-bit Device
II CORE BLOCK: BCU (Bus Co ntrol Unit )
S1C33L03 FUNCTION PART EPSON B-II-4-15
A-1
B-II
BCU
Byte 0
15
Data bus
0#WRL
1
0
#WRH
0
1
A0
1
0
A1
∗
∗
No.
1
1' Data retained
Byte 0Data retained
Byte 3 Byte 2 Byte 1 Byte 0
31 0
A[1:0]=
∗
0A[1:0]=
∗
1
0
1'1
15
Source (general-purpose register)
Destination (16-bit device)
Bus operation
Little-endian
Byte 0
15
Data bus
0#WRL
1
0
#WRH
0
1
A0
0
1
A1
∗
∗
No.
1
1' Data retained
Byte 0Data retained
Byte 3 Byte 2 Byte 1 Byte 0
31 0
A[1:0]=
∗
1A[1:0]=
∗
0
0
1'1
15
Source (general-purpose register)
Destination (16-bit device)
Bus operation
Big-endian
Figure 4.9 Byte Data Writing to a 16-bit Device
RD byte
15
Data bus
0#WRL
1
1
#WRH
1
1
A0
1
0
A1
∗
∗
No.
1
1' Ignored
RD byteIgnored
RD byte
31 0
A[1:0]=
∗
0A[1:0]=
∗
1
0
1'1
15
Bus operation
Sign or Zero extension
Destination (general-purpose register)
Source (16-bit device)
Little-endian
RD byte
15
Data bus
0#WRL
1
1
#WRH
1
1
A0
0
1
A1
∗
∗
No.
1
1' Ignored
RD byteIgnored
RD byte
31 0
A[1:0]=
∗
1A[1:0]=
∗
0
0
1'1
15
Bus operation
Sign or Zero extension
Destination (general-purpose register)
Source (16-bit device)
Big-endian
Figure 4.10 Byte Data Reading from a 16-bit Device
Data retained
15
Data bus
0#WRL
0
0
0
0
#WRH
X
X
X
X
A0
0
1
0
1
A1
0
0
1
1
No.
1
2
3
4
Byte 0
Data retained Byte 1
Data retained Byte 2
Data retained Byte 3
Byte 3 Byte 2 Byte 1 Byte 0
31 0
A[1:0]=10 A[1:0]=00A[1:0]=11 A[1:0]=01
80
14 888000
Source (general-purpose register)
Destination (8-bit device)
3 2
Bus operation
(X: Not connected/Unused)
Little-endian
Byte 3
15
Data bus
0#WRL
1
1
1
1
#WRH
0
0
0
0
A0
0
1
0
1
A1
0
0
1
1
No.
1
2
3
4
Data retained
Byte 2 Data retained
Byte 1 Data retained
Byte 0 Data retained
Byte 3 Byte 2 Byte 1 Byte 0
31 0
A[1:0]=01 A[1:0]=11A[1:0]=00 A[1:0]=10
80
41 888000
Source (general-purpose register)
Destination (8-bit device)
2 3
Bus operation
Big-endian
Figure 4.11 Word Data Writing to an 8-bit Device
Ignored
15
Data bus
0#WRL
1
1
1
1
#WRH
X
X
X
X
A0
0
1
0
1
A1
0
0
1
1
No.
1
2
3
4
Byte 0
Ignored Byte 1
Ignored Byte 2
Ignored Byte 3
Byte 3 Byte 2 Byte 1 Byte 0
31 0
A[1:0]=10 A[1:0]=00A[1:0]=11 A[1:0]=01
80
14 88800032
Bus operation
(X: Not connected/Unused)
Destination (general-purpose register)
Source (8-bit device)
Little-endian
Byte 3
15
Data bus
0#WRL
1
1
1
1
#WRH
1
1
1
1
A0
0
1
0
1
A1
0
0
1
1
No.
1
2
3
4
Ignored
Byte 2 Ignored
Byte 1 Ignored
Byte 0 Ignored
Byte 3 Byte 2 Byte 1 Byte 0
31 0
A[1:0]=01 A[1:0]=11A[1:0]=00 A[1:0]=10
80
41 88800023
Bus operation
Destination (general-purpose register)
Source (8-bit device)
Big-endian
Figure 4.12 Word Data Reading from an 8-bit Device
II CORE BLOCK: BCU (Bus Co ntrol Unit )
B-II-4-16 EPSON S1C33L03 FUNCTION PART
Data retained
15
Data bus
0#WRL
0
0
#WRH
X
X
A0
0
1
A1
∗
∗
No.
1
2Byte 0
Data retained Byte 1
Byte 3 Byte 2 Byte 1 Byte 0
31 0
A[1:0]=∗0A[1:0]=∗1
0
1
880
Source (general-purpose register)
Destination (8-bit device)
2
Bus operation
(X: Not connected/Unused)
Little-endian
Byte 1
15
Data bus
0#WRL
0
0
#WRH
0
0
A0
0
1
A1
∗
∗
No.
1
2Data retained
Byte 0 Data retained
Byte 3 Byte 2 Byte 1 Byte 0
31 0
A[1:0]=∗1A[1:0]=∗0
0
2
880
Source (general-purpose register)
Destination (8-bit device)
1
Bus operation
(∗: Uniformly 1 or 0)
Big-endian
Figure 4.13 Half-word Data Writing to an 8-bit Device
Ignored
15
Data bus
0#WRL
1
1
#WRH
X
X
A0
0
1
A1
∗
∗
No.
1
2Byte 0
Ignored Byte 1
Byte 1 Byte 0
31 0
A[1:0]=∗0A[1:0]=∗1
0
1
880
2
Bus operation
(X: Not connected/Unused)
Destination (general-purpose register)
Source (8-bit device)
Sign or Zero extension
Little-endian
Byte 1
15
Data bus
0#WRL
1
1
#WRH
1
1
A0
0
1
A1
∗
∗
No.
1
2Ignored
Byte 0 Ignored
Byte 1 Byte 0
31 0
A[1:0]=∗1A[1:0]=∗0
0
2
880
1
Bus operation
Destination (general-purpose register)
Sign or Zero extension
Big-endian
(∗: Uniformly 1 or 0)
Figur e 4.14 Half-word Data Reading from an 8-bit Device
Data retained
15
Data bus
0#WRL
0
#WRH
X
A0
∗
A1
∗
No.
1 Byte 0
Byte 3 Byte 2 Byte 1 Byte 0
31 0
A[1:0]=
∗∗ 0
1
8
Source (general-purpose register)
Destination (8-bit device)
Bus operation
(X: Not connected/Unused)
Little-endian
Byte 0
15
Data bus
0#WRL
1
#WRH
0
A0
∗
A1
∗
No.
1 Data retained
Byte 3 Byte 2 Byte 1 Byte 0
31 0
A[1:0]=
∗∗ 0
1
8
Source (general-purpose register)
Destination (8-bit device)
Bus operation
Big-endian
Figure 4.15 Byte Data Writing to an 8-bit Device
Ignored
15
Data bus
0#WRL
1
#WRH
X
A0
∗
A1
∗
No.
1 Byte 0
Byte 0
31 0
A[1:0]=∗∗
0
1
8
Bus operation
(X: Not connected/Unused)
Destination (general-purpose register)
Source (8-bit device)
Sign or Zero extension
Little-endian
Byte 0
15
Data bus
0#WRL
1
#WRH
1
A0
∗
A1
∗
No.
1 Ignored
Byte 0
31 0
A[1:0]=∗∗
0
1
8
Bus operation
Destination (general-purpose register)
Source (8-bit device)
Sign or Zero extension
Big-endian
Figure 4.16 Byte Data Reading from an 8-bit Device
II CORE BLOCK: BCU (Bus Co ntrol Unit )
S1C33L03 FUNCTION PART EPSON B-II-4-17
A-1
B-II
BCU
Bus Clock
The bus clock is generated by the BCU us ing the CPU system clock output from the clock generator.
Figure 4.17 shows the clock system.
High-speed (OSC3)
oscillation circuit
CLKCHGCLKDT[1:0]
PLLS[1:0] pins #X2SPD pin To CPU
OSC3_CLK
PLL_CLK
ACPU_CLK BCU_CLK
CPU_CLK
OSC3_CLK
PLL_CLK
Bus clock
PLL
Low-speed (OSC1)
oscillation circuit
CLG BCU
1/1 or 1/2
1/1–1/8 BCLKSEL[1:0]
SDRENA
SD_CLK
SDRAMC
1/1 or 1/2
Refresh
counter
BCLK pin
PLL_CLK and CPU_CLK
BCU_CLK
SD_CLK (When #X2SPD = "1")
OSC3_CLK (PLL: off)
PLL_CLK (PLL: x2 mode)
PLL_CLK (PLL: x4 mode)
A
CPU_CLK (CLKDT = 1/1)
CPU_CLK (CLKDT = 1/2)
CPU_CLK (CLKDT = 1/4)
CPU_CLK (CLKDT = 1/8)
CPU_CLK
BCU_CLK (#X2SPD = "1", x1 speed mode)
BCU_CLK (#X2SPD = "0", x2 speed mode)
(when the CPU system clock source is OSC3)
∗1
∗1 Access to the internal RAM
∗2 Access to the external memory (other than SDRAM)
∗3 Access to the SDRAM
∗1
∗1
∗1
∗2∗1∗2
∗2
∗3∗2∗1
∗1∗2
#SDCEx
CPU_CLK
BCU_CLK
SD_CLK (SDRCLK = "1")
SD_CLK (SDRCLK = "0")
SDCKE Self refresh
SD_CLK (When #X2SPD = "0")
∗3∗2∗1
#SDCEx
CPU_CLK
BCU_CLK
SD_CLK (SDRCLK = "1")
SD_CLK (SDRCLK = "0")
SDCKE Self refresh
Figur e 4.17 Clock System
II CORE BLOCK: BCU (Bus Co ntrol Unit )
B-II-4-18 EPSON S1C33L03 FUNCTION PART
Since the bus clock is generated from the CPU system clock (CPU_CLK), the following settings affect the bus
clock:
1. Selectio n of an oscillat ion circui t (OSC 3 or OS C1)
2. PLL configuration (OSC3_ CLK x 1, x2 or x4)
3. CPU c lock division rat io for power saving (1/8, 1/4, 1/2, or 1/1 of OSC3_ C LK or PLL_ CLK)
Items 2 and 3 apply when the high-speed (OSC3) oscillation circuit is selected as the CPU clock source.
For details about the settings of the system clock, refer to "CLG (Clock Generator)".
Bus c lock operation during standby is as follows:
Basic HALT m ode :the BCU and bus clock continue operating. DRAM can be refreshed.
HA LT2 mode: the BCU and bus clock are stopped.
SLEEP mode: the BCU and bus clock are stopped.
Bus Speed Mode
The CPU - bus clock rat io can be set using t he #X2SPD pin as foll ows:
When #X2SPD = "1", x1 speed mode (CPU - bus clock rati o is 1 : 1) is set. The bus clock and the CPU s ystem
clock will be the same.
When #X2SPD = "0", x2 spe ed mode (CPU - bus clock ratio is 2 : 1) is set . In x2 speed mo de, the bus clock will be
dynamically varie d acco rding to the memory to be accessed.
•When an external memory area is accessed, the bus clock frequency becomes half of the CPU system clock.
•When the internal RAM/ROM area is accessed, the bus clock frequency becomes equal to the CPU system clock.
In x1 speed mode, area 1 (internal I/O area) is accessed in 4 cycles of the CPU system clock, while in x2 speed
mode , the number of access cycles can be selected using A1X1MD (D3) / BCLK select register (0x4813A).
When A1X1MD = "1", area 1 is accessed in 2 cycles of the CPU system clock.
When A1X1MD = "0", area 1 is accessed in 4 cycles of the CPU system clock. (default)
Bus Clock Output
The bus clock is also output from the BCLK pin to an external device. The BCLK output clock can be selected
from among five types using BCLKSEL[1:0] (D[1:0]) / BCLK select register (0x4813A) and SDRENA (D7) /
SD RAM control register (0x39FFC1).
Table 4.14 Selection of BCLK Output Clock
SDRENA BCLKSEL1 BCLKSEL0 Output clock
11PLL_CLK (PLL output clock)
10OSC3_CLK (OSC3 oscillation clock)
01BCU_CLK (BCU o perating clock)
0
00CPU_CLK (CPU operating clock)
1––SD_CLK (SDRAM clock)
II CORE BLOCK: BCU (Bus Co ntrol Unit )
S1C33L03 FUNCTION PART EPSON B-II-4-19
A-1
B-II
BCU
Bus Cycles in External System Interface
The following shows a sample SRAM connection the basic bus cycles.
A[9:1]
D[15:0]
#RD
#WRH
#WRL
#CE
S1C33
(1) A0 system (little endian/big endian)
A[8:0]
I/O[15:0]
#RD
#WRH
#WRL
#CE
SRAM
A[9:1]
D[15:0]
A0
#WRH
#WRL
#CE
#RD
S1C33
(2) #BSL system (little endian)
A[8:0]
I/O[15:0]
#LB
#UB
#WE
#OS
#OE
SRAM
A[9:1]
D[15:0]
A0
#WRH
#WRL
#CE
#RD
S1C33
(3) #BSL system (big endian)
A[8:0]
I/O[15:0]
#LB
#UB
#WE
#OS
#OE
SRAM
Figur e 4.18 Sample DRAM Connection
SRAM Rea d Cycles
Basic read cycle with no wait mode
BCLK
A[23:0]
#CExx
D[15:0]
#RD
#WAIT
;;;
;;;
;;
;;
addr
data
C1
Figur e 4.19 Basic Read Cycl e with No W ait
Read cycle with wait mode
Example: W hen the BCU has no internal wait mo de and 2 wa it cycles vi a #WAIT pin are inserted
;;;;;;
;;;;;;
;;;;;
;;;;;
;;;;;
;;;;;
;;;;;
;;;;;
BCLK
A[23:0]
#CExx
D[15:0]
#RD
#WAIT
C1 CW CW
;;;
;;;
;;;;;;;;;;;;;;
;;;;;;;;;;;;;;
addr
data
Figur e 4.20 Read Cycle with Wait
The #WAIT signal is sampled at the falling edge of the transition of BCLK (bus clock) and when it is
sampled on an inactive (high level), the read cycle is terminated.
Note: Insertion of wait cycl e s via the #WAIT pin is po ssi ble on l y when the devi ce f or bus co nd iti on s is se t
for SRAM, and SWAITE (D 0) / Bus contr ol register (0x4812E) is en abled for wa iting .
II CORE BLOCK: BCU (Bus Co ntrol Unit )
B-II-4-20 EPSON S1C33L03 FUNCTION PART
The abo ve example shows a read cycle when a wait mode is inserted via the #WAIT signal. A wait mode
consisting of 0 to 7 cycles can also be inserted using the wait control bits. The settings of these bits can also
be used in com bin ation with the #WAIT signal. In this case as well, the #WAIT signal is sampled at the
falling edge of the transition of BCLK. However, even when the #WAIT signal is inactive before the wait
cycles set by the wait control bits are terminated, the read cycle is not terminated at that time.
Precaution
#C E and ad dress hold times at the rising edge of the #RD signal
In read cycles of this BCU, the rise of the #RD signal, negating the chip enable (#CExx) signal and changing
the address (A[23:0]) occur simultaneously at the same clock edge. No hold time is inserted to the chip enable
and address signals. The same applies even when an output disable delay time is inserted.
There fore w hen con necting a periph eral ci rcu it, w hi ch ch an ges its internal state by reading, to the bus, take a
measure to insert a delay to the address and chip enable signals.
BCLK
A[23:0]
#CE4
#CE7
#RD
addr
Hazard occurrence.
This hazard causes an erroneous
RD operation on the next area.
Figur e 4.21 Trouble Case
Output disable cycle
When an output disable cycle (set with output disable delay time parameter) is inserted, the chip enable
(#CExx) signal temporarily goes high. This makes an interval between the next read cycle.
Note , however, that no output disable cyc le is inserted wh en reading is continuously performed to the area
that is accessed with the same chip enable signal.
Bus Timing
In read cycles, the rise of the #RD signal and changing the chip enable setting (#CE4 to #CE10) and address (A23
to A0) occur at the same clock edge.
This timing is the same even if a long setting is made for the output disable cycle by the bus controller, for example,
and changeover occurs simultaneously.
Th erefore, when an I/O periphe ral circuit w hos e intern al information is changed by a read operation is connected to
the C33 bus, appropriate measures must be taken to insert a delay for the address and chip enable signals.
With an output disable cycle, there is normally a gap between one read cycle and the next. Note, however, that this
outpu t disable cycle is not inserted in the case of consecutive reads in a memory area for which the same chip
enable signal is output.
II CORE BLOCK: BCU (Bus Co ntrol Unit )
S1C33L03 FUNCTION PART EPSON B-II-4-21
A-1
B-II
BCU
SRAM Write Cycles
Basic write cyc le with n o wait mode
BCLK
A[23:0]
#CExx
D[15:0]
#WRH/#WRL
#WAIT
#WR
#BSL/#BSH
;;;
;;;
addr
data
C1 C2
Figur e 4.22 Half-word Write Cycle with No Wait
BCLK
A[23:0]
#CExx
#WRH
#WRL
D[15:8]
D[7:0]
C1 C2 C3 C4
;;;
;;;
addr
Undefined Valid
Valid Undefined
Figure 4.23 Byte Write Cycle with No Wait (A0 system, little endian)
BCLK
A[23:0]
#CExx
#BSH
#BSL
#WRL
D[15:8]
D[7:0]
C1 C2 C3 C4
;;;
;;;
addr
Undefined Valid
Valid Undefined
Figure 4.24 Byte Write Cycle with No Wait (#BSL system, little endian)
II CORE BLOCK: BCU (Bus Co ntrol Unit )
B-II-4-22 EPSON S1C33L03 FUNCTION PART
Write cycle with wait mode
Example: W hen the BCU has no internal w ai t mode, and 1 wait cycle is inserted via the #WAIT pin
BCLK
A[23:0]
#CExx
D[15:0]
#WRH/#WRL
#WAIT
#WR
#BSL/#BSH
C1 CW C2
;;;
;;;
addr
data
Figur e 4.25 Half-word Write Cycle with Wait
The #WAIT signal is sampled at the falling edge of the transition of BCLK (bus clock), and the write cycle is
terminated in the cycle immediately following the cycle in which the #WAIT signal was sampled in an
inactive (high level).
Note: Insertion of wait cycl e s via the #WAIT pin is po ssib le on l y when the devic e f or bus co nd iti on s is se t
to SRAM and SWAITE (D0) / Bus control regi ster (0 x4 812E) is enable d for waiting.
The abo ve example shows a write cycle when a wait mode is inserted via the #WAIT signal. A wait mode
consisting of 2 to 7 cycles can also be inserted using the wait control bits. The settings of these bits also can
be used in com bin ation with the #WAIT signal. In this case as well, the #WAIT signal is sampled at the
falling edge of the transition of BCLK. However, even when the #WAIT signal is inactive before the wait
cycles set by the wait control bits are terminated, the write cycle is not terminated at that time.
Note: The basic wri te cycle consist s of at l east two cycles. This does not change regardless of whether
zero or one wa it cycle is set by t he wait control bits. If the number of wait cycles set is 2 or more,
the b us cycle is actual ly extended. In t his case, the bus write cycle cons ists of [num ber of wait
cycles + 1], as in the case of read cycles (providing that there is no external wait).
II CORE BLOCK: BCU (Bus Co ntrol Unit )
S1C33L03 FUNCTION PART EPSON B-II-4-23
A-1
B-II
BCU
Burst ROM Read Cycles
Burst read cycle
Ex ampl e: When 4-con secu tiv e-bu rst and 2-wait cycles are set during the first access
BCLK
A[23:2]
A[1:0]
#CE10(9)
D[15:0]
#RD
;;;
;;;
addr[23:2]
;;;
;;;
"11""10""01""00"
;;;;
;;;;
;;;;
;;;;
IR3IR2
;;;;
;;;;
IR1
;;;;;;;;;;;;;;
;;;;;;;;;;;;;;
IR0
Figure 4.26 Burst Read Cycle
A bur st read cycle occurs when area 10 or 9 is set for burst ROM and one of those areas is accessed for the
following reasons:
1) Instruction fetch
The bur st read cycle is executed as long as a instruction fetch from contiguous addresses continues until
A[2:1] = "11" (for 4-consecutive bursts); or
A[3:1] = "111" (for 8-consecutive bursts)
2) Word (32-bit ) d ata read out
Note: A 16-bit output i s supp orted f or the burst ROM . Set the device si ze to 16 bits.
Wait cycles during burst read
In the first bus operation, 0 to 7 wait cycles can be inserted using the wait control bits A10WT[2:0] (D[2:0]) /
Areas 10–9 set-up register (0x48126) in the same way as for ordinary SRAM. For the wait cycles to be
inserted in the burst cycle that follows, use a dedicated wait control bits, A10BW[1:0], which is only used for
reading bursts. The wait cycles can be set in the range from 0 to 3 using these bits.
Note that no wait cycle via the #WAIT pin can be inserted into the burst-read cycle.
Write cycle to burst ROM area
If area 10 or 9 is set for burst ROM, a SRAM write cycle is executed when a write to that area is attempted. In
this case, wait cycles via the #WAIT pin can be inserted.
II CORE BLOCK: BCU (Bus Co ntrol Unit )
B-II-4-24 EPSON S1C33L03 FUNCTION PART
DRAM Direct Interface
Outline of DRAM Interface
Th e BCU inc orpo rates a DRAM di rect interface that allows DRAM to be connected directly to areas 8 and 7 or
areas 14 and 13. This interface supports the 2CAS method, so that column addresses can be set at between 8 and 11
bits. In addition, this interface supports a fast-page or an EDO-page mode (EDO DRAM directly connectable to
areas) as well as random cycles. The refresh method (CAS-before-RAS refresh or self-refresh) and timing
conditions (e.g., number of RAS/CAS cycles and number of precharge cycles) can be programmed using a control
bit.
When se lecting areas 8 and 7 or areas 14 and 13 to be used for DRAM, it depend s o n chip-e nable settings using
CEFUNC (D9) / DRAM timing set-u p register (0x4 81 30 ).
CEFUNC = "00": DRAM can be connected to areas 8 and 7 (default)
#CE8 and #CE7 function as #RAS0 and # RAS 1, re sp ecti v ely .
CEFUNC ≠ "00": DRAM can be connected to areas 14 and 13.
#C E14 a nd #CE1 3 function as #RAS2 and #R AS 3, respect ively.
Figure 4.27 shows a sample DRAM connection. Table 4.15 and Table 4.16 show examples of connectable DRAMs
and t y pi cal conf ig ura t io ns.
A[9:1]
D[15:0]
#RD
#RASx(#CEx)*
#HCAS
#LCAS
#WE
S1C33
A[8:0]
I/O[15:0]
#OE
#RAS
#HCAS
#LCAS
#WE
4M DRAM
(256K x 16)
∗ x: 14, 13, 8 or 7
Figur e 4.27 Sample DRAM Connection
Table 4.15 Connectable DRAM Example
DRAM Number of
devices Number of
Row bits Number of
Column bits Memory size
1M (64K x 16) 1 8 8 128K bytes
4M (256K x 16) 1 9 9 512K bytes
16M (1M x 16) 1 12 8 2M bytes
Table 4.16 DRAM Configuration Example (areas 7 and 8 only)
Area 7 Area 8 Total memory size
1I/O DRAM (1M) 1M bits (128K bytes)
2I/O DRAM (4M) 4M bits (512K bytes)
3I/O DRAM (16M) 16M bits (2M bytes)
4DRAM (1 M) DRAM (1M) 2M bits (2 56K bytes)
5DRAM (4 M) DRAM (4M) 8M bits (1 M byte s)
6DRAM (1 6M) DRAM (16M) 32M bits (4M bytes)
Also, the S1C3 3L03 provides an SDRAM direct interface. Refer to "VI SDRAM Controller Block" for details.
II CORE BLOCK: BCU (Bus Co ntrol Unit )
S1C33L03 FUNCTION PART EPSON B-II-4-25
A-1
B-II
BCU
DRAM Setting Conditions
The DRAM interface allows the following conditions to be selected. Although DRAM can be used in areas 8 and 7
or areas 14 and 13, these condition are applied to all four areas and cannot be set individually for each area.
Table 4.17 DRAM In terfa ce Parame ters
Parameter Selectable condition Initial setting Control bits
Page mode EDO page mode
or Fast page mode Fast page mode REDO(DC)/Bus control register(0x4812E)
RAS mode Suc cessive RAS mode
or Normal mode Normal mode CRAS(D8)/DRAM timing set-up register(0x48130)
Column address size 8, 9, 10 or 11 bits 8 bits RCA[1:0](D[B:A])/Bus control register(0x4812E)
Refresh enable Enabled or Disabled Disabled RPC2(D9)/Bus control register(0x4812E)
Refresh method Self-refresh
or CAS-before-RAS
refresh
CBR refresh RPC1(D8)/Bus control register(0x4812E)
Refresh RPC delay 2.0 or 1.0 1.0 RPC0(D7)/Bus control register(0x4812E)
Refresh RAS pulse width 2, 3, 4 or 5 cycles 2 cycles RRA[1:0](D[6:5])/Bus control register(0x4812E)
Number of RAS precharge
cycles 1, 2, 3 or 4 cycles 1 cycle RPRC[1:0](D[7:6])/DRAM timing set-up register(0x48130)
CAS cycle control 1, 2, 3 or 4 cycles 1 c ycle CASC[1:0](D[4:3])/DRAM timing set-up register(0x48130)
RAS cycle control 1, 2, 3 or 4 cycles 1 c ycle RASC[1:0](D[1:0])/DRAM timing set-up register(0x48130)
Page mode
The DRAM interface allows EDO DRAM to be connected directly. Therefore, the EDO-page mode is
supported along with the fast-page mode.
Use REDO to cho ose the de sired page mode that suits the DRAM to be used.
REDO = " 1" : EDO pa ge mode
REDO = " 0": Fast page mode (default)
Successive RAS mode
For applications that require high-speed DRAM access, the DRAM interface supports a successive RAS
mode . In this mode, even when successive accesses to the DRAM are not requested by the CPU or DMA, the
#R A S signal is kept low and operation is continued without inserting any precharge cycle. Therefore, when
accessing the same page (row address) of the DRAM that has been accessed previously, the page mode
remains active, allowing read/write to be performed at high speeds.
However, to ma intain the rated AC characteristics, one idle cycle is inserted when access in the page mode is
begun and w he n fi nis he d.
CR AS is use d to set the successive RAS mode.
CRAS = "1": Succes si ve R AS mod e
CRAS = "0": Normal mode (default)
The successive RAS mode is suspended by one of the following causes:
• a refresh cycle has occurred;
• bus control is requested by an external bus master;
• the requested device and page are not compatible with DRAM memory; and
• the slp or halt instruction is executed.
If the successive RAS mode is suspended, a precharge cycle is inserted before the next bus cycle begins.
Note: When using th e successive RAS mo de, always be sure to us e #DRD f or the read sig nal and
#DWE for the low-byte write si gnal.
II CORE BLOCK: BCU (Bus Co ntrol Unit )
B-II-4-26 EPSON S1C33L03 FUNCTION PART
Column address size
When ac cessing DRAM, addresses are divided into a row address and a column address as they are output.
Choose the size of this column address using RCA, as shown below.
Table 4.18 Column Address Size
RCA1 RCA0 Column address size
11 11
10 10
01 9
00 8
The initial default size is 8 bits. Choose the desired size according to the address input pins of the DRAM to
be used.
The row addresses output synchronously with falling edges of the #RAS signal are derived from the CPU's
internal 28-bit addresses by logically shifting them to the right by an amount equal to the column address size.
The MSB contains a 1. The column addresses are output to the address bus along with the falling edges of the
#C AS signal. Th ese addresses are derived directly from the CPU's internal 28-bit addresses.
Figure 4.28 shows the contents of the row addresses thus output.
28-bit CPU internal address
T = "1", 0–27: Bit number of CPU internal address
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
(1) Row address when column address is set to 8 bits
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8T T T T T T T T
(2) Row address when column address is set to 9 bits
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9T T T T T T T T
(3) Row address when column address is set to 10 bits
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10T T T T T T T T
(4) Row address when column address is set to 11 bits
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11T T T T T T T T
T
T
T
T
T T
Figur e 4.28 Example of Row/Column Address Mapping
Refresh enable
Use RPC2 to e nable or disable t he internal refresh function.
RPC2 = "1": Enabl ed
RPC2 = "0": Disabled (default)
Aft er choosing the desired refresh method using RPC1, write "1" to RPC2.
Refresh method
The DRAM interface sup ports both a CAS-before-RAS refresh cycle and a self-refresh cycle. Choose the
desired method using RPC1.
RPC1 = "1": Self-refresh
RPC1 = "0": CAS-before-RAS refresh
The gen eration interval of the CAS-before-RAS refresh is determined by the underflow signal of an 8-bit
programmable t imer 0. Consequently, before the CAS-before-RAS refresh can be executed, the 8-bit
programmable timer 0 must be set to obtain the necessary underflow timing. When this method is selected
and RPC2 is enabled, the refresh cycle is generated each time the 8-bit programmable timer 0 underflows.
Th e self-refresh is started by writing "1" to RPC2 while RPC1 = "1" and is terminated by clearing RPC1 or
RPC2 to "0".
If RPC1 is switched over when RPC2 = "1" (refresh enabled), an undesirable self-refresh cycle is generated.
So be sure to clear RPC2 to "0" (refresh disabled) before selecting the refresh method.
II CORE BLOCK: BCU (Bus Co ntrol Unit )
S1C33L03 FUNCTION PART EPSON B-II-4-27
A-1
B-II
BCU
Refresh RPC delay
Use RPC0 to set the RPC delay value of a refresh cycle (a delay time from the immediately preceding
precharge to the fall of #CAS).
RPC0 = "1": 2 cycles
RPC0 = "0": 1 cycle
Refresh RAS pulse width
Use RRA to set the #RAS pul se width of a CA S-before-RAS refresh cycle.
Table 4.19 Refresh RAS Pulse Width
RRA1 RRA0 Pulse width
11 5 cycles
10 4 cycles
01 3 cycles
00 2 cycles
The initial default value is 2 cycles.
Numb er o f RAS precha r g e cycles
Use RPRC to choose the number of RAS precharge cycles.
Table 4.20 Number of RAS Precharge Cycles
RPRC1 RPRC0 Number of cycles
11 4 cycles
10 3 cycles
01 2 cycles
00 1 cycle
The initial default value is 1 cycle.
CAS cycle control
Use CASC to choose the number of CAS cycles when accessing DRAM.
Table 4.21 Number of CAS Cycles
CASC1 CASC0 Number of cycles
11 4 cycles
10 3 cycles
01 2 cycles
00 1 cycle
The initial default value is 1 cycle.
RAS cycle control
Use RASC to choose the number of RAS cycles when accessing DRAM.
Table 4.22 Number of RAS Cycles
RASC1 RASC0 Number of cycles
11 4 cycles
10 3 cycles
01 2 cycles
00 1 cycle
The initial default value is 1 cycle.
II CORE BLOCK: BCU (Bus Co ntrol Unit )
B-II-4-28 EPSON S1C33L03 FUNCTION PART
DRAM Read/Write Cycles
The following shows the basic bus cycles of DRAM.
The DRAM interface does not accept wait cycles inserted via the #WAIT pin.
DRAM random read cycle
Example: RAS: 1 cycle; CAS : 2 cycles ; Precha rge: 1 cycle
BCLK
A[11:0]
#RASx
#HCAS/
#LCAS
#RD
D[15:0]
;;;;;;;
;;;;;;;
;;;;;;;;;;;;;
;;;;;;;;;;;;;
;;;;
;;;;
ROW COL
data
RAS cycle CAS cycle Precharge
cycle
Figur e 4.29 DRAM Random Read Cy cl e
DRAM read cycle (fast page mode)
Example: RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle
BCLK
A[11:0]
#RASx
#HCAS/
#LCAS
#RD
D[15:0]
;;;;;;;
;;;;;;;
;;;;;;;;;;;;;
;;;;;;;;;;;;;
;;;;;;;;;
;;;;;;;;;
ROW COL #1 COL #2
data
;;;;
;;;;
data
RAS cycle CAS cycle #1 CAS cycle #2 Precharge
cycle
Figur e 4.30 DRAM Read Cycle (fast page mode)
DRAM read cycle (EDO page mode)
Example: RAS: 1 cycle; CAS : 2 cycles ; Precha rge: 1 cycle
BCLK
A[11:0]
#RASx
#HCAS/
#LCAS
#RD
D[15:0]
;;;;;;;
;;;;;;;
;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;
;;;;;;;;;
;;;;;;;;;
ROW COL #1 COL #2
data
;;
;;
data
RAS cycle CAS cycle #1 CAS cycle #2 Precharge
cycle
Figur e 4.31 DRAM Read Cycle (EDO page mode)
The read timing in EDO page-mode lags 0.5 cycles behind that in fast pag e mode .
II CORE BLOCK: BCU (Bus Co ntrol Unit )
S1C33L03 FUNCTION PART EPSON B-II-4-29
A-1
B-II
BCU
DRAM random write cycle
Example: RAS: 1 cycle; CAS : 2 cycles ; Precha rge: 1 cycle
BCLK
A[11:0]
#RASx
#HCAS/
#LCAS
#WE
D[15:0]
;;;;;;;
;;;;;;;
;;;;;
;;;;;
ROW COL
write data
RAS cycle CAS cycle Precharge
cycle
Figur e 4.32 2CAS Type DRAM Random Write Cycle
DRAM write cycle (fast page or EDO page mode)
Example: RAS: 1 cycle; CAS : 2 cycl es; Prec harg e: 1 cycle; w or d-w rite sa m ple
;;;;;;;
;;;;;;;
ROW COL #1 COL #2
write data
RAS cycle CAS cycle #1 CAS cycle #2 Precharge
cycle
BCLK
A[11:0]
#RASx
#HCAS/
#LCAS
#WE
D[15:0]
;;;;;
;;;;;
write data
Figur e 4.33 DRAM Word-Write Cycle (fast page or EDO page mode)
Example: RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle; byte-write sample (little endian)
;;;;;;;
;;;;;;;
ROW COL
write data
BCLK
A[11:0]
#RASx
#HCAS
#LCAS
#WE
D[15:8]
D[7:0]
;;;;;
;;;;;
Undefined
Undefined
;;;;;
;;;;;
write data
RAS cycle CAS cycle #1 CAS cycle #2 Precharge
cycle
Figur e 4.34 DRAM Byte-Write Cycle (fast page or EDO page mode)
II CORE BLOCK: BCU (Bus Co ntrol Unit )
B-II-4-30 EPSON S1C33L03 FUNCTION PART
Operation in successive RAS mode
Example: RAS: 2 cycles ; CAS: 1 cycle; P recharg e: 2 cycl es
BCLK
A[11:0]
#RASx
#HCAS/
#LCAS
#DRD
#DWE
RAS
cycle
Accsess to other
device than DRAM Not asserted for areas
other than DRAM
Precharge
cycle
Deassert
cycle Assert
cycle
CAS cycles
in page mode RAS
cycle CAS
cycles
CAS cycles
in page mode
(1) (2) (3) (4)
Figur e 4.35 Operation in Successive RAS Mode
(1) When accessing the DRAM area, an ordinary RAS cycle is executed first.
(2) If access to the same DRAM is suspended during a page mode, #RASx remains asserted while some other
device is accessed. In this case, a cycle to temporarily deassert #DRD/#DWE is inserted before accessing the
other device.
(3) If access to the same page in the same DRAM area as in (1) is requested after (2), #DRD/#DWE is asserted
back again to restart the page mode.
(4) A precharge cycle is executed when one of the following conditions that cause the page mode to suspend is
encountered:
• access to different DRAM is requested;
• access to a different page in the same DRAM area is requested;
• access to some other device than DRAM is requested;
• CAS-before-RAS refresh is requested; and
• relinquishing of bus control is requested by an external bus master.
Note: When using th e successive RAS mo de, always be sure to us e #DRD f or the read sig nal and
#DWE for the low-byte write si gnal.
II CORE BLOCK: BCU (Bus Co ntrol Unit )
S1C33L03 FUNCTION PART EPSON B-II-4-31
A-1
B-II
BCU
DRAM Refresh Cy cles
The DRAM interface sup ports a C AS-b efore -R A S refre sh cycle and a se lf-refresh cycle.
CAS-before-RAS refresh cycle
Before performing a CAS-before-RAS refresh, set RPC2 to "1" while RPC1 = "0" in order to enable the
DRAM refresh function. Once this is done, the BCU executes a CAS-before-RAS refresh by using the
underflow signal that is output by the 8-bit programmable timer 0 as a trigger. Therefore, refresh generation
timing can be programmed using the internal prescaler and 8-bit programmable timer 0.
For details on how to control the prescaler and 8-bit programmable timer 0, refer to "Prescaler and Operating
Clock for Peripheral Circuits", and "8-Bit Programmable Timers".
Exampl e: RPC delay: 1 cycle; Refresh RAS pu lse width: 2 cycles; Precharge: 1 cycle
CAS-before-RAS refresh cycle
Refresh
RPC delay Fixed at
1 cycle Refresh
RPC pulse width Precharge
cycle
BCLK
#RAS
#HCAS/
#LCAS
;;;;;;;
;;;;;;;
;;;;
;;;;
Figure 4.36 CAS-Before-RAS Refresh
When the refresh cycle is terminated, the #HCAS/#LCAS signal boot timing is 0.5 cycles before that of
#R A S. Consequently, t he pu lse width of #HCAS /#LC A S is determined by the refresh RAS pulse width that
was s et using RRA. The number of precharge cycles after the refresh cycle is defined by the value that was
set using RPRC, the same value that is used for both random cycles and page mode accesses.
Self-refresh
To support DRAM chips equipped with a self-refresh function, the BCU has a function to generate a self-
refresh cycle.
To star t a self-refresh cycle, set RPC2 to "1" after setting RPC1 to "1". To deactivate a self-refresh cycle,
write "0" to RPC1 or RPC2.
Exampl e: RPC delay: 1 cycle
Self-refresh mode set up Self-refresh mode
deactivationSelf-refresh mode
Refresh
RPC delay Fixed at
1 cycle Precharge cycle
(6 cycles)
BCLK
#RAS
#HCAS/
#LCAS
;;;;;;;
;;;;;;;
;;;;
;;;;
Figur e 4.37 Self-Refresh
For a self-refresh function as well, the RPC delay is determined by setting RPC0 in the same way as for a
CAS-before-RAS refresh.
The refresh RAS pulse width is determined by the timing at which the refresh is deactivated in software and
is unaffected by settings of RRA.
#R A S and #H CA S/#LCAS are booted up simultane ous ly upon c om ple tion of a self-refresh and the precharge
duration that follows is fixed at 6 cycles.
II CORE BLOCK: BCU (Bus Co ntrol Unit )
B-II-4-32 EPSON S1C33L03 FUNCTION PART
Normally, DRAM speci fications require that the contents of all row addresses be refreshed within a certain
time before and after a self-refresh. To meet this requirement, make sure a CAS-before-RAS refresh is
executed by a program. In this case, set the 8-bit programmable timer 0 so that the contents of all row
addresses are refreshed within a predetermined time.
Note: If read from or write to the DRAM under a self-refresh is attempted, the BCU keeps #RAS and
#H CAS/#LCAS low as it ex ecutes a read/write cycle. Other bus sig nals than #RAS and
#H CAS/#LCAS ( e.g., address, data, and contr o l sig nals) change their state according t o the
specified conditions. Since said attempt initiates an invalid access to the DRAM, do not read from
or write to the DRAM during a self-refresh.
Releasing External Bus
The external bus is normally controlled by the CPU, but the BCU is designed to release control of the bus
ow ners hip to an e xternal device. This function is enabled by writing "1" to SEMAS (D2) / Bus control register
(0x4812E) (disabled by default). The #BUSREQ (P34) and #BUSACK (P35) pins are used for control of the bus
ow ners hip. To direct the P34 and P35 pins for input/output of the #BUSREQ and #BUSACK signals, write "1" to
CFP34 (D 4) and CFP35 (D 5) / P3 f unction se le ct re gi st e r (0x4 02 D C [B y te]).
Sequence in which control of the bus is released
This sequence is descr ibed below.
1. Th e external bus mast er device requesting con trol of the bus owne rsh ip low ers the #BUSREQ pi n.
2. The CPU keeps monitoring t he status of the #BUSREQ pin, so that when this pin is lower, the CPU
terminates the bus cycle being executed and places the signals listed below in high-impedance state one
cycle later:
A[23:0], D[15:0], #R D , #W RL, #W RH , #HCA S, #LCAS, #CExx
Then the CPU lowe rs the #BUSACK pi n to inform the external device that control of the bus ownership
has been released.
3. One cycle later, the external bus starts its own bus cycle. The external bus master must hold the
#BUSREQ pin low until the bus cycle is completed.
4. Af ter comp leting the necessary bus cycles, the external bus master places the bus in high-impedance state
and releases the #BUSREQ pin back high.
5. Af ter confirming that the #BUSREQ pin is raised again, the CPU raises the #BUSACK pin one cycle
later and resu me s th e proces sing th at has b een susp en ded.
BCLK
#BUSREQ
#BUSACK
D[15:0]
A[23:0]
#RD, #WR
Synchronization
Synchronization
The S1C33
terminates the bus
cycle being executed. The S1C33
controls bus cycles.1 cycle 1 cycle
Hi-Z
1 cycle
The external bus master
controls bus cycles.
Figur e 4.38 External Bus Release Timing
If control of the bus ownership is requested during a DMA transfer by the internal DMA controller, the DMA
transfer under way is suspended at a break in data to accept the request for bus ownership control. The DMA
transfer that has been kept pending is restarted when the CPU gains control of the bus ownership.
II CORE BLOCK: BCU (Bus Co ntrol Unit )
S1C33L03 FUNCTION PART EPSON B-II-4-33
A-1
B-II
BCU
DRAM refresh when bus owners hip control is released
In systems where DRAM is connected directly, a refresh request could arise while control of the bus
ownership is released from the CPU. In such a case, take one of the corrective measures described below.
•Monitoring the output signal of the 8-bit programm able timer 0
The unde rflow signal (DRAM ref resh request) of t he 8-bit programm abl e timer 0 can be output from the P10
I/ O port pin.
If a refresh request arises while the external bus master is monitoring this output, release #BUSREQ back
high to drop the request for bus ownership control.
Start a DRAM refresh cycle when control of the bus ownership is returned to the CPU.
To direct the P10 pin in or der to output the underflo w signal of the 8-bit programmable timer 0, write "1" to
CFP10 (D 0) / P1 function select register (0x402D4 [Byte]) and IOC10 (D0) / P1 I/O control register
(0x402D6 [Byte]). Also, to output the underflow signal to an external device, write "1" to PTOUT0 (D2) / 8-
bit Timer 0 control register (0x40160 [Byte]). For details about output control, refer to "8-Bit Programmable
Timers".
•Monitorin g the #BUSGET si gnal
The #BUSGET signal can be output from the P31 I/O port pin.
The #BUSGET sig nal is derived from logical sum of the following signals:
1. DRAM refresh request signal (output from the 8-bit programmable timer 0)
2. Interrupt request signal from the interrupt controller to the CPU
3. Start up request signal from the interrupt controller to the IDMA
If the #BUSGET signal is found to be active when the external bus master is monitoring it, release #BUSREQ
back high to drop the request for bus own ership control.
When using the #BUSGET signal to only monitor a refresh request, set the interrupt controller in such a way
that no interrupt request or IDMA startup request will be generated.
To direct the P31 pin for output of t he #B USGET signal, write "1" to CFEX3 (D3) / Port function extension
register (0x402DF [Byte]).
Power-down Control by External Device
In addition to requesting the releasing of bus ownership control described above, it is possible to place the CPU in
a HALT state by using the #BUSREQ signal. This allows the CPU to be stopped during bus operation by an
external bus master in order to conserve power.
This fun ction is enabled by writing "1" to SEPD (D1) / Bus control register (0x4812E).
If SEPD = "1", the CPU and the BCU stop operating when the #BUSREQ pin is lowered, thus entering a HALT
state. This HALT state is not cleared by an interrupt from the internal peripheral circuits and remains set until the
#B U SREQ pin is released back high. U nlike in the case of ordinary releasing of the bus by #BUSREQ, the address
bus and bus control signals are not placed in high-impedance state.
For a DRAM refresh request that may arise in this HALT state, take one of the corrective measures described
above.
II CORE BLOCK: BCU (Bus Co ntrol Unit )
B-II-4-34 EPSON S1C33L03 FUNCTION PART
I/O Memory of BCU
Table 4.23 shows t he control bits of the BCU. These I/O memories are mapped into the area (0x48000 and
following addresses) used for the internal 16-bit peripheral circuits. However, these I/O memories can be accessed
in bytes or words, as well as in half-words.
For the control bits of the external system interface pins assigned to the I/O ports, and for details on how to control
the 8-bit programmable timer 0 in order to generate a DRAM refresh cycle, refer to each corresponding section in
this m an ua l.
Table 4.23 Control Bits of External System Interface
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
–
A18SZ
A18DF1
A18DF0
–
A18WT2
A18WT1
A18WT0
–
A16SZ
A16DF1
A16DF0
–
A16WT2
A16WT1
A16WT0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Areas 18–17 device size selection
Areas 18–17
output disable delay time
reserved
Areas 18–17 wait control
reserved
Areas 16–15 device size selection
Areas 16–15
output disable delay time
reserved
Areas 16–15 wait control
–
–
–
1 8 bits 0 16 bits
1 8 bits 0 16 bits –
0
1
1
–
1
1
1
–
0
1
1
–
1
1
1
–
R/W
R/W
–
R/W
–
R/W
R/W
–
R/W
0 when being read.
0 when being read.
0 when being read.
0 when being read.
0048120
(HW)
Areas 18–15
set-up register
1
1
0
0
1
0
1
0
A18DF[1:0] Number of cycles
3.5
2.5
1.5
0.5
1
1
0
0
1
0
1
0
A16DF[1:0] Number of cycles
3.5
2.5
1.5
0.5
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A18WT[2:0] Wait cycles
7
6
5
4
3
2
1
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A16WT[2:0] Wait cycles
7
6
5
4
3
2
1
0
–
A14DRA
A13DRA
A14SZ
A14DF1
A14DF0
–
A14WT2
A14WT1
A14WT0
DF–9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Area 14 DRAM selection
Area 13 DRAM selection
Areas 14–13 device size selection
Areas 14–13
output disable delay time
reserved
Areas 14–13 wait control
–
–
1 Used 0 Not used
1 Used 0 Not used
1 8 bits 0 16 bits
–
0
0
0
1
1
–
1
1
1
–
R/W
R/W
R/W
R/W
–
R/W
0 when being read.
0 when being read.
0048122
(HW)
1
1
0
0
1
0
1
0
A14DF[1:0] Number of cycles
3.5
2.5
1.5
0.5
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A14WT[2:0] Wait cycles
7
6
5
4
3
2
1
0
Areas 14–13
set-up register
II CORE BLOCK: BCU (Bus Co ntrol Unit )
S1C33L03 FUNCTION PART EPSON B-II-4-35
A-1
B-II
BCU
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
A12SZ
A12DF1
A12DF0
–
A12WT2
A12WT1
A12WT0
DF–7
D6
D5
D4
D3
D2
D1
D0
reserved
Areas 12–11 device size selection
Areas 12–11
output disable delay time
reserved
Areas 12–11 wait control
–
–
1 8 bits 0 16 bits –
0
1
1
–
1
1
1
–
R/W
R/W
–
R/W
0 when being read.
0 when being read.
0048124
(HW)
Areas 12–11
set-up register
1
1
0
0
1
0
1
0
A18DF[1:0] Number of cycles
3.5
2.5
1.5
0.5
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A18WT[2:0] Wait cycles
7
6
5
4
3
2
1
0
–
A10IR2
A10IR1
A10IR0
–
A10BW1
A10BW0
A10DRA
A9DRA
A10SZ
A10DF1
A10DF0
–
A10WT2
A10WT1
A10WT0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Area 10 internal ROM size
selection
reserved
Areas 10–9
burst ROM
burst read cycle wait control
Area 10 burst ROM selection
Area 9 burst ROM selection
Areas 10–9 device size selection
Areas 10–9
output disable delay time
reserved
Areas 10–9 wait control
–
–
–
1 Used 0 Not used
1 Used 0 Not used
1 8 bits 0 16 bits
–
1
1
1
–
0
0
0
0
0
1
1
–
1
1
1
–
R/W
–
R/W
R/W
R/W
R/W
R/W
–
R/W
0 when being read.
0 when being read.
0 when being read.
0048126
(HW)
1
1
0
0
1
0
1
0
A10BW[1:0] Wait cycles
3
2
1
0
1
1
0
0
1
0
1
0
A10DF[1:0] Number of cycles
3.5
2.5
1.5
0.5
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A10IR[2:0] ROM size
2MB
1MB
512KB
256KB
128KB
64KB
32KB
16KB
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A10WT[2:0] Wait cycles
7
6
5
4
3
2
1
0
Areas 10–9
set-up register
–
A8DRA
A7DRA
A8SZ
A8DF1
A8DF0
–
A8WT2
A8WT1
A8WT0
DF–9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Area 8 DRAM selection
Area 7 DRAM selection
Areas 8–7 device size selection
Areas 8–7
output disable delay time
reserved
Areas 8–7 wait control
–
–
1 Used 0 Not used
1 Used 0 Not used
1 8 bits 0 16 bits
–
0
0
0
1
1
–
1
1
1
–
R/W
R/W
R/W
R/W
–
R/W
0 when being read.
0 when being read.
0048128
(HW)
Areas 8–7
set-up register
1
1
0
0
1
0
1
0
A8DF[1:0] Number of cycles
3.5
2.5
1.5
0.5
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A8WT[2:0] Wait cycles
7
6
5
4
3
2
1
0
II CORE BLOCK: BCU (Bus Co ntrol Unit )
B-II-4-36 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
A6DF1
A6DF0
–
A6WT2
A6WT1
A6WT0
–
A5SZ
A5DF1
A5DF0
–
A5WT2
A5WT1
A5WT0
DF–E
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Area 6
output disable delay time
reserved
Area 6 wait control
reserved
Areas 5–4 device size selection
Areas 5–4
output disable delay time
reserved
Areas 5–4 wait control
–
–
–
1 8 bits 0 16 bits
–
1
1
–
1
1
1
–
0
1
1
–
1
1
1
–
R/W
–
R/W
–
R/W
R/W
–
R/W
0 when being read.
0 when being read.
0 when being read.
0 when being read.
004812A
(HW)
Areas 6–4
set-up register 1
1
0
0
1
0
1
0
A6DF[1:0] Number of cycles
3.5
2.5
1.5
0.5
1
1
0
0
1
0
1
0
A5DF[1:0] Number of cycles
3.5
2.5
1.5
0.5
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A6WT[2:0] Wait cycles
7
6
5
4
3
2
1
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A5WT[2:0] Wait cycles
7
6
5
4
3
2
1
0
RBCLK
–
RBST8
REDO
RCA1
RCA0
RPC2
RPC1
RPC0
RRA1
RRA0
–
SBUSST
SEMAS
SEPD
SWAITE
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BCLK output control
reserved
Burst ROM burst mode selection
DRAM page mode selection
Column address size selection
Refresh enable
Refresh method selection
Refresh RPC delay setup
Refresh RAS pulse width
selection
reserved
External interface method selection
External bus master setup
External power-down control
#WAIT enable
–
–
1 Fixed at H 0 Enabled
1
8-successive
0
4-successive
1 Enabled 0 Disabled
1 Self-refresh 0
CBR-refresh
1 2.0 0 1.0
1 #BSL 0 A0
1 Existing 0 Nonexistent
1 Enabled 0 Disabled
1 Enabled 0 Disabled
1 EDO 0 Fast page
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
–
R/W
R/W
R/W
R/W
Writing 1 not allowed.
Writing 1 not allowed.
004812E
(HW)
1
1
0
0
1
0
1
0
RCA[1:0] Size
11
10
9
8
1
1
0
0
1
0
1
0
RRA[1:0] Number of cycles
5
4
3
2
Bus control
register
II CORE BLOCK: BCU (Bus Co ntrol Unit )
S1C33L03 FUNCTION PART EPSON B-II-4-37
A-1
B-II
BCU
NameAddressRegister name Bit Function Setting Init. R/W Remarks
1 Successive 0 Normal
–
A3EEN
CEFUNC1
CEFUNC0
CRAS
RPRC1
RPRC0
–
CASC1
CASC0
–
RASC1
RASC0
DF–C
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Area 3 emulation
#CE pin function selection
Successive RAS mode setup
DRAM
RAS precharge cycles selection
reserved
DRAM
CAS cycles selection
reserved
DRAM
RAS cycles selection
– –
1
0
0
0
0
0
–
0
0
–
0
0
–
R/W
R/W
R/W
R/W
–
R/W
–
R/W
0 when being read.
0 when being read.
0 when being read.
0048130
(HW)
1
0
0
x
1
0
CEFUNC[1:0]
#CE output
#CE7/8..#CE17/18
#CE6..#CE17
#CE4..#CE10
1
1
0
0
1
0
1
0
RPRC[1:0] Number of cycles
4
3
2
1
–
1
1
0
0
1
0
1
0
CASC[1:0] Number of cycles
4
3
2
1
–
1
1
0
0
1
0
1
0
RASC[1:0] Number of cycles
4
3
2
1
DRAM timing
set-up register 1
Internal ROM
0 Emulation
–
1 Internal
access 0 External
access
1 Internal
access 0 External
access
1 Big endian 0
Little endian
A18IO
A16IO
A14IO
A12IO
–
A8IO
A6IO
A5IO
A18EC
A16EC
A14EC
A12EC
A10EC
A8EC
A6EC
A5EC
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Area 18, 17 internal/external access
Area 16, 15 internal/external access
Area 14, 13 internal/external access
Area 12, 11 internal/external access
reserved
Area 8, 7 internal/external
access
Area 6 internal/external
access
Area 5, 4 internal/external
access
Area 18, 17 endian control
Area 16, 15 endian control
Area 14, 13 endian control
Area 12, 11 endian control
Area 10, 9 endian control
Area 8, 7 endian control
Area 6 endian control
Area 5, 4 endian control
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.
0048132
(HW)
Access control
register
–
1 Enabled 0 Disabled
1 Enabled 0 Disabled
A18AS
A16AS
A14AS
A12AS
–
A8AS
A6AS
A5AS
A18RD
A16RD
A14RD
A12RD
–
A8RD
A6RD
A5RD
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Area 18, 17 address strobe signal
Area 16, 15 address strobe signal
Area 14, 13 address strobe signal
Area 12, 11 address strobe signal
reserved
Area 8, 7 address strobe signal
Area 6 address strobe signal
Area 5, 4 address strobe signal
Area 18, 17 read signal
Area 16, 15 read signal
Area 14, 13 read signal
Area 12, 11 read signal
reserved
Area 8, 7 read signal
Area 6 read signal
Area 5, 4 read signal
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
–
R/W
R/W
R/W
0 when being read.
0 when being read.
0048138
(HW)
G/A read signal
control register
–
1 Enabled 0 Disabled
1 Enabled 0 Disabled
–
A1X1MD
–
BCLKSEL1
BCLKSEL0
D7–4
D3
D2
D1
D0
reserved
Area 1 access-speed
reserved
BCLK output clock selection 1
1
0
0
1
0
1
0
BCLKSEL[1:0]
–
–BCLK
PLL_CLK
OSC3_CLK
BCU_CLK
CPU_CLK
0
0
0
0
0
–
R/W
–
R/W
0 when being read.
x2 speed mode only
0 when being read.
004813A
(B)
BCLK select
register 1 2 cycles 0 4 cycles
II CORE BLOCK: BCU (Bus Co ntrol Unit )
B-II-4-38 EPSON S1C33L03 FUNCTION PART
A18SZ:Areas 18–17 device siz e selection (DE) / Area s 18–1 5 set-up registe r (0x48120)
A16SZ:Areas 16–15 device siz e selection (D6) / Area s 18–1 5 set-up register (0x 48120 )
A14SZ:Areas 14–13 device siz e selection (D6) / Area s 14–1 3 set-up register (0x 48122 )
A12SZ:Areas 12–11 device siz e selection (D6) / Area s 12–1 1 set-up register (0x 48124 )
A10SZ:Areas 10–9 devi ce size selecti on ( D6) / Areas 10–9 set-up register (0x 48126 )
A8SZ:Areas 8–7 device size se lecti on (D6) / Areas 8–7 set-up register (0x 48128 )
A5SZ:Areas 5–4 device size se lecti on (D6) / Areas 6–4 set-up register (0x 4812A )
Select the size of the device connected to each area.
Write "1": 8 bits
Write "0": 1 6 bits
Read: Valid
A dev ice size can be selected for every two areas. An 8-bit size is selected by writing "1" to AxxSZ and a 16-bit
size is selected by writing "0" to AxxSZ. Area 6 has its first half (0x300000 through 0x37FFFF) fixed to an 8-bit
device and the last half (0x380000 through 0x3FFFFF) fixed to a 16-bit device.
At c old start, these bits are set to "0" (16 bits). At hot start, these bits retain their status before being initialized.
A18DF1–A18DF0:Ar ea s 18 –1 7 ou t put di s able de lay tim e (D[ D: C]) / Area s 18–1 5 se t -up r eg iste r ( 0x 48120 )
A16DF1–A16DF0:Ar ea s 16 –1 5 ou t put di s able de lay tim e (D[ 5: 4]) / Area s 18 –1 5 set -up r eg iste r (0x 481 20 )
A14DF1–A14DF0:Ar ea s 14 –1 3 ou t pu t dis able de lay tim e (D[ 5:4] ) / Area s 14 –13 se t -up r eg iste r (0x 481 22)
A12DF1–A12DF0:Ar ea s 12 –1 1 ou t put di s able de lay tim e (D[ 5: 4]) / Area s 12 –1 1 set -up r eg iste r (0x 481 24 )
A10DF1–A10DF0:Ar ea s 10 –9 out put dis ab le de l ay t im e ( D[5: 4] ) / Areas 10 –9 se t-u p r egis ter ( 0x481 26 )
A8DF1–A8DF0:Area s 8–7 ou t put dis ab le de l ay t ime ( D[ 5:4] ) / Ar eas 8– 7 se t-u p reg is ter ( 0x481 28 )
A6DF1–A6DF0:Area 6 ou tput dis ab le de l ay tim e ( D[D: C] ) / Area s 6–4 se t -up r eg iste r ( 0x 481 2A )
A5DF1–A5DF0:Area s 5–4 ou t put dis ab le de l ay t ime ( D[ 5:4] ) / Ar eas 6– 4 se t-u p reg is ter ( 0x481 2A )
Set the output-disable delay time. Table 4.24 Output Disable Delay Time
AxxDF1 AxxDF0 Delay time
113.5 cycles
102.5 cycles
011.5 cycles
000.5 cycles
When using a dev ice that has a long output-disable time, set a delay time to ensure that no contention for the data
bus occurs during the bus operation immediately after a device is read.
At c old start, these bits are set to "11" (3.5 cycles). At hot start, the bits retain their status before being initialized.
A18WT2–A18WT0:Areas 18–17 wa it control ( D [A:8]) / Areas 18–1 5 set-up registe r (0x48120)
A16WT2–A16WT0:Areas 16–15 wa it control ( D [2:0] ) / Areas 18–15 set-up regis ter (0x48120)
A14WT2–A14WT0:Areas 14–13 wa it control ( D [2:0] ) / Areas 14–13 set-up regis ter (0x48122)
A12WT2–A12WT0:Areas 12–11 wa it control ( D [2:0] ) / Areas 12–11 set-up regis ter (0x48124)
A10WT2–A10WT0:Areas 10–9 wait control (D[2:0]) / Areas 10–9 set-up register (0x48126)
A8WT2–A8WT0:Areas 8–7 wait control ( D[2:0]) / Areas 8–7 se t-up r egister (0x 48128 )
A6WT2–A6WT0:Area 6 wait control (D[A:8]) / Areas 6–4 set-up registe r (0x4812A)
A5WT2–A5WT0:Areas 5–4 wait control ( D[2:0]) / Areas 6–4 se t-up r egister (0x 4812A )
Set the number of wait cycles to be inserted when accessing an SRAM device.
The values 0 through 7 wr itten to the control bits equal the number of wait cycles inserted.
Note that the write cycle consists of a minimum of two cycles, so that a writing 0 or 1 is invalid.
When an SRAM device is connected, wait cycles derived via the #WAIT pin can also be inserted. In this case too,
the wait cycles set by AxxWT are valid.
The DRAM read/ write cycles do not have wait cycles inserted that are set by AxxWT or derived from the #WAIT
pin.
The bur st read cycle of a burst ROM (except for the first access) also does not have any wait cycle inserted. The
first read cycle of a burst ROM and the write cycle to the burst ROM area have wait cycles inserted that are set by
AxxWT. Wait c ycles derived from the #WAIT pin also can be inserted in the cycle for writing to the burst ROM
area.
At c old start, these bits are set to "111" (7 cycles). At hot start, the bits retain their status before being initialized.
II CORE BLOCK: BCU (Bus Co ntrol Unit )
S1C33L03 FUNCTION PART EPSON B-II-4-39
A-1
B-II
BCU
A14DRA:Area 14 DRAM selection (D8) / Area s 14–1 3 set-up registe r (0x48122)
A13DRA:Area 13 DRAM selection (D7) / A re as 14–13 set-up registe r (0x48122)
A8DRA:Area 8 DRAM selection (D8) / A re as 8– 7 set-up registe r (0x48128)
A7DRA:Area 7 DRAM selection (D7) / A re as 8– 7 set-up registe r (0x48128)
Select the DRAM direct interface.
Write "1": DRAM is used
Write "0": DRAM is not used
Read: Valid
When DRAM is used by connecting it directly to the BCU, write "1" to this bit. The ordinary SRAM interface is
selected by writing "0" to the control bit.
The a reas to wh ic h DRAM can be connected are areas 8 and 7 when the CEFUNC = "0", or areas 14 and 13 when
the bit = "1".
At c old start, these bits are set to "0" (DRAM not used). At hot start, the bits retain their status before being
initialized.
A10IR2–A10IR0: Area 10 internal ROM size selection (D[E:C]) / Areas 10–9 set-up register (0x48126)
Select an area 10 internal/emulation memory size.
Table 4.25 Area 10 Internal ROM Size
A10IR2 A10IR1 A10IR0 ROM size
000 16 KB
001 32 KB
010 64 KB
011 128 KB
100 256 KB
101 512 KB
110 1 MB
111 2 MB
At c old start, A10IR is set to "111" (2 MB). At hot start, A10IR retains its status before being initialized.
A10BW1–A10BW0: Burst read cycle wait control (D[A:9]) / Areas 10–9 set-up register (0x48126)
Set the number of wait cycles inserted during a burst read.
The values 0 to 3 written to the bits constitute the number of wait cycles inserted. The contents set here are applied
to both areas 10 and 9. The wait cycles set by AxxWT are inserted in the first read cycle of burst ROM and in the
burst ROM write cycle. For the burst ROM write cycle, the wait cycles set via the #WAIT pin can also be used.
At c old start, A10BW is set to "0" (no wait cycle). At hot start, A10BW retains its status before being initialized.
II CORE BLOCK: BCU (Bus Co ntrol Unit )
B-II-4-40 EPSON S1C33L03 FUNCTION PART
A10DRA:Area 10 burst ROM selection (D8) / Areas 10–9 set-up register (0x48126)
A9DRA:Area 9 burst ROM selection (D7) / Areas 10–9 set-up register (0x48126)
Set areas 10 and 9 for use of burst ROM.
Write "1": B urst ROM is used
Write "0": Bur st ROM is not used
Read: Valid
When using burst ROM, write "1" to the control bit. The ordinary SRAM interface is selected by writing "0" to the
bit.
Area 9 can only be used when the CEFUNC = "00".
At c old start, these bits are set to "0" (burst ROM not used). At hot start, the bits retain their status before being
initialized.
RBCLK: BCLK output control (DF) / Bus control regis ter (0x4812E)
Control the bus clock BCLK to enable or disable external output.
Write "1": Fixed at high level
Write "0": Out put enabled
Read: Valid
To stop outputting the bus clock from the BCLK pin, write "1" to RBCLK. When the clock output is stopped, the
BC LK pin is fixed at high level. The bus clock output from the BCLK pin is enabled by writing "0" to RBCLK.
The bus clock output from the BCLK pin also is stopped in the HALT2 and the SLEEP modes.
At c old start, the RBCLK is set to "0" (output enabled). At hot start, RBCLK retains its status before being
initialized.
RBST8: Burst mode selection (DD) / Bus cont rol register (0x4812E)
Set the operation mode during a burst read.
Write "1": 8 -successive-b urst m od e
Write "0": 4 -successive-b urst m od e
Read: Valid
The 8-successive-burst mode is selected by wr iting "1" to RB ST8 a nd the 4-successive-burst mo de is selected by
writing "0" to RBST8. This setting is valid when areas 10 and 9 are set for burst ROM, and the setting is applied to
both areas simultaneously.
At c old start, RBST8 is set to "0" (4-successive-burst mode). At hot start, RBST8 retains its status before being
initialized.
REDO: Page mode se lection (DC) / Bus contr ol registe r (0x4812E)
Select the page mo de of DR A M .
Write "1": EDO-page mode
Write "0": Fast-page mode
Read: Valid
When using EDO DRAM, write "1" to REDO to select the EDO-page mode.
The con tents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM.
At cold start, REDO i s set to "0" (fast-page mode). At hot start, REDO retains its status before being initialized.
II CORE BLOCK: BCU (Bus Co ntrol Unit )
S1C33L03 FUNCTION PART EPSON B-II-4-41
A-1
B-II
BCU
RCA1–RCA0: Column address size selection (D[B:A]) / Bus control register (0x4812E)
Select the column address size of DRAM.
Table 4.26 Column Address Size
RCA1 RCA0 Column address size
11 11
10 10
01 9
00 8
The con tents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM.
RC A can be read to obtain its set value.
At c old start, RCA is set to "0" (8 bits). At hot start, RCA retain its status before being initialized.
RPC2: Refre sh enable (D9) / Bus control r egister (0x 4812E )
Control the DRAM refresh function.
Write "1": Ena bled
Write "0": Disabl ed
Read: Valid
When DRAM is connected directly, a refresh cycle is generated by writing "1" to RPC2. The internal refresh
function is disabled by writing "0" to RPC2.
Since the BCU stops operating in the HALT2 and the SLEEP modes, no refresh cycle is generated regardless of
how this bit is set.
The con tents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM.
At c old start, RPC2 is set to "0" (disabled). At hot start, RPC2 retains its status before being initialized.
RPC1: Refre sh me thod selecti on (D8) / Bus control r egister (0x 4812E)
Select the DRAM refresh method.
Write "1": Self-refresh
Write "0": CAS-before-RAS refresh
Read: Valid
To perform a CAS- before-RAS refresh, set RPC1 to "0" and then RPC2 to "1". This causes the underflow output
signal of the 8-bit programmable timer 0 is fed to the DRAM interface, at which timing a refresh cycle is
generated.
To star t a self-refresh, set RPC1 to "1" and then RPC2 to "1". The self-refresh is disabled by writing "0" to RPC2.
The con tents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM.
At c old start, RPC1 is set to "0" (CAS-before-RAS refresh). At hot start, RPC1 retains its status before being
initialized.
RPC0: Refre sh RPC delay (D7) / Bus contr ol register (0x4812E)
Set a RPC delay when at start of refresh.
Write "1": 2 cycles
Write "0": 1 cycle
Read: Valid
Set a time from the immediately preceding precharge to the falling transition of #HCAS/#LCAS necessary in order
to perform a refresh. This time is 2 cycles when RPC0 = "1" or 1 cycle when RPC0 = "0".
The con tents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM.
At c old start, RPC0 is set to "0" (1 cycle). At hot start, RPC0 retains its status before being initialized.
II CORE BLOCK: BCU (Bus Co ntrol Unit )
B-II-4-42 EPSON S1C33L03 FUNCTION PART
RRA1–RRA0: Refresh RAS pu lse widt h selection (D[6: 5]) / Bus co ntrol register (0x4812E)
Select the RAS pulse width of a CAS-before-RAS refresh.
Table 4.27 Refresh RAS Pulse Width
RRA1 RRA0 Pulse width
11 5 cycles
10 4 cycles
01 3 cycles
00 2 cycles
The con tents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM.
The RRA c an be read to obtain their set value.
At c old start, RRA is set to "0" (2 cycles). At hot start, RRA retains its status before being initialized.
SBUSST: Ext erna l inte rface method select r e gister ( D 3) / Bus contr ol register (0x 4812E )
Select the interface method of an SRAM device.
Write "1": # BSL system
Write "0": A0 system
Read: Valid
When using the #BSL system, write "1" to SBUSST.
The con tents set here are applied to all areas that are set for the SRAM type.
At c old start, SBUSST is set to "0" (A0 system). At hot start, SBUSST retains its status before being initialized.
SEMAS: External bus ma ster setup ( D 2) / Bus control r egister (0x 4812E)
Speci fy wh ether an ex ternal bus master exists.
Write "1": Existing
Write "0": Nonex istent
Read: Valid
A req uest for bus ownersh ip con trol via the #BUSREQ pi n is ma de a cceptable by writing "1" to SEMAS. If the
system does not have any external bus master, fix this register at "0".
At c old start, SEMAS is set to "0" (nonexistent). At hot start, SEMAS retains its status before being initialized.
SEPD: External power- down co ntrol (D1) / Bus control r egister (0x 4812E )
Enabl e or disable the CPU 's po w er-down control by an external bus master.
Write "1": Ena bled
Write "0": Disabl ed
Read: Valid
Power-down control via an external pin (#BUSREQ) is enabled by writing "1" to SEPD. If the #BUSREQ pin is
lowered when external power-down control is thus enabled, the CPU is placed in a HALT state, allowing for
reduction in power consumption.
At c old start, SEPD is set to "0" (disabled). At hot start, SEPD retains its status before being initialized.
II CORE BLOCK: BCU (Bus Co ntrol Unit )
S1C33L03 FUNCTION PART EPSON B-II-4-43
A-1
B-II
BCU
SWAITE: #WAI T enable (D0) / Bus control register (0x4812E )
Enabl e or disable wait cycle control via the #WAIT pin.
Write "1": Ena bled
Write "0": Disabl ed
Read: Valid
A wait request from an SRAM device is made acceptable by writing "1" to SWAITE. The wait request signal input
from the #WAIT pin is sampled at each falling edge of the bus clock when executing an SRAM read/write cycle.
Wait cycles are inserted until the wait request signal is sampled and detected as high (inactive).
Wait control for 0 to 7 cycles can be accomplished by AxxWT without using the #WAIT pin. However, since the
setting via AxxWT is applied to every two areas, the number of wait cycles may be controlled individually in each
area or more than 7 wait cycles may be set. In such a case, use an external wait request via the #WAIT pin.
Wait requests from the #WAIT pin are ignored when SWAITE = "0".
The con tents set here are applied to all areas that are set for SRAM, and are also effective for write cycles in the
areas that are set for burst ROM.
At c old start, SWAITE is set to "0" (disabled). At hot start, SWAITE retains its status before being initialized.
A3EEN: Are a 3 emulation (DB) / DRAM timin g set-up reg ister (0x48130)
Select area 3 emulation mode.
Write "1": Inte rnal ROM mode
Write "0": Emula tion mode
Read: Valid
When "0" is written to A3EEN, internal ROM emulation mode is selected and the external device will be accessed
with the same condition as the internal ROM. When "1" is written, the internal ROM will be used for accessing
area 3. This bit functions the same as the EA3MD pin. The bit status and the pin status are logically ORed.
At cold start, A3EEN is set to "1" (internal ROM mode). At hot start, A3EEN retains its status before being
initialized.
CEFUNC1–CEFUNC0: #CE pin function selection (D[A:9]) / DRAM timing set-up register (0x48130)
Change the #CE pin-assigned area.
Table 4.28 #CE Output Assignment
PinCEFUNC = "00" CEFUNC = "01" CEFUNC = "1x"
#CE4 #CE4 #CE11 #CE11+#CE12
#CE5 #CE5 #CE15 #CE15+#CE16
#CE6 #CE6 #CE6 #CE7+#CE8
#CE7/#RAS0 #CE7/#RAS0 #CE13/#RAS2 #CE13/#RAS2
#CE8/#RAS1 #CE8/#RAS1 #CE14/#RAS3 #CE14/#RAS3
#CE9 #CE9 #CE17 #CE17+#CE18
#CE10EX #CE10EX #CE10EX #CE9+#CE10EX
(Default: CEFUNC = "00")
The high-order areas that are made available for use by writing "01" to CEFUNC can be larger in size than the
default low-order areas. For example, when using DRAM in default settings, the available space is 4 MB in areas 7
and 8. However, if areas 13 and 14 are used, up to 32 MB of DRAM can be used. The same applies to the other
areas.
Furthermore, when CEFUNC is set to "10" or "11", four chip enable signal is expanded into two area size.
At c old start, CEFUNC is set to "00". At hot start, CEFUNC retains its status before being initialized.
II CORE BLOCK: BCU (Bus Co ntrol Unit )
B-II-4-44 EPSON S1C33L03 FUNCTION PART
CRAS: Successive RAS m ode (D8) / DRAM timi ng set-up register (0x48130)
Set the successive RAS mode.
Write "1": Successive RAS mode
Write "0": N ormal mode
Read: Valid
In systems using DRAM, the successive RAS mode is entered by writing "1" to CRAS. In this mode, read/write
operations can be performed in page mo de eve n when DR AM accesses do not occur back-to-back.
When using the successive RAS mode, be sure to use #DRD for the read signal and #DWE for the write signal for
low-byte.
When CRAS = "0", random read/write cycles are used for non-successive DRAM accesses.
The con tents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM.
At c old start, CRAS is set to "0" (normal mode). At hot start, CRAS retains its status before being initialized.
RPRC1–RPRC0: Number of RAS precharge cycles (D[7:6]) / DRAM timing set-up register (0x48130)
Select the number of precharge cycles during a DRAM access.
Table 4.29 Number of RAS Precharge Cycles
RPRC1 RPRC0 Number of cycles
11 4 cycles
10 3 cycles
01 2 cycles
00 1 cycle
The con tents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM.
At cold start, RPRC is set to "0" (1 cycle). At hot start, RPRC retains its status before being initialized.
CASC1–CASC0: Number of CAS cycles (D[4:3]) / DRAM timing set-up register (0x48130)
Select the number of CAS cycles during a DRAM access.
Table 4.30 Number of CAS Cycles
CASC1 CASC0 Number of cycles
11 4 cycles
10 3 cycles
01 2 cycles
00 1 cycle
The con tents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM.
At c old start, CASC is set to "0" (1 cycle). At hot start, CASC retains its status before being initialized.
RASC1–RASC0: Number of RAS cycles (D[1:0]) / DRAM timing set-up register (0x48130)
Select the number of RAS cycles during a DRAM access.
Table 4.31 Number of RAS Cycles
RASC1 RASC0 Number of cycles
11 4 cycles
10 3 cycles
01 2 cycles
00 1 cycle
The con tents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM.
At c old start, RASC is set to "0" (1 cycle). At hot start, RASC retains its status before being initialized.
II CORE BLOCK: BCU (Bus Co ntrol Unit )
S1C33L03 FUNCTION PART EPSON B-II-4-45
A-1
B-II
BCU
A18IO:Areas 18–17 internal/external access selection (DF) / Access control register (0x48132)
A16IO:Areas 16–15 internal/external access selection (DE) / Access control register (0x48132)
A14IO:Areas 14–1 3 inter nal/external access selecti on (DD) / Access control register ( 0x481 32)
A12IO:Areas 12–11 internal/external access selection (DC) / Access control register (0x48132)
A8IO:Areas 8–7 internal/external access selection (DA) / Access control register (0x48132)
A6IO:Area 6 internal/external access selecti on (D 9) / Access control regis ter (0x48132)
A5IO:Areas 5–4 internal/external access selection (D8) / Access control register (0x48132)
Select either internal access or external access for each area.
Write "1": Inte rnal access
Write "0": Extern al access
Read: Valid
When AxxIO is set to "1", the internal device that mapped to the corresponding area is accessed. When AxxIO is
set to "0", the external device is accessed.
At c old start, these bits are set to "0" (external access). At hot start, these bits retain their status before being
initialized.
A18EC:Areas 18–17 little/big endian meth od selection (D7) / Access control r egister (0x48132)
A16EC:Areas 16–15 little/big endian meth od selection (D6) / Access control r egister (0x48132)
A14EC:Areas 14–13 little/big endian meth od selection (D5) / Access control r egister (0x48132)
A12EC:Areas 12–11 little/big endian meth od selection (D4) / Access control r egister (0x48132)
A10EC:Areas 10–9 little/big endian method selection (D3) / Access control register (0x48132)
A8EC:Areas 8–7 little/bi g endian method selection ( D2) / Access control register (0x48132)
A6EC:Area 6 little/big endian method selection (D1) / Access control register (0x48132)
A5EC:Areas 5–4 little/bi g endian method selection ( D0) / Access control register (0x48132)
Select either little endian or big-endian method for accessing each area.
Write "1": Big-endian
Write "0 ": Littl e-end ian
Read: Valid
When AxxEC is set to "1", the corresponding area is accessed in big-endian method. When AxxEC is set to "0",
the area is accessed in little-endian method. When using area 10 as the boot area, fix A10EC at "0" (little-endian).
At co ld st art, these bits are set to "0" (little-endian). At hot start, these bits retain their status before being
initialized.
A18AS:Areas 18–17 address strobe signal (DF) / G/A r ead signa l control r egister (0x 48138 )
A16AS:Areas 16–15 address strobe signal (DE) / G/A r ead signal control r egister (0x 48138 )
A14AS:Areas 14–13 address strobe signal (DD) / G/A read signal control reg ister (0x48138)
A12AS:Areas 12–11 address strobe signal (DC) / G/A read signal control reg ister (0x48138)
A8AS:Areas 8–7 address str obe signa l ( DA) / G/A read signal control register (0x48138)
A6AS:Area 6 address strobe signal ( D 9) / G/A read signal control register (0 x48138)
A5AS:Areas 5–4 address str obe signa l (D8) / G/A read signal control register (0x48138)
Enable/disable the exclusive address strobe signal output.
Write "1": Ena bled
Write "0": Disabl ed
Read: Valid
If AxxAS is set to "1", the exclusive address strobe signal is output from #GAAS (P21) pin when the
corresponding area is accessed. If AxxAS is set to "0", the signal output is disabled.
At c old start, these bits are set to "0" (disabled). At hot start, these bits retain their status before being initialized.
II CORE BLOCK: BCU (Bus Co ntrol Unit )
B-II-4-46 EPSON S1C33L03 FUNCTION PART
A18RD:Areas 18–17 read signal (D7) / G/A read signal control register (0x48138)
A16RD:Areas 16–15 read signal (D6) / G/A read signal control register (0x48138)
A14RD:Areas 14–13 read signal (D5) / G/A read signal control register (0x48138)
A12RD:Areas 12–11 read signal (D4) / G/A read signal control register (0x48138)
A8RD:Areas 8–7 rea d signal (D2) / G/A read signal control register (0x48138)
A6RD:Area 6 read signal (D1) / G/A read signal control register (0x48138)
A5RD:Areas 5–4 rea d signal (D0) / G/A read signal control register (0x48138)
Enable/disable the exclusive read signal output.
Write "1": Ena bled
Write "0": Disabl ed
Read: Valid
If AxxRD is set to "1", the exclusive read signal is output from #GARD (P31) pin when the corresponding area is
read. If AxxRD is set to "0", the signal output is disabled.
At c old start, these bits are set to "0" (disabled). At hot start, these bits retain their status before being initialized.
BCLKSEL1–BCLKSEL0: BCLK output clock selection (D[1:0]) / BCLK select register (0x4813A)
Select a clock to be output from the BCLK pin. These bits are effective only when SDRENA (D7/0x39FFC1) is
"0". Table 4.32 Selection of BCLK Output Clock
SDRENA BCLKSEL1 BCLKSEL0 Output clock
11PLL_CLK (PLL output clock)
10OSC3_CLK (OSC3 oscillation clock)
01BCU_CLK (BCU o perating clock)
0
00CPU_CLK (CPU operating clock)
1––SD_CLK (SDRAM clock)
PLL_CLK: PLL outpu t clock. This clock is stable and kept as output except in the following cases:
1. When the PLL is off by setting the PLLS[1:0] pins.
2. When the OSC3 (high-speed) oscillation is stopped by executing the SLP instruction.
3. When the OSC3 (high-speed) oscillation is stopped using the CLG register.
Note that the PLL_CLK clock is out of phase with the CPU operating clock.
OSC3_CLK: OSC3 (high-speed) oscillation circuit output clock. This clock is stable and kept as output except in
the following cases:
1. When the OSC3 (high-speed) oscillation is stopped by executing the SLP instruction.
2. When the OSC3 (high-speed) oscillation is stopped using the CLG register.
Note that the OSC3_CLK clock is out of phase with the CPU operating clock.
BCU_CLK: Bus c lock in t he bus controller. This clock varies according to the bus cycle speed. Furthermore, the
clock frequency changes dynamically in x2 speed mode as follows:
1. When the internal RAM/ROM is accessed, x2 clock (e.g., 50 MHz same as the CPU operating
clock) is output.
2. When an external device is accessed via the external bus, x1 clock (e.g., 25 MHz) is output.
This dynami c change (e.g., between 50 MHz and 25 MHz) does not affect the external memory
access timing, such as position relationship between the rising or falling edge of the 25 MHz clock
and the falling edge of the #WR signal. (It is the same as that in the x1 speed mode with 25 MHz
clock.)
CPU_CLK: The CPU operating clock. The clock frequency is as follows:
1. Equals to the PLL output clock frequency when the PLL is on.
2. Equals to the OSC3 (high-speed) oscillation circuit output clock frequency when the PLL is off.
3. However, it equals to the divided frequency when the CLG is set to generate the CPU operating
clock by dividing the source clock.
4. When the CPU stops by the HALT or SLP i nstruction, this clock is also stopped.
This clock is almost in phase with the bus clock.
At i nitial reset, BCLKSEL is set to "00" (CPU_CLK).
II CORE BLOCK: BCU (Bus Co ntrol Unit )
S1C33L03 FUNCTION PART EPSON B-II-4-47
A-1
B-II
BCU
SDRENA: Enabl e SDRAM si gnal s (D7) / S DR A M control register (0 x39FFC 1)
Enable the pins used for the SDRAM.
Write "1": Ena bled
Write "0": Disabl ed
Read: Valid
Writing "1" to SDRENA sets the pins shared with other functions to be used for the SDRAM, with the SDRAM
clock output from the BCLK pin. If SDRENA = "0", the shared pins serve other functions.
The SDRAM clock output from the BCLK pin is stopped in the HALT2 and the SLEEP modes.
At c old start, SDRENA is set to "0" (disabled). At hot start, SDRENA retains its status before being initialized.
A1X1MD: Area 1 ac cess speed (D 3) / BCLK select register (0x4813A )
Select a number of access cycles for area 1 in x2 speed mode.
Write "1": 2 cycles
Write "0": 4 cycles
Read: Valid
When x2 speed mode is set (#X2SPD pin = "0") and A1X1MD = "1", area 1 is read/written in 2 cycles of the CPU
system clock.
When A1X1MD = "0", area 1 is read/written in 4 cycles.
When x1 speed mode is set ( #X 2SP D pin = "1"), a rea 1 is a lway s accessed in 2 cycles regardless of the A1X1MD
value.
At c old start, A1X1MD i s s et to "0" (4 cycles). At hot start, A1X1MD retains its status before being initialized.
II CORE BLOCK: BCU (Bus Co ntrol Unit )
B-II-4-48 EPSON S1C33L03 FUNCTION PART
TH IS PAGE IS BLANK.
II CORE BLOCK: ITC (In t errupt Controller)
S1C33L03 FUNCTION PART EPSON B-II-5-1
A-1
B-II
ITC
II-5 ITC (In t errupt Co ntroller)
The C33 Core Bloc k conta ins an i nterr upt cont ro ll e r, mak ing i t possible to control all interrupts generated by
the internal peripheral circuits. This section explains the functions of this interrupt controller centering around the
method for controlling maskable interrupts. For details about the various factors and conditions under which
interrupts are generated, refer to the description of each peripheral circuit in this manual.
Outline of Interrupt Functions
Maskable Interrupts
The ITC c an handle 39 kinds of m ask able interrupts as shown in the table below.
Table 5.1 List of Maskable Interrupts
No
.
HE
X
No
.
Vector numbe
r
(Hex address
)
Inter rupt system
(Peripheral circ uit ) Interrupt factor IDMA
Ch. Priorit
y
11016(Base+40) Port input interrupt 0 Edge (rising or falling) or level (High or Low) 1 High
21117(Base+44) Port input interrupt 1 Edge (rising or falling) or level (High or Low) 2 ↑
31218(Base+48) Port input interrupt 2 Edge (rising or falling) or level (High or Low) 3
41319(Base+4C) Port input interrupt 3 Edge (rising or falling) or level (High or Low) 4
51420(Base+50) Key input interrupt 0 Rising or falling edge –
61521(Base+54) Key input interrupt 1 Rising or falling edge –
71622(Base+58) High-speed DMA Ch.0 High-speed DMA Ch.0, end of transfer 5
81723(Base+5C) High-speed DMA Ch.1 High-speed DMA Ch.1, end of transfer 6
91824(Base+60) High-speed DMA Ch.2 High-speed DMA Ch.2, end of transfer –
10 19 25(Base+64) High-speed DMA Ch.3 High-speed DMA Ch.3, end of transfer –
11 1A 26(Base+68) IDMA Intelligent DMA, end of transfer –
–27–29 reserved – –
12 1E 30(Base+78) 16-bit programmable timer 0 Timer 0 comparison B 7
13 1F 31(Base+7C) Timer 0 comparison A 8
–32–33 reserved – –
14 22 34(Base+88) 16-bit programmable timer 1 Timer 1 comparison B 9
15 23 35(Base+8C) Timer 1 comparison A 10
–36–37 reserved – –
16 26 38(Base+98) 16-bit programmable timer 2 Timer 2 comparison B 11
17 27 39(Base+9C) Timer 2 comparison A 12
–40–41 reserved – –
18 2A 42(Base+A8) 16-bit programmable timer 3 Timer 3 comparison B 13
19 2B 43(Base+AC) Timer 3 comparison A 14
–44–45 reserved – –
20 2E 46(Base+B8) 16-bit programmable timer 4 Timer 4 comparison B 15
21 2F 47(Base+BC) Timer 4 comparison A 16
–48–49 reserved – –
22 32 50(Base+C8) 16-bit programmable timer 5 Timer 5 comparison B 17
23 33 51(Base+CC) Timer 5 comparison A 18
24 34 52(Base+D0) 8-bit programmable timer Timer 0 underflow 19
25 35 53(Base+D4) Timer 1 underflow 20
26 36 54(Base+D8) Timer 2 underflow 21
27 37 55(Base+DC) Timer 3 underflow 22
28 38 56(Base+E0) Serial interface Ch.0 Receive error –
29 39 57(Base+E4) Receive buffer full 23
30 3A 58(Base+E8) Transmit buffer empty 24
–59 reserved – –
31 3C 60(Base+F0) Serial interface Ch.1 Receive error –
32 3D 61(Base+F4) Receive buffer full 25
33 3E 62(Base+F8) Transmit buffer empty 26
–63 reserved – –
34 40 64(Base+100) A/D converter A/D converter, end of conversion 27
35 41 65(Base+104) Clock timer Falling edge of 32 Hz, 8 Hz, 2 Hz or 1 Hz signal
1-minuet, 1-hour or specified time count up –
–66–67 reserved – –
36 44 68(Base+110) Port input interrupt 4 Edge (rising or falling) or level (High or Low) 28
37 45 69(Base+114) Port input interrupt 5 Edge (rising or falling) or level (High or Low) 29
38 46 70(Base+118) Port input interrupt 6 Edge (rising or falling) or level (High or Low) 30 ↓
39 47 71(Base+11C
)
Port input interrupt 7 Edge (rising or falling) or level (High or Low) 31 Low
II CORE BLOCK: ITC (In t errupt Controller)
B-II-5-2 EPSON S1C33L03 FUNCTION PART
Contents of table
"Hex No." indicates an interrupt number in hexadecimal value.
"Vector number (Address)" indicates the trap table's vector number. The numerals in parentheses show an
offset (in bytes) from the starting address (Base) of the trap table. The starting address (Base) of the trap table
by default is the boot address, 0xC00000 set at an initial reset. This address can be changed using the TTBR
register (0x48134 to 0x48137).
For details about the trap table contents including exception factors, etc., refer to the "S1C33000 Core CPU
Manual".
"Interrupt system (Peripheral circuit)" indicates that interrupt levels can be programmed for each peripheral
circuit written.
"Interrupt factor" indicates the factor of the interrupt occurring in each interrupt system.
"IDMA Ch." indicates that an interrupt factor which has a numeric value in this column can start up the
intelligent DMA (IDMA) to transfer data when an interrupt factor occurs. The numeric value indicates the
IDMA's channel number. Interrupt factors that do not have a numeric value here cannot start up the IDMA.
"Priority" indicates the priority of interrupts in cases when all interrupt systems are set to the same interrupt
level. If two or more interrupt factors occur simultaneously, interrupt requests are accepted in order of highest
priority. Interrupt priority varies depending on the interrupt levels set in each interrupt system. However, the
prioritie s of interrupt factors in the same interrupt system are fixed in the order that they are written here.
Maskable interrupt generating conditions
A mask ab le interrupt to the CPU occurs when all of the conditions described below are met.
•The interrupt enable register for the interrupt factor that has occurred is set to "1".
•The IE (Interrupt Enable) bit of the Processor Status Register (PSR) in the CPU is set to "1".
•The interrupt factor that has occurred has a higher priority level than the value that is set in the PSR's
Interrupt Level (IL). (The interrupt levels can be set using the interrupt priority register in each interrupt
system.)
•No other trap factor having higher priority, such as NMI, has occurred.
•The interrupt factor does not invoke IDMA (the IDMA request bit is set to "0").
When an interrupt factor occurs, the corresponding interrupt factor flag is set to "1" and the flag remains set
until it is reset in the software program. Therefore, in no cases can the generated interrupt factor be
inadvertently cleared even if the above conditions are not met when the interrupt factor has occurred. The
interrupt will occur when the above conditions are met.
However, wh en the interrupt factor invokes IDMA, the interrupt factor is reset if the following condition is
met.
•The IDMA transfer counter is not "0".
•Interrupts are disabled in the IDMA control information even if the transfer counter is "0".
If two or more maskable interrupt factors occur simultaneously, the interrupt factor that has the highest
priority is allowed to signal an interrupt request to the CPU. The other interrupts with lower priorities are kept
pending until the abov e co nditions are met .
The PSR a nd interrupt control register will be detailed later.
For details about interrupt factor generating conditions, refer to the description of each peripheral circuit in
this m an ua l.
II CORE BLOCK: ITC (In t errupt Controller)
S1C33L03 FUNCTION PART EPSON B-II-5-3
A-1
B-II
ITC
Interrupt Factors and Intelligent DMA
Several interrupt factors can be set so that they can invoke IDMA startup. When one of these interrupt factors
occurs, IDM A is started up before an interrupt request to the CPU. The interrupt request to the CPU is generated
after IDMA is completed. (The interrupt request can be disabled by a program.)
IDMA is always started up regardless of how the PSR is set. For details, refer to "IDMA Invocation".
Nonmaskable Interrupt (NMI)
The nonmaskable interrupt (NMI) can be generated by pulling the #NMI pin low or using the internal watchdog
timer. The vector number of NMI is 7, with the vector address set to the trap table's starting address + 28 bytes.
This interrupt is prioritized over other interrupts and is unconditionally accepted by the CPU.
However, s in ce this interrupt may operate erratically if it occurs before the stack pointer (SP) is set up, it is masked
in hardware until a write to the SP is completed after an initial reset.
Interrupt Processing by the CPU
The CPU keeps sa m pli ng inte rru pt requ ests every cycl e. W he n th e CPU acce pts an inte rru pt requ est, it enters tr ap
processing after completing execution of the instruction that was being executed.
The following lists the contents executed in trap processing.
(1) The PSR and the current program counter (PC) value are saved to the stack.
(2) The IE bit of the PSR is reset to "0" (following maskable interrupts are disabled).
(3) The IL of the PSR is set to the priority level of the accepted interrupt (NMI does not have its interrupt level
changed).
(4) The vector of the generated interrupt factor is loaded into the PC, thus executing the interrupt processing
routine.
Thus, once an interrupt is accepted, all maskable interrupts that may follow are disabled in (2). Multiple interrupts
can also be handled by setting the IE bit to "1" in the interrupt processing routine. In this case, since the IL has
been changed in (3), only an interrupt that has a higher priority than that of the currently processed interrupt is
accepted.
When the interrupt processing routine is terminated by the reti instruction, the PSR is restored to its previous status
before the interrupt has occurred. The program restarts processing after branching to the instruction next to the one
that was being executed when the interrupt occurred.
Clearing Standby Mode by Interrupts
The standby modes (HALT and SLEEP) are cleared by an NMI or a maskable interrupt.
All maskable interrupts can be used to clear HALT mode. However, if the bus clock has stopped in HALT2 mode,
a DM A in te rrupt cannot be used .
In SLEEP mode, since the high-speed (OSC3) oscillation circuit is deactivated, interrupts from the peripheral
circuits that operate with the OSC3 clock cannot be used.
Interrupts that can be used to clear basic HALT mode: NMI and all maskable interrupts
Interrupts that can be used to clear HALT2 mode: NMI and all maskable interrupts (except DMA interrupts)
Interrupts that can be used to clear SLEEP mode: NMI, input port interrupts, and clock timer interrupts
Clearing of t he s tandby mo des is accomplished by an interrupt request to the CPU. Therefore, this requires that the
PSR be set in such a way that the requested interrupt will be accepted, and that the interrupt enable register for the
interrupt factor be set to accept the interrupt.
When st andby mode is cleared and the CPU has accepted the interrupt, it returns to the instruction next to the halt
or slp instruction after executing the interrupt processing routine.
Note: If the interrupt factor used to restart from the standby mode has been set to invoke the IDMA, the
IDMA is started up by that interrupt.
In the case of SLEEP mode, the high-speed (OSC3) oscillation circuit also starts operating.
If an interrupt to be gene ra ted up on compl e tio n of I DMA i s dis ab led at the set tin g of t he IDMA si de,
no interrupt request is si gna led to the CPU. Therefore, the CPU remains idle until the next
interrupt request is generated.
II CORE BLOCK: ITC (In t errupt Controller)
B-II-5-4 EPSON S1C33L03 FUNCTION PART
Trap Table
The C33 Core Bloc k allows the base (starting) address of the trap table to be set by the TTBR register.
TTBR0 (D[9:0]) / TTBR low-order register (0x48134): Trap table base address [9:0] (fixed at "0")
TTBR1 (D[F:A]) / TTBR low-order register (0x48134): Trap table base address [15:10]
TTBR2 (D[B:0]) / TTBR high-order register (0x48136): Trap table base address [27:16]
TTBR3 (D[F:C]) / TTBR high-order register (0x48136): Trap table base address [31:28] (fixed at "0")
Aft er an initial reset, the TTBR register is set to 0x0C00000.
There fore, even when the trap table position is changed, it is necessary that at least the reset vector be written to the
above ad dress.
TTBR0 and TTBR3 are read-only bits which are fixed at "0". Therefore, the trap table starting address always
begins with a 1K B boundary address.
The TTBR register is normal ly write-protected to prevent them from being inadvertently rewritten. To remove this
wri te protection function, another register, TBRP (D[7:0]) / TTBR write-protect register (0x4812D [byte]), is
provided. A write to the TTBR register is enabled by writing "0x59" to TBRP and is disabled back again by a write
to the most significant byte of the TTBR register (0x48137). Consequently, a write to the TTBR register needs to
begin with the low-order half-word first. However, since an occurrence of NMI or the like between writes of the
low-order and h i gh -o rd er half-w ord s would caus e a mal f un ct i on , it is recommended that the register be written in
words.
II CORE BLOCK: ITC (In t errupt Controller)
S1C33L03 FUNCTION PART EPSON B-II-5-5
A-1
B-II
ITC
Control of Maskable Interrupts
Structure of the Interrupt Controller
The interrupt controller is configured as show n in Figure 5.1.
CPU interrupt
priority judgment
(with interrupt level)
Interrupt vector
generator
Interrupt factor flag
Interrupt enable
IDMA request
IDMA enable
Interrupt request
Interrupt level
Interrupt vector
Key input x
HSDMA x
K5x (#DMAREQx) input Software trigger
16-bit timer x
8-bit timer x
Serial I/F x
A/D
Port input x
CPU
ITC
IDMA request
priority judgment
(without interrupt level)
IDMA channel number
generator
Interrupt factor flag
Interrupt enable
IDMA request
IDMA enable
IDMA request
IDMA channel number
IDMA completion
Reset A
Reset B
Reset C
Ch.x HSDMA request
HSDMA trigger
selection circuit
IDMA
HSDMA
Ch.x
I
nterrupt
factors
•
•
•
Figur e 5.1 Configuration of Interrupt Controller
The following sections explain the functions of the registers used to control interrupts.
Processor Status Register (PSR)
The PSR is a special register incorporated in the core CPU and contains control bits to enable or disable an
interrupt request to the CPU.
Interrupt Enable (IE) bit: PSR[4]
This bit is used to enable or disable an interrupt request to the CPU. When this bit is set to "1", the CPU is
enabled to accept a maskable interrupt request. When this bit is reset to "0", no maskable interrupt request is
accepted by the CPU.
When the CPU accepts an interrupt request (or some other trap occurs), it saves the PSR to the stack and
resets the IE bit to "0". Consequently, no maskable interrupt request occurring thereafter will be accepted
unless the IE bit is set to "1" in software program or the interrupt (trap) processing routine is terminated by
the reti instruction.
The IE bit is initialized to "0" (interrupts disabled) by an initial reset.
Interrupt Level (IL): PS R[11:8]
The IL bits disable the interrupts whose priorities are below the set interrupt level. For example, if the
interrupt level set in the IL is 3, the interrupts whose priorities are set below 3 in the interrupt priority register
(described later) are not accepted by the CPU even if the IE bit is set to "1". The IL and the interrupt priority
register together allow you to control the interrupt priorities in each interrupt system. For details about the
interrupt levels, refer to "Interrupt Priority Register and Interrupt Levels".
When the CPU accepts a maskable interrupt request, it saves the PSR to the stack and sets the IL to the
accepted interrupt's priority level. Therefore, even when the IE bit is set to "1" in the interrupt processing
routine, no interrupts whose priority levels are equal or below that of the interrupt currently being processed
are accepted unless the IL is rewritten.
The IL is restored to its previous status when the interrupt processing routine is terminated by the reti
instruction.
II CORE BLOCK: ITC (In t errupt Controller)
B-II-5-6 EPSON S1C33L03 FUNCTION PART
The IL is rewritten for only maskable interrupts and not for any other traps (except a reset).
The IL is set to level 0 (that is, all interrupts above level 1 are enabled) by an initial reset.
Note: As t he S1C33000 Core CPU function, the IL allows interrupt levels to be set in the range of 0 to 15.
However, since the interrupt priority register in the ITC consists of three bits, interrupt levels in
each interrupt system can on ly be set for up to 8.
Interrupt Factor Flag and Interrupt Enable Register
An interrupt factor flag and an interrupt enable register are provided for each maskable interrupt factor.
Interrupt factor flag
The interrupt factor flag is set to "1" when the corresponding interrupt factor occurs. Reading the flag enables
you to de termine w hat cau sed an interrupt, making it unnecessary to resort to the CPU's trap processing. The
interrupt factor flag is reset by writing data in software or by IDMA operation. Note that the method by which
this flag is reset can be selected from the software application using either of the two methods described
below. This selection is accomplished using RSTONLY (D0) / Flag set/reset method select register
(0x4029F).
• Reset-only method (default)
This method is selected (RSTONLY = "1") when initially reset.
With this method, the interrupt factor flag is reset by writing "1". Although multiple interrupt factor flags are
located at the same address of the interrupt control register, the interrupt factor flags for which "0" has been
written can be neither set nor reset. Therefore, this method ensures that only a specific factor flag is reset.
However, wh en using read-modify- wri te instructions (e.g., bset, bclr, or bnot), note that an interrupt factor
flag that has been set to "1" is reset by writing.
In this method, no interrupt factor flag can be set in the software application.
• Read/write method
This method is selected by writing "0" to RSTONLY.
When this method is used, interrupt factor flags can be read and written as for other registers. Therefore, the
flag is reset by writing "0" and set by writing "1". In this case, all factor flags for which "0" has been written
are reset. Even in a read-modify-write operation, an interrupt factor can occur between the read and the write,
so be careful when using this method.
Since interrupt factor flags are not initialized by an initial reset, be sure to reset them before enabling
interrupts.
Note: Even when a mask able int errupt req uest is accept ed by the CPU an d control br anch es off t o the
interrupt processing routine, the interrupt factor flag is not reset. Consequently, if control is
returned from the interrupt processing routine by the reti instruction without resetting the interrupt
factor flag in a program, the same interrupt factor occurs again.
For details about interrupt factor generating conditions, refer to the description of each peripheral circuit in
this m an ua l.
II CORE BLOCK: ITC (In t errupt Controller)
S1C33L03 FUNCTION PART EPSON B-II-5-7
A-1
B-II
ITC
Interrupt enable register
This regist er controls the output of an interrupt request to the CPU. Only when the interrupt enable bit of this
register is set to "1" can an interrupt request to the CPU be enabled by an occurrence of the corresponding
interrupt factor. If the bit is set to "0", no interrupt request is made to the CPU even when the corresponding
inte rrupt fa ctor o ccu rs.
Interrupt enable bits can be read and written as for other registers. Therefore, the interrupt enable bit is reset
by w riting "0" and set by writing "1". By reading this register, its setup status can be checked at any time.
Settings of the interrupt enable register do not affect the operation of interrupt factor flags, so when an
interrupt factor occurs the interrupt factor flag is set to "1" even if the corresponding interrupt enable bit is set
to "0".
When initially reset, the interrupt enable register is set to "0" (interrupts are disabled).
In cases when IDMA is started up by occurrence of an interrupt factor or when clearing standby mode
(HALT or SLEEP mode) too, the corresponding interrupt enable bit must be set to "1".
The interrupt controller outputs an interrupt request to the CPU when the following conditions are met:
• An inte rrupt fa cto r h as o ccu rr ed and th e inte rru pt facto r flag is set to "1" .
• The bit of the interrupt enable register for the interrupt factor that has occurred is set to "1" (interrupt enable).
• The bit of the IDMA request register for the interrupt factor that has occurred is set to "0" (interrupt request).
If two or more interrupt factors occur simultaneously, the interrupt factor that has the highest priority is allowed to
signal an interrupt request to the CPU. (See the following section.)
When thes e conditions are met, the interrupt controller outputs an interrupt request signal to the CPU along with
the setup content (interrupt level) of the interrupt priority register for the generated interrupt system and its vector
number.
These signals remain asserted until the interrupt factor flag is reset to "0" or the corresponding bit of the interrupt
enable register is set to "0" (interrupts are disabled) or until some other interrupt factor of higher priority occ urs.
They a re not cleared if the CPU simply accepts the interrupt request.
II CORE BLOCK: ITC (In t errupt Controller)
B-II-5-8 EPSON S1C33L03 FUNCTION PART
Interrupt Priority Register and Interrupt Levels
The interrupt priority register is a 3-bit register provided for each interrupt system. It allows the interrupt levels of a
given interr upt system to be set in the range of 0 to 7. The default pri oriti es shown i n Table 5.1 can be modified
according to system requirements by this setting.
The value set in this register is used by the interrupt controller and the CPU as described below.
Roles o f the interrupt priori ty regist er in the interrupt controller
If two or more interrupt factors that have been enabled by the interrupt enable register occur simultaneously,
the interrupt factor in the interrupt system whose interrupt priority register contains the greatest value is
allowed by the interrupt controller to signal an interrupt request to the CPU.
If an interrupt factor occurs in two or more interrupt systems having the same value, the interrupt priority is
resolved according to the default priorities in Table 5.1. Interrupt factors in the same interrupt system also
have their priorities resolved according to the order in Table 5.1.
Other interrupt factors are kept pending until all interrupts of higher priority are accepted by the CPU.
When output ting an interrupt request signal to the CPU, the interrupt controller outputs the content of the
interrupt priority register to the CPU along with it.
If another interrupt factor of higher priority occurs during outputting an interrupt request signal, the interrupt
controller changes the vector number and interrupt level to those of the new interrupt factor before they are
output to the CPU. The first interrupt request is left pending.
Rol es of th e interrupt priority register in CPU processing
The C PU comp ares the content of the interrupt priority register received from the interrupt controller with the
interrupt level that is set in the IL of the PSR to determine whether or not to accept the interrupt request.
IE bit = "1" & IL < interrupt priority register: the interrupt request is accepted
IE bit = "1" & IL > interrupt priority register: the interrupt request is rejected
Before interrupts can be controlled by an interrupt level, the interrupt disabling level must be written to the IL.
For example, if the value written to the IL is 3, only the interrupts whose interrupt levels written in the
interrupt priority register are 4 or more will be accepted.
When an interrupt is accepted, the interrupt level that is set in its interrupt priority register is written to the IL.
As a result, the interrupt requests below that interrupt level can no longer be accepted.
If the interrupt priority register for an interrupt is set to "0", the interrupt is disabled. However, invoking
IDMA by means of an interrupt factor works fine.
Notes:•As the S1C33000 Core CPU function, t he IL allows interrupt levels to be set in the range of 0 to
15. However, since the int e r ru pt priority register in the C33 Core Block consists of three bits,
interrupt levels in each interrupt system can only be set for up to 8.
•Multiple interrupts can al so be hand led by rewri ting the interrupt level to the IL in the interrupt
processing routine. However, if the interrupt level of the IL is set below the current level and the
IE is set to enable interrupts before resetting the interrupt factor flag after an interrupt has
occurred, the sam e inter rup t may oc cur again.
II CORE BLOCK: ITC (In t errupt Controller)
S1C33L03 FUNCTION PART EPSON B-II-5-9
A-1
B-II
ITC
IDMA Invocation
The interrupt factors for which IDMA channel numbers are written in Table 5.1 have the function to invoke the
intelligent DMA (IDMA).
IDMA request register
The IDMA request register is used to specify the interrupt factor that invoke an IDMA transfer. If an IDMA
request bit is set to "1", the IDMA request will be generated when the corresponding interrupt factor occurs.
When th e IDMA request bit is set to "0", the corresponding interrupt factor does not invoke IDMA and a
normal interrupt processing will be performed. The IDMA request register is set to "0" by an initial reset.
The m ethod by w hich this register is set can be selected from the software application using either of the two
methods descri bed below . This selec tion is accomplished using IDMAONLY (D1) / Flag set/reset method
sel e ct re giste r (0x4 02 9F ).
•Set-onl y m ethod (default)
This method is selected (IDMAONLY = "1") when initially reset.
With this method, an IDMA request bit is set by writing "1". Although multiple IDMA request bits are
located in the IDMA request register, the IDMA request bits for which "0" has been written can be neither set
nor reset. Therefore, this method ensures that only a specific IDMA request bit is set.
However, wh en using read-modify- write inst ructions (e.g., bset, bclr, or bnot), note that an IDMA r eque st bit
that has been set to "1" is not reset by writing.
•Read/write method
This method is selected by writing "0" to IDMAONLY.
When this method is used, IDMA request bits can be read and written as for other registers. Therefore, the
IDMA request bit is reset by writing "0" and set by writing "1". In this case, all IDMA request bits for which
"0" has been written a re reset. Even in a read-modify-write operation, an IDMA request bit can be reset by
the hardware between the read and the write, so be careful when using this method.
IDMA enable register
To perfo rm IDMA transfer using an interrupt factor, the corresponding bit of the IDMA enable register must
be set to "1". If this bit is set to "0", the interrupt factor cannot invoke the IDMA channel. The IDMA enable
register is set to "0" by an initial reset.
The IDMA ena ble register allows sel ection of a set method (set-only m ethod or Read/wr ite method) similar to
the IDMA reque st regist er . Thi s s el ection is accompl is hed using DENONLY (D2) / Fla g s et/reset method
select register (0x4029F). See the above explanation for the set method.
Invoking IDMA
Before IDMA can be invoked by the occurrence of an interrupt factor, the corresponding bits of the IDMA
request and IDMA enable registers must be set to "1". Then when an interrupt factor occurs, the interrupt
request to the CPU is made pending and the corresponding IDMA channel is invoked. The DMA transfer is
performed according to the control information of that IDMA channel. The interrupt level set by the interrupt
priority r egister of the ITC do es not affect the IDMA invocation. The IDMA request can be accepted even if
the interrupt level of the CPU is higher than the set value of the interrupt priority register. However, when
generating the interrupt request to the CPU after the IDMA transfer is completed, the interrupt is controlled
using the interrupt level set by the interrupt priority register.
An IDMA invocation request is accepted even when the interrupt enable register and PSR of the CPU is set to
disable interrupts. It is also necessary that the control information for the IDMA channel has been set.
II CORE BLOCK: ITC (In t errupt Controller)
B-II-5-10 EPSON S1C33L03 FUNCTION PART
Interrupt after IDMA transfer
To gene rate an int errupt after completion of IDMA transfer:
The interrupt request that has been kept pending can be generated after completion of the DMA transfer.
In this case, the interrupt must be enabled by the IDMA control information (DINTEM = "1") in adition to
the interrupt controller and the PSR register settings.
However, if t he transfer counter set for the selected IDMA channel does not reach the terminal count of 0
after the number of transfers set have been performed, the interrupt factor flag is reset and no interrupt request
is generated. The transfer counter is decremented by 1 for each transfer performed.
If the transfer counter is decremented to 0 when DINTEN is set to "1", the interrupt factor flag is not reset
and the IDMA request bit is cleared to "0". An interrupt request is generated if other interrupt conditions are
met.
The IDMA request bit must be set up again in order for IDMA to be invoked when an interrupt factor occurs
next time as well. To ensure that no unwanted IDMA request occurs, this setup must be performed after
resettin g th e inte rru pt fa cto r flag .
Figure 5.2 shows the hardware sequence when DI NTEN is set to "1".
3 2 1 0
IDMA trigger (interrupt factor flag)
Transfer counter
Data transfer
Reset A signal
(reset interrupt factor flag)
Reset B signal
(reset IDMA request bit)
IDMA request bit
Interrupt request
Figur e 5.2 Sequence when DINTEN = "1"
To disable an interrupt after completion of IDMA transfer:
If an interrupt has been disabled in the IDMA control information (DINTEN = "0"), the interrupt is not
generated since the interrupt factor flag is reset when the transfer counter becomes 0.
In this case, the IDMA request bit remains set to "1" without being cleared. However, the IDMA enable bit is
cleared, so the following IDMA request by the same interrupt factor will be disabled.
Figure 5.3 shows the hardware sequence when DI NTEN is set to "0".
3 2 1 0
IDMA trigger (interrupt factor flag)
Transfer counter
Data transfer
Reset A signal
(reset interrupt factor flag)
Reset B signal
(reset IDMA request bit)
Reset C signal
(reset IDMA enable bit)
IDMA request bit
IDMA enable bit
L
"1"
Figur e 5.3 Sequence when DINTEN = "0"
For details on IDMA, refer to "IDMA (Intelligent DMA)".
II CORE BLOCK: ITC (In t errupt Controller)
S1C33L03 FUNCTION PART EPSON B-II-5-11
A-1
B-II
ITC
HSDMA Invocation
Some interrupt fa ctors can in voke high -speed D M As (HS DMA ).
HSDMA t r igger set-up register
The DM A blo ck contains four channel of HSDMA circuit. Each channel allows selection of an interrupt
factor as the trigger. The HSDMA trigger set-up registers are used for this selection.
HSDMA Ch.0: HSD0S [3:0] ( D[3:0])/HSDMA Ch.0/1 trigger set-up register (0x40298)
HSDMA Ch.1: HSD1S [3:0] ( D[7:4])/HSDMA Ch.0/ 1 trigger s et -up regist er (0x40 298)
HSDMA Ch.2: HSD2S [3:0] ( D[3:0])/HSDMA Ch.2/ 3 trigger s et -up regist er (0x40 299)
HSDMA Ch.3: HSD3S [3:0] ( D[7:4])/HSDMA Ch.2/ 3 trigger s et -up regi ster (0x40 299)
Table 5.2 shows t he setting value and the corresponding trigger factor.
Table 5.2 HSDMA Trigger Factor
Value Ch.0 trigger factor Ch.1 trigger factor Ch.2 trigger factor Ch.3 trigger factor
0000 Software trigger Software trigger Software trigger Software trigger
0001 K50 port input (falling edge) K51 port input (falling edge) K53 port input (falling edge) K54 port input (falling edge)
0010 K50 port input (rising edge) K51 port input (rising edge) K53 port input (rising edge) K54 port input (rising edge)
0011 Port 0 input Port 1 input Port 2 input Port 3 input
0100 Port 4 input Port 5 input Port 6 input Port 7 input
0101 8-bit timer 0 underflow 8-bit timer 1 underflow 8-bit timer 2 underflow 8-bit timer 3 underflow
0110 16-bit timer 0 compare B 16-bit timer 1 compare B 16-bit timer 2 compare B 16-bit timer 3 compare B
0111 16-bit timer 0 compare A 16-bit timer 1 compare A 16-bit timer 2 compare A 16-bit timer 3 compare A
1000 16-bit timer 4 compare B 16-bit timer 5 compare B 16-bit timer 4 compare B 16-bit timer 5 compare B
1001 16-bit timer 4 compare A 16-bit timer 5 compare A 16-bit timer 4 compare A 16-bit timer 5 compare A
1010 Serial I/F Ch.0 Rx buffer full Serial I/F Ch.1 Rx buffer full Serial I/F Ch.0 Rx buffer full Serial I/F Ch.1 Rx buffer full
1011 Serial I/F Ch.0 Tx buffer empty Serial I/F Ch.1 Tx buffer empty Serial I/F Ch.0 Tx buffer empty Serial I/F Ch.1 Tx buffer empty
1100 A/D conversion completion A/D conversion completion A/D conversion completion A/D conversion completion
Invoking HSDMA
By selec ting an interrupt factor with the HSDMA trigger set-up register, the HSDMA channel is invoked
when the selecte d interru pt facto r o ccurs . T he inte rru pt contro l bits (i nterru p t facto r fl ag , inte rru pt en ab le
register, ID M A requ est registe r, inte rrupt p rio rity registe r) d o not af fe ct this in vo catio n.
Since HSDMA does not reset the interrupt factor flag, an interrupt will occur when the DMA transfer is
completed if the interrupt is enabled by ITC.
Before HSDMA c an be invoked by the occurrence of an interrupt factor, it is necessary that DMA be enabled
on the H SDMA sid e by setting t he control register for HSDMA transfer .
For details about HSDMA, refer to "HSDMA (High-Speed DMA)".
II CORE BLOCK: ITC (In t errupt Controller)
B-II-5-12 EPSON S1C33L03 FUNCTION PART
I/O Memo ry of Interrupt Con trolle r
Table 5.3 shows the control bits of the interrupt controller.
Table 5.3 Control Bits of Interrupt Controller
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
0 to 7
0 to 7
–
–
PP1L2
PP1L1
PP1L0
–
PP0L2
PP0L1
PP0L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Port input 1 interrupt level
reserved
Port input 0 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040260
(B)
Port input 0/1
interrupt
priority register
–
0 to 7
0 to 7
–
–
PP3L2
PP3L1
PP3L0
–
PP2L2
PP2L1
PP2L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Port input 3 interrupt level
reserved
Port input 2 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040261
(B)
Port input 2/3
interrupt
priority register
–
0 to 7
0 to 7
–
–
PK1L2
PK1L1
PK1L0
–
PK0L2
PK0L1
PK0L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Key input 1 interrupt level
reserved
Key input 0 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040262
(B)
Key input
interrupt
priority register
–
0 to 7
0 to 7
–
–
PHSD1L2
PHSD1L1
PHSD1L0
–
PHSD0L2
PHSD0L1
PHSD0L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
High-speed DMA Ch.1
interrupt level
reserved
High-speed DMA Ch.0
interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040263
(B)
High-speed
DMA Ch.0/1
interrupt
priority register
–
0 to 7
0 to 7
–
–
PHSD3L2
PHSD3L1
PHSD3L0
–
PHSD2L2
PHSD2L1
PHSD2L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
High-speed DMA Ch.3
interrupt level
reserved
High-speed DMA Ch.2
interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040264
(B)
High-speed
DMA Ch.2/3
interrupt
priority register
–
0 to 7
–
PDM2
PDM1
PDM0
D7–3
D2
D1
D0
reserved
IDMA interrupt level –
X
X
X
–
R/W 0 when being read.0040265
(B)
IDMA interrupt
priority register
–
0 to 7
0 to 7
–
–
P16T12
P16T11
P16T10
–
P16T02
P16T01
P16T00
D7
D6
D5
D4
D3
D2
D1
D0
reserved
16-bit timer 1 interrupt level
reserved
16-bit timer 0 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040266
(B)
16-bit timer 0/1
interrupt
priority register
–
0 to 7
0 to 7
–
–
P16T32
P16T31
P16T30
–
P16T22
P16T21
P16T20
D7
D6
D5
D4
D3
D2
D1
D0
reserved
16-bit timer 3 interrupt level
reserved
16-bit timer 2 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040267
(B)
16-bit timer 2/3
interrupt
priority register
II CORE BLOCK: ITC (In t errupt Controller)
S1C33L03 FUNCTION PART EPSON B-II-5-13
A-1
B-II
ITC
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
0 to 7
0 to 7
–
–
P16T52
P16T51
P16T50
–
P16T42
P16T41
P16T40
D7
D6
D5
D4
D3
D2
D1
D0
reserved
16-bit timer 5 interrupt level
reserved
16-bit timer 4 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040268
(B)
16-bit timer 4/5
interrupt
priority register
–
0 to 7
0 to 7
–
–
PSI002
PSI001
PSI000
–
P8TM2
P8TM1
P8TM0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Serial interface Ch.0
interrupt level
reserved
8-bit timer 0–3 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040269
(B)
8-bit timer,
serial I/F Ch.0
interrupt
priority register
–
0 to 7
0 to 7
–
–
PAD2
PAD1
PAD0
–
PSI012
PSI011
PSI010
D7
D6
D5
D4
D3
D2
D1
D0
reserved
A/D converter interrupt level
reserved
Serial interface Ch.1
interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
004026A
(B)
Serial I/F Ch.1,
A/D interrupt
priority register
–
0 to 7
–
PCTM2
PCTM1
PCTM0
D7–3
D2
D1
D0
reserved
Clock timer interrupt level –
X
X
X
–
R/W Writing 1 not allowed.004026B
(B)
Clock timer
interrupt
priority register
–
0 to 7
0 to 7
–
–
PP5L2
PP5L1
PP5L0
–
PP4L2
PP4L1
PP4L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Port input 5 interrupt level
reserved
Port input 4 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
004026C
(B)
Port input 4/5
interrupt
priority register
–
0 to 7
0 to 7
–
–
PP7L2
PP7L1
PP7L0
–
PP6L2
PP6L1
PP6L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Port input 7 interrupt level
reserved
Port input 6 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
004026D
(B)
Port input 6/7
interrupt
priority register
–
EK1
EK0
EP3
EP2
EP1
EP0
D7–6
D5
D4
D3
D2
D1
D0
reserved
Key input 1
Key input 0
Port input 3
Port input 2
Port input 1
Port input 0
– –
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.0040270
(B) 1 Enabled 0 Disabled
Key input,
port input 0–3
interrupt
enable register
–
EIDMA
EHDM3
EHDM2
EHDM1
EHDM0
D7–5
D4
D3
D2
D1
D0
reserved
IDMA
High-speed DMA Ch.3
High-speed DMA Ch.2
High-speed DMA Ch.1
High-speed DMA Ch.0
– –
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
0 when being read.0040271
(B) 1 Enabled 0 Disabled
DMA interrupt
enable register
E16TC1
E16TU1
–
E16TC0
E16TU0
–
D7
D6
D5–4
D3
D2
D1–0
16-bit timer 1 comparison A
16-bit timer 1 comparison B
reserved
16-bit timer 0 comparison A
16-bit timer 0 comparison B
reserved
0
0
–
0
0
–
R/W
R/W
–
R/W
R/W
–
0 when being read.
0 when being read.
0040272
(B) 1 Enabled 0 Disabled
16-bit timer 0/1
interrupt
enable register –
1 Enabled 0 Disabled
–
E16TC3
E16TU3
–
E16TC2
E16TU2
–
D7
D6
D5–4
D3
D2
D1–0
16-bit timer 3 comparison A
16-bit timer 3 comparison B
reserved
16-bit timer 2 comparison A
16-bit timer 2 comparison B
reserved
0
0
–
0
0
–
R/W
R/W
–
R/W
R/W
–
0 when being read.
0 when being read.
0040273
(B) 1 Enabled 0 Disabled
16-bit timer 2/3
interrupt
enable register –
1 Enabled 0 Disabled
–
II CORE BLOCK: ITC (In t errupt Controller)
B-II-5-14 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
E16TC5
E16TU5
–
E16TC4
E16TU4
–
D7
D6
D5–4
D3
D2
D1–0
16-bit timer 5 comparison A
16-bit timer 5 comparison B
reserved
16-bit timer 4 comparison A
16-bit timer 4 comparison B
reserved
0
0
–
0
0
–
R/W
R/W
–
R/W
R/W
–
0 when being read.
0 when being read.
0040274
(B) 1 Enabled 0 Disabled
16-bit timer 4/5
interrupt
enable register –
1 Enabled 0 Disabled
–
–
E8TU3
E8TU2
E8TU1
E8TU0
D7–4
D3
D2
D1
D0
reserved
8-bit timer 3 underflow
8-bit timer 2 underflow
8-bit timer 1 underflow
8-bit timer 0 underflow
– –
0
0
0
0
–
R/W
R/W
R/W
R/W
0 when being read.0040275
(B) 1 Enabled 0 Disabled
8-bit timer
interrupt
enable register
–
ESTX1
ESRX1
ESERR1
ESTX0
ESRX0
ESERR0
D7–6
D5
D4
D3
D2
D1
D0
reserved
SIF Ch.1 transmit buffer empty
SIF Ch.1 receive buffer full
SIF Ch.1 receive error
SIF Ch.0 transmit buffer empty
SIF Ch.0 receive buffer full
SIF Ch.0 receive error
– –
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.0040276
(B) 1 Enabled 0 Disabled
Serial I/F
interrupt
enable register
–
EP7
EP6
EP5
EP4
ECTM
EADE
D7–6
D5
D4
D3
D2
D1
D0
reserved
Port input 7
Port input 6
Port input 5
Port input 4
Clock timer
A/D converter
– –
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.0040277
(B) 1 Enabled 0 Disabled
Port input 4–7,
clock timer,
A/D interrupt
enable register
–
FK1
FK0
FP3
FP2
FP1
FP0
D7–6
D5
D4
D3
D2
D1
D0
reserved
Key input 1
Key input 0
Port input 3
Port input 2
Port input 1
Port input 0
– –
X
X
X
X
X
X
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.0040280
(B) 1 Factor is
generated 0 No factor is
generated
Key input,
port input 0–3
interrupt factor
flag register
–
FIDMA
FHDM3
FHDM2
FHDM1
FHDM0
D7–5
D4
D3
D2
D1
D0
reserved
IDMA
High-speed DMA Ch.3
High-speed DMA Ch.2
High-speed DMA Ch.1
High-speed DMA Ch.0
– –
X
X
X
X
X
–
R/W
R/W
R/W
R/W
R/W
0 when being read.0040281
(B)
DMA interrupt
factor flag
register 1 Factor is
generated 0 No factor is
generated
F16TC1
F16TU1
–
F16TC0
F16TU0
–
D7
D6
D5–4
D3
D2
D1–0
16-bit timer 1 comparison A
16-bit timer 1 comparison B
reserved
16-bit timer 0 comparison A
16-bit timer 0 comparison B
reserved
X
X
–
X
X
–
R/W
R/W
–
R/W
R/W
–
0 when being read.
0 when being read.
0040282
(B) 1 Factor is
generated 0 No factor is
generated
16-bit timer 0/1
interrupt factor
flag register –
1 Factor is
generated 0 No factor is
generated
–
F16TC3
F16TU3
–
F16TC2
F16TU2
–
D7
D6
D5–4
D3
D2
D1–0
16-bit timer 3 comparison A
16-bit timer 3 comparison B
reserved
16-bit timer 2 comparison A
16-bit timer 2 comparison B
reserved
X
X
–
X
X
–
R/W
R/W
–
R/W
R/W
–
0 when being read.
0 when being read.
0040283
(B) 1 Factor is
generated 0 No factor is
generated
16-bit timer 2/3
interrupt factor
flag register –
1 Factor is
generated 0 No factor is
generated
–
F16TC5
F16TU5
–
F16TC4
F16TU4
–
D7
D6
D5–4
D3
D2
D1–0
16-bit timer 5 comparison A
16-bit timer 5 comparison B
reserved
16-bit timer 4 comparison A
16-bit timer 4 comparison B
reserved
X
X
–
X
X
–
R/W
R/W
–
R/W
R/W
–
0 when being read.
0 when being read.
0040284
(B) 1 Factor is
generated 0 No factor is
generated
16-bit timer 4/5
interrupt factor
flag register –
1 Factor is
generated 0 No factor is
generated
–
–
F8TU3
F8TU2
F8TU1
F8TU0
D7–4
D3
D2
D1
D0
reserved
8-bit timer 3 underflow
8-bit timer 2 underflow
8-bit timer 1 underflow
8-bit timer 0 underflow
– –
X
X
X
X
–
R/W
R/W
R/W
R/W
0 when being read.0040285
(B) 1 Factor is
generated 0 No factor is
generated
8-bit timer
interrupt factor
flag register
–
FSTX1
FSRX1
FSERR1
FSTX0
FSRX0
FSERR0
D7–6
D5
D4
D3
D2
D1
D0
reserved
SIF Ch.1 transmit buffer empty
SIF Ch.1 receive buffer full
SIF Ch.1 receive error
SIF Ch.0 transmit buffer empty
SIF Ch.0 receive buffer full
SIF Ch.0 receive error
– –
X
X
X
X
X
X
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.0040286
(B) 1 Factor is
generated 0 No factor is
generated
Serial I/F
interrupt factor
flag register
II CORE BLOCK: ITC (In t errupt Controller)
S1C33L03 FUNCTION PART EPSON B-II-5-15
A-1
B-II
ITC
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
FP7
FP6
FP5
FP4
FCTM
FADE
D7–6
D5
D4
D3
D2
D1
D0
reserved
Port input 7
Port input 6
Port input 5
Port input 4
Clock timer
A/D converter
– –
X
X
X
X
X
X
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.0040287
(B) 1 Factor is
generated 0 No factor is
generated
Port input 4–7,
clock timer, A/D
interrupt factor
flag register
R16TC0
R16TU0
RHDM1
RHDM0
RP3
RP2
RP1
RP0
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 0 comparison A
16-bit timer 0 comparison B
High-speed DMA Ch.1
High-speed DMA Ch.0
Port input 3
Port input 2
Port input 1
Port input 0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0040290
(B) 1 IDMA
request 0 Interrupt
request
Port input 0–3,
high-speed
DMA Ch. 0/1,
16-bit timer 0
IDMA request
register
R16TC4
R16TU4
R16TC3
R16TU3
R16TC2
R16TU2
R16TC1
R16TU1
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 4 comparison A
16-bit timer 4 comparison B
16-bit timer 3 comparison A
16-bit timer 3 comparison B
16-bit timer 2 comparison A
16-bit timer 2 comparison B
16-bit timer 1 comparison A
16-bit timer 1 comparison B
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0040291
(B) 1 IDMA
request 0 Interrupt
request
16-bit timer 1–4
IDMA request
register
RSTX0
RSRX0
R8TU3
R8TU2
R8TU1
R8TU0
R16TC5
R16TU5
D7
D6
D5
D4
D3
D2
D1
D0
SIF Ch.0 transmit buffer empty
SIF Ch.0 receive buffer full
8-bit timer 3 underflow
8-bit timer 2 underflow
8-bit timer 1 underflow
8-bit timer 0 underflow
16-bit timer 5 comparison A
16-bit timer 5 comparison B
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0040292
(B) 1 IDMA
request 0 Interrupt
request
16-bit timer 5,
8-bit timer,
serial I/F Ch.0
IDMA request
register
RP7
RP6
RP5
RP4
–
RADE
RSTX1
RSRX1
D7
D6
D5
D4
D3
D2
D1
D0
Port input 7
Port input 6
Port input 5
Port input 4
reserved
A/D converter
SIF Ch.1 transmit buffer empty
SIF Ch.1 receive buffer full
0
0
0
0
–
0
0
0
R/W
R/W
R/W
R/W
–
R/W
R/W
R/W
0 when being read.
0040293
(B) 1 IDMA
request 0 Interrupt
request
1 IDMA
request 0 Interrupt
request
–
Serial I/F Ch.1,
A/D,
port input 4–7
IDMA request
register
DE16TC0
DE16TU0
DEHDM1
DEHDM0
DEP3
DEP2
DEP1
DEP0
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 0 comparison A
16-bit timer 0 comparison B
High-speed DMA Ch.1
High-speed DMA Ch.0
Port input 3
Port input 2
Port input 1
Port input 0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0040294
(B) 1 IDMA
enabled 0 IDMA
disabled
Port input 0–3,
high-speed
DMA Ch. 0/1,
16-bit timer 0
IDMA enable
register
DE16TC4
DE16TU4
DE16TC3
DE16TU3
DE16TC2
DE16TU2
DE16TC1
DE16TU1
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 4 comparison A
16-bit timer 4 comparison B
16-bit timer 3 comparison A
16-bit timer 3 comparison B
16-bit timer 2 comparison A
16-bit timer 2 comparison B
16-bit timer 1 comparison A
16-bit timer 1 comparison B
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0040295
(B) 1 IDMA
enabled 0 IDMA
disabled
16-bit timer 1–4
IDMA enable
register
DESTX0
DESRX0
DE8TU3
DE8TU2
DE8TU1
DE8TU0
DE16TC5
DE16TU5
D7
D6
D5
D4
D3
D2
D1
D0
SIF Ch.0 transmit buffer empty
SIF Ch.0 receive buffer full
8-bit timer 3 underflow
8-bit timer 2 underflow
8-bit timer 1 underflow
8-bit timer 0 underflow
16-bit timer 5 comparison A
16-bit timer 5 comparison B
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0040296
(B) 1 IDMA
enabled 0 IDMA
disabled
16-bit timer 5,
8-bit timer,
serial I/F Ch.0
IDMA enable
register
DEP7
DEP6
DEP5
DEP4
–
DEADE
DESTX1
DESRX1
D7
D6
D5
D4
D3
D2
D1
D0
Port input 7
Port input 6
Port input 5
Port input 4
reserved
A/D converter
SIF Ch.1 transmit buffer empty
SIF Ch.1 receive buffer full
0
0
0
0
–
0
0
0
R/W
R/W
R/W
R/W
–
R/W
R/W
R/W
0 when being read.
0040297
(B) 1 IDMA
enabled 0 IDMA
disabled
1 IDMA
enabled 0 IDMA
disabled
–
Serial I/F Ch.1,
A/D,
port input 4–7
IDMA enable
register
II CORE BLOCK: ITC (In t errupt Controller)
B-II-5-16 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
HSD1S3
HSD1S2
HSD1S1
HSD1S0
HSD0S3
HSD0S2
HSD0S1
HSD0S0
D7
D6
D5
D4
D3
D2
D1
D0
High-speed DMA Ch.1
trigger set-up
High-speed DMA Ch.0
trigger set-up
0
0
0
0
0
0
0
0
R/W
R/W
0040298
(B) 0
1
2
3
4
5
6
7
8
9
A
B
C
Software trigger
K51 input (falling edge)
K51 input (rising edge)
Port 1 input
Port 5 input
8-bit timer Ch.1 underflow
16-bit timer Ch.1 compare B
16-bit timer Ch.1 compare A
16-bit timer Ch.5 compare B
16-bit timer Ch.5 compare A
SI/F Ch.1 Rx buffer full
SI/F Ch.1 Tx buffer empty
A/D conversion completion
0
1
2
3
4
5
6
7
8
9
A
B
C
Software trigger
K50 input (falling edge)
K50 input (rising edge)
Port 0 input
Port 4 input
8-bit timer Ch.0 underflow
16-bit timer Ch.0 compare B
16-bit timer Ch.0 compare A
16-bit timer Ch.4 compare B
16-bit timer Ch.4 compare A
SI/F Ch.0 Rx buffer full
SI/F Ch.0 Tx buffer empty
A/D conversion completion
High-speed
DMA Ch.0/1
trigger set-up
register
HSD3S3
HSD3S2
HSD3S1
HSD3S0
HSD2S3
HSD2S2
HSD2S1
HSD2S0
D7
D6
D5
D4
D3
D2
D1
D0
High-speed DMA Ch.3
trigger set-up
High-speed DMA Ch.2
trigger set-up
0
0
0
0
0
0
0
0
R/W
R/W
0040299
(B) 0
1
2
3
4
5
6
7
8
9
A
B
C
Software trigger
K54 input (falling edge)
K54 input (rising edge)
Port 3 input
Port 7 input
8-bit timer Ch.3 underflow
16-bit timer Ch.3 compare B
16-bit timer Ch.3 compare A
16-bit timer Ch.5 compare B
16-bit timer Ch.5 compare A
SI/F Ch.1 Rx buffer full
SI/F Ch.1 Tx buffer empty
A/D conversion completion
0
1
2
3
4
5
6
7
8
9
A
B
C
Software trigger
K53 input (falling edge)
K53 input (rising edge)
Port 2 input
Port 6 input
8-bit timer Ch.2 underflow
16-bit timer Ch.2 compare B
16-bit timer Ch.2 compare A
16-bit timer Ch.4 compare B
16-bit timer Ch.4 compare A
SI/F Ch.0 Rx buffer full
SI/F Ch.0 Tx buffer empty
A/D conversion completion
High-speed
DMA Ch.2/3
trigger set-up
register
–
DENONLY
IDMAONLY
RSTONLY
D7–3
D2
D1
D0
reserved
IDMA enable register set method
selection
IDMA request register set method
selection
Interrupt factor flag reset method
selection
– –
1
1
1
–
R/W
R/W
R/W
004029F
(B)
Flag set/reset
method select
register 1 Set only 0 RD/WR
1 Set only 0 RD/WR
1 Reset only 0 RD/WR
II CORE BLOCK: ITC (In t errupt Controller)
S1C33L03 FUNCTION PART EPSON B-II-5-17
A-1
B-II
ITC
NameAddressRegister name Bit Function Setting Init. R/W Remarks
T8CH5S0
SIO3TS0
T8CH4S0
SIO3RS0
SIO2TS0
SIO3ES0
SIO2RS0
SIO2ES0
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 5 underflow
SIO Ch.3 transmit buffer empty
8-bit timer 4 underflow
SIO Ch.3 receive buffer full
SIO Ch.2 transmit buffer empty
SIO Ch.3 receive error
SIO Ch.2 receive buffer full
SIO Ch.2 receive error
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00402C5Interrupt factor
FP function
switching
register
1SIO Ch.3
TXD Emp. 0FP6
1SIO Ch.3
RXD Full 0FP4
1SIO Ch.2
TXD Emp. 0FP3
1SIO Ch.3
RXD Err. 0FP2
1SIO Ch.2
RXD Full 0FP1
1SIO Ch.2
RXD Err. 0FP0
1T8 Ch.5 UF 0FP7
1T8 Ch.4 UF 0FP5
T8CH5S1
T8CH4S1
SIO3ES1
SIO2ES1
SIO3TS1
SIO3RS1
SIO2TS1
SIO2RS1
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 5 underflow
8-bit timer 4 underflow
SIO Ch.3 receive error
SIO Ch.2 receive error
SIO Ch.3 transmit buffer empty
SIO Ch.3 receive buffer full
SIO Ch.2 transmit buffer empty
SIO Ch.2 receive buffer full
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00402CBInterrupt factor
TM16 function
switching
register 1SIO Ch.3
RXD Err. 0TM16 Ch.3
comp.A
1SIO Ch.2
RXD Err. 0TM16 Ch.3
comp.B
1SIO Ch.3
TXD Emp. 0TM16 Ch.4
comp.A
1SIO Ch.3
RXD Full 0TM16 Ch.4
comp.B
1SIO Ch.2
TXD Emp. 0TM16 Ch.5
comp.A
1SIO Ch.2
RXD Full 0TM16 Ch.5
comp.B
1T8 Ch.5 UF 0TM16 Ch.2
comp.A
1T8 Ch.4 UF 0TM16 Ch.2
comp.B
TBRP7
TBRP6
TBRP5
TBRP4
TBRP3
TBRP2
TBRP1
TBRP0
D7
D6
D5
D4
D3
D2
D1
D0
TTBR register write protect 0
0
0
0
0
0
0
0
WUndefined in read.004812D
(B) Writing 01011001 (0x59)
removes the TTBR (0x48134)
write protection.
Writing other data sets the
write protection.
TTBR write
protect register
TTBR15
TTBR14
TTBR13
TTBR12
TTBR11
TTBR10
TTBR09
TTBR08
TTBR07
TTBR06
TTBR05
TTBR04
TTBR03
TTBR02
TTBR01
TTBR00
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Trap table base address [15:10]
Trap table base address [9:0] Fixed at 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R0 when being read.
Writing 1 not allowed.
0048134
(HW)
TTBR low-
order register
TTBR33
TTBR32
TTBR31
TTBR30
TTBR2B
TTBR2A
TTBR29
TTBR28
TTBR27
TTBR26
TTBR25
TTBR24
TTBR23
TTBR22
TTBR21
TTBR20
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Trap table base address [31:28]
Trap table base address [27:16]
Fixed at 0
0x0C0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
R
R/W
0 when being read.
Writing 1 not allowed.
0048136
(HW)
TTBR high-
order register
II CORE BLOCK: ITC (In t errupt Controller)
B-II-5-18 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
A10IR2
A10IR1
A10IR0
–
A10BW1
A10BW0
A10DRA
A9DRA
A10SZ
A10DF1
A10DF0
–
A10WT2
A10WT1
A10WT0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Area 10 internal ROM size
selection
reserved
Areas 10–9
burst ROM
burst read cycle wait control
Area 10 burst ROM selection
Area 9 burst ROM selection
Areas 10–9 device size selection
Areas 10–9
output disable delay time
reserved
Areas 10–9 wait control
–
–
–
1 Used 0 Not used
1 Used 0 Not used
1 8 bits 0 16 bits
–
1
1
1
–
0
0
0
0
0
1
1
–
1
1
1
–
R/W
–
R/W
R/W
R/W
R/W
R/W
–
R/W
0 when being read.
0 when being read.
0 when being read.
0048126
(HW)
1
1
0
0
1
0
1
0
A10BW[1:0] Wait cycles
3
2
1
0
1
1
0
0
1
0
1
0
A10DF[1:0] Number of cycles
3.5
2.5
1.5
0.5
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A10IR[2:0] ROM size
2MB
1MB
512KB
256KB
128KB
64KB
32KB
16KB
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A10WT[2:0] Wait cycles
7
6
5
4
3
2
1
0
Areas 10–9
set-up register
The following collectively explains the basic functions of each control register/bit. For details about individual
interrupt systems and the contents classified by an interrupt factor, refer to the descriptions of the peripheral
circuits in this manual.
Pxxx2–Pxxx0: Interrupt priority register
Set the priority levels of each interrupt system in the range of 0 to 7.
If this register is set below the IL value of the PSR, no interrupt is generated. The value of this register when
initially reset is indeterminate.
Exxx: Interrupt enable register
Enable or disable interrupt g ene ra tio n to the CPU.
Write "1": Inte rrupt enabled
Write "0": Inte rrupt disabled
Read: Valid
Interrupts are enabled when the corresponding bits of this register are set to "1" and are disabled when the bits are
set to "0".
For the interrupt factors used to request IDMA invocation or clear the standby mode, the corresponding interrupt
enable register bit must be set for interrupt enable.
When initially reset, this register is set to "0" (interrupt disabled).
II CORE BLOCK: ITC (In t errupt Controller)
S1C33L03 FUNCTION PART EPSON B-II-5-19
A-1
B-II
ITC
Fxxx: Interrupt factor flag
Indicate the status of interrupt factors generated.
When read
Read "1": Interrupt factor generated
Read "0": No inte rrupt fa cto r g ene ra ted
When written using the rese t-onl y m etho d (d ef au lt)
Write "1": Factor flag is reset
Write "0": Invalid
When written using the read /w rite m et ho d
Write "1": Factor flag is set
Write "0": Factor flag is reset
The interrupt factor flag is set to "1" when an interrupt factor occurs in each peripheral circuit.
If the following conditions are met at this time, an interrupt is generated to the CPU:
1. The corresponding bit of the interr upt enable regi ster is set to "1".
2. No other interrupt request of hi ghe r priority has occurred.
3. The IE bit of the PSR is set to "1" (interrupt enabled).
4. The corresponding interrupt priori ty register is set to a level higher than the CPU's interrupt level (IL).
When using an interrupt factor to request IDMA, note that even when the above conditions are met, no interrupt
request to the CPU is generated for the interrupt factor that has occurred. If interrupts are enabled at the setting of
IDMA, an interrupt is generated under the above conditions after the data transfer by IDMA is completed.
The interrupt factor flag is always set to "1" when an interrupt factor occurs no matter how the interrupt enable and
inte rrupt p rio rity regi ste rs are set.
In order for the next interrupt to be accepted after interrupt generation, the interrupt factor flag must be reset and
the PSR must be set up again (by setting the IL below the level indicated by the interrupt priority register and
setting the IE bit to "1" or executing the reti instruction).
The interrupt factor flag can only be reset by a write instruction in the software application. If the PSR is again set
up to accept interrupts (or the reti instruction is executed) without resetting the interrupt factor flag, the same
interrupt may occur again. Note also that the value to be written to reset the flag is "1" when using the reset-only
meth od (RST ONLY = "1") and "0" when using t he read/ write me thod (RSTONLY = " 0"). Be car ef ul not to
confuse these two conditions.
The interrupt factor flag becomes indeterminate when initially reset, so be sure to reset the flag in the software
application.
Rxxx: IDMA request re gi st er
Specify whether or not to invoke IDMA when an interrupt factor occurs.
When using the se t-o n ly m et ho d (d ef ault)
Write "1": IDMA request
Write "0": Not changed
Read: Valid
When using the read /w rite m et ho d
Write "1": IDMA request
Write "0": Inte rrupt request
Read: Valid
If a bit of this register is set to "1", IDMA is invoked when the corresponding interrupt factor occurs and the
progr ammed data transfer is performed. If the register bit is set to "0", regular interrupt processing is performed,
without ever invoking IDMA.
For details about IDMA, refer to "IDMA (Intelligent DMA)".
If interrupts are enabled on the IDMA side and the transfer counter reaches the terminal count of 0 after completion
of D M A transfer, the IDMA request register is reset to "0" and an interrupt request for the interrupt factor that
enabled IDMA invoking is generated.
Aft er an initial reset, this register is set to "0" (Interrupt is requested).
II CORE BLOCK: ITC (In t errupt Controller)
B-II-5-20 EPSON S1C33L03 FUNCTION PART
DExxx: IDMA enable register
Enabl e or disable the IDMA request.
When using the se t-o n ly m et ho d (d ef ault)
Write "1": IDMA enabled
Write "0": Not changed
Read: Valid
When using the read /w rite m et ho d
Write "1": IDMA enabled
Write "0": IDMA disabled
Read: Valid
If a bit of this register is set to "1", the IDMA request by the interrupt factor is enabled. If the register bit is set to
"0", the IDMA request is disabled.
Aft er an initial reset, this register is set to "0" (IDMA is disabled).
RSTONLY:Interrupt f actor flag reset m et ho d sele ct io n
(D0) / Flag set/reset method select register (0x4029F)
Select the method for resetting the interrupt factor flag.
Write "1": Res et-only method
Write "0": Rea d/write method
Read: Valid
With the r eset-only method, the interrupt factor flag is reset by writing "1".
The interrupt factor flags for which "0" has been written can neither be set nor reset. Therefore, this method
ensures that only a specific factor flag is reset. However, when using read-modify-write instructions (e.g., bset, bclr,
or bnot), note that an i nterrupt factor fla g that has been set to "1" is reset by writing. This method cannot be used to
set any interrupt factor flag in the software application.
The read/write method is selected by writing "0" to RSTONLY. When this method is selected, interrupt factor
flags can be read and written as for other registers. Therefore, the flag is reset by writing "0" and set by writing "1".
In this case all factor flags for which "0" has been written are reset. Even in a read-modify-write operation, an
interrupt factor can occur between read and write instructions, so be careful when using this method.
Aft er an initial reset, RSTONLY is set to "1" (reset-only method).
IDMAONLY:IDMA request register set method selection
(D1) / Flag set/reset method select register (0x4029F)
Select the method for setting the IDMA request registers.
Write "1": Set- only method
Write "0": Rea d/write method
Read: Valid
With the s et-only method, IDMA request bits are set by writing "1".
The IDMA request bits for which "0" has been written can neither be set nor reset. Therefore, this method ensures
that only a specific IDMA request bit is set. However, when using read-modify-write instructions (e.g., bset, bclr,
or bnot), note that an I D M A request bit that has been set to "1" is not reset by writing.
The read/write method is selected by writing "0" to IDMAONLY. When this method is selected, IDMA request
bits can be read and written as for other registers. Therefore, the IDMA request bit is reset by writing "0" and set
by w riting "1". In this case all IDMA request bits for which "0" has been written are reset. Even in a read-modify-
wri te operation, an IDMA request bit can be reset by the hardware between the read and the write, so be careful
when using this met ho d.
Aft er an initial reset, IDMAONLY is set to "1" (set-only method).
II CORE BLOCK: ITC (In t errupt Controller)
S1C33L03 FUNCTION PART EPSON B-II-5-21
A-1
B-II
ITC
DENONLY:IDMA enable register set met ho d sele ct io n
(D2) / Flag set/reset method select register (0x4029F)
Select the method for setting the IDMA enable registers.
Write "1": Set- only method
Write "0": Rea d/write method
Read: Valid
With the s et-only method, IDMA enable bits are set by writing "1".
The IDMA enable bits for which "0" has been written can neither be set nor reset. Therefore, this method ensures
that only a specific IDMA enable bit is set. However, when using read-modify-write instructions (e.g., bset, bclr, or
bnot), note that an IDMA enable bit that has been set to "1" is not reset by writing.
The r ea d/ write method i s s el ec ted by writin g "0" to DENONL Y. When this method is selec ted, IDMA enable bits
can be read and written as for other registers. Therefore, the IDMA enable bit is reset by writing "0" and set by
writing "1". In this case all IDMA enable bits for which "0" has been written are reset. Even in a read-modify-write
operation, an interrupt enable bit can be reset by the hardware between the read and the write, so be careful when
using this m et ho d.
Aft er an init ia l reset, DENONLY is set to "1" (set-only method).
SIO2ES0:SIO Ch.2 receive error/FP0 interrupt factor switching
(D0) / Interrupt factor FP function switching register (0x402C5)
Switches the interrupt factor.
Write "1": S IO Ch.2 receive error
Write "0": FP0 input
Read: Valid
Set to "1" to use the SIO Ch.2 receive error interrupt.
Set to "0" to use the FP0 input interrupt.
At po wer-on, this bit is set to "0".
SIO2RS0:SIO Ch.2 receive-buffer full/FP1 interrupt factor switching
(D1) / Interrupt factor FP function switching register (0x402C5)
Switches the interrupt factor.
Write "1": S IO Ch.2 receive-buffer full
Write "0": FP1 input
Read: Valid
Set to "1" to use the SIO Ch.2 receive-buffer full interrupt.
Set to "0" to use the FP1 input interrupt.
At po wer-on, this bit is set to "0".
SIO3ES0:SIO Ch.3 receive error/FP2 interrupt factor switching
(D2) / Interrupt factor FP function switching register (0x402C5)
Switches the interrupt factor.
Write "1": S IO Ch.3 receive error
Write "0": FP2 input
Read: Valid
Set to "1" to use the SIO Ch.3 receive error interrupt.
Set to "0" to use the FP2 input interrupt.
At po wer-on, this bit is set to "0".
II CORE BLOCK: ITC (In t errupt Controller)
B-II-5-22 EPSON S1C33L03 FUNCTION PART
SIO2TS0:SIO Ch.2 transmit-buffer empty/FP3 interrupt factor switching
(D3) / Interrupt factor FP function switching register (0x402C5)
Switches the interrupt factor.
Write "1": S IO Ch.2 transmit-buffer empty
Write "0": FP3 input
Read: Valid
Set to "1" to use the SIO Ch.2 transmit-buffer empty interrupt.
Set to "0" to use the FP3 input interrupt.
At po wer-on, this bit is set to "0".
SIO3RS0:SIO Ch.3 receive-buffer full/FP4 interrupt factor switching
(D4) / Interrupt factor FP function switching register (0x402C5)
Switches the interrupt factor.
Write "1": S IO Ch.3 receive-buffer full
Write "0": FP4 input
Read: Valid
Set to "1" to use the SIO Ch.3 receive-buffer full interrupt.
Set to "0" to use the FP4 input interrupt.
At po wer-on, this bit is set to "0".
T8CH4S0: 8-bit timer 4 underfl ow/FP 5 inter rupt factor swi tching
(D5) / Interrupt factor FP function switching register (0x402C5)
Switches the interrupt factor.
Write "1": 8 -bit ti mer 4 underflow
Write "0": FP5 input
Read: Valid
Set to "1" to use the 8-bit timer 4 underflow interrupt.
Set to "0" to use the FP5 input interrupt.
At po wer-on, this bit is set to "0".
SIO3TS0: SIO Ch.3 transmit-buffer empty/FP6 interrupt factor switching
(D6) / Interrupt factor FP function switching register (0x402C5)
Switches the interrupt factor.
Write "1": S IO Ch.3 transmit-buffer empty
Write "0": FP6 input
Read: Valid
Set to "1" to use the SIO Ch.3 transmit-buffer empty interrupt.
Set to "0" to use the FP6 input interrupt.
At po wer-on, this bit is set to "0".
T8CH5S0: 8-bit timer 5 underflow/FP7 interrupt factor switching
(D7) / Interrupt factor FP function switching register (0x402C5)
Switches the interrupt factor.
Write "1": 8 -bit ti mer 5 underflow
Write "0": FP7 input
Read: Valid
Set to "1" to use the 8-bit timer 5 underflow interrupt.
Set to "0" to use the FP7 input interrupt.
At po wer-on, this bit is set to "0".
II CORE BLOCK: ITC (In t errupt Controller)
S1C33L03 FUNCTION PART EPSON B-II-5-23
A-1
B-II
ITC
SIO2RS1: SIO Ch.2 receive-buffer full/TM16 Ch.5 compare B interrupt factor switching
(D0) / Interrupt factor TM16 function switching register (0x402CB)
Switches the interrupt factor.
Write "1": S IO Ch.2 receive-buffer full
Write "0": T M16 Ch.5 compare B
Read: Valid
Set to "1" to use the SIO Ch.2 receive-buffer full interrupt.
Set to "0" to use the TM16 Ch.5 compare B interrupt.
At po wer-on, this bit is set to "0".
SIO2TS1: SIO Ch.2 transmit-buffer empty/TM16 Ch.5 compare A interrupt factor switching
(D1) / Interrupt factor TM16 function switching register (0x402CB)
Switches the interrupt factor.
Write "1": S IO Ch.2 transmit-buffer empty
Write "0": T M16 Ch.5 compare A
Read: Valid
Set to "1" to use the SIO Ch.2 transmit-buffer empty interrupt.
Set to "0" to use the TM16 Ch.5 compare A interrupt.
At po wer-on, this bit is set to "0".
SIO3RS1: SIO Ch.3 receive-buffer full/TM16 Ch.4 compare B interrupt factor switching
(D2) / Interrupt factor TM16 function switching register (0x402CB)
Switches the interrupt factor.
Write "1": S IO Ch.3 receive-buffer full
Write "0": T M16 Ch.4 compare B
Read: Valid
Set to "1" to use the SIO Ch.3 receive-buffer full interrupt.
Set to "0" to use the TM16 Ch.4 compare B interrupt.
At po wer-on, this bit is set to "0".
SIO3TS1: SIO Ch.3 transmit-buffer empty/TM16 Ch.4 compare A interrupt factor switching
(D3) / Interrupt factor TM16 function switching register (0x402CB)
Switches the interrupt factor.
Write "1": S IO Ch.3 transmit-buffer empty
Write "0": T M16 Ch.4 compare A
Read: Valid
Set to "1" to use the SIO Ch.3 transmit-buffer empty interrupt.
Set to "0" to use the TM16 Ch.4 compare A interrupt.
At po wer-on, this bit is set to "0".
SIO2ES1: SIO Ch.2 receive error/TM16 Ch.3 compare B interrupt factor switching
(D4) / Interrupt factor TM16 function switching register (0x402CB)
Switches the interrupt factor.
Write "1": S IO Ch.2 receive error
Write "0": T M16 Ch.3 compare B
Read: Valid
Set to "1" to use the SIO Ch.2 receive error interrupt.
Set to "0" to use the TM16 Ch.3 compare B interrupt.
At po wer-on, this bit is set to "0".
II CORE BLOCK: ITC (In t errupt Controller)
B-II-5-24 EPSON S1C33L03 FUNCTION PART
SIO3ES1:SIO Ch.3 receive error/TM16 Ch.3 compare A interrupt factor switching
(D5) / Interrupt factor TM16 function switching register (0x402CB)
Switches the interrupt factor.
Write "1": S IO Ch.3 receive error
Write "0": T M16 Ch.3 compare A
Read: Valid
Set to "1" to use the SIO Ch.3 receive error interrupt.
Set to "0" to use the TM16 Ch.3 compare A interrupt.
At po wer-on, this bit is set to "0".
T8CH4S1:8-bit ti mer 4 underfl ow/T M16 Ch.2 compare B interrupt f actor switching
(D6) / Interrupt factor TM16 function switching register (0x402CB)
Switches the interrupt factor.
Write "1": 8 -bit ti mer 4 underflow
Write "0": T M16 Ch.2 compare B
Read: Valid
Set to "1" to use the 8-bit timer 4 underflow interrupt.
Set to "0" to use the TM16 Ch.2 compare B interrupt.
At po wer-on, this bit is set to "0".
T8CH5S1:8-bit ti mer 5 underfl ow/TM 16 Ch.2 compare A interrupt f actor switching
(D7) / Interrupt factor TM16 function switching register (0x402CB)
Switches the interrupt factor.
Write "1": 8 -bit ti mer 5 underflow
Write "0": T M16 Ch.2 compare A
Read: Valid
Set to "1" to use the 8-bit timer 5 underflow interrupt.
Set to "0" to use the TM16 Ch.2 compare A interrupt.
At po wer-on, this bit is set to "0".
TBRP7–TBRP0: TTBR regist er write protection ([D[7:0]) / TTBR write-protect register (0x4812D)
Remove write protection for the TTBR register.
Write 0x59: Write protection is removed
Write not the above: No operation (write protected)
Read: Valid
Before writing to the TTBR register, set TBRP to "0x59" to remove the write protection. Then when data is written
to the most significant byte (0x48137) of the TTBR, the register once again becomes write-protected.
Aft er an initial reset, TBRP is set to "0x0" (write protected).
II CORE BLOCK: ITC (In t errupt Controller)
S1C33L03 FUNCTION PART EPSON B-II-5-25
A-1
B-II
ITC
TTBR09–TTBR00:Trap table base address [9:0] (D[9 :0 ]) / T TBR low -or der re gi st er (0 x4 8 134[ HW])
TTBR15–TTBR10:Trap table base address [1 5:10 ] (D[F: A ]) / T TB R lo w -order re gist er ( 0 x4 8134[HW] )
TTBR2B–TTBR20:Trap table base address [27:16] (D[B:0]) / TTBR high-order register (0x48136[HW])
TTBR33–TTBR30:Trap table base address [31:28] (D[F:C]) / TTBR high-order register (0x48136[HW])
Set the starting address of the trap table.
TTBR0 and TTBR3 are read-only registers and are fixed to "0". For this reason, the trap table starting address
always begins with a 1KB bo unda ry address.
The TTBR register s norm ally are write-protected to prevent them from being inadvertently rewritten. To remove
this write protect function, another register, TBRP (D[7:0]) / TTBR write-protect register (0x4812D), is provided.
A wri te to the TTBR register is enabled by writing "0x59" to TBRP and is disabled back again by a write to the
most significant byte of the TTBR register (0x48137). Consequently, writes to the TTBR register need to begin
with the low-order half-word first. However, since occurrences of NMI and the like between writes of the low-
order and high-order half-wo rds cause m alfunc tions, it i s recom mended that the register be w ritten in words .
Aft er an initial reset, the TTBR register is set to 0x0C00000.
Pr ogramming Notes
(1) In cases when an interrupt factor that is used for restarting from the standby mode has been set to invoke
IDMA, IDMA is started up by the interrupt at its occurrence. In SLEEP mode, the high-speed (OSC3)
oscillation cir cuit also starts operatin g. Ho w eve r, if an interr upt to be generated upon complet ion of IDMA is
disabled at the setting of IDMA side, no interrupt request is signaled to the CPU. Therefore, the CPU remains
idle until the next interrupt request is generated.
(2) As the S1C33000 Core CPU function, the IL allows interrupt levels to be set in the range of 0 to 15. However,
since the interrupt priority register in the C33 Core Block consists of three bits, interrupt levels in each
interrupt system can only be set for up to 8.
(3) When the reset-only method is used to reset the interrupt factor flag (by writing "1"), if a read-modify-write
instruction (e.g., bset, bclr, or bnot) is executed, the other interrupt factor flags at the same address that have
been set to "1" are reset by a write. This requires caution. In cases when the read/write method is used to reset
the interrupt factor flag (by writing "0"), all factor flags for which "0" has been written are reset. When a
read-modify-write operation is performed, an interrupt factor may occur between reads and writes, so be
careful when using this method.
The same applies to the set-only method and read/write method for the IDMA request and IDMA enable
registers.
(4) After an initial reset, the interrupt factor flags and interrupt priority registers all become indeterminate. To
preve nt unw anted in terrupts or IDMA requests from being generated inadvertently, be sure to reset these
flags and registers in the software application.
(5) To prevent another interrupt from being generated for the same factor again after generation of an interrupt,
be sure to reset the interrupt factor flag before enabling interrupts and setting the PSR again or executing the
reti in struc tio n.
II CORE BLOCK: ITC (In t errupt Controller)
B-II-5-26 EPSON S1C33L03 FUNCTION PART
TH IS PAGE IS BLANK.
II CORE BLOCK: CLG (Clock Generator)
S1C33L03 FUNCTION PART EPSON B-II-6-1
A-1
B-II
CLG
II-6 CLG (Clock Generator)
This section describes the method for controlling the system clock.
Configuration of Clock Generator
The C33 Co re Block has a built- in clock generator that consists of a high-speed oscill ation circuit (OSC3) and a
PLL.
The hig h-speed (OSC3) oscillation cir cuit generates the main clo ck for the CPU and internal peripheral circuits
(e.g., DMA, serial interface, programmable timer, and A/D converter).
Furthermore, the clock generator can input a sub clock, such as low-speed (OSC1, 32.768 kHz, Typ.) clock
generated by the Peripheral Block, for the clock timer and for operating the CPU at a low clock speed in order to
reduce current consumption.
Note: When the Peripheral Block including the low-speed (OSC1) oscillation circuit is used, the source
clocks for the CPU and the peripheral circuits (e.g., serial int erface, pro grammable t imer, and A/D
converter) can be selected between t he OSC3 clock and the OSC1 clock. For details, refe r to
"Setting and Switching Over the CPU O perating Cl ock" i n this se ction and "Prescale r" and "Low-
Speed (OSC1) Oscillation Circuit" of the Peripheral Block.
Figure 6.1 shows the configuration of the clock generator.
High-speed (OSC3)
oscillation circuit Clock
switch
CLKCHG
To CPU
SLEEP
OSC3
OSC4
HALT, HALT2,
SLEEP
SOSC3
Oscillation ON/OFF CLKDT[1:0]
Divider
1/1 to 1/8
To BCU and DMA
HALT2, SLEEP
To peripheral circuits
To peripheral circuits
and clock timer
SLEEP
PLL
PLLC
PLLS0
PLLS1
Low-speed (OSC1)
oscillation circuit
SOSC1
Oscillation ON/OFF
OSC1
OSC2
CLG
Peripheral Block
Figur e 6.1 Configuration of Clock Generator
Aft er an initial reset, the output (OSC3 clock) of the high-speed (OSC3) oscillation circuit is set for the CPU
operating clock.
When the low-speed (OSC1) oscillation circuit is used, the CPU operating clock can be switched to the output
(OSC1 clock) of the low-speed (OSC1) oscillation circuit in a program. Furthermore, each oscillation circuit can be
stopped in a program.
If the OSC3 clock is unnecessary such as when performing clock processing only, set the OSC1 clock for operation
of the CPU and turn off the high-speed (OSC3) oscillation circuit in order to reduce current consumption. In
addition, when SLEEP mode is set, the high-speed (OSC3) oscillation circuit is turned off, greatly reducing current
consumption (no internal units except for the clock timer need to be operated).
II CORE BLOCK: CLG (Clock Generator)
B-II-6-2 EPSON S1C33L03 FUNCTION PART
I/O Pins of Clock Generator
Table 6.1 lists the I/O pins of the clock generator.
Table 6.1 I/O Pins of Clock Generator
Pin name I/O Function
OSC3 I High-speed (OSC3) oscillation input pin
Crystal/ceramic oscillation or external clock input
OSC4 O High-speed (OSC3) oscillation output pin
Crystal/ceramic oscillation (open when external clock is used)
PLLC – Capasitor connecting pin for PLL
PLLS[1:0] I PLL set-up pins
PLLS1 PLLS0 fin (fOSC3)fout (fPSCIN)
1110–25MHz 20–50MHz ∗1
0110–12.5MHz 40–50MHz ∗1
00PLL is not used L ∗2
∗1: ROM-less model with 3.3 V ± 0.3 V operating voltage
∗2: When the PLL is not used, the OSC3 clock is used directly.
High-Speed (OSC3) Oscillation Circuit
The hig h-speed (OSC3) oscillation cir cuit generates the main clo ck for the CPU and internal peripheral circuits
(e.g., DMA, serial interface, programmable timer, and A/D converter).
This cir cuit can be a crystal or a ceramic oscillation circuit. Optionally an external clock source can be used.
Figure 6.2 show s the structure of the high-speed (OSC3) oscillat ion circuit.
V
SS
OSC4
OSC3
R
f
C
D2
C
G2
Oscillation circuit
control signal
SLEEP status
Oscillation circuit
control signal
SLEEP status
X'tal2
or
Ceramic
f
OSC3
OSC4
OSC3
External
clock
N.C.
V
SS
V
DD
f
OSC3
(
1
)
Cr
y
stal/ceramic oscillation circuit
(
2
)
External clock in
p
ut
Figur e 6.2 High-Speed (OSC3) Oscillation Circuit
When using a crystal or a ceramic oscillation for this circuit, connect a crystal (X'tal2) or ceramic (Ceramic)
resonator and feedback resistor (Rf) between the OSC3 and OSC4 pins, and two capacitors (CG2, CD2) betw ee n th e
OSC3 pi n and VSS and the OSC4 pin and VSS, re spec tively .
When an external clock is used, leave the OSC4 pin open and input a square-wave clock to the OSC3 pin.
The range of oscillation frequencies is 10 MHz to 33 MHz. This frequency range also applies when an external
clock is used.
Note: When using the PLL, the oscillation frequency range changes according to the PLL setting. See
Table 6.2.
For details on osc illation characteristics and the external clock input characteristics, refer to "Electrical
Characteristics".
II CORE BLOCK: CLG (Clock Generator)
S1C33L03 FUNCTION PART EPSON B-II-6-3
A-1
B-II
CLG
PLL
The PLL inputs the OSC3 clock and multiply its frequency. The multiply mode should be set using the PLLS[1:0]
pins according to the OSC3 clock frequency.
Table 6.2 Setting the PLLS[1:0] Pins
PLLS1 PLLS0 Mode fin (OSC3 clock) fout Notes
11 x210 to 25 MHz 20 to 50 MHz No ROM, and 3.3 V ± 0.3 V
01 x410 to 12.5 MHz 40 to 50 MHz No ROM, and 3.3 V ± 0.3 V
00 PLL
Not used –Not used
Figure 6.3 shows a basic external connection diagram for the PLL pins.
V
SS
PLLS1
PLLS0
PLLC
PLL
100 pF
5 pF
4.7 kΩ
V
DD
Figur e 6.3 External Connection Diagram
Note: When the PLL is not used, the OSC3 oscillation output is used as the source clock. In this case,
the oscillation frequency range is 10 MHz to 33 MHz. Furthermore, leave the PLLC pin open.
Controlling Osc illat ion
The high-speed (OSC3) oscillation circuit can be t urned on or off using SOSC3 (D1) / Power control register
(0x40180).
The osc illation circuit is turned off by writing "0" to SOSC3 and turned back on again by writing "1". SOSC3 is set
to "1" at initial reset, so the oscillation circuit is turned on.
Notes:•When the high-speed (OSC3) oscillation circuit is used as the clock source for the CPU
operating clock, it cannot be turned off. In this case, writing "0" to SOSC3 is ignored. Note also
that writing to SOSC3 is allowed on ly when the power-control register protect ion fla g is set to
"0b10010110".
•Immediately after the oscillation circuit is turned on, a certain period of time is required for
oscillation to stabilize (for 3.3-V crystal resonator, this time is 10 ms max.). To prevent the
device from operating erratically, do not use the clock until its oscillation has stabilized.
The high-speed (OSC3) oscillat ion circuit turns off when the CPU is set in SLEEP mode.
II CORE BLOCK: CLG (Clock Generator)
B-II-6-4 EPSON S1C33L03 FUNCTION PART
Setting and Switching Over the CPU Operating Clock
Setting the CPU operating clock frequency
When oper ating the CPU with the high-speed (OSC3) clock, the operating frequency can be switched over in
four steps. Use CLKDT[1:0] (D[7:6]) / Power control register (0x40180) for this switchover.
Table 6.3 Setting of CPU Operating Clock
CLKDT1 CLKDT0 Division ratio
11 fout/8
10 fout/4
01 fout/2
00 fout/1
fout: PLL output
The clock thus set becomes the system clock, which is used as the CPU operating clock and the bus clock.
At i nitial reset, the division ratio is set to fout/1, so the CPU is operated directly by the PLL output clock.
Since the device's current consumption can be decreased by reducing the CPU operating speed, switch over
the operating frequency as necessary.
This setting is effective only for the high-speed (OSC3) clock, and has no effect when the low-speed (OSC1)
clock is used as the system clock.
Note: Writing to CLKDT[1:0] is effective only when the power-control register protection flag is set to
"0b10010110".
Switching ov er the CPU operati ng clock
Note: The CPU operati ng clock can be sw itche d from O SC3 to O SC1 on ly when the low- spee d (OSC1)
oscillation circuit in the Peripheral Block is used.
Aft er an initial reset, the CPU starts operating using the OSC3 clock. All internal peripheral circuits also
operate.
In cases in which some peripheral circuits (e.g., programmable timer, serial interface, A/D converter, and
ports) do not need to be operate or pr oce ssing in low-speed operation is possible, and the CPU c an process its
jobs at a low clock speed, the CPU operating clock can be switched to the OSC1 clock, thereby reducing
current consumption. Use CLKCHG (D2) / Power control register (0x40180) to switch over the operating
clock.
Procedu re for switchi ng over from the OSC3 clock to the OSC1 clock
1. Turn on the low-speed (OSC1) oscillation circuit (by writing "1" to SOSC1).
2. W ait until the OSC1 oscillation stabilizes (three seconds or more).
3. Change the CPU ope ratin g clock (by writi ng "0" to CLKCH G ).
4. Turn off the high-speed (OSC3) oscillation circuit (by writing "0" to SOSC3).
∗ Steps 1 and 2 are required only when the low-speed (OSC1) oscillation circuit is inactive.
Notes:•Use separate instructions to switch from OSC3 to OSC1 and turn the OSC3 oscillation off. If
these operations are processed simultaneously us ing one instr uction, t he CPU may operate
erratically.
•Make sure the operation of t he peripheral cir cuits, such as the programm able timer and serial
interface is terminated before the OSC3 oscillation is turned off in order to prevent them from
operating err atically or the prescaler clo ck is set as OS C1. In additi on, in order to prevent
incorrect operation, a set up of prescaler must be performed before changing the CPU clock.
Procedu re for switchi ng over from the OSC1 clock to the OSC3 clock
1. Turn on the high-speed (OSC3) oscillation circuit (by writing "1" to SOSC3).
2. W ait until the OSC3 oscillation stabilizes (10 ms or more for a 3.3-V crystal resonator).
3. Switch over the CPU operating clock (by writing "1" to CLKCHG).
Note: The operating clock switchover by CLKCHG is effective only when both oscillation circuits are on
and the power-control reg ister protect ion fla g is set to " 0b10 01011 0" .
II CORE BLOCK: CLG (Clock Generator)
S1C33L03 FUNCTION PART EPSON B-II-6-5
A-1
B-II
CLG
Power-Control Register Protection Flag
The power-control register at address 0x40180, w hich is used to control the oscillation circuits and the CPU
operating clock, is norm ally disabled against writing in order to prevent it from malfunctioning due to unnecessary
writing.
To enable this register for writing, the power-control register protection flag CLGP[7:0] (D[7:0]) / Power-control
protection register (0x4019E) must be set to "0b10010110". Note that this setting allows for the power-control
register (0x40180) to be written to only once, so all bits of CLGP[7:0] are cleared to "0" when this address is
written to. Therefore, CLGP[7:0] must be set to "0b10010110" each time the power-control register (0x40180) is
written to.
The flag CL GP[7:0] does not affect the readout from the power-control register (0x40180).
Operation in Standby Mode
In HALT mode, which is entered by executing the halt instruction, the high-speed (OSC3) and low-speed (OSC1)
oscillation circuits both retain their status before HALT mode is entered. Under normal conditions, therefore, there
is no need to control the oscillation circuits before entering or after exiting HALT mode.
The high-speed (OSC3) osc illat ion circuit stops op erating afte r SLEEP mode is entered, which is done by
executing the slp (sleep) instruction. If the high-speed (OSC3) oscillation circuit was operating before SLEEP
mode was entered, it automatically starts oscillating again after SLEEP mode is exited.
In addition, if the CPU was operating using the OSC3 clock before SLEEP mode was entered, the CPU starts
operati ng us ing the OSC3 clock again even after SLEEP mode is exited. The high-speed (OSC3) oscillation circuit
requires 10 ms max. (when using a 3.3-V crystal resonator) for its oscillation to stabilize after oscillation starts. To
prevent the CPU from operating erratically upon restart during this period, the C33 Core Block is designed to allow
the OSC3 clock supply to the CPU to be disabled in the hardware after SLEEP mode is exited. Use 8T1ON (D2) /
Clock option register (0x40190) to select this function. Use 8-bit programmable timer 1 to set the waitting time
before clock supply is started.
The pro cessing procedure and the operations to be performed when this function is used are as follows:
1. Disable the 8-bit pr ogrammable timer 1 interrupt.
2. Preset the initial count to 8-bit programmable timer 1.
Set a value that will provide an ample stabilization waiting time. It is also necessary to set the input clock for 8-
bit programmable timer 1 using the prescaler.
3. Enable the interrupt used to exit SLEEP mode.
Before enabling the interrupt, be sure to reset the interrupt factor flag.
4. Write "0" to 8T1ON (turn on the func tio n for waiting until the oscillation stabilizes after exiting SLEEP mode).
5. Activate 8-bit programmable timer 1 to start counting.
6. Ent er SLEEP mode usi ng the slp instruction.
:
SL EEP mo de
:
7. Exi t SLEE P m ode using an NMI, input port, or timer interrupt.
8. The high-speed (OSC3) oscillat ion circuit star ts oscillating when SLEEP mode is exited. 8-bit programmable
timer 1 also is made to start counting using the OSC3 clock.
9. 8-bit pr ogrammabl e timer 1 underflow s.
The ope rating clock supply to the CPU is begun by the underflow signal, so that the CPU restarts.
For details on how to control the 8-bit programmable timer, prescaler, and interrupts, refer to the description of
each item in this manual.
Note: The function for waiting until the high-speed (OSC3) oscillation is stabilized by 8T1ON is effective
only when SLEEP mode is exite d.
Writing to 8T1ON is effective only when the power-control register protection flag is set to
"0b10010110".
II CORE BLOCK: CLG (Clock Generator)
B-II-6-6 EPSON S1C33L03 FUNCTION PART
I/O Memo ry of Clock Generato r
Table 6.4 lists t he control bits of clock generator.
Table 6.4 Control Bits of Clock Generator
NameAddressRegister name Bit Function Setting Init. R/W Remarks
CLKDT1
CLKDT0
PSCON
–
CLKCHG
SOSC3
SOSC1
D7
D6
D5
D4–3
D2
D1
D0
System clock division ratio
selection
Prescaler On/Off control
reserved
CPU operating clock switch
High-speed (OSC3) oscillation On/Off
Low-speed (OSC1) oscillation On/Off
1 On 0 Off
1 OSC3 0 OSC1
1 On 0 Off
1 On 0 Off
0
0
1
0
1
1
1
R/W
R/W
–
R/W
R/W
R/W
Writing 1 not allowed.
0040180
(B) 1
1
0
0
1
0
1
0
CLKDT[1:0] Division ratio
1/8
1/4
1/2
1/1
–
Power control
register
–
HLT2OP
8T1ON
–
PF1ON
D7–4
D3
D2
D1
D0
–
HALT clock option
OSC3-stabilize waiting function
reserved
OSC1 external output control
–
0
1
0
0
–
R/W
R/W
–
R/W
0 when being read.
Do not write 1.
0040190
(B) 1 On 0 Off
1 Off 0 On
1 On 0 Off
–
–
Clock option
register
Writing 10010110 (0x96)
removes the write protection of
the power control register
(0x40180) and the clock option
register (0x40190).
Writing another value set the
write protection.
CLGP7
CLGP6
CLGP5
CLGP4
CLGP3
CLGP2
CLGP1
CLGP0
D7
D6
D5
D4
D3
D2
D1
D0
Power control register protect flag 0
0
0
0
0
0
0
0
R/W004019E
(B)
Power control
protect register
SOSC1: Low-speed (OSC1) oscillation control (D0) / Power control register (0x40180)
Turns the low-speed (OSC1) os cillati on on or off.
Write "1": O SC1 osci lla tio n tu rn ed on
Write "0": O SC1 oscilla tio n tu rn ed off
Read: Valid
The osc illation of the low-speed (OSC1) oscillation circuit is stopped by writing "0" to SOSC1, and started again
by w riting "1".
Since a duration of maximum three seconds is required for oscillation to stabilize after the oscillation has been
restarted, at least this length of time must pass before the OSC1 clock can be used.
Writing to SOSC1 is allowed only when CLGP[7:0] is set to "0b10010110". Note also that if the CPU is operating
using the OSC1 clock, writing "0" to SOSC1 is ignored and the oscillation is not turned off.
At i nitial reset, SOSC1 is set to "1" (OSC1 oscillation turned on).
Note: This control bit is effective only when the low-speed (OSC1) oscillation circuit in the Peripheral
Block is us ed.
SOSC3: High-speed (OSC3) oscillation control (D1) / Power control register (0x40180)
Turns the high-speed (OSC3) oscillat ion on or off.
Write "1": O SC3 osci lla tio n tu rn ed on
Write "0": O SC3 oscillation turned off
Read: Valid
The osc illation of the high-speed (OSC3) oscillation circuit is stopped by writing "0" to SOSC3, and started again
by w riting "1".
Since a duration of maximum 10 ms (for a 3.3-V crystal resonator) is required for oscillation to stabilize after the
oscillation has been restarted, at least this length of time must pass before the OSC3 clock can be used.
Writing to SOSC3 is allowed only when CLGP[7:0] is set to "0b10010110". Note also that if the CPU is operating
using the OSC3 clock, writing "0" to SOSC3 is ignored and the oscillation is not turned off.
At i nitial reset, SOSC3 is set to "1" (OSC3 oscillation turned on).
II CORE BLOCK: CLG (Clock Generator)
S1C33L03 FUNCTION PART EPSON B-II-6-7
A-1
B-II
CLG
CLKCHG: CPU operating clo ck switch (D2) / Power control r egister (0x40180 )
Selects the CPU operating clock.
Write "1": O SC3 clock
Write "0": O SC1 clock
Read: Valid
The OSC3 clock is selected as the CPU operating clock by writing "1" to CLKCHG, and OSC1 is selected by
writing "0". The operating clock can be switched over in this way only when both the high-speed (OSC3) and low-
speed (OSC1) oscillation circuits are on. In addition, writing to CLKCHG is effective only when CLGP[7:0] is set
to "0b10010110". Immediately after the oscillation circuit has started oscillating, wait for the oscillation to stabilize
before switching over the CPU operating clock.
At i nitial reset, CLKCHG is set to "1" (OSC3 clock).
Note: This control bit is effective only when the low-speed (OSC1) oscillation circuit in the Peripheral
Block is us ed.
CLKDT1–CLKDT0: CPU op erati ng frequency selection (D[7:6]) / Power cont rol regis ter (0x 40180 )
Select the CPU operating clock frequency.
Table 6.5 Setting of CPU Operating Clock
CLKDT1 CLKDT0 Division ratio
11 fout/8
10 fout/4
01 fout/2
00 fout/1
fout: PLL output
This setting is effective when the CPU is operated using the high-speed (OSC3) clock and has no effect on the low-
speed (OSC1) clock. Writing to CLKDT[1:0] is allowed only when CLGP[7:0] is set to "0b10010110".
At i nitial reset, CLKDT is set to "0" (fout/1).
8T1ON: High-s p eed (OS C 3) o scilla tio n wai tin g func tio n (D2) / Clo ck option regi st er (0x4 0 190)
Sets the function for waiting until the high-speed (OSC3) oscillation stabilizes after SLEEP mode is exited.
Write "1": Off
Write "0": On
Read: Valid
After SL EEP mode is exited, the high-speed (OSC3) oscillation waiting function is effective by writing "1" to
8T1ON. For this function to be used, the waiting time must be set in 8-bit programmable timer 1 to allow it to start
counting before entering SLEEP mode. After SLEEP mode is exited, the OSC3 clock is not supplied to the CPU
until 8-bit programmable timer 1 underflows. This function will not work when 8T1ON is set to "0".
The high-speed (OSC3) oscillat ion waiting function is effective only when SLEEP mode is exited.
Writing to 8T1ON is effective only when CLGP[7:0] is set to "0b10010110".
When writ ing to 8T1O N , alway s be sure to write "0" to the reserved bits at a ddre ss 0x4019 0.
At i nitial reset, 8T1ON is set to "1" (Off).
HLT2OP: HALT clock option (D3) / Clock op tion r egister (0x40190)
Select a HALT condition (basic mode or HALT2 m ode ).
Write "1": H ALT2 mode
Write "0": Bas ic mode
Read: Valid
When "1" is written to HLT2OP, the CPU will enter HALT2 mode when the HALT instruction is executed. When
"0" is written, the CPU will enter basic mode.
Writing to HLT2OP is allowed only when CLGP[7:0] is set to "0b10010110".
At i nitial reset, HLT2OP is set to "0" (basic mode).
The following shows the operating status in HALT mode (basic mode and HALT2 mode) and SLEEP mode.
II CORE BLOCK: CLG (Clock Generator)
B-II-6-8 EPSON S1C33L03 FUNCTION PART
Table 6.6 Operating Status in Standby Mode
Standby mode Operating status Reactivating factor
HALT mode Basic mode • The CPU clock is stopped. (CPU stop status)
•BCU clo ck is supplied. (BCU run status)
•DMA clock is not stopped. (DMA run status)
•Clocks for the peripheral circuits maintain the
status before entering HALT mode. (run or
stop)
•The high-speed oscillation circuit maintains
the status before entering HALT mode.
•The low-speed oscillation circuit maintains
the status before entering HALT mode.
•Reset, NMI
•Enabled (not m asked) interrupt
factors
HALT 2 m ode • The CPU cl ock is stopped. (CPU stop status)
•BCU clo ck is stopped. (BCU stop status)
•DMA clock is stopped. (DMA stop status)
•Clocks for the peripheral circuits maintain the
status before entering HALT mode. (run or
stop)
•The high-speed oscillation circuit maintains
the status before entering HALT mode.
•The low-speed oscillation circuit maintains
the status before entering HALT mode.
A restart is possible only in the
case of:
•Reset, NMI
•Enabled (not m asked) interrupt
factors
Note, however, that an interrupt
from a peripheral circuit can restart
the CPU only when the operating
clock is supplied to the peripheral
circuit.
SLEEP mode • The CPU clock is stopped. (CPU stop status)
•BCU clo ck is stopped. (BCU stop status)
•Clocks for the peripheral circuits are stopped.
•The high-speed oscillation circuit is stopped.
•The low-speed oscillation circuit maintains
the status before entering SLEEP mode.
•Reset, NMI
•Enabled (not masked) input port
interrupt factors
•Clock timer interrupt when the
low-speed oscillation circuit is
being operated
CLGP7–CLGP0: Power-control register protection flag ([D[7:0]) / Power control protection register (0x4019E)
These bits remove the protection against writi ng to add resses 0x4018 0 and 0x4019 0.
Write "0b100 10 11 0" : Writ e p rotecti o n rem ov ed
Write othe r than the above: No operation (write-protected)
Read: Valid
Before writing to address 0x40 180 or 0x40 190, set CLGP[ 7:0] to "0b10010110" to remove the protection against
writing to that address. This clearing of write protection is effective for only one writing, so the bits are cleared to
"0b00000000" by one writing. Therefore, CLGP[7:0] must be set each time the protected address is written to.
At i nitial reset, CLGP is set to "0b00000000" (write-protected).
II CORE BLOCK: CLG (Clock Generator)
S1C33L03 FUNCTION PART EPSON B-II-6-9
A-1
B-II
CLG
Pr ogramming Notes
(1) Immediately after the high-speed (OSC3) oscillation circuit is turned on, a certain period of time is required
for oscillation to stabilize (for a 3.3-V crystal resonator, this time is 10 ms max.). To prevent the device from
operating erratically, do not use the clock until its oscillation has stabilized.
In particular, if the CPU is set in SLEEP mode during operation using the OSC3 clock, the high-speed
(OSC3) oscillation circuit is turned off during in SLEEP mode and starts oscillating again after SLEEP mode
is exited. To prevent the CPU from operating erratically at restart due to an unstable OSC3 clock, set a
sufficient stabilization waiting time in 8-bit programmable timer 1 to turn on the oscillation stabilization
waiting function after SLEEP mode is exited before entering SLEEP mode.
(2) The oscillation circuit used for the CPU operating clock cannot be turned off.
(3) The CPU operating clock can only be switched over when both the OSC3 and OSC1 oscillation circuits are
on. Furthermore, when turning off an oscillation circuit that has become unnecessary as a result of the CPU
operating clock switchover, be sure to use separate instructions for switchover and oscillation turnoff. If these
two operations are processed simultaneously using one instruction, the CPU may operate erratically.
(4) If the high-speed (OSC3) oscillation circuit is turned off, all peripheral circuits operated using the OSC3
clock will be inactive.
(5) If the OSC3 clock is unnecessary, use the OSC1 clock to operate the CPU and turn the high-speed (OSC3)
oscillation circuit off. This helps reduce current consumption.
(6) In HALT mode, since the DMA and BCU clocks operate, if the next operation is performed in HALT mode,
not HALT2 mode, with a settin g of 0 in clock option regis ter HLT2OP (D3 /0x40190), that operati on will be
an unpredictable erroneous operation.
If a DMA trigger occurs and DMA is invoked while the CPU is stopped after HALT mode execution,
erroneous operation will result. Ensure that DMA is not invoked in HALT mode.
In HALT2 mode, DMA is not invoked since the DMA and BCU clocks are stopped.
(7) In the SLEEP mode, the oscillation circuit clock stops, and in the HALT2 mode, the clocks for peripheral
circuits maintain the status before entering HALT2 (stop or run).
When restarting from this state, interrupt input from a port can be used as a trigger, but functionally, this
interrupt input operates as level input. Therefore, a level input based restart is performed even in the case of
set edge input.
Restart operation is as follows for rising and falling edges.
In case of rising edge interrupt setting: Restarted by high level input.
In case of falling edge interrupt setting: Restarted by low level input.
In normal operation, a restart begins following the elapse of a given time after execution of the SLP
instruction, but when restart by a falling (rising) level (edge) is set, the operation is as follows.
•The restart is effected immediately after execution of the SLP instruction.
•As ports are already at the low level when the SLP instruction is executed, there is no falling (rising) edge,
and therefore the SLEEP state is entered only momentarily, and the restart is effected immediately
afterwards.
There was a syn chronization circuit using a clock signal in the port input circuit, and as the clock is stopped
in the SLEEP state and the clock can be stopped in the HALT2 state, the configuration provided for this
synchronization circuit to be bypassed when restarting. Therefore, a restart is effected when the input level
from a port is active by level. Consequently, the system design should assume that a restart by means of port
input from the SLEEP state or HALT2 state is performed by level.
II CORE BLOCK: CLG (Clock Generator)
B-II-6-10 EPSON S1C33L03 FUNCTION PART
(8) If the IC enters the debug mode through the connected S5U1C33000H (In-Circuit Debugger for S1C33
Family) when the OSC3 clock is divided by 2, 4, or 8 using the CLKDT[1:0] (D[7:6])/Power control register
(0x40180) to generate the CPU clock (CPU_CLK), the division ratio is automatically changed to 1/1. This
may cause the CPU_CLK frequency to exceed the range assumed. Also it affects the BCU_CLK and BCLK
outpu t clocks as they are generated from CPU_CLK. If the BCU_CLK and BCLK output clock frequencies
exceed the access time condition or operating range of the devices driven with these clocks, debugging
functions such as memory dump as well as program execution may not operate correctly. Therefore, prescribe
remedies for malfunctions when debugging, for example, changing the number of wait cycles and other
parameters in the BCU registers using the debugger, so that the program can be executed and debugged
without problems even when the division ratio changes to 1/1.
(9) When the base clock (CPU operating clock) is generated by dividing the source clock output from OSC3 or
PL L by a value (2, 4, or 8) specified using CLKDT[1:0] (D[7:6])/Power control register (0x40180), the
peripheral circuit clocks must be set lower than the base clock frequency using the prescaler. If the peripheral
circuit clock frequency is equal to or higher than the base clock frequency, the peripheral circuit does not
operate normally.
II CORE BLOCK: DBG (Debug Unit)
S1C33L03 FUNCTION PART EPSON B-II-7-1
A-1
B-II
DBG
II-7 DBG (Debug Unit)
Debug Circuit
The C33 Co re Block has a built- in debug circui t.
This fun ctional block is provided to simply realize an advanc ed softwa re developm en t en vi ronm en t.
Note:The debug circuit does not work during normal operati on. To cons truct a software developme nt
environment using the debug circuit, the S5U1C33000 H (In-Ci rcuit Debugge r for S1C33 Fa mily) is
separately required.
I/O Pins of Debug Circuit
Six pins used to exclusively connect the S5U1C33000H (In-Circuit Debugger for S1C33 Family) are reserved for
the debug circuit. The I/O voltage level of these pins is 3.3 V.
Table 7.1 lists t he I/O pins of the debug circuit.
Table 7.1 I/O Pins of Debug Circuit
Pin name I/O Pull-up Initial status Voltage level Function
DCLKO–13.3 V Clock output for debugging
DST2 O– 03.3 V Status output 2 for debugging
DST1 O– 13.3 V Status output 1 for debugging
DST0 O– 13.3 V Status output 0 for debugging
DPCO O– 13.3 V PC output for debugging
DSIO I/O With pull-up 1 (Input) 3.3 V Serial I/O for debugging
The D CLK, D ST[2:0] and DPCO outputs are exten ded functi ons of the I/O port pin s P14, P1[2:0] a nd P13,
respectively. At initial reset, these pins are set as debug signal outputs.
If the debug circuit is not used, these pins can be used for I/O ports or the redefined per iphe ral circuits by writing
"0" to CFEX[1:0] (D[1:0]) / Port function extension register (0x402DF). Refer to "I/O Ports (P Ports)" for the pin
functions.
Note:When these pins are set as debug signal output s, only t he S5 U1C33000H (In-C ircuit Debugge r for
S1C33 Fami ly) can be conn ec ted to t hese pi n s. Le av e the se pin s op en if the S5U1C 330 00 H is no t
connec ted. For connecting the S5U1C 33000 H, ref er to the "S5 U1C33000H Manua l (S1C33
Family In-Circuit Debugger)".
Furthermore, the pin status i s fixed as shown in the above table aft er a user reset.
II CORE BLOCK: DBG (Debug Unit)
B-II-7-2 EPSON S1C33L03 FUNCTION PART
TH IS PAGE IS BLANK.
S1C33L03 FUNCTION PART
III PERIPHERAL BLOCK
III PERIPHERAL BLOCK: INTRODUCTION
S1C33L03 FUNCTION PART EPSON B-III-1-1
A-1
B-III
Intro
III-1 INTRODUCTION
The C33 pe ripheral block consists of a prescal er, six 8-bit programmable timer channels, six 16-bit
programmable timer channels including watchdog timer and event counter functions, four serial interface channels,
inpu t and I/O p ort s, a low -sp eed (O S C1 ) osci llatio n circuit, and a cl oc k time r.
CORE_PAD
Pads
C33_SBUS
C33 Core Block
C33 LCD Controller Block
Pads
PERI_PAD
Pads
C33_PERI
(Prescaler, 8-bit timer, 16-bit timer,
Clock timer, Serial interface, Ports)
C33 Peripheral BlockC33 Analog Block
C33_CORE
(CPU, BCU, ITC, CLG, DBG)
C33_ADC
(A/D converter)
C33 Internal Memory Block
Internal RAM
(Area 0)
Internal ROM
(Area 10)
C33 DMA Block
C33_DMA
(IDMA, HSDMA)
C33_SDRAMC
(SDRAM interface)
C33_LCDC
(LCD panel interface)
C33 SDRAM Controller Block
Figur e 1. 1 Peripheral Block
Note: In te rn al RO M is not prov ided in the S 1C33L03 .
III PERIPHERAL BLOCK: INTRODUCTION
B-III-1-2 EPSON S1C33L03 FUNCTION PART
TH IS PAGE IS BLANK.
III PERIPHERAL BLOCK: PRESCALER
S1C33L03 FUNCTION PART EPSON B-III-2-1
A-1
B-III
PSC
III-2 PRESCALER
Configuration of Prescaler
The prescaler divides the source clock (OSC3/PLL output clock or OSC1 clock) to generate the clocks for the
internal peripheral circuits. The prescaler division ratio can be selected for each peripheral circuit in a program. A
clock control circuit to control the clock supply to each peripheral circuit is also included.
The following are the peripheral circuits that use the output clock:
• 16-bit programmable timers 5 to 0 (and watchdog timer)
• 8-bit programmable timers 5 to 0 (and serial interface)
• A/D converter
Figure 2.1 shows the configuration of the prescaler.
For details on control of each peripheral circuit, refer to each corresponding section in this manual.
Division ratio
select register Selector
Selector 1/21/1 1/4 1/8 1/16 1/32 1/64 1/128 1/256 1/512 1/1024 1/2048 1/4096
Control register
PSCON
θ
OSC3 or
PLL output clock
OSC1 clock
16-bit programmable timer 5–0
Prescaler
output control
8-bit programmable timer 5–0
A/D converter
Figur e 2.1 Configuration of Prescaler and Clock Control Circuit
Source Clock
The sou rce clock for the prescaler can be selected using PSCDT0 (D0) / Prescaler clock select register (0x40181).
When PSCDT0 = "0", the OSC3 clock (when the PLL is not used) or the PLL outpu t clock (when the PLL is used)
is selected.
When PSCDT0 = "1", the OSC1 clock (typ. 32 kHz) is selected.
At i nitial reset, the OSC3/PLL output clock is selected.
Note: For the prescaler clock, the clock source same as the CPU operating clock must be selected.
For details on how to control the oscillation circuit and CPU operating clock, refer to "CLG (Clock Generator)".
At i nitial reset, the OSC3 clock is selected.
The sou rce clock is supplied to the prescaler by writing "1" to PSCON (D5) / Power control register (0x40180). At
initial reset, PSCON is set to "1", so the prescaler is in an operating state. If all of said peripheral circuits can be
turned off and the peripheral circuits (e.g., 16-bit programmable timers (watchdog timer), 8-bit programmable
timers (DRAM refresh), A/D converter, serial interface, and ports) that use the prescaler input clock (the source
clock for prescaler) can be turned off, stop the prescaler by writing "0" to PSCON. This helps to reduce current
consumption.
III PERIPHERAL BLOCK: PRESCALER
B-III-2-2 EPSON S1C33L03 FUNCTION PART
Selecting Division Ratio and Output Control for Prescaler
The prescaler has registers for selecting the division ratio and clock output control separately for each peripheral
circuit described above, allowing each peripheral circuit to be controlled.
The pre scaler' s division ratio can be selected from among eight ratios set for each peripheral circuit through the use
of the division ratio selec tion bits. The divided clock is output to t he co rresponding peripheral circuit by writin g
"1" to the clock control bit.
Table 2.1 Control Bits of the Clock Control Registers
Peripheral circuit Division ratio selection bit Clock control bit
16-bit programmable timer 0 P16TS0[2:0] (D[2:0]/0x40147)∗1P16TON0 (D3/0x40147)
16-bit programmable timer 1 P16TS1[2:0] (D[2:0]/0x40148)∗1P16TON1 (D3/0x40148)
16-bit programmable timer 2 P16TS2[2:0] (D[2:0]/0x40149)∗1P16TON2 (D3/0x40149)
16-bit programmable timer 3 P16TS3[2:0] (D[2:0]/0x4014A)∗1P16TON3 (D3/0x4014A)
16-bit programmable timer 4 P16TS4[2:0] (D[2:0]/0x4014B)∗1P16TON4 (D3/0x4014B)
16-bit programmable timer 5 P16TS5[2:0] (D[2:0]/0x4014C)∗1P16TON5 (D3/0x4014C)
8-bit programmable timer 0 P8TS0[2:0] (D[2:0]/0x4014D)∗2P8TON0 (D3/0 x4 014 D)
8-bit programmable timer 1 P8TS1[2:0] (D[6:4]/0x4014D)∗3P8TON1 (D7/0 x4 014 D)
8-bit programmable timer 2 P8TS2[2:0] (D[2:0]/0x4014E)∗4P8TON2 (D3/0 x4 014 E )
8-bit programmable timer 3 P8TS3[2:0] (D[6:4]/0x4014E)∗2P8TON3 (D7/0 x4 014 E )
8-bit programmable timer 4 P8TS4[2:0] (D[2:0]/0x40145)∗4P8TON4 (D3/0 x4014 5)
8-bit programmable timer 5 P8TS5[2:0] (D[6:4]/0x40145)∗2P8TON5 (D7/0 x4014 5)
A/D converter PSAD[2:0] (D[2:0]/0x4014F)∗2PSONAD (D3/0x4014F)
∗1 to ∗4: See Table 2.2.
Table 2.2 Division Ratio
Bit setting 76543210
∗1θ/4096 θ/1024 θ/256 θ/64 θ/16 θ/4 θ/2 θ/1
∗2θ/256 θ/128 θ/64 θ/32 θ/16 θ/8 θ/4 θ/2
∗3θ/4096 θ/2048 θ/1024 θ/512 θ/256 θ/128 θ/64 θ/32
∗4θ/4096 θ/2048 θ/64 θ/32 θ/16 θ/8 θ/4 θ/2
(θ = Source clock selected by PSCDT0)
Current consumption can be reduced by turning off the clock output to the peripheral circuits that are unused
among those listed above.
Note: In the following cases, the prescaler o utput clock may contain a hazard:
•If, when a clock is output , its division ratio i s chan ged
•When the clock output is switched betw een on and off
•When the oscillation circuit is turned off or the CPU operating clock is switched over
Before perfor m ing these operations, make sure the 16-bit an d 8-bit programmable t imers and the
A/D converter are turned off.
Source Clock Output to 8-Bit Programmable Timer
In addition to the divided clock, the prescaler can output the source clock directly to the 8-bit programmable timer.
This fun ction can be selected for each 8-bit timer using P8TPCKx bit.
8-bit timer 0: P8TPCK0 (D0) / 8-bit timer clock select register (0x40146)
8-bit timer 1: P8TPCK1 (D1) / 8-bit timer clock select register (0x40146)
8-bit timer 2: P8TPCK2 (D2) / 8-bit timer clock select register (0x40146)
8-bit timer 3: P8TPCK3 (D3) / 8-bit timer clock select register (0x40146)
8-bit t imer 4: P8TPCK4 (D0) / 8-bit timer 4/5 cl ock select re gister (0x401 40)
8-bit t imer 5: P8TPCK5 (D1) / 8-bit timer 4/5 cl ock select re gister (0x401 40)
When P8TPCKx is set to "1", the prescaler input clock (θ/1) is selected for the 8-bit timer x operating clock.
The clock output is controlled by the P8TONx bit even if P8TPCKx is set to "1".
When P8TPCKx is "0", the divided clock that is selected by P8 TSx[ 2:0] will be output t o the 8-bit timer x.
At i nitial reset, P8TPCKx is set to "0" and P8TSx[2:0] becomes effective.
III PERIPHERAL BLOCK: PRESCALER
S1C33L03 FUNCTION PART EPSON B-III-2-3
A-1
B-III
PSC
I/O Memo ry of Prescale r
Table 2.3 shows t he control bits of the prescaler.
Table 2.3 Control Bits of Prescaler
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
P8TPCK5
P8TPCK4
D7–2
D1
D0
reserved
8-bit timer 5 clock selection
8-bit timer 4 clock selection
–
0
0
–
R/W
R/W
0 when being read.
θ: selected by
Prescaler clock select
register (0x40181)
0040140
(B) 1θ/1 0 Divided clk.
1θ/1 0 Divided clk.
8-bit timer 4/5
clock select
register
–
1 On 0 OffP8TON5
P8TS52
P8TS51
P8TS50
P8TON4
P8TS42
P8TS41
P8TS40
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 5 clock control
8-bit timer 5
clock division ratio selection
8-bit timer 4 clock control
8-bit timer 4
clock division ratio selection
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
θ: selected by
Prescaler clock select
register (0x40181)
8-bit timer 5 can
generate the clock for
the serial I/F Ch.3.
θ: selected by
Prescaler clock select
register (0x40181)
8-bit timer 4 can
generate the clock for
the serial I/F Ch.2.
0040145
(B) 1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
θ/256
θ/128
θ/64
θ/32
θ/16
θ/8
θ/4
θ/2
1 On 0 Off
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
θ/4096
θ/2048
θ/64
θ/32
θ/16
θ/8
θ/4
θ/2
8-bit timer 4/5
clock control
register
––
P8TPCK3
P8TPCK2
P8TPCK1
P8TPCK0
D7–4
D3
D2
D1
D0
reserved
8-bit timer 3 clock selection
8-bit timer 2 clock selection
8-bit timer 1 clock selection
8-bit timer 0 clock selection
–
0
0
0
0
–
R/W
R/W
R/W
R/W
0 when being read.
θ: selected by
Prescaler clock select
register (0x40181)
0040146
(B) 1θ/1 0 Divided clk.
1θ/1 0 Divided clk.
1θ/1 0 Divided clk.
1θ/1 0 Divided clk.
8-bit timer
clock select
register
––
P16TON0
P16TS02
P16TS01
P16TS00
D7–4
D3
D2
D1
D0
reserved
16-bit timer 0 clock control
16-bit timer 0
clock division ratio selection
–
0
0
0
0
–
R/W
R/W
0 when being read.
θ: selected by
Prescaler clock select
register (0x40181)
16-bit timer 0 can be
used as a watchdog
timer.
0040147
(B) 1 On 0 Off
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
P16TS0[2:0] Division ratio
θ/4096
θ/1024
θ/256
θ/64
θ/16
θ/4
θ/2
θ/1
16-bit timer 0
clock control
register
––
P16TON1
P16TS12
P16TS11
P16TS10
D7–4
D3
D2
D1
D0
reserved
16-bit timer 1 clock control
16-bit timer 1
clock division ratio selection
–
0
0
0
0
–
R/W
R/W
0 when being read.
θ: selected by
Prescaler clock select
register (0x40181)
0040148
(B) 1 On 0 Off
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
P16TS1[2:0] Division ratio
θ/4096
θ/1024
θ/256
θ/64
θ/16
θ/4
θ/2
θ/1
16-bit timer 1
clock control
register
––
P16TON2
P16TS22
P16TS21
P16TS20
D7–4
D3
D2
D1
D0
reserved
16-bit timer 2 clock control
16-bit timer 2
clock division ratio selection
–
0
0
0
0
–
R/W
R/W
0 when being read.
θ: selected by
Prescaler clock select
register (0x40181)
0040149
(B) 1 On 0 Off
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
P16TS2[2:0] Division ratio
θ/4096
θ/1024
θ/256
θ/64
θ/16
θ/4
θ/2
θ/1
16-bit timer 2
clock control
register
III PERIPHERAL BLOCK: PRESCALER
B-III-2-4 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
––
P16TON3
P16TS32
P16TS31
P16TS30
D7–4
D3
D2
D1
D0
reserved
16-bit timer 3 clock control
16-bit timer 3
clock division ratio selection
–
0
0
0
0
–
R/W
R/W
0 when being read.
θ: selected by
Prescaler clock select
register (0x40181)
004014A
(B) 1 On 0 Off
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
P16TS3[2:0] Division ratio
θ/4096
θ/1024
θ/256
θ/64
θ/16
θ/4
θ/2
θ/1
16-bit timer 3
clock control
register
––
P16TON4
P16TS42
P16TS41
P16TS40
D7–4
D3
D2
D1
D0
reserved
16-bit timer 4 clock control
16-bit timer 4
clock division ratio selection
–
0
0
0
0
–
R/W
R/W
0 when being read.
θ: selected by
Prescaler clock select
register (0x40181)
004014B
(B) 1 On 0 Off
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
P16TS4[2:0] Division ratio
θ/4096
θ/1024
θ/256
θ/64
θ/16
θ/4
θ/2
θ/1
16-bit timer 4
clock control
register
––
P16TON5
P16TS52
P16TS51
P16TS50
D7–4
D3
D2
D1
D0
reserved
16-bit timer 5 clock control
16-bit timer 5
clock division ratio selection
–
0
0
0
0
–
R/W
R/W
0 when being read.
θ: selected by
Prescaler clock select
register (0x40181)
004014C
(B) 1 On 0 Off
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
P16TS5[2:0] Division ratio
θ/4096
θ/1024
θ/256
θ/64
θ/16
θ/4
θ/2
θ/1
16-bit timer 5
clock control
register
1 On 0 OffP8TON1
P8TS12
P8TS11
P8TS10
P8TON0
P8TS02
P8TS01
P8TS00
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 1 clock control
8-bit timer 1
clock division ratio selection
8-bit timer 0 clock control
8-bit timer 0
clock division ratio selection
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
θ: selected by
Prescaler clock select
register (0x40181)
8-bit timer 1 can
generate the OSC3
oscillation-stabilize
waiting period.
θ: selected by
Prescaler clock select
register (0x40181)
8-bit timer 0 can
generate the DRAM
refresh clock.
004014D
(B) 1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
P8TS1[2:0] Division ratio
θ/4096
θ/2048
θ/1024
θ/512
θ/256
θ/128
θ/64
θ/32
1 On 0 Off
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
P8TS0[2:0] Division ratio
θ/256
θ/128
θ/64
θ/32
θ/16
θ/8
θ/4
θ/2
8-bit timer 0/1
clock control
register
III PERIPHERAL BLOCK: PRESCALER
S1C33L03 FUNCTION PART EPSON B-III-2-5
A-1
B-III
PSC
NameAddressRegister name Bit Function Setting Init. R/W Remarks
1 On 0 OffP8TON3
P8TS32
P8TS31
P8TS30
P8TON2
P8TS22
P8TS21
P8TS20
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 3 clock control
8-bit timer 3
clock division ratio selection
8-bit timer 2 clock control
8-bit timer 2
clock division ratio selection
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
θ: selected by
Prescaler clock select
register (0x40181)
8-bit timer 3 can
generate the clock for
the serial I/F Ch.1.
θ: selected by
Prescaler clock select
register (0x40181)
8-bit timer 2 can
generate the clock for
the serial I/F Ch.0.
004014E
(B) 1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
P8TS3[2:0] Division ratio
θ/256
θ/128
θ/64
θ/32
θ/16
θ/8
θ/4
θ/2
1 On 0 Off
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
P8TS2[2:0] Division ratio
θ/4096
θ/2048
θ/64
θ/32
θ/16
θ/8
θ/4
θ/2
8-bit timer 2/3
clock control
register
–
PSONAD
PSAD2
PSAD1
PSAD0
D7–4
D3
D2
D1
D0
reserved
A/D converter clock control
A/D converter clock division ratio
selection
–
0
0
0
0
–
R/W
R/W
0 when being read.
θ: selected by
Prescaler clock select
register (0x40181)
004014F
(B)
A/D clock
control register
1 On 0 Off
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
P8TS0[2:0] Division ratio
θ/256
θ/128
θ/64
θ/32
θ/16
θ/8
θ/4
θ/2
–
CLKDT1
CLKDT0
PSCON
–
CLKCHG
SOSC3
SOSC1
D7
D6
D5
D4–3
D2
D1
D0
System clock division ratio
selection
Prescaler On/Off control
reserved
CPU operating clock switch
High-speed (OSC3) oscillation On/Off
Low-speed (OSC1) oscillation On/Off
1 On 0 Off
1 OSC3 0 OSC1
1 On 0 Off
1 On 0 Off
0
0
1
0
1
1
1
R/W
R/W
–
R/W
R/W
R/W
Writing 1 not allowed.
0040180
(B) 1
1
0
0
1
0
1
0
CLKDT[1:0] Division ratio
1/8
1/4
1/2
1/1
–
Power control
register
–
PSCDT0
D7–1
D0 reserved
Prescaler clock selection 0
0–
R/W
0040181
(B) –Prescaler clock
select register 1 OSC1 0 OSC3/PLL
Writing 10010110 (0x96)
removes the write protection of
the power control register
(0x40180) and the clock option
register (0x40190).
Writing another value set the
write protection.
CLGP7
CLGP6
CLGP5
CLGP4
CLGP3
CLGP2
CLGP1
CLGP0
D7
D6
D5
D4
D3
D2
D1
D0
Power control register protect flag 0
0
0
0
0
0
0
0
R/W004019E
(B)
Power control
protect register
PSCON: Prescaler on/off control (D5) / Power control register (0x40180)
Turns the prescaler on or off.
Write "1": On
Write "0": Off
Read: Valid
The sou rce clock is input to the prescaler by writing "1" to PSCON, thereby starting a dividing operation.
The prescaler is turned off by writing "0". If the peripheral circuits do not need to be operated, write "0" to this bit
to reduce current consumption. Since PSCON is protected against writing the same as SOSC1, SOSC3, CLKCHG
and CLKDT[1:0], CLGP[7:0] must be set to "0b10010110" before PSCON can be changed.
In addition, writing "0" (Off) to PSCON stops supplying the source clock to the prescaler and stops the peripheral
circuits that use the same clock (e.g., 16-bit programmable timers, 8-bit programmable timers, A/D converter,
serial interface, and ports). Therefore, do not turn off the prescaler when these peripheral circuits are used.
At i nitial reset, PSCON is set to "1" (On).
III PERIPHERAL BLOCK: PRESCALER
B-III-2-6 EPSON S1C33L03 FUNCTION PART
CLGP7–CLGP0: Power-control register protection flag ([D[7:0]) / Power control protection register (0x4019E)
These bits remove the protection against writi ng to add resses 0x4018 0 and 0x4019 0.
Write "0b100 10 11 0" : Writ e p rotecti o n rem ov ed
Write othe r than the above: No operation (write-protected)
Read: Valid
Before writing to address 0x40 180 or 0x40 190, set CLGP[ 7:0] to "0b10010110" to remove the protection against
writing to that address. This clearing of write protection is effective for only one writing, so the bits are cleared to
"0b00000000" by one writing. Therefore, CLGP[7:0] must be set each time the protected address is written to.
At i nitial reset, CLGP is set to "0b00000000" (write-protected).
PSCDT0: Pre sc aler clock selection (D0) / Pres caler clock select register (0 x40181)
Select the source clock for the prescaler.
Write "1": O SC1 clock
Write "0": O SC3 clock/P LL o ut p ut cl oc k
Read: Valid
When "1" is written to PSCDT0, the OSC1 clock (typ. 32 kHz) is selected.
When "0" is written, the OSC3 clock (when the PLL is not used) or the PLL ou tput clock (when the PLL is use d) is
selected.
For the prescaler clock, the clock source same as the CPU operating clock must be selected.
At i nitial reset, PSCDT0 is set to "0" (OSC3 clock/PLL output clock).
P16TS0[2:0]:16-bit timer 0 clock division ratio (D[2:0]) / 16-bit timer 0 clock control register (0x40147)
P16TS1[2:0]:16-bit timer 1 clock division ratio (D[2:0]) / 16-bit timer 1 clock control register (0x40148)
P16TS2[2:0]:16-bit timer 2 clock division ratio (D[2:0]) / 16-bit timer 2 clock control register (0x40149)
P16TS3[2:0]:16-bit timer 3 clock division ratio (D[2:0]) / 16-bit timer 3 clock control register (0x4014A)
P16TS4[2:0]:16-bit timer 4 clock division ratio (D[2:0]) / 16-bit timer 4 clock control register (0x4014B)
P16TS5[2:0]:16-bit timer 5 clock division ratio (D[2:0]) / 16-bit timer 5 clock control register (0x4014C)
P8TS0[2:0]:8-bit time r 0 clock d ivi sio n ra tio (D[2:0 ]) / 8 -bi t ti mer 0 /1 c loc k con tro l register ( 0 x4014D)
P8TS1[2:0]:8-bit time r 1 clock d ivi sio n ra tio (D[6:4 ]) / 8 -bi t ti mer 0 /1 c loc k con tro l register ( 0 x4014D)
P8TS2[2:0]:8-bit time r 2 clock d ivi sio n ra tio (D[2:0 ]) / 8 -bi t ti mer 2 /3 c loc k con tro l register (0x4014E)
P8TS3[2:0]:8-bit time r 3 clock d ivi sio n ra tio (D[6:4 ]) / 8 -bi t ti mer 2 /3 c loc k con tro l register ( 0 x4014E)
P8TS4[2:0]:8-bit time r 4 clock d ivi sio n ra tio (D[2:0 ]) / 8 -bi t ti mer 4 /5 c loc k con tro l register ( 0 x40145)
P8TS5[2:0]:8-bit time r 5 clock d ivi sio n ra tio (D[6:4 ]) / 8 -bi t ti mer 4 /5 c loc k con tro l register ( 0 x40145)
PSAD[2:0]:A/D converte r c loc k d ivi sio n ra tio (D[2:0 ]) / A /D clock c on tro l register ( 0 x4014F)
Select a clock for each peripheral circuit.
The des ired division ratio c an be s elected from among the eight r atios shown on the I/O map. No te that the divisi on
ratio differs for each peripheral circuit.
These bits can also be read out.
At i nitial reset, all of these bits are set to "0b000" (highest frequency available).
III PERIPHERAL BLOCK: PRESCALER
S1C33L03 FUNCTION PART EPSON B-III-2-7
A-1
B-III
PSC
P16TON0:16-bit timer 0 clock control (D3) / 16-bit t imer 0 clock control reg ister (0x40147)
P16TON1:16-bit timer 1 clock control (D3) / 16-bit t imer 1 clock control reg ister (0x40148)
P16TON2:16-bit timer 2 clock control (D3) / 16 -bit timer 2 clock control regist er (0x40149)
P16TON3:16-bit timer 3 clock control (D3) / 16-bit t imer 3 clock control reg ister (0x4014A)
P16TON4:16-bit timer 4 clock control (D3) / 16-bit t imer 4 clock control reg ister (0x4014B)
P16TON5:16-bit timer 5 clock control ( D 3) / 16-bit timer 5 clock control register (0x401 4C)
P8TON0:8-bit timer 0 clock control (D3) / 8-bit timer 0 /1 c loc k cont ro l register (0x4014D)
P8TON1:8-bit timer 1 clock control (D7) / 8-bit timer 0 /1 c loc k cont ro l register (0x4014D)
P8TON2:8-bit timer 2 clock control (D3) / 8-bit timer 2 /3 c loc k cont ro l register (0x4014E)
P8TON3:8-bit timer 3 clock control (D7) / 8-bit timer 2 /3 c loc k cont ro l register (0x4014E)
P8TON4:8-bit timer 4 clock control (D3) / 8-bit timer 4 /5 c loc k cont ro l register (0x40145)
P8TON5:8-bit timer 5 clock control (D7) / 8-bit timer 4 /5 c loc k cont ro l register (0x40145)
PSONAD:A/D converter clock control (D3) / A/D clock control register (0x4014F)
Control the clock supply to each peripheral circuit.
Write "1": On
Write "0": Off
Read: Valid
The clock selected using the division ratio setup bits is output to the corresponding peripheral circuit by writing "1"
to these bits.
The clock is not output by writing "0". If the peripheral circuits do not need to be operated, write "0" to these bits.
This helps to reduce current consumption.
At i nitial reset, all of these bits are set to "0" (Off).
P8TPCK0: 8-bi t timer 0 cloc k sele ct io n (D0) / 8-bi t timer c loc k s elect regi st er (0 x4 0 146)
P8TPCK1: 8-bit timer 1 clock selection (D1) / 8-bit timer clock sele ct register ( 0 x40146)
P8TPCK2: 8-bi t timer 2 cloc k sele ct io n (D2) / 8-bi t timer c loc k s elect regi st er (0 x4 0 146)
P8TPCK3: 8-bi t timer 3 cloc k sele ct io n (D3) / 8-bi t timer c loc k s elect regi st er (0 x4 0 146)
P8TPCK4: 8-bit timer 4 clock selection (D0) / 8-bit ti me r 4 /5 cl oc k s el e ct regist er (0 x4 0 140)
P8TPCK5: 8-bit timer 5 clock selection (D1) / 8-bit timer 4 /5 c loc k s el e ct register (0x4 014 0)
Select the operating clock for the 8-bit programmable timer.
Write "1": Prescaler input clock (θ/1)
Write "0": Divided clock
Read: Valid
When "1" is written to P8TPCKx, the prescaler input clock (θ/1) is selected for the 8-bit timer x operating clock.
The clock output is controlled by the P8TONx bit even if P8TPCKx is set to "1".
When "0" is written, the divided clock that is selected by P8TSx[2:0] will be output to the 8-bit timer x.
At i nitial reset, P8TPCKx is set to "0" (divided clock).
III PERIPHERAL BLOCK: PRESCALER
B-III-2-8 EPSON S1C33L03 FUNCTION PART
Pr ogramming Notes
(1) For the prescaler clock, the clock source same as the CPU operating clock must be selected.
(2) In the following cases, the prescaler output clock may contain a hazard:
• If, during outputting of a clock, its division ratio is changed
• When the clock output is switched between on and off
• When the oscillation circuit is turned off or the CPU operating clock is switched over
Before performing these operations, make sure the 16-bit and 8-bit programmable timers and the A/D
converter are turned off.
(3) When the 16-bit and 8-bit programmable timers and the A/D converter do not need to be operated, turn off
the clock supply to those peripheral circuits. This helps to reduce current consumption.
(4) Be aware that some peripheral circuits stops operating when the prescaler is turned off (PSCON (D5) / Power
control register (0x40180) = "0") as well as the peripheral circuits that use the prescaler output clock.
The prescaler status affects the peripheral circuits shown below.
(A) Peripheral circuits that use the clock generated by the prescaler
• 16-bit programmable timers (watchdog timer)
• 8-bit programmable timers (DRAM refresh, serial interface)
• A/D converter
(B) Peripheral circuits that use the clock supplied to the prescaler (the source clock for prescaler)
• 16-bit programmable timers (watchdog timer)
• 8-bit programmable timers (DRAM refresh)
• A/D converter
• Serial interface
• Input/output ports
If none of all circuits of the above (A) and (B) need to be used, turn off the prescaler (PSCON = "0"). If a
circuit of the above (A) or (B) need to be used, do not turn off the prescaler. When the prescaler is turned off,
the clock supply to the circuits of the above (B) stops. When some these circuits of the above (A) need to be
used, turn off all ot her unnecessary circuits and stop the clock supply from the prescaler to those circuits.
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS
S1C33L03 FUNCTION PART EPSON B-III-3-1
A-1
B-III
8TM
III-3 8-BIT PROGRAMMABLE TIMERS
Configuration of 8-Bit Programmable Timer
The Peripheral Block contains six channels of 8-bit programmable timers (timers 0 to 5).
Figure 3.1 sho w s the structure of the 8-b it programmable timer.
Data bus
8-bit reload data register (RLDx)
8-bit down counter
Control registers
Control circuit Data buffer (PTDx)
Underflow
Reload
Clock output
Underflow signal output
Underflow
interrupt Interrupt
controller
Prescaler
Clock
generator
Figur e 3.1 Structure of 8-Bit Programmable Timer
Each timer consists of an 8-bit presentable counter and can output a clock generated by the counter's underflow
signal to the internal peripheral circuits or external devices. The output clock cycle can be selected from a wide
range of cycles by setting the preset data that can be set in the software and the input clock in the prescaler.
Output Pins of 8-Bit Programmable Timers
The unde rflow s ignals of 8-bit programmable t imer s 0 to 3 can be output to external devices.
Table 3.1 shows t he pins that are used to output the underflow signals of the 8-bit programmable timers to external
devices. Table 3.1 Output Pins of 8-Bit Programmable Timers
Pin name I/O Function Function select bit
P10/EXCL0/
T8UF0 I/O I/O port / 16-bit timer 0 event counter
input / 8-bit timer 0 output / DST0 output CFP10(D0)/P1 functio n s elect reg ister (0x402D4)
CFEX1(D1)/Port function extension register (0x402DF)
P11/EXCL1/
T8UF1 I/O I/O port / 16-bit timer 1 event counter
input / 8-bit timer 1 output / DST1 output CFP11(D1/P1 function select register (0x402D4)
CFEX1(D1)/Port function extension register (0x402DF)
P12/EXCL2/
T8UF2 I/O I/O port / 16-bit timer 2 event counter
input / 8-bit timer 2 output / DST2 output CFP12(D2/P1 function select register (0x402D4)
CFEX0(D0)/Port function extension register (0x402DF)
P13/EXCL3/
T8UF3 I/O I/O port / 16-bit timer 3 event counter
input / 8-bit timer 3 output / DPCO output CFP13(D3/P1 function select register (0x402D4)
CFEX1(D1)/Port function extension register (0x402DF)
T8UFx (output pin of the 8-bit programm able timer)
This pin outputs a clock divided in each 8-bit programmable timer. The pulse width is equal to that of input
clock of the 8-bit programmable timer (prescaler output). Therefore, the pulse width varies according to the
prescaler setting.
How to set the output pins of the 8-bit programmable timer
All pins used by the 8-bit programmable timers are shared with I/O ports, event counter inputs of the 16-bit
programmable timers and debug signal outputs. At cold start, all these pins are set for the debug signal
outpu ts (function s elect bit CFP1[3:0] = "0", port extended function bit CFEX[1:0] = "1"). When using the
clock output function of the 8-bit programmable timer, write "0" to the port extended function bit CFEXx and
wri te "1" to the function select bit CFP1x for the corresponding pin.
Then, after setting the above, write "1" to the I/O port's I/O control bit IOC1x (D[3:0]) / P1 I/O control
register (0x402D6) to set to output mode. In input mode, the pin functions as the 16-bit programmable timer's
event counter input and cannot be used to output a clock of the 8-bit programmable timer. At cold start, the
register is set to input mode. At hot start, the register retains its status from prior to the reset.
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS
B-III-3-2 EPSON S1C33L03 FUNCTION PART
Uses of 8-Bit Programmable Timers
The down-counter of the 8-bit programmable timer cyclically outputs an underflow signal according to the preset
data that is set in the software. This underflow signal is used to generate an interrupt request to the CPU or to
control the internal peripheral circuits. In addition, this signal can be output to external devices.
Furthermore, each 8-bit programmable timer generates a clock from the underflow signal by dividing it by 2, and
the resulting clock is output to a specific internal peripheral circuit.
CPU interrupt request/IDMA invocation request
Each timer's un derflow condition can be used as an interrupt factor to output an interrupt request to the CPU.
There fore, an interrupt can be generated at an interval that is set in the software.
This interrupt factor also can be used to invoke IDMA or HSDMA.
Clock o u tpu t to ext ernal devices
The unde rflow signal can be outpu t from the chip to the outside. This output can be used to control external
devices. The output pins of each timer are descri bed in the preceding section.
Control of and clock supply to internal peripheral circuits
The following describes the functions controlled by the underflow signal from the 8-bit programmable timer
and the internal peripheral circuits that use the timer's output clock.
8-bit pr ogram m able timer 0
• DRAM refresh
When the BCU has a DRAM directly connected to its external bus, the underflow signal from timer 0
can be used as a DRAM refresh request signal. This enables the intervals of the refresh cycle to be
programmed.
To use this function, write "1" to the BCU's control bit RPC2 (D9) / Bus control register (0x4812E) to
enable the DRAM refresh.
• A/D conver sion start trigger
The A/ D conve rt er enables a trigger for starting the A/D conversion to be selected from among four
available types. One of these is the underflow signal of the 8-bit programmable timer 0. This makes it
possible to perform the A/D conversion at programmable intervals.
To use this function, write "10" to the A/D converter control bit TS[1:0] (D[4:3]) / A/D trigger register
(0x40242) to select the 8-bit programmable timer 0 as the trigger.
8-bit pr ogram m able timer 1
• Oscillation stabilization wait time of the high-speed (OSC3) oscillation circuit
When SLEEP mode is cle ared by an external interrupt, the high-speed (OSC3) oscillation circuit starts
oscillating. To prevent the CPU from being operated erratically by an unstable clock before the
oscillation stabilizes, the C33 Core Block enables setting of the waiting time before the CPU starts
operating after SLEEP is cleared. Use the 8-bit programmable timer 1 to generate this waiting time. If the
8-bit program mable timer 1 is set so that the timer is actuated when the high-speed (OSC3) oscillation
circuit starts oscillating the timer and, after the oscillation stabilization time elapses, an underflow signal
is generated, then the CPU can be started up by that underfl ow s ignal.
To use this function, write "0" to the oscillation circuit control bit 8T1ON (D2) / Clock option register
(0x40190) to enable the oscillation stabilization waiting function.
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS
S1C33L03 FUNCTION PART EPSON B-III-3-3
A-1
B-III
8TM
8-bit pr ogram m able timer 2
• Clock supply to the Ch.0 serial interface
When using the Ch.0 serial interface in the clock-synchronized master mode or the internal clock-based
asynchronous mode, the output clock derived from the underflow signal of the 8-bit programmable timer
2 by div iding it by 2 is supplied to the serial interface as its operating clock. This enables the transfer rate
of the serial interface to be programmed.
To use this function, write "0" to the serial interface control bit SSCK0 (D2) / Serial I/F Ch.0 control
register (0x401E3) to select the internal clock.
8-bit pr ogram m able timer 3
• Clock supply to the Ch.1 serial interface
When using the Ch.1 serial interface in the clock-synchronized master mode or the internal clock-based
asynchronous mode, the output clock derived from the underflow signal of the 8-bit programmable timer
3 by div iding it by 2 is supplied to the serial interface as its operating clock. This enables the transfer rate
of the serial interface to be programmed.
To use this function, write "0" to the serial interface control bit SSCK1 (D2) / Serial I/F Ch.1 control
register (0x401E8) to select the internal clock.
8-bit pr ogram m able timer 4
• Clock supply to the Ch.2 serial interface
When using the Ch.2 serial interface in the clock-synchronized master mode or the internal clock-based
asynchronous mode, the output clock derived from the underflow signal of the 8-bit programmable timer
4 by div iding it by 2 is supplied to the serial interface as its operating clock. This enables the transfer rate
of the serial interface to be programmed.
To use this function, write "0" to the serial interface control bit SSCK2 (D2) / Serial I/F Ch.2 control
register (0x401F3) to select the internal clock.
8-bit pr ogram m able timer 5
• Clock supply to the Ch.3 serial interface
When using the Ch.3 serial interface in the clock-synchronized master mode or the internal clock-based
asynchronous mode, the output clock derived from the underflow signal of the 8-bit programmable timer
5 by div iding it by 2 is supplied to the serial interface as its operating clock. This enables the transfer rate
of the serial interface to be programmed.
To use this function, write "0" to the serial interface control bit SSCK3 (D2) / Serial I/F Ch.3 control
register (0x401F8) to select the internal clock.
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS
B-III-3-4 EPSON S1C33L03 FUNCTION PART
Control and Operation of 8-Bit Programmable Timer
With the 8-b it programmable timer, the following settings must first be made before it starts counting:
1. Setting the output pin (only when necessary)
2. Setting the input clock
3. Setti ng the preset data (initial counter value)
4. Setting the interrupt/IDMA/HSDMA
Setting of an output pin is ne cessary only w hen the output clock of the 8-bit programmable timer is supplied to
external devices. For details on how to set the pin, refer to "Output Pins of 8-Bit Programmable Timers".
For details on how to s et interrupts and DMA, refer to "8-Bit Programmable Timer Interrupts and DMA".
Note: The 8-bit programmable t imers 0 through 3 all op erate in the same way du ring counti ng, and the
structure of their control registers is also the same. The contr ol bit names are assigned the
num erals "0" through "3" to denote the timer numbers. Since all these timers have common
func tio n s, ti mer n um b er s here are represented it is by "x" unless ne cess ary to specify a tim er
number.
Setting the input clock
The 8-b it programmable timer is operated by the prescaler's output clock. The prescaler's division ratio can be
selected for each timer.
Division ratio select bit Clock control bit Register
8-bit t imer 0: P8TS0[2:0] (D[2:0]) P8TON0 ( D3) 8-bit timer 0/1 clock control register (0x4014D)
8-bit t imer 1: P8TS1[ 2:0] (D[6:4]) P8TON1 (D7) 8-bit timer 0/1 clock control register (0x4014D)
8-bit t imer 2: P8TS2[ 2:0] (D[2:0]) P8TON2 (D3) 8-bit timer 2/3 clock control register (0x4014E)
8-bit t imer 3: P8TS3[ 2:0] (D[6:4]) P8TON3 (D7) 8-bit timer 2/3 clock control register (0x4014E)
8-bit t imer 4: P8TS4[ 2:0] (D[2:0]) P8TON4 (D3) 8-bit timer 4/5 clock control register (0x40145)
8-bit t imer 5: P8TS5[ 2:0] (D[6:4]) P8TON5 (D7) 8-bit timer 4/5 clock control register (0x40145)
Note that the division ratios differ for each timer (see Table 3.2).
Furthermore, the prescaler input clock can be directly supplied to the 8-bit timer by writing "1" to the
P8TPCKx bit in the 8-bit timer clock se lect re gi st e r (0x4 01 46).
Timer 0 clock s election: P8TP CK 0 (D0) / 8-bit timer clock select register (0x40146)
Timer 1 c lock selec tion: P8TPCK1 (D1) / 8-bit timer clock select register (0x40146)
Timer 2 clock s election: P8TP CK 2 (D2) / 8-bit timer clock select register (0x40146)
Timer 3 clock s election: P8TP CK 3 (D3) / 8-bit timer clock select register (0x40146)
Timer 4 c lock selec tion: P8TPCK4 (D0) / 8-bit timer clock select register (0x40140)
Timer 5 clock s election: P8TP CK 5 (D1) / 8-bit timer clock select register (0x40140)
When using the divided clock selected by P8TSx, set P8TPCKx to "0".
Table 3.2 Input Clock Selection
Timer P8TSx = 7 P8TSx = 6 P8TSx = 5 P8TSx = 4 P8TSx = 3 P8TSx = 2 P8TSx = 1 P8TSx = 0 P8TPCK = 1
Timer 0 fPSCIN/256 fPSCIN/128 fPSCIN/64 fPSCIN/32 fPSCIN/16 fPSCIN/8 fPSCIN/4 fPSCIN/2 fPSCIN/1
Timer 1 fPSCIN/4096 fPSCIN/2048 fPSCIN/1024 fPSCIN/512 fPSCIN/256 fPSCIN/128 fPSCIN/64 fPSCIN/32 fPSCIN/1
Timer 2 fPSCIN/4096 fPSCIN/2048 fPSCIN/64 fPSCIN/32 fPSCIN/16 fPSCIN/8 fPSCIN/4 fPSCIN/2 fPSCIN/1
Timer 3 fPSCIN/256 fPSCIN/128 fPSCIN/64 fPSCIN/32 fPSCIN/16 fPSCIN/8 fPSCIN/4 fPSCIN/2 fPSCIN/1
Timer 4 fPSCIN/4096 fPSCIN/2048 fPSCIN/64 fPSCIN/32 fPSCIN/16 fPSCIN/8 fPSCIN/4 fPSCIN/2 fPSCIN/1
Timer 5 fPSCIN/256 fPSCIN/128 fPSCIN/64 fPSCIN/32 fPSCIN/16 fPSCIN/8 fPSCIN/4 fPSCIN/2 fPSCIN/1
fPSCIN: Prescaler input clock frequency
The selected c lock is output from the prescaler to the 8-bit programmable timer by writing "1" to P8TONx.
Notes:•The 8-bit programmable timer operates only when the prescaler is op erati ng. (Refer t o
"Prescaler".)
•Do not use a clock that is faster than the CPU op erati ng clock as the 8-bit program m able timer .
•When setti ng an inpu t clock, make sure the 8-bit programmable timer is turned off.
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS
S1C33L03 FUNCTION PART EPSON B-III-3-5
A-1
B-III
8TM
Setting preset data (initial counter value)
Each timer has an 8-bit down-c ounter and a reload data register. The reload data register RLDx is used to set
the initial value of the down-counter of each timer.
Timer 0 reload data: RLD0[7:0] (D[7:0]) / 8-bit timer 0 reload data register (0x40161)
Timer 1 reload data: RLD1[7:0] (D[7:0]) / 8-bit timer 1 reload data register (0x40165)
Timer 2 reload data: RLD2[7:0] (D[7:0]) / 8-bit timer 2 reload data register (0x40169)
Timer 3 reload data: RLD3[7:0] (D[7:0]) / 8-bit timer 3 reload data register (0x4016D)
Timer 4 reload data: RLD4[7:0] (D[7:0]) / 8-bit timer 4 reload data register (0x40175)
Timer 5 reload data: RLD5[7:0] (D[7:0]) / 8-bit timer 5 reload data register (0x40179)
The reload data registers can be read and written. At initial reset, the reload data registers are not initialized.
The data written to this register is preset in the down-counter, and the counter starts counting down from the
preset valu e.
Data is thus preset in the down-counter in the following two cases:
1. When it is preset in the software
Presetting in the software is performed using the preset control bit PSETx. When this bit is set to "1", the
content of the reload data register is loaded into the down-counter at that point.
Timer 0 preset: PSET0 (D1) / 8-bit t imer 0 control r egister (0x40160)
Timer 1 preset: PSET1 (D1) / 8-bit t imer 1 control r egister (0x40164)
Timer 2 preset: PSET2 (D1) / 8-bit t imer 2 control r egister (0x40168)
Timer 3 preset: PSET3 (D1) / 8-bit t imer 3 control r egister (0x4016C)
Timer 4 preset: PSET4 (D1) / 8-bit tim er 4 control register (0x40174)
Timer 5 preset: PSET5 (D1) / 8-bit t imer 5 control r egister (0x40178)
2. When the down-counter un derflown duri ng count ing
Since the reload data is preset in the down -cou nter upon unde rflow, its underflow cycle is determined by the
value that is set in the reload data register. This underflow signal controls each function described in the
preceding section.
Before star ting the 8-bit program m able timer, set the initial value in the reload data register and use the
PSETx bi t to preset the data in the down-counter.
The unde rflow cycle is determined by the prescaler setting and the reload data. The relationship between
these two parameters is expressed by the following equation:
RLDx + 1
Under flow cycle = —————— [sec.]
fPSCIN × pdr
fPSCIN:Prescaler input clock frequency [Hz]
pdr: Pr escaler division ratio set by P8TSx
RL Dx: Set value of the RLDx r egister ( 0 to 255)
Timer RUN/STOP control
Each timer has a PTRUNx bit to control RUN/STOP.
Timer 0 RUN/ STOP control: PTRUN0 (D0) / 8-bit timer 0 control register (0x40160)
Timer 1 RUN/ STOP control: PTRUN1 (D0) / 8-bit timer 1 control register (0x40164)
Timer 2 RUN/ STOP control: PTRUN2 (D0) / 8-bit timer 2 control register (0x40168)
Timer 3 RUN/ STOP control: PTRUN3 (D0) / 8-bit timer 3 control register (0x4016C)
Timer 4 RUN/ STOP control: PTRUN4 (D0) / 8-bit timer 4 control register (0x40174)
Timer 5 RUN/ STOP control: PTRUN5 (D0) / 8-bit timer 5 control register (0x40178)
The tim er is initiated to start counting down by writing "1" to PTRUNx. Writing "0" to PTRUNx disables the
clock input and causes the timer to stop counting.
This RUN/ STOP control does not affect the counter data. Even when the timer has stopped counting, the
counter retains its count so that it can start counting again from that point.
When the terminal count is reached and the counter underflows, the initial value is reloaded from the reload
data register into the counter.
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS
B-III-3-6 EPSON S1C33L03 FUNCTION PART
When both the timer RUN/STOP control bit (PTRUNx) and the timer preset bit (PSETx) are set to "1" at the
same time, the timer starts counting after presetting the reload register value into the counter.
PTRUNx
PSETx
RLDx
Input clock
PTDx7
PTDx6
PTDx5
PTDx4
PTDx3
PTDx2
PTDx1
PTDx0
Preset
Timer
initial setup Reload and
interrupt
0xA60x10 0xF3
Figur e 3.2 Basic Operation Timing of Counter
Reading out counter data
The cou nter data is read out via a PTDx data buffer. The counter data can be read out at any time.
Tim er 0 data: PTD0 [7:0] (D[7:0]) / 8-bit timer 0 counter data register (0x40162)
Tim er 1 data: PTD1 [7:0] (D[7:0]) / 8-bit timer 1 counter data register (0x40166)
Tim er 2 data: PTD2 [7:0] (D[7:0]) / 8-bit timer 2 counter data register (0x4016A)
Tim er 3 data: PTD3 [7:0] (D[7:0]) / 8-bit timer 3 counter data register (0x4016E)
Tim er 4 data: PTD4 [7:0] (D[7:0]) / 8-bit timer 4 counter data register (0x40176)
Tim er 5 data: PTD5 [7:0] (D[7:0]) / 8-bit timer 5 counter data register (0x4017A)
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS
S1C33L03 FUNCTION PART EPSON B-III-3-7
A-1
B-III
8TM
Control of Clock Output
When output ting an underflow signal of the 8-bit programmable timer to external devices, or when supplying a
clock generated by the underflow signal to the serial interface, it is necessary to control the clock output of the
timer.
Timer 0 clock output control: PTOUT0 (D2) / 8-bit timer 0 control register (0x40160)
Timer 1 clock output control: PTOUT1 (D2) / 8-bit timer 1 control register (0x40164)
Timer 2 clock output control: PTOUT2 (D2) / 8-bit timer 2 control register (0x40168)
Timer 3 clock output control: PTOUT3 (D2) / 8-bit timer 3 control register (0x4016C)
To output the underflow signal/clo ck, wr ite "1" to PTOUTx. If an output pin has been set, the underflow signal is
output from that pin.
The same applies when timer 2 or 3 has been set as the clock source of the serial interface. A clock generated from
the underflow signal by dividing it by 2 is output to the serial interface through this control. The clock output is
turned off by writing "0" to PTOUTx, and the external output is fixed at "0" and the internal clock output is fixed at
"1".
Figure 3.3 shows the waveforms of the output signals.
Underflow signal
Underflow signal/2
PTOUTx
External output
T8UFx pin
Clock output
Figur e 3.3 8-Bit Programmable Timer Output Waveform
The unde rflow signal's pulse width (duration of t he high period) is equal to that of the timer's input clock
(prescaler's output).
8-bi t timer external output (P10–P 13 ports)
1) Aft er an initial reset (cold start), the ports (P10–P13) are set to debug signal putput ports.
2) The port ( P10– P13) outputs "0" when it is set to the 8-bit timer output (timer output is off status).
3) The t imer output is left as "0" when the timer output is turned on after setting the input clock and timer
initial v alu e.
4) When an un derflow occ urs after starting the timer, the port outputs a pulse with the same width as the 8-bit
timer input clock pulse (prescaler's output).
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS
B-III-3-8 EPSON S1C33L03 FUNCTION PART
8-Bit Programmable Timer Int errupts and DMA
The 8-b it programmable timer has a function to generate an interrupt based on the underflow state of the timer 0 to
3.
The timing at wh ich an interrupt is generated is shown in Figure 3.2 in the preceding section.
Control registers of the interrupt controller
Table 3.3 shows t he interrupt controller's control register provided for each timer.
Table 3.3 Control Registers of Interrupt Controller
Timer Interrupt factor flag Interrupt enable register Interrupt priority register
Timer 0 F8TU0(D0/0x40285) E8TU0(D0/0x40275) P8TM[2:0](D[2:0]/0x40269)
Timer 1 F8TU1(D1/0x40285) E8TU1(D1/0x40275)
Timer 2 F8TU2(D2/0x40285) E8TU2(D2/0x40275)
Timer 3 F8TU3(D3/0x40285) E8TU3(D3/0x40275)
When the timer underflows, the corresponding interrupt factor flag is set to "1". If the interrupt enable register
bit corresponding to that interrupt factor flag has been set to "1", an interrupt request is generated.
An interrupt caused by a timer can be disabled by leaving the interrupt enable register bit for that timer set to
"0". The interrupt factor flag is set to "1" whenever the timer underflows, regardless of how the interrupt
enable register is set (even when it is set to "0").
The interrupt priority register sets an interrupt priority level (0 to 7) for the four timers as one interrupt source.
Within 8-bit programmable timers, timer 0 has the highest priority and timer 3 the lowest. An interrupt
request to the CPU is accepted on the condition that no other interrupt request of a higher priority has been
generated.
It is only when the PSR's IE bit = "1" (interrupts enabled) and the set value of the IL is smaller than the timer
interrupt level set by the interrupt priority register, that a timer interrupt request is actually accepted by the
CPU.
For details on these interrupt control registers and device operation when an interrupt has occurred, refer to
"ITC (Interrupt Controller)".
Int e ll ig e nt D M A
The underflow interrupt factor of the timer 0 to 3 can invoke intelligent DMA (IDMA). This enables
memory-to-memory DMA transfers to be performed cycl ically.
The following shows the IDMA channel numbers set to each timer:
IDMA channel
Timer 0: 0x13
Timer 1: 0x14
Timer 2: 0x15
Timer 3: 0x16
For IDMA to be invoked, the IDMA request and IDMA enable bits shown in Table 3.4 must be set to "1" in
advance. Transfer conditions, etc. must also be set on the IDMA side in advance.
Table 3.4 Control Bits fo r IDMA Transfe r
Timer IDMA request bi tIDMA enable bit
Timer 0 R8TU0(D2/0x40292) DE8TU0(D2/0x40296)
Timer 1 R8TU1(D3/0x40292) DE8TU1(D3/0x40296)
Timer 2 R8TU2(D4/0x40292) DE8TU2(D4/0x40296)
Timer 3 R8TU3(D5/0x40292) DE8TU3(D5/0x40296)
If the IDMA request and enable bits are set to "1", IDMA is invoked through generation of an interrupt factor.
No interrupt request is generated at that point. An interrupt request is generated after the DMA transfer is
completed. The registers can also be set so as not to generate an interrupt, with only a DMA transfer
performed.
For details on IDMA transfers and interrupt control upon completion of IDMA transfer, refer to "IDMA
(Intelligent DMA)".
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS
S1C33L03 FUNCTION PART EPSON B-III-3-9
A-1
B-III
8TM
Hig h -speed DM A
The unde rflow interrupt factor of the timer 0 to 3 can also invoke high-speed DMA (HSDMA).
The f ol lowing shows the HSDMA channel number and trigger set-up bit corresponding to the timer 0 to 3:
Table 3.5 HSDMA Trigger Set-up Bits
Timer HSDMA channel Trigger set-up bits
Timer 0 0 HSD0S[3:0] (D[3:0]) / HSDMA Ch.0/1 trigger set-up register (0x40298)
Timer 1 1 HSD1S[3:0] (D[7:4]) / HSDMA Ch.0/1 trigger set-up register (0x40298)
Timer 2 2 HSD2S[3:0] (D[3:0]) / HSDMA Ch.2/3 trigger set-up register (0x40299)
Timer 3 3 HSD3S[3:0] (D[7:4]) / HSDMA Ch.2/3 trigger set-up register (0x40299)
For HSDMA t o be invok ed, the trigger set-up bits should be set to "0101" in advance. Transfer conditions, etc.
must also be set on the HSDMA side.
If the 8-bit timer is selected as the HSDMA trigger, the HSDMA channel is invoked through generation of
the interrupt factor.
For details on HSDMA transfer, refer to "HSDMA (High-Speed DMA)".
Trap vectors
The trap vector addresses for individual underflow interrupt factors are set by de fault as shown below:
Timer 0 underflow interrupt: 0x0C000D0
Timer 1 underflow inter rupt: 0x0C000D4
Timer 2 underflow interrupt: 0x0C000D8
Timer 3 underflow interrupt: 0x0C000DC
The bas e address of the trap table can be changed using the TTBR register (0x48134 to 0x48137).
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS
B-III-3-10 EPSON S1C33L03 FUNCTION PART
I/O Memory of 8-Bit Programmable Timers
Table 3.6 shows t he control bits of the 8-bit programmable timers.
For details on the I/O memory of the prescaler used to set a clock, refer to "Prescaler".
Table 3.6 Control Bits of 8-Bit Programmable Timer
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
PTOUT0
PSET0
PTRUN0
D7–3
D2
D1
D0
reserved
8-bit timer 0 clock output control
8-bit timer 0 preset
8-bit timer 0 Run/Stop control
–
0
–
0
–
R/W
W
R/W
0 when being read.
0 when being read.
0040160
(B) –
1 On 0 Off
1 Preset 0 Invalid
1 Run 0 Stop
8-bit timer 0
control register
0 to 255RLD07
RLD06
RLD05
RLD04
RLD03
RLD02
RLD01
RLD00
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 0 reload data
RLD07 = MSB
RLD00 = LSB
X
X
X
X
X
X
X
X
R/W0040161
(B)
8-bit timer 0
reload data
register
0 to 255PTD07
PTD06
PTD05
PTD04
PTD03
PTD02
PTD01
PTD00
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 0 counter data
PTD07 = MSB
PTD00 = LSB
X
X
X
X
X
X
X
X
R0040162
(B)
8-bit timer 0
counter data
register
–
PTOUT1
PSET1
PTRUN1
D7–3
D2
D1
D0
reserved
8-bit timer 1 clock output control
8-bit timer 1 preset
8-bit timer 1 Run/Stop control
–
0
–
0
–
R/W
W
R/W
0 when being read.
0 when being read.
0040164
(B) –
1 On 0 Off
1 Preset 0 Invalid
1 Run 0 Stop
8-bit timer 1
control register
0 to 255RLD17
RLD16
RLD15
RLD14
RLD13
RLD12
RLD11
RLD10
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 1 reload data
RLD17 = MSB
RLD10 = LSB
X
X
X
X
X
X
X
X
R/W0040165
(B)
8-bit timer 1
reload data
register
0 to 255PTD17
PTD16
PTD15
PTD14
PTD13
PTD12
PTD11
PTD10
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 1 counter data
PTD17 = MSB
PTD10 = LSB
X
X
X
X
X
X
X
X
R0040166
(B)
8-bit timer 1
counter data
register
–
PTOUT2
PSET2
PTRUN2
D7–3
D2
D1
D0
reserved
8-bit timer 2 clock output control
8-bit timer 2 preset
8-bit timer 2 Run/Stop control
–
0
–
0
–
R/W
W
R/W
0 when being read.
0 when being read.
0040168
(B) –
1 On 0 Off
1 Preset 0 Invalid
1 Run 0 Stop
8-bit timer 2
control register
0 to 255RLD27
RLD26
RLD25
RLD24
RLD23
RLD22
RLD21
RLD20
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 2 reload data
RLD27 = MSB
RLD20 = LSB
X
X
X
X
X
X
X
X
R/W0040169
(B)
8-bit timer 2
reload data
register
0 to 255PTD27
PTD26
PTD25
PTD24
PTD23
PTD22
PTD21
PTD20
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 2 counter data
PTD27 = MSB
PTD20 = LSB
X
X
X
X
X
X
X
X
R004016A
(B)
8-bit timer 2
counter data
register
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS
S1C33L03 FUNCTION PART EPSON B-III-3-11
A-1
B-III
8TM
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
PTOUT3
PSET3
PTRUN3
D7–3
D2
D1
D0
reserved
8-bit timer 3 clock output control
8-bit timer 3 preset
8-bit timer 3 Run/Stop control
–
0
–
0
–
R/W
W
R/W
0 when being read.
0 when being read.
004016C
(B) –
1 On 0 Off
1 Preset 0 Invalid
1 Run 0 Stop
8-bit timer 3
control register
0 to 255RLD37
RLD36
RLD35
RLD34
RLD33
RLD32
RLD31
RLD30
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 3 reload data
RLD37 = MSB
RLD30 = LSB
X
X
X
X
X
X
X
X
R/W004016D
(B)
8-bit timer 3
reload data
register
0 to 255PTD37
PTD36
PTD35
PTD34
PTD33
PTD32
PTD31
PTD30
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 3 counter data
PTD37 = MSB
PTD30 = LSB
X
X
X
X
X
X
X
X
R004016E
(B)
8-bit timer 3
counter data
register
–
PTOUT4
PSET4
PTRUN4
D7–3
D2
D1
D0
reserved
8-bit timer 4 clock output control
8-bit timer 4 preset
8-bit timer 4 Run/Stop control
–
0
–
0
–
R/W
W
R/W
0 when being read.
0 when being read.
0040174
(B) –
1 On 0 Off
1 Preset 0 Invalid
1 Run 0 Stop
8-bit timer 4
control register
0 to 255RLD47
RLD46
RLD45
RLD44
RLD43
RLD42
RLD41
RLD40
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 4 reload data
RLD47 = MSB
RLD40 = LSB
X
X
X
X
X
X
X
X
R/W0040175
(B)
8-bit timer 4
reload data
register
0 to 255PTD47
PTD46
PTD45
PTD44
PTD43
PTD42
PTD41
PTD40
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 4 counter data
PTD47 = MSB
PTD40 = LSB
X
X
X
X
X
X
X
X
R0040176
(B)
8-bit timer 4
counter data
register
–
PTOUT5
PSET5
PTRUN5
D7–3
D2
D1
D0
reserved
8-bit timer 5 clock output control
8-bit timer 5 preset
8-bit timer 5 Run/Stop control
–
0
–
0
–
R/W
W
R/W
0 when being read.
0 when being read.
0040178
(B) –
1 On 0 Off
1 Preset 0 Invalid
1 Run 0 Stop
8-bit timer 5
control register
0 to 255RLD57
RLD56
RLD55
RLD54
RLD53
RLD52
RLD51
RLD50
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 5 reload data
RLD57 = MSB
RLD50 = LSB
X
X
X
X
X
X
X
X
R/W0040179
(B)
8-bit timer 5
reload data
register
0 to 255PTD57
PTD56
PTD55
PTD54
PTD53
PTD52
PTD51
PTD50
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 5 counter data
PTD57 = MSB
PTD50 = LSB
X
X
X
X
X
X
X
X
R004017A
(B)
8-bit timer 5
counter data
register
–
0 to 7
0 to 7
–
–
PSIO02
PSIO01
PSIO00
–
P8TM2
P8TM1
P8TM0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Serial interface Ch.0
interrupt level
reserved
8-bit timer 0–3 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040269
(B)
8-bit timer,
serial I/F Ch.0
interrupt
priority register
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS
B-III-3-12 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
E8TU3
E8TU2
E8TU1
E8TU0
D7–4
D3
D2
D1
D0
reserved
8-bit timer 3 underflow
8-bit timer 2 underflow
8-bit timer 1 underflow
8-bit timer 0 underflow
– –
0
0
0
0
–
R/W
R/W
R/W
R/W
0 when being read.0040275
(B) 1 Enabled 0 Disabled
8-bit timer
interrupt
enable register
–
F8TU3
F8TU2
F8TU1
F8TU0
D7–4
D3
D2
D1
D0
reserved
8-bit timer 3 underflow
8-bit timer 2 underflow
8-bit timer 1 underflow
8-bit timer 0 underflow
– –
X
X
X
X
–
R/W
R/W
R/W
R/W
0 when being read.0040285
(B) 1 Factor is
generated 0 No factor is
generated
8-bit timer
interrupt factor
flag register
RSTX0
RSRX0
R8TU3
R8TU2
R8TU1
R8TU0
R16TC5
R16TU5
D7
D6
D5
D4
D3
D2
D1
D0
SIF Ch.0 transmit buffer empty
SIF Ch.0 receive buffer full
8-bit timer 3 underflow
8-bit timer 2 underflow
8-bit timer 1 underflow
8-bit timer 0 underflow
16-bit timer 5 comparison A
16-bit timer 5 comparison B
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0040292
(B) 1 IDMA
request 0 Interrupt
request
16-bit timer 5,
8-bit timer,
serial I/F Ch.0
IDMA request
register
DESTX0
DESRX0
DE8TU3
DE8TU2
DE8TU1
DE8TU0
DE16TC5
DE16TU5
D7
D6
D5
D4
D3
D2
D1
D0
SIF Ch.0 transmit buffer empty
SIF Ch.0 receive buffer full
8-bit timer 3 underflow
8-bit timer 2 underflow
8-bit timer 1 underflow
8-bit timer 0 underflow
16-bit timer 5 comparison A
16-bit timer 5 comparison B
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0040296
(B) 1 IDMA
enabled 0 IDMA
disabled
16-bit timer 5,
8-bit timer,
serial I/F Ch.0
IDMA enable
register
–
CFP16
CFP15
CFP14
CFP13
CFP12
CFP11
CFP10
D7
D6
D5
D4
D3
D2
D1
D0
reserved
P16 function selection
P15 function selection
P14 function selection
P13 function selection
P12 function selection
P11 function selection
P10 function selection
–
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.
Extended functions
(0x402DF)
00402D4
(B) 1 EXCL5
#DMAEND1
0 P16
1 EXCL4
#DMAEND0
0 P15
1 EXCL3
T8UF3 0 P13
1 EXCL2
T8UF2 0 P12
1 EXCL1
T8UF1 0 P11
1 EXCL0
T8UF0 0 P10
–P1 function
select register
1 FOSC1 0 P14
–
IOC16
IOC15
IOC14
IOC13
IOC12
IOC11
IOC10
D7
D6
D5
D4
D3
D2
D1
D0
reserved
P16 I/O control
P15 I/O control
P14 I/O control
P13 I/O control
P12 I/O control
P11 I/O control
P10 I/O control
–
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.
This register
indicates the values
of the I/O control
signals of the ports
when it is read. (See
detailed explanation.)
00402D6
(B) 1Output 0Input
–P1 I/O control
register
CFEX7
CFEX6
CFEX5
CFEX4
CFEX3
CFEX2
CFEX1
CFEX0
D7
D6
D5
D4
D3
D2
D1
D0
P07 port extended function
P06 port extended function
P05 port extended function
P04 port extended function
P31 port extended function
P21 port extended function
P10, P11, P13 port extended
function
P12, P14 port extended function
0
0
0
0
0
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00402DF
(B)
Port function
extension
register
1
#DMAEND3
0 P07, etc.
1
#DMAACK3
0 P06, etc.
1
#DMAEND2
0 P05, etc.
1
#DMAACK2
0 P04, etc.
1 #GARD 0 P31, etc.
1 #GAAS 0 P21, etc.
1 DST0
DST1
DPC0
0 P10, etc.
P11, etc.
P13, etc.
1 DST2
DCLK 0 P12, etc.
P14, etc.
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS
S1C33L03 FUNCTION PART EPSON B-III-3-13
A-1
B-III
8TM
CFP13–CFP10: P1[ 3:0 ] p in func tio n select io n (D[3:0 ]) / P 1 fu nctio n sele ct regist er (0 x4 0 2D4 )
Selects the pin that is used to output a timer underflow signal to external devices.
Write "1": Under flow signal o utp ut pi n
Write "0": I/ O port pin
Read: Valid
Select the pin used to output a timer underflo w signal to exter nal devices from amon g P10 through P1 3 by wr iting
"1" to the corresponding bit, CFP10 through CF P13. P10 through P13 correspond to t imers 0 through 3,
respectively. If "0" is written to CFP1x, the pin is set for an I/O port.
At c old start, CFP1x is set to "0" (I/O port). At hot start, the bit retains its state from prior to the initial reset.
IOC13–IOC10: P1[3:0 ] p ort I/O con tro l (D[3:0 ]) / P 1 I/ O con tro l regi st er (0 x40 2D 6 )
Directs P10 through P13 for input or output and indicates the I/O control signal value of the port.
When writing data
Write "1": O utput mode
Write "0": Input mode
If a pin chosen from among P10 through P13 is used to output an underflow signal, write "1" to the corresponding
I/O control bit to set it to output mode. If the pin is set to input mode, even if its CFP1x is set to "1", it functions as
the event counter input pin of a 16-bit programmable timer cannot be used to output a timer underflow signal.
When re ad in g d ata
Read "1": I/O control signal (output)
Read "0": I/O control signal (input)
The I/O control signal value for the port pin is read from this register. When I/O port function is selected using the
CFEX and CFP1x reg isters, the value written to the IOC register is read out as is. When peripheral function is
selected, the read value depends on the peripheral circuit status and may not indicate the value written to the IOC
register.
At c old start, IOC1x is set to "0" (input mode). At hot start, the bit retains its state from prior to the initial reset.
CFEX1: P10, P11, P13 port extended fun ction ( D 1) / Port function ex tension reg ister (0x402DF)
CFEX0: P12, P14 port extended function (D0) / Port function ex tension register (0x402DF)
Sets whether the function of an I/O-port pin is to be extended.
Write "1": Fun ction-extended pin
Write "0": I/O- port/peripheral-circuit pin
Read: Valid
When CFEX[1:0] is set to "1", the P13–P10 ports function as debug si gn al o utput ports. W he n C FE X [1:0] = "0",
the CFP1[3:0] bit becomes effective, so the settings of these bits determine whether the P13–P10 ports function as
I/O p ort s or timer underflow signal output ports.
At c old start, CFEX[1:0] is set to "1" (function-extended pins). At hot start, CFEX[1:0] retains its state from prior
to the initial reset.
RLD07–RLD00: Timer 0 reload data (D[7:0]) / 8-bit timer 0 reload data register (0x40161)
RLD17–RLD10: Timer 1 reload data (D[7:0]) / 8-bit timer 1 reload data register (0x40165)
RLD27–RLD20: Timer 2 reload data (D[7:0]) / 8-bit timer 2 reload data register (0x40169)
RLD37–RLD30: Timer 3 reload data (D[7:0]) / 8-bit timer 3 reload data register (0x4016D)
RLD47–RLD40: Timer 4 reload data (D[7:0]) / 8-bit timer 4 reload data register (0x40175)
RLD57–RLD50: Timer 5 reload data (D[7:0]) / 8-bit timer 5 reload data register (0x40179)
Set the initial counter value of each timer.
The reload data set in this register is loaded into each counter, and the counter starts counting down beginning with
this data, which is used as the initial count.
There are two cases in which the reload data is loaded into the counter: when data is preset after "1" is written to
PS ETx, or wh en data is automatically reloaded upon counter underflow.
At i nitial reset, RLD is not initialized.
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS
B-III-3-14 EPSON S1C33L03 FUNCTION PART
PTD07–PTD00: Tim er 0 count er d ata (D[7 :0 ]) / 8 -bi t timer 0 cou nt er data (0x40 16 2)
PTD17–PTD10: Tim er 1 count er d ata (D[7 :0 ]) / 8 -bi t timer 1 cou nt er data (0x40 16 6)
PTD27–PTD20: Tim er 2 count er d ata (D[7 :0 ]) / 8 -bi t timer 2 cou nt er data (0x40 16 A)
PTD37–PTD30: Tim er 3 count er d ata (D[7 :0 ]) / 8 -bi t timer 3 cou nt er data (0x40 16 E)
PTD47–PTD40: Tim er 4 count er d ata (D[7 :0 ]) / 8 -bi t timer 4 cou nt er data (0x40 17 6)
PTD57–PTD50: Tim er 5 counter d ata (D[7 :0 ]) / 8 -bi t timer 5 count er d ata (0x40 17 A)
The 8-b it programmable timer data can be read out from these bits.
These bits function as buffers that retain the counter data when read out, enabling the data to be read out at any
time.
At initial reset, PTD is not initialized.
PSET0: Timer 0 pr eset (D1) / 8-bit timer 0 control register (0x40160)
PSET1: Timer 1 pr eset (D1) / 8-bit timer 1 control register (0x40164)
PSET2: Timer 2 pr eset (D1) / 8-bit timer 2 control register (0x40168)
PSET3: Timer 3 pr eset (D1) / 8-bit t imer 3 control register (0x4016C)
PSET4: Timer 4 pr eset (D1) / 8-bit timer 4 control register (0x40174)
PSET5: Timer 5 pr eset (D1) / 8-bit timer 5 control register (0x40178)
Preset the reload data in the counter.
Write "1": Preset
Write "0": Invalid
Read: Alwa ys "0"
The reload data of RLDx is preset in the counter of timer x by writing "1" to PSETx. If the counter is preset when
in a RUN state, the counter starts counting immediately after the reload data is preset.
If the counter is preset when in a STOP state, the reload data that has been preset is retained.
Writing "0" results in No Operation.
Since PSETx is a write-only bit, its content when read is always "0".
PTRUN0: Timer 0 RUN/STOP control (D0) / 8-bit timer 0 control regis ter (0x40160)
PTRUN1: Timer 1 RUN/STOP control (D0) / 8-bit timer 1 control regis ter (0x40164)
PTRUN2: Timer 2 RUN/STOP control (D0) / 8-bit timer 2 control regis ter (0x40168)
PTRUN3: Timer 3 RUN/STOP control (D0) / 8-bit timer 3 control regist er (0x4016C)
PTRUN4: Timer 4 RUN/STOP control (D0) / 8-bit timer 4 control regis ter (0x40174)
PTRUN5: Timer 5 RUN/STOP control (D0) / 8-bit timer 5 control regis ter (0x40178)
Controls the counter's RUN/STOP states.
Write "1": RUN
Write "0": STOP
Read: Valid
The cou nter of each timer starts counting down when "1" written to PTRUNx, and stops counting when "0" is
written.
While in a STOP state, the counter retains its count until it is preset with reload data or placed in a RUN state.
When the state is changed from STOP to RUN, the counter can restart counting beginning with the retained count.
At i nitial reset, PTRUNx is set to "0" (STOP).
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS
S1C33L03 FUNCTION PART EPSON B-III-3-15
A-1
B-III
8TM
PTOUT0: Timer 0 clock out put control register (D2) / 8-bit timer 0 control reg ister (0x40160)
PTOUT1: Tim er 1 clock out put control register (D2) / 8-b it timer 1 control register (0x40164 )
PTOUT2: Timer 2 clock out put control register (D2) / 8-bit timer 2 control reg ister (0x40168)
PTOUT3: Timer 3 clock out put control reg ister (D2) / 8-b it timer 3 control register (0x4016C)
PTOUT4: Timer 4 clock out put control register (D2) / 8-bit timer 4 control reg ister (0x40174)
PTOUT5: Timer 5 clock out put control register (D2) / 8-bit timer 5 control reg ister (0x40178)
Controls the clock output of each timer.
Write "1": On
Write "0": Off
Read: Valid
The unde rflow signal of timer x is ou tput from the exter nal output pin set by CFP1x by wr iting "1" to PTO U Tx.
When using timer 2 or 3 as the clock source of the serial interface, a clock generated from the underflow signal by
dividing it by 2 is output to t he c orresponding chan nel of the serial int erface.
The clock output is turned off by writing "0" to PTOUT, and the external output is fixed at "0" and the internal
clock output is fixed at "1".
At i nitial reset, PTOUT is set to "0" (off).
P8TM2–P8TM0: 8-b i t t im er interru pt lev el ( D[ 2: 0] ) / 8- b it ti m er, ser i al I/ F Ch. 0 i nt err u pt pr i or ity regi st er (0x 4026 9)
Set the priority level of the 8-bit programmable timer interrupt in the range of 0 to 7.
At i nitial reset, the content of the P8TM register becomes indeterminate.
E8TU0: Timer 0 interrupt enable (D0) / 8-bit time r i n t errupt enable regist er (0 x40275)
E8TU1: Timer 1 interrupt enable (D1) / 8-bit time r i n t errupt enable regist er (0 x40275)
E8TU2: Timer 2 interrupt enable (D2) / 8-bit time r interrupt enable regist er (0 x40275)
E8TU3: Timer 3 interrupt enable (D3) / 8-bit time r i n t errupt enable regist er (0 x40275)
Enabl es or disables generation of an interrupt to the CPU.
Write "1": Inte rrupt enabled
Write "0": Inte rrupt disabled
Read: Valid
E8TUx i s the interrupt enable bit which controls the interrupt generated by each timer. The interrupt set to "1" by
this bit is enabled, and the interrupt set to "0" by this bit is disabled.
At i nitial reset, E8TUx is set to "0" (interrupt disabled).
F8TU0: Timer 0 interrupt factor flag (D0) / 8-bit timer interrupt factor flag register (0x40285)
F8TU1: Timer 1 interrupt factor flag (D1) / 8-bit timer interrupt factor flag register (0x40285)
F8TU2: Timer 2 interrupt factor flag (D2) / 8-bit timer interrupt factor flag register (0x40285)
F8TU3: Timer 3 interrupt factor flag (D3) / 8-bit timer interrupt factor flag register (0x40285)
Indicates the interrupt generation status of the 8-bit programmable timer.
When read
Read "1": Interrupt facto r has o ccu rred
Read "0": No inte rrupt fa ctor h as o ccu rred
When written using the rese t-onl y m etho d (d ef au lt)
Write "1": Interrupt factor flag is reset
Write "0": Invalid
When written using the read /w rite m et ho d
Write "1": Interrupt flag is set
Write "0": Interrupt flag is reset
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS
B-III-3-16 EPSON S1C33L03 FUNCTION PART
F8TUx i s the interrupt factor flag corresponding to each timer. It is set to "1" when the counter underflows.
At t his time, if the following conditions are met, an interrupt to the CPU is generated:
1. The corresponding interrupt enable register bit is set to "1".
2. No other interrupt request of a higher prior ity has been generated.
3. The IE bit of the PSR is set to "1" (interrupts enabled).
4. The value set in the corresponding interrupt priority register is higher than the interrupt level (IL) of the CPU.
When using the interrupt factor of the 8-bit programmable timer to request IDMA, note that even when the above
conditions are met, no interrupt request to the CPU is generated for the interrupt factor that has occurred. If
interrupts are enabled at the setting of IDMA, an interrupt is generated under the above conditions after the data
transfer by IDMA is completed.
The interrupt factor flag is set to "1" whenever interrupt generation conditions are met, regardless of how the
inte rrupt en ab le and in te rru pt p riority regi ste rs are set.
If the next interrupt is to be accepted after an interrupt has occurred, it is necessary that the interrupt factor flag be
reset, and that the PSR be set again (by setting the IE bit to "1" after setting the IL to a value lower than the level
indicated by the interrupt priority register, or by executing the reti instruction).
The interrupt factor flag can be reset only by writing to it in the software. Note that if the PSR is set again to accept
interrupts generated (or if the reti instruction is executed) without resetting the interrupt factor flag, the same
interrupt occurs again. Note also that the value to be written to reset the flag is "1" when the reset-only method
(RSTONLY = " 1" ) is used, and "0" when the rea d/ write me thod (RSTONLY = "0" ) is used.
At i nitial reset, the content of F8TUx becomes indeterminate, so be sure to reset it in the software.
R8TU0: Timer 0 I D M A reques t (D2) / 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA request register (0x40292)
R8TU1: Timer 1 I D M A reques t (D3) / 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA request register (0x40292)
R8TU2: Timer 2 I D M A reques t (D4) / 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA request register (0x40292)
R8TU3: Timer 3 I D M A reques t (D5) / 16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA request register (0x40292)
Specifies whether IDMA is to be invoked at the occurrence of an interrupt factor.
When using the se t-o n ly m et ho d (d ef ault)
Write "1": IDMA request
Write "0": Not changed
Read: Valid
When using the read /w rite m et ho d
Write "1": IDMA request
Write "0": Inte rrupt request
Read: Valid
R8TUx is the IDMA request bit for each timer. If this bit is set to "1", IDMA can be invoked when an interrupt
factor occurs, and thus programmed data transfers are performed. If the bit is set to "0", normal interrupt
processing is performed and IDMA is not invoked.
For details on IDMA, refer to "IDMA (Intelligent DMA)".
At i nitial reset, R8TUx is set to "0" (interrupt request).
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS
S1C33L03 FUNCTION PART EPSON B-III-3-17
A-1
B-III
8TM
DE8TU0: Timer 0 ID M A enable ( D2) / 16- bit timer 5, 8-bit timer , serial I/F Ch .0 I D M A enable r egiste r (0x402 96)
DE8TU1: Timer 1 ID M A enable ( D3) / 16- bit timer 5, 8-bit timer , serial I/F Ch .0 I D M A enable r egiste r (0x40 296)
DE8TU2: Timer 2 ID M A enable ( D4) / 16- bit timer 5, 8-bit timer , serial I/F Ch .0 I D M A enable r egiste r (0x402 96)
DE8TU3: Timer 3 ID M A enable ( D5) / 16- bit timer 5, 8-bit timer , serial I/F Ch .0 I D M A enable r egiste r (0x402 96)
Enables ID M A transfer by means of an interrupt factor.
When using the se t-o n ly m et ho d (d ef ault)
Write "1": IDMA enabled
Write "0": Not changed
Read: Valid
When using the read /w rite m et ho d
Write "1": IDMA enabled
Write "0": IDMA disabled
Read: Valid
If DE8TUx is set to "1", the IDMA request by the interrupt factor is enabled. If the register bit is set to "0", the
IDMA request is disabled.
Aft er an initial reset, DE8TUx is set to "0" (IDMA disabled).
Pr ogramming Notes
(1) The 8-bit programmable timer operates only when the prescaler is operating.
(2) Do not use a clock that is faster than the CPU operating clock for the 8-bit programmable timer.
(3) When setting an input clock, make sure the 8-bit programmable timer is turned off.
(4) Since the underflow interrupt condition and the timer output status are undefined after an initial reset, the
counter initial value should be set to the 8-bit timer before resetting the interrupt factor flag or turning the
timer output on.
(5) After an initial reset, the interrupt factor flag (F8TUx) becomes indeterminate. To prevent generation of an
unw anted interrupt or IDMA request, be s ure to reset this flag in the software.
(6) To prevent another interrupt from being generated again by the same factor after an interrupt has occurred, be
sure to reset the interrupt factor flag (F8TUx) before setting the PSR again or executing the reti instruction.
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS
B-III-3-18 EPSON S1C33L03 FUNCTION PART
TH IS PAGE IS BLANK.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS
S1C33L03 FUNCTION PART EPSON B-III-4-1
A-1
B-III
16TM
III-4 16-BIT PROGRAMMABLE TIMERS
Configuration of 16-Bit Programmable Timer
The Peripheral Block contains six systems of 16-bit programmable timers (timers 0 to 5). They also have an event
counter function using an I/O port pin.
Note: On the following pages, each timer is identified as timer x (x = 0 to 5). The functions and co ntrol
register s tr u ctur e s of 16 -bit program mable timers 0 to 5 ar e the sam e. Control bit names are
assi g ned nu mer al s "0" t o "5" de noti ng t im er num bers . Sinc e ex pla nati on s are commo n t o all timer s,
ti mer n umb er s ar e represented by "x" un less it is ne cess ary to specify a tim er num ber.
Figure 4.1 sho w s the structure of one chann el of the 16-bit programmable timer.
Data bus
16-bit up counter (TCx)
16-bit comparison data register B (CRxB)
Comparison register B buffer (CRBxB)
16-bit comparison data register A (CRxA)
Comparison register A buffer (CRBxA)
Timer x control register
Control circuit
Clock select circuitPrescaler
Clock
generator
Comparator
Comparator
INCLx
Clock output TMx
Comparison A
interrupt
Comparison B
interrupt
Comparison
match B
Comparison
match A
Comparison A
Comparison B
Timer x
Interrupt
controller
External clock EXCLx
Figur e 4.1 Structure of 16-Bit Programmable Timer
In each timer, a 16-bit up-counter (TCx), as well as two 16-bit comparison data registers (CRxA, CRxB) and their
buffers (CRBxA, CRBxB), are provided.
The 16- bit counter can be reset to "0" by software and counts up using the prescaler output clock or an external
signal input from the I/O port. The counter value can be read by software.
The comparison data registers A and B are used to store the data to be compared with the content of the up-counter.
This regist er can be directly read and written. Furthermore, comparison data can be set via the comparison register
buffer. In this case, the set value is loaded to the comparison data register when the counter is reset by the
comparison match B signal or software (by writing "1" to PRESETx bit). The software can select whether
comparison data is written to the comparison data register or the buffer.
When the counter value matches to the content of each comparison data register, the comparator outputs a signal
that cont ro ls th e inte rrupt an d th e outp ut sign al. Thu s the regi ste rs al lo w in te rru pt g ene ra tin g in te rva l s an d th e
timer's output clock frequency and duty ratio to be programmed.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS
B-III-4-2 EPSON S1C33L03 FUNCTION PART
I/O Pins of 16-Bit Programmable Timers
Table 4.1 shows t he input/output pins used for the 16-bit programmable timers.
Table 4.1 I/O Pins of 16-Bit Programmable Timer
Pin name I/O Fu nction Functi on select bit
P10/EXCL0/
T8UF0/DST0 I/O I/O port / 16-bit timer 0 event counter input (I) /
8-bit timer 0 output (O) / DST0 output (Ex) CFP10(D0)/P1 function select register(0x402D4)
CFEX1(D1)/Port function extension register(0x402DF)
P11/EXCL1/
T8UF1/DST1 I/O I/O port / 16-bit timer 1 event counter input (I) /
8-bit timer 1 output (O) / DST1 output (Ex) CFP11(D1)/P1 function select register(0x402D4)
CFEX1(D1)/Port function extension register(0x402DF)
P12/EXCL2/
T8UF2/DST2 I/O I/O port / 16-bit timer 2 event counter input (I) /
8-bit timer 2 output (O) / DST2 output (Ex) CFP12(D2)/P1 function select register(0x402D4)
CFEX0(D0)/Port function extension register(0x402DF)
P13/EXCL3/
T8UF3/DPCO I/O I/O port / 16-bit timer 3 event counter input (I) /
8-bit timer 3 output (O) / DPCO output (Ex) CFP13(D3)/P1 function select register(0x402D4)
CFEX1(D1)/Port function extension register(0x402DF)
P15/EXCL4
/#DMAEND0 I/O I/O port / 16-bit timer 4 event counter input (I) /
High-speed DMA Ch.0 end signal output (O) CFP15(D5)/P1 function select register(0x402D4)
P16/EXCL5
/#DMAEND1 I/O I/O port / 16-bit timer 5 event counter input (I) /
High-speed DMA Ch.1 end signal output (O) CFP16(D6)/P1 function select register(0x402D4)
P22/TM0 I/O I/O port / 16-bit timer 0 output CFP22(D2)/P2 function select register(0x402D8)
P23/TM1 I/O I/O port / 16-bit timer 1 output CFP23(D3)/P2 function select register(0x402D8)
P24/TM2 I/O I/O port / 16-bit timer 2 output CFP24(D4)/P2 function select register(0x402D8)
P25/TM3 I/O I/O port / 16-bit timer 3 output CFP25(D5)/P2 function select register(0x402D8)
P26/TM4 I/O I/O port / 16-bit timer 4 output CFP26(D6)/P2 function select register(0x402D8)
P27/TM5 I/O I/O port / 16-bit timer 5 output CFP27(D7)/P2 function select register(0x402D8)
(I): Input mode, (O): Output mode, (Ex): Extend ed f u nct ion
TMx (output pin of the 16-bit programmable timer)
This pin outputs a clock generated by the t imer x.
EXCLx (event counter input pin)
When using the timer x as an event counter, input count pulses from an external source to this pin.
How to set the input/output pins of 16-bit programmable timers
All clock output pins used by the 16-bit programmable timers are shared with I/O ports. At cold start, all
these pins are set for the I/O port pins P2x (function select bit CFP2x = "0"), and go into high-impedance.
When using the clock output function of the 16-bit programmable timer, select the desired timer and write "1"
to the function select bit CFP2x for the corresponding pin. At hot start, these pins retain their status before
from prior to the reset.
All event-counter input pins are also shared with I/O-ports. At cold start, the EXCL[3:0] pins are set for
debug signal output pins (function extension bit CFEX[1:0] = "1") and the EXCL[5:4] pins are set for I/O-
port pins P1[5:4] (function select bit CFP1[5:4] = "0"). When using the event counter function, select the
desired timer and write "1" to the function select bit CFP1x and write "0" to the function select bit CFEXx for
the corresponding pin.
Note that these pins are also shared with output pins for the 8-bit programmer timers, etc. When the
input/output pins are set in input mode, they function as event counter inputs. Therefore, it is necessary to set
the I/O port's I/O control bit IOC1x to "0" in advance. At cold start, these pins are set in input mode. At hot
start, they retain their status from prior to the reset.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS
S1C33L03 FUNCTION PART EPSON B-III-4-3
A-1
B-III
16TM
Uses of 16-Bit Programmable Timers
The up- coun ters of the 16-bit programmable timer cyclically output a comparison-match signal in accordance with
the comparison data that are set in the software. This signal is used to generate an interrupt request to the CPU or
control the internal peripheral circuits. A clock generated from the signal can also be output to external devices.
CPU interrupt request/IDMA invocation request
Each timer's comparison match (matching of counter and comparison data) can be used as an interrupt factor
to generate an interrupt request to the CPU. Therefore, an interrupt can be generated at an interval that is set
in the software.
Furthermore, this interrupt factor can also be used to invoke IDMA or HSDMA.
Clock o u tpu t to ext ernal devices
A clo ck generated from the comparison-match signal can be output from the chip to the outside. The clock
cycle is determined by comparison data B, and the duty ratio is determined by comparison data A. This
outpu t can be used to control external devices. The output pins of each timer are described in the preceding
section.
A/D co nv erter start trig g er
The A/ D conve rt er allows a trigger to start the A/D conversion to be selected from among four available types.
One i s the comparison-match B of the 16-bit programmable timer 0. This makes it possible to perform the
A/D c onversi on at programmable intervals.
To use this function, write "01" to the A/D converter control TS[1:0] (D[4:3]) / A/D trigger register
(0x40242) to select the 16-bit programmable timer 0 as the trigger.
Watchdog timer
The 16- bit programmable t imer 0 can be used as a watchdog timer to monitor C PU cras h. In this ca se , the
comparison-match B of this timer serves as an NMI request signal to the CPU.
To use this function, write "1" to the watchdog timer control bit EWD (D1) / Watchdog timer enable register
(0x40171) to enable the NMI. For details on how to control the watchdog timer, refer to "Watchdog Timer".
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS
B-III-4-4 EPSON S1C33L03 FUNCTION PART
Control and Operation of 16-Bit Programmable Timer
The following settings must first be made before the 16-bit programmable timer starts counting:
1. Setti ng pins for input/output (only when necessary)
2. Setting input clock
3. Selecting comparison data register/buffer
4. Setti ng c lock output conditions (signal active level, fine mode)
5. Setting comparison data
6. Setting interrupt/IDMA
For details on how to set clock output conditions and interrupts and DMA, refer to "Controlling Clock Output" and
"16-Bit Programmable Timer Interrupts and DMA".
Setting pin for input/output
The pin mu st be set for output for the output clock of the 16-bit programmable timer to be fed to external
devices.
The pin for input must be set for the 16-bit programmable timer to be used as an event counter that counts
external clock pulses.
For details on how to set the pin, refer to "I/O Pins of 16-Bit Programmable Timers".
Setting the input clock
The cou nt clock for each timer can be selected from between an internal clock and an external clock. Use the
following control bits to select the input clock:
Timer 0 input clock selection: CKSL0 (D3) / 16-bit timer 0 control register (0x48186)
Timer 1 input clock sel ection: CKSL 1 (D3) / 16-bit timer 1 contr ol regist er (0x4818E)
Timer 2 input clock selection: CKSL2 (D3) / 16-bit timer 2 control register (0x48196)
Timer 3 input clock selection: CKSL3 (D3) / 16-bit timer 3 control register (0x4819E)
Timer 4 input clock selection: CKSL4 (D3) / 16-bit timer 4 control register (0x481A6)
Timer 5 input clock selection: CKSL5 (D3) / 16-bit timer 5 control register (0x481AE)
An external clock is selected by writing "1" to CKSLx, and the internal clock is selected by writing "0".
At i nitial reset, CKSLx is set for the internal clock.
An external clock can be used for the timer for which the pin is set for input.
•Internal cl ock
When the internal clock is selected as a timer, the timer is operated by the prescaler output clock. The
prescaler div ision ratio can be selected for each timer.
Table 4.2 Setting the Internal Clock
Timer Control register Division ratio select bit Clock control bit
Timer 0 16-bit timer 0 clock control register (0x40147) P16TS0[2:0] (D2:0]) P16TON0 (D3)
Timer 1 16-bit timer 1 clock control register (0x40148) P16TS1[2:0] (D2:0]) P16TON1 (D3)
Timer 2 16-bit timer 2 clock control register (0x40149) P16TS2[2:0] (D2:0]) P16TON2 (D3)
Timer 3 16-bit timer 3 clock control register (0x4014A) P16TS3[2:0] (D2:0]) P16TON3 (D3)
Timer 4 16-bit timer 4 clock control register (0x4014B) P16TS4[2:0] (D2:0]) P16TON4 (D3)
Timer 5 16-bit timer 5 clock control register (0x4014C) P16TS5[2:0] (D2:0]) P16TON5 (D3)
The division ratio can be selected fro m among eight types as shown in Table 4.3.
Table 4.3 Input Clock Selection
P16TS = 7 P16TS = 6 P16TS = 5 P16TS = 4 P16TS = 3 P16TS = 2 P16TS = 1 P16TS = 0
fPSCIN/4096 fPSCIN/1024 fPSCIN/256 fPSCIN/64 fPSCIN/16 fPSCIN/4 fPSCIN/2 fPSCIN/1
fPSCIN: Prescaler input clock frequency
The selected c lock is output from the prescaler to the 16-bit programmable timer by writing "1" to P16TONx.
Notes:•When th e inte rn al c loc k i s used, the 16-bit program m able timer operates only when the
prescaler is operating (ref er to "P re scaler" ) .
•When setti ng an inpu t clock, make su re the 16-bit programmable timer is turned off.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS
S1C33L03 FUNCTION PART EPSON B-III-4-5
A-1
B-III
16TM
•External clock
When using the timer as an event counter by supplying clock pulses from an external source, make sure the
event cycle is at least the CPU operating clock period.
Selecting comparison data register/buffer
The comparison data registers A and B are used to store the data to be compared with the content of the up-
counter. This register can be directly read and written. Furthermore, comparison data can be set via the
comparison register buffer. In this case, the set value is loaded to the comparison data register when the
counter is reset by the comparison match B signal or software (by writing "1" to PRESETx bit).
Select whether comparison data is written to the comparison data register or the buffer using the following
control bits:
Time r 0 compar ison reg is ter buffer enable: SELCRB0 (D5) / 16-bit timer 0 control register (0x48186)
Time r 1 compar ison reg is ter buffer enable: SELCRB1 (D5) / 16-bit timer 1 control register (0x4818E)
Time r 2 compar ison reg is ter buffer enable: SELCRB2 (D5) / 16-bit timer 2 control register (0x48196)
Time r 3 compar ison reg is ter buffer enable: SELCRB3 (D5) / 16-bit timer 3 control register (0x4819E)
Time r 4 compar ison reg is ter buffer enable: SELCRB4 (D5) / 16-bit timer 4 control register (0x481A6)
Time r 5 compar ison reg is ter buffer enable: SELCRB5 (D5) / 16-bit timer 5 control register (0x481AE)
When "1" is written to SELCRBx, the comparison register buffer is selected and when "0" is written, the
comparison data register is selected.
At i nitial reset, the comparison data register is selected.
Setting comparison data
The pro gram m able tim er contains two data comparators that allows the count data to be compared with given
values. The following registers are used to set these values.
Time r 0 compari son da ta A: CR 0A[15 :0] ( D[F:0]) / 16 -bit timer 0 comparison data A set-up register (0x48180)
Time r 0 compar ison dat a B: CR 0B[1 5:0] ( D[F:0] ) / 16- bit timer 0 comparison data B set-up register (0x48182)
Time r 1 compari son da ta A: CR 1A[15 :0] ( D[F:0]) / 16 -bit timer 1 comparison data A set-up register (0x48188)
Time r 1 compar ison dat a B: CR 1B[1 5:0] ( D[F:0] ) / 16- bit timer 1 comparison data B set-up register (0x4818A)
Time r 2 compari son da ta A: CR 2A[15 :0] ( D[F:0]) / 16 -bit timer 2 comparison data A set-up register (0x48190)
Time r 2 compa r ison dat a B: CR 2B[ 1 5:0] (D[ F: 0]) / 16 - bit timer 2 comp ari so n dat a B set -u p reg is ter (0x 48 19 2)
Time r 3 compari son da ta A: CR 3A[15 :0] ( D[F:0]) / 16 -bit timer 3 comparison data A set-up register (0x48198)
Time r 3 compar ison dat a B: CR 3B[1 5:0] ( D[F:0] ) / 16- bit timer 3 comparison data B set-up register (0x4819A)
Time r 4 compari son da ta A: CR 4A[15 :0] ( D[F:0]) / 16 -bit timer 4 comparison data A set-up register (0x481A0)
Time r 4 compar ison dat a B: CR 4B[1 5:0] ( D[F:0] ) / 16- bit timer 4 comparison data B set-up register (0x481A2)
Time r 5 compari son da ta A: CR 5A[15 :0] ( D[F:0]) / 16 -bit timer 5 comparison data A set-up register (0x481A8)
Time r 5 compar ison dat a B: CR 5B[1 5:0] ( D[F:0] ) / 16- bit timer 5 comparison data B set-up register (0x481AA)
When SELCRBx is set to "0", these registers allow direct reading/writing from/to the comparison data
register.
When SELCRBx is set to "1", these registers are used to read/write from/to the comparison register buffer.
The con tent of the buffer is loaded to the comparison data register when the counter is reset.
At i nitial reset, the comparison data registers/buffers are not initialized.
The pro gram mable timer comp ares the comparison data register and count data and, when the two values are
equal, generates a comparison match signal. This comparison match signal controls the clock output (TMx
signal) to external devices, in addition to generating an interrupt.
The comparison data B i s also us ed to reset the counter.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS
B-III-4-6 EPSON S1C33L03 FUNCTION PART
Resetting the counter
Each timer includes the PRESETx bit to reset the counter.
Timer 0 reset : PRESET0 (D1) / 16-bit timer 0 control register (0x48186)
Timer 1 reset : PRESET1 (D1) / 16-bit timer 1 control register (0x4818E)
Timer 2 reset : PRESET2 (D1) / 16-bit timer 2 control register (0x48196)
Timer 3 reset : PRESET3 (D1) / 16-bit timer 3 control register (0x4819E)
Timer 4 reset : PRESET4 (D1) / 16-bit timer 4 control register (0x481A6)
Timer 5 reset : PRESET5 (D1) / 16-bit timer 5 control register (0x481AE)
Normally, reset the counter before starting count-up by writing "1" to this control bit.
After the counter starts counting, it will be reset by comparison match B.
Timer RUN/STOP control
Each timer includes the PRUNx bit to control RUN/STOP.
Timer 0 RUN/ STOP control: PRUN0 (D0) / 16-bit timer 0 control register (0x48186)
Timer 1 RUN/ STOP control: PRUN1 (D0) / 16-bit timer 1 control register (0x4818E)
Timer 2 RUN/ STOP control: PRUN2 (D0) / 16-bit timer 2 control register (0x48196)
Timer 3 RUN/ STOP control: PRUN3 (D0) / 16-bit timer 3 control register (0x4819E)
Timer 4 RUN/ STOP control: PRUN4 (D0) / 16-bit timer 4 control register (0x481A6)
Timer 5 RUN/ STOP control: PRUN5 (D0) / 16-bit timer 5 control register (0x481AE)
The tim er starts counting when "1" is written to PRUNx. The clock input is disabled and the timer stops
counting when "0" is written to PRUNx.
This RUN/ STOP control does not affect the counter data. Even when the timer has stopped counting, the
counter retains its count so that the timer can start counting again from that point.
If the count of the counter matches the set value of the comparison data register during count-up, the timer
generates a com pa ris on match in te rru pt.
When the counter matches comparison data B, an interrupt is generated and the counter is reset. At the same
time, the values set in the compare register buffer are loaded to the compare data register if SELCRBx is set
to "1".
The cou nter continues counting up regardless of which interrupt has occurred. In the case of a comparison B
interrupt, the counter starts counting beginning with 0.
When both the timer RUN/STOP control bit (PRUNx) and the timer reset bit (PRESETx) are set to "1" at the
same time, the timer starts counting after resetting the counter.
PRUNx
PRESETx
CRxA
CRxB
Input clock
TCx
Reset Comparison A
interrupt Reset and
Comparison B
interrupt
Comparison A
interrupt Reset and
Comparison B
interrupt
0x2
01
234501234501
0x5
Figur e 4.2 Basic Operation Timing of Counter
Reading counter data
The cou nter data can be read out from the following addresses shown below at any time:
Timer 0 counter dat a: TC 0[15:0] (D[F:0]) / 16-bit timer 0 counter data register (0x48184)
Timer 1 counter dat a: TC 1[15:0] (D[F:0]) / 16-bit timer 1 counter data register (0x4818C)
Timer 2 counter dat a: TC 2[15:0] (D[F:0]) / 16-bit timer 2 counter data register (0x48194)
Timer 3 counter dat a: TC 3[15:0] (D[F :0 ]) / 16-b it time r 3 coun te r data re gi ste r (0x4 81 9C )
Timer 4 counter dat a: TC 4[15:0] (D[F:0]) / 16-bit timer 4 counter data register (0x481A4)
Timer 5 counter dat a: TC 5[15:0] (D[F:0]) / 16-bit timer 5 counter data register (0x481AC)
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS
S1C33L03 FUNCTION PART EPSON B-III-4-7
A-1
B-III
16TM
Controllin g Clock Output
The tim ers can generate a TMx signal using the comparison match signals from the counter.
Setting the signal active level
By default, an active high signal (normal low) is generated. This logic can be inverted using the OUTINVx
bit.
When "1" is written to the OUTINVx bit, the timer generates an active low (normal high) signal.
Timer 0 clock output inversion: OUTINV0 (D4) / 16-bit timer 0 control register (0x48186)
Timer 1 clock output inversion: OUTINV1 (D4) / 16-bit timer 1 control register (0x4818E)
Timer 2 clock output inversion: OUTINV2 (D4) / 16-bit timer 2 control register (0x48196)
Timer 3 clock output inversion: OUTINV3 (D4) / 16-bit timer 3 control register (0x4819E)
Timer 4 clock output inversion: OUTINV4 (D4) / 16-bit timer 4 control register (0x481A6)
Timer 5 clock output i nversion: OUTINV5 (D4) / 16-bit timer 5 control register (0x481AE)
See Figure 4.3 for the waveforms.
Setting the output port
The TMx signa l generated here can be output from the clock output pins (see Table 4.1), enabling a
progr ammable clock to be supplied to external devices.
Aft er a cold start, the output pins are set for the I/O ports and set in input mode. The pins go into high-
impedance status.
When the pin function is switched to the timer output, the pin goes low if OUTINVx is set to "0" or goes high
if OUTINVx is set to "1".
Starting clock output
To output the TMx clock, write "1" to the clock output control bit PTMx. Clock output is stopped by writing
"0" to PTMx and goes to the off level according to the OUTINVx setting (low when OUTINVx = "0" or high
when OUTINVx = "1") .
Timer 0 clock output control: PTM0 (D2) / 16-bit timer 0 control register (0x48186)
Timer 1 clock output control: PTM1 (D2) / 16-bit timer 1 control register (0x4818E)
Timer 2 clock output control: PTM2 (D2) / 16-bit timer 2 control register (0x48196)
Timer 3 clock output control: PTM3 (D2) / 16-bit timer 3 control register (0x4819E)
Timer 4 clock output control: PTM4 (D2) / 16-bit timer 4 control register (0x481A6)
Timer 5 clock output control: PTM5 (D2) / 16-bit timer 5 control register (0x481AE)
Figure 4.3 shows the waveform of the output signal.
Input clock
PRUNx
CRxA
CRxB
Counter value
Comparison match A signal
Comparison match B signal
PTMx
TMx output (when OUTINVx = "0")
TMx output (when OUTINVx = "1")
3
5
0 1234501234501234501
Figur e 4.3 Waveform of 16-Bit Programmable Timer Output
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS
B-III-4-8 EPSON S1C33L03 FUNCTION PART
When OUTI NVx = "0" (active high):
The tim er outputs a low level until the counter becomes equal to the comparison data A set in the CRxA
register. When the counter is incremented to the next value from the comparison data A, the output pin goes
high and a compa ris on A inte rru pt o ccu rs. Whe n th e coun te r becomes equal to the comparison data B set in
the CRxB register, the counter is reset and the output pin goes low. At the same time a comparison B
inte rrupt o ccu rs.
When OUTI NVx = "1" (active low):
The tim er outputs a high level until the counter becomes equal to the comparison data A set in the CRxA
register. When the counter is incremented to the next value from the comparison data A, the output pin goes
low and a comparison A interrupt occurs. When the counter becomes equal to the comparison data B set in
the CRxB register, the counter is reset and the output pin goes high. At the same time a comparison B
inte rrupt o ccu rs.
Setting clock output fine mode
By default (after an initial reset), the clock output signal changes at the rising edge of the input clock when
CR xA [15:0] becomes e qual to TCx[15:0].
In fine mode, the output signal changes according to CRxA[0] when CRxA[15:1] becomes equal to
TCx[14:0].
When CRxA[0] is "0", the output signal changes at the rising edge of the input clock.
When CRxA[0] is "1", the output signal changes at the falling edge of the input clock a half cycle from the
default setting.
Exampl e) CR xA = 3, CRxB = 5
Input clock
Counter value
Comparison match A signal
Comparison match B signal
TMx output (when OUTINVx = "0")
TMx output (when OUTINVx = "1")
01234501234501
Figur e 4.4 Clock Output in Fine Mode
As shown in the figure above, in fine mode the output clock duty ratio can be adjusted in the half cycle of the
input clock. However, when the CRxA value is "0", the timer outputs a pulse with a 1-cycle width as the
input clock, the same as the default setting.
In fine mode, the maximum value of CRxB is 215 - 1 = 32,767 and the range of CRxA that can be set is 0 to (2
× CRxB - 1).
The fine mode is set by the following registers:
Timer 0 fine mode select ion: SELFM0 (D6) / 16-bit timer 0 control register (0x48186)
Timer 1 fine mode select ion: SELFM1 (D6) / 16-bit timer 1 control register (0x4818E)
Timer 2 fine mode selection: SELFM2 (D6) / 16-bit timer 2 control register (0x48196)
Timer 3 fine mode select ion: SELFM3 (D6) / 16-bit timer 3 control register (0x4819E)
Timer 4 fine mode select ion: SELFM4 (D6) / 16-bit timer 4 control register (0x481A6)
Timer 5 fine mode select ion: SELFM5 (D6) / 16-bit timer 5 control register (0x481AE)
When "1" is written to the SELFMx bit, fine mode is set. At initial reset, the fine mode is disabled.
Precautions
1) If a same value is set to the comparison data A and B registers, a hazard may be generated in the output
signal. Therefore, do not set the comparison registers as A = B.
There is no problem when the interru pt fu nc tio n o nly is used.
2) When using the out put clock, set the comparison data registers as A ≥ 0 and B ≥ 1. Th e mini mum sett in gs
are A = 0 and B = 1. In this case, the timer output clock cycle is the input clock × 1/2.
3) When the comparison data registers are set as A > B, no comparison A signal is generated. In this case,
the output signal is fixed at the off level.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS
S1C33L03 FUNCTION PART EPSON B-III-4-9
A-1
B-III
16TM
16-Bit Programmable Timer Interrupts and DMA
The 16- bit programmable timer has a function for generating an interrupt using the comparison match A and B
states.
The timing at wh ich an interrupt is generated is shown in Figure 4.2 in the preceding section.
Control registers of the interrupt controller
Table 4.4 shows t he control registers of the interrupt controller provided for each timer.
Table 4.4 Control Registers of Interrupt Controller
Interrupt factor Interrupt factor flag Interrupt enable register Interrupt priority register
Timer 0 comparison A F16TC0 (D3/0x40282) E16TC0 (D3/0x40272) P16T0[2:0] (D[2:0]/0x40266)
Timer 0 comparison B F16TU0 (D2/0x40282) E16TU0 (D2/0x40272)
Timer 1 comparison A F16TC1 (D7/0x40282) E16TC1 (D7/0x40272) P16T1[2:0] (D[6:4]/0x40266)
Timer 1 comparison B F16TU1 (D6/0x40282) E16TU1 (D6/0x40272)
Timer 2 comparison A F16TC2 (D3/0x40283) E16TC2 (D3/0x40273) P16T2[2:0] (D[2:0]/0x40267)
Timer 2 comparison B F16TU2 (D2/0x40283) E16TU2 (D2/0x40273)
Timer 3 comparison A F16TC3 (D7/0x40283) E16TC3 (D7/0x40273) P16T3[2:0] (D[6:4]/0x40267)
Timer 3 comparison B F16TU3 (D6/0x40283) E16TU3 (D6/0x40273)
Timer 4 comparison A F16TC4 (D3/0x40284) E16TC4 (D3/0x40274) P16T4[2:0] (D[2:0]/0x40268)
Timer 4 comparison B F16TU4 (D2/0x40284) E16TU4 (D2/0x40274)
Timer 5 comparison A F16TC5 (D7/0x40284) E16TC5 (D7/0x40274) P16T5[2:0] (D[6:4]/0x40268)
Timer 5 comparison B F16TU5 (D6/0x40284) E16TU5 (D6/0x40274)
When a comparison match state occurs in the timer, the corresponding interrupt factor flag is set to "1".
If the interrupt enable register bit corresponding to that interrupt factor flag has been set to "1", an interrupt
request is generated.
An interrupt caused by a timer can be disabled by leaving the interrupt enable register bit for that timer set to
"0". The interrupt factor flag is always set to "1" by the timer's comparison match state, regardless of how the
interrupt enable register is set (even when set to "0").
The interrupt priority register sets an interrupt priority level (0 to 7) for each timer. Priorities within a timer
block are such that timers of smaller numbers have a higher priority. Prio riti es betwee n in te rrupt ty pe s are
such that the comparison B interrupt has priority over the comparison A interrupt. An interrupt request to the
CP U is accepted only wh en no oth er interr upt request of a higher prior ity has been generated.
It is only when the PSR's IE bit = "1" (interrupts enabled) and the set value of the IL is smaller than the timer
interrupt level set by the interrupt priority register, that a timer interrupt request is actually accepted by the
CPU.
For details on these interrupt control registers, as well as the device operation when an interrupt has occurred,
refer to "ITC (Interrupt Controller)".
Int e ll ig e nt D M A
The interrupt factor of each timer can also invoke intelligent DMA (IDMA). This allows memory-to-memory
DMA transfers to be performed cyclically.
The following shows the IDMA channel numbers set for each interrupt factor of timer:
IDMA Ch. IDMA Ch.
Timer 0 com parison B: 0x07 Timer 0 compar ison A: 0x08
Timer 1 com parison B: 0x09 Timer 1 compar ison A: 0x0A
Timer 2 com parison B: 0x0B Timer 2 com parison A: 0x0C
Timer 3 com parison B: 0x0D Time r 3 com parison A: 0x0E
Timer 4 com parison B: 0x 0F Ti m er 4 com parison A: 0x10
Timer 5 com parison B: 0x11 Timer 5 compar ison A: 0x12
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS
B-III-4-10 EPSON S1C33L03 FUNCTION PART
For IDMA to be invoked, the IDMA request and IDMA enable bits shown in Table 4.5 must be set to "1" in
advance. Transfer conditions, etc. must also be set on the IDMA side in advance.
Table 4.5 Control Bits fo r IDMA Transfe r
Interrupt factor IDMA request bit IDMA enable bit
Timer 0 comparison A R16TC0(D7/0x40290) DE16TC0(D7/0x40294)
Timer 0 comparison B R16TU0(D6/0x40290) DE16TU0(D6/0x40294)
Timer 1 comparison A R16TC1(D1/0x40291) DE16TC1(D1/0x40295)
Timer 1 comparison B R16TU1(D0/0x40291) DE16TU1(D0/0x40295)
Timer 2 comparison A R16TC2(D3/0x40291) DE16TC2(D3/0x40295)
Timer 2 comparison B R16TU2(D2/0x40291) DE16TU2(D2/0x40295)
Timer 3 comparison A R16TC3(D5/0x40291) DE16TC3(D5/0x40295)
Timer 3 comparison B R16TU 3(D4/0x4029 1)DE16TU3(D4/0x40295)
Timer 4 comparison A R16TC4(D7/0x40291) DE16TC4(D7/0x40295)
Timer 4 comparison B R16TU4(D6/0x40291) DE16TU4(D6/0x40295)
Timer 5 comparison A R16TC5(D1/0x40292) DE16TC5(D1/0x40296)
Timer 5 comparison B R16TU5(D0/0x40292) DE16TU5(D0/0x40296)
If the IDMA request and enable bits are set to "1", IDMA is invoked through generation of an interrupt factor.
No interrupt request is generated at that point. An interrupt request is generated after the DMA transfer is
completed. The registers can also be set so as not to generate an interrupt, with only a DMA transfer
performed.
For details on IDMA transfers and interrupt control upon completion of IDMA transfer, refer to "IDMA
(Intelligent DMA)".
Hig h -speed DM A
The interrupt factor of each timer can also invoke high-speed DMA (HSDMA).
The f ol lowing shows the HSDMA cha nnel number and trigger set-up bit corresponding to each timer:
Table 4.6 HSDMA Trigger Set-up Bits
Interrupt factor HSDMA
Ch. Trigger set-up bits
Timer 0 comparison A 0 HSD0S[3:0] (D[3:0]) / HSDMA Ch.0/1 trigger set-up register (0x40298) = "0111"
Timer 0 comparison B 0 HSD0S[3:0] (D[3:0]) / HSDMA Ch.0/1 trigger set-up register (0x40298) = "0110"
Timer 1 comparison A 1 HSD1S[3:0] (D[7:4]) / HSDMA Ch.0/1 trigger set-up register (0x40298) = "0111"
Timer 1 comparison B 1 HSD1S[3:0] (D[7:4]) / HSDMA Ch.0/1 trigger set-up register (0x40298) = "0110"
Timer 2 comparison A 2 HSD2S[3:0] (D[3:0]) / HSDMA Ch.2/3 trigger set-up register (0x40299) = "0111"
Timer 2 comparison B 2 HSD2S[3:0] (D[3:0]) / HSDMA Ch.2/3 trigger set-up register (0x40299) = "0110"
Timer 3 comparison A 3 HSD3S[3:0] (D[7:4]) / HSDMA Ch.2/3 trigger set-up register (0x40299) = "0111"
Timer 3 comparison B 3 HSD3S[3:0] (D[7:4]) / HSDMA Ch.2/3 trigger set-up register (0x40299) = "0110"
Timer 4 comparison A 0 HSD0S[3:0] (D[3:0]) / HSDMA Ch.0/1 trigger set-up register (0x40298) = "1001"
2HSD2S[3:0] (D[3:0]) / HSDMA Ch.2/3 trigger set-up register (0x40299) = "1001"
Timer 4 comparison B 0 HSD0S[3:0] (D[3:0]) / HSDMA Ch.0/1 trigger set-up register (0x40298) = "1000"
2HSD2S[3:0] (D[3:0]) / HSDMA Ch.2/3 trigger set-up register (0x40299) = "1000"
Timer 5 comparison A 1 HSD1S[3:0] (D[7:4]) / HSDMA Ch.0/1 trigger set-up register (0x40298) = "1001"
3HSD3S[3:0] (D[7:4]) / HSDMA Ch.2/3 trigger set-up register (0x40299) = "1001"
Timer 5 comparison B 1 HSD1S[3:0] (D[7:4]) / HSDMA Ch.0/1 trigger set-up register (0x40298) = "1000"
3HSD3S[3:0] (D[7:4]) / HSDMA Ch.2/3 trigger set-up register (0x40299) = "1000"
For HSDMA t o be invok ed, a 16-bit timer interrupt factor should be selected using the trigger set-up bits in
advance. Transfer conditions, etc. must also be set on the HSDMA side.
If a 16-bit timer is selected as the HSDMA trigger, the HSDMA channel is invoked through generation of the
inte rru pt facto r.
For details on HSDMA transfer, refer to "HSDMA (High-Speed DMA)".
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS
S1C33L03 FUNCTION PART EPSON B-III-4-11
A-1
B-III
16TM
Trap vectors
The trap vector addresses for each default interrupt factor are set as shown below:
Timer 0 com parison B: 0x0C00078
Tim er 0 compar ison A: 0x0C0007 C
Timer 1 com parison B: 0x0C00088
Tim er 1 compar ison A: 0x0C0008 C
Timer 2 com parison B: 0x0C00098
Tim er 2 compar ison A: 0x0C0009 C
Timer 3 com parison B: 0x0C000A8
Tim er 3 compar ison A: 0x0C 000AC
Timer 4 com parison B: 0x0C000B8
Tim er 4 compar ison A: 0x0C000BC
Timer 5 com parison B: 0x0C000C8
Tim er 5 compar ison A: 0x0C000CC
The bas e address of the trap table can be changed using the TTBR register (0x48134 to 0x48137).
Precaution
Serial interface Ch.2 and Ch.3 share interrupt signals with the 16-bit timers. A register setting determined
which is used. The initial setting is for use of the 16-bit timers. Refer to Section III-8, "Serial Interface", for
details of the settings.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS
B-III-4-12 EPSON S1C33L03 FUNCTION PART
I/O Memory of 16-Bit Programmable Timers
Table 4.7 shows t he control bits of the 16-bit programmable timers.
For details on the I/O memory of the prescaler used to set a clock, refer to "Prescaler".
Table 4.7 Control Bits of 16-Bit Programmable Timer
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
0 to 7
0 to 7
–
–
P16T12
P16T11
P16T10
–
P16T02
P16T01
P16T00
D7
D6
D5
D4
D3
D2
D1
D0
reserved
16-bit timer 1 interrupt level
reserved
16-bit timer 0 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040266
(B)
16-bit timer 0/1
interrupt
priority register
–
0 to 7
0 to 7
–
–
P16T32
P16T31
P16T30
–
P16T22
P16T21
P16T20
D7
D6
D5
D4
D3
D2
D1
D0
reserved
16-bit timer 3 interrupt level
reserved
16-bit timer 2 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040267
(B)
16-bit timer 2/3
interrupt
priority register
–
0 to 7
0 to 7
–
–
P16T52
P16T51
P16T50
–
P16T42
P16T41
P16T40
D7
D6
D5
D4
D3
D2
D1
D0
reserved
16-bit timer 5 interrupt level
reserved
16-bit timer 4 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040268
(B)
16-bit timer 4/5
interrupt
priority register
E16TC1
E16TU1
–
E16TC0
E16TU0
–
D7
D6
D5–4
D3
D2
D1–0
16-bit timer 1 comparison A
16-bit timer 1 comparison B
reserved
16-bit timer 0 comparison A
16-bit timer 0 comparison B
reserved
0
0
–
0
0
–
R/W
R/W
–
R/W
R/W
–
0 when being read.
0 when being read.
0040272
(B) 1 Enabled 0 Disabled
16-bit timer 0/1
interrupt
enable register –
1 Enabled 0 Disabled
–
E16TC3
E16TU3
–
E16TC2
E16TU2
–
D7
D6
D5–4
D3
D2
D1–0
16-bit timer 3 comparison A
16-bit timer 3 comparison B
reserved
16-bit timer 2 comparison A
16-bit timer 2 comparison B
reserved
0
0
–
0
0
–
R/W
R/W
–
R/W
R/W
–
0 when being read.
0 when being read.
0040273
(B) 1 Enabled 0 Disabled
16-bit timer 2/3
interrupt
enable register –
1 Enabled 0 Disabled
–
E16TC5
E16TU5
–
E16TC4
E16TU4
–
D7
D6
D5–4
D3
D2
D1–0
16-bit timer 5 comparison A
16-bit timer 5 comparison B
reserved
16-bit timer 4 comparison A
16-bit timer 4 comparison B
reserved
0
0
–
0
0
–
R/W
R/W
–
R/W
R/W
–
0 when being read.
0 when being read.
0040274
(B) 1 Enabled 0 Disabled
16-bit timer 4/5
interrupt
enable register –
1 Enabled 0 Disabled
–
F16TC1
F16TU1
–
F16TC0
F16TU0
–
D7
D6
D5–4
D3
D2
D1–0
16-bit timer 1 comparison A
16-bit timer 1 comparison B
reserved
16-bit timer 0 comparison A
16-bit timer 0 comparison B
reserved
X
X
–
X
X
–
R/W
R/W
–
R/W
R/W
–
0 when being read.
0 when being read.
0040282
(B) 1 Factor is
generated 0 No factor is
generated
16-bit timer 0/1
interrupt factor
flag register –
1 Factor is
generated 0 No factor is
generated
–
F16TC3
F16TU3
–
F16TC2
F16TU2
–
D7
D6
D5–4
D3
D2
D1–0
16-bit timer 3 comparison A
16-bit timer 3 comparison B
reserved
16-bit timer 2 comparison A
16-bit timer 2 comparison B
reserved
X
X
–
X
X
–
R/W
R/W
–
R/W
R/W
–
0 when being read.
0 when being read.
0040283
(B) 1 Factor is
generated 0 No factor is
generated
16-bit timer 2/3
interrupt factor
flag register –
1 Factor is
generated 0 No factor is
generated
–
F16TC5
F16TU5
–
F16TC4
F16TU4
–
D7
D6
D5–4
D3
D2
D1–0
16-bit timer 5 comparison A
16-bit timer 5 comparison B
reserved
16-bit timer 4 comparison A
16-bit timer 4 comparison B
reserved
X
X
–
X
X
–
R/W
R/W
–
R/W
R/W
–
0 when being read.
0 when being read.
0040284
(B) 1 Factor is
generated 0 No factor is
generated
16-bit timer 4/5
interrupt factor
flag register –
1 Factor is
generated 0 No factor is
generated
–
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS
S1C33L03 FUNCTION PART EPSON B-III-4-13
A-1
B-III
16TM
NameAddressRegister name Bit Function Setting Init. R/W Remarks
R16TC0
R16TU0
RHDM1
RHDM0
RP3
RP2
RP1
RP0
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 0 comparison A
16-bit timer 0 comparison B
High-speed DMA Ch.1
High-speed DMA Ch.0
Port input 3
Port input 2
Port input 1
Port input 0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0040290
(B) 1 IDMA
request 0 Interrupt
request
Port input 0–3,
high-speed
DMA Ch. 0/1,
16-bit timer 0
IDMA request
register
R16TC4
R16TU4
R16TC3
R16TU3
R16TC2
R16TU2
R16TC1
R16TU1
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 4 comparison A
16-bit timer 4 comparison B
16-bit timer 3 comparison A
16-bit timer 3 comparison B
16-bit timer 2 comparison A
16-bit timer 2 comparison B
16-bit timer 1 comparison A
16-bit timer 1 comparison B
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0040291
(B) 1 IDMA
request 0 Interrupt
request
16-bit timer 1–4
IDMA request
register
RSTX0
RSRX0
R8TU3
R8TU2
R8TU1
R8TU0
R16TC5
R16TU5
D7
D6
D5
D4
D3
D2
D1
D0
SIF Ch.0 transmit buffer empty
SIF Ch.0 receive buffer full
8-bit timer 3 underflow
8-bit timer 2 underflow
8-bit timer 1 underflow
8-bit timer 0 underflow
16-bit timer 5 comparison A
16-bit timer 5 comparison B
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0040292
(B) 1 IDMA
request 0 Interrupt
request
16-bit timer 5,
8-bit timer,
serial I/F Ch.0
IDMA request
register
DE16TC0
DE16TU0
DEHDM1
DEHDM0
DEP3
DEP2
DEP1
DEP0
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 0 comparison A
16-bit timer 0 comparison B
High-speed DMA Ch.1
High-speed DMA Ch.0
Port input 3
Port input 2
Port input 1
Port input 0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0040294
(B) 1 IDMA
enabled 0 IDMA
disabled
Port input 0–3,
high-speed
DMA Ch. 0/1,
16-bit timer 0
IDMA enable
register
DE16TC4
DE16TU4
DE16TC3
DE16TU3
DE16TC2
DE16TU2
DE16TC1
DE16TU1
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 4 comparison A
16-bit timer 4 comparison B
16-bit timer 3 comparison A
16-bit timer 3 comparison B
16-bit timer 2 comparison A
16-bit timer 2 comparison B
16-bit timer 1 comparison A
16-bit timer 1 comparison B
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0040295
(B) 1 IDMA
enabled 0 IDMA
disabled
16-bit timer 1–4
IDMA enable
register
DESTX0
DESRX0
DE8TU3
DE8TU2
DE8TU1
DE8TU0
DE16TC5
DE16TU5
D7
D6
D5
D4
D3
D2
D1
D0
SIF Ch.0 transmit buffer empty
SIF Ch.0 receive buffer full
8-bit timer 3 underflow
8-bit timer 2 underflow
8-bit timer 1 underflow
8-bit timer 0 underflow
16-bit timer 5 comparison A
16-bit timer 5 comparison B
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0040296
(B) 1 IDMA
enabled 0 IDMA
disabled
16-bit timer 5,
8-bit timer,
serial I/F Ch.0
IDMA enable
register
–
CFP16
CFP15
CFP14
CFP13
CFP12
CFP11
CFP10
D7
D6
D5
D4
D3
D2
D1
D0
reserved
P16 function selection
P15 function selection
P14 function selection
P13 function selection
P12 function selection
P11 function selection
P10 function selection
–
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.
Extended functions
(0x402DF)
00402D4
(B) 1 EXCL5
#DMAEND1
0 P16
1 EXCL4
#DMAEND0
0 P15
1 EXCL3
T8UF3 0 P13
1 EXCL2
T8UF2 0 P12
1 EXCL1
T8UF1 0 P11
1 EXCL0
T8UF0 0 P10
–P1 function
select register
1 FOSC1 0 P14
–
IOC16
IOC15
IOC14
IOC13
IOC12
IOC11
IOC10
D7
D6
D5
D4
D3
D2
D1
D0
reserved
P16 I/O control
P15 I/O control
P14 I/O control
P13 I/O control
P12 I/O control
P11 I/O control
P10 I/O control
–
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.
This register
indicates the values
of the I/O control
signals of the ports
when it is read. (See
detailed explanation.)
00402D6
(B) 1Output 0Input
–P1 I/O control
register
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS
B-III-4-14 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
CFP27
CFP26
CFP25
CFP24
CFP23
CFP22
CFP21
CFP20
D7
D6
D5
D4
D3
D2
D1
D0
P27 function selection
P26 function selection
P25 function selection
P24 function selection
P23 function selection
P22 function selection
P21 function selection
P20 function selection
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W Ext. func.(0x402DF)
00402D8
(B) 1 TM5 0 P27
1 TM4 0 P26
1 TM3 0 P25
1 TM2 0 P24
1 TM1 0 P23
1 TM0 0 P22
1 #DWE 0 P21
1 #DRD 0 P20
P2 function
select register
CFEX7
CFEX6
CFEX5
CFEX4
CFEX3
CFEX2
CFEX1
CFEX0
D7
D6
D5
D4
D3
D2
D1
D0
P07 port extended function
P06 port extended function
P05 port extended function
P04 port extended function
P31 port extended function
P21 port extended function
P10, P11, P13 port extended
function
P12, P14 port extended function
0
0
0
0
0
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00402DF
(B)
Port function
extension
register
1
#DMAEND3
0 P07, etc.
1
#DMAACK3
0 P06, etc.
1
#DMAEND2
0 P05, etc.
1
#DMAACK2
0 P04, etc.
1 #GARD 0 P31, etc.
1 #GAAS 0 P21, etc.
1 DST0
DST1
DPC0
0 P10, etc.
P11, etc.
P13, etc.
1 DST2
DCLK 0 P12, etc.
P14, etc.
0 to 65535CR0A15
CR0A14
CR0A13
CR0A12
CR0A11
CR0A10
CR0A9
CR0A8
CR0A7
CR0A6
CR0A5
CR0A4
CR0A3
CR0A2
CR0A1
CR0A0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 0 comparison data A
CR0A15 = MSB
CR0A0 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048180
(HW)
16-bit timer 0
comparison
data A set-up
register
0 to 65535CR0B15
CR0B14
CR0B13
CR0B12
CR0B11
CR0B10
CR0B9
CR0B8
CR0B7
CR0B6
CR0B5
CR0B4
CR0B3
CR0B2
CR0B1
CR0B0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 0 comparison data B
CR0B15 = MSB
CR0B0 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048182
(HW)
16-bit timer 0
comparison
data B set-up
register
0 to 65535TC015
TC014
TC013
TC012
TC011
TC010
TC09
TC08
TC07
TC06
TC05
TC04
TC03
TC02
TC01
TC00
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 0 counter data
TC015 = MSB
TC00 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R0048184
(HW)
16-bit timer 0
counter data
register
–
SELFM0
SELCRB0
OUTINV0
CKSL0
PTM0
PRESET0
PRUN0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
16-bit timer 0 fine mode selection
16-bit timer 0 comparison buffer
16-bit timer 0 output inversion
16-bit timer 0 input clock selection
16-bit timer 0 clock output control
16-bit timer 0 reset
16-bit timer 0 Run/Stop control
0
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
W
R/W
0 when being read.
0 when being read.
0048186
(B) –
1 Enabled 0 Disabled
1 Fine mode 0 Normal
1 Invert 0 Normal
1
External clock
0
Internal clock
1 On 0 Off
1 Reset 0 Invalid
1 Run 0 Stop
16-bit timer 0
control register
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS
S1C33L03 FUNCTION PART EPSON B-III-4-15
A-1
B-III
16TM
NameAddressRegister name Bit Function Setting Init. R/W Remarks
0 to 65535CR1A15
CR1A14
CR1A13
CR1A12
CR1A11
CR1A10
CR1A9
CR1A8
CR1A7
CR1A6
CR1A5
CR1A4
CR1A3
CR1A2
CR1A1
CR1A0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 1 comparison data A
CR1A15 = MSB
CR1A0 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048188
(HW)
16-bit timer 1
comparison
data A set-up
register
0 to 65535CR1B15
CR1B14
CR1B13
CR1B12
CR1B11
CR1B10
CR1B9
CR1B8
CR1B7
CR1B6
CR1B5
CR1B4
CR1B3
CR1B2
CR1B1
CR1B0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 1 comparison data B
CR1B15 = MSB
CR1B0 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W004818A
(HW)
16-bit timer 1
comparison
data B set-up
register
0 to 65535TC115
TC114
TC113
TC112
TC111
TC110
TC19
TC18
TC17
TC16
TC15
TC14
TC13
TC12
TC11
TC10
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 1 counter data
TC115 = MSB
TC10 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R004818C
(HW)
16-bit timer 1
counter data
register
–
SELFM1
SELCRB1
OUTINV1
CKSL1
PTM1
PRESET1
PRUN1
D7
D6
D5
D4
D3
D2
D1
D0
reserved
16-bit timer 1 fine mode selection
16-bit timer 1 comparison buffer
16-bit timer 1 output inversion
16-bit timer 1 input clock selection
16-bit timer 1 clock output control
16-bit timer 1 reset
16-bit timer 1 Run/Stop control
0
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
W
R/W
0 when being read.
0 when being read.
004818E
(B) –
1 Enabled 0 Disabled
1 Fine mode 0 Normal
1 Invert 0 Normal
1
External clock
0
Internal clock
1 On 0 Off
1 Reset 0 Invalid
1 Run 0 Stop
16-bit timer 1
control register
0 to 65535CR2A15
CR2A14
CR2A13
CR2A12
CR2A11
CR2A10
CR2A9
CR2A8
CR2A7
CR2A6
CR2A5
CR2A4
CR2A3
CR2A2
CR2A1
CR2A0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 2 comparison data A
CR2A15 = MSB
CR2A0 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048190
(HW)
16-bit timer 2
comparison
data A set-up
register
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS
B-III-4-16 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
0 to 65535CR2B15
CR2B14
CR2B13
CR2B12
CR2B11
CR2B10
CR2B9
CR2B8
CR2B7
CR2B6
CR2B5
CR2B4
CR2B3
CR2B2
CR2B1
CR2B0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 2 comparison data B
CR2B15 = MSB
CR2B0 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048192
(HW)
16-bit timer 2
comparison
data B set-up
register
0 to 65535TC215
TC214
TC213
TC212
TC211
TC210
TC29
TC28
TC27
TC26
TC25
TC24
TC23
TC22
TC21
TC20
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 2 counter data
TC215 = MSB
TC20 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R0048194
(HW)
16-bit timer 2
counter data
register
–
SELFM2
SELCRB2
OUTINV2
CKSL2
PTM2
PRESET2
PRUN2
D7
D6
D5
D4
D3
D2
D1
D0
reserved
16-bit timer 2 fine mode selection
16-bit timer 2 comparison buffer
16-bit timer 2 output inversion
16-bit timer 2 input clock selection
16-bit timer 2 clock output control
16-bit timer 2 reset
16-bit timer 2 Run/Stop control
0
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
W
R/W
0 when being read.
0 when being read.
0048196
(B) –
1 Enabled 0 Disabled
1 Fine mode 0 Normal
1 Invert 0 Normal
1
External clock
0
Internal clock
1 On 0 Off
1 Reset 0 Invalid
1 Run 0 Stop
16-bit timer 2
control register
0 to 65535CR3A15
CR3A14
CR3A13
CR3A12
CR3A11
CR3A10
CR3A9
CR3A8
CR3A7
CR3A6
CR3A5
CR3A4
CR3A3
CR3A2
CR3A1
CR3A0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 3 comparison data A
CR3A15 = MSB
CR3A0 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048198
(HW)
16-bit timer 3
comparison
data A set-up
register
0 to 65535CR3B15
CR3B14
CR3B13
CR3B12
CR3B11
CR3B10
CR3B9
CR3B8
CR3B7
CR3B6
CR3B5
CR3B4
CR3B3
CR3B2
CR3B1
CR3B0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 3 comparison data B
CR3B15 = MSB
CR3B0 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W004819A
(HW)
16-bit timer 3
comparison
data B set-up
register
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS
S1C33L03 FUNCTION PART EPSON B-III-4-17
A-1
B-III
16TM
NameAddressRegister name Bit Function Setting Init. R/W Remarks
0 to 65535TC315
TC314
TC313
TC312
TC311
TC310
TC39
TC38
TC37
TC36
TC35
TC34
TC33
TC32
TC31
TC30
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 3 counter data
TC315 = MSB
TC30 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R004819C
(HW)
16-bit timer 3
counter data
register
–
SELFM3
SELCRB3
OUTINV3
CKSL3
PTM3
PRESET3
PRUN3
D7
D6
D5
D4
D3
D2
D1
D0
reserved
16-bit timer 3 fine mode selection
16-bit timer 3 comparison buffer
16-bit timer 3 output inversion
16-bit timer 3 input clock selection
16-bit timer 3 clock output control
16-bit timer 3 reset
16-bit timer 3 Run/Stop control
0
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
W
R/W
0 when being read.
0 when being read.
004819E
(B) –
1 Enabled 0 Disabled
1 Fine mode 0 Normal
1 Invert 0 Normal
1
External clock
0
Internal clock
1 On 0 Off
1 Reset 0 Invalid
1 Run 0 Stop
16-bit timer 3
control register
0 to 65535CR4A15
CR4A14
CR4A13
CR4A12
CR4A11
CR4A10
CR4A9
CR4A8
CR4A7
CR4A6
CR4A5
CR4A4
CR4A3
CR4A2
CR4A1
CR4A0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 4 comparison data A
CR4A15 = MSB
CR4A0 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W00481A0
(HW)
16-bit timer 4
comparison
data A set-up
register
0 to 65535CR4B15
CR4B14
CR4B13
CR4B12
CR4B11
CR4B10
CR4B9
CR4B8
CR4B7
CR4B6
CR4B5
CR4B4
CR4B3
CR4B2
CR4B1
CR4B0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 4 comparison data B
CR4B15 = MSB
CR4B0 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W00481A2
(HW)
16-bit timer 4
comparison
data B set-up
register
0 to 65535TC415
TC414
TC413
TC412
TC411
TC410
TC49
TC48
TC47
TC46
TC45
TC44
TC43
TC42
TC41
TC40
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 4 counter data
TC415 = MSB
TC40 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R00481A4
(HW)
16-bit timer 4
counter data
register
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS
B-III-4-18 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
SELFM4
SELCRB4
OUTINV4
CKSL4
PTM4
PRESET4
PRUN4
D7
D6
D5
D4
D3
D2
D1
D0
reserved
16-bit timer 4 fine mode selection
16-bit timer 4 comparison buffer
16-bit timer 4 output inversion
16-bit timer 4 input clock selection
16-bit timer 4 clock output control
16-bit timer 4 reset
16-bit timer 4 Run/Stop control
0
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
W
R/W
0 when being read.
0 when being read.
00481A6
(B) –
1 Enabled 0 Disabled
1 Fine mode 0 Normal
1 Invert 0 Normal
1
External clock
0
Internal clock
1 On 0 Off
1 Reset 0 Invalid
1 Run 0 Stop
16-bit timer 4
control register
0 to 65535CR5A15
CR5A14
CR5A13
CR5A12
CR5A11
CR5A10
CR5A9
CR5A8
CR5A7
CR5A6
CR5A5
CR5A4
CR5A3
CR5A2
CR5A1
CR5A0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 5 comparison data A
CR5A15 = MSB
CR5A0 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W00481A8
(HW)
16-bit timer 5
comparison
data A set-up
register
0 to 65535CR5B15
CR5B14
CR5B13
CR5B12
CR5B11
CR5B10
CR5B9
CR5B8
CR5B7
CR5B6
CR5B5
CR5B4
CR5B3
CR5B2
CR5B1
CR5B0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 5 comparison data B
CR5B15 = MSB
CR5B0 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W00481AA
(HW)
16-bit timer 5
comparison
data B set-up
register
0 to 65535TC515
TC514
TC513
TC512
TC511
TC510
TC59
TC58
TC57
TC56
TC55
TC54
TC53
TC52
TC51
TC50
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 5 counter data
TC515 = MSB
TC50 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R00481AC
(HW)
16-bit timer 5
counter data
register
–
SELFM5
SELCRB5
OUTINV5
CKSL5
PTM5
PRESET5
PRUN5
D7
D6
D5
D4
D3
D2
D1
D0
reserved
16-bit timer 5 fine mode selection
16-bit timer 5 comparison buffer
16-bit timer 5 output inversion
16-bit timer 5 input clock selection
16-bit timer 5 clock output control
16-bit timer 5 reset
16-bit timer 5 Run/Stop control
0
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
W
R/W
0 when being read.
0 when being read.
00481AE
(B) –
1 Enabled 0 Disabled
1 Fine mode 0 Normal
1 Invert 0 Normal
1
External clock
0
Internal clock
1 On 0 Off
1 Reset 0 Invalid
1 Run 0 Stop
16-bit timer 5
control register
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS
S1C33L03 FUNCTION PART EPSON B-III-4-19
A-1
B-III
16TM
CFP16–CFP10: P1[ 6:0 ] p in func tio n select io n (D[6:0 ]) / P 1 fu nctio n sele ct regist er (0 x4 0 2D4 )
Selects the pin to be used for input of an external count clock to the timer.
Write "1": Clo ck input pin
Write "0": I/ O port pin
Read: Valid
Select clock input pins for the timers that are used as an event counter from among P10 through P16, by writing
"1" to CFP10–CFP16. For the relationship between each pin and timer, refer to Table 4.1. The pin is set for an I/O
port by writi ng "0" to CFP1x.
In addition to pin selection here, the pin to be used for clock input to the 16-bit programmable timer must be set to
input mode using the I/O control register.
At c old start, CFP1x is set to "0" (I/O port). At hot start, CFP1x retains its status from prior to the initial reset.
CFP27–CFP22: P2[ 7:2 ] p in func tio n select io n (D[7:2 ]) / P 2 fu nctio n sele ct regist er (0 x4 0 2D8 )
Selects the pin used for clock output.
Write "1": Clo ck o utp ut pi n
Write "0": I/ O port pin
Read: Valid
Select the pin to be used to output a timer-generated clock to external devices from among P22 through P27, by
writing "1" to CFP22–CFP27. For the relationship between each pin and timer, refer to Table 4.1. The pin is set for
an I/O port by writing "0" to CFP2x.
At c old start, CFP2x is set to "0" (I/O port). At hot start, CFP2x retains its status from prior to the initial reset.
CFEX1: P10, P11, P13 port extended fun ction ( D 1) / Port function ex tension reg ister (0x402DF)
CFEX0: P12, P14 port extended funct ion (D0) / Port function ex tension reg ister (0x402DF)
Sets whether the function of an I/O-port pin is to be extended.
Write "1": Fun ction-extended pin
Write "0": I/O- port/peripheral-circuit pin
Read: Valid
When CFEX[1:0] is set to "1", the P14–P10 ports function as debug signal output ports. When CFEX[1:0] = "0",
the CFP1[4:0] bit becomes effective, so the settings of these bits determine whether the P14–P10 ports function as
I/O port s or external clock input ports.
At c old start, CFEX[1:0] is set to "1" (function-extended pins). At hot start, CFEX[1:0] retains its state from prior
to the initial reset.
IOC16–IOC10: P1[6:0 ] p ort I/O con tro l (D[6:0 ]) / P 1 I/ O con tro l regi st er (0 x40 2D 6 )
Directs P10 through P16 for input or output and indicates the I/O control signal value of the port.
When writing data
Write "1": O utput mode
Write "0": Input mode
For the pin sel ected from a m ong P1 0 through P16 for use for external clock input, write "0" to the corresponding
I/O control bit to set it to input mode. If the pin is set to output mode, even though its CFP1x may be set to "1", it
functions as the output pin of an 8-bit programmable timer and cannot be used to receive an external clock.
When re ad in g d ata
Read "1": I/O control signal (output)
Read "0": I/O control signal (input)
The I/O control signal value for the port pin is read from this register. When I/O port function is selected using the
CFEX and CFP1x reg isters, the value written to the IOC register is read out as is. When peripheral function is
selected, the read value depends on the peripheral circuit status and may not indicate the value written to the IOC
register.
At c old start, IOC1x is set to "0" (input mode). At hot start, the bit retains its state from prior to the initial reset.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS
B-III-4-20 EPSON S1C33L03 FUNCTION PART
SELFM0: Timer 0 fine mode selection (D6) / 16-b it time r 0 cont rol register (0x48186)
SELFM1: Timer 1 fine mode selection (D6) / 16-b it time r 1 cont rol register (0x4818E)
SELFM2: Timer 2 fine mode selection (D6) / 16-b it time r 2 cont rol register (0x48196)
SELFM3: Timer 3 fine mode selection (D6) / 16-b it time r 3 cont rol register (0x4819E)
SELFM4: Timer 4 fine mode selection (D6) / 16-bit timer 4 control register (0x481A6)
SELFM5: Time r 5 fine mode selecti on (D6) / 16-bit timer 5 control register (0x481AE)
Sets fin e m ode for clock output.
Write "1": F ine mode
Write "0": N ormal output
Read: Valid
When SELFMx is set to "1", clock output is set in fine mode which allows adjustment of the output signal duty
ratio in units of a half cycle for the input clock.
When SELFMx is set to "0", normal clock output will be performed.
At i nitial reset, SELFMx is set to "0" (normal output).
SELCRB0: Timer 0 comparison register buffer enable (D5) / 16-bit timer 0 control reg ister (0x48186)
SELCRB1: Timer 1 comparison register buffer enable (D5) / 16-bit timer 1 contr ol registe r (0x4818E)
SELCRB2: Timer 2 comparison register buffer enable (D5) / 16-bit timer 2 control reg ister (0x48196)
SELCRB3: Timer 3 comparison register buffer enable (D5) / 16-bit timer 3 control reg ister (0x4819E)
SELCRB4: Timer 4 comparison register buffer enable (D5) / 16-bit timer 4 control register (0x481A6)
SELCRB5: Timer 5 comparison register buffer enable (D5) / 16-bit timer 5 cont rol regis ter (0x 481AE)
Enabl es or disables writing to the comparison register buffer.
Write "1": Ena bled
Write "0": Disabl ed
Read: Valid
When SELCRBx is set to "1", comparison data is read and written from/to the comparison register buffer. The
content of the buffer is loaded to the comparison data register when the counter is reset by the software or the
comparison B signal.
When SELCRBx is set to "0", comparison data is read and written from/to the comparison data register.
At i nitial reset, SELCRBx is set to "0" (disabled).
OUTINV0: Timer 0 output inv ersion (D4) / 16-bit timer 0 control register (0x48186)
OUTINV1: Timer 1 output inv ersion (D4) / 16- bit tim er 1 control r egister (0x 4818E )
OUTINV2: Timer 2 output inv ersion (D4) / 16- bit tim er 2 control r egister (0x 48196 )
OUTINV3: Timer 3 output inv ersion (D4) / 16-bit timer 3 control register (0x4819E)
OUTINV4: Timer 4 output inv ersion (D4) / 16- bit timer 4 control r egister (0x481A6 )
OUTINV5: Timer 5 output inv ersion (D4) / 16-bit timer 5 control register (0x481AE)
Selects a logic of the output signal.
Write "1": Inverted (active low)
Write "0": Normal (active high)
Read: Valid
By writing "1" to OUTINVx , an active-low signal (off level = high) is generated for the TMx output. When
OUTINVx is set to "0", an active-high signal (off level = low) is generated.
At i nitial reset, OUTINVx is set to "0" (active high).
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS
S1C33L03 FUNCTION PART EPSON B-III-4-21
A-1
B-III
16TM
CKSL0: Timer 0 input clock selection (D3) / 16-bit timer 0 control register (0x48186)
CKSL1: Timer 1 input clock selection (D3) / 16-bit timer 1 control register (0x4818E)
CKSL2: Timer 2 input clock selection (D3) / 16-bit timer 2 control register (0x48196)
CKSL3: Timer 3 input clock selection (D3) / 16-bit timer 3 control register (0x4819E)
CKSL4: Timer 4 input clock selection (D3) / 16-bit timer 4 control register (0x481A6)
CKSL5: Timer 5 input clock selection (D3) / 16-bit timer 5 control register (0x481AE)
Selects the input clock of each timer.
Write "1": Extern al clock
Write "0": Inte rnal clock
Read: Valid
The internal clock (prescaler output) is selected for the input clock of each timer by writing "0" to CKSLx. An
external clock (one that is fed from the clock input pin) is selected by writing "1", and the timer functions as an
event counter. In this case, the clock input pin must be set using CFP1x before an external clock is selected here.
At i nitial reset, CKSLx is set to "0" (internal clock).
PTM0: Timer 0 clock out put contr ol (D2) / 16- bit tim er 0 control r egister (0x 48186 )
PTM1: Timer 1 clock out put contr ol (D2) / 16- bit tim er 1 control r egister (0x 4818E)
PTM2: Timer 2 clock out p ut control (D2) / 16-bit timer 2 control r egister (0x 48196 )
PTM3: Timer 3 clock out put contr ol (D2) / 16- bit tim er 3 control r egister (0x 4819E)
PTM4: Timer 4 clock out put contr ol (D2) / 16- bit tim er 4 control register (0x481A6)
PTM5: Timer 5 clock out put contr ol (D2) / 16- bit timer 5 control r egister (0x 481AE)
Controls the output of the TMx signal (t im er o utp ut clock).
Write "1": On
Write "0": Off
Read: Valid
The TMx signa l is output from the clock output pin by writing "1" to PTMx. Clock output is stopped by writing "0"
to PTMx and goes to the off level according to the OUTINVx setting (low when OUTINVx = "0" or high when
OUTINVx = "1"). In this case, the clock output pin must be set using CFP2x before outputting the TMx signal
here.
At i nitial reset, PTMx is set to "0" (off).
PRESET0: Timer 0 reset (D1) / 16-bit timer 0 co ntrol registe r (0x48186)
PRESET1: Timer 1 reset (D1) / 16-bit timer 1 co ntrol registe r (0x4818E)
PRESET2: Timer 2 reset (D1) / 16-bit timer 2 co ntrol registe r (0x48196)
PRESET3: Timer 3 reset (D1) / 16-bit timer 3 co ntrol registe r (0x4819E)
PRESET4: Timer 4 reset (D1) / 16-bit timer 4 control register (0x481A6)
PRESET5: Timer 5 reset (D1) / 16-bit timer 5 control register (0x481AE)
Resets the counter.
Write "1": Res et
Write "0": Invalid
Read: Alwa ys "0"
The cou nter of timer x is reset by writing "1" to PRESETx.
Writing "0" results in No Operation.
Since PRESETx is a write-only bit, its content when read is always "0".
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS
B-III-4-22 EPSON S1C33L03 FUNCTION PART
PRUN0: Timer 0 RUN/STOP control (D0) / 16-bit timer 0 control register (0x48186)
PRUN1: Timer 1 RUN/STOP control (D0) / 16-bit timer 1 control register (0x4818E)
PRUN2: Timer 2 RUN/STOP control (D0) / 16-bit timer 2 control register (0x48196)
PRUN3: Timer 3 RUN/STOP control (D0) / 16-bit t imer 3 control register (0x4819E )
PRUN4: Timer 4 RUN/STOP control (D0) / 16-bit timer 4 c ontrol register ( 0 x481A6)
PRUN5: Timer 5 RUN/STOP control (D0) / 16-bit timer 5 c ontrol register ( 0 x481AE)
Controls the timer's RUN/STOP state.
Write "1": RUN
Write "0": STOP
Read: Valid
Each timer is made to start counting up by writing "1" to PRUNx and made to stop counting by writing "0".
In the STOP state, the counter data is retained until the timer is reset or placed in a RUN state. By changing states
from STOP to RUN, the timer can restart counting beginning at the retained count.
At i nitial reset, PRUNx is set to "0" (STOP).
CR0A15–CR0A0: Timer 0 comparison data A (D[F:0]) / 16-bit timer 0 comparison data A set-up register (0x48180)
CR1A15–CR1A0: Timer 1 comparison data A (D[F:0]) / 16-bit timer 1 comparison data A set-up register (0x48188)
CR2A15–CR2A0: Timer 2 comparison data A (D[F:0]) / 16-bit timer 2 comparison data A set-up register (0x48190)
CR3A15–CR3A0: Timer 3 comparison data A (D[F:0]) / 16-bit timer 3 comparison data A set-up register (0x48198)
CR4A15–CR4A0: Timer 4 comparison data A (D[F:0]) / 16-bit timer 4 comparison data A set-up register (0x481A0)
CR5A15–CR5A0: Timer 5 comparison data A (D[F:0]) / 16-bit timer 5 comparison data A set-up register (0x481A8)
Sets the comparison data A of each timer.
When SELCRBx is set to "0", comparison data is directly read or writing from/to the comparison data register A.
When SELCRBx is set to "1", comparison data is read or written from/to the comparison register buffer A. The
content of the buffer is loaded to the comparison data register A when the counter is reset.
The data set in this register is compared with each corresponding counter data. When the contents match, a
comparison A interrupt is generated and the output signal rises (OUTINVx = "0") or falls (OUTINVx = "1"). This
does no t affect the counter value and count-up operation.
At i nitial reset, CRxA is not initialized.
CR0B15–CR0B0: Timer 0 comparison data B (D[F:0]) / 16-bit timer 0 comparison data B set-up register (0x48182)
CR1B15–CR1B0: Timer 1 comparison data B (D[F:0]) / 16-bit timer 1 comparison data B set-up register (0x4818A)
CR2B15–CR2B0: Timer 2 comparison data B (D[F:0]) / 16-bit timer 2 comparison data B set-up register (0x48192)
CR3B15–CR3B0: Timer 3 comparison data B (D[F:0]) / 16-bit timer 3 comparison data B set-up register (0x4819A)
CR4B15–CR4B0: Timer 4 comparison data B (D[F:0]) / 16-bit timer 4 comparison data B set-up register (0x481A2)
CR5B15–CR5B0: Timer 5 comparison data B (D[F:0]) / 16-bit timer 5 comparison data B set-up register (0x481AA)
Sets the comparison data B of each timer.
When SELCRBx is set to "0", comparison data is directly read or writing from/to the comparison data register B.
When SELCRBx is set to "1", comparison data is read or written from/to the comparison register buffer B. The
content of the buffer is loaded to the comparison data register B when the counter is reset.
The data set in this register is compared with each corresponding counter data. When the contents match, a
comparison B interrupt is generated and the output signal falls (OUTINVx = "0") or rises (OUTINVx = "1").
Furthermore, the counter is reset to "0".
At i nitial reset, CRxB is not initialized.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS
S1C33L03 FUNCTION PART EPSON B-III-4-23
A-1
B-III
16TM
TC015–TC00: Timer 0 count er data (D[F:0 ]) / 1 6-b it timer 0 counter data register (0x48184)
TC115–TC10: Timer 1 count er data (D[F :0 ]) / 1 6-bit timer 1 cou nt er data regi st er (0 x48 18 C )
TC215–TC20: Timer 2 count er data (D[F :0 ]) / 1 6-bit timer 2 cou nt er data regi st er (0 x48 19 4)
TC315–TC30: Timer 3 count er da ta (D [F :0 ]) / 1 6-bit time r 3 counter data register (0x4819C)
TC415–TC40: Timer 4 count er data (D[F :0 ]) / 1 6-bit timer 4 cou nt er data regi st er (0 x48 1A 4)
TC515–TC50: Timer 5 count er data (D[F :0 ]) / 1 6-bit timer 5 cou nt er data regi st er (0 x48 1A C )
The cou nter data of each timer can be read from this register.
The data can be read out at any time.
Since TCx is a read-only register, writing to this register is ignored.
At i nitial reset, TCx is not initialized.
P16T02–P16T00: Timer 0 interrupt level (D[2:0]) / 16-bit timer 0/1 interrupt priority register (0x40266)
P16T12–P16T10: Timer 1 interrupt level (D[6:4]) / 16-bit timer 0/1 interrupt priority register (0x40266)
P16T22–P16T20: Timer 2 interrupt level (D[2:0]) / 16-bit timer 2/3 interrupt priority register (0x40267)
P16T32–P16T30: Timer 3 interrupt level (D[6:4]) / 16-bit timer 2/3 interrupt priority register (0x40267)
P16T42–P16T40: Timer 4 interrupt level (D[2:0]) / 16-bit timer 4/5 interrupt priority register (0x40268)
P16T52–P16T50: T imer 5 interru pt lev el (D[6 :4 ]) / 1 6-b it ti mer 4 /5 inte rru pt prio rit y regi st er (0x4 0 268)
Sets the priority levels of 16-bit programmable timer interrupts.
The priority level can be set in the range of 0 to 7.
At i nitial reset, P16Tx becomes indeterminate.
E16TU0, E16TC0: Timer 0 interrupt enable (D2, D3) / 16-bit tim er 0/1 int errupt enable r egiste r (0x40272)
E16TU1, E16TC1: Timer 1 interrupt enable (D6, D7) / 16-bit tim er 0/1 int errupt enable r egiste r (0x40272)
E16TU2, E16TC2: Timer 2 interrupt enable (D2, D3) / 16-bit time r 2/ 3 inter rupt enable register (0x40273)
E16TU3, E16TC3: Timer 3 interrupt enable (D6, D7) / 16-bit tim er 2/3 int errupt enable r egiste r (0x40273)
E16TU4, E16TC4: Timer 4 interrupt enable (D2, D3) / 16-bit tim er 4/5 int errupt enable r egiste r (0x40274)
E16TU5, E16TC5: Timer 5 interrupt enable (D6, D7) / 16-bit tim er 4/5 int errupt enable r egiste r (0x40274)
Enabl es or disables the generation of an interrupt to the CPU.
Write "1": Inte rrupt enabled
Write "0": Inte rrupt disabled
Read: Valid
The E16T Ux and E16TCx are provided for the comparison B and comparison A interrupt factors, respectively. The
interrupt for which the bit is set to "1" is enabled, and the interrupt for which the bit is set to "0" is disabled.
At i nitial reset, these bits are set to "0" (interrupt disabled).
F16TU0, F16T C0: Timer 0 interrupt factor flag (D2, D3) / 16-bit timer 0/1 interrupt factor flag register (0x40282)
F16TU1, F16T C1: Timer 1 interrupt factor flag (D6, D7) / 16-bit timer 0/1 interrupt factor flag register (0x40282)
F16TU2, F16T C2: Timer 2 interrupt factor flag (D2, D3) / 16-bit timer 2/3 interrupt factor flag register (0x40283)
F16TU3, F16T C3: Timer 3 interrupt factor flag (D6, D7) / 16-bit timer 2/3 interrupt factor flag register (0x40283)
F16TU4, F16T C4: Timer 4 interrupt factor flag (D2, D3) / 16-bit timer 4/5 interrupt factor flag register (0x40284)
F16TU5, F16T C5: Timer 5 interrupt factor flag (D6, D7) / 16-bit timer 4/5 interrupt factor flag register (0x40284)
Indicates the status of 16-bit programmable timer interrupt generation.
When read
Read "1": Interrupt facto r has o ccu rred
Read "0": No inte rrupt fa ctor h as o ccu rred
When written using the rese t-onl y m etho d (d ef au lt)
Write "1": Interrupt factor flag is reset
Write "0": Invalid
When written using the read /w rite m et ho d
Write "1": Interrupt flag is set
Write "0": Interrupt flag is reset
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS
B-III-4-24 EPSON S1C33L03 FUNCTION PART
F16TUx and F16TCx are the interrupt factor flags corresponding to the comparison B and comparison A interrupts,
respectively. The flag is set to "1" when each interrupt factor occurs.
At t his time, if the following conditions are met, an interrupt to the CPU is generated:
1. The corresponding interrupt enable register bit is set to "1".
2. No other interrupt request of a higher prior ity has been generated.
3. The PSR's IE bit is set to "1" (interrupts enabled).
4. The value set in the corresponding interrupt priority register is higher than the CPU's interrupt level (IL).
When using the interrupt factor of the 16-bit programmable timer to request IDMA, note that even when the above
conditions are met, no interrupt request to the CPU is generated for the interrupt factor that has occurred. If
interrupts are enabled at the setting of IDMA, an interrupt is generated under the above conditions after the data
transfer by IDMA is completed.
The interrupt factor flag is set to "1" whenever interrupt generation conditions are met, regardless of how the
inte rrupt en ab le and in te rru pt p riority regi ste rs are set.
If the next interrupt is to be accepted after an interrupt has occurred, it is necessary that the interrupt factor flag be
reset, and that the PSR be set again (by setting the IE bit to "1" after setting the IL to a value lower than the level
indicated by the interrupt priority register, or by executing the reti instruction).
The interrupt factor flag can be reset only by writing to it in the software. Note that if the PSR is set again to accept
interrupts generated (or if the reti instruction is executed) without resetting the interrupt factor flag, the same
interrupt occurs again. Note also that the value to be written to reset the flag is "1" when the reset-only method
(RSTONLY = " 1" ) is used, and "0" when the rea d/ write me thod (RSTONLY = "0" ) is used.
At i nitial reset, all these flags become indeterminate, so be sure to reset them in the software.
R16TU0, R16TC0:Timer 0 IDMA request (D6, D7) /
Port inp ut 0–3, HSDMA, 16-bit timer 0 IDMA r eques t register (0x40290)
R16TU1, R16TC1:Timer 1 IDMA request (D0, D1) / 16-bit timer 1 –4 IDMA request registe r (0x40291)
R16TU2, R16TC2:Timer 2 IDMA request (D2, D3) / 16-bit timer 1–4 I D M A request registe r (0x40291)
R16TU3, R16TC3:Timer 3 IDMA request (D4, D5) / 16-bit timer 1–4 I D M A request registe r (0x40291)
R16TU4, R16TC4:Timer 4 IDMA request (D6, D7) / 16-bit timer 1–4 I D M A request registe r (0x40291)
R16TU5, R16TC5:Timer 5 IDMA request (D0, D1) /
16-bit t imer 5, 8- bit timer, serial I/F Ch.0 IDMA request register (0x40292)
Specifies whether to invoke IDMA when an interrupt factor occurs.
When using the se t-o n ly m et ho d (d ef ault)
Write "1": IDMA request
Write "0": Not changed
Read: Valid
When using the read /w rite m et ho d
Write "1": IDMA request
Write "0": Inte rrupt request
Read: Valid
R16TUx and R16TCx are IDMA request bits corresponding to the comparison B and comparison A interrupt
factors, respectively. When the bit is set to "1", IDMA is invoked when the interrupt factor occurs, thereby
performing programmed data transfers. When the register is set to "0", normal interrupt processing is performed
and IDMA is not invoked. For details on IDMA, refer to "IDMA (Intelligent DMA)".
At i nitial reset, these bits are set to "0" (interrupt request).
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS
S1C33L03 FUNCTION PART EPSON B-III-4-25
A-1
B-III
16TM
DE16TU0, DE16T C0:Timer 0 IDMA enab le (D6, D7) /
Port inp ut 0–3, HSDM A, 16-bit timer 0 IDMA enable register (0x40294)
DE16TU1, DE16T C1:Timer 1 IDMA enable (D0, D1) / 16-bit timer 1–4 I DM A enab le register (0x40295)
DE16TU2, DE16T C2:Timer 2 IDMA enable (D2, D3) / 16-bit timer 1–4 I DM A enab le register (0x40295)
DE16TU3, DE16T C3:Timer 3 IDMA enable (D4, D5) / 16-bit timer 1–4 ID M A enab le registe r (0x40295)
DE16TU4, DE16T C4:Timer 4 IDMA enable (D6, D7) / 16-bit timer 1–4 I DM A enab le register (0x40295)
DE16TU5, DE16T C5:Timer 5 IDMA enab le (D0, D1) /
16-bit t imer 5, 8- bit timer, serial I/F Ch.0 IDMA enable register (0x40296)
Enables ID M A transfer by means of an interrupt factor.
When using the se t-o n ly m et ho d (d ef ault)
Write "1": IDMA enabled
Write "0": Not changed
Read: Valid
When using the read /w rite m et ho d
Write "1": IDMA enabled
Write "0": IDMA disabled
Read: Valid
DE16TUx and DE16TCx are IDMA enable bits corresponding to the comparison B and comparison A interrupt
factors, respectively. If the bit is set to "1", the IDMA request by the interrupt factor is enabled. If the bit is set to
"0", the IDMA request is disabled.
Aft er an initial reset, these bits are set to "0" (IDMA disabled).
Pr ogramming Notes
(1) The 16-bit programmable timers operate only when the prescaler is operating.
(2) When setting the input clock or operation mode, make sure the 16-bit programmable timer is turned off.
(3) If a same value is set to the comparison data A and B registers, a hazard may be generated in the output signal.
Therefore, do not set the comparison registers as A = B.
There is no problem when t he interrupt function only is used.
(4) When using the output clock, set the comparison data registers as A ≥ 0 a nd B ≥ 1. The minimum settings are
A = 0 and B = 1. In this case, the timer output clock cycle is the input clock × 1/2.
(5) When the comparison data registers are set as A > B in normal mode, no comparison A interrupt is generated.
In this case, the output signal is fixed at the off level.
In fine mode, no comparison A interrupt is generated when the comparison data registers are set as A > 2 × B
+ 1.
(6) After an initial reset, the interrupt factor flag becomes indeterminate. To prevent generation of an unwanted
interrupt or IDMA request, be sure to reset this flag and register in the software.
(7) To prevent another interrupt from being generated by the same factor after an interrupt has occurred, be sure
to reset the interrupt factor flag before setting the PSR again or executing the reti instruction.
(8) Be aware that unnecessary pulse may be generated according to the control of the clock output and port
configuration when a 16-bit programmable timer is used to output the TMx clock.
For example, when TMx is set as inverted output (OUTINVx = "1"), the output waveform falls with the
comparison B signal and it rises with the comparison A signal. Furthermore, the output pin is fixed at high
level when PTMx is set to "0" to stop the clock output. When switching the output pin to the I/O port pin and
then setting the port to low after the TMx signal falls with the comparison A signal, a high level pulse will be
generated if "0" is written to PTMx before setting the port to low. It can be prevented by writing "0" to PTMx
after setting the port to low.
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS
B-III-4-26 EPSON S1C33L03 FUNCTION PART
TH IS PAGE IS BLANK.
III PERIPHERAL BLOCK: WATCHDOG TIMER
S1C33L03 FUNCTION PART EPSON B-III-5-1
A-1
B-III
WDT
III-5 WATCHDOG TIMER
Configuration of Watchdog Timer
The Peripheral Block incorporates a watchdog timer function to detect the CPU's crash.
This fun ction is implemented through the use of the 16-bit programmable timer 0. When this function is enabled,
an NMI (nonmaskable interrupt) is generated by the comparison B signal from the 16-bit programmable timer 0
(generating intervals can be set through the use of software). The 16-bit programmable timer 0 set in the software
so as not to generate the NMI, making it possible to detect a program crash that may not pass through this
processing routine.
Figure 5.1 shows the block diagram of the watchdog timer.
Clock generator 16-bit
programmable timer 0
Prescaler NMI
Watchdog timer
EWD
Figur e 5.1 Watchdog Timer Block Diagram
Control of Watc hdo g Timer
Setting the operating clock and NMI generating interval
The watchdog timer is operated by the prescaler's output clock. Therefore, the watchdog timer function
cannot be used when the prescaler is inactive.
The NM I is ge nerated every time the 16-bit programmable timer 0 is reset by the comparison B setting.
Th erefore, this interval is determined by the prescaler's P16TS0[2:0] (D[2:0]) / 16-bit timer 0 clock control
register (0x40147), and the comparison data B set in CR0B[15:0] (D[F:0]) / 16-bit timer 0 comparison
register B (0x48182).
The NM I generating interval is calculated using the following equation:
NMI generatin g interval = CR0B + 1 [sec.]
fPSCIN × pdr
fPSCIN:Prescaler input clock frequency [Hz]
pdr: Pr esc aler's division ratio set by the P16TS0 register (1/4096, 1/1024, 1/256, 1/64, 1/16, 1/4, 1/2, 1/1)
CR 0B: Set value of the CR0B r egist er (0 to 65, 535)
For details on how to control the prescaler and the 16-bit programmable timer 0, refer to "Prescaler" and "16-
Bit Programmable Timers".
Setting the watchdog timer function
To use the watchdog timer function, enable the NMI that is generated by the comparison B signal from the
16-bit programmable ti me r 0. For this p urp os e, use E W D (D1 ) / Wat ch do g timer enab le regi ster (0x4 01 71).
The NM I is enabled by writing "1" to EWD. At initial reset, EWD is set to "0", so generation of the NMI is
disabled.
To prevent an unw anted NMI from being generated by erroneous writing to EWD, this register is normally
write-protected. To write-enable EWD, write "1" to WRWD (D7) / Watchdog timer write-protect register
(0x40170). Only one writing to EWD is enabled in this way by the WRWD bit. When data is written to EWD
after it is write-enabled, the WRWD bit is reset back to "0", thus making EWD write-protected again.
For the 16-bit programmable timer 0, set an appropriate comparison B value to make it start operating.
If the watchdog timer function is not to be used, set EWD to "0" and do not change it.
III PERIPHERAL BLOCK: WATCHDOG TIMER
B-III-5-2 EPSON S1C33L03 FUNCTION PART
Resetting the watchdog timer
When using the watchdog timer, prepare a routine to reset the 16-bit programmable timer 0 before an NMI is
generated in a location where it will be periodically processed. Make sure this routine is processed within the
NMI generation interval described above.
The 16- bit programmable timer 0 is reset by writing "1" to PRESET0 (D1) / 16-bit timer 0 control register
(0x48186). At this point, the timer counter is set to 0, and the timer starts counting the NMI generation
interval over again from that point.
If the watchdog timer is not reset within the set interval for any reason, the CPU is made to enter trap
processing by an N MI and starts executing the processing routine indicated by the NMI vector.
The N M I trap vector addre ss is set t o 0x0C 0001 C by de fault.
The trap table base address can be changed using the TTBR registers (0x48134 to 0x48137).
Operation in Standby Modes
During HALT mode
In HALT mode (basic mode or HALT2 mo de), the prescaler and wat chdo g timer are operating. Conseq uently,
if HALT mode continues beyond the NMI generation interval, HALT mode is cleared by the NMI.
To disable the watchdog timer in HALT mode, set EWD to "0" before executing the halt instruction or turn
off the 16-bit programmable timer 0.
If the NMI is disabled by EWD, the 16-bit programmable timer 0 continues counting even in HALT mode.
To reenable the NMI after clearing HALT mode, reset the 16-bit programmable timer 0 in advance.
If HALT mode was entered after the 16-bit programmable timer 0 was turned off, reset the timer before
restarting it.
During SLEEP mode
In SLEEP mode, the prescaler is turned off. Therefore, the watchdog timer also stops operating. To prevent
generation of an unw anted NMI after clear ing SLEEP mode, reset the 16-bit pro grammable timer 0 before
executing the slp instruction. In addition, disable generation of the NMI by EWD as necessary.
III PERIPHERAL BLOCK: WATCHDOG TIMER
S1C33L03 FUNCTION PART EPSON B-III-5-3
A-1
B-III
WDT
I/O Memo ry of Watc hdog Ti mer
Table 5.1 shows t he control bits of the watchdog timer.
Table 5.1 Control Bits of Watchdog Timer
NameAddressRegister name Bit Function Setting Init. R/W Remarks
WRWD
–
D7
D6–0 EWD write protection
–0
–R/W
–0 when being read.
0040170
(B) –
1
Write enabled
0
Write-protect
Watchdog
timer write-
protect register
–
–
–
EWD
–
D7–2
D1
D0
–
Watchdog timer enable
–
–
0
–
–
R/W
–
0 when being read.
0 when being read.
0040171
(B) 1
NMI enabled
0
NMI disabled
Watchdog
timer enable
register
WRWD: EWD writ e protection (D7) / Watchdog timer wri te-pr otect regis ter (0x 40170 )
Enables writing to the EWD register.
Write "1": Wri ting enabled
Write "0": Write-protected
Read: Valid
The EWD bit is write-protected to prevent unwanted modifications. Writing to this bit is enabled for only one
writing by setting WRWD to "1". WRWD is reset back to "0" by writing to EWD, so EWD is write-protected
again.
If WRWD is reset to "0" when EWD is write-enabled (WRWD = "1"), EWD becomes write-protected again.
At i nitial reset, WRWD is set to "0" (write-protected).
EWD: NMI enable (D1) / Watchdog timer enable register (0x40171 )
Controls the generat ion of a nonm aska ble interrupt (NMI) by the watchdog timer.
Write "1": NMI is enabled
Write "0": NMI is disabled
Read: Valid
The watchdog timer's interrupt signal is masked by writing "0" to EWD, so a nonmaskable interrupt (NMI) to the
CPU is not generated. If EWD is set to "1", an NMI is generated by the 16-bit programmable timer 0 comparison B
signal.
Writing to EWD is valid only when WRWD = "1".
Even when EW D is set to "0", the 16-bit programmable timer 0 does not stop counting. Therefore, if the NMI has
been tem por arily disabled, be sure to reset the 16-bit programmable timer 0 before setting the EWD register back
to "1".
At i nitial reset, EWD is set to "0" (NMI disabled).
Pr ogramming Notes
(1) If the watchdog timer's NMI is enabled, the watchdog timer must be reset in the software before the 16-bit
programmable timer 0 ou tputs the comparison B signal.
(2) Even when EWD is set to "0", the 16-bit programmable timer 0 does not stop counting. Therefore, if the NMI
has been temporaril y disabled, be sure to reset the 16-bit programmable timer 0 before setting EWD back to
"1".
III PERIPHERAL BLOCK: WATCHDOG TIMER
B-III-5-4 EPSON S1C33L03 FUNCTION PART
TH IS PAGE IS BLANK.
III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT
S1C33L03 FUNCTION PART EPSON B-III-6-1
A-1
B-III
OSC1
III-6 LOW-SPEED ( OSC 1) O SCI LLATION CI R CUIT
Configuration of Low-Speed (OSC1) Oscillation Circuit
The Peripheral Block has a built-in low-speed (OSC1) oscillation circuit.
The low-speed (OSC1) oscillation circuit generates a 32.768-kHz (Typ.) subclock.
The OSC1 clock output by this circuit is delivered to the CLG (clock generator) in the Core Block and is used as
the source clock for the clock timer. It can also be used as a sub-clock for the low-speed (low-power) operation of
the CPU and peripheral circuits (switchable in a program).
Figure 6.1 shows the configuration of the clock system.
Clock
switch
CLKCHG
To CPU
and BCU
OSC3/PLL
clock
To peripheral
circuits
Low-speed (OSC1)
oscillation circuit
SOSC1
PF1ON
Oscillation
ON/OFF
OSC1
OSC2
I/O port Prescaler
Clock timer
FOSC1
(P14)
CLG
Figur e 6.1 Configuration of Clock System
The CPU op erating clock can be switched to the output (OSC1 clock) of the low-speed (OSC1) oscillation circuit
in a program. Furthermore, the oscillation circuit can be stopped in a program.
If the OSC3 clock is unnecessary such as when performing clock processing only, set the OSC1 clock for operation
of the CPU/ peripheral circuits and turn off the high-speed (OSC3) oscillation circuit in order to reduce current
consumption.
The low-speed (O SC1) oscillation circuit does not stop in SLEEP mode.
For the control method when using the OSC1 clock for the operating clock of the peripheral circuits, refer to
"Prescaler".
I/O Pins of Low-Speed (OSC1) Oscillation Circuit
Table 6.1 lists t he I/O pins of the low-speed (OSC1) oscillation circuit.
Table 6.1 I/O Pins of Low-Speed (OSC1) Oscillation Circuit
Pin name I/O Function
OSC1 I Low-speed (OSC1) oscillation input pin
Crystal oscillation or external clock input
OSC2 O Low-speed (OSC1) oscillation output pin
Crystal oscillation (open when external clock is used)
P14/FOSC1/DCLK I/O I/O port / Low-speed (OSC1) oscillation clock output / DCLK signal output
III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT
B-III-6-2 EPSON S1C33L03 FUNCTION PART
Oscillator Types
In the low-speed (OSC1) oscillation circuit, either a crystal oscillation or an external clock input can be selected as
the type of oscillation circuit.
Figure 6.2 shows the structure of the low-speed (OSC1) oscillation circuit.
V
SS
OSC2
OSC1
R
f
C
D1
C
G1
Oscillation circuit
control signal Oscillation circuit
control signal
X'tal1
f
OSC1
OSC2
OSC1
External
clock
N.C.
V
SS
V
DD f
OSC1
(1) Crystal oscillation circuit
V
SS
OSC2
OSC1
Oscillation circuit
control signal
Low level
(
3
)
When not used
(2) External clock input
Figur e 6.2 Low-Speed (OSC1) Oscillation Circuit
When using a crystal oscillation for this circuit, connect a crystal resonator X'tal1 (32.768 kHz, Typ.) and feedback
resistor (Rf) between the OSC1 and OSC2 pins, and two capacitors (CG1, CD1) betw ee n th e OSC 1 pin an d V SS and
the OSC2 pin and VSS, re sp ec tiv ely .
When an external clock source is used, leave the OSC2 pin open and input a square-wave clock to the OSC1 pin.
If the low-speed (OSC1) oscillation circuit is not used, connect the OSC1 pin to VSS and leave the OSC2 pin open.
The oscillation frequency is 32.768 kHz (Typ.). Use a crystal resonator or ex ternal clock that oscillates at this
frequency. No other frequency can be used for clock applications.
For details on osc illation characteristics and the external clock input characteristics, refer to "Electrical
Characteristics".
III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT
S1C33L03 FUNCTION PART EPSON B-III-6-3
A-1
B-III
OSC1
Controlling Osc illat ion
The low- speed (OSC1) osc illat ion circuit can be turned on or off using SOSC1 (D0) / Pow er control regist er
(0x40180).
The osc illation circuit is turned off by writing "0" to SOSC1 and turned back on again by writing "1". SOSC1 is set
to "1" at initial reset, so the oscillation circuit is turned on.
Notes:•When the low-speed (OSC1) oscillation circuit is used as the clock source for the CPU operating
clock, i t cann ot be turned off. In this case, writing "0" to SOSC1 is ignored. Note also that writing
to SOSC1 is allowed only when the powe r-contro l re g i st er pr otec ti o n fl a g i s se t to
"0b10010110".
•Immediately after the oscillation circuit is turned on, a certain period of time is required for
oscillation to stabilize (3 sec max.). To prevent the device from operating erratically, do not use
the clock until its oscillation has stabilized.
The low-spe ed (OSC1) oscillation cir cuit does not stop when the CPU is set in SLEEP mode.
Switching Over the CPU Operating Clock
Aft er an initial reset, the CPU starts operating using the OSC3 clock.
In cases in which some peripheral circuits (e.g., programmable timer, serial interface, A/D converter, and ports) do
not need to be ope rate or processing in low -speed ope ration is possible, and the CPU can process its jobs at a low
clock speed, the CPU operating clock can be switched to the OSC1 clock, thereby reducing current consumption.
Use CLKCHG (D2) / Power control register (0x40180) to switch over the operating clock.
Procedu re for switchi ng over from the OSC3 clock to the OSC1 clock
1. Turn on the low-speed (OSC1) oscillation circuit (by writing "1" to SOSC1).
2. W ait until the OSC1 oscillation stabilizes (three seconds or more).
3. Change the CPU operating clock (by writing "0" to CLKCHG).
4. Turn off the high-speed (OSC3) oscillation circuit (by writing "0" to SOSC3).
∗ Steps 1 and 2 are required only when the low-speed (OSC1) oscillation circuit is inactive.
Notes:•Use separate instructions to switch from OSC3 to OSC1 and turn the OSC3 oscillation off. If
these operations are processed simultaneously us ing one instr uction, the CPU m ay op erate
erratically.
•Make sure the operation of t he peripheral cir cuits, such as the programm able timer and serial
interface is terminated before the OSC3 oscillation is turned off in order to prevent them from
operating err a tically or the prescaler clock is se t as O SC1. In additi on, in order to prevent
incorrect operation, a set up of prescaler must be performed before changing the CPU clock.
Procedu re for switchi ng over from the OSC1 clock to the OSC3 clock
1. Turn on the high-speed (OSC3) oscillat ion cir cuit (by writin g "1" t o SOSC3 ).
2. W ait until the OSC3 oscillation stabilizes (10 ms or more for a 3.3-V crystal resonator).
3. Switch over the CPU operating clock (by writing "1" to CLKCHG).
Note: The operating clock switchover by CLKCHG is effective only when both oscillation circuits are on
and the power-control reg ister protect ion fla g is set to " 0b10 01011 0" .
III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT
B-III-6-4 EPSON S1C33L03 FUNCTION PART
Power-Control Register Protection Flag
The power-contr ol regist er (SO SC1 , SOSC3, CLKCHG, CLK D T[1 :0]) at address 0x40 180, w hich is used to
control the oscillation circuits and the CPU operating clock, is normally disabled against writing in order to prevent
it from malfunctioning due to unnecessary writing.
To enable this register for writing, the power-control register protection flag CLGP[7:0] (D[7:0]) / Power-control
protection register (0x4019E) must be set to "0b10010110". Note that this setting allows for the power-control
register (0x40180) to be written to only once, so all bits of CLGP[7:0] are cleared to "0" when this address is
written to. Therefore, CLGP[7:0] must be set to "0b10010110" each time the power-control register (0x40180) is
written to.
The flag CL GP[7:0] does not affect the readout from the power-control register (0x40180).
Operation in Standby Mode
In HALT mode, which is entered by executing the halt instruction, the low-speed (OSC1) oscillation circuits
retains its status before HALT mode is entered. Under normal conditions, therefore, there is no need to control the
oscillation circuit before entering or after exiting HALT mode.
The low-spe ed (OSC1) osc illat ion circui t does not stop operating in SLEEP mode set by executing the slp (sleep)
instruction. Therefore, if the CPU was operating using the OSC1 clock before SLEEP mode was entered, the CPU
keeps operating using the OSC1 clock in SLEEP mode.
OSC1 Clock Output to External Devices
The low-speed (O SC1) oscillatio n cl oc k can be output from the FOSC1 (P14) pin to external devices.
Table 6.2 OSC1 Clock Output Pin
Pin name I/O Function Function selec t bit
P14/FOSC1/
DCLK I/O I/O port / Low-speed (OSC1) oscillation
clock output / DCLK signal output CFP14(D4) / P1 function select register (0x402D4)
CFEX0 (D0) / Port function extension register (0x402DF)
Setting the clock output pin
The pin used to output the OSC1 clock to external devices is shared with the P14 I/O port and the debug
clock signal DCLK.
At c old start, it is set for the DCLK signal output (CFP14 = "0" and CFEX0 = "1"). When using the clock
outpu t function, write "1" to CFP14 and "0" to CFEX0 (refer to "I/O Ports"), and also write "1" to IOC14
(0x402D6/D4).
At ho t start, the pin retains its pre-reset status.
Output control
To start clo ck output, w rite "1" t o PF1O N (D0) / Clock option register (0x40190). The clock output is stopped
by w riting "0".
At i nitial reset, PF1ON is set to "0" (output disabled).
PF1ON register
FOSC1(P14) pin output
00
VDD
VSS
1
Figure 6.3 OSC1 Clock Output
III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT
S1C33L03 FUNCTION PART EPSON B-III-6-5
A-1
B-III
OSC1
I/O Memo ry of Low-Spe ed (OSC1) Oscillat ion Circuit
Table 6.3 lists t he control bits of the low-speed (OSC1) oscillation circuit.
Table 6.3 Control Bits of Low-Speed (OSC1) Oscillation Circuit
NameAddressRegister name Bit Function Setting Init. R/W Remarks
CLKDT1
CLKDT0
PSCON
–
CLKCHG
SOSC3
SOSC1
D7
D6
D5
D4–3
D2
D1
D0
System clock division ratio
selection
Prescaler On/Off control
reserved
CPU operating clock switch
High-speed (OSC3) oscillation On/Off
Low-speed (OSC1) oscillation On/Off
1 On 0 Off
1 OSC3 0 OSC1
1 On 0 Off
1 On 0 Off
0
0
1
0
1
1
1
R/W
R/W
–
R/W
R/W
R/W
Writing 1 not allowed.
0040180
(B) 1
1
0
0
1
0
1
0
CLKDT[1:0] Division ratio
1/8
1/4
1/2
1/1
–
Power control
register
–
HLT2OP
8T1ON
–
PF1ON
D7–4
D3
D2
D1
D0
–
HALT clock option
OSC3-stabilize waiting function
reserved
OSC1 external output control
–
0
1
0
0
–
R/W
R/W
–
R/W
0 when being read.
Do not write 1.
0040190
(B) 1 On 0 Off
1 Off 0 On
1 On 0 Off
–
–
Clock option
register
Writing 10010110 (0x96)
removes the write protection of
the power control register
(0x40180) and the clock option
register (0x40190).
Writing another value set the
write protection.
CLGP7
CLGP6
CLGP5
CLGP4
CLGP3
CLGP2
CLGP1
CLGP0
D7
D6
D5
D4
D3
D2
D1
D0
Power control register protect flag 0
0
0
0
0
0
0
0
R/W004019E
(B)
Power control
protect register
–
CFP16
CFP15
CFP14
CFP13
CFP12
CFP11
CFP10
D7
D6
D5
D4
D3
D2
D1
D0
reserved
P16 function selection
P15 function selection
P14 function selection
P13 function selection
P12 function selection
P11 function selection
P10 function selection
–
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.
Extended functions
(0x402DF)
00402D4
(B) 1 EXCL5
#DMAEND1
0 P16
1 EXCL4
#DMAEND0
0 P15
1 EXCL3
T8UF3 0 P13
1 EXCL2
T8UF2 0 P12
1 EXCL1
T8UF1 0 P11
1 EXCL0
T8UF0 0 P10
–P1 function
select register
1 FOSC1 0 P14
CFEX7
CFEX6
CFEX5
CFEX4
CFEX3
CFEX2
CFEX1
CFEX0
D7
D6
D5
D4
D3
D2
D1
D0
P07 port extended function
P06 port extended function
P05 port extended function
P04 port extended function
P31 port extended function
P21 port extended function
P10, P11, P13 port extended
function
P12, P14 port extended function
0
0
0
0
0
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00402DF
(B)
Port function
extension
register
1
#DMAEND3
0 P07, etc.
1
#DMAACK3
0 P06, etc.
1
#DMAEND2
0 P05, etc.
1
#DMAACK2
0 P04, etc.
1 #GARD 0 P31, etc.
1 #GAAS 0 P21, etc.
1 DST0
DST1
DPC0
0 P10, etc.
P11, etc.
P13, etc.
1 DST2
DCLK 0 P12, etc.
P14, etc.
III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT
B-III-6-6 EPSON S1C33L03 FUNCTION PART
SOSC1: Low-speed (OSC1) oscillation control (D0) / Power control register (0x40180)
Turns the low-speed (OSC1) os cillati on on or off.
Write "1": O SC1 osci lla tio n tu rn ed on
Write "0": O SC1 oscilla tio n tu rn ed off
Read: Valid
The osc illation of the low-speed (OSC1) oscillation circuit is stopped by writing "0" to SOSC1, and started again
by w riting "1".
Since a duration of maximum three seconds is required for oscillation to stabilize after the oscillation has been
restarted, at least this length of time must pass before the OSC1 clock can be used.
Writing to SOSC1 is allowed only when CLGP[7:0] is set to "0b10010110". Note also that if the CPU is operating
using the OSC1 clock, writing "0" to SOSC1 is ignored and the oscillation is not turned off.
At i nitial reset, SOSC1 is set to "1" (OSC1 oscillation turned on).
CLKCHG: CPU operating clo ck switch (D2) / Power control r egister (0x40180 )
Selects the CPU operating clock.
Write "1": O SC3 clock
Write "0": O SC1 clock
Read: Valid
The OSC3 clock is selected as the CPU operating clock by writing "1" to CLKCHG, and OSC1 is selected by
writing "0". The operating clock can be switched over in this way only when both the high-speed (OS C3 ) and lo w -
speed (OSC1) oscillation circuits are on. In addition, writing to CLKCHG is effective only when CLGP[7:0] is set
to "0b10010110". Immediately after the oscillation circuit has started oscillating, wait for the oscillation to stabilize
before switching over the CPU operating clock.
At i nitial reset, CLKCHG is set to "1" (OSC3 clock).
For controlling the high-speed (OSC3) oscillation circuit, refer to "CLG (Clock Generator)" in the Core Block.
HLT2OP: HALT clock option (D3) / Clock op tion r egister (0x40190)
Select a HALT condition (basic mode or HALT2 m ode ).
Write "1": H ALT2 mode
Write "0": Bas ic mode
Read: Valid
When "1" is written to HLT2OP, the CPU will enter HALT2 mode when the HALT instruction is executed. When
"0" is written, the CPU will enter basic mode.
Writing to HLT2OP is allowed only when CLGP[7:0] is set to "0b10010110".
At i nitial reset, HLT2OP is set to "0" (basic mode).
III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT
S1C33L03 FUNCTION PART EPSON B-III-6-7
A-1
B-III
OSC1
The following shows the operating status in HALT mode (basic mode and HALT2 mode) and SLEEP mode.
Table 6.4 Operating Status in Standby Mode
Standby mode Operating status Reactivating factor
HALT mode Basic mode • The CPU clock is stopped. (CPU stop status)
•BCU clo ck is supplied. (BCU run status)
•DMA clock is not stopped. (DMA run status)
•Clocks for the peripheral circuits maintain the
status before entering HALT mode. (run or
stop)
•The high-speed oscillation circuit maintains
the status before entering HALT mode.
•The low-speed oscillation circuit maintains
the status before entering HALT mode.
•Reset, NMI
•Enabled (not m asked) interrupt
factors
HALT 2 m ode • The CPU cl ock is stopped. (CPU stop status)
•BCU clo ck is stopped. (BCU stop status)
•DMA clock is stopped. (DMA stop status)
•Clocks for the peripheral circuits maintain the
status before entering HALT mode. (run or
stop)
•The high-speed oscillation circuit maintains
the status before entering HALT mode.
•The low-speed oscillation circuit maintains
the status before entering HALT mode.
A restart is possible only in the
case of:
•Reset, NMI
•Enabled (not m asked) interrupt
factors
Note, however, that an interrupt
from a peripheral circuit can restart
the CPU only when the operating
clock is supplied to the peripheral
circuit.
SLEEP mode • The CPU clock is stopped. (CPU stop status)
•BCU clo ck is stopped. (BCU stop status)
•Clocks for the peripheral circuits are stopped.
•The high-speed oscillation circuit is stopped.
•The low-speed oscillation circuit maintains
the status before entering SLEEP mode.
•Reset, NMI
•Enabled (not masked) input port
interrupt factors
•Clock timer interrupt when the
low-speed oscillation circuit is
being operated
PF1ON: OSC1 external output cont rol (D0) / Clock option r egister (0x 40190 )
Turns the low-speed (OSC1) clock output to external devices on or off.
Write "1": On
Write "0": Off
Read: Valid
The low-speed (OSC1) clock is output from the FOSC1 pin to an external device by writing "1" to PF1ON.
However, for this setting to be effective, the P14 pin must be set for the FOSC1 pin by CFP14 and CFEX0, and
outpu t must be set by setting IOC14 (D4/0x4 02D6 <P1 I/O con trol regis ter> ) to "1".
The clock output is disabled by writing "0".
Writing to PF1ON is allowed only when CLGP[7:0] is set to "0b10010110".
At i nitial reset, PF1ON is set to "0" (Off).
CLGP7–CLGP0: Pow e r-c ontrol register p r otecti o n fl ag ([D[7:0]) / Power control protection register
(0x4019E)
These bits remove the protection against writi ng to add resses 0x4018 0 and 0x4019 0.
Write "0b100 10 11 0" : Writ e p rotecti o n rem ov ed
Write othe r than the above: No operation (write-protected)
Read: Valid
Before writing to address 0x40 180 or 0x40 190, set CLGP[ 7:0] to "0b10010110" to remove the protection against
writing to that address. This clearing of write protection is effective for only one writing, so the bits are cleared to
"0b00000000" by one writing. Therefore, CLGP[7:0] must be set each time the protected address is written to.
At i nitial reset, CLGP is set to "0b00000000" (write-protected).
III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT
B-III-6-8 EPSON S1C33L03 FUNCTION PART
CFP14: P14 function selection (D4) / P1 function select register (0x402D4)
Selects the pin function of the P14 I/O port.
Write "1": O SC1 clock output pin
Write "0": I/ O port pin
Read: Invalid
The P14 pin is set for O SC1 c lock output (FOSC1) by writing "1" to CFP14.
When this pin is used as the FOSC1 output pin, also set IOC14 (D4/0x402D6 <P1 I/O control register>) to "1"
(output).
At c old start, CFP14 is set to "0" (I/O port pin). At hot start, CFP14 retains its status from before the initial reset.
CFEX0: P12, P14 extended function (D0) / Port function ex tension regi ster ( 0x402DF)
Sets whether the function of the P14 pin is to be extended.
Write "1": DCLK output pin
Write "0": P14 /FOSC1 output pin
Read: Invalid
When CFEX0 is set to "1", the P14 pin functions as a debug clock DCLK output pin. When CFEX0 = "0", the
CFP14 r egist er become s eff ective, so the settings of this register determine whether the P14 pin functions as an P14
I/O port or a FOSC1 output pin.
At c old start, CFEX0 is set to "1" (DCLK output pin). At hot start, CFEX0 retains its state from prior to the initial
reset.
Pr ogramming Notes
(1) Immediately after the low-speed (OSC1) oscillation circuit is turned on, a certain period of time is required
for oscillation to stabilize (3 sec max.). To prevent the device from operating erratically, do not use the clock
until its oscillation has stabilized.
(2) The oscillation circuit used for the CPU operating clock cannot be turned off.
(3) The CPU operating clock can only be switched over when both the OSC3 and OSC1 oscillation circuits are
on. Furthermore, when turning off an oscillation circuit that has become unnecessary as a result of the CPU
operating clock switchover, be sure to use separate instructions for switchover and oscillation turnoff. If these
two operations are processed simultaneously using one instruction, the CPU may operate erratically.
(4) If the low-speed (OSC1) oscillation circuit is turned off, all peripheral circuits operated using the OSC1 clock
will be inactive.
(5) If the OSC3 clock is unnecessary, use the OSC1 clock to operate the CPU and turn the high-speed (OSC3)
oscillation circuit off. This helps reduce current consumption.
(6) When the P14/FOSC1/DCLK pin is used as the FOSC1 output pin, set IOC14 (D4/0x402D6) to "1" (output)
in addition to the CFP14 (D4/0x402D4) and CFEX0 (D0/0x402DF) settings.
III PERIPHERAL BLOCK: CLOCK TIMER
S1C33L03 FUNCTION PART EPSON B-III-7-1
A-1
B-III
CTM
III-7 CLOCK TIMER
Configuration of Clock Timer
The clock timer consists of an 8-bit binary counter that is clocked by a 256-Hz signal derived from the low-speed
(OSC1) oscillation clock fOSC1, and second, minute, hour, and day counters, allowing all data (128 Hz to 1 Hz,
seconds, minutes, hours, and day) to be read out in a software. It can also generate an interrupt using a 32-Hz, 8-Hz,
2-H z, or 1-Hz (1-second) signal or w hen a one-m inute, one-hour, or one-day count is up, in addition to generating
an alarm at a specified time (minute or hour) or day.
The low-speed (O SC1) oscillation circuit and the clock timer can be kept operating even when the CPU and other
internal peripheral circuits are placed in standby mode (HALT or SLEEP).
Normally, this clock timer should be used for a clock and various other clocking functions.
Figure 7.1 shows the structure of the clock timer.
Note: Since the clock timer is driven by a clock originating from the low-speed (OSC1) oscillation circuit,
this timer cannot be used unless the low-speed (OSC1) oscillation circuit (32.768 kHz, Typ.) is
used.
OSC1
oscillation
circuit
Interrupt generation
control circuit
Interrupt/alarm
select circuit
Divider
Internal data bus
Alarm generation
control circuit
fOSC1 256 Hz
3
2.768 kHz
128
Hz 64
Hz 32
Hz 16
Hz 8
Hz 4
Hz 2
Hz 1
Hz
Clock timer Run/Stop
Clock timer reset
Interrupt request
(to interrupt controller)
6-bit
seconds
counter
6-bit
minutes
counter
5-bit
hours
counter
16-bit
day
counter
Comparator Comparator Comparato
r
6-bit minute
comparison
data
5-bit hour
comparison
data
5-bit day
comparison
data
Figur e 7.1 Structure of Clock Timer
III PERIPHERAL BLOCK: CLOCK TIMER
B-III-7-2 EPSON S1C33L03 FUNCTION PART
Control and Operation of the Clock Timer
Initial setting
At i nitial reset, the clock timer's counter data, setup contents of alarms, and control bits including RUN/STOP,
are not initialized. (This does not include the CPU core power on /off flag TCHVOF or OSC1 auto-off f lag
TCAOFF.)
There fore, wh en using the clock timer, initialize it as follows:
1. Before you star t sett ing up, sto p the clock timer and disable the clock timer interrupt.
2. Reset the counte rs.
3. Preset the minute, hour, and day data (only when necessary).
4. Select an interrupt factor.
5. Select the alarm function.
6. Enable the interrupt.
7. Start the clock timer.
The following shows how to set and control each of the above. For details on interrupt control, refer to
"Interrupt Function".
Resetting the counters
Each counter of the clock timer can only be reset to "0" in the software. Note that they are not reset by an
initial reset or the auto-off function.
To reset the clock timer, write "1" to TCRST (D1) / Clock timer Run/Stop register (0x40151). Note, however,
that this reset input is accepted only when the clock timer is inactive, and is ignored when the timer is
operating.
Notes: •The clock timer reset bit TCRST and the clock timer RUN/STOP control bit TCRUN are located
at the same addr ess (0x40151). However, the clock tim er cann ot be reset at t he same t ime it i s
set to RUN by writing "1" to both. In this case, the reset input is ignored and the timer starts
counting up f rom the counter val ues then in effect. Always make sure TCRUN = "0" before
resetting the timer.
•When t he coun ters are cleared as the clock timer is reset, an interrupt may be generated
depending on the timer settin gs. Therefore, first disable th e cl oc k t ime r in ter ru pt before resetting
the clock timer, and after resetting the clock timer, reset the interrupt factor flag, interrupt factor
generation flag, and alarm factor generatio n flag.
Presetting minute, hour, and day data
The clock timer' s mi nute, hour, and day counters have a data preset functi on, enabling the desired time and
day to be set.
Table 7.1 Presetting the Counters
CounterData register Preset value
Minute counterTCHD[5:0] (D[5: 0]) / Clock timer minute register (0x40155) 0 to 59
Hour counter TCDD[4:0] (D[4:0]) / Clock timer h our register (0x40156) 0 to 23
Day counter TCND[15:0](D[7:0]) / Clock timer day (high-order) regis ter (0x40158)
(D[7:0]) / Clock timer day (low -orde r) register (0x40157) 0 to 65535
When using the clock timer as an RTC, be sure to set these counter values before starting operating of the
cl oc k time r. For the day co un t e r, set a num be r of days starting from the reference day (e.g., Jan uary 1, 1990).
III PERIPHERAL BLOCK: CLOCK TIMER
S1C33L03 FUNCTION PART EPSON B-III-7-3
A-1
B-III
CTM
RU N/STOP the clock timer
The clock timer starts counting when "1" is written to TCRUN (D0) / Clock timer Run/Stop register
(0x40151) and stops counting when "0" is written.
When the clock timer is made to RUN, the 256-Hz clock input is enabled at a falling edge of the low-speed
(OSC1) oscillation clock pulse, and the 8-bit binary counter counts up at each falling edge of this 256-Hz
clock. Figure 7.2 shows the operation of the 8-bit binary counter.
256 Hz
128 Hz
64 Hz
32 Hz
16 Hz
8 Hz
4 Hz
2 Hz
1 Hz
32 Hz interrupt
8 Hz interrupt
2 Hz interrupt
1 Hz interrupt
f
OSC1
/128
TCD0
TCD1
TCD2
TCD3
TCD4
TCD5
TCD6
TCD7
Figur e 7.2 Timing Char t of 8-Bit Binary Counter
The 8-b it binary counter outputs a 1-Hz signal in its final stage.
The second counter counts the 1-Hz signal thus output. When it counts 60 seconds, the counter outputs a 60-
second signal and is reset to 0 seconds.
Sim ilarly, the m inute and hour cou nters count 60 m inu tes and 24 hours, respecti vely, using the signals output
by each preceding counter.
The day counter is a 16-bit binary counter and can count up to 65,536 days using the 24-hour signal output by
the hour c ounter.
One of the following signals output by each counter can be selected to generate an interrupt:
32 H z, 8 Hz , 2 Hz, 1 Hz (1 second) , 1 minute, 1 hour, 1 day
If "0" is written to TCRUN, the clock timer is stopped at a rising edge of the low-speed (OSC1) oscillation
clock to prevent device malfunction caused by the concurrent termination of counting (falling edge of the
256-Hz clock).
Even when the clock timer is stopped, each counter retains the data set at that point. When the timer is made
to RUN again while in that state, each counter restarts counting from the retained value.
Reading out counter data
The data in each counter can be read out in a software as binary data.
Table 7.2 Reading Out Counter Data
Counter Counter data
1 Hz to 128 Hz TCD[7:0] (D[7:0]) / Clock timer divider register (0x40153)
Second counter TCMD[5:0] (D[5:0]) / Clock timer second counter (0x40154)
Minute counterTCHD[5:0] (D[5:0]) / Clock timer minute cou nte r (0x40155)
Hour counter TCDD[4:0] (D[4 : 0]) / Clock timer hour counte r (0x40156)
Day counter TCND[15:0](D[7:0]) / Clock timer d ay (high-order) counter (0 x40158)
(D[7:0]) / Clock timer day (low -orde r) counter (0x40157)
Data is read directly from the counter during operation. For this reason, a counter can overflow while reading
data from each counter, so the data thus read may not be exact. For example, if the 8-bit binary counter is read
at 0xFF and then overflows before reading the next seconds counter, the value of the seconds counter is its
count plus the one second that has elapsed since the 8-bit binary counter was read. To prevent this problem,
try reading out each counter several times and make sure data has not been modified.
III PERIPHERAL BLOCK: CLOCK TIMER
B-III-7-4 EPSON S1C33L03 FUNCTION PART
Setting alarm function
The clock timer has an alarm function, enabling an interrupt to be generated at a specified time and day. This
specification can be made in minutes, hours, and days for each alarm or a combination of multiple alarms.
Use TCASE[2 :0] ( D[4:2) / Clock timer interrupt control register (0x40152) for this specification.
Table 7.3 Alarm Factor Selection
TCASE2 TCASE1 TCASE0 Alarm factor
XX1Minutes alarm
X1XHours alarm
1XXDay alarm
000None
For example, if TCASE is set to "001", only a minutes alarm is enabled and an alarm is generated at a
specified minute every hour. If TCASE is set to "111", an alarm is generated on each specified day at each
specified hour and minute. If alarms are not to be used, set TCASE to "000".
An interrupt can be generated every minute, every hour, and every day through the use of the counter's
interrupt function instead of the alarm function.
To spe cify a day, hours, and minutes, use the regist ers shown be low :
To specify mi nutes: TCCH[ 5:0] (D[5:0]) / Minute-comparison data register (0x40159) 0 to 59 minutes*
To specify hours: TCCD[4:0] (D[4:0]) / Hour-comparison data register (0x4015A) 0 to 23 hours*
To specify day: TCCN [4:0] (D[4:0]) / Day- compari son data register 0x4015B) 0 to 31 days after
∗The minute- compari son da ta register (6 bits) and hour-comparison data register (5 bits) can be set for up to 63
minutes and 31 ho urs, respectively. Note t hat even when the data set in these registers exceeds 59 minutes or
23 hour s, the data is not considered invalid.
The values set in these registers are compared with those of each counter, and when they match, the alarm
factor generation flag TCAF (D0) / Clock timer interrupt control register (0x40152) is set to "1". If clock
timer interrupts have been enabled using the interrupt controller, an interrupt is generated when the flag is set.
The day-comparison data register is a 5-bit register, and its value is compared with the five low-order bits of
the day counter. Therefore, an alarm can be generated for up to 31 days after the register is set.
Inter ru pt Fu nc tion
Clock timer interrupt factors
The clock timer can generate an inte rru pt usin g a 32-H z, 8- H z, 2-Hz, 1-Hz (1-secon d), 1-minute, 1-hour, or 1-
day signal. The interr upt factor to be used from am ong these signals can be selected using the interrupt factor
selection bit TCISE[2:0] (D[7:5]) / Clock timer interrupt control register (0x40152).
Table 7.4 Selecting Interrupt Factor
TCISE2 TCISE1 TCISE0 Interrupt factor
111None
1101 day
1011 hour
1001 minute
0111 Hz
0102 Hz
0018 Hz
00032 Hz
An interrupt factor is generated at intervals of a selected signal (each falling edge of the signal).
If interrupts based on these signals are not to be used, set TCISE to "111".
When a selected interrupt factor is generated, the interrupt factor generation flag TCIF (D1) / Clock timer
interrupt control register (0x40152) is set to "1". At the same time, the clock timer interrupt factor flag FCTM
(D1) / Port input 4–7, clock timer, A/D interrupt factor flag register (0x40287) also is set to "1". At this time,
if the interrupt conditions set by the interrupt control registers are met, an interrupt to the CPU is generated.
III PERIPHERAL BLOCK: CLOCK TIMER
S1C33L03 FUNCTION PART EPSON B-III-7-5
A-1
B-III
CTM
An interrupt can be generated on a specified alarm day at a specified time as described in the preceding
section.
Interrupts generated by a signal and those generated by an alarm can both be used. However, since the clock
timer has only one interrupt factor flag, it is the same interrupt that is generated by the timer. Therefore, if
both types of interrupts are used, when an interrupt occurs, read the interrupt factor generation flag TCIF and
al arm fa ctor g ene ra tio n flag TCAF to dete rm in e which fa cto r has g ene ra ted the inte rru pt.
Once the factor generation flag is set to "1", it remains set until it is reset by writing "1" in the software. After
confirming that the flag is set, write "1" to reset it.
The interrupt factor generation flag TCIF and alarm factor generation flag TCAF should be reset after at least
4 ms hav e passed from ge neration of an interrupt or an alarm.
Note: To prevent generation of an un wanted inter rupt, disable the clock tim er int errupt before selec ti ng
the interrupt and alarm factors. Then, before reenabling the interrupt, reset each factor generation
flag and the interrupt factor flag.
Control registers of the interrupt controller
The following lists the clock timer interrupt control registers:
Interrupt factor flag: FCTM (D1) / Port input 4–7, clock timer, A/D interrupt factor flag register (0x40287)
Interrupt enable: ECTM (D1) / Port input 4–7, clock timer, A/D interrupt enable register (0x40277)
Interrupt level: PCTM[2:0] (D[2:0]) / Clock timer interrupt priority register (0x4026B)
When an interrupt factor occurs, the clock timer sets the interrupt actor flag to "1" as described above. At this
time, if the interrupt enable register bit is set to "1", an interrupt request is generated.
Interrupts can be disabled by leaving the interrupt enable register bit reset to "0". The interrupt factor flag is
always set to "1" when an interrupt factor is generated, regardless of the setting of the interrupt enable register
(even when it is set to "0").
The interrupt priority register sets the priority levels (0 to 7) of interrupts. An interrupt request to the CPU is
accepted on the condition that no other interrupt request has been generated that is of a higher priority.
It is only when the PSR's IE bit = "1" (interrupts enabled) and the set value of the IL is smaller than the clock
timer interrupt level set by the interrupt priority register that a clock timer interrupt request is actually
accepted by the CPU.
For details on these interrupt control registers, as well as the device operation when an interrupt has occurred,
refer to "ITC (Interrupt Controller)".
Note that the clock timer interrupt factor does not have a function to invoke an intelligent DMA.
Trap vectors
The trap vector addresses for the clock-timer interrupt by default are set to 0x0C00104.
The trap table base address can be changed using the TTBR registers (0x48134 to 0x48137).
III PERIPHERAL BLOCK: CLOCK TIMER
B-III-7-6 EPSON S1C33L03 FUNCTION PART
Examples of Use of Clock Timer
The following shows examples of use of the clock timer and how to control the timer in each case.
To use the clock timer as a timer/counter
Ex ample in whic h while the CPU is inactive, the clock timer is kept operating in order to start again the CPU
after a specified length of time has elapsed (e.g., three days):
1. Make sure the low-speed (OSC1) oscillatio n circuit is osci llatin g stab ly (S O SC1 = "1").
Wait for approximately three seconds after the oscillation starts for its oscillation to stabilize.
2. Disable the clock timer interrupt using the interrupt controller (ECTM = "0").
3. Stop the clock timer and set "3 days" in the day-comparison register (TCRUN = "0", TCCN = "3").
4. Choose a "day-specified alarm" using the alarm-factor select bit and set "none" in the interrupt-factor
select bit (TCASE = "100", TCISE = "1 11").
5. Reset the interrupt factor and alarm factor generation flags (FCTM = "0", TCAF = "0").
6. Reenab le the c lock timer interrupt using the interrupt controller (ECTM = "1").
7. Swit ch the CPU operating clock to the low-speed (OSC1) clock (CLKCHG = "0").
8. Turn off the h igh -s peed (O S C3 ) osci lla tion circu i t (SO SC3 = "0").
9. Reset the clock timer (TCRST = "0").
10.Start the clock timer (TCRUN = "1").
11.Execute the halt instruction to stop the CPU.
:
Wait until an interrupt is generated by a day-specified alarm from the clock timer. When an interrupt
occurs, the CPU starts up using the OSC1 clock.
:
12.If necessary, turn on the high-speed (OSC3) oscillation circuit and change the CPU operating clock back
to the OSC3 clock.
In the above example, if the device is reset before a three-day period has elapsed, the device operates as
follows:
• The CPU starts up using the OSC3 clock.
• The clock timer counters are not reset. They remain in the RUN state.
The time during whic h the CPU has been idle can be checked by reading out the clock timer counters.
For using the clock timer as RTC
Ex ampl e in which the clock timer is kept operating and an alarm is generated at 10:00 A.M. every day:
1. Disable the clock timer interrupt using the interrupt controller (ECTM = "0").
2. Stop the clock timer (TCRUN = "0").
3. Reset the clock timer (TCRST = "1").
4. Set the current day and time in the minute (TCHD), hour (TCDD), and day (TCND) counters. For the
day cou nter, set a num ber of days s tarting from the reference day (e.g., January 1, 1990). W hen the count
is read, it is converted into the current date by the software.
5. Set "10 :00" i n the hour-com pare register (TCCD = "0x0A").
6. Select an a "hour-specified alarm" using the alarm factor select bit, and set "none" in the interrupt factor
select bit (TCASE = "010", TCISE = "1 11").
7. Reset the interrupt factor and alarm-factor generation flags (FCTM = "1", TCAF = "0").
8. Reenab le the c lock timer interrupt using the interrupt controller (ECTM = "1").
9. Start the clock timer (TCRUN = "1").
:
The clock timer is made to generate an interrupt at 10:00 every day by an hour-specified alarm.
:
In the above example, if any interrupt factor other than an alarm is selected, an interrupt is also generated by
that interrupt factor. To determine which factor caused the interrupt generated, read the interrupt factor
generation flag TCIF and alarm factor generation flag TCAF. If TCAF is set to 1, the interrupt has been
caused by an alarm. If you select an interrupt factor (other than a 1-day factor) along with the hour-specified
alarm, the selected interrupt factor occurs at the same time as the alarm factor.
III PERIPHERAL BLOCK: CLOCK TIMER
S1C33L03 FUNCTION PART EPSON B-III-7-7
A-1
B-III
CTM
I/O Memo ry of Clock Ti mer
Table 7.5 shows t he control bits of the clock timer.
Table 7.5 Control Bits of Clock Timer
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
TCRST
TCRUN
D7–2
D1
D0
reserved
Clock timer reset
Clock timer Run/Stop control
–
X
X
–
W
R/W
0 when being read.
0 when being read.
0040151
(B) 1 Reset 0 Invalid
1 Run 0 Stop
–Clock timer
Run/Stop
register
TCISE2
TCISE1
TCISE0
TCASE2
TCASE1
TCASE0
TCIF
TCAF
D7
D6
D5
D4
D3
D2
D1
D0
Clock timer interrupt factor
selection
Clock timer alarm factor selection
Interrupt factor generation flag
Alarm factor generation flag
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W Reset by writing 1.
Reset by writing 1.
0040152
(B)
1 Generated 0
Not generated
1 Generated 0
Not generated
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
TCISE[2:0] Interrupt factor
None
Day
Hour
Minute
1 Hz
2 Hz
8 Hz
32 Hz
1
X
X
0
X
1
X
0
X
X
1
0
TCASE[2:0] Alarm factor
Day
Hour
Minute
None
Clock timer
interrupt
control register
TCD7
TCD6
TCD5
TCD4
TCD3
TCD2
TCD1
TCD0
D7
D6
D5
D4
D3
D2
D1
D0
Clock timer data 1 Hz
Clock timer data 2 Hz
Clock timer data 4 Hz
Clock timer data 8 Hz
Clock timer data 16 Hz
Clock timer data 32 Hz
Clock timer data 64 Hz
Clock timer data 128 Hz
X
X
X
X
X
X
X
X
R
R
R
R
R
R
R
R
0040153
(B) 1 High 0 Low
1 High 0 Low
1 High 0 Low
1 High 0 Low
1 High 0 Low
1 High 0 Low
1 High 0 Low
1 High 0 Low
Clock timer
divider register
–
TCMD5
TCMD4
TCMD3
TCMD2
TCMD1
TCMD0
D7–6
D5
D4
D3
D2
D1
D0
reserved
Clock timer second counter data
TCMD5 = MSB
TCMD0 = LSB
–
X
X
X
X
X
X
–
R0 when being read.0040154
(B) –
0 to 59 seconds
Clock timer
second
register
–
TCHD5
TCHD4
TCHD3
TCHD2
TCHD1
TCHD0
D7–6
D5
D4
D3
D2
D1
D0
reserved
Clock timer minute counter data
TCHD5 = MSB
TCHD0 = LSB
–
X
X
X
X
X
X
–
R/W 0 when being read.0040155
(B) –
0 to 59 minutes
Clock timer
minute register
0 to 23 hours
–
TCDD4
TCDD3
TCDD2
TCDD1
TCDD0
D7–5
D4
D3
D2
D1
D0
reserved
Clock timer hour counter data
TCDD4 = MSB
TCDD0 = LSB
–
X
X
X
X
X
–
R/W 0 when being read.0040156
(B)
Clock timer
hour register –
0 to 65535 days
(low-order 8 bits)
TCND7
TCND6
TCND5
TCND4
TCND3
TCND2
TCND1
TCND0
D7
D6
D5
D4
D3
D2
D1
D0
Clock timer day counter data
(low-order 8 bits)
TCND0 = LSB
X
X
X
X
X
X
X
X
R/W0040157
(B)
Clock timer
day (low-order)
register
0 to 65535 days
(high-order 8 bits) X
X
X
X
X
X
X
X
R/WTCND15
TCND14
TCND13
TCND12
TCND11
TCND10
TCND9
TCND8
D7
D6
D5
D4
D3
D2
D1
D0
Clock timer day counter data
(high-order 8 bits)
TCND15 = MSB
0040158
(B)
Clock timer
day (high-
order) register
III PERIPHERAL BLOCK: CLOCK TIMER
B-III-7-8 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
0 to 59 minutes
(Note) Can be set within 0–63.
–
TCCH5
TCCH4
TCCH3
TCCH2
TCCH1
TCCH0
D7–6
D5
D4
D3
D2
D1
D0
reserved
Clock timer minute comparison
data
TCCH5 = MSB
TCCH0 = LSB
–
X
X
X
X
X
X
–
R/W 0 when being read.0040159
(B) –Clock timer
minute
comparison
register
0 to 23 hours
(Note) Can be set within 0–31.
–
TCCD4
TCCD3
TCCD2
TCCD1
TCCD0
D7–5
D4
D3
D2
D1
D0
reserved
Clock timer hour comparison data
TCCD4 = MSB
TCCD0 = LSB
–
X
X
X
X
X
–
R/W 0 when being read.004015A
(B) –Clock timer
hour
comparison
register
0 to 31 days
–
TCCN4
TCCN3
TCCN2
TCCN1
TCCN0
D7–5
D4
D3
D2
D1
D0
reserved
Clock timer day comparison data
TCCN4 = MSB
TCCN0 = LSB
–
X
X
X
X
X
–
R/W 0 when being read.
Compared with
TCND[4:0].
004015B
(B) –Clock timer
day
comparison
register
–
0 to 7
–
PCTM2
PCTM1
PCTM0
D7–3
D2
D1
D0
reserved
Clock timer interrupt level –
X
X
X
–
R/W Writing 1 not allowed.004026B
(B)
Clock timer
interrupt
priority register
–
EP7
EP6
EP5
EP4
ECTM
EADE
D7–6
D5
D4
D3
D2
D1
D0
reserved
Port input 7
Port input 6
Port input 5
Port input 4
Clock timer
A/D converter
– –
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.0040277
(B) 1 Enabled 0 Disabled
Port input 4–7,
clock timer,
A/D interrupt
enable register
–
FP7
FP6
FP5
FP4
FCTM
FADE
D7–6
D5
D4
D3
D2
D1
D0
reserved
Port input 7
Port input 6
Port input 5
Port input 4
Clock timer
A/D converter
– –
X
X
X
X
X
X
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.0040287
(B) 1 Factor is
generated 0 No factor is
generated
Port input 4–7,
clock timer, A/D
interrupt factor
flag register
TCRST: Clo ck ti mer re se t (D1 ) / Clo ck timer R u n/ S t op register (0x40151)
Resets the clock timer.
Write "1": The clock timer is reset
Write "0": Invalid
Read: Alwa ys "0"
The clock timer is reset by writing "1" to TCRST when the timer is inactive. All timer counters are cleared to "0".
The clock timer cannot be reset when in the RUN state, nor can it be reset at the same time it is made to RUN
through the execution of one write to address 0x40151. (The clock timer is started, but not reset.) In this case, first
reset the clock timer and then use another instruction to RUN the clock timer. When the counters are cleared as the
clock timer is reset, an interrupt may be generated, depending on the register settings. Therefore, before resetting
the clock timer, first disable the clock timer interrupt, and after resetting the clock timer, reset the interrupt factor
fl ag and th e inte rru pt fa cto r and alarm fa cto r g ene ra tio n flag s.
Writing "0" to TCRST results in No Operation. Since this TCRST is a write-only bit, its value when read is always
"0".
The clock timer is not reset by an initial reset.
III PERIPHERAL BLOCK: CLOCK TIMER
S1C33L03 FUNCTION PART EPSON B-III-7-9
A-1
B-III
CTM
TCRUN: C lo ck timer RUN/STOP control (D0) / Clock timer Run/Stop register (0x40151)
Controls the RUN/STOP of the clock timer.
Write "1": RUN
Write "0": STOP
Read: Valid
The clock timer is made to start counting by writing "1" to the TCRUN register and made to stop by writing "0".
The tim er data is retained even in the STOP state. The timer can also be made to start counting from the retained
data by changin g its state from STOP to RUN.
The TCRUN register is not initialized at initial reset.
TCD7–TCD0:1–128 Hz counter data (D[7:0 ]) / C lo ck timer d ivide r register (0 x4015 3)
TCMD5–TCMD0:Second counter data (D[5:0]) / Clock timer second register (0x40154)
TCHD5–TCHD0:Minute counter data (D[5 :0 ]) / C lo ck timer m in ut e regist er (0 x4 0 155)
TCDD4–TCDD0:Hour counter data (D[4:0 ]) / C lo ck time r h our regi st er (0 x4 0 156)
TCND15–TCND0:Day counter data (D[7:0 ]) / Cl o ck timer d ay (hig h- or der) re gister (0 x4 0 15 8)
(D[7 :0 ]) / C lo ck time r d ay (l ow-o rd er ) regi ster (0 x4 0 15 7)
Dat a can be read out from each counter.
The minute, hour, and day counters allow data to be written to, in addition to being read out.
The 1–12 8 H z count er and seconds counter are read-only, so writing to these registers is ignored.
The unus ed high-order bits at each address of the second, minute, and hour counter data are always "0" when read
out.
The cou nter data is not initialized at initial reset.
TCCH5–TCCH0:Minute-comparison data (D[5:0]) / Clock timer minute-comparison register (0x40159)
TCCD4–TCCD0:Hour-compari son da ta (D[4:0] ) / Cloc k timer hour- compar ison r egister (0x 4015A )
TCCN4–TCCN0:Day-comp ariso n d ata (D[4 :0 ]) / C lo ck timer d ay -c omparison register (0 x4015B)
Set a day on which and a time at which an alarm is to be generated.
The comparison data register corresponding to the alarm factor selected using the TCASE register is compared
with the counter data, and when the data matches, an alarm interrupt request is generated.
The day-comparison data is compared with the 5 low-order bits of the day counter.
Each register can be read out.
These registers are not initialized at initial reset.
TCISE2–TCISE0: Interrupt factor selection (D[7:5]) / Clock timer interrupt control register (0x40152)
Selects the factor for which the clock timer interrupt is to be generated.
Table 7.6 Selecting Interrupt Factor
TCISE2 TCISE1 TCISE0 Interrupt factor
111None
1101 day
1011 hour
1001 minute
0111 Hz
0102 Hz
0018 Hz
00032 Hz
When the clock timer interrupt is enabled, an interrupt is generated cyclically at each falling edge of the selected
signal. If you the interrupt caused by these factors is not be used set TCISE to "111".
TC ISE is not initialized at initial reset.
III PERIPHERAL BLOCK: CLOCK TIMER
B-III-7-10 EPSON S1C33L03 FUNCTION PART
TCASE2–TCASE0: Alarm factor select register (D[4:2]) / Clock timer interrupt control register (0x40152)
Selects the factor for which an alarm is to be generated.
Table 7.7 Selecting Al arm Fac tor
TCASE2 TCASE1 TCASE0 Alarm factor
XX1Minute alarm
X1XHour alarm
1XXDay alarm
000None
Use t he TCASE2, TCASE1, and TCASE0 bit s to select a day, hour, and minute alarm, respectively. It is therefore
possible to select multiple alarm factors. When one of these bits is set to "1", the contents of the comparison data
register that corresponds to the selected alarm factor is compared with the counter. If the comparison data of all
selected alarm factors matches the counter data, an alarm interrupt request is generated. The comparison data
register from which the alarm factor is unselected by writing "0" is not compared with the counter data.
TCASE is not initialized at initial reset.
TCIF: Interrupt factor generation flag (D1) / Clock timer interrupt control register (0x40152)
Indicates whe the r an inte rru pt facto r h as o ccu rr ed.
Read "1": Interrupt facto r has o ccu rred
Read "0": No inte rrupt fa ctor h as o ccu rred
Write "1": Flag is reset
Write "0": Invalid
TC IF is set to "1" when an interrupt factor selected using TCISE occurs. Since there is only one source for the
clock timer interrupt, use this flag to differentiate it from interrupts caused by an alarm.
Once set to "1", TCIF remains set until it is reset by writing "1".
TC IF is not initialized at initial reset.
This bit does not affect generation of an i nterrupt even if it is set to "1" or "0".
TCAF: Alarm factor generation flag (D0) / Clock timer interrupt control register (0x40152)
Indicates whe the r an al arm facto r h as o ccu rred .
Read "1": Alarm facto r has o ccu rred
Read "0": No alarm fa cto r has o ccurred
Write "1": Flag is reset
Write "0": Invalid
TC AF is set to "1" when all alarm factors selected using the TCASE register occur. Since there is only one source
for the clock timer interrupt, use this flag to differentiate it from interrupts due to other interrupt factors.
Once set to "1", TCAF remains set until it is reset by writing "1".
TC AF is not initialized at initial reset.
This bit does not affect generation of an alarm even if it is set to "1" or "0".
PCTM2–PCTM0: Clock timer interrupt level (D[2:0]) / Clock timer interrupt priority register (0x4026B)
Sets the priority level of the clock timer interrupt between 0 and 7.
At i nitial reset, PCTM becomes indeterminate.
III PERIPHERAL BLOCK: CLOCK TIMER
S1C33L03 FUNCTION PART EPSON B-III-7-11
A-1
B-III
CTM
ECTM: Cloc k tim er interrupt enable (D1) / Port inp ut 4– 7, clock tim er , A/D i nter r upt en abl e r egis ter ( 0x402 77 )
Enabl es or disables generation of an interrupt to the CPU.
Write "1": Inte rrupt enabled
Write "0": Inte rrupt disabled
Read: Valid
This bit controls the clock timer interrupt. The interrupt is enabled by setting ECTM to "1" and is disabled by
setting it to "0".
At i nitial reset, ECTM is set to "0" (interrupt disabled).
FCTM: Clock timer interrup t factor flag (D1) / Port input 4–7, clock timer, A/D interrupt factor flag register (0x40287)
Indicates whether the clock timer interrupt factor has occurred.
When read
Read "1": Interrupt facto r has o ccu rred
Read "0": No inte rrupt fa ctor h as o ccu rred
When written using the rese t-onl y m etho d (d ef au lt)
Write "1": Interrupt factor flag is reset
Write "0": Invalid
When written using the read /w rite m et ho d
Write "1": Interrupt flag is set
Write "0": Interrupt flag is reset
FC TM is set to "1" when the selected interrupt factor or alarm factor occurs.
At t his time, if the following conditions are met, an interrupt to the CPU is generated:
1. The corresponding interrupt enable register bit is set to "1".
2. No other interrupt request of a higher interrupt priority is generated.
3. The IE bit of the PSR is set to "1" (interrupt enabled).
4. The corresponding interrupt priori ty register is set to a value higher than the CPU interrupt level (IL).
The interrupt factor flag is always set to "1" when an interrupt factor occurs, no matter how the interrupt enable and
inte rrupt p rio rity regi ste rs are set.
For the next interrupt to be accepted after an interrupt has occurred, it is necessary that the interrupt factor flag be
reset, and that the PSR be set again (by setting the IE bit to "1" after setting the IL to a value lower than the level
indicated by the interrupt priority register, or by executing the reti instruction).
The interrupt factor flag can be reset only by writing to it in the software. Note that if the PSR is set again to accept
generated interrupts (or if the reti instruction is executed) without the interrupt factor flag being reset, the same
interrupt occurs again. Note also that the value to be written to reset the flag is "1" when the reset-only method
(RSTONLY = " 1" ) is used, and "0" when the rea d/ write me thod (RSTONLY = "0" ) is used.
The FCTM flag becomes indeterminate at initial reset, so be sure to reset it in the software.
III PERIPHERAL BLOCK: CLOCK TIMER
B-III-7-12 EPSON S1C33L03 FUNCTION PART
Pr ogramming Notes
(1) The low-speed (OSC1) oscillation circuit, which is the clock source for the clock timer, requires a muxmum
of three seconds for its oscillation to stabilize after it is started up. Therefore, immediately after power-on,
wai t un til the oscillation stabilizes before starting the clock timer.
(2) At initial reset, the clock timer counter data, the setup contents of alarms, and control bits, including
RU N/STOP, are not initialized. Therefore, always initialize the clock timer in the software following power-
on.
(3) The clock timer reset bit TCRST and the clock timer RUN/STOP control bit TCRUN are located at the same
address (0x40151). However, the clock timer cannot be reset at the same time it is set to RUN by writing "1"
to both. In this case, the reset input is ignored and the timer starts counting up from the counter values then in
effect. When resetting the timer, always make sure TCRUN = "0" (timer stopped).
(4) When the counters are cleared as the clock timer is reset, an interrupt may be generated depending on the
register settings. Therefore, before resetting the clock timer, first disable the clock timer interrupt and, after
resettin g th e cloc k time r, re se t the inte rru pt fa cto r flag and th e inte rru pt fa cto r g ene ra tion an d al arm fa cto r
generation flag s.
(5) To prevent generation of an unwanted interrupt, disable the clock timer interrupt before selecting the interrupt
and alarm factors. Then, before reenabling the interrupt, reset each factor generation flag and the interrupt
factor flag .
(6) The interrupt factor flag (FCTM) becomes indeterminate at initial reset. To prevent generation of an
unw anted interrupt, be sure t o reset the flag in a program.
(7) To prevent regeneration of interrupts with the same factor after an interrupt has occurred, be sure to reset the
interrupt factor flag (FCTM) before setting the PSR again or executing the reti instruction.
III PERIPHERAL BLOCK: SERIAL I NTERFACE
S1C33L03 FUNCTION PART EPSON B-III-8-1
A-1
B-III
SIF
III-8 SERIAL INTERFACE
Configuration of Serial Interfaces
Features of Serial Interfaces
The Peripheral Block contains four channels (Ch.0, Ch.1, Ch.2 and Ch.3) of serial interfaces, the features of which
are described below. The functions of these four serial interfaces are the same.
•A clock-synchronized or asynchronous mode can be selected for the transfer method.
Clock-synchronized mode
Data length: 8 bits, fixed (No start, stop, and parity bits)
Receive error: An overrun error can been detected.
Asynchronous mode
Data length: 7 or 8 bits, selectable
Receive erro r: O ve rru n, fram in g, o r parity er rors ca n been dete cted.
Start bit: 1 bit, fixed
Stop bit: 1 or 2 bi ts, selectable
Parity bit: Even, odd, or none; selectable
Since the transmit and receive units are independent, full-duplex communication is possible.
•Baud-rate setting: Any desired baud rate can be set by selecting the prescaler's division ratio, setting the 8-bit
programmable timer, or using external clock input (asynchronous mode only).
•The receive and transmit units are constructed with a double-buffer structure, allowing for successive receive and
transm it o per ation s.
•Data transfers using IDMA or HSDMA are possible.
•Three types of interrupts (transmit data empty, receive data full, and receive error) can be generated.
Figure 8.1 shows the configuration of the serial interface (one channel).
Control registers
Transmit unit
Data buffer
and
shift register
Interrupt
control circuit
Start bit
detection circuit Clock
control circuit
Transmit data buffer empty
interrupt request
Receive data buffer full
interrupt request
Receive error
interrupt request
SOUTx
#SCLKx
#SRDYx
SINx
Internal data bus
Receive unit
Data buffer
and
shift register
Serial output
control circuit
Serial input
control circuit
Ready signal
control circuit
8-bit programmable timer output
Figur e 8.1 Configuration of Serial Interface
Note: Ch.0 to Ch.3 ha ve the sa me configuratio n and the same f unction. The signal and control bit
nam es are suffixed by a 0, 1, 2, or 3 to ind icate t he chan nel num ber, enabli ng discrimination
betwee n chan nels 0 to 3. In this manua l, however, ch anne l numbers 0 to 3 ar e replaced with "x"
unless discrimi nation is necessary, because ex planations are comm on to all four channels.
III PERIPHERAL BLOCK: SERIAL I NTERFACE
B-III-8-2 EPSON S1C33L03 FUNCTION PART
I/O Pins of Serial Interface
Table 8.1 lists t he I/O pins used by the serial interface.
Table 8.1 Serial-Interface Pin Configuration
Pin name I/O Function Functi on se lect bit
P00/SIN0 I/O I/O port / Serial IF Ch.0 data input CFP00(D0)/P0 function select register(0x402D0)
P01/SOUT0 I/O I/O port / Serial IF Ch.0 data output CFP01(D1)/P0 function select register(0x402D0)
P02/#SCLK 0 I/O I/O port / Serial IF Ch.0 clock input/output CFP02(D2)/P0 function select register(0x402D0)
P03/#SRDY0 I/O I/O port / Serial IF Ch.0 ready input/output CFP03(D3)/P0 function select register(0x402D0)
P04/SIN1/
#DMAACK2 I/O I/O port / Serial IF Ch.1 data input
/ #DMAACK2 signal output CFP04(D4)/P0 function select register(0x402D0)
CFEX4(D4)/Port function extension register(0x402DF)
P05/SOUT1/
#DMAEND2 I/O I/O port / Serial IF Ch.1 data output
/ #DMAEND2 signal output CFP05(D5)/P0 function select register(0x402D0)
CFEX5(D5)/Port function extension register(0x402DF)
P06/#SCLK1/
#DMAACK3 I/O I/O port / Serial IF Ch.1 clock input/output
/ #DMAACK3 signal output CFP06(D6)/P0 function select register(0x402D0)
CFEX6(D6)/Port function extension register(0x402DF)
P07/#SRDY1/
#DMAEND3 I/O I/O port / Serial IF Ch.1 ready input/output
/ #DMAEND3 signal output CFP07(D7)/P0 function select register(0x402D0)
CFEX7(D7)/Port function extension register(0x402DF)
P27/TM5/SIN2 I/O I/O port / Serial IF Ch.2 data input CFP27(D7)/Function select register(0x402D8)
SSIN2(D0)/Function select register(0x402DB)
P26/TM4/SOUT2 I/O I/O port / Serial IF Ch.2 data output CFP26(D6)/Function select register(0x402D8)
SSOUT2(D1)/Function select register(0x402DB)
P25/TM3/#SCLK2 I/O I/O port / Serial IF Ch.2 serial clock input/output CFP25(D5)/Function select register(0x402D8)
SSCLK2(D2)/Function select register(0x402DB)
P24/TM2/#SRDY2 I/O I/O port / Serial IF Ch.2 ready input/output CFP24(D4)/Function select register(0x402D8)
SSRDY2(D3)/Function select register(0x402DB)
P33/#DMAACK1/
SIN3 I/O I/O port / Serial IF Ch.3 data input CFP33(D3)/Function select register(0x402DC)
SSIN3(D0)/Function select register(0x402D7)
P16/EXCL5/
#DMAAND1/
SOUT3
I/O I/O port / Serial IF Ch.3 data output CFP16(D6)/Function select register(0x402D4)
SSOUT3(D1)/Function select register(0x402D7)
P15/EXCL4/
#DMAAND0/
#SCLK3
I/O I/O port / Serial IF Ch.3 serial clock input/output CFP15(D5)/Function select register(0x402D4)
SSCLK3(D2)/Function select register(0x402D7)
P32/#DMAACK0/
#SRDY3 I/O I/O port / Serial IF Ch.3 ready input/output CFP32(D2)/Function select register(0x402DC)
SSRDY3(D3)/Function select register(0x402D7)
SINx (serial-dat a input pin)
This pin is used to input serial data to the device, regardless of the transfer mode.
SOUTx (serial-data output pin)
This pin is used to output serial data from the device, regardless of the transfer mode.
#SCLKx (clock input/output pin)
This pin is used to input or output a clock.
In the clock-synchronized slave mode, it is used as a clock input pin; in the clock-synchronized master mode,
it is used as a clock output pin.
In the asynchronous mode, this pin is used as clock input when an external clock is used. This pin is not used
when the internal clock is used, so it can be used as an I/O port.
#SRDYx (ready-signal input/output pin)
This pin is used to input or output the ready signal that is used in the clock-synchronized mode.
In the clock-synchronized slave mode, it is used as a ready-signal output pin; in the clock-synchronized
master mode, it is used as a ready-signal input pin.
This pin is not used in the asynchronous mode, so it can be used as an I/O port.
Method for setting t he serial-interface input/output pins
All of the pins used in the serial interface are shared with I/O ports. At cold start, they are all set for I/O port
pins P0x (functio n select bit Pxx, CFPx x = "0"). When using the serial interface, make function select bit
settings for the pins used, according to the channel and transfer mode to be used.
At ho t start, the pins retain their status from prior to the reset.
III PERIPHERAL BLOCK: SERIAL I NTERFACE
S1C33L03 FUNCTION PART EPSON B-III-8-3
A-1
B-III
SIF
Setting Tra nsfer Mode
The transfer mode of the serial interface can be set using SMDx[1:0] individually for each channel as shown in
Table 8.2 below.
Table 8.2 Transfer Mode
SMDx1 SMDx0 Transfer mode
118-bit as ynchr ono us mode
107-bit as ynchr ono us mode
01Clock-synchronized slave mode
00Clock-synchronized master mode
At i nitial reset, SMDx becomes indeterminate, so be sure to initialize it in the software.
When using the IrDA interface, set the transfer mode for the asynchronous 7-bit or asynchronous 8-bit mode.
The input/output pins are configured differently, depending on the transfer mode. The pin configuration in each
mode is shown in Table 8.3.
Table 8.3 Pin Configuration by Transfer Mode
Transfer mode SINx SOUTx #SCLKx #SRDYx
8-bit asynchronous Data input Data output Clock input/P port P port
7-bit asynchronous Data input Data output Clock input/P port P port
Clock-synchronized slave Data input Data output Clock input Ready output
Clock-synchronized
master Data input Data output Cloc k ou tput Rea dy in put
All four pins are used in the clock-synchronized mode.
In the asynchronous mode, since #SRDYx is unused, P03 (or P07, P24, P23) can be used as an I/O (P) port. I n
addition, when an external clock is not used, P02 (or P06, P25, P15) can also be used as an I/O port.
The I/O control and data registers for the I/O ports used in the serial interface can be used as general-purpose
read/write registers.
Note: To enable the IrDA interface to be set, IRMDx[1:0] (D[1:0]) / Serial I/F IrDA register (Ch.0:
0x401E4, Ch.1: 0x401E9, Ch.2: 0x401F4, Ch.3: 0x401F9) is provided. Since these bits become
indeterminate at initial reset, be sure to initialize them by writing "00" when using as the normal
interface or "10" when using as the IrDA interface.
III PERIPHERAL BLOCK: SERIAL I NTERFACE
B-III-8-4 EPSON S1C33L03 FUNCTION PART
Clock-Synchronized Interface
Outline of Clock-Synchronized Interface
In the clock-synchronized transfer mode, 8 bits of data are synchronized to the common clock on both the transmit
and receive sides when the data is transferred. Since the transmit and receive units both have a double-buffer
structure, successive transmit and receive operations are possible. Since the clock line is shared between the
transm it an d re ce ive unit s, th e com m un ica tio n mod e is half -du pl ex .
Master an d sl ave modes
Either the clock-synchronized master mode or the clock-synchronized slave mode can be selected using
SMDx[1:0].
Clock-synchronized master mode (SMDx[ 1: 0] = "00")
In this mode, clock-synchronized 8-bit serial transfers, in which the serial interface functions as the master,
can be performed using the internal clock to synchronize the operation of the internal shift registers.
The syn chronizing clock is output from the #SCLKx pin, enabling an external (slave side) serial input/output
device to be contr olled. The #SRDY x pin is also us ed to input a signal that indicates whether the external
serial input/output device is ready to transmit or receive (when ready in a low level).
Clock-synchronized slave mod e (SMDx [1:0] = "01")
In this mode, clock-synchronized 8-bit serial transfers, in which the serial interface functions as a slave, can
be perform ed using the synchronizing clock that is supplied by an external (master side) serial input/output
device.
The syn chronizing clock is input from the #SCLKx pin for use as the synchronizing clock of the serial
interface. In addition, a #SRDYx signal indicating whether the serial interface is ready to transmit or receive
(when ready in a low level) is output from the #SRDYx pin.
Figure 8.2 shows an example of how the input/output pins are connected in the clock-synchronized mode.
Data input
Data output
Clock input
Ready output
SINx
SOUTx
#SCLKx
#SRDYx
SINx
SOUTx
#SCLKx
#SRDYx
External
serial device
(
1
)
Master mode
(
2
)
Slave mode
S1C33
Data input
Data output
Clock output
Ready input
External
serial device
S1C33
Figur e 8.2 Example of Connection in Clock-Synchronized Mode
Clock-synchronized transfer data format
In clock-synchronized transfers, the data format is fixed as shown below.
Data length: 8 bits
Start bit: None
Stop bit: None
Parity bit: None
#SCLKx
Data D0 D1 D2 D3 D4 D5 D6 D7
LSB MSB
Figur e 8.3 Clock-Synchronized Transfer Data Format
Serial data is transmitted and received starting with the LSB.
III PERIPHERAL BLOCK: SERIAL I NTERFACE
S1C33L03 FUNCTION PART EPSON B-III-8-5
A-1
B-III
SIF
Setting Cloc k-Sy nchronized Interface
When performing clock-synchronized transfers via the serial interface, the following settings must be made before
data transfer is actually begun:
1. Setting input/output pins
2. Setting the interface mode
3. Setting the transfer mode
4. Setting the input clock
5. Setting interrupts and IDMA/HSDMA
The following explains the content of each setting. For details on interrupt/DMA settings, refer to "Serial Interface
Interrupts and DMA".
Note: Always make sure the serial interface is inactive (TXE Nx and RX ENx = "0") before these settings
are made. A chan ge of settin gs during operation may caus e a m alfuncti on.
Setting input/output pins
All four pins—SINx, SOUTx, #SCLKx, and #SRDYx—are used in the clock-synchronized mode. When
using Ch.0, set CFP0[ 3:0] (D [3 :0 ]) / P 0 func tio n se le ct register (0x402D0) to "1111" and when using Ch.1,
set CFP0[7:4] (D[7:4]) to "1111". When using Ch.2, set D[3:0] / Port SIO function extension register
(0x402DB) to "1111", and when using Ch.3, set D[3:0] / Port SIO function extension register (0x402D7) to
"1111". (It is possible to use both channels.)
Setting the interface mode
IRMDx[1:0] (D[1:0]) / Serial I/F Ch.0 IrDA register (0x401E4), Serial I/F Ch.1 IrDA register (0x401E9),
Serial I/F Ch.2 IrDA register (0x401F4) or Serial I/F Ch.3 IrDA register (0x401F9) is used to set the interface
mode (normal or IrDA interface). Wri te "0 0" to IRMDx[1:0] to choose the ordinary interface. Since
IRMDx[1:0] becomes indeterminate at initial reset, it must be initialized.
Setting the transfer mode
Use SMDx to set the transfer mode of the serial interface as described earlier. When using the serial interface
as the master for clock-synchronized transfer, set SMDx[1:0] to "00"; when using the serial interface as a
slave, set SMDx[1:0] to "01".
Setting the input clock
•Clock-synchronized master mode
This mode operates using an internally derived clock. The clock source for each channel is as follows:
Ch.0: A clock output by 8-bit program m able timer 2
Ch.1: A clock output by 8-bit program m able timer 3
Ch.2: A clock output by 8-bit program m able timer 4
Ch.3: A clock output by 8-bit program m able timer 5
There fore, in order for the serial interface to be used in the clock-synchronized master mode, the following
conditions must be met:
1. The prescaler is feeding a clock to 8-bit programmable timer 2 (3).
2. The 8-bit pro gram m able tim er 2 (3) is generating a clock.
Any des ired clock frequency can be selected by setting the division ratio of the prescaler and the reload data
of the 8-bit programmable timer as necessary. The relationship between the contents of these settings and the
transfer rate is expressed by Eq . 1 below.
To ensur e that the duty ratio of the clock to be fed to the serial interface is 50%, the 8-bit programmable timer
further divides the underflow signal frequency by 2 internally. This 1/2 frequency division is factored into Eq.
1.
III PERIPHERAL BLOCK: SERIAL I NTERFACE
B-III-8-6 EPSON S1C33L03 FUNCTION PART
RLD = fPSCIN × pdr- 1 (Eq . 1)
2 × bps
RLD: Reload data register setup value of the 8-bit programmable timer
fPSCIN:Prescaler input clock frequency (Hz)
bps: Transf er ra te (b its /seco nd )
pdr: Divi sion ratio of t he presc aler
Note: The di vision rat ios selected by the prescaler differ between 8-bit pr ogram m able timers 2 and 3, so
be careful when setting the ratio.
8-bit pr ogram m able timer 2, 4: 1/2, 1/4 , 1/ 8, 1/16, 1/32, 1/6 4, 1/2048, 1/4096
8-bit pr ogram m able timer 3, 5: 1/2, 1/4 , 1/ 8, 1/16, 1/32, 1/6 4, 1/128, 1/2 56
For details on how to control the prescaler and 8-bit programmable timers, refer to "Prescaler", and "8-Bit
Programmable Timers".
The serial-i nterface control register contains an SSCKx bit to select the clock source used for the
asynchronous mode. Although this bit does not affect the clock in the clock-synchronized mode, its content
becomes indeterminate at initial reset. Therefore, be sure to initialize this bit by writing "0" (Internal clock),
even when using the serial interface in the clock-synchronized master mode.
•Clock-synchronized slave mo de
This mode operates using the clock that is output by the external master. This clock is input from the #SCLK
pin.
There fore, there is no need to control the prescaler or 8-bit programmable timer.
Initialize SSCKx by writing "1" (#SCLKx).
III PERIPHERAL BLOCK: SERIAL I NTERFACE
S1C33L03 FUNCTION PART EPSON B-III-8-7
A-1
B-III
SIF
Control and Operation of Clock-Synchronized Transfer
Transmit control
(1) Enabling transmit operation
Use the transmit-enable bit TXENx for transmit control.
Ch.0 transmit-enable: TXEN0 (D7) / Serial I/F Ch.0 control register (0x401E3)
Ch.1 transmit-enable: TXEN1 (D7) / Serial I/F Ch.1 control register (0x401E8)
Ch.2 transmit-enable: TXEN2 (D7) / Serial I/F Ch.2 control register (0x401F3)
Ch.3 transmit-enable: TXEN3 (D7) / Serial I/F Ch.3 control register (0x401F8)
When transmit is enabled by writing "1" to this bit, the clock input to the shift register is enabled (ready for
input), thus allowing for data to be transmitted. The synchronizing clock input/output of the #SCLKx pin is
also enabled (ready for input/output).
Transmit is disabled by writing "0" to TXENx.
After the function select register is set for the serial interface, the I/O direction of the #SRDY and #SCLK
pins are changed at follows:
#SRDY: When slave mode is set, a switch is made to output mode.
Otherwise, input mode is maintained.
#SCLK: When master mode is set, a switch is made to output mode.
Otherwise, input mode is maintained.
Note: In clock-synchronized transfers, the clock line is shared between the transmit and receive units, so
the c ommunica tion mode is half-duplex. Theref ore, TXENx and recei ve-enable bi t RXENx cannot
be enab led simultaneously. When t ransm itting data, fix RXENx at " 0" and do not change it du ring
a transmit oper ation.
In addition, make sure TXENx is not set to "0" during a transmit operation.
(2) Transmit p rocedure
The serial interface co nt ain s a tran sm it sh ift regi ster and a tran sm it d ata register (tran sm it data buff er), whi ch
are provided independently of those used for a receive operation.
Ch.0 transmit data: TXD0[7:0] (D[7:0]) / Serial I/F Ch.0 transmit data register (0x401E0)
Ch.1 transmit data: TXD1[7:0] (D[7:0]) / Serial I/F Ch.1 transmit data register (0x401E5)
Ch.2 transmit data: TXD2[7:0] (D[7:0]) / Serial I/F Ch.2 transmit data register (0x401F0)
Ch.3 transmit data: TXD3[7:0] (D[7:0]) / Serial I/F Ch.3 transmit data register (0x401F5)
The serial interface contains a status bit to indicate the status of the transmit data register.
Ch.0 tra nsmit data buffer empty: TDBE0 (D1) / Seria l I/F Ch.0 sta tus reg ister (0x401E2)
Ch.1 tra nsmit data buffer empty: TDBE1 (D1) / Seria l I/F Ch.1 sta tus reg ister (0x401E7)
Ch.2 tra nsmit data buffe r empty: TDBE2 (D1) / Serial I/F Ch.2 status register (0x401F2)
Ch.3 tra nsmit data buffe r empty: TDBE3 (D1) / Serial I/F Ch.3 status register (0x401F7)
This bit is reset to "0" by writing data to the transmit-data register, and set to "1" again (buffer empty) when
the data is transferred to the shift register.
The serial interface starts transmitting when data is written to the transmit data register.
The transfer status can be checked using the transmit-completion flag (TENDx).
Ch.0 transmit-completion flag: TEND0 (D5) / Serial I/F Ch.0 status register (0x401E2)
Ch.1 transmit-completion flag: TEND1 (D5) / Serial I/F Ch.1 status register (0x401E7)
Ch.2 transmit-completion flag: TEND2 (D5) / Serial I/F Ch.2 status register (0x401F2)
Ch.3 transmit-completion flag: TEND3 (D5) / Serial I/F Ch.3 status register (0x401F7)
This bit goes "1" when data is being transmitted and goes "0" when the transmission has completed.
When data is transmitted successively in clock-synchronized master mode, TENDx maintains "1" until all
data is transmitted (Figure 8.4). In slave mode, TENDx goes "0" every time 1-byte data is transmitted (Figure
8.5).
Following explains transmit operation in both the master and slave modes.
III PERIPHERAL BLOCK: SERIAL I NTERFACE
B-III-8-8 EPSON S1C33L03 FUNCTION PART
•Clock-synchronized ma ster mode
The timing at wh ich the device starts transmitting in the master mode is as follows:
When #SRDY is on a low level while TDBEx = "0" (the transmit-data register contains data written to it) or
when TDBEx is set to "0" (data has been written to the transmit-data register) while #SRDY is on a low level.
Figure 8.4 shows a transmit timing chart in the clock-synchronized master mode.
#SCLKx
#SRDYx
SOUTx
TDBEx
TENDx
Transmit-buffer empty
interrupt request
Transmit-buffer empty
interrupt request
A
BSlave device receives the LSB.
Slave device receives the MSB. C
DFirst data is written.
Next data is written.
AB
D0 D1 D2 D3 D4 D5 D6 D7 D6 D7D0 D1 D2
B
CD
Figur e 8.4 Transmit Timing Chart in Clock-Synchronized Master Mode
1. If the #SRDYx s ignal fro m the slave is on a high level, the master waits until it is on a low level (ready to
receive).
2. If #S RDYx i s on a low l evel, the synchronizing clock input to the serial interface begins. The
synchronizing clock is also output from the #SCLKx pin to the slave device.
3. The content of the data register is transferred to the shift register synchronously with the first falling edge
of the clock. At the same time, the LSB of the data transferred to the shift register is output from the
SOUTx pin.
4. The data i n the shift register is shifted 1 bit by the next falling edge of the clock, and the bit following the
LSB is output from SOUTx. This operation is repeated until all 8 bits of data are transmitted.
The slave device must take in each bit synchronously with the rising edges of the synchronizing clock.
•Clock-synchronized slave mo de
Figure 8.5 shows a transmit timing chart in the clock-synchronized slave mode.
Transmit-buffer empty
interrupt request
Transmit-buffer empty
interrupt request
A
BFirst data is written.
Next data is written.
#SCLKx
SOUTx
#SRDYx
TDBEx
TENDx
D0 D1 D2 D3 D4 D5 D6 D7 D6 D7D0 D1 D2
AB
Figur e 8.5 Transmit Timing Chart in Clock-Synchronized Slave Mode
1. After s etting the #SRDYx signal to a low level (ready to transmit), the slave waits for clock input from the
master.
2. When the synchronizing clock is input from the #SCLKx pin, the content of the data register is transferred
to the shift register synchronously with the first falling edge of the clock. At the same time, the LSB of the
data transferred to the shift register is output from the SOUTx pin.
The #SRDYx sig nal is returned to a high level at this point.
III PERIPHERAL BLOCK: SERIAL I NTERFACE
S1C33L03 FUNCTION PART EPSON B-III-8-9
A-1
B-III
SIF
3. The data i n the shift register is shifted 1 bit by the next falling edge of the clock, and the bit following the
LSB is output from SOUTx. This operation is repeated until all 8 bits of data are transmitted.
4. The #SRDY x signal is set to a low level when the last bit (8th bit) is output from the SOUTx pin.
The master dev ice must take in each bit synchronously with the rising edges of the synchronizing clock.
•Successiv e transmit operations
When the data in the transmit data register is transferred to the shift register, TDBEx is reset to "1" (buffer
empty). Once this occurs, the next transmit data can be written to the transmit data register, even during data
transmission.
This allows data to be transmitted successively. The transmit procedure is described above.
When TDBEx is set to "1", a tran smit-da ta em p ty inte rrupt fa cto r o ccurs . Sinc e an inte rru pt ca n b e gene ra ted
as set by the interrupt controller, the next piece of transmit data can be written using an interrupt processing
routine. In addition, since this interrupt factor can be used to invoke DMA, the data prepared in memory can
be transmitted successively to the transmit-data register through DMA transfers.
For details on how to control interrupts and DMA requests, refer to "Serial Interface Interrupts and DMA".
(3) Terminating transmit operation
Upon completion of data tra nsmission, write "0" to the transmit-enable bit TXENx to disable transmit
operation.
Receive cont ro l
(1) Enabling receive operation
Use the receive-enable bit RXENx for receive control.
Ch.0 receive-enable: RXEN0 (D6) / Serial I/F Ch.0 control register (0x401E3)
Ch.1 receive-enable: RXEN1 (D6) / Serial I/F Ch.1 control register (0x401E8)
Ch.2 receive-enable: RXEN2 (D6) / Serial I/F Ch.2 control register (0x401F3)
Ch.3 receive-enable: RXEN3 (D6) / Serial I/F Ch.3 control register (0x401F8)
When receive operations are enabled by writing "1" to this bit, clock input to the shift register is enabled
(ready for input), thereby starting a data-receive operation. The synchronizing clock input/output on the
#SCLKx pi n also i s enabled (ready for input/output). Receive operations are disabled by writing "0" to
RXENx.
After the function select register is set for the serial interface, the I/O direction of the #SRDY and #SCLK
pins are changed at follows:
#SRDY: When slave mode is set, a switch is made to output mode.
Otherwise, input mode is maintained.
#SCLK: When master mode is set, a switch is made to output mode.
Otherwise, input mode is maintained.
Note: In clock-synchronized transfers, the clock line is shared between the transmit and receive units, so
the c ommunica tion mode i s half-duplex. Therefore, RXENx and transmit-enable bit TXENx cannot
be enab led simultaneously. W hen receiving data, fix TXENx at "0" and do not change it during a
rece iv e o peration. I n addition, m ake sure RX ENx is not set to "0" during a rec eive operati on.
(2) Receive procedure
This serial interface has a receive shift register and a receive data register (receive data buffer) that are
provided independently of those used for transmit operations.
Ch.0 receive data: RXD0[7:0] (D[7:0]) / Serial I/F Ch.0 receive data register (0x401E1)
Ch.1 receive data: RXD1[7:0] (D[7:0]) / Serial I/F Ch.1 receive data register (0x401E6)
Ch.2 receive data: RXD2[7:0] (D[7:0]) / Serial I/F Ch.2 receive data register (0x401F1)
Ch.3 receive data: RXD3[7:0] (D[7:0]) / Serial I/F Ch.3 receive data register (0x401F6)
The receive data can be read out from this register.
III PERIPHERAL BLOCK: SERIAL I NTERFACE
B-III-8-10 EPSON S1C33L03 FUNCTION PART
A status bit is also provided that indicates the status of the receive data register.
Ch.0 receive data buffer full: RDBF0 (D0) / Serial I/F Ch.0 status register (0x401E2)
Ch.1 receive data buffer full: RDBF1 (D0) / Serial I/F Ch.1 status register (0x401E7)
Ch.2 receive data buffer full: RDBF2 (D0) / Serial I/F Ch.2 status register (0x401F2)
Ch.3 receive data buffer full: RDBF3 (D0) / Serial I/F Ch.3 status register (0x401F7)
This bit is set to "1" (buffer full) when the MSB of serial data is received and the data in the shift register is
transferred to the receive data register, indicating that the received data can be read out. When the data is read
out, the bit is reset to "0".
The following describes a receive operation in the master and slave modes.
•Clock-synchronized ma ster mode
Figure 8.6 shows a receive timing chart in the clock-synchronized master mode.
#SCLKx
SINx
RXDx
RDBFx
#SRDYx
Receive-buffer full
interrupt request
Receive-buffer full
interrupt request
A First data is read.
D0 D1 D6 D7 D0 D1 D6 D7 D0 D1
A
1st data 2nd data
Figur e 8.6 Receive Timing Chart in Clock-Synchronized Master Mode
1. If the #SRDYx s ignal fro m the slave is on a high level, the master waits until it turns to a low level (ready
to receive).
2. If #S RDYx i s on a low level, synchronizing clock input to the serial interface begins. The synchronizing
clock is also output from the #SCLKx pin to the slave device.
3. The slave device outputs eac h bit of data synchronously with the falling edges of the clock. The LSB is
output first.
4. Thi s serial interface takes the SIN input into the shift register at the rising edges of the clock. The data in
the shift register is sequentially shifted as bits are taken in. This operation is repeated until the MSB of data
is received.
5. When the MSB is taken in, the data in the shift register is transferred to the receive data register, enabling
the data to be read out.
•Clock-synchronized slave mo de
Figure 8.7 shows a receive timing chart in the clock-synchronized slave mode.
#SCLKx
SINx
RXDx
RDBFx
#SRDYx
Receive-buffer full
interrupt request
Receive-buffer full
interrupt request
A
BFirst data is read.
3rd data is read. C
DAn overrun error occurs because the receive operation has completed when RDBFx = "1".
Send the busy signal to the master device to stop the clock.
D0 D1 D6 D7 D0 D1 D6 D7 D0
Receive-buffer full
interrupt request
A
D1 D6 D7
1st data 2nd data 3rd data
CD
B
Figur e 8.7 Receive Timing Chart in Clock-Synchronized Slave Mode
III PERIPHERAL BLOCK: SERIAL I NTERFACE
S1C33L03 FUNCTION PART EPSON B-III-8-11
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B-III
SIF
1. After s etting the #SRDYx signal to a low level (ready to receive), the slave waits for clock input from the
master.
2. The master device outputs each bit of data synchronously with the falling edges of the clock. The LSB is
output first.
3. Thi s serial interface takes the SIN input into the shift register at the rising edges of the clock that is input
from #SCLKx. The data in the shift register is sequentially shifted as bits are taken in. This operation is
repeated until the MSB of data is received.
4. When the MSB is taken in, the data in the shift register is transferred to the receive data register, enabling
the data to be read out.
•Successiv e rece ive operati ons
When the data received in the shift register is transferred to the receive data register, RDBFx is set to "1"
(buffer full), indicating that the received data can be read out.
Since the receive data register can be read out while receiving the next data, data can be received successively.
The pro cedure for receiving i s described above.
When RDBFx is set to "1", a rece ive -d ata full in terru pt fa cto r occu rs . Sinc e an inte rru pt ca n b e gene ra ted as
set by the interrupt controller, the received data can be read by an interrupt processing routine. In addition,
since this interrupt factor can be used to invoke DMA, the received data can be received successively in
locations prepared in memory through DMA transfers.
For details on how to control interrupts/DMA, refer to "Serial Interface Interrupts and DMA".
(3) Overrun error
If, during successive receive operation, a receive operation for the next data is completed before the receive
data register is read out, the receive data register is overwritten with the new data. Therefore, the receive data
register must always be read out before a receive operation for the next data is completed.
When the receive data register is overwritten, an overrun error is generated and the overrun error flag is set to
"1".
Ch.0 overrun error flag: OER0 (D2) / Serial I/F Ch.0 status register (0x401E2)
Ch.1 overrun error flag: OER1 (D2) / Serial I/F Ch.1 status register (0x401E7)
Ch.2 overrun error flag: OER2 (D2) / Serial I/F Ch.2 status register (0x401F2)
Ch.3 overrun error flag: OER3 (D2) / Serial I/F Ch.3 status register (0x401F7)
Once the overrun error flag is set to "1", it remains set until it is reset by writing "0" to it in the software.
The ove rrun error is one of the receive-error interrupt factors in the serial interface. An interrupt can be
generated for this error by setting the interrupt controller as necessary, so that the error can be processed by
an int e rru pt proces si n g ro utine .
(4) #SRDYx i n slave m ode
When receive operations are enabled by writing "1" to RXENx, the #SRDYx signal is turned to a low level,
thereby indicating to the master device that the slave is ready to receive. When the LSB of serial data is
received, #SRDYx is turned to a high level; when the MSB is received, #SRDYx is returned to a low level, in
preparation for the next receive operation.
If an overrun error occurs, #SRDYx is turned to a high level (unable to receive) at that point, with receive
operations for the following data thus suspended. In this case, #SRDYx is returned to a low by reading out
the data overwritten in the receive data register, and if any receive data follows, the slave restarts receiving
data.
(5) Terminating recei ve operation
Upon completion of a data receive operation, write "0" to the receive-enable bit RXENx to disable receive
operations.
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Asynchronous Interface
Outline of Asynchronous Interface
Asynchronous t ransfers are performed by adding a start bit and a stop bit to the start and end points of each serial-
converted data. With this method, there is no need to use a clock that is fully synchronized on the transmit and
receive sides; instead, transfer operations are timed by the start and stop bits added to the start and end points of
each data.
In the 8-bit asynchronous mode (SMDx[1:0] = "11"), 8 bits of data can be transferred; in the 7-bit asynchronous
mode (SMDx[1:0] = "10"), 7 bits of data can be transferred.
In either mode, it is possible to select the stop-bit length, add a parity bit, and choose between even and odd parity.
The start bit is fixed at "1".
The ope rating clock can be selected betwe en an internal clock generated by a n 8-bit programmable timer or an
external clock that is input from the #SCLKx pin.
Since the transmit and receive units are both constructed with a double-buffer structure, successive transmit and
receive operations are possible. Furthermore, since the transmit and receive units are independent, full-duplex
communication in which transmit and receive operations are performed simultaneously is also possible.
Figure 8.8 shows an example of how input/output pins are connected for transfers in the asynchronous mode.
Data input
Data output
External clock
SINx
SOUTx
#SCLKx
SINx
SOUTx
External
serial device
(
1
)
When external clock is used
(
2
)
When internal clock is used
S1C33
Data input
Data output
External
serial device
S1C33
Figur e 8.8 Example of Connection in Asynchronous Mode
When the asynchronous mode is selected, it is possible to use the IrDA interface function.
Asynchronous-transfer data format
The data format for asynchronous transfer is shown below.
Data length: 7 or 8 bits (determined by the selected transfer mode)
Start bit: 1 bit, fixed
Stop bit: 1 or 2 bits
Parity bit: Even or odd parity, or none
Sampling clock (for transmitting)
s1: start bit, s2 & s3: stop bit, p: parity bit
7-bit asynchronous mode
(Stop bit: 1 bit, parity: none) s1 D0 D1 D2 D3 D4 D5 D6 s2
(Stop bit: 1 bit, parity: used) s1 D0 D1 D2 D3 D4 D5 D6 ps2
(Stop bit: 2 bits, parity: none) s1 D0 D1 D2 D3 D4 D5 D6 s2 s3
(Stop bit: 2 bits, parity: used) s1 D0 D1 D2 D3 D4 D5 D6 ps2 s3
8-bit asynchronous mode
(Stop bit: 1 bit, parity: none) s1 D0 D1 D2 D3 D4 D5 D6 D7 s2
(Stop bit: 1 bit, parity: used) s1 D0 D1 D2 D3 D4 D5 D6 D7 ps2
(Stop bit: 2 bits, parity: non) s1 D0 D1 D2 D3 D4 D5 D6 D7 s2 s3
(Stop bit: 2 bits, parity: used) s1 D0 D1 D2 D3 D4 D5 D6 D7 ps2 s3
Figur e 8.9 Data Format for Asynchronous Transfer
Serial data is transmitted and received, starting with the LSB.
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Setting Asynchronous Interface
When performing asynchronous transfer via the serial interface, the following must be done be fore data transfer
can be started:
1. Setting input/output pins
2. Setting the interface mode
3. Setting the transfer mode
4. Setting the input clock
5. Setting the data format
6. Setting interrupt/IDMA/HSDMA
The followi ng de scribes how t o set each of the above. For details on interrupt/DMA settings, refer to "Serial
Interface Interrupts and DMA".
Note: Always make sure the serial interface is inactive (TXE Nx and RX ENx = "0") before making these
settings. A change in settin gs during operati on may resul t in a malfunction.
Setting input/output pins
In the asynchronous mode, two pins–SINx and SOUTx–are used. When external clock input is used, one
more pi n, #SCLKx, is also used.
Set CFP0[7:0] (D[7:0]) / P0 function select register (0x402D0) according to the pins used. (Both channels can
be used, if necessary.) Since the #SRDYx pi n is not used, P03 or P07 can be used as an I/O port. During
operation using the internal clock, P03 or P06 can also be used as an I/O port.
Setting the interface mode
IRMDx[1:0] (D[1:0]) / Serial I/F IrDA register (Ch.0: 0x401E4, Ch.1: 0x401E 9, Ch.2: 0x401F4, Ch.3:
0x401F9) i s used to set the IrDA interface. Since IRMDx[1:0] becomes indeterminate at initial reset,
initialize it by writing "00" when using the serial interface as a normal interface, or "10" when using the serial
interface as an IrDA interface. This setting must be made before a transfer mode is set.
Setting the transfer mode
Use SMDx to set the transfer mode of the serial interface as described earlier. When using the serial interface
in the 8-bit asynchronous mode, set SMDx[1:0] to "11", when using the serial interface in the 7-bit
asynchronous mode, set SMDx[1:0] to "10".
Setting the input clock
In the asynchronous mode, the operating clock can be selected between the internal clock and an external
clock.
Ch.0 input clock selection: SSCK0 (D2) / Serial I/F Ch.0 control register (0x401E3)
Ch.1 input clock selection: SSCK1 (D2) / Serial I/F Ch.1 control register (0x401E8)
Ch.2 input clock selection: SSCK2 (D2) / Serial I/F Ch.2 control register (0x401F3)
Ch.3 input clock selection: SSCK3 (D2) / Serial I/F Ch.3 control register (0x401F8)
The external clock is selected (input from the #SCLKx pin) by writing "1" to SSCKx, and an internal clock is
selected by writing "0".
Note: SSCKx becomes in deter m inate at initial reset, so be sure to reset it in the software.
•Internal cl ock
When the internal clock is selected, the serial interface is clocked by a clock generated using an 8-bit
programmable timer. The clock source for each channel is as follows:
Ch.0: Clock out put by 8-bit programmab le timer 2
Ch.1: Clock out put by 8-bit programmab le timer 3
Ch.2: Clock out put by 8-bit programmab le timer 4
Ch.3: Clock out put by 8-bit programmab le timer 5
There fore, before the internal clock can be used, the following conditions must be met:
1. The prescaler is outpu tting a clock to the 8-bit programmable timer 2 (or 3).
2. The 8-bit program m able timer 2 (or 3) is outputting a cl ock.
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Any des ired clock frequency can be obtained by setting the prescaler division ratio and the reload data of the
8-bit program mable timer as necessary. The relationship between the contents of these setting and the transfer
rate is expr es sed by Eq. 2.
The 8-b it programmable t imer has its unde rflow signal further divided by 2 internally, in order to ensure that
the duty ratio of the clock supplied to the serial interface is 50%.
Furthermore, the clock output by the 8-bit programmable timer is divided by 16 or 8 internally in the serial
interface, in order to create a sampling clock (refer to "Sampling clock"). This division ratio must also be
considered when setting the transfer rate.
These division ratios are taken into account in Eq. 2.
fPSCIN × pdr × sdr
RLD = ———————— - 1 (Eq. 2)
2 × bps
RLD: Set value of the 8-bit programmable timer's reload data register
fPSCIN:Prescaler input clock frequency (Hz)
bps: Transf er ra te (b its /seco nd )
pdr: Divi sion ratio of t he presc aler
sdr: Internal division ratio of the serial interface (1/16 or 1/8)
Note: The di vision rat io selected usi ng the prescaler diff ers between 8-bit pro gramma ble timers 2 and 3.
Take this i nto accoun t when settin g a divis ion ratio.
8-bit pr ogram m able timer 2, 4: 1/2, 1/ 4, 1/8, 1/1 6, 1/32, 1/64, 1/2 048, 1/4096
8-bit pr ogram m able timer 3, 5: 1/2, 1/ 4, 1/8, 1/1 6, 1/32, 1/64, 1/1 28, 1/256
Table 8.4 shows examples of prescaler division ratios and the reload data settings of the programmable timer,
in cases in which the internal division ratio of the serial interface is set to 1/16.
Table 8.4 Example of Transfer Rate Settings
Transfer rate fPSCIN = 20 MHz fPSCIN = 25 MHz fPSCIN = 33 MHz
(bps) RLD pd r Error (%) RLD pdr Error (%) RLD pdr Error (%)
300 129 1/16 0.16025 162 1/16 -0.14698 216 1/16 0.00640
1200 129 1/4 0.16025 162 1/4 -0.14698 216 1/4 0.00640
2400 129 1/2 0.16025 162 1/2 -0.14698 216 1/2 0.00640
4800 64 1/2 0.16025 80 1/2 -0.46939 108 1/2 -0.45234
9600 32 1/2 -1.35732 40 1/2 -0.75584 53 1/2 0.46939
14400 21 1/2 -1.35732 13 1/4 -3.11880 35 1/2 0.46939
28800 10 1/2 -1.35732 13 1/2 -3.11880 17 1/2 0.46939
Make sure the error is within 1%. Calculate the error using the following equation:
fPSCIN × pdr
Error = {—————————— -1} × 100 [%]
(RLD + 1) × 32 × bps
For details on how to control the prescaler and 8-bit programmable timers, refer to "Prescaler" and "8-Bit
Programmable Timers".
•External clock
When an external clock is selected, the serial interface is clocked by a clock input from the #SCLKx pin.
There fore, there is no need to control the prescaler and 8-bit programmable timers.
Any des ired clock frequency can be set. The clock input from the #SCLKx pin is internally divided by 16 or
8 in the serial interface, in order to create a sampling clock (refer to "Sampling clock"). This division ratio
must also be considered when setting the transfer rate.
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•Sampling clock
In the asynchronous mode, TCLK (the clock output by the 8-bit programmable timer or input from the
#SCLKx pi n) is internally divided in the serial interface, in order to create a sampling clock.
A 1/1 6 division ratio is selected by writing "0" to DIVMDx , and a 1/8 ratio is selected by writing "1".
Ch.0 clock division ratio selection: DIVMD0 (D4) / Serial I/F Ch.0 IrDA register (0x401E4)
Ch.1 clock division ratio selection: DIVMD1 (D4) / Serial I/F Ch.1 IrDA register (0x401E9)
Ch.2 clock division ratio selection: DIVMD2 (D4) / Serial I/F Ch.2 IrDA register (0x401F4)
Ch.3 clock division ratio selection: DIVMD3 (D4) / Serial I/F Ch.3 IrDA register (0x401F9)
Note: The DI VM Dx bit becomes indeterm inate at in itial reset, so be sure to reset it in the software.
Settings of this bit are valid only in the asynch ronous m ode (and wh en using the IrDA int erface).
For receiving
SINx
TCLK
Sampling clock for receiving
Sampling of start bit
Start bit D0
12
6×TCLK 10×TCLK
128816
Sampling of D0 bit
Figur e 8.10 Sampling Clock for Asynchronous Receive Operation (when 1/16 division is selected)
As shown i n Figure 8.10, the sampling clock is created by dividin g T CLK by 16 (or 8). Its duty ratio (low:
high ratio) is 6:10 (or 2:6 when divided by 8), and not 50%. Since the receive data is sampled in the middle
point of each bit, the sampling clock recognizes the start bit first, and then changes the level from high to low
at the second falling edge of TCLK. And at the 8th (4th for 1/8) falling edge of TCLK, it changes the level
from low to high. This change in levels is repeated for the following bits of data:
Each bit of data is sampled at each rising edge of this sampling clock. When the stop bit is sampled, the
sampling clock is fixed at high level until the next start bit is sampled.
If the SINx pin is returned to high level at the second falling edge of TCLK when it recognize the start bit, the
data is assumed to be noise, and gen eration of the sampling clock is stopped.
If the SINx pin is not on a low level when the start bit is sampled at the 8th (4th for 1/8) clock, such as when
the baud rate is not matched between the transmit and receive units, the serial interface stops sampling the
following data and returns to a start-bit detection mode. In this case, no error is generated.
For transmitting
TCLK
Sampling clock for transmitting
123 16. . .
8×TCLK 8×TCLK
Figur e 8.11 Sampling Clock for Asynchronous Transmit Operation (when 1/16 division is selected)
When transmitting data, a sampling clock of a 50% duty cycle is generated from TCLK by di vid ing it by 16
(or 8), and each bit of data is output synchronously with this clock.
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Setting the data format
In the asynchronous mode, the data length is 7 or 8 bits as determined by the transfer mode set. The start bit is
fixed at 1.
The stop and parit y b its can be set as shown in the Table 8.5 using the following control bits:
Table 8.5 Serial I/F Control Bits
Ch.0 (Serial I/F Ch.0
control register) Ch.1 (Serial I/F Ch.1
control register) Ch.2 (Serial I/F Ch.2
control register) Ch.3 (Serial I/F Ch.3
control register)
Stop-bit selection STPB0(D3/0x401E3) STPB1(D3/0x401E8) STPB2(D3/0x401F3) STPB3(D3/0x401F8)
Parity enable EPR0(D5/0x401E3) EPR1(D5/0x401E8) EPR2(D5/0x401F3) EPR3(D5/0x401F8)
Parity-mode selection PMD0(D4/0x401E3) PMD1(D4/0x401E8) PMD2(D4/0x401F3) PMD3(D4/0x401F8)
Table 8.6 Stop Bit and Parity Bit Settings
STPBx EPRx PMDx Stop bit Parity bit
111 2 bits Odd
02 bits Even
0∗2 bit s Non e
011 1 bit Odd
01 bit Even
0∗1 bit Non
∗ Setting PMDx is invalid when EPRx = "0".
Note: These bit s beco m e indeterminate at initia l reset, so be sure to initialize them in the software.
Control and Operation o f Asynchronous Transfer
Transmit control
(1) Enabling transmit operation
Use the transmit-enable bit TXENx for transmit control.
Ch.0 transmit-enable: TXEN0 (D7) / Serial I/F Ch.0 control register (0x401E3)
Ch.1 transmit-enable: TXEN1 (D7) / Serial I/F Ch.1 control register (0x401E8)
Ch.2 transmit-enable: TXEN2 (D7) / Serial I/F Ch.2 control register (0x401F3)
Ch.3 transmit-enable: TXEN3 (D7) / Serial I/F Ch.3 control register (0x401F8)
When transmit is enabled by writing "1" to this bit, the clock input to the shift register is enabled (ready for
input), thus allowing data to be transmitted.
Transmit is disabled by writing "0" to TXENx.
Note: Do not set TX ENx to " 0" during a transmit oper ation.
(2) Transmit p rocedure
The serial interface has a transmit shift register and a transmit data register (transmit data buffer) that are
provided independently of those used for receive operations.
Ch.0 transmit data: TXD0[7:0] (D[7:0]) / Serial I/F Ch.0 transmit data register (0x401E0)
Ch.1 transmit data: TXD1[7:0] (D[7:0]) / Serial I/F Ch.1 transmit data register (0x401E5)
Ch.2 transmit data: TXD2[7:0] (D[7:0]) / Serial I/F Ch.2 transmit data register (0x401F0)
Ch.3 transmit data: TXD3[7:0] (D[7:0]) / Serial I/F Ch.3 transmit data register (0x401F5)
The serial interface starts a transmit operation by writing data to this register. In the 7-bit asynchronous mode,
bit 7 (MSB) in each register is ignored.
The serial interface also contains a status bit to indicate the status of the transmit data register.
Ch.0 transmit data buffer empty: TDBE0 (D1) / Serial I/F Ch. 0 status reg ister (0x401E2)
Ch.1 tra nsmit data buffer empty: TDBE1 (D1) / Seria l I/F Ch.1 sta tus reg ister (0x401E7)
Ch.2 tra nsmit data buffe r empty: TDBE2 (D1) / Serial I/F Ch.2 status register (0x401F2)
Ch.3 tra nsmit data buffe r empty: TDBE3 (D1) / Serial I/F Ch.3 status register (0x401F7)
This bit is reset to "0" by writing data to the transmit data register, and set back to "1" (buffer empty) when
the data is transferred to the shift register. The transfer begins when the serial interface starts sending the start
bit.
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The transfer status can be checked using the transmit-completion flag (TENDx).
Ch.0 transmit-completion flag: TEND0 (D5) / Serial I/F Ch.0 status register (0x401E2)
Ch.1 transmit-completion flag: TEND1 (D5) / Serial I/F Ch.1 status register (0x401E7)
Ch.2 transmit-completion flag: TEND2 (D5) / Serial I/F Ch.2 status register (0x401F2)
Ch.3 transmit-completion flag: TEND3 (D5) / Serial I/F Ch.3 status register (0x401F7)
This bit goes "1" when data is being transmitted and goes "0" when the transmission has completed.
When data is transmitted successively in asynchronous mode, TENDx maintains "1" until all data is
transmitted.
Figure 8.12 shows a transmit timing chart in the asynchronous mode.
Example: Data length 8 bits
Stop bit 1 bit
Parity bit Included
Sampling clock
SOUTx
TDBEx
TENDx
Transmit-buffer empty
interrupt request
Transmit-buffer empty
interrupt requestS1
S2
P
Start bit
Stop bit
Parit
y
bit
A
BFirst data is written.
Next data is written.
S1 D0 D1 S1 D0D2 D3 D4 D5 D6 D7 PS2 PS2
AB
Figur e 8.12 Transmit Timing Chart in Asynchronous Mode
1. The contents of the data register are transferred to the shift register synchronously with the first falling
edge of the sampling clock. At the same time, the SOUTx pin is setting to a low level to send the start bit.
2. Each bit of data in the shift register is transmitted beginning with the LSB at each falling edge of the
subsequent sampling clock. This operation is repeated until all 8 (or 7) bits of data are transmitted.
3. After s ending the MSB, the parity bit (if EPRx = "1") and the stop bit are transmitted insuccession.
•Successiv e transmit operation
When the data in the transmit data register is transferred to the shift register, TDBEx is reset to "1" (buffer
empty). Once this occurs, the next transmit data can be written to the transmit data register, even during data
transmission.
This allows data to be transmitted successively. The transmit procedure is described above.
When TDBE x is set to "1", a transmit-data empty interrupt factor simultaneously occurs. Since an interrupt
can be generated as set by the interrupt controller, the next transmit data can be written using an interrupt
processing routine. In addition, since this interrupt factor can be used to invoke IDMA, the data prepared in
memory can be transmitted successively to the transmit data register through DMA transfers.
For details on how to control interrupts and IDMA requests, refer to "Serial Interface Interrupts and DMA".
(3) Terminating transmit operations
When data transmission is completed, write "0" to the transmit-enable bit TXENx to disable transmit
operations.
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Receive cont ro l
(1) Enabling receive operations
Use the receive-enable bit RXENx for receive control.
Ch.0 receive-enable: RXEN0 (D6) / Serial I/F Ch.0 control register (0x401E3)
Ch.1 receive-enable: RXEN1 (D6) / Serial I/F Ch.1 control register (0x401E8)
Ch.2 receive-enable: RXEN2 (D6) / Serial I/F Ch.2 control register (0x401F3)
Ch.3 receive-enable: RXEN3 (D6) / Serial I/F Ch.3 control register (0x401F8)
When receiving enabled by writing "1" to this bit, clock input to the shift register is enabled (ready for input),
meaning that it is ready to receive data.
Receive operations are disabled by writing "0" to RXENx.
Note: Do not set RXENx to "0" during a receive operation.
(2) Receive procedure
This serial interface has a receive shift register and a receive data register (receive data buffer) that are
provided independently of those used for transmit operations.
Ch.0 receive data: RXD0[7:0] (D[7:0]) / Serial I/F Ch.0 receive data register (0x401E1)
Ch.1 receive data: RXD1[7:0] (D[7:0]) / Serial I/F Ch.1 receive data register (0x401E6)
Ch.2 receive data: RXD2[7:0] (D[7:0]) / Serial I/F Ch.2 receive data register (0x401F1)
Ch.3 receive data: RXD3[7:0] (D[7:0]) / Serial I/F Ch.3 receive data register (0x401F6)
Receive data can be read out from this register.
A status bit is also provided to indicate the status of the receive data register.
Ch.0 receive data buffer full: RDBF0 (D0) / Serial I/F Ch.0 status register (0x401E2)
Ch.1 receive data buffer full: RDBF1 (D0) / Serial I/F Ch.1 status register (0x401E7)
Ch.2 receive data buffer full: RDBF2 (D0) / Serial I/F Ch.2 status register (0x401F2)
Ch.3 receive data buffer full: RDBF3 (D0) / Serial I/F Ch.3 status register (0x401F7)
This bit is set to "1" (buffer full) when data is transferred from the shift register to the receive data register
after the stop bit is sampled (the second bit if two stop bits are used), indicating that the received data can be
read out. When the data is read out, the bit is reset to "0".
Figure 8.13 shows a receive timing chart in the asynchronous mode.
Example: Data length 8 bits
Stop bit 1 bit
Parity bit Included
Sampling clock
SOUTx
RDBFx
RXDx
Receive-buffer full
interrupt request
S1
S2 Start bit
Stop bit P
AParity bit
First data is read.
S1 D0 D1 S1 D0 D1D2 D3 D4 D5 D6 D7 P S2
A
1st data
Figur e 8.13 Receive Timing Chart in Asynchronous Mode
1. The seri al interface starts sampling when the start bit is input (SINx = low).
2. When the start bit is sampled at the first rising edge of the sampling clock, each bit of receive data is taken
into the shift register, beginning with the LSB at each rising edge of the subsequent clock. This operation
is repeated until the MSB of data is received.
3. When the MSB is taken in, the parity bit that follows is also taken in (if EPRx = "1").
4. Wh en the stop bit is sampled, the data in the shift register is transferred to the receive data register,
enabling the data to be read out.
The parity is checked when data is transferred to the receive data register (if EPRx = "1").
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Note:The receive operation is terminated when the first stop bit is sampled even if the stop bit is
configured with two bits.
•Successiv e rece ive operati ons
When the data received in the shift register is transferred to the receive data register, RDBFx is set to "1"
(buffer full), indicating that the received data can be read out. Thereafter, data can be received successively
because the receive data register can be read out while the next data is received. The procedure for receiving
is described above.
When RDBFx is set to "1", a receive-data full interrupt factor occurs. Since an interrupt can be generated as
set by the interrupt controller, the received data can be read using an interrupt processing routine. In addition,
since this interrupt factor can be used to invoke IDMA, the received data can be received successively in
locations prepared in memory through DMA transfers.
For details on how to control interrupts and IDMA requests, refer to "Serial Interface Interrupts and DMA".
(3) Receive errors
Three types of receive errors can be detected when receiving data in the asynchronous mode.
Since an interrupt can be generated by setting the interrupt controller, the error can be processed using an
interrupt processing routine. For details on receive error interrupts, refer to "Serial Interface Interrupts and
DMA".
•Parity error
If EPRx is set to "1" (parity added), the parity is checked when data is received.
This parity check is performed when the data received in the shift register is transferred to the receive data
register in order to check conformity with PMDx settings (odd or even parity). If any nonconformity is found
in this check, a parity error is assumed and the parity error flag is set to "1".
Ch.0 parity error flag: PER0 (D3) / Serial I/F Ch.0 status register (0x401E2)
Ch.1 parity error flag: PER1 (D3) / Serial I/F Ch.1 status register (0x401E7)
Ch.2 parity error flag: PER2 (D3) / Serial I/F Ch.2 status register (0x401F2)
Ch.3 parity error flag: PER3 (D3) / Serial I/F Ch.3 status register (0x401F7)
Ev en when this error occurs, the received data in error is transferred to the receive data register and the
receive operation is continued. However, the content of the received data for which a parity error is flagged
cannot be guaranteed.
The PERx fla g is reset to "0" by writing "0".
•Framing error
If data with a stop bit = "0" is received, the serial interface assumes that the data is out of synchronization and
generates a fram in g erro r.
If two stop bits are used, only the first stop bit is checked.
When this error occurs, the framing-error flag is set to "1".
Ch.0 framing-error flag: FER0 (D4) / Serial I/F Ch.0 status register (0x401E2)
Ch.1 framing-error flag: FER1 (D4) / Serial I/F Ch.1 status register (0x401E7)
Ch.2 framing-error flag: FER2 (D4) / Serial I/F Ch.2 status register (0x401F2)
Ch.3 framing-error flag: FER3 (D4) / Serial I/F Ch.3 status register (0x401F7)
Ev en when this error occurs, the received data in error is transferred to the receive data register and the
receive operation is continued. However, the content of the received data for which a framing error is flagged
cannot be guaranteed, even if no framing error is found in the following data received.
The FERx fla g is reset to "0" by writing "0".
III PERIPHERAL BLOCK: SERIAL I NTERFACE
B-III-8-20 EPSON S1C33L03 FUNCTION PART
•Overrun error
If during successive receive operations, a receive operation for the next data is completed before the receive
data register is read out, the receive data register is overwritten with the new data. Therefore, the receive data
register must always be read out before a receive operation for the next data is completed.
When the receive data register is overwritten, an overrun error is generated and the overrun-error flag is set to
"1".
Ch.0 overrun-error flag: OER0 (D2) / Serial I/F Ch.0 status register (0x401E2)
Ch.1 overrun-error flag: OER1 (D2) / Serial I/F Ch.1 status register (0x401E7)
Ch.2 overrun-error flag: OER2 (D2) / Serial I/F Ch.2 status register (0x401F2)
Ch.3 overrun-error flag: OER3 (D2) / Serial I/F Ch.3 status register (0x401F7)
Ev en when this error occurs, the received data in error is transferred to the receive data register and the
receive operation is continued.
The OERx flag is reset to "0" by writing "0".
(4) Terminating recei ve operation
When a data receive operation is completed, write "0" to the receive-enable bit RXENx to disable receive
operations.
III PERIPHERAL BLOCK: SERIAL I NTERFACE
S1C33L03 FUNCTION PART EPSON B-III-8-21
A-1
B-III
SIF
IrDA Inter face
Outline of IrDA Interface
Each channel of the serial interface contains a PPM modulator circuit, allowing an infrared-ray communication
circuit to be configured based on IrDA 1.0 simply by adding a simple external circuit.
PPM
Modulator SOUTx
LED
TXD
LED A
LED C
RXD
CX1
Vcc
CX2
GND
VP1N
VP1N
Photodiode
SINx
VDD
VSS
Serial I/F
PPM
Modulator
S1C33
Infrared communication module
(Example: HP HSDL-1000)
Figur e 8.14 Configuration Example of IrDA Interface
This IrD A interface function can be used only when the selected transfer mode is an asynchronous mode.
Since the contents of the asynchronous mode are applied directly for the serial-interface functions other than the
IrDA interface unit, refer to "Asynchronous Interface", for details on how to set and control the data formats and
data transfers.
Setting IrDA Interface
When performing infrared-ray communication, the following settings must be made before communication can be
started:
1. Setting input/output pins
2. Selectin g the in te rface m od e (I rD A in te rfa ce fu nct i o n)
3. Setting the transfer mode
4. Setting the input clock
5. Setting the data format
6. Setting the interrupt/IDMA/HSDMA
7. Setting the input/output logic
The con tents for items 1 through 5 have been explained in connection with the asynchronous interface. For details,
refer to "Asynchronous Interface". For details on item 6, refer to "Serial Interface Interrupts and DMA".
Note: Before making these setti ngs, alwa ys ma ke sur e the serial interface is inactive (TXENx and
RX ENx are both set to " 0"), as a chan ge in settin gs during operati on could caus e a m alfuncti on.
In addition, be sure to set the transfer mode in (3) and the following items before selecting the
IrDA interface function in (2).
III PERIPHERAL BLOCK: SERIAL I NTERFACE
B-III-8-22 EPSON S1C33L03 FUNCTION PART
Selecting the IrDA interface function
To use the IrDA interface function, select it using the control bits shown below and then set the 8-bit (or 7-
bit) asynchronous mode as the transfer mode.
Ch.0 IrDA interface-function selection: IRMD0[1:0] (D[1:0]) / Serial I/F Ch.0 IrDA register (0x401E4)
Ch.1 IrDA interface-function selection: IRMD1[1:0] (D[1:0]) / Serial I/F Ch.1 IrDA register (0x401E9)
Ch.2 IrDA interface-function selection: IRMD2[1:0] (D[1:0]) / Serial I/F Ch.2 IrDA register (0x401F4)
Ch.3 IrDA interface-function selection: IRMD3[1:0] (D[1:0]) / Serial I/F Ch.3 IrDA register (0x401F9)
Table 8.7 Setting of IrDA Interface
IRMDx1 IRMDx0 Interface mode
11Do not set. (reserved)
10IrDA 1.0 interface
01Do not set. (reserved)
00Normal interface
Note: The I R M Dx bit becomes indeterminate when initially reset, so be sure to initialize it in the software.
Setting the input/output logic
When using the IrDA interface, the logic of the input/output signals of the PPM modulator circuit can be
changed in accordance with the infrared-ray communication module or the circuit connected externally to the
chip. The logic of the internal serial interface is "active-low". If the input/output signals are active-high, the
logic of these signals must be inverted before they can be used. The input SINx and output SOUTx logic can
be set individually through the use of the IRRLx and IRTLx bits, respectively.
Table 8.8 IrDA Input/Output Logic Inversion Bits
Ch.0 (Serial I/F Ch.0
control register) Ch.1 (Serial I/F Ch.1
control register) Ch.2 (Serial I/F Ch.2
control register) Ch.3 (Serial I/F Ch.3
control register)
IrDA input logic
inversion IRRL0(D2/0x401E4) IRRL1(D2/0x401E9) IRRL2(D2/0x401F4) IRRL3(D2/0x401F9)
IrDA output logic
inversion IRTL0(D3/0x401E4) IRTL1(D3/0x401E9) IRTL2(D3/0x401F4) IRTL3(D3/0x401F9)
The logic of the input/output signal is inverted by writing "1" to each corresponding bit. Logic is not inverted
if the bit is set to "0".
PPM modulator input (I/F output)
PPM modulator output (SOUTx)
(1) IRTLx = "0"
When transmitting
PPM modulator input (I/F output)
PPM modulator output (SOUTx)
(2) IRTLx = "1"
PPM modulator input (SINx)
PPM modulator output (I/F input)
(1) IRRLx = "0"
When receiving
PPM modulator input (SINx)
PPM modulator output (I/F input)
(2) IRRLx = "1"
Figur e 8.15 IRRLx and IRTLx Settings
Note: The I RRLx an d IRTL x bits become indeterminate at initial reset, so be sure to initialize them in the
software.
III PERIPHERAL BLOCK: SERIAL I NTERFACE
S1C33L03 FUNCTION PART EPSON B-III-8-23
A-1
B-III
SIF
Control and Operation o f IrDA Interface
Th e transmi t/rece ive proce d ures hav e been explained in the section on the asynchronous interface, so refer to
"Control and Operation of Asynchronous Transfer".
The following de scribes the data modu lation and dem odu lation performed using the PP M m odu lator circuit:
When transmitting
During data transmission, the pulse width of the serial interface output signal is set to 3/16 before the signal is
outpu t from the SOUTx pin.
TCLK
PPM modulator input (I/F output)
PPM modulator output (SOUTx)
123 891011 16
3×TCLK
16×TCLK
Figur e 8.16 Data Modulation by PPM Circuit
When receiving
During data r eception, the pulse width of the input signal from SINx is set to 16/3 before the signal is
transferred to the serial interface.
TCLK
PPM modulator input (SINx)
PPM modulator output (I/F input)
1234 16
16×TCLK
3×TCLK
Figur e 8.17 Demodulation by PPM Circuit
Note: When using th e I rDA inte rfa ce , s et th e intern al d ivi sio n ratio o f the seri al inte rfa ce 1/16 (DIV MD x =
"1"), rather than 1/8 (DIVMDx = "0").
III PERIPHERAL BLOCK: SERIAL I NTERFACE
B-III-8-24 EPSON S1C33L03 FUNCTION PART
Serial I nterface Interrupts and DMA
The serial interface can generate the following three types of interrupts in each channel:
• Transmit-buffer empty inte rru pt
• Receive-buffer full interrupt
• Receive-error in terru pt
Transmit-buffer empty interrupt factor
This interrupt factor occurs when the transmit data set in the transmit data register is transferred to the shift
register, in which case the interrupt factor flag FSTXx is set to "1". At this time, if the interrupt conditions set
using the interrupt control register are met, an interrupt to the CPU is generated.
Occurrence of this interrupt factor indicates that the next transmit data can be written to the transmit data
register.
This interrupt factor can also be used to invoke IDMA, enabling transmit data to be written to the register by
mean s of a DMA tra n s fer .
Receive-completion interrupt
This interrupt factor occurs when a receive operation is completed and the receive data taken into the shift
register is transferred to the receive data register, in which case the interrupt factor flag FSRXx is set to "1".
At t his time, if the interrupt conditions set using the interrupt control register are met, an interrupt to the CPU
is generated. Occurrence of this interrupt factor indicates that the received data can be read out.
This interrupt factor can also be used to invoke IDMA, enabling the received data to be written into specified
memory locations by means of a DMA tra n s fer .
Receive-error i n terru pt
This interrupt factor occurs when a parity, framing, or overrun error is detected during data reception, in
which case the interrupt factor flag FSERRx is set to "1". At this time, if the interrupt conditions set using the
interrupt control register are met, an interrupt to the CPU is generated.
Since all three types of errors generate the same interrupt factor, check the error flags PERx (parity error),
OERx (overrun error), and FERx (framing error) to identify the type of error that has occurred. In the clock-
synchronized m od e, parity an d fram ing errors d o not o ccur.
Note: If a receive error (parity or framing error) occurs, the receive-error interrupt and receive-buffer full
interrupt factors occur simultaneously. However, since the receive-error interrupt has priority over
the receive-buffer full interrupt, the receive-error interrupt is processed first. It is therefore
necess ary for the receive-buffer full interrupt factor flag be cleared through the use of the receive-
error interrupt processing routine.
Control registers of the interrupt controller
•Ch.0 and Ch.1
Table 8.9 shows t he interrupt controller's control registers provided for each interrupt source (channel).
Table 8.9 Control Register of Interrupt Controller
Channel Interrupt factor Int errupt factor flag Interrupt enable register Interrupt priority register
Ch.0 Receive-error interru pt FSERR0(D0/0x40286) ESERR0(D0/0x40276) PSIO0[2:0](D[6:4]/0x40269)
Recei ve- buffer full FSRX 0(D1/0x40286) ESRX0(D1/0x40276)
Transmit-buffer empty FSTX0(D2/0x40286) ESTX0(D2/0x40276)
Ch.1 Receive-error interru pt FSERR1(D3/0x40286) ESERR1(D3/0x40276) PSIO1[2:0](D[2:0]/0x4026A)
Recei ve- buffer full FSRX 1(D4/0x40286) ESRX1(D4/0x40276)
Transmit-buffer empty FSTX1(D5/0x40286) ESTX1(D5/0x40276)
When the interrupt factor described above occurs, the corresponding interrupt factor flag is set to "1". If the
interrupt enable register bit for that interrupt factor has been set to "1", an interrupt request is generated.
Interrupts caused by an interrupt factor can be disabled by leaving the interrupt enable register bit for that
factor set to "0". The interrupt factor flag is set to "1" whenever interrupt conditions are met, regardless of the
setting of the interrupt enable register (even if it is set to "0").
III PERIPHERAL BLOCK: SERIAL I NTERFACE
S1C33L03 FUNCTION PART EPSON B-III-8-25
A-1
B-III
SIF
The interrupt priority register sets the interrupt priority level of each interrupt source in a range between 0 and
7. An interrupt request to the CPU is accepted only when no other interrupt request of a higher priority has
been ge nerated.
In addition, only when the PSR's IE bit = "1" (interrupts enabled) and the set value of the IL is smaller than
the input interrupt level set by the interrupt priority register, will the input interrupt request actually be
accepted by the CPU.
For details on these interrupt control registers, as well as the device operation when an interrupt has occurred,
refer to "ITC (Interrupt Controller)".
•Ch.2 and Ch.3
Ch.2 and Ch.3 do not have dedicated interrupt signals. Either a port inpu t interrupt o r 16-b it ti mer inte rru pt is
sel e cted, and interru pt h and ling is perf orm e d acco rdingly.
The correspondence between port input interrupt factors and 16-bit timer interrupt factors is shown in
Table.8.10.
Table 8.10 Correspondence between Interrupt Factors
Serial I/F Ch.2, Ch.3/
T8-Ch.4, Ch.5 interrupt factor Port input interrupt
factor 16-bit timer interrupt
factor
T8 Ch.5 UF FPT7 Timer 2 compare A
T8 Ch.4 UF FPT5 Timer 2 compare B
SIO Ch.3 TXD Emp. FPT6 Timer 4 compare A
SIO Ch.3 RXD Full FPT4 Timer 4 compare B
SIO Ch.3 RXD Err. FP T2 Timer 3 compare A
SIO Ch.2 TXD Emp. FPT3 Timer 5 compare A
SIO Ch.2 RXD Full FPT1 Timer 5 compare B
SIO Ch.2 RXD Err. FP T0 Timer 3 compare B
Sw itching between the above interrupt factors is performed by means of the interrupt factor FP function
switching register (0x402C5) and the interrupt factor TM16 function switching register (0x402CB).
For the setting of the interrupt controller in the CPU-core, the setting for the selected interrupt factor is used.
Refer to "ITC (Interrupt Controller)" in the Core Block section for details of interrupts, and "Input/Output
Ports" and "16-Bit Programmable Timers" in the Peripheral Block section for detail s of port input interrupt
facto r and 1 6-b it ti me r inte rru pt fa cto r se tting s.
Int e ll ig e nt D M A
•Ch.0 and Ch.1
The receive-buffer full interrupt and transmit-buffer empty interrupt factors can be used to invoke intelligent
DMA (IDMA). This enab le s succ essiv e tran sm it/receive oper ations betw ee n m em o ry an d th e
transmit/receive-buffer to be performed by means of a DAM transfer.
The following shows the IDMA channel numbers set for each interrupt factor:
IDMA Ch.
Ch.0 receive-buffer full interrupt: 0x17
Ch.0 transmit-buffer empty interrupt: 0x18
Ch.1 receive-buffer full interrupt: 0x19
Ch.1 transmit-buffer empty interrupt: 0x1A
The IDMA request and enable bits shown in Table 8.11 must be set to "1" for IDMA to be invoked. Transfer
conditions, etc. on the IDMA side must also be set in advance.
Table 8.11 Control Bits for IDMA Transfer
Channel Interrupt factor IDMA request bit IDMA enable bit
Ch.0 Receive-buf fer full RSRX0(D6/0x40292) DESRX0(D6/0x40296)
Transmit-buffer empty RSTX0(D7/0x40292) DESTX0(D7/0x40296)
Ch.1 Receive-buf fer full RSRX1(D0/0x40293) DESRX1(D0/0x40297)
Transmit-buffer empty RSTX1(D1/0x40293) DESTX1(D1/0x40297)
III PERIPHERAL BLOCK: SERIAL I NTERFACE
B-III-8-26 EPSON S1C33L03 FUNCTION PART
If an interrupt factor occurs when the IDMA request and enable bits are set to "1", IDMA is invoked. No
interrupt request is generated at that point. An interrupt request is generated upon completion of the DMA
transfer. The bits can also be set so as not to generate an interrupt, with only a DAM transfer performed.
For details on DMA transfer and how to control interrupts upon completion of DMA transfer, refer to "IDMA
(Intelligent DMA)".
•Ch.2 and Ch.3
For Ch.2 and Ch.3, eith er a p ort inpu t inte rru pt o r 16-bit time r inte rru pt is sele cte d, an d ID MA is initi ale d b y
means of that interrupt factor.
The correspondence between IDMA channels and Serial I/F Ch.2 and Ch.3 is shown in Table 8.12.
Table 8.12 Correspondence to IDMA Channels
Serial I/F Ch.2, Ch.3 /
T8-Ch.4, Ch.5 interrupt factor Port input / 16-bit timer
interrupt factor IDMA Ch.
T8 Ch.5 UF FPT7 31
Timer 2 comp are A 12
T8 Ch.4 UF FPT5 29
Timer 2 comp are B 11
SIO Ch.3 TXD Emp. FPT6 30
Timer 4 comp are A 16
SIO Ch.3 RXD Full FPT4 28
Timer 4 comp are B 15
SIO Ch.3 RXD Err. FPT2 3
Timer 3 comp are A 14
SIO Ch.2 TXD Emp. FPT3 4
Timer 5 comp are A 18
SIO Ch.2 RXD Full FPT1 2
Timer 5 comp are B 17
SIO Ch.2 RXD Err. FPT0 1
Timer 3 comp are B 13
For example, when port input interrupts are selected, Serial I/F Ch.2 transmit buffer empty corresponds to
port 3, a nd to IDM A Ch.4. Therefore, IDMA can be invoked by setting both IDMA request bit RP3
(D3/0x40290) and IDMA enable bit DEP3 (D3/0x40294) to "1".
Hig h -speed DM A
•Ch.0 and Ch.1
Th e receive-bu ffer full inte rrupt an d tr an sm it- bu ffer emp ty inte rru pt fa cto rs can al so invo ke high -s pe ed DM A
(HSDMA).
The f ol lowing shows the HSDMA channel number and trigger set-up bit corresponding to each channel:
Table 8.13 HSDMA Trigger Set-up Bits
SIF Ch. HSDMA Ch. Trigger set-up bits
00HSD0S[3:0 ] (D[3:0]) / HSDMA Ch.0/1 trigger set-up register (0x40298)
11HSD1S[3:0 ] (D[7:4]) / HSDMA Ch.0/1 trigger set-up register (0x40298)
02HSD2S[3:0 ] (D[3:0]) / HSDMA Ch.2/3 trigger set-up register (0x40299)
13HSD3S[3:0 ] (D[7:4]) / HSDMA Ch.2/3 trigger set-up register (0x40299)
For HSDMA t o be invok ed by the receive-buffer full interrupt factor, the trigger set-up bits should be set to
"1010". For HSDMA to be invoked by the transmit-buffer empty interrupt factor, the trigger set-up bits
should be set to "1011". Transfer conditions, etc. must also be set on the HSDMA side.
The HSDMA channel is invoked through generation of the interrupt factor.
For details on HSDMA transfer, refer to "HSDMA (High-Speed DMA)".
III PERIPHERAL BLOCK: SERIAL I NTERFACE
S1C33L03 FUNCTION PART EPSON B-III-8-27
A-1
B-III
SIF
•Ch.2 and Ch.3
For Ch.2 and Ch.3, either port input interrupts or 16-bit timer interrupts are selected, and HSDMA is invoked
by means of those interr upt factor (See Table 8.10).
When port input interrupts are selected, Serial I/F Ch.2 receive buffer full corresponds to port 1, and transmit
buffer em pty to port 3. Ther efore, HSDMA can be invoked by setting HSDMA Ch.1 and Ch.3 trigger factor
values (D[7:4]/0x4029 8, D[7:4]/0x40299) of "0011".
Sim ilarly, as Serial I/F Ch.3 receiv e buf fer ful l corresponds to port 4, and tra nsmi t buffer em pty to port 6,
HSDMA can be invoked by setting HS DMA Ch.0 and Ch.2 trigger factor values (D[7:4]/0x40298,
D[7:4]/0x40299) of "0100".
When 16-bit timer interrupts are selected, the HSDMA trigger factor set values are different for receive buffer
full an d tran sm it b uff er em p ty .
In the case of Serial I/F Ch.2, receive buffer full corresponds to 16-bit timer 5 compare B, and transmit buffer
empty to 16-bit timer 5 compare A. Therefore, to use HSDMA for both transmission and reception, an
HSDMA Ch.3trigger factor val ue (D[7:4]/0x40299) of "1001" mu st be set w hen the Ch.1 trigger factor value
(D[7:4]/0x40298) has been set to " 1000 ". (HSDMA can also be invoked by the reverse combination of set
values.)
Similarly, to use 16-bit timer 4 compare A and B on Se rial I/F Ch.3, HSDM A can be invoked by setting a n
HSDMA Ch.2 val ue of "10 01" when the Ch.0 va lue has been set to "1000". (HSDMA can also be invoked by
the reverse combination of set values.)
With interrupts other than receive buffer full and transmit buffer empty, also, the above approach can be used
to activate the HSDMA channel set for the corresponding port No. or 16-bit timer compare.
Trap vectors
•Ch.0 and Ch.1
Th e trap-v ecto r add ress of each default interrupt factor is set as follows:
Ch.0 receive-error interrupt: 0x0C000E0
Ch.0 receive-buffer full interrupt: 0x0C000E4
Ch.0 transmit-buffer empty interrupt: 0x0C000E8
Ch.1 receive-error interrupt: 0x0C000EC
Ch.1 receive-buffer full interrupt: 0x0C000F0
Ch.1 transmit-buffer empty interrupt: 0x0C000F4
The bas e address of the trap table can be changed using the TTBR register (0x48134 to 0x48137).
•Ch.2 and Ch.3
Ch.2 and Ch.3 do not have dedicated interrupt signals. Either a port inpu t interrupt o r 16-b it ti mer inte rru pt is
sel e cte d, an d in terrupt hand l i ng is perf orm e d acco rding l y .
For details, refer to the "Trap Vector" subsection in the "16-Bit Programmable Timers" or "Input/Output
Ports" section.
III PERIPHERAL BLOCK: SERIAL I NTERFACE
B-III-8-28 EPSON S1C33L03 FUNCTION PART
I/O Memo ry of Serial Inter fac e
Table 8.14 shows t he control bits of the serial interface.
For details on the I/O memory of the prescaler that is used to set clocks, as well of that of 8-bit programmable
timers, refer to "Prescaler" and "8-Bit Programmable Timers", respectively.
Table 8.14 Control Bits of Serial Interface
NameAddressRegister name Bit Function Setting Init. R/W Remarks
0x0 to 0xFF(0x7F)TXD07
TXD06
TXD05
TXD04
TXD03
TXD02
TXD01
TXD00
D7
D6
D5
D4
D3
D2
D1
D0
Serial I/F Ch.0 transmit data
TXD07(06) = MSB
TXD00 = LSB
X
X
X
X
X
X
X
X
R/W 7-bit asynchronous
mode does not use
TXD07.
00401E0
(B)
Serial I/F Ch.0
transmit data
register
0x0 to 0xFF(0x7F)RXD07
RXD06
RXD05
RXD04
RXD03
RXD02
RXD01
RXD00
D7
D6
D5
D4
D3
D2
D1
D0
Serial I/F Ch.0 receive data
RXD07(06) = MSB
RXD00 = LSB
X
X
X
X
X
X
X
X
R 7-bit asynchronous
mode does not use
RXD07 (fixed at 0).
00401E1
(B)
Serial I/F Ch.0
receive data
register
–
TEND0
FER0
PER0
OER0
TDBE0
RDBF0
D7–6
D5
D4
D3
D2
D1
D0
–
Ch.0 transmit-completion flag
Ch.0 flaming error flag
Ch.0 parity error flag
Ch.0 overrun error flag
Ch.0 transmit data buffer empty
Ch.0 receive data buffer full
–
0
0
0
0
1
0
–
R
R/W
R/W
R/W
R
R
0 when being read.
Reset by writing 0.
Reset by writing 0.
Reset by writing 0.
00401E2
(B) –
1 Error 0 Normal
1
Transmitting
0 End
1 Error 0 Normal
1 Error 0 Normal
1 Empty 0 Buffer full
1 Buffer full 0 Empty
Serial I/F Ch.0
status register
TXEN0
RXEN0
EPR0
PMD0
STPB0
SSCK0
SMD01
SMD00
D7
D6
D5
D4
D3
D2
D1
D0
Ch.0 transmit enable
Ch.0 receive enable
Ch.0 parity enable
Ch.0 parity mode selection
Ch.0 stop bit selection
Ch.0 input clock selection
Ch.0 transfer mode selection 1
1
0
0
1
0
1
0
SMD0[1:0] Transfer mode
8-bit asynchronous
7-bit asynchronous
Clock sync. Slave
Clock sync. Master
0
0
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Valid only in
asynchronous mode.
00401E3
(B) 1 Enabled 0 Disabled
1 Enabled 0 Disabled
1 With parity 0 No parity
1 Odd 0 Even
1 2 bits 0 1 bit
1 #SCLK0 0
Internal clock
Serial I/F Ch.0
control register
–
DIVMD0
IRTL0
IRRL0
IRMD01
IRMD00
D7–5
D4
D3
D2
D1
D0
–
Ch.0 async. clock division ratio
Ch.0 IrDA I/F output logic inversion
Ch.0 IrDA I/F input logic inversion
Ch.0 interface mode selection 1
1
0
0
1
0
1
0
IRMD0[1:0]
–
I/F mode
reserved
IrDA 1.0
reserved
General I/F
–
X
X
X
X
X
–
R/W
R/W
R/W
R/W
0 when being read.
Valid only in
asynchronous mode.
00401E4
(B) 1 1/8 0 1/16
1 Inverted 0 Direct
1 Inverted 0 Direct
Serial I/F Ch.0
IrDA register
0x0 to 0xFF(0x7F)TXD17
TXD16
TXD15
TXD14
TXD13
TXD12
TXD11
TXD10
D7
D6
D5
D4
D3
D2
D1
D0
Serial I/F Ch.1 transmit data
TXD17(16) = MSB
TXD10 = LSB
X
X
X
X
X
X
X
X
R/W 7-bit asynchronous
mode does not use
TXD17.
00401E5
(B)
Serial I/F Ch.1
transmit data
register
0x0 to 0xFF(0x7F)RXD17
RXD16
RXD15
RXD14
RXD13
RXD12
RXD11
RXD10
D7
D6
D5
D4
D3
D2
D1
D0
Serial I/F Ch.1 receive data
RXD17(16) = MSB
RXD10 = LSB
X
X
X
X
X
X
X
X
R 7-bit asynchronous
mode does not use
RXD17 (fixed at 0).
00401E6
(B)
Serial I/F Ch.1
receive data
register
III PERIPHERAL BLOCK: SERIAL I NTERFACE
S1C33L03 FUNCTION PART EPSON B-III-8-29
A-1
B-III
SIF
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
TEND1
FER1
PER1
OER1
TDBE1
RDBF1
D7–6
D5
D4
D3
D2
D1
D0
–
Ch.1 transmit-completion flag
Ch.1 flaming error flag
Ch.1 parity error flag
Ch.1 overrun error flag
Ch.1 transmit data buffer empty
Ch.1 receive data buffer full
–
0
0
0
0
1
0
–
R
R/W
R/W
R/W
R
R
0 when being read.
Reset by writing 0.
Reset by writing 0.
Reset by writing 0.
00401E7
(B) –
1 Error 0 Normal
1
Transmitting
0 End
1 Error 0 Normal
1 Error 0 Normal
1 Empty 0 Buffer full
1 Buffer full 0 Empty
Serial I/F Ch.1
status register
TXEN1
RXEN1
EPR1
PMD1
STPB1
SSCK1
SMD11
SMD10
D7
D6
D5
D4
D3
D2
D1
D0
Ch.1 transmit enable
Ch.1 receive enable
Ch.1 parity enable
Ch.1 parity mode selection
Ch.1 stop bit selection
Ch.1 input clock selection
Ch.1 transfer mode selection 1
1
0
0
1
0
1
0
SMD1[1:0] Transfer mode
8-bit asynchronous
7-bit asynchronous
Clock sync. Slave
Clock sync. Master
0
0
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Valid only in
asynchronous mode.
00401E8
(B)
Serial I/F Ch.1
control register 1 Enabled 0 Disabled
1 Enabled 0 Disabled
1 With parity 0 No parity
1 Odd 0 Even
1 2 bits 0 1 bit
1 #SCLK1 0
Internal clock
–
DIVMD1
IRTL1
IRRL1
IRMD11
IRMD10
D7–5
D4
D3
D2
D1
D0
–
Ch.1 async. clock division ratio
Ch.1 IrDA I/F output logic inversion
Ch.1 IrDA I/F input logic inversion
Ch.1 interface mode selection 1
1
0
0
1
0
1
0
IRMD1[1:0]
–
I/F mode
reserved
IrDA 1.0
reserved
General I/F
–
X
X
X
X
X
–
R/W
R/W
R/W
R/W
0 when being read.
Valid only in
asynchronous mode.
00401E9
(B) 1 1/8 0 1/16
1 Inverted 0 Direct
1 Inverted 0 Direct
Serial I/F Ch.1
IrDA register
0x0 to 0xFF(0x7F)TXD27
TXD26
TXD25
TXD24
TXD23
TXD22
TXD21
TXD20
D7
D6
D5
D4
D3
D2
D1
D0
Serial I/F Ch.2 transmit data
TXD27(26) = MSB
TXD20 = LSB
X
X
X
X
X
X
X
X
R/W00401F0
(B)
Serial I/F Ch.2
transmit data
register
0x0 to 0xFF(0x7F)RXD27
RXD26
RXD25
RXD24
RXD23
RXD22
RXD21
RXD20
D7
D6
D5
D4
D3
D2
D1
D0
Serial I/F Ch.2 receive data
RXD27(26) = MSB
RXD20 = LSB
X
X
X
X
X
X
X
X
R00401F1
(B)
Serial I/F Ch.2
receive data
register
–
TEND2
FER2
PER2
OER2
TDBE2
RDBF2
D7–6
D5
D4
D3
D2
D1
D0
reserved
Ch.2 transmit-completion flag
Ch.2 flaming error flag
Ch.2 parity error flag
Ch.2 overrun error flag
Ch.2 transmit data buffer empty
Ch.2 receive data buffer full
–
0
0
0
0
1
0
–
R
R/W
R/W
R/W
R
R
0 when being read.
Reset by writing 0.
Reset by writing 0.
Reset by writing 0.
00401F2
(B) –
1 Error 0 Normal
1
Transmitting
0 End
1 Error 0 Normal
1 Error 0 Normal
1 Empty 0 Buffer full
1 Buffer full 0 Empty
Serial I/F Ch.2
status register
TXEN2
RXEN2
EPR2
PMD2
STPB2
SSCK2
SMD21
SMD20
D7
D6
D5
D4
D3
D2
D1
D0
Ch.2 transmit enable
Ch.2 receive enable
Ch.2 parity enable
Ch.2 parity mode selection
Ch.2 stop bit selection
Ch.2 input clock selection
Ch.2 transfer mode selection 1
1
0
0
1
0
1
0
SMD2[1:0] Transfer mode
8-bit asynchronous
7-bit asynchronous
Clock sync. Slave
Clock sync. Master
0
0
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Valid only in
asynchronous mode.
00401F3
(B)
Serial I/F Ch.2
control register 1 Enabled 0 Disabled
1 Enabled 0 Disabled
1 With parity 0 No parity
1 Odd 0 Even
1 2 bits 0 1 bit
1 #SCLK2 0
Internal clock
–
DIVMD2
IRTL2
IRRL2
IRMD21
IRMD20
D7–5
D4
D3
D2
D1
D0
reserved
Ch.2 async. clock division ratio
Ch.2 IrDA I/F output logic inversion
Ch.2 IrDA I/F input logic inversion
Ch.2 interface mode selection 1
1
0
0
1
0
1
0
IRMD2[1:0]
–
I/F mode
reserved
IrDA 1.0
reserved
General I/F
–
X
X
X
X
X
–
R/W
R/W
R/W
R/W
0 when being read.
Valid only in
asynchronous mode.
00401F4
(B) 1 1/8 0 1/16
1 Inverted 0 Direct
1 Inverted 0 Direct
Serial I/F Ch.2
IrDA register
III PERIPHERAL BLOCK: SERIAL I NTERFACE
B-III-8-30 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
0x0 to 0xFF(0x7F)TXD37
TXD36
TXD35
TXD34
TXD33
TXD32
TXD31
TXD30
D7
D6
D5
D4
D3
D2
D1
D0
Serial I/F Ch.3 transmit data
TXD37(36) = MSB
TXD30 = LSB
X
X
X
X
X
X
X
X
R/W00401F5
(B)
Serial I/F Ch.3
transmit data
register
0x0 to 0xFF(0x7F)RXD37
RXD36
RXD35
RXD34
RXD33
RXD32
RXD31
RXD30
D7
D6
D5
D4
D3
D2
D1
D0
Serial I/F Ch.3 receive data
RXD37(36) = MSB
RXD30 = LSB
X
X
X
X
X
X
X
X
R00401F6
(B)
Serial I/F Ch.3
receive data
register
–
TEND3
FER3
PER3
OER3
TDBE3
RDBF3
D7–6
D5
D4
D3
D2
D1
D0
reserved
Ch.3 transmit-completion flag
Ch.3 flaming error flag
Ch.3 parity error flag
Ch.3 overrun error flag
Ch.3 transmit data buffer empty
Ch.3 receive data buffer full
–
0
0
0
0
1
0
–
R
R/W
R/W
R/W
R
R
0 when being read.
Reset by writing 0.
Reset by writing 0.
Reset by writing 0.
00401F7
(B) –
1 Error 0 Normal
1
Transmitting
0 End
1 Error 0 Normal
1 Error 0 Normal
1 Empty 0 Buffer full
1 Buffer full 0 Empty
Serial I/F Ch.3
status register
TXEN3
RXEN3
EPR3
PMD3
STPB3
SSCK3
SMD31
SMD30
D7
D6
D5
D4
D3
D2
D1
D0
Ch.3 transmit enable
Ch.3 receive enable
Ch.3 parity enable
Ch.3 parity mode selection
Ch.3 stop bit selection
Ch.3 input clock selection
Ch.3 transfer mode selection 1
1
0
0
1
0
1
0
SMD3[1:0] Transfer mode
8-bit asynchronous
7-bit asynchronous
Clock sync. Slave
Clock sync. Master
0
0
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Valid only in
asynchronous mode.
00401F8
(B)
Serial I/F Ch.3
control register 1 Enabled 0 Disabled
1 Enabled 0 Disabled
1 With parity 0 No parity
1 Odd 0 Even
1 2 bits 0 1 bit
1 #SCLK3 0
Internal clock
–
DIVMD3
IRTL3
IRRL3
IRMD31
IRMD30
D7–5
D4
D3
D2
D1
D0
reserved
Ch.3 async. clock division ratio
Ch.3 IrDA I/F output logic inversion
Ch.3 IrDA I/F input logic inversion
Ch.3 interface mode selection 1
1
0
0
1
0
1
0
IRMD3[1:0]
–
I/F mode
reserved
IrDA 1.0
reserved
General I/F
–
X
X
X
X
X
–
R/W
R/W
R/W
R/W
0 when being read.
Valid only in
asynchronous mode.
00401F9
(B) 1 1/8 0 1/16
1 Inverted 0 Direct
1 Inverted 0 Direct
Serial I/F Ch.3
IrDA register
–
0 to 7
0 to 7
–
–
PSIO02
PSIO01
PSIO00
–
P8TM2
P8TM1
P8TM0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Serial interface Ch.0
interrupt level
reserved
8-bit timer 0–3 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040269
(B)
8-bit timer,
serial I/F Ch.0
interrupt
priority register
–
0 to 7
0 to 7
–
–
PAD2
PAD1
PAD0
–
PSIO12
PSIO11
PSIO10
D7
D6
D5
D4
D3
D2
D1
D0
reserved
A/D converter interrupt level
reserved
Serial interface Ch.1
interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
004026A
(B)
Serial I/F Ch.1,
A/D interrupt
priority register
–
ESTX1
ESRX1
ESERR1
ESTX0
ESRX0
ESERR0
D7–6
D5
D4
D3
D2
D1
D0
reserved
SIF Ch.1 transmit buffer empty
SIF Ch.1 receive buffer full
SIF Ch.1 receive error
SIF Ch.0 transmit buffer empty
SIF Ch.0 receive buffer full
SIF Ch.0 receive error
– –
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.0040276
(B) 1 Enabled 0 Disabled
Serial I/F
interrupt
enable register
III PERIPHERAL BLOCK: SERIAL I NTERFACE
S1C33L03 FUNCTION PART EPSON B-III-8-31
A-1
B-III
SIF
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
FSTX1
FSRX1
FSERR1
FSTX0
FSRX0
FSERR0
D7–6
D5
D4
D3
D2
D1
D0
reserved
SIF Ch.1 transmit buffer empty
SIF Ch.1 receive buffer full
SIF Ch.1 receive error
SIF Ch.0 transmit buffer empty
SIF Ch.0 receive buffer full
SIF Ch.0 receive error
– –
X
X
X
X
X
X
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.0040286
(B) 1 Factor is
generated 0 No factor is
generated
Serial I/F
interrupt factor
flag register
RSTX0
RSRX0
R8TU3
R8TU2
R8TU1
R8TU0
R16TC5
R16TU5
D7
D6
D5
D4
D3
D2
D1
D0
SIF Ch.0 transmit buffer empty
SIF Ch.0 receive buffer full
8-bit timer 3 underflow
8-bit timer 2 underflow
8-bit timer 1 underflow
8-bit timer 0 underflow
16-bit timer 5 comparison A
16-bit timer 5 comparison B
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0040292
(B) 1 IDMA
request 0 Interrupt
request
16-bit timer 5,
8-bit timer,
serial I/F Ch.0
IDMA request
register
RP7
RP6
RP5
RP4
–
RADE
RSTX1
RSRX1
D7
D6
D5
D4
D3
D2
D1
D0
Port input 7
Port input 6
Port input 5
Port input 4
reserved
A/D converter
SIF Ch.1 transmit buffer empty
SIF Ch.1 receive buffer full
0
0
0
0
–
0
0
0
R/W
R/W
R/W
R/W
–
R/W
R/W
R/W
0 when being read.
0040293
(B) 1 IDMA
request 0 Interrupt
request
1 IDMA
request 0 Interrupt
request
–
Serial I/F Ch.1,
A/D,
port input 4–7
IDMA request
register
DESTX0
DESRX0
DE8TU3
DE8TU2
DE8TU1
DE8TU0
DE16TC5
DE16TU5
D7
D6
D5
D4
D3
D2
D1
D0
SIF Ch.0 transmit buffer empty
SIF Ch.0 receive buffer full
8-bit timer 3 underflow
8-bit timer 2 underflow
8-bit timer 1 underflow
8-bit timer 0 underflow
16-bit timer 5 comparison A
16-bit timer 5 comparison B
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0040296
(B) 1 IDMA
enabled 0 IDMA
disabled
16-bit timer 5,
8-bit timer,
serial I/F Ch.0
IDMA enable
register
DEP7
DEP6
DEP5
DEP4
–
DEADE
DESTX1
DESRX1
D7
D6
D5
D4
D3
D2
D1
D0
Port input 7
Port input 6
Port input 5
Port input 4
reserved
A/D converter
SIF Ch.1 transmit buffer empty
SIF Ch.1 receive buffer full
0
0
0
0
–
0
0
0
R/W
R/W
R/W
R/W
–
R/W
R/W
R/W
0 when being read.
0040297
(B) 1 IDMA
enabled 0 IDMA
disabled
1 IDMA
enabled 0 IDMA
disabled
–
Serial I/F Ch.1,
A/D,
port input 4–7
IDMA enable
register
T8CH5S0
SIO3TS0
T8CH4S0
SIO3RS0
SIO2TS0
SIO3ES0
SIO2RS0
SIO2ES0
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 5 underflow
SIO Ch.3 transmit buffer empty
8-bit timer 4 underflow
SIO Ch.3 receive buffer full
SIO Ch.2 transmit buffer empty
SIO Ch.3 receive error
SIO Ch.2 receive buffer full
SIO Ch.2 receive error
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00402C5Interrupt factor
FP function
switching
register
1 SIO Ch.3
TXD Emp. 0 FP6
1 SIO Ch.3
RXD Full 0 FP4
1 SIO Ch.2
TXD Emp. 0 FP3
1 SIO Ch.3
RXD Err. 0 FP2
1 SIO Ch.2
RXD Full 0 FP1
1 SIO Ch.2
RXD Err. 0 FP0
1 T8 Ch.5 UF 0 FP7
1 T8 Ch.4 UF 0 FP5
T8CH5S1
T8CH4S1
SIO3ES1
SIO2ES1
SIO3TS1
SIO3RS1
SIO2TS1
SIO2RS1
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 5 underflow
8-bit timer 4 underflow
SIO Ch.3 receive error
SIO Ch.2 receive error
SIO Ch.3 transmit buffer empty
SIO Ch.3 receive buffer full
SIO Ch.2 transmit buffer empty
SIO Ch.2 receive buffer full
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00402CBInterrupt factor
TM16 function
switching
register 1 SIO Ch.3
RXD Err. 0 TM16 Ch.3
comp.A
1 SIO Ch.2
RXD Err. 0 TM16 Ch.3
comp.B
1 SIO Ch.3
TXD Emp. 0 TM16 Ch.4
comp.A
1 SIO Ch.3
RXD Full 0 TM16 Ch.4
comp.B
1 SIO Ch.2
TXD Emp. 0 TM16 Ch.5
comp.A
1 SIO Ch.2
RXD Full 0 TM16 Ch.5
comp.B
1 T8 Ch.5 UF 0 TM16 Ch.2
comp.A
1 T8 Ch.4 UF 0 TM16 Ch.2
comp.B
III PERIPHERAL BLOCK: SERIAL I NTERFACE
B-III-8-32 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
CFP07
CFP06
CFP05
CFP04
CFP03
CFP02
CFP01
CFP00
D7
D6
D5
D4
D3
D2
D1
D0
P07 function selection
P06 function selection
P05 function selection
P04 function selection
P03 function selection
P02 function selection
P01 function selection
P00 function selection
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Extended functions
(0x402DF)
00402D0
(B) 1 #SRDY1 0 P07
1 #SCLK1 0 P06
1 SOUT1 0 P05
1 SIN1 0 P04
1 #SRDY0 0 P03
1 #SCLK0 0 P02
1 SOUT0 0 P01
1 SIN0 0 P00
P0 function
select register
–
SSRDY3
SSCLK3
SSOUT3
SSIN3
D7–4
D3
D2
D1
D0
reserved
Serial I/F Ch.3 SRDY selection
Serial I/F Ch.3 SCLK selection
Serial I/F Ch.3 SOUT selection
Serial I/F Ch.3 SIN selection
– –
0
0
0
0
–
R/W
R/W
R/W
R/W
00402D7Port SIO
function
extension
register
1 #SRDY3 0
P32/
#DMAACK0
1 #SCLK3 0
P15/EXCL4/
#DMAEND0
1 SOUT3 0
P16/EXCL5/
#DMAEND1
1 SIN3 0
P33/
#DMAACK1
–
SSRDY2
SSCLK2
SSOUT2
SSIN2
D7–4
D3
D2
D1
D0
reserved
Serial I/F Ch.2 SRDY selection
Serial I/F Ch.2 SCLK selection
Serial I/F Ch.2 SOUT selection
Serial I/F Ch.2 SIN selection
–
0
0
0
0
–
R/W
R/W
R/W
R/W
00402DB 1 #SRDY2 0 P24/TM2
1 #SCLK2 0 P25/TM3
1 SOUT2 0 P26/TM4
1 SIN2 0 P27/TM5
Port SIO
function
extension
register
–
CFEX7
CFEX6
CFEX5
CFEX4
CFEX3
CFEX2
CFEX1
CFEX0
D7
D6
D5
D4
D3
D2
D1
D0
P07 port extended function
P06 port extended function
P05 port extended function
P04 port extended function
P31 port extended function
P21 port extended function
P10, P11, P13 port extended
function
P12, P14 port extended function
0
0
0
0
0
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00402DF
(B)
Port function
extension
register
1
#DMAEND3
0 P07, etc.
1
#DMAACK3
0 P06, etc.
1
#DMAEND2
0 P05, etc.
1
#DMAACK2
0 P04, etc.
1 #GARD 0 P31, etc.
1 #GAAS 0 P21, etc.
1 DST0
DST1
DPC0
0 P10, etc.
P11, etc.
P13, etc.
1 DST2
DCLK 0 P12, etc.
P14, etc.
CFP07–CFP00: P0[ 7:0 ] p in func tio n select io n (D[7:0 ]) / P 0 fu nctio n sele ct regist er (0 x4 0 2D0 )
Selects the pins used for the serial interface.
Write "1": Seri al-i nterface input/output pin
Write "0": I/ O port pin
Read: Valid
Select the pins used for the serial interface from among P00 through P07 by writing "1" to CFP00 thr ough CFP0 7.
P00–P0 3 (SIN0, SOU T0, #SCLK0, #SRDY0) are us ed for channel 0; P04–P07 (SIN1, SO UT1, #SCLK1,
#SRD Y1) are used for channel 1. If the bit for a pin is set to "0", the pin functions as an I/O port.
The nec essary input/output pi ns differ depending on the transfer mode set (see Table 8.3).
At c old start, CFP is set to "0" (I/O port). At hot start, CFP retains its state from prior to the initial reset.
SSIN3: Serial I/F Ch.3 SIN selection (D0) / Port SIO function extension register (0x402D7)
Switches the function of pin P33/#DMAACK1/SIN3.
Write "1": SIN3
Write "0": P33/#DMAACK1
Read: Valid
To use the pin as SIN3, set SSIN3 (D0 / 0x402D 7) to " 1" and CFP33 (D 3 / 0x402DC) to "0" .
To use the pin as P33 or #DMAAC K1, set this bit to "0".
At po wer-on, this bit is set to "0".
III PERIPHERAL BLOCK: SERIAL I NTERFACE
S1C33L03 FUNCTION PART EPSON B-III-8-33
A-1
B-III
SIF
SSOUT3: Serial I/F Ch.3 SOUT selection (D1) / Port SIO function extension register (0x402D7)
Switches the function of pin P16/EXCL5/#DMAEND1/SOUT3.
Write "1": SOUT 3
Write "0": P16 /EXCL5/#DMAEND1
Read: Valid
To use the pin as SOUT3, set SSOUT3 (D1 / 0x402D7) t o "1" a nd CFP1 6 (D6 / 0x402D4) t o "0".
To use the pin as P16, EXCL5, or #DMAEND1, set this bit to "0".
At po wer-on, this bit is set to "0".
SSCLK3: Seria l I /F Ch.3 SCLK selection (D2) / Port SIO functi on extension register (0x402D7)
Sw itches the function of pi n P15/EXCL4 /#DMAEND 0/#SCLK3.
Write "1": # SCLK3
Write "0": P15 /EXCL4/#DMAEND0
Read: Valid
To use the pin as #SCLK 3, set SSCLK3 (D2 / 0x402D 7) to " 1" and CFP15 (D5 / 0x402D4) to "0".
To use the pin as P15, EXCL4, or #DMAEND0, set this bit to "0".
At po wer-on, this bit is set to "0".
SSRDY3: Serial I/F Ch.3 SRDY selection (D3) / Port SIO function extension register (0x402D7)
Switches the function of pin P32/#DMAACK0/#SRDY3.
Write "1": # SRDY3
Write "0": P32/#DMAACK0
Read: Valid
To use the pin as #SRDY 3, set SSRDY3 (D3 / 0x402D 7) to " 1" and CFP32 (D2 / 0x402DC) to "0" .
To use the pin as P32 or #DMAAC K0, set this bit to "0".
At po wer-on, this bit is set to "0".
SSIN2: Serial I/F Ch.2 SIN selection (D0) / Port SIO function extension register (0x402DB)
Sw itches the function of pi n P27/TM5/ SIN2 .
Write "1": SIN2
Write "0": P27 /TM5
Read: Valid
To use the pin as SIN2, set SSIN2 (D0 / 0x402D B) to "1" and CFP27 (D 7 / 0x402D 8) to "0".
To use the pin as P27 or TM5, set this bit to "0".
At po wer-on, this bit is set to "0".
SSOUT2: Serial I/F Ch.2 SOUT selection (D1) / Port SIO function extension register (0x402DB)
Sw itches the function of pi n P26/TM4/ SO UT2.
Write "1": SOUT 2
Write "0": P26 /TM4
Read: Valid
To use the pin as SOUT2 , set SSOUT 2 (D1 / 0x402D B) to "1" and CFP26 (D 6 / 0x402D8) t o "0".
To use the pin as P26 or TM4, set this bit to "0".
At po wer-on, this bit is set to "0".
III PERIPHERAL BLOCK: SERIAL I NTERFACE
B-III-8-34 EPSON S1C33L03 FUNCTION PART
SSCLK2: Serial I/F Ch.2 SCLK selection (D2) / Port SIO function extension register (0x402DB)
Sw itches the function of pi n P25/TM3/ #SCLK2.
Write "1": # SCLK2
Write "0": P25 /TM3
Read: Valid
To use the pin as #SCLK2, set SSCLK2 (D2 / 0x402DB) to " 1" and CFP25 (D5 / 0x402D 8) to "0".
To use the pin as P25 or TM3, set this bit to "0".
At po wer-on, this bit is set to "0".
SSRDY2: Serial I/F Ch.2 SRDY selection (D3) / Port SIO function extension register (0x402DB)
Sw itches the function of pi n P24/TM2/ #SRDY2.
Write "1": # SRDY2
Write "0": P24 /TM2
Read: Valid
To use the pin as #SRDY 2, set SSRDY2 (D3 / 0x402D B) to " 1" and CFP24 (D4 / 0x402D8) to "0".
To use the pin as P24 or TM2, set this bit to "0".
At po wer-on, this bit is set to "0".
CFEX7–CFEX4: P0[ 7:4] p in fu nc tio n select io n (D[7:4 ]) / P or t functio n exten sio n regi ster (0x40 2D F )
Selects the extended function o f pins P07–P0 4.
Write "1": Fun ction-extended pin
Write "0": I/O- port/s erial I/O pi n
Read: Valid
When CFEX[7:4] is set to "1", the P07–P04 ports function as DMA signal output ports. When CFEX[7:4] = "0",
the CFP0[7:4] bit becomes effective, so the settings of these bits determine whether the P07–P04 ports function as
I/O port s or serial interface Ch.1 signal output ports.
At c old start, CFEX[7:4] is set to "0" (I/O-port/serial I/O pin). At hot start, CFEX[7:4] retains its state from prior to
the initial reset.
TXD07–TXD00: Ch.0 transmit data (D[7:0]) / Serial I/F Ch.0 transmit data register (0x401E0)
TXD17–TXD10: Ch.1 transmit data (D[7:0]) / Serial I/F Ch.1 transmit data register (0x401E5)
TXD27–TXD20: Ch.2 transmit data (D[7:0]) / Serial I/F Ch.2 transmit data register (0x401F0)
TXD37–TXD30: Ch.3 transmit data (D[7:0]) / Serial I/F Ch.3 transmit data register (0x401F5)
Sets tran sm it d ata .
When data is written to this register (transmit buffer) after "1" is written to TXENx, a transmit operation is begun.
TD BEx is set to "1" (tra nsmi t-buffer em pty) when the data is transferred to the shift register. A transmit-buffer
empty interrupt factor is simultaneously generated. The next transmit data can be written to the buffer at any time
thereafter, even when the serial interface is sending data.
In the 7-bit asynchronous mode, TXDx7 (MSB) is ignored.
The serial-converted data is output from the SOUT pin beginning with the LSB, in which the bits set to "1" are
outpu t as high-lev el signals and those set to "0" output as low-level signals.
This regist er can be read as well as written.
At i nitial reset, the content of TXDx becomes indeterminate.
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RXD07–RXD00: Ch.0 receive data (D[7:0]) / Serial I/F Ch.0 receive data register (0x401E1)
RXD17–RXD10: Ch.1 receive data (D[7:0]) / Serial I/F Ch.1 receive data register (0x401E6)
RXD27–RXD20: Ch.2 receive data (D[7:0]) / Serial I/F Ch.2 receive data register (0x401F1)
RXD37–RXD30: Ch.3 receive data (D[7:0]) / Serial I/F Ch.3 receive data register (0x401F6)
Stores receive d d ata .
When a receive operation is completed and the data received in the shift register is transferred to this register
(receive buffer), RDBFx is set to "1" (receive buffer full). At the same time, a receive-buffer full interrupt factor is
generated. Thereafter, the data can be read out at any time before a receive operation for the next data is completed.
If the next data receive operation is completed before this register is read out, the data in it is overwritten with the
newly received data, causing an overrun error to occur.
In the 7-bit asynchronous mode, "0" is stored in RXDx7.
The serial data input from the SINx pin is converted into parallel data beginning with the LSB, with the high-level
signals changed to "1"s and the low-level signals changed to "0"s. The resulting data is stored in this buffer.
This regist er is a read-only register, so no data can be written to it.
At i nitial reset, the content of RXDx becomes indeterminate.
TEND0: Ch.0 transmit-completion flag (D5) / Serial I/F Ch.0 status register (0x401E2)
TEND1: Ch.1 transmit-completion flag (D5) / Serial I/F Ch.1 status register (0x401E7)
TEND2: Ch.2 transmit-completion flag (D5) / Serial I/F Ch.2 status register (0x401F2)
TEND3: Ch.3 transmit-completion flag (D5) / Serial I/F Ch.3 status register (0x401F7)
Indicates the transmission status.
Read "1": During transmitting
Read "0": End of transmission
Write: Invalid
TE N Dx go es "1" w hen data is being transmitted and goes "0" when the transmission has completed.
When data is transmitted successively in clock-synchronized master mode or asynchronous mode, TENDx
maintains "1" until all data is transmitted (see Figure 8.4 and Figure 8.12). In clock-synchronized slave mode,
TENDx goes "0" every time 1-byte data is transmitted (see Figure 8.5).
At i nitial reset, TENDx is set to "0" (End of transmission).
FER0: Ch.0 framing-error flag (D4) / Serial I/F Ch.0 status register (0x401E2)
FER1: Ch.1 framing-error flag (D4) / Serial I/F Ch.1 status register ( 0 x401E7)
FER2: Ch.2 framing-error flag (D4) / Serial I/F Ch.2 status register ( 0 x401F2)
FER3: Ch.3 framing-error flag (D4) / Serial I/F Ch.3 status register ( 0 x401F7)
Indicates whether a framing error occurred.
Read "1": An erro r occurred
Read "0": No erro r occurred
Write "1": Invalid
Write "0": R eset to "0"
The FERx fla g is an error flag indicating whether a framing error occurred. When an error has occurred, it is set to
"1". A framing error occurs when data with a stop bit = "0" is received in the asynchronous mode.
The FERx fla g is reset by writing "0".
At i nitial reset, as well as when RXENx and TXENx both are set to "0", the FERx flag is set to "0" (no error).
III PERIPHERAL BLOCK: SERIAL I NTERFACE
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PER0: Ch.0 parity-error flag (D3) / Serial I/F Ch.0 status register (0x401E2)
PER1: Ch.1 parity-error flag (D3) / Serial I/F Ch.1 status register (0x401E7)
PER2: Ch.2 parity-error flag (D3) / Serial I/F Ch.2 status register (0x401F2)
PER3: Ch.3 parity-error flag (D3) / Serial I/F Ch.3 status register (0x401F7)
Indicates whe the r a p arity error occu rred .
Read "1": An erro r occurred
Read "0": No erro r occurred
Write "1": Invalid
Write "0": R eset to "0"
The PERx fla g is an error flag indicating whether a parity error occurred. When an error has occurred, it is set to
"1". Parity checks are valid only in the asynchronous mode with EPRx set to "1" (parity added). This check is
performed when the received data is transferred from the shift register to the receive data register.
The PERx fla g is reset by writing "0".
At i nitial reset, as well as when RXENx and TXENx both are set to "0", PERx is set to "0" (no error).
OER0: Ch.0 overrun-error flag (D2) / Serial I/F Ch.0 status register (0x401E2)
OER1: Ch.1 overrun-error flag (D2) / Serial I/F Ch.1 status register (0x401E7)
OER2: Ch.2 overrun-error flag (D2) / Serial I/F Ch.2 status register (0x401F2)
OER3: Ch.3 overrun-error flag (D2) / Serial I/F Ch.3 status register (0x401F7)
Indicates whether an overrun error occurred.
Read "1": An erro r occurred
Read "0": No erro r occurred
Write "1": Invalid
Write "0": R eset to "0"
The OERx flag is an error flag indicating whether an overrun error occurred. When an error has occurred, it is set
to "1". An overrun error occurs when the next receive operation is completed before the receive data register is
read out, resulting in the receive data register being overwritten.
The OERx flag is reset by writing "0".
At i nitial reset, as well as when RXENx and TXENx both are set to "0", OERx is set to "0" (no error).
TDBE0: Ch.0 transmit data buffer empty (D1) / Serial I/F Ch.0 status register (0x401E2)
TDBE1: Ch.1 transmit data buffer empty (D1) / Serial I/F Ch.1 status register (0x401E7)
TDBE2: Ch.2 transmit data buffer empty (D1) / Serial I/F Ch.2 status register (0x401F2)
TDBE3: Ch.3 transmit data buffer empty (D1) / Serial I/F Ch.3 status register (0x401F7)
Indicates the status of the transmit data register (buffer).
Read "1": Buffer empty
Read "0": Buffer full
Write: Invalid
TD BEx is s et to "0" when transmit data is written to the transmit data register, and is set to "1" when this data is
transferred to the shift register (transmit operation started).
Transmit data is written to the transmit data register when this bit = "1".
At i nitial reset, TDBEx is set to "1" (buffer empty).
III PERIPHERAL BLOCK: SERIAL I NTERFACE
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RDBF0: Ch.0 receive data buffer full (D0) / Serial I/F Ch.0 status register (0x401E2)
RDBF1: Ch.1 receive data buffer full (D0) / Serial I/F Ch.1 status register (0x401E7)
RDBF2: Ch.2 receive data buffer full (D0) / Serial I/F Ch.2 status register (0x401F2)
RDBF3: Ch.3 receive data buffer full (D0) / Serial I/F Ch.3 status register (0x401F7)
Indicates the status of the receive data register (buffer).
Read "1": Buffer full
Read "0": Buffer empty
Write: Invalid
RD BFx is set to "1" when the data received in the shift register is transferred to the receive data register (receive
operation completed), indicating that the received data can be read out. This bit is reset to "0" when the data is read
out.
At i nitial reset, RDBFx is set to "0" (buffer empty).
TXEN0: Ch.0 transmit enable (D7) / Serial I/F Ch.0 control register (0x401E3)
TXEN1: Ch.1 transmit enable (D7) / Serial I/F Ch.1 control register (0x401E8)
TXEN2: Ch.2 transmit enable (D7) / Serial I/F Ch.2 control register (0x401F3)
TXEN3: Ch.3 transmit enable (D7) / Serial I/F Ch.3 control register (0x401F8)
Enables each channel for transmit operations.
Write "1": Transmit enabled
Write "0": T ransmit disabled
Read: Valid
When TXENx for a channel is set to "1", the channel is enabled for transmit operations. When TXENx is set to "0",
the channel is disabled for transmit operations.
Alwa ys make sure the TXENx = "0" before setting the transfer mode and other conditions.
At i nitial reset, TXENx is set to "0" (transmit disabled).
RXEN0: Ch.0 receive enable (D6) / Serial I/F Ch.0 control register (0x401E3)
RXEN1: Ch.1 receive enable (D6) / Serial I/F Ch.1 control register (0x401E8)
RXEN2: Ch.2 receive enable (D6) / Serial I/F Ch.2 control register (0x401F3)
RXEN3: Ch.3 receive enable (D6) / Serial I/F Ch.3 control register (0x401F8)
Enables each channel for receive operations.
Write "1": Rec eive en able d
Write "0": Rec eive disabled
Read: Valid
When RXEN x for a channel is set to "1", the channel is enabled for receive operations. When RXENx is set to "0",
the channel is disabled for receive operations.
Alwa ys make sure the RXENx = "0" before setting the transfer mode and ot her con ditions.
At i nitial reset, RXENx is set to "0" (receive disabled).
III PERIPHERAL BLOCK: SERIAL I NTERFACE
B-III-8-38 EPSON S1C33L03 FUNCTION PART
EPR0: Ch.0 parity enable (D5) / Serial I/F Ch.0 control register (0x401E3)
EPR1: Ch.1 parity enable (D5) / Serial I/F Ch.1 control register (0x401E8)
EPR2: Ch.2 parity enable (D5) / Serial I/F Ch.2 control register (0x401F3)
EPR3: Ch.3 parity enable (D5) / Serial I/F Ch.3 control register (0x401F8)
Selects a parity fu nc tio n.
Write "1": Pari ty added
Write "0": No parity added
Read: Valid
EPRx is used to select whether receive data is to be checked for parity, and whether a parity bit is to be added to
transmit data. When EPRx is set to "1", the receive data is checked for parity. A parity bit is automatically added to
the transmit data. When EPRx is set to "0", parity is not checked and no parity bit is added.
The parity function is only valid in the asynchronous mode. Settings of EPRx have no effect in the clock-
synchroni ze d m od e.
At i nitial re se t, EPRx b eco m es inde ter m ina te .
PMD0: Ch.0 parity mode selection (D4) / Serial I/F Ch.0 control register (0x401E3)
PMD1: Ch.1 parity mode selection (D4) / Serial I/F Ch.1 control register (0x401E8)
PMD2: Ch.2 parity mode selection (D4) / Serial I/F Ch.2 control register (0x401F3)
PMD3: Ch.3 parity mode selection (D4) / Serial I/F Ch.3 control register (0x401F8)
Selects an odd or even parity.
Write "1": Odd parity
Write "0": E ven parity
Read: Valid
Odd parity is selected by writing "1" to PMDx, and even parity is selected by writing "0". Parity check and the
addition of a parity bit are only effective in asynchronous transfers in which EPRx is set to "1". If EPRx = "0",
settings of PMDx do not have any ef fe ct.
At i nitial reset, PMDx becomes indeterminate.
STPB0: Ch.0 stop bit selection (D3) / Serial I/F Ch.0 control register (0x401E3)
STPB1: Ch.1 stop bit selection (D3) / Serial I/F Ch.1 control register (0x401E8)
STPB2: Ch.2 stop bit selection (D3) / Serial I/F Ch.2 control register (0x401F3)
STPB3: Ch.3 stop bit selection (D3) / Serial I/F Ch.3 control register (0x401F8)
Selects a stop-bit length during the performance of an asynchronous transfer.
Write "1": 2 bits
Write "0": 1 bit
Read: Valid
ST PBx is only valid in an asynchronous transfer. Two stop bits are selected by writing "1" to STPBx , and one stop
bit is selected by writing "0". The start bit is fixed at 1 bit.
Settings of STPBx are ignored during the performance of a clock-synchronized transfer.
At i nitial reset, STPBx becomes indeterminate.
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SSCK0: Ch.0 input clock selection (D2) / Serial I/F Ch.0 control register (0x401E3)
SSCK1: Ch.1 input clock selection (D2) / Serial I/F Ch.1 control register (0x401E8)
SSCK2: Ch.2 input clock selection (D2) / Serial I/F Ch.2 control register (0x401F3)
SSCK3: Ch.3 input clock selection (D2) / Serial I/F Ch.3 control register (0x401F8)
Selects the clock source for an asynchronous transfer.
Write "1": # SCLK (external clock)
Write "0": Inte rnal clock
Read: Valid
During ope ration in the asynchronous mode, this bit is used to select the clock source between an internal clock
(output by an 8-bit programmable timer) and an external clock (input from the #SCLKx pin). An external clock is
selected by writing "1" to this bit, and an internal clock is selected by writing "0".
At i nitial reset, SSCKx becomes indeterminate.
SMD01–SMD00: Ch.0 transfer mode selection (D[1:0]) / Serial I/F Ch.0 control register (0x401E3)
SMD11–SMD10: Ch.1 transfer mode selection (D[1:0]) / Serial I/F Ch.1 control register (0x401E8)
SMD21–SMD20: Ch.2 transfer mode selection (D[1:0]) / Serial I/F Ch.2 control register (0x401F3)
SMD31–SMD30: Ch.3 transfer mode selection (D[1:0]) / Serial I/F Ch.3 control register (0x401F8)
Sets the transfer mode of the serial interface as shown in Table 8.15 below.
Table 8.15 Setting of Transfer Mode
SMDx1 SMDx0 Transfer mode
118-bit as ynchr ono us mode
107-bit as ynchr ono us mode
01Clock-synchronized slave mode
00Clock-synchronized master mode
The SMDx bit can be read as well as written.
When using the IrDA interface, always be sure to set an asynchronous mode for the transfer mode.
At i nitial reset, SMDx becomes indeterminate.
DIVMD0: Sampling clock division ratio (D4) / Serial I/F Ch.0 IrDA register (0x401E4)
DIVMD1: Sampling clock division ratio (D4) / Serial I/F Ch.1 IrDA register (0x401E9)
DIVMD2: Sampling clock division ratio (D4) / Serial I/F Ch.2 IrDA register (0x401F4)
DIVMD3: Sampling clock division ratio (D4) / Serial I/F Ch.3 IrDA register (0x401F9)
Selects the division ratio of the sampling clock.
Write "1": 1 /8
Write "0": 1 /16
Read: Valid
Select the division ratio necessary to generate the sampling clock for asynchronous transfers. When DIVMDx is set
to "1", the sampling clock is generated from the input clock of the serial interface (output by an 8-bit
programmable t imer or input from #SCL K x) by dividing it by 8. When DIVMDx is set to "0", the input clock is
divided by 16.
At i nitial reset, DIVMDx becomes indeterminate.
III PERIPHERAL BLOCK: SERIAL I NTERFACE
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IRTL0: Ch.0 IrDA output logic inversion (D3) / Serial I/F Ch.0 IrDA register (0x401E4)
IRTL1: Ch.1 IrDA output logic inversion (D3) / Serial I/F Ch.1 IrDA register (0x401E9)
IRTL2: Ch.2 IrDA output logic inversion (D3) / Serial I/F Ch.2 IrDA register (0x401F4)
IRTL3: Ch.3 IrDA output logic inversion (D3) / Serial I/F Ch.3 IrDA register (0x401F9)
Inverts the logic of the IrDA output signal.
Write "1": Inverted
Write "0": Not inverted
Read: Valid
When using the IrDA interface, set the logic of the SOUTx output signal to suit the infrared-ray communication
circuit that is connected external to the chip. If IRTLx is set to "1", a high pulse is output when the output data =
"0" (held low-level when the output data = "1"). If IRTLx is set to "0", a low pulse is output when the output data =
"0" (held high-level when the output data = "1").
At i nitial reset, IRTLx becomes indeterminate.
IRRL0: Ch.0 IrDA input logic inversion (D2) / Serial I/F Ch.0 IrDA register (0x401E4)
IRRL1: Ch.1 IrDA input logic inversion (D2) / Serial I/F Ch.1 IrDA register (0x401E9)
IRRL2: Ch.2 IrDA input logic inversion (D2) / Serial I/F Ch.2 IrDA register (0x401F4)
IRRL3: Ch.3 IrDA input logic inversion (D2) / Serial I/F Ch.3 IrDA register (0x401F9)
Inverts the logic of the IrDA input signal.
Write "1": Inverted
Write "0": Not inverted
Read: Valid
When using the IrDA interface, set the logic of the signal that is input from an external infrared-ray communication
circuit to the chip to suit the serial interface. If IRRLx is set to "1", a high pulse is input as a logic "0". If IRRLx is
set to "0", a low pulse is input as a logic "0".
At i nitial reset, IRRLx becomes indeterminate.
IRMD01–IRMD00: Ch.0 IrDA interface mode selection (D[1:0]) / Serial I/F Ch.0 IrDA register (0x401E4)
IRMD11–IRMD10: Ch.1 IrDA interface mode selection (D[1:0]) / Serial I/F Ch.1 IrDA register (0x401E9)
IRMD21–IRMD20: Ch.2 IrDA interface mode selection (D[1:0]) / Serial I/F Ch.2 IrDA register (0x401F4)
IRMD31–IRMD30: Ch.3 IrDA interface mode selection (D[1:0]) / Serial I/F Ch.3 IrDA register (0x401F9)
Selects the IrDA interface function.
Table 8.16 IrDA Interface Setting
IRMDx1 IRMDx0 Interface mode
11Do not set. (reserved)
10IrDA 1.0 interface
01Do not set. (reserved)
00Normal interface
When using the IrDA interface function, write "10" to IRMDx while setting to an asynchronous mode for the
transfer mode. If the IrDA interface function is not to be used, write "00" to IRMDx.
At i nitial reset, IRMDx becomes indeterminate.
Note: Thi s selection must always be pe rformed before the tra nsfer mo de and other conditi ons are set.
PSIO02–PSIO00: Ch.0 interrupt level (D[6:4]) / 8-bit timer, serial I/F Ch.0 interrupt priority register (0x40269)
PSIO12–PSIO10: Ch.1 interrupt level (D[2:0]) / Serial I/F Ch.1, A/D interrupt priority register (0x4026A)
Sets the priority level of the serial-interface interrupt.
The interrupt priority level can be set for each channel in the range of 0 to 7.
At i nitial reset, PSIOx becomes indeterminate.
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ESERR0, ESRX0, ESTX0: Ch.0 interrupt enable (D0,D1 ,D2) / Se rial I /F i nterr upt enab le regis te r (0x402 76)
ESERR1, ESRX1, ESTX1: Ch.1 interrupt enable (D3,D4 ,D5) / Se rial I /F i nterr upt enab le regis te r (0x402 76)
Enable or disable interrupt generation to the CPU.
Write "1": Inte rrupt enabled
Write "0": Inte rrupt disabled
Read: Valid
The ESERR x, ESRXx, and ESTXx bits are interrupt enable bits corresponding to receive-error, receive-buffer full,
and transmit-buffer empty interrupt factors, respectively, in each channel. The interrupts for which this bit is set to
"1" are enabled, and the interrupts for which this bit is set to "0" are disabled.
At i nitial reset, all these bits are set to "0" (interrupts disabled).
FSERR0, FSRX0, FSTX0: Ch.0 interrupt factor flags (D0,D1,D2) / Serial I/F interrupt factor flag register (0x40286)
FSERR1, FSRX1, FSTX1: Ch.1 interrupt factor flags (D3,D4,D5) / Serial I/F interrupt factor flag register (0x40286)
Indicate the status of serial-interface interrupt generation.
When read
Read "1": An inte rrupt fa cto r o ccu rr ed
Read "0": No inte rrupt fa cto r o ccu rr ed
When written using the rese t-onl y m etho d (d ef au lt)
Write "1": Flag is reset
Write "0": Invalid
When written using the read /w rite m et ho d
Write "1": Flag is set
Write "0": Flag is reset
The FSER Rx, FSRXx, and FSTXx fla gs are interrupt factor flags corresponding to receive-error, receive-buffer
full, and transmit-buffer empty interrupts, respectively, in each channel. The flag is set to "1" when each interrupt
factor o ccu rs.
A transmit-buffer empty interrupt factor occurs when transmit data is transferred from the transmit data register to
the shift register.
A receive-bu ff er full interrupt factor occurs when receive data is transferred from the shift register to the receive
data register.
A receive-error interrupt factor occurs when a parity, framing, or overrun error is detected during reception of data.
At t his time, if the following conditions are met, an interrupt to the CPU is generated:
1. The corresponding interrupt enable register bit is set to "1".
2. No other interrupt request of a higher prior ity has been generated.
3. The PSR's IE bit is set to "1" (interrupts enabled).
4. The set value of the corresponding inter rup t priority register is higher than the CPU interrupt level (IL).
When using the receive-buffer full or transmit-buffer empty interrupt factor as an IDMA request, the fact that the
above conditions are met does not necessarily mean that an interrupt request to the CPU has been output
simultaneously when an interrupt factor occurs. An interrupt is generated under the above conditions upon
completion of the data transfer by IDMA, provided that interrupts are enabled by settings on the IDMA side.
The interrupt factor flag is set to "1" whenever an interrupt factor occurs, regardless of the settings of the interrupt-
enab le and in te rru pt p rio rity regi ste rs.
If the next interrupt is to be accepted following the occurrence of an interrupt, it is necessary that the interrupt
factor flag be reset, and that the PSR be set up again (by setting the IE bit to "1" after setting the IL to a value
lower than the level indicated by the interrupt priority register, or by executing the reti instruction).
The interrupt factor flag can only be reset by writing to it in the software. Note that if the PSR is set up again to
accept interrupts generated (or if the reti instruction is executed) without resetting the interrupt factor flag, the same
interrupt occurs again. Note also that the value to be written to reset the flag is "1" when the reset-only method
(RSTONLY = " 1" ) is used, and "0" when the rea d/ write me thod (RSTONLY = "0" ) is used.
At i nitial reset, all of these flags become indeterminate, so be sure to reset them in the software.
III PERIPHERAL BLOCK: SERIAL I NTERFACE
B-III-8-42 EPSON S1C33L03 FUNCTION PART
RSRX0, RSTX0:Ch.0 IDMA request (D6, D7) /
16-bit t imer 5, 8- bit timer, serial I/F Ch.0 IDMA request register (0x40292)
RSRX1, RSTX1:Ch.1 IDMA request (D0, D1) / Serial I/F Ch.1, A/D IDMA request register (0x40293)
Specifies whether to invoke IDMA when an interrupt factor occurs.
When using the se t-o n ly m et ho d (d ef ault)
Write "1": IDMA request
Write "0": Not changed
Read: Valid
When using the read /w rite m et ho d
Write "1": IDMA request
Write "0": Inte rrupt request
Read: Valid
The RSRXx and RSTXx bits are IDMA request bits correspondin g to recei ve-buff er full and tran sm it- bu ffe r emp ty
interrupt factors, respectively. If the bit is set to "1", IDMA is invoked when an interrupt factor occurs, thus
performing a programmed data transfer. If this bit is set to "0", normal interrupt processing is performed, without
invoking IDMA.
For details on IDMA, refer to "IDMA (Intelligent DMA)".
At i nitial reset, these bits are set to "0" (interrupt request).
DESRX0, DESTX0:Ch.0 IDMA enable (D6, D7) /
16-bit t imer 5, 8- bit timer, serial I/F Ch.0 IDMA enable register (0x40296)
DESRX1, DESTX1:Ch.1 IDMA enable (D0, D1) / Serial I/F Ch.1, A/D IDMA enable register (0x40297)
Enables ID M A transfer by means of an interrupt factor.
When using the se t-o n ly m et ho d (d ef au lt)
Write "1": IDMA enabled
Write "0": Not changed
Read: Valid
When using the read /w rite m et ho d
Write "1": IDMA enabled
Write "0": IDMA disabled
Read: Valid
The DESRXx and DESTXx bits are IDMA enable bits corresponding to receive-buffer full and transmit-buffer
empty interrupt factors, respectively. If the bit is set to "1", the IDMA request by the interrupt factor is enabled. If
the bit is set to "0", the IDMA request is disabled.
At i nitial reset, these bits are set to "0" (IDMA disabled).
SIO2ES0:SIO Ch.2 receive error/FP0 interrupt factor switching
(D0) / Interrupt factor FP function switching register (0x402C5)
Switches the interrupt factor.
Write "1": S IO Ch.2 receive error
Write "0": FP0 input
Read: Valid
Set to "1" to use the SIO Ch.2 receive error interrupt.
Set to "0" to use the FP0 input interrupt.
At po wer-on, this bit is set to "0".
III PERIPHERAL BLOCK: SERIAL I NTERFACE
S1C33L03 FUNCTION PART EPSON B-III-8-43
A-1
B-III
SIF
SIO2RS0:SIO Ch.2 receive-buffer full/FP1 interrupt factor switching
(D1) / Interrupt factor FP function switching register (0x402C5)
Switches the interrupt factor.
Write "1": S IO Ch.2 receive-buffer full
Write "0": FP1 input
Read: Valid
Set to "1" to use the SIO Ch.2 receive-buffer full interrupt.
Set to "0" to use the FP1 input interrupt.
At po wer-on, this bit is set to "0".
SIO3ES0:SIO Ch.3 receive error/FP2 interrupt factor switching
(D2) / Interrupt factor FP function switching register (0x402C5)
Switches the interrupt factor.
Write "1": S IO Ch.3 receive error
Write "0": FP2 input
Read: Valid
Set to "1" to use the SIO Ch.3 receive error interrupt.
Set to "0" to use the FP2 input interrupt.
At po wer-on, this bit is set to "0".
SIO2TS0:SIO Ch.2 transmit-buffer empty/FP3 interrupt factor switching
(D3) / Interrupt factor FP function switching register (0x402C5)
Switches the interrupt factor.
Write "1": S IO Ch.2 transmit-buffer empty
Write "0": FP3 input
Read: Valid
Set to "1" to use the SIO Ch.2 transmit-buffer empty interrupt.
Set to "0" to use the FP3 input interrupt.
At po wer-on, this bit is set to "0".
SIO3RS0:SIO Ch.3 receive-buffer full/FP4 interrupt factor switching
(D4) / Interrupt factor FP function switching register (0x402C5)
Switches the interrupt factor.
Write "1": S IO Ch.3 receive-buffer full
Write "0": FP4 input
Read: Valid
Set to "1" to use the SIO Ch.3 receive-buffer full interrupt.
Set to "0" to use the FP4 input interrupt.
At po wer-on, this bit is set to "0".
T8CH4S0: 8-bit timer 4 underfl ow/FP 5 inter rupt factor swi tching
(D5) / Interrupt factor FP function switching register (0x402C5)
Switches the interrupt factor.
Write "1": 8 -bit ti mer 4 underflow
Write "0": FP5 input
Read: Valid
Set to "1" to use the 8-bit timer 4 underflow interrupt.
Set to "0" to use the FP5 input interrupt.
At po wer-on, this bit is set to "0".
III PERIPHERAL BLOCK: SERIAL I NTERFACE
B-III-8-44 EPSON S1C33L03 FUNCTION PART
SIO3TS0: SIO Ch .3 transmit-b uffer em pty/FP6 int errupt factor switching
(D6) / Interrupt factor FP function switching register (0x402C5)
Switches the interrupt factor.
Write "1": S IO Ch.3 transmit-buffer empty
Write "0": FP6 input
Read: Valid
Set to "1" to use the SIO Ch.3 transmit-buffer empty interrupt.
Set to "0" to use the FP6 input interrupt.
At po wer-on, this bit is set to "0".
T8CH5S0: 8-bit timer 5 underflow/FP7 interrupt factor switching
(D7) / Interrupt factor FP function switching register (0x402C5)
Switches the interrupt factor.
Write "1": 8 -bit ti mer 5 underflow
Write "0": FP7 input
Read: Valid
Set to "1" to use the 8-bit timer 5 underflow interrupt.
Set to "0" to use the FP7 input interrupt.
At po wer-on, this bit is set to "0".
SIO2RS1: SIO Ch.2 receive-buffer full/TM16 Ch.5 compare B interrupt factor switching
(D0) / Interrupt factor TM16 function switching register (0x402CB)
Switches the interrupt factor.
Write "1": S IO Ch.2 receive-buffer full
Write "0": T M16 Ch.5 compare B
Read: Valid
Set to "1" to use the SIO Ch.2 receive-buffer full interrupt.
Set to "0" to use the TM16 Ch.5 compare B interrupt.
At po wer-on, this bit is set to "0".
SIO2TS1: SIO Ch.2 transmit-buffer empty/TM16 Ch.5 compare A interrupt factor switching
(D1) / Interrupt factor TM16 function switching register (0x402CB)
Switches the interrupt factor.
Write "1": S IO Ch.2 transmit-buffer empty
Write "0": T M16 Ch.5 compare A
Read: Valid
Set to "1" to use the SIO Ch.2 transmit-buffer empty interrupt.
Set to "0" to use the TM16 Ch.5 compare A interrupt.
At po wer-on, this bit is set to "0".
SIO3RS1: SIO Ch.3 receive-buffer full/TM16 Ch.4 compare B interrupt factor switching
(D2) / Interrupt factor TM16 function switching register (0x402CB)
Switches the interrupt factor.
Write "1": S IO Ch.3 receive-buffer full
Write "0": T M16 Ch.4 compare B
Read: Valid
Set to "1" to use the SIO Ch.3 receive-buffer full interrupt.
Set to "0" to use the TM16 Ch.4 compare B interrupt.
At po wer-on, this bit is set to "0".
III PERIPHERAL BLOCK: SERIAL I NTERFACE
S1C33L03 FUNCTION PART EPSON B-III-8-45
A-1
B-III
SIF
SIO3TS1: SIO Ch.3 transmit-buffer empty/TM16 Ch.4 compare A interrupt factor switching
(D3) / Interrupt factor TM16 function switching register (0x402CB)
Switches the interrupt factor.
Write "1": S IO Ch.3 transmit-buffer empty
Write "0": T M16 Ch.4 compare A
Read: Valid
Set to "1" to use the SIO Ch.3 transmit-buffer empty interrupt.
Set to "0" to use the TM16 Ch.4 compare A interrupt.
At po wer-on, this bit is set to "0".
SIO2ES1: SIO Ch.2 receive error/TM16 Ch.3 compare B interrupt factor switching
(D4) / Interrupt factor TM16 function switching register (0x402CB)
Switches the interrupt factor.
Write "1": S IO Ch.2 receive error
Write "0": T M16 Ch.3 compare B
Read: Valid
Set to "1" to use the SIO Ch.2 receive error interrupt.
Set to "0" to use the TM16 Ch.3 compare B interrupt.
At po wer-on, this bit is set to "0".
SIO3ES1:SIO Ch.3 receive error/TM16 Ch.3 compare A interrupt factor switching
(D5) / Interrupt factor TM16 function switching register (0x402CB)
Switches the interrupt factor.
Write "1": S IO Ch.3 receive error
Write "0": T M16 Ch.3 compare A
Read: Valid
Set to "1" to use the SIO Ch.3 receive error interrupt.
Set to "0" to use the TM16 Ch.3 compare A interrupt.
At po wer-on, this bit is set to "0".
T8CH4S1: 8-bit ti mer 4 underflow /TM16 Ch.2 com pare B inter rupt f actor switc hing
(D6) / Interrupt factor TM16 function switching register (0x402CB)
Switches the interrupt factor.
Write "1": 8 -bit ti mer 4 underflow
Write "0": T M16 Ch.2 compare B
Read: Valid
Set to "1" to use the 8-bit timer 4 underflow interrupt.
Set to "0" to use the TM16 Ch.2 compare B interrupt.
At po wer-on, this bit is set to "0".
T8CH5S1: 8-bit ti mer 5 underflow /TM16 Ch.2 com pare A inter rupt f actor switc hing
(D7) / Int errupt fac tor TM16 function switc hing register (0x402C B)
Switches the interrupt factor.
Write "1": 8 -bit ti mer 5 underflow
Write "0": T M16 Ch.2 compare A
Read: Valid
Set to "1" to use the 8-bit timer 5 underflow interrupt.
Set to "0" to use the TM16 Ch.2 compare A interrupt.
At po wer-on, this bit is set to "0".
III PERIPHERAL BLOCK: SERIAL I NTERFACE
B-III-8-46 EPSON S1C33L03 FUNCTION PART
Programming Notes
(1) Before setting various serial-interface parameters, make sure the transmit and receive operations are disabled
(TXENx = RXENx = "0").
(2) When the serial interface is transmitting or receiving data, do not set TXENx or RXENx to "0", and do not
execute the slp instruction.
(3) In clock-synchronized transfers, the mode of communication is half-duplex, in which the clock line is shared
between the transmit and receive units. Therefore, RXENx and TXENx cannot be enabled simultaneously.
(4) After an initial reset, the interrupt factor flag becomes indeterminate. To prevent generation of an unwanted
interrupt or IDMA request, reset this flag in the program.
(5) If a receive error occurs, the receive-error interrupt and receive-buffer full interrupt factors occur
simultaneously. However, since the receive-error interrupt has priority over the receive-buffer full interrupt,
the receive-error interrupt is processed first. Therefore, it is necessary to reset the receive-buffer full interrupt
factor flag through the use of the receive-error interrupt processing routine.
(6) To prevent the regeneration of interrupts due to the same factor following the occurrence of an interrupt,
always be sure to reset the interrupt factor flag before setting the PSR again or executing the reti instruction.
(7) Follow the procedure described below to initialize the serial interface.
Set IRMDx[1:0]
Set SMDx[1:0]
Other settings
Enable transmitting/receiving
"00"(normal I/F) or "10"(IrDA I/F)
Transfer mode setting
Data format and clock selection
Internal division ratio, IrDA I/O logic
and other settings
Enable transmitting, receiving or both
Figure 8.18 Serial Interface Initialize Procedure
(8) When transmitting data in the clock-synchronized master mode, transmit data is written to the transmit data
register after the initial setting is performed following the flow in item (7). However, the clock generated by
the 8-bit timer must be supplied to the serial interface (at least one underflow has had to have occurred in the
8-bit tier) before this writing. Otherwise, 0xFF will be transmitted prior to the written data.
(9) The maximum transfer rate of the serial interface is limited to 1 Mbps.
(10) If the receive circuit is stopped during reception, set both transmission and reception to the disabled status.
(11) When perform ing da ta transfer in the clock-synchronized mode, t he division ratio of the prescaler and the
reload data for the 8-bit programmable timer should be set so that the baud-rate is 1/4 of the system clock
frequency or lower.
(12) The serial interface operates only when the prescaler is operating.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
S1C33L03 FUNCTION PART EPSON B-III-9-1
A-1
B-III
I/O
III-9 INPUT/OUTPUT PORTS
The Peripheral Block has a total of 42 input/output ports. Although each pin is used for input/output from/to the
internal peripheral circuits, some pins can be used as general-purpose input/outp ut ports unless they are used for
the peripheral circuits.
Input Ports (K Ports)
Structure of Input Port
The Peripheral Block contains 13 bits of i nput ports (K50 to K 54, K 60 to K67) .
Figure 9.1 shows the structure of a typical input port.
Input interrupt
circuit
Kxx
KxxD
V
DDE
∗1
∗2
∗1 AV
DDE
for K50 and K60–K67
∗2 Available only for K50–K54
V
SS
Address
Internal data bus
Figur e 9.1 Structure of Input Port
Each input-port pin is connected directly to the internal data bus via a three-state buffer. The state of the input
signal when read at an input port is directly taken into the internal circuit as data.
When K50 is used as an input port and K60 to K67 are used as general-purpose input ports, the power supply for
the port input buffers is AVDDE.
There fore, wh en these por ts are used as high-level or low-level input ports, the high level must be AVDDE, and th e
low level VSS.
If there is a potential difference between AVDDE and VDDE, in particular, if the level from outside is VDDE, a
current may flow in the input buffer (when AVDDE > VDDE) or between VDDE and AVDDE (when AVDDE < VDDE).
There fore, if t hese ports are not used, when the input level is fixed externally, it should be fixed at VSS or AVDDE.
The K 50 po rt is provided with a pull-up resistance that pulls the port up to AVDDE.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
B-III-9-2 EPSON S1C33L03 FUNCTION PART
Input-Port Pins
The input pins concurrently serve as the input pins for peripheral circuits, as shown in Table 9.1. Whether they are
used a s input ports or for peripheral cir cuits can be set bit-for-bit usin g a func tio n se le ct re gi ste r. A ll p ins not u sed
for peripheral circuits can be used as general-purpose input ports that have an interrupt function.
Table 9.1 Input Pins
Pin name I/O Pull-up Function Function select bit
K50/#DMAREQ0 IAvailable Input port / High-speed DMA request 0 CFK50(D0)/K5 function select register(0x402C0)
K51/#DMAREQ1 IAvailable Input port / High-speed DMA request 1 CFK51(D1)/K5 function select register(0x402C0)
K52/#ADTRG IAvailable Input port / AD converter trigger CFK52(D2)/K5 function select register(0x402C0)
K53/#DMAREQ2 IAvailable Input port / High-speed DMA request 2 CFK53(D3)/K5 function select register(0x402C0)
K54/#DMAREQ3 IAvailable Input port / High-speed DMA request 3 CFK54(D4)/K5 function select register(0x402C0)
K60/AD0 I–Input port / AD converter input 0 CFK60(D0)/K6 function select register(0x402C3)
K61/AD1 I–Input port / AD converter input 1 CFK61(D1)/K6 function select register(0x402C3)
K62/AD2 I–Input port / AD converter input 2 CFK62(D2)/K6 function select register(0x402C3)
K63/AD3 I–Input port / AD converter input 3 CFK63(D3)/K6 function select register(0x402C3)
K64/AD4 I–Input port / AD converter input 4 CFK64(D4)/K6 function select register(0x402C3)
K65/AD5 I–Input port / AD converter input 5 CFK65(D5)/K6 function select register(0x402C3)
K66/AD6 I–Input port / AD converter input 6 CFK66(D6)/K6 function select register(0x402C3)
K67/AD7 I–Input port / AD converter input 7 CFK67(D7)/K6 function select register(0x402C3)
At c old start, all pins are set for input ports Kxx (function select register CFKxx = "0"). When these pins are used
for the internal peripheral circuits, write "1" to CFKxx. For details on pin functions in this case, refer to the
description of each peripheral circuit i n this ma nual .
At ho t start, the pins retain their state from prior to the reset.
When the ports set for A/D converter input are read, the value obtained is always "0".
Notes on Use
The inp ut buffers of the K50 a nd K60 t o K 67 po rts use AV DDE (power voltage for A/D converter) as their power
source. Furthermore, the K50 pull-up resistor is connected to AVDDE. Therefore, the following precautions must be
taken.
1) Wh en using K50 and K6 0–K67 as general-purpos e input po rts, the voltage input to the port mu st be high level
= AVDDE and low level = VSS.
2) When using VDDE as high level similar to other ports, VDDE must be the same voltage level as AVDDE. If the
input VDDE level is lower than the AVDDE level, current flows in the input buffer, or if the input VDDE level is
higher than the AVDDE level, current flows from the VDDE power supply to the AVDDE pow er s u ppl y.
3) To fix the input level externally when the port is not used, the input pin should be connected to VSS or AVDDE.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
S1C33L03 FUNCTION PART EPSON B-III-9-3
A-1
B-III
I/O
I/O Memory of Input Ports
Table 9.2 shows t he control bits of the input ports.
Table 9.2 Control Bits of Input Ports
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
CFK54
CFK53
CFK52
CFK51
CFK50
D7–5
D4
D3
D2
D1
D0
reserved
K54 function selection
K53 function selection
K52 function selection
K51 function selection
K50 function selection
– –
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
0 when being read.00402C0
(B) 1
#DMAREQ3
0 K54
1
#DMAREQ2
0 K53
1 #ADTRG 0 K52
1
#DMAREQ1
0 K51
1
#DMAREQ0
0 K50
K5 function
select register
–
K54D
K53D
K52D
K51D
K50D
D7–5
D4
D3
D2
D1
D0
reserved
K54 input port data
K53 input port data
K52 input port data
K51 input port data
K50 input port data
– –
–
–
–
–
–
–
R
R
R
R
R
0 when being read.00402C1
(B) 1 High 0 Low
K5 input port
data register
CFK67
CFK66
CFK65
CFK64
CFK63
CFK62
CFK61
CFK60
D7
D6
D5
D4
D3
D2
D1
D0
K67 function selection
K66 function selection
K65 function selection
K64 function selection
K63 function selection
K62 function selection
K61 function selection
K60 function selection
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00402C3
(B) 1 AD7 0 K67
1 AD6 0 K66
1 AD5 0 K65
1 AD4 0 K64
1 AD3 0 K63
1 AD2 0 K62
1 AD1 0 K61
1 AD0 0 K60
K6 function
select register
K67D
K66D
K65D
K64D
K63D
K62D
K61D
K60D
D7
D6
D5
D4
D3
D2
D1
D0
K67 input port data
K66 input port data
K65 input port data
K64 input port data
K63 input port data
K62 input port data
K61 input port data
K60 input port data
–
–
–
–
–
–
–
–
R
R
R
R
R
R
R
R
00402C4
(B) 1 High 0 LowK6 input port
data register
CFK54–CFK50: K5[4:0] function selection (D[4:0]) / K5 function select register (0x402C0)
CFK67–CFK60: K6[7:0] function selection (D[7:0]) / K6 function select register (0x402C3)
Selects the function of each input-port pin.
Write "1": U sed fo r peripheral circuit
Write "0": Input port pin
Read: Invalid
When a bit of the CFK register is set to "1", the corresponding pin is set for use with the peripheral circuit (see
Table 9.1). The pins for which register bits are set to " 0" can be used as gen eral-purpose input ports.
At c old start, CFK is set to "0" (input port). At hot start, CFK retains its state from prior to the initial reset.
K54D–K50D: K5[4:0] input port data (D[4:0]) / K5 input port data register (0x402C1)
K67D–K60D: K6[7:0] input port data (D[7:0]) / K6 input port data register (0x402C4)
The input data on each input port pin can be read from this register.
Read "1": High level
Read "0": Low level
Write: Invalid
The pin voltage of each input port can be read out "1" directly when the voltage is high (VDD) o r "0" when the
voltage is low (VSS) respec tiv ely.
Since this register is a read-only register, writing to the register is ignored.
When the ports set for A/D converter input are read, the value obtained is always "0".
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
B-III-9-4 EPSON S1C33L03 FUNCTION PART
I/O Ports (P Ports)
Structure of I/O Port
The Peripheral Bl ock contains 29 bi ts of I/O por ts (P00 to P07, P10 to P16, P20 to P27, P30 to P3 5) that can be
directed for input or output through the use of a program.
Figure 9.2 shows the structure of a typical I/O port.
V
DDE
V
SS
Internal data bus
Pxx
Data
register
Peripheral circuit
input
Peripheral circuit
output
I/O control
register
Peripheral circuit
I/O control Function
select register
I/O control
signal
Figur e 9.2 Structure of I/O Port
I/O Port Pins
The I/O ports concurrently serve as the input/output pins for peripheral circuits, as shown in Table 9.3. Whether
they are used as I/O ports or for peripheral circuits can be set bit-for-bit using a function select register. All pins not
used for pe ripheral circuits can be used as general-purp ose I/O ports.
Table 9.3 I/O Pins
Pin name I/O Pull-up Function Function select bit
P00/SIN0 I/O – I/O port / Serial IF Ch.0 data input CFP00(D0)/P0 function select register(0x402D0)
P01/SOUT0 I/O – I/O port / Serial IF Ch.0 data output CFP01(D1)/P0 function select register(0x402D0)
P02/#SCLK 0 I/O – I/O port / Serial IF Ch.0 clock input/output CFP02(D2)/P0 function select register(0x402D0)
P03/#SRDY0 I/O – I/O port / Serial IF Ch.0 ready input/output CFP03(D3)/P0 function select register(0x402D0)
P04/SIN1/
#DMAACK2 I/O – I/O port / Serial IF Ch.1 data input /
#DMAACK2 output (Ex) CFP04(D4)/P0 function select register(0x402D0)
CFEX4(D4)/Port function extension register(0x402DF)
P05/SOUT1/
#DMAEND2 I/O – I/O port / Serial IF Ch.1 data output /
#DMAEND2 output (Ex) CFP05(D5)/P0 function select register(0x402D0)
CFEX5(D5)/Port function extension register(0x402DF)
P06/#SCLK1/
#DMAACK3 I/O – I/O port / Serial IF Ch.1 clock input/output /
#DMAACK3 output (Ex) CFP06(D6)/P0 function select register(0x402D0)
CFEX6(D6)/Port function extension register(0x402DF)
P07/#SRDY1/
#DMAEND3 I/O – I/O port / Serial IF Ch.1 ready input/output /
#DMAEND3 output (Ex) CFP07(D7)/P0 function select register(0x402D0)
CFEX7(D7)/Port function extension register(0x402DF)
P10/EXCL0/
T8UF0/DST0 ∗I/O – I/O port / 16-bit timer 0 event counter input (I)
/ 8-bit timer 0 output (O) / DST0 output (Ex) CFP10(D0)/P1 function select register(0x402D4)
CFEX1(D1)/Port function extension register(0x402DF)
P11/EXCL1/
T8UF1/DST1 ∗I/O – I/O port / 16-bit timer 1 event counter input (I)
/ 8-bit timer 1 output (O) / DST1 output (Ex) CFP11(D1)/P1 function select register(0x402D4)
CFEX1(D1)/Port function extension register(0x402DF)
P12/EXCL2/
T8UF2/DST2 ∗I/O – I/O port / 16-bit timer 2 event counter input (I)
/ 8-bit timer 2 output (O) / DST2 output (Ex) CFP12(D2)/P1 function select register(0x402D4)
CFEX0(D0)/Port function extension register(0x402DF)
P13/EXCL3/
T8UF3/DPCO ∗I/O – I/O port / 16-bit timer 3 event counter input (I)
/ 8-bit timer 3 output (O) / DPCO output (Ex) CFP13(D3)/P1 function select register(0x402D4)
CFEX1(D1)/Port function extension register(0x402DF)
P14/FOSC1/
DCLK ∗I/O – I/O port / Low-speed (OSC1) clock output /
DCLK out put (Ex) CFP14(D4)/P1 function select register(0x402D4)
CFEX0(D0)/Port function extension register(0x402DF)
P15/EXCL4/
#DMAEND0/
#SCLK3
I/O – I/O port / 16-bit timer 4 event counter input (I)
/ #DMAEND0 output (O) / Serial IF Ch.3 clock
input/output
CFP15(D5)/P1 function select register(0x402D4)
P16/EXCL5/
#DMAEND1/
SOUT3
I/O – I/O port / 16-bit timer 5 event counter input (I)
/ #DMAEND1 output (O) / Serial IF Ch.3 data
output
CFP16(D6)/P1 function select register(0x402D4)
(I): Input mode, (O): Output mode, (Ex): Extend ed f u nct ion
∗: A 3-V system I/O voltage can only be used for the P10–P14 pins.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
S1C33L03 FUNCTION PART EPSON B-III-9-5
A-1
B-III
I/O
Pin name I/O Pull-up Function Function select bit
P20/#DRD I/O – I/O port / #DRD output CFP20(D0)/P2 function select register(0x402D8)
P21/#DWE/
#GAAS I/O – I/O port / #DWE output /
GA address strobe output (Ex) CFP21(D1)/P2 function select register(0x402D8)
CFEX2(D2)/Port function extension register(0x402DF)
P22/TM0 I/O – I/O port / 16-bit timer 0 output CFP22(D2)/P2 function select register(0x402D8)
P23/TM1 I/O – I/O port / 16-bit timer 1 output CFP23(D3)/P2 function select register(0x402D8)
P24/TM2/
#SRDY2 I/O – I/O port / 16-bit timer 2 output / Serial IF Ch.2
ready input/output CFP24(D4)/P2 function select register(0x402D8)
P25/TM3/
#SCLK2 I/O – I/O port / 16-bit timer 3 output / Serial IF Ch.2
clock input/output CFP25(D5)/P2 function select register(0x402D8)
P26/TM4/
SOUT2 I/O – I/O port / 16-bit timer 4 output / Serial IF Ch.2
data output CFP26(D6)/P2 function select register(0x402D8)
P27/TM5/SIN2 I/O – I/O port / 16-bit timer 5 output / Serial IF Ch.2
data input CFP27(D7)/P2 function select register(0x402D8)
P30/#WAIT/
#CE4&5 I/O – I/O port / #WAIT input (I) / #CE4&5 output (O) CFP30(D0)/P3 function select register(0x402DC)
P31/#BUSGET/
#GARD I/O – I/O port / #BUSGET output /
GA read signal output (Ex) CFP31(D1)/P3 function select register(0x402DC)
CFEX3(D3)/Port function extension register(0x402DF)
P32/#DMAACK0
/#SRDY3 I/O – I/O port / #DMAACK0 output / Serial IF Ch.3
ready input/output CFP32(D2)/ P3 function select register(0x402DC)
P33/#DMAACK1
/SIN3 I/O – I/O port / #DMAACK1 output / Serial IF Ch.3
data input CFP33(D3)/P3 function select register(0x402DC)
P34/#BUSREQ/
#CE6 I/O – I/O port / #BUSREQ input (I) / #CE6 output
(O) CFP34(D4)/P3 function select register(0x402DC)
P35/#BUSACK I/O – I/O port / #BUSACK output CFP35(D5)/P3 function select register(0x402DC)
(I): Input mode, (O): Output mode, (Ex): Extend ed f u nct ion
At c old start, all pins are set for I/O ports Pxx (function select register CFPxx = "0"). When these pins are used for
the internal peripheral circuits, write "1" to CFPxx. For details on pin functions in this case, refer to the description
of each peripheral circuit in this manual.
At ho t start, the pins retain their state from prior to the reset.
In addition to being an I/O port, the P10–P13, P15–P16, P30 and P34 pins are shared with two t ypes (three types
for P10–P13) of peripheral circuits . The typ e of peripheral circuit for which these pins are used is determined by
the direction (input or output) in which the pin is set using an I/O control register, as will be described later.
The P04– P07, P10– P14, P21 and P31 ports have extended functions indicated with (Ex) in the table. They can be
selected by writing "1" to CFEXx / Port function extension register (0x402DF).
The setting of CFEXx has priori ty over the CFPx x.
At c old start, CFEX1 and CFEX0 are set to "1", so the P10–P14 pins are set for debug signal outputs.
I/O Control Register and I/O Modes
The I/O ports are directed for input or output mode s by wr iting data to an I/O control register corresponding to
each port bit.
P07–P0 0 I/O control : IOC0[7:0] (D[7:0]) / P0 I/O control register (0x402D2)
P16–P1 0 I/O control : IOC1[6:0] (D[6:0]) / P1 I/O control register (0x402D6)
P27–P2 0 I/O control : IOC2[7:0] (D[7:0]) / P2 I/O control register (0x402DA)
P35–P3 0 I/O control : IOC3[5:0] (D[5:0]) / P3 I/O control register (0x402DE)
To set an I/O port for input, write "0" to the I/O control bit. I/O ports set for input mode are placed in the high-
impedance state, and thus function as input ports.
In the input mode, the state of the input pin is read directly, so the data is "1" when the pin state is high (VDD level)
or "0" when the pin state is low (VSS level).
Even in the input mode, data can be written to the data register without affecting the pin state.
To set a n I/O port for output, write "1" to the I/O control bit. I/O port set for output function as output ports. When
the port output data is "1", the port outputs a high level (VDD level); when the data is "0", the port outputs a low
level (VSS level).
At c old start, the I/O control register is set to "0" (input mode).
At ho t start, the pins retain their state from prior to the reset.
Note: If pins P10–P14, P15– P16, P30 and P34 are set for us e with periphe ral circuits , their pin functi ons
vary depending on the input/o utput direction co ntrol by the IOC1 x register .
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
B-III-9-6 EPSON S1C33L03 FUNCTION PART
I/O Memory of I/O Ports
Table 9.4 shows t he control bits of the I/O ports.
Table 9.4 Control Bits of I/O Ports
NameAddressRegister name Bit Function Setting Init. R/W Remarks
CFP07
CFP06
CFP05
CFP04
CFP03
CFP02
CFP01
CFP00
D7
D6
D5
D4
D3
D2
D1
D0
P07 function selection
P06 function selection
P05 function selection
P04 function selection
P03 function selection
P02 function selection
P01 function selection
P00 function selection
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Extended functions
(0x402DF)
00402D0
(B) 1 #SRDY1 0 P07
1 #SCLK1 0 P06
1 SOUT1 0 P05
1 SIN1 0 P04
1 #SRDY0 0 P03
1 #SCLK0 0 P02
1 SOUT0 0 P01
1 SIN0 0 P00
P0 function
select register
P07D
P06D
P05D
P04D
P03D
P02D
P01D
P00D
D7
D6
D5
D4
D3
D2
D1
D0
P07 I/O port data
P06 I/O port data
P05 I/O port data
P04 I/O port data
P03 I/O port data
P02 I/O port data
P01 I/O port data
P00 I/O port data
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00402D1
(B) 1 High 0 LowP0 I/O port data
register
IOC07
IOC06
IOC05
IOC04
IOC03
IOC02
IOC01
IOC00
D7
D6
D5
D4
D3
D2
D1
D0
P07 I/O control
P06 I/O control
P05 I/O control
P04 I/O control
P03 I/O control
P02 I/O control
P01 I/O control
P00 I/O control
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
This register
indicates the values
of the I/O control
signals of the ports
when it is read. (See
detailed explanation.)
00402D2
(B) 1 Output 0 InputP0 I/O control
register
–
CFP16
CFP15
CFP14
CFP13
CFP12
CFP11
CFP10
D7
D6
D5
D4
D3
D2
D1
D0
reserved
P16 function selection
P15 function selection
P14 function selection
P13 function selection
P12 function selection
P11 function selection
P10 function selection
–
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.
Extended functions
(0x402DF)
00402D4
(B) 1 EXCL5
#DMAEND1
0 P16
1 EXCL4
#DMAEND0
0 P15
1 EXCL3
T8UF3 0 P13
1 EXCL2
T8UF2 0 P12
1 EXCL1
T8UF1 0 P11
1 EXCL0
T8UF0 0 P10
–P1 function
select register
1 FOSC1 0 P14
–
P16D
P15D
P14D
P13D
P12D
P11D
P10D
D7
D6
D5
D4
D3
D2
D1
D0
reserved
P16 I/O port data
P15 I/O port data
P14 I/O port data
P13 I/O port data
P12 I/O port data
P11 I/O port data
P10 I/O port data
–
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.00402D5
(B) 1 High 0 Low
–
P1 I/O port data
register
–
IOC16
IOC15
IOC14
IOC13
IOC12
IOC11
IOC10
D7
D6
D5
D4
D3
D2
D1
D0
reserved
P16 I/O control
P15 I/O control
P14 I/O control
P13 I/O control
P12 I/O control
P11 I/O control
P10 I/O control
–
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.
This register
indicates the values
of the I/O control
signals of the ports
when it is read. (See
detailed explanation.)
00402D6
(B) 1Output 0Input
–P1 I/O control
register
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
S1C33L03 FUNCTION PART EPSON B-III-9-7
A-1
B-III
I/O
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
SSRDY3
SSCLK3
SSOUT3
SSIN3
D7–4
D3
D2
D1
D0
reserved
Serial I/F Ch.3 SRDY selection
Serial I/F Ch.3 SCLK selection
Serial I/F Ch.3 SOUT selection
Serial I/F Ch.3 SIN selection
– –
0
0
0
0
–
R/W
R/W
R/W
R/W
00402D7Port SIO
function
extension
register
1 #SRDY3 0
P32/
#DMAACK0
1 #SCLK3 0
P15/EXCL4/
#DMAEND0
1 SOUT3 0
P16/EXCL5/
#DMAEND1
1 SIN3 0
P33/
#DMAACK1
CFP27
CFP26
CFP25
CFP24
CFP23
CFP22
CFP21
CFP20
D7
D6
D5
D4
D3
D2
D1
D0
P27 function selection
P26 function selection
P25 function selection
P24 function selection
P23 function selection
P22 function selection
P21 function selection
P20 function selection
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W Ext. func.(0x402DF)
00402D8
(B) 1 TM5 0 P27
1 TM4 0 P26
1 TM3 0 P25
1 TM2 0 P24
1 TM1 0 P23
1 TM0 0 P22
1 #DWE 0 P21
1 #DRD 0 P20
P2 function
select register
P27D
P26D
P25D
P24D
P23D
P22D
P21D
P20D
D7
D6
D5
D4
D3
D2
D1
D0
P27 I/O port data
P26 I/O port data
P25 I/O port data
P24 I/O port data
P23 I/O port data
P22 I/O port data
P21 I/O port data
P20 I/O port data
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00402D9
(B) 1 High 0 LowP2 I/O port data
register
IOC27
IOC26
IOC25
IOC24
IOC23
IOC22
IOC21
IOC20
D7
D6
D5
D4
D3
D2
D1
D0
P27 I/O control
P26 I/O control
P25 I/O control
P24 I/O control
P23 I/O control
P22 I/O control
P21 I/O control
P20 I/O control
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
This register
indicates the values
of the I/O control
signals of the ports
when it is read. (See
detailed explanation.)
00402DA
(B) 1 Output 0 InputP2 I/O control
register
–
SSRDY2
SSCLK2
SSOUT2
SSIN2
D7–4
D3
D2
D1
D0
reserved
Serial I/F Ch.2 SRDY selection
Serial I/F Ch.2 SCLK selection
Serial I/F Ch.2 SOUT selection
Serial I/F Ch.2 SIN selection
–
0
0
0
0
–
R/W
R/W
R/W
R/W
00402DB 1 #SRDY2 0 P24/TM2
1 #SCLK2 0 P25/TM3
1 SOUT2 0 P26/TM4
1 SIN2 0 P27/TM5
Port SIO
function
extension
register
–
–
CFP35
CFP34
CFP33
CFP32
CFP31
CFP30
D7–6
D5
D4
D3
D2
D1
D0
reserved
P35 function selection
P34 function selection
P33 function selection
P32 function selection
P31 function selection
P30 function selection
–
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.
Ext. func.(0x402DF)
00402DC
(B) –P3 function
select register 1 #BUSACK 0 P35
1 #BUSREQ
#CE6 0 P34
1
#DMAACK0
0 P32
1 #BUSGET 0 P31
1 #WAIT
#CE4/#CE5 0 P30
1
#DMAACK1
0 P33
–
P35D
P34D
P33D
P32D
P31D
P30D
D7–6
D5
D4
D3
D2
D1
D0
reserved
P35 I/O port data
P34 I/O port data
P33 I/O port data
P32 I/O port data
P31 I/O port data
P30 I/O port data
–
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.00402DD
(B) 1 High 0 Low
–
P3 I/O port data
register
–
IOC35
IOC34
IOC33
IOC32
IOC31
IOC30
D7–6
D5
D4
D3
D2
D1
D0
reserved
P35 I/O control
P34 I/O control
P33 I/O control
P32 I/O control
P31 I/O control
P30 I/O control
–
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.
This register
indicates the values
of the I/O control
signals of the ports
when it is read. (See
detailed explanation.)
00402DE
(B) 1 Output 0 Input
–P3 I/O control
register
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
B-III-9-8 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
CFEX7
CFEX6
CFEX5
CFEX4
CFEX3
CFEX2
CFEX1
CFEX0
D7
D6
D5
D4
D3
D2
D1
D0
P07 port extended function
P06 port extended function
P05 port extended function
P04 port extended function
P31 port extended function
P21 port extended function
P10, P11, P13 port extended
function
P12, P14 port extended function
0
0
0
0
0
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00402DF
(B)
Port function
extension
register
1
#DMAEND3
0 P07, etc.
1
#DMAACK3
0 P06, etc.
1
#DMAEND2
0 P05, etc.
1
#DMAACK2
0 P04, etc.
1 #GARD 0 P31, etc.
1 #GAAS 0 P21, etc.
1 DST0
DST1
DPC0
0 P10, etc.
P11, etc.
P13, etc.
1 DST2
DCLK 0 P12, etc.
P14, etc.
CFP07–CFP00: P0[7:0] function selection (D[7:0]) / P0 function select register (0x402D0)
CFP16–CFP10: P1[6:0] function selection (D[6:0]) / P1 function select register (0x402D4)
CFP27–CFP20: P2[7:0] function selection (D[7:0]) / P2 function select register (0x402D8)
CFP35–CFP30: P3[5:0] function selection (D[5:0]) / P3 function select register (0x402DC)
Selects the function of each I/O port pin.
Write "1": U sed fo r peripheral circuit
Write "0": I/ O port pin
Read: Valid
When a bit of the CFP register is set to "1", the corresponding pin is set for use with peripheral circuits (see Table
9.3). The pins for which register bi ts are set to " 0" can be used as ge neral-purpose I/O ports.
At c old start, CFP is set to "0" (I/O port). At hot start, CFP retains its state from prior to the initial reset.
P07D–P00D: P 0[ 7:0 ] I/ O port data (D[7:0 ]) / P 0 I/ O port data regist er (0x40 2D 1)
P16D–P10D: P 1[ 6:0 ] I/ O port data (D[6:0 ]) / P 1 I/ O port data regist er (0x40 2D 5 )
P27D–P20D: P 2[ 7:0 ] I/ O port data (D[7:0 ]) / P 2 I/ O port data regist er (0x40 2D 9 )
P35D–P30D: P 3[ 5:0 ] I/ O port data (D[5:0 ]) / P 3 I/ O port data regist er (0x40 2D D )
This regist er reads data from I/O-port pins or sets output data.
When writing data
Write "1": H igh level
Write "0": Low level
When an I/O port is set for output, the data written to it is directly output to the I/O port pin. If the data written to
the port is "1", the port pin is set high (VDD and VDDE level); if the data is "0", the port pin is set low (VSS level).
Even in the input mode, data can be written to the port data register.
When re ad in g d ata
Read "1": High level
Read "0": Low level
The voltage level on the port pin is read out regardless of whether an I/O port is set for input or output mode. If the
pin voltage is high (VDD and VDDE level), "1" is read out as input data; if the pin voltage is low (VSS level), "0" is
read out as input data.
At c old start, all data bits are set to "0". At hot start, they retain their state from prior to the initial reset.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
S1C33L03 FUNCTION PART EPSON B-III-9-9
A-1
B-III
I/O
IOC07–IOC00: P0[7:0 ] p ort I/O con tro l (D[7:0 ]) / P 0 p ort I/O con tro l register (0 x40 2D 2 )
IOC16–IOC10: P1[6:0 ] p ort I/O con tro l (D[6:0 ]) / P1 port I/O c ontro l regi st er (0 x40 2D 6 )
IOC27–IOC20: P2[7:0 ] p ort I/O con tro l (D[7:0 ]) / P 2 p ort I/O con tro l register (0 x40 2D A )
IOC35–IOC30: P3[5:0 ] p ort I/O con tro l (D[5:0 ]) / P 3 p ort I/O con tro l register (0 x40 2D E )
Directs an I/O port for input or output and indicates the I/O control signal value of the port.
When writing data
Write "1": O utput mode
Write "0": Input mode
This I/O control register corresponds bit-for-bit to each I/O port. When an IOC bit is set to "1", the corresponding
I/O port is directed for output; if it is set to "0", the I/O port is directed for input.
At c old start, all IOC bits are set to "0" (input). At hot start, IOC retains its state from prior to the initial reset.
If pins P10–P13, P15–P16, P30 and P34 a re set for use with peripheral circuits , their pi n functions vary depending
on the input/output direction control by the IOC1x register.
When re ad in g d ata
Read "1": I/O control signal (output)
Read "0": I/O control signal (input)
The I/O control signal value for the port pin is read from this register. When I/O port function is selected using the
CFEX and CFP r egisters, the value wr itten to the IOC register is read out as is. When peripheral function is
selected, the read value depends on the peripheral circuit status and may not indicate the value written to the IOC
register.
However, the read va lues of the IOC bits for P10–P13, P15–P16, P30, and P34 are the same as the written value
even if the peripheral function is selected.
SSIN3: Serial I/F Ch.3 SIN selection (D0) / Port SIO function extension register (0x402D7)
Switches the function of pin P33/#DMAACK1/SIN3.
Write "1": SIN3
Write "0": P33/#DMAACK1
Read: Valid
To use the pin as SIN3, set SSIN3 (D0 / 0x402D 7) to " 1" and CFP33 (D 3 / 0x402DC) to "0" .
To use the pin as P33 or #DMAAC K 1, set thi s bit to " 0".
At po wer-on, this bit is set to "0".
SSOUT3: Serial I/F Ch.3 SOUT selection (D1) / Port SIO function extension register (0x402D7)
Switches the function of pin P16/EXCL5/#DMAEND1/SOUT3.
Write "1": SOUT 3
Write "0": P16/EXCL5/#DMAEND1
Read: Valid
To use the pin as SOUT3, set SSOUT3 (D1 / 0x402D7) t o "1" a nd CFP1 6 (D6 / 0x402D4) t o "0".
To use the pin as P16, EXCL5, or #DMAEND1, set this bit to "0".
At po wer-on, this bit is set to "0".
SSCLK3: Seria l I /F Ch.3 SCLK selection (D2) / Port SIO functi on extension register (0x402D7)
Sw itches the function of pi n P15/EXCL4 /#DMAEND 0/#SCLK3.
Write "1": # SCLK3
Write "0": P15 /EXCL4/#DMAEND0
Read: Valid
To use the pin as #SCLK 3, set SSCLK3 (D2 / 0x402D 7) to " 1" and CFP15 (D5 / 0x402D4) to "0".
To use the pin as P15, EXCL4, or #DMAEND0, set this bit to "0".
At po wer-on, this bit is set to "0".
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
B-III-9-10 EPSON S1C33L03 FUNCTION PART
SSRDY3: Serial I/F Ch.3 SRDY selection (D3) / Port SIO function extension register (0x402D7)
Switches the function of pin P32/#DMAACK0/#SRDY3.
Write "1": # SRDY3
Write "0": P32/#DMAACK0
Read: Valid
To use the pin as #SRDY 3, set SSRDY3 (D3 / 0x402D 7) to " 1" and CFP32 (D2 / 0x402DC) to "0" .
To use the pin as P32 or #DMAAC K0, set this bit to "0".
At po wer-on, this bit is set to "0".
SSIN2: Serial I/F Ch.2 SIN selection (D0) / Port SIO function extension register (0x402DB)
Sw itches the function of pi n P27/TM5/ SIN2 .
Write "1": SIN2
Write "0": P27 /TM5
Read: Valid
To use the pin as SIN2, set SSIN2 (D0 / 0x402D B) to "1" and CFP27 (D 7 / 0x402D 8) to "0".
To use the pin as P27 or TM5, set this bit to "0".
At po wer-on, this bit is set to "0".
SSOUT2: Serial I/F Ch.2 SOUT selection (D1) / Port SIO function extension register (0x402DB)
Sw itches the function of pi n P26/TM4/ SO UT2.
Write "1": SOUT 2
Write "0": P26 /TM4
Read: Valid
To use the pin as SOUT2 , set SSOUT 2 (D1 / 0x402D B) to "1" and CFP26 (D 6 / 0x402D8) t o "0".
To use the pin as P26 or TM4, set this bit to "0".
At po wer-on, this bit is set to "0".
SSCLK2: Serial I/F Ch.2 SCLK selection (D2) / Port SIO function extension register (0x402DB)
Sw itches the function of pi n P25/TM3/ #SCLK2.
Write "1": # SCLK2
Write "0": P25 /TM3
Read: Valid
To use the pin as #SCLK2, set SSCLK2 (D2 / 0x402DB) to " 1" and CFP25 (D5 / 0x402D 8) to "0".
To use the pin as P25 or TM3, set this bit to "0".
At po wer-on, this bit is set to "0".
SSRDY2: Serial I/F Ch.2 SRDY selection (D3) / Port SIO function extension register (0x402DB)
Sw itches the function of pi n P24/TM2/ #SRDY2.
Write "1": # SRDY2
Write "0": P24 /TM2
Read: Valid
To use the pin as #SRDY 2, set SSRDY2 (D3 / 0x402D B) to " 1" and CFP24 (D4 / 0x402D8) to "0".
To use the pin as P24 or TM2, set this bit to "0".
At po wer-on, this bit is set to "0".
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
S1C33L03 FUNCTION PART EPSON B-III-9-11
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I/O
CFEX0: P12, P14 function extension (D0) / Port fun ction extens ion registe r (0x402DF)
CFEX1: P10, P11, P13 function ex tension (D1) / Port function ex tension register (0x402DF)
CFEX2: P21 func tio n extension (D2) / Port function ex tension register (0x402DF)
CFEX3: P31 function extension (D3) / Port function extension register (0x402DF)
CFEX4: P04 func tio n extension (D4) / Port function ex tension register (0x402DF)
CFEX5: P05 func tio n extension (D5) / Port function ex tension register (0x402DF)
CFEX6: P06 func tio n extension (D6) / Port function extens ion regist er (0x402DF)
CFEX7: P07 func tio n extension (D7) / Port function ex tension register (0x402DF)
Sets whether the function of an I/O-port pin is to be extended.
Write "1": Fun ction-extended pin
Write "0": I/O- port/peripheral-circuit pin
Read: Valid
When CFEXx is set to "1", the corresponding pin is set to the extended function input/output pin. When CFEXx =
"0", the corresponding CFP bit becomes effective.
At c old start, CFEX0 and CFEX1 are set to "1" (function-extended pin) and other bits are set to "0" (I/O-
port/peripheral- circuit pi n). At hot start, CF EX retains its state from prior to the initial reset.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
B-III-9-12 EPSON S1C33L03 FUNCTION PART
Input Interrupt
The input ports and the I/O ports support eight system of port input interrupts and two systems of key input
interrupts.
Port Input Interrupt
The por t input interrupt circuit has eight interrupt systems (FPT7–FPT0) and a port can be selected for generating
each interrupt factor.
The interrupt condition can also be selected from betwee n in pu t sign al edge and input signal level.
Figure 9.3 shows the configuration of the port input interrupt circuit.
FPT0
FPT1
FPT2
Internal data bus
FPT3
FPT4
FPT5
K67
P33
P07
P27
Input polarity
selection SPPT7
Edge/level
selection SEPT7
Address
Address
FPT6
FPT7
FPT7
FPT6
FPT5
FPT4
FPT3
FPT2
FPT1
FPT0
Input port selection
SPT7
Interrupt
request
Interrupt signal
generation
Figur e 9.3 Configuration of Port Input Interrupt Circuit
Selecting input pins
The interrupt factors allows selection of an input pin from the four predefined pins independently.
Table 9.5 shows t he control bits and the selectable pins for each factor.
Table 9.5 Selecting Pins for Port Input Interrupts
Interrupt SPT settings
factor Control bit 11 10 01 00
FPT7 SPT7[1:0] (D[7:6])/Port input interrupt select register 2 (0x402C7) P27 P07 P33 K67
FPT6 SPT6[1:0] (D[5:4])/Port input interrupt select register 2 (0x402C7) P26 P06 P32 K66
FPT5 SPT5[1:0] (D[3:2])/Port input interrupt select register 2 (0x402C7) P25 P05 P31 K65
FPT4 SPT4[1:0] (D[1:0])/Port input interrupt select register 2 (0x402C7) P24 P04 K54 K64
FPT3 SPT3[1:0] (D[7:6])/Port input interrupt select register 1 (0x402C6) P23 P03 K53 K63
FPT2 SPT2[1:0] (D[5:4])/Port input interrupt select register 1 (0x402C6) P22 P02 K52 K62
FPT1 SPT1[1:0] (D[3:2])/Port input interrupt select register 1 (0x402C6) P21 P01 K51 K61
FPT0 SPT0[1:0] (D[1:0])/Port input interrupt select register 1 (0x402C6) P20 P00 K50 K60
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
S1C33L03 FUNCTION PART EPSON B-III-9-13
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B-III
I/O
Conditions for port input-interrupt generation
Each port input interrupt can be generated by the edge or level of the input signal. The SEPTx bit of the
edge/level select register (0x402C9) is used for this selection. When SEPTx is set to "1", the FPTx interrupt
will be generated at the signal edge. When SEPTx is set to "0", the FPTx interrupt will be generated by the
input signal level.
Furthermore, the signal polarity can be selected using the SPPTx bit of the input porarity select register
(0x402C8).
With these registers, the port input interrupt condition is decided as shown in Table 9.6.
Table 9.6 Port Input Interrupt Condition
SEPTx SPPTx FPTx interrupt condition
11Rising edge
10Falling edge
01High level
00Low level
When the input signal goes to the selected status, the interrupt factor flag FP is set to "1" and, if other
interrupt conditions set by the interrupt controller are met, an interrupt is generated.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
B-III-9-14 EPSON S1C33L03 FUNCTION PART
Key Input Interrupt
The key input inte rru pt ci rcu i t has tw o int e rru pt system s (F PK 1 and F PK 0) and a port grou p can be selected for
generating each inte rru pt fa cto r.
The interrupt condition can also be set by software.
Figure 9.4 shows the configuration of the port input interrupt circuit.
Internal data bus
K54, K64, P04, P24
K53, K63, P03, P23
K52, K62, P02, P22
K50
K60
P00
P20
Input comparison
register SCPK0
Input mask
register SMPK0
Address
Address
K51, K61, P01, P21
K50, K60, P00, P20
Input port selection
SPPK0
FPK0
Interrupt
request
Interrupt signal
generation
FPK0 system
K63, K67, P07, P27
K62, K66, P06, P26
K60
K64
P04
P24
Input comparison
register SCPK1
Input mask
register SMPK1
Address
Address
K61, K65, P05, P25
K60, K64, P04, P24
Input port selection
SPPK1
FPK1
Interrupt
request
Interrupt signal
generation
FPK1 system
Figur e 9.4 Configuration of Key Input Interrupt Circuit
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
S1C33L03 FUNCTION PART EPSON B-III-9-15
A-1
B-III
I/O
Selecting input pins
For the FPK1 inte rru pt sy stem , a four -b it inpu t pin group can be selected from the four predefined groups.
For the FPK0 system, a fi ve -bi t inpu t pin group can be select e d.
Table 9.7 shows t he control bits and the selectable groups for each factor.
Table 9.7 Selecting Pins for Key Input Interrupts
Interrupt SPPK settings
factor Control bit 11 10 01 00
FPK1 SPPK1[1:0] (D[3:2])/Key input interrupt select register (0x402CA) P2[7:4] P0[7:4] K6[7:4] K6[3:0]
FPK0 SPPK0[1:0] (D[1:0])/Key input interrupt select register (0x402CA) P2[4:0] P0[4:0] K6[4:0] K5[4:0]
Conditions for key input-interrupt generation
The key input interrupt circuit has two input mask registers (SMPK0[4:0] for FPK0 and SMPK1[3:0] for
FPK1) and two input comparison registers (SCPK0[4:0] for FPK0 and SCPK0[3:0] for FPK1) to set input-
inte rru pt co nd ition s.
The input mask register SMPK is used to mask the input pin that is not used for an interrupt. This register
masks each input pin, whereas the interrupt enable register of the interrupt controller masks the interrupt
factor for each interrupt group.
The input comparison register SCPK is used to select whether an interrupt for each input port is to be
generated at the ris ing or falling edge of the input.
A change in state occurs so that the input pin enabled for interrupt by the interrupt mask register SMPK and
the content of the input comparison register SCPK become unmatched after being matched, the interrupt
factor flag FK is set to "1" and, if other interrupt conditions are met, an interrupt is generated.
Figure 9.5 shows cases in which a FPK0 interrupt is generated. Here, it is assumed that the K5[4:0] pins are
selected for the input-pin group and the control register of the interrupt controller is set so as to enable
generation of a FPK0 in te rru pt.
Intput mask register SMPK0
Input comparison register SCPK0
SMPK04
1SMPK03
1SMPK02
1SMPK01
1SMPK00
0
Input port K5
(1) (Initial value)
Interrupt generation
K54
1
SCPK04
1SCPK03
1SCPK02
0SCPK01
1SCPK00
0
With the settings shown above, FPK0 interrupt is generated under the condition shown below.
(2)
K54
1
(3)
K54
1
(4)
K54
1
K53
1K52
0K51
1K50
0
K53
1K52
0K51
1K50
1
K53
0K52
0K51
1K50
0
K53
0K52
1K51
1K50
0
Because interrupt has been disabled for
K50, interrupt will be generated when non-
conformity occurs between the contents of
the four bits K51–K54 and the four bits
input comparison register SCPK0[4:1].
Figure 9.5 FPK0 Interrupt Generation Example (when K5[4:0] is selected by SPPK[1:0])
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
B-III-9-16 EPSON S1C33L03 FUNCTION PART
Since K50 is masked from interrupt by SMPK00, no interrupt occurs at that point (2) above.
Next, because K53 becomes "0" at (3), an interrupt is generated due to the lack of a match between the data
of the input pin K5[4:1] that is enabled for interrupt and that of the input comparison register SCPK0[4:1].
Since only a change in states in which the input data and the content of the input comparison register SCPK
become unm atched after being matched cons titut es an interrupt generation condition as described above, no
interrupt is generated when a change in states from one unmatched state to another, as in (4), occurs.
Conseq uently, i f another interrupt is to be generated again following the occurrence of an interrupt, the state
of the input pin must be temporarily restored to the same content as that of the input comparison register
SC PK, or t he input comparison register SCPK must be set again. Note that the input pins masked from
interrupt by the SMPK register do not affect interrupt generation conditions.
An interrupt is generated for FPK1 in the same way as described above .
Control Registers of the Interrupt Controller
Table 9.8 shows t he control registers of the interrupt controller that are provided for each input-interrupt
system.
Table 9.8 Control Registers of Interrupt Controller
System Interrupt factor flag Interrupt enable register Interrupt priority register
FPT7 FP7(D5/0x40287) EP7(D5/0x40277) PP7L[2:0](D[6:4]/0x4026D)
FPT6 FP6(D4/0x40287) EP6(D4/0x40277) PP6L[2:0](D[2:0]/0x4026D)
FPT5 FP5(D3/0x40287) EP5(D3/0x40277) PP5L[2:0](D[6:4]/0x4026C)
FPT4 FP4(D2/0x40287) EP4(D2/0x40277) PP4L[2:0](D[2:0]/0x4026C)
FPT3 FP3(D3/0x40280) EP3(D3/0x40270) PP3L[2:0](D[6:4]/0x40261)
FPT2 FP2(D2/0x40280) EP2(D2/0x40270) PP2L[2:0](D[2:0]/0x40261)
FPT1 FP1(D1/0x40280) EP1(D1/0x40270) PP1L[2:0](D[6:4]/0x40260)
FPT0 FP0(D0/0x40280) EP0(D0/0x40270) PP0L[2:0](D[2:0]/0x40260)
FPK1 FK1(D5/0x40280) EK1(D5/0x40270) PK1L[2:0](D[6:4]/0x40262)
FPK0 FK0(D4/0x40280) EK0(D4/0x40270) PK0L[2:0](D[2:0]/0x40262)
When the interrupt generation condition described above is met, the corresponding interrupt factor flag is set
to "1". If the interrupt enable register bit for that interrupt factor has been set to "1", an interrupt request is
generated.
Interrupts due to an interrupt factor can be disabled by leaving the interrupt enable register bit for that factor
set to "0". The interrupt factor flag is set to "1" whenever interrupt generation conditions are met, regardless
of the setting of the interrupt enable register.
The interrupt priority register sets the interrupt priority level (0 to 7) for each interrupt system. An interrupt
request to the CPU is accepted only when no other interrupt request of a higher priority has been generated.
In addition, only when the PSR's IE bit = "1" (interrupts enabled) and the set value of the IL is smaller than
the input interrupt level set using the interrupt priority register will the input interrupt request actually be
accepted by the CPU.
For details on these interrupt control registers, as well as the device operation when an interrupt has occurred,
refer to "ITC (Interrupt Controller)".
Int e ll ig e nt D M A
The port input interrupt system can invoke an intelligent DMA (IDMA) through the use of its interrupt factor.
This enables the port inputs to be used as a trigger to perform DMA transfer.
The following shows the IDMA channel numbers assigned to each interrupt factor:
IDMA Ch. IDMA Ch.
FPT0 input interrupt: 1 FPT4 input interrupt: 28
FPT1 input interrupt: 2 FPT5 input interrupt: 29
FPT2 input interrupt: 3 FPT6 input interrupt: 30
FPT3 input interrupt: 4 FPT7 input interrupt: 31
For IDMA to be invoked, the IDMA request and IDMA enable bits shown in Table 9.9 must be set to "1" in
advance. Transfer conditions, etc. must also be set on the IDMA side in advance.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
S1C33L03 FUNCTION PART EPSON B-III-9-17
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I/O
Table 9.9 Control Bits fo r IDMA Transfe r
System IDMA request bit IDMA enable bit
FPT7 RP7(D7/0x40293) DEP7(D7/0x40297)
FPT6 RP6(D6/0x40293) DEP6(D6/0x40297)
FPT5 RP5(D5/0x40293) DEP5(D5/0x40297)
FPT4 RP4(D4/0x40293) DEP4(D4/0x40297)
FPT3 RP3(D3/0x40290) DEP3(D3/0x40294)
FPT2 RP2(D2/0x40290) DEP2(D2/0x40294)
FPT1 RP1(D1/0x40290) DEP1(D1/0x40294)
FPT0 RP0(D0/0x40290) DEP0(D0/0x40294)
If the IDMA request and enable bits are set to "1", IDMA is invoked through generation of an interrupt factor.
No interrupt request is generated at that point. An interrupt request is generated after the DMA transfer is
completed. The registers can also be set so as not to generate an interrupt, with only DMA transfers
performed.
For details on IDMA transfers and interrupt control upon completion of IDMA transfer, refer to "IDMA
(Intelligent DMA)".
Trap vectors
Th e trap-v ecto r address of each input default interrupt factor is set as follows:
FPT0 input interrupt:0x0C00040
FPT1 input interrupt:0x0C00044
FPT2 input interrupt:0x0C00048
FPT3 input interrupt:0x0C0004C
FPK0 input interrupt:0x0C00050
FPK1 input interrupt:0x0C00054
FPT4 input interrupt:0x0C00110
FPT5 input interrupt:0x0C00114
FPT6 input interrupt:0x0C00118
FPT7 input interrupt:0x0C0011C
The bas e address of the trap table can be changed using the TTBR register (0x48134 to 0x48137).
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
B-III-9-18 EPSON S1C33L03 FUNCTION PART
I/O Memory for In put Inter rupt s
Table 9.10 shows t he control bits for the port input and key input interrupts.
Table 9.10 Control Bits for Input Interrupts
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
0 to 7
0 to 7
–
–
PP1L2
PP1L1
PP1L0
–
PP0L2
PP0L1
PP0L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Port input 1 interrupt level
reserved
Port input 0 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040260
(B)
Port input 0/1
interrupt
priority register
–
0 to 7
0 to 7
–
–
PP3L2
PP3L1
PP3L0
–
PP2L2
PP2L1
PP2L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Port input 3 interrupt level
reserved
Port input 2 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040261
(B)
Port input 2/3
interrupt
priority register
–
0 to 7
0 to 7
–
–
PK1L2
PK1L1
PK1L0
–
PK0L2
PK0L1
PK0L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Key input 1 interrupt level
reserved
Key input 0 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040262
(B)
Key input
interrupt
priority register
–
0 to 7
0 to 7
–
–
PP5L2
PP5L1
PP5L0
–
PP4L2
PP4L1
PP4L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Port input 5 interrupt level
reserved
Port input 4 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
004026C
(B)
Port input 4/5
interrupt
priority register
–
0 to 7
0 to 7
–
–
PP7L2
PP7L1
PP7L0
–
PP6L2
PP6L1
PP6L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Port input 7 interrupt level
reserved
Port input 6 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
004026D
(B)
Port input 6/7
interrupt
priority register
–
EK1
EK0
EP3
EP2
EP1
EP0
D7–6
D5
D4
D3
D2
D1
D0
reserved
Key input 1
Key input 0
Port input 3
Port input 2
Port input 1
Port input 0
– –
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.0040270
(B) 1 Enabled 0 Disabled
Key input,
port input 0–3
interrupt
enable register
–
EP7
EP6
EP5
EP4
ECTM
EADE
D7–6
D5
D4
D3
D2
D1
D0
reserved
Port input 7
Port input 6
Port input 5
Port input 4
Clock timer
A/D converter
– –
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.0040277
(B) 1 Enabled 0 Disabled
Port input 4–7,
clock timer,
A/D interrupt
enable register
–
FK1
FK0
FP3
FP2
FP1
FP0
D7–6
D5
D4
D3
D2
D1
D0
reserved
Key input 1
Key input 0
Port input 3
Port input 2
Port input 1
Port input 0
– –
X
X
X
X
X
X
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.0040280
(B) 1 Factor is
generated 0 No factor is
generated
Key input,
port input 0–3
interrupt factor
flag register
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
S1C33L03 FUNCTION PART EPSON B-III-9-19
A-1
B-III
I/O
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
FP7
FP6
FP5
FP4
FCTM
FADE
D7–6
D5
D4
D3
D2
D1
D0
reserved
Port input 7
Port input 6
Port input 5
Port input 4
Clock timer
A/D converter
– –
X
X
X
X
X
X
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.0040287
(B) 1 Factor is
generated 0 No factor is
generated
Port input 4–7,
clock timer, A/D
interrupt factor
flag register
R16TC0
R16TU0
RHDM1
RHDM0
RP3
RP2
RP1
RP0
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 0 comparison A
16-bit timer 0 comparison B
High-speed DMA Ch.1
High-speed DMA Ch.0
Port input 3
Port input 2
Port input 1
Port input 0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0040290
(B) 1 IDMA
request 0 Interrupt
request
Port input 0–3,
high-speed
DMA Ch. 0/1,
16-bit timer 0
IDMA request
register
RP7
RP6
RP5
RP4
–
RADE
RSTX1
RSRX1
D7
D6
D5
D4
D3
D2
D1
D0
Port input 7
Port input 6
Port input 5
Port input 4
reserved
A/D converter
SIF Ch.1 transmit buffer empty
SIF Ch.1 receive buffer full
0
0
0
0
–
0
0
0
R/W
R/W
R/W
R/W
–
R/W
R/W
R/W
0 when being read.
0040293
(B) 1 IDMA
request 0 Interrupt
request
1 IDMA
request 0 Interrupt
request
–
Serial I/F Ch.1,
A/D,
port input 4–7
IDMA request
register
DE16TC0
DE16TU0
DEHDM1
DEHDM0
DEP3
DEP2
DEP1
DEP0
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 0 comparison A
16-bit timer 0 comparison B
High-speed DMA Ch.1
High-speed DMA Ch.0
Port input 3
Port input 2
Port input 1
Port input 0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0040294
(B) 1 IDMA
enabled 0 IDMA
disabled
Port input 0–3,
high-speed
DMA Ch. 0/1,
16-bit timer 0
IDMA enable
register
DEP7
DEP6
DEP5
DEP4
–
DEADE
DESTX1
DESRX1
D7
D6
D5
D4
D3
D2
D1
D0
Port input 7
Port input 6
Port input 5
Port input 4
reserved
A/D converter
SIF Ch.1 transmit buffer empty
SIF Ch.1 receive buffer full
0
0
0
0
–
0
0
0
R/W
R/W
R/W
R/W
–
R/W
R/W
R/W
0 when being read.
0040297
(B) 1 IDMA
enabled 0 IDMA
disabled
1 IDMA
enabled 0 IDMA
disabled
–
Serial I/F Ch.1,
A/D,
port input 4–7
IDMA enable
register
SPT31
SPT30
SPT21
SPT20
SPT11
SPT10
SPT01
SPT00
D7
D6
D5
D4
D3
D2
D1
D0
FPT3 interrupt input port selection
FPT2 interrupt input port selection
FPT1 interrupt input port selection
FPT0 interrupt input port selection
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
00402C6
(B)
Port input
interrupt select
register 1
11 10 01 00
P23 P03 K53 K63
11 10 01 00
P22 P02 K52 K62
11 10 01 00
P21 P01 K51 K61
11 10 01 00
P20 P00 K50 K60
11 10 01 00
P27 P07 P33 K67
11 10 01 00
P26 P06 P32 K66
11 10 01 00
P25 P05 P31 K65
11 10 01 00
P24 P04 K54 K64
SPT71
SPT70
SPT61
SPT60
SPT51
SPT50
SPT41
SPT40
D7
D6
D5
D4
D3
D2
D1
D0
FPT7 interrupt input port selection
FPT6 interrupt input port selection
FPT5 interrupt input port selection
FPT4 interrupt input port selection
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
00402C7
(B)
Port input
interrupt select
register 2
1 High level
or
Rising edge
0 Low level
or
Falling
edge
SPPT7
SPPT6
SPPT5
SPPT4
SPPT3
SPPT2
SPPT1
SPPT0
D7
D6
D5
D4
D3
D2
D1
D0
FPT7 input polarity selection
FPT6 input polarity selection
FPT5 input polarity selection
FPT4 input polarity selection
FPT3 input polarity selection
FPT2 input polarity selection
FPT1 input polarity selection
FPT0 input polarity selection
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00402C8
(B)
Port input
interrupt
input polarity
select register
1 Edge 0 LevelSEPT7
SEPT6
SEPT5
SEPT4
SEPT3
SEPT2
SEPT1
SEPT0
D7
D6
D5
D4
D3
D2
D1
D0
FPT7 edge/level selection
FPT6 edge/level selection
FPT5 edge/level selection
FPT4 edge/level selection
FPT3 edge/level selection
FPT2 edge/level selection
FPT1 edge/level selection
FPT0 edge/level selection
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00402C9
(B)
Port input
interrupt
edge/level
select register
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
B-III-9-20 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
SPPK11
SPPK10
SPPK01
SPPK00
D7–4
D3
D2
D1
D0
reserved
FPK1 i
nterrupt input port selection
FPK0 i
nterrupt input port selection
–
0
0
0
0
–
R/W
R/W
0 when being read.00402CA
(B)
Key input
interrupt select
register
–
11 10 01 00
P2[7:4] P0[7:4] K6[7:4] K6[3:0]
11 10 01 00
P2[4:0] P0[4:0] K6[4:0] K5[4:0]
–
SCPK04
SCPK03
SCPK02
SCPK01
SCPK00
D7–5
D4
D3
D2
D1
D0
reserved
FPK04 input comparison
FPK03 input comparison
FPK02 input comparison
FPK01 input comparison
FPK00 input comparison
– –
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
0 when being read.00402CC
(B) 1 High 0 Low
Key input
interrupt
(FPK0) input
comparison
register
–
SCPK13
SCPK12
SCPK11
SCPK10
D7–4
D3
D2
D1
D0
reserved
FPK13 input comparison
FPK12 input comparison
FPK11 input comparison
FPK10 input comparison
– –
0
0
0
0
–
R/W
R/W
R/W
R/W
0 when being read.00402CD
(B) 1 High 0 Low
Key input
interrupt
(FPK1) input
comparison
register
–
SMPK04
SMPK03
SMPK02
SMPK01
SMPK00
D7–5
D4
D3
D2
D1
D0
reserved
FPK04 input mask
FPK03 input mask
FPK02 input mask
FPK01 input mask
FPK00 input mask
– –
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
0 when being read.00402CE
(B) 1 Interrupt
enabled 0 Interrupt
disabled
Key input
interrupt
(FPK0) input
mask register
–
SMPK13
SMPK12
SMPK11
SMPK10
D7–4
D3
D2
D1
D0
reserved
FPK13 input mask
FPK12 input mask
FPK11 input mask
FPK10 input mask
– –
0
0
0
0
–
R/W
R/W
R/W
R/W
0 when being read.00402CF
(B) 1 Interrupt
enabled 0 Interrupt
disabled
Key input
interrupt
(FPK1) input
mask register
SPT71–SPT70: FPT7 interrupt input po rt se l ection (D[7:6]) / Port input interrupt select register 2 (0x402C7)
SPT61–SPT60: FPT6 interrupt input por t sel ection (D[5:4]) / Port input interrupt select register 2 (0x402C7)
SPT51–SPT50: FPT5 interrupt input po rt se l ection (D[3:2]) / Port input interrupt select register 2 (0x402C7)
SPT41–SPT40: FPT4 interrupt input po rt se l ection (D[1:0]) / Port input interrupt select register 2 (0x402C7)
SPT31–SPT30: FPT3 interrupt input po rt se l ection (D[7:6]) / Port input interrupt select register 1 (0x402C6)
SPT21–SPT20: FPT2 interrupt input po rt se l ection (D[5:4]) / Port input interrupt select register 1 (0x402C6)
SPT11–SPT10: FPT1 interrupt input po rt se l ection (D[3:2]) / Port input interrupt select register 1 (0x402C6)
SPT01–SPT00: FPT0 interrupt input po rt se l ection (D[1:0]) / Port input interrupt select register 1 (0x402C6)
Select an input pin for port interrupt generation.
Table 9.11 Selecting Pins for Port Input Interrupts
Interrupt SPT settings
system 11 10 01 00
FPT7 P27 P07 P33 K67
FPT6 P26 P06 P32 K66
FPT5 P25 P05 P31 K65
FPT4 P24 P04 K54 K64
FPT3 P23 P03 K53 K63
FPT2 P22 P02 K52 K62
FPT1 P21 P01 K51 K61
FPT0 P20 P00 K50 K60
At c old start, SPT is set to "00". At hot start, SPT retains its state from prior to the initial reset.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
S1C33L03 FUNCTION PART EPSON B-III-9-21
A-1
B-III
I/O
SPPT7–SPPT0: Input polarity s ele ct io n (D[7:0 ]) / P o rt interru pt input p ola ri ty s ele ct register (0x40 2C8 )
Selects input signal porarity for port interrupt generation.
Write "1": H igh level or Rising edge
Write "0": Low level or Falling edge
Read: Valid
SPPTx i s the input polarity select bit corresponding to the FPTx interrupt. When SPPTx is set to "1", the FPTx
interrupt will be generated by a high level input or at the rising edge. When SPPTx is set to "0", the interrupt will
be gen erated by a low level input or at the falling edge. An edge or a level interrupt is selected by the SEPTx bit.
At c old start, SPPT is set to "0" (low level). At hot start, SPPT retains its state from prior to the initial reset.
SEPT7–SEPT0: Edge/level selection (D[7:0]) / Port interrupt edge/level select register (0x402C9)
Selects an edge trigger or a level trigger for port interrupt generation.
Write "1": Edge
Write "0": Lev el
Read: Valid
SE PTx is the edge/level select bit corresponding to the FPTx interrupt. When SEPTx is set to "1", the FPTx
interrupt will be generated at the signal edge. Either falling edge or rising edge can be selected by the SPPTx bit.
When SEPTx i s set to "0", the interrupt will be generated by the level (high or low) specified with the SPPTx bit.
At c old start, SEPT is set to "0" (level). At hot start, SEPT retains its state from prior to the initial reset.
SPPK11–SPPK10: FPK1 interrupt input port selection (D[3:2]) / Key input interrupt select register (0x402CA)
SPPK01–SPPK00: FPK0 interrupt input port selection (D[1:0]) / Key input interrupt select register (0x402CA)
Select an input-pin group for key interrupt generation.
Table 9.12 Selecting Pins for Key Input Interrupts
Interrupt SPPK settings
system 11 10 01 00
FPK1 P2[7:4] P0[7:4] K6[7:4] K6[3:0]
FPK0 P2[4:0] P0[4:0] K6[4:0] K5[4:0]
At c old start, SPPK is set to "00". At hot start, SPPK retains its state from prior to the initial reset.
SCPK13–SCPK10: FPK1 input c omp ari so n (D[3 :0 ]) / F PK 1 input c omp ari so n regist er (0x40 2CD )
SCPK04–SCPK00: FPK0 input c omp ari so n (D[4:0 ]) / F PK0 input c om p ari son re gi st er (0x40 2CC )
Sets the conditions for key-input interrupt generation (timing of interrupt generation).
Write "1": Generate d at falling edge
Write "0": Generate d at rising edge
Read: Valid
SC PK0[4:0] is compared with the input state of five bits of the FPK0 input ports, and SCPK1[3:0] is compared
with the input state of four bits of the FPK1 input ports, and when a change in states from a matched to an
unmatched state occurs in either, an interrupt is generated (except for the inputs disabled from interrupt by the
SMPK register).
At c old start, SCPK is set to "0" (rising edge). At hot start, SCPK retains its state from prior to the initial reset.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
B-III-9-22 EPSON S1C33L03 FUNCTION PART
SMPK13–SMPK10: FPK1 input m as k (D[3 :0 ]) / F PK1 input m as k re gi s ter (0x40 2CF )
SMPK04–SMPK00: FPK0 input m as k (D[4 :0 ]) / F PK0 input m as k re gi st er (0x40 2CE )
Sets condit ion s fo r key- in pu t inte rru pt g eneratio n (i nte rru pt enab le d/d is ab led).
Write "1": Inte rrupt enabled
Write "0": Inte rrupt disabled
Read: Valid
SMPK is a n input mask register for each key-input interrupt system. Interrupts for bits set to "1" are enabled, and
interrupts for bits set to "0" are disabled. A change in the state of an input pin that is disabled from interrupt does
not affect interru pt g ene ra tio n.
At c old start, SMPK is set to "0" (interrupt disabled). At hot start, SMPK retains its state from prior to the initial
reset.
PP0L2–PP0L0: Port input 0 interrupt level (D[2:0]) / Port input 0/1 interrupt priority register (0x40260)
PP1L2–PP1L0: Port input 1 interrupt level (D[6:4]) / Port input 0/1 interrupt priority register (0x40260)
PP2L2–PP2L0: Port input 2 interrupt level (D[2:0]) / Port input 2/3 interrupt priority register (0x40261)
PP3L2–PP3L0: Port input 3 interrupt level (D[6:4]) / Port input 2/3 interrupt priority register (0x40261)
PP4L2–PP4L0: Port input 4 interrupt level (D[2:0]) / Port input 4/5 interrupt priority register (0x4026C)
PP5L2–PP5L0: Port input 5 int errupt level (D[ 6:4]) / Port input 4/5 int errup t priority r egiste r (0x 4026C)
PP6L2–PP6L0: Port input 6 interrupt level (D[2:0]) / Port input 6/7 interrupt priority register (0x4026D)
PP7L2–PP7L0: Port input 7 interrupt level (D[6:4]) / Port input 6/7 interrupt priority register (0x4026D)
PK0L2–PK0L0: Key input 0 interrupt level (D[2:0]) / Key input interrupt priority register (0x40262)
PK1L2–PK1L0: Key input 1 interrupt level (D[6:4]) / Key input interrupt priority register (0x40262)
Sets the priority level of the input interrupt.
PP xL and PK xL are interrupt pri ority regist ers corresponding to each port-input inter rupt and key-input interrupt,
respectively.
The priority level can be set for each interrupt group in the range of 0 to 7.
At i nitial reset, these registers becomes indeterminate.
EP3–EP0: Port input 3–0 interrupt enable (D[3:0]) /
Key input, por t input 0–3 i nterrupt enable register (0x40270)
EP7–EP4: Port input 7–4 interrupt enable (D[5:2]) /
Port inp ut 4–7, clock timer, A/D interrupt en able regis ter ( 0x402 77)
EK1, EK0: Key input 1, 0 interrupt enable (D[5:4]) /
Key input, por t input 0–3 i nterrupt enable register (0x40270)
Enabl es or disables the generation of an interrupt to the CPU.
Write "1": Inte rrupt enabled
Write "0": Inte rrupt disabled
Read: Valid
EP and EK are interrupt enable bits corresponding to the port-input interrupt and the key-input interrupt,
respectively. Interrupts for input systems set to "1" are enabled, and interrupts for input systems set to "0" are
disabled.
At i nitial reset, these bits are set to "0" (interrupt disabled).
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
S1C33L03 FUNCTION PART EPSON B-III-9-23
A-1
B-III
I/O
FP3–FP0: Port input 3–0 interrupt factor flag (D[3:0]) /
Key input, port input 0–3 interrupt factor flag register (0x40280)
FP7–FP4: Port input 7–4 interrupt factor flag (D[5:2]) /
Port input 4–7, clock timer, A/D interrupt factor flag register (0x40287)
FK1, FK0: Key input 1, 0 interrupt factor flag (D[5:4]) /
Key input, port input 0–3 interrupt factor flag register (0x40280)
Indicates the status of an input interrupt factor generated.
When read
Read "1": Interrupt facto r has o ccu rred
Read "0": No inte rrupt fa ctor h as o ccu rred
When written using the rese t-onl y m etho d (d ef au lt)
Write "1": Interrupt factor flag is reset
Write "0": Invalid
When written using the read /w rite m et ho d
Write "1": Interrupt flag is set
Write "0": Interrupt flag is reset
FP and FK are an interrupt factor flags corresponding to the port-input interrupt and the key-input interrupt,
respectively. The flag is set to "1" when interrupt generation conditions are met.
At t his time, if the following conditions are met, an interrupt to the CPU is generated:
1. The corresponding interrupt enable register bit is set to "1".
2. No other interrupt request of a higher prior ity has been generated.
3. The IE bit of the PSR is set to "1" (interrupts enabled).
4. The value set in the corresponding interrupt priority register is higher than the interrupt level (IL) of the CPU.
When using the interrupt factor of the port-input to request IDMA, note that even when the above conditions are
met, no interrupt request to the CPU is generated for the interrupt factor that has occurred. If interrupts are enabled
at the setting of IDMA, an interrupt is generated under the above conditions after the data transfer by IDMA is
completed.
The interrupt factor flag is set to "1" whenever interrupt generation conditions are met, regardless of how the
inte rrupt en ab le and in te rru pt p riority regi ste rs are set.
If the next interrupt is to be accepted after an interrupt has occurred, it is necessary that the interrupt factor flag be
reset, and that the PSR be set again (by setting the IE bit to "1" after setting the IL to a value lower than the level
indicated by the interrupt priority register, or by executing the reti instruction).
The interrupt factor flag can be reset only by writing to it in the software. Note that if the PSR is set again to accept
interrupts generated (or if the reti instruction is executed) without resetting the interrupt factor flag, the same
interrupt occurs again. Note also that the value to be written to reset the flag is "1" when the reset-only method
(RSTONLY = " 1" ) is used, and "0" when the rea d/ write me thod (RSTONLY = "0" ) is used.
At i nitial reset, all the flags become indeterminate, so be sure to reset them in the software.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
B-III-9-24 EPSON S1C33L03 FUNCTION PART
RP3–RP0: Port input 3–0 IDMA request (D[3:0]) /
Port inp ut 0–3, high-speed DMA, 16-bit timer 0 IDMA request register (0x40290)
RP7–RP4: Port inpu t 7 –4 IDMA reque st (D [7 :4 ]) /
Serial I/F Ch.1, A/D, Port input 4–7 IDMA request register (0x40293)
Specifies whether to invoke IDMA when an interrupt factor occurs.
When using the se t-o n ly m et ho d (d ef ault)
Write "1": IDMA request
Write "0": Not changed
Read: Valid
When using the read /w rite m et ho d
Write "1": IDMA request
Write "0": Inte rrupt request
Read: Valid
RP7 to RP0 are IDMA request bits corres pond ing to t he po rt-i nput 7 to 0 interrupts, respectively. If the bit is set to
"1", IDMA is invoked when an interrupt factor occurs, thereby performing a programmed data transfer. If the bit is
set to "0", normal interrupt processing is performed, without invoking IDMA.
For details on IDMA, refer to "IDMA (Intelligent DMA)".
At i nitial reset, RP is set to "0" (interrupt request).
DEP3–DEP0: Port input 3–0 IDMA enable (D[3:0]) /
Port inp ut 0–3, high-speed DMA, 16-bit timer 0 IDMA enable regis ter (0x40294)
DEP7–DEP4: Port input 7–4 IDMA enable (D[7:4]) /
Serial I/F Ch.1, A/D, Port input 4–7 IDMA enable register (0x40297)
Enables ID M A transfer by means of an interrupt factor.
When using the se t-o n ly m et ho d (d ef ault)
Write "1": IDMA enabled
Write "0": Not changed
Read: Valid
When using the read /w rite m et ho d
Write "1": IDMA enabled
Write "0": IDMA disabled
Read: Valid
If DEP is set to "1", the IDMA request by the interrupt factor is enabled. If the register bit is set to "0", the IDMA
request is disabled.
Aft er an initial reset, DEP is set to "0" (IDMA disabled).
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
S1C33L03 FUNCTION PART EPSON B-III-9-25
A-1
B-III
I/O
Programming Notes
(1) After an initial reset, the interrupt factor flags become indeterminate. To prevent generation of an unwanted
interrupt or IDMA request, be sure to reset the flags in a program.
(2) To prevent regeneration of interrupts due to the same factor following the occurrence of an interrupt, always
be sure to reset the interrupt factor flag before resetting the PSR or executing the reti instruction.
(3) The input/output ports operate only when the prescaler is operating.
(4) When restarting from the SLEEP or HALT2 state, interrupt input from a port can be used as a trigger, but
func tio na lly , this in te rru pt in pu t oper at es as leve l inpu t. T herefor e, a leve l inpu t base d re sta rt is perf ormed
even in the case of set edge input.
Restart operation is as follows for rising and falling edges.
In case of rising edge interrupt setting: Restarted by high level input.
In case of falling edge interrupt setting: Restarted by low level input.
In normal operation, a restart begins following the elapse of a given time after execution of the SLP
instruction, but when restart by a falling (rising) level (edge) is set, the operation is as follows.
•The restart is effected immediately after execution of the SLP instruction.
•As ports are already at the low level when the SLP instruction is executed, there is no falling (rising) edge,
and therefore the SLEEP state is entered only momentarily, and the restart is effected immediately
afterwards.
There was a syn chronization circuit using a clock signal in the port input circuit, and as the clock is stopped
in the SLEEP state and the clock can be stopped in the HALT2 state, the configuration provided for this
synchronization circuit to be bypassed when restarting. Therefore, a restart is effected when the input level
from a port is active by level. Consequently, the system design should assume that a restart by means of port
input from the SLEEP state or HALT2 state is performed by level.
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
B-III-9-26 EPSON S1C33L03 FUNCTION PART
TH IS PAGE IS BLANK.
S1C33L03 FUNCTION PART
IV ANALOG BLOCK
IV ANALOG BLOCK: IN TRODUCTION
S1C33L03 FUNCTION PART EPSON B-IV-1-1
A-1
B-IV
Intro
IV-1 INTRODUCTION
The analog block consists of an A/D converter with 8 input channels.
CORE_PAD
Pads
C33_SBUS
C33 Core Block
C33 LCD Controller Block
Pads
PERI_PAD
Pads
C33_PERI
(Prescaler, 8-bit timer, 16-bit timer,
Clock timer, Serial interface, Ports)
C33 Peripheral BlockC33 Analog Block
C33_CORE
(CPU, BCU, ITC, CLG, DBG)
C33_ADC
(A/D converter)
C33 Internal Memory Block
Internal RAM
(Area 0)
Internal ROM
(Area 10)
C33 DMA Block
C33_DMA
(IDMA, HSDMA)
C33_SDRAMC
(SDRAM interface)
C33_LCDC
(LCD panel interface)
C33 SDRAM Controller Block
Figur e 1. 1 Analog Block
Note: In te rn al RO M is not prov ided in the S 1C33L03 .
IV ANALOG BLOCK: IN TRODUCTION
B-IV-1-2 EPSON S1C33L03 FUNCTION PART
TH IS PAGE IS BLANK.
IV ANALOG BLOC K: A/D CONVERTER
S1C33L03 FUNCTION PART EPSON B-IV-2-1
A-1
B-IV
A/D
IV-2 A/D CONVERTER
Features and Structure of A/D Converter
The A nal og Bl ock contains an A/D converter with the following features:
•Conversion method: Successive comparison
•Resolution: 10 bits
•Input chan ne ls : M ax im um o f 8
•Conversion time: Maximum o f 10 µs (w hen a 2-M Hz i n put clock is selected)
•Conversion range: Between VSS and AVDDE
•Two conversion modes can be sele cted:
Normal mode: Conversion is completed in one operation.
Continuous mode: Conversion is continuous and terminated through software control.
Continuous conversion of multiple channels can be performed in each mode.
•Four types of A/D-conversion start triggers can be selected:
Triggered by the external pin (#ADTRG)
Triggered by the compare match B of the 16-bit programmable timer 0
Triggered by the underflow of the 8-bit programm able timer 0
Triggered by the software
•A/D conversion results can be read out fr om a 10-bit data regi ste r.
•An interru pt is gene ra ted upon com pletion of A/D conversion.
Figure 2.1 shows the structure of the A/D converter.
Internal data bus
AV
DDE
V
SS
Analog
input
decoder Control circuit
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
#ADTRG
8-bit timer 0
16-bit timer 0
Clock
generator Prescaler Interrupt request
Analog
block
Successive
approximation
block
Data
register
Interrupt
control
circuit
Control
registers
Figur e 2.1 Structure of A/D Converter
IV ANALOG BLOC K: A/D CONVERTER
B-IV-2-2 EPSON S1C33L03 FUNCTION PART
I/O Pins of A/D Converter
Table 2.1 shows t he pins us ed by the A /D c onve rter.
Table 2.1 I/O Pins of A/D Converter
Pin name I/O Function Function select bit
K52/#ADTRG I Input port / AD trigger CFK52(D2)/K5 function select register(0x402C0)
K60/AD0 I Input port / AD converter input 0 CFK60(D0)/K6 function select register(0x402C3)
K61/AD1 I Input port / AD converter input 1 CFK61(D1)/K6 function select register(0x402C3)
K62/AD2 I Input port / AD converter input 2 CFK62(D2)/K6 function select register(0x402C3)
K63/AD3 I Input port / AD converter input 3 CFK63(D3)/K6 function select register(0x402C3)
K64/AD4 I Input port / AD converter input 4 CFK64(D4)/K6 function select register(0x402C3)
K65/AD5 I Input port / AD converter input 5 CFK65(D5)/K6 function select register(0x402C3)
K66/AD6 I Input port / AD converter input 6 CFK66(D6)/K6 function select register(0x402C3)
K67/AD7 I Input port / AD converter input 7 CFK67(D7)/K6 function select register(0x402C3)
AVDDE –Analog refe r ence v olta ge (+) –
AVDDE (analog power-supply pin)
AVDDE is the power-supply pin for the analog circuit. The voltage level supplied to this pin must be AVDDE
= VDDE.
Note: When the A /D con verte r is set to enabl ed state, a cu rrent flows between AV DDE and VSS, and
power is consumed, even when A/D operations are not performed. Therefore, when the A/D
converter is not used, it mu st be set to the disabled state (default "0" setting of ADE (D2) in the
A/D enable register (0x40244)).
AD[7:0] (analog-signal input pins)
The analog input pins AD7 (Ch.7) through AD0 (Ch.0) are shared with input port pins K67 through K60.
There fore, wh en these pin s are used for analog input, they must be set for use with the A/D converter in the
software. This setting can be made individually for each pin. At cold start, all these pins are set for input
ports.
The analog input voltage AVIN can be input in the range of VSS ≤ AVIN ≤ AVDDE.
#ADTRG (external-trigger input pin)
This pin is used to input a trigger signal to start A/D conversion from an external source. Since this pin is
shared with input port K52, it must be set for use with the A/D converter in the software before an external
trigger can be applied to the pin. At cold start, this pin is set for an input port.
Method for setting A/D-converter input pins
At c old start, the #ADTRG and AD[7:0] pins all are set for input ports Kxx (function select bit CFKxx = "0").
When using these pins for the A/D converter, write "1" to the function select bit CFKxx.
At ho t start, these pins retain their state from prior to the reset.
IV ANALOG BLOC K: A/D CONVERTER
S1C33L03 FUNCTION PART EPSON B-IV-2-3
A-1
B-IV
A/D
Setting A/D Converter
When the A/D c onverter is used, the following settings must be made before an A/D conversion can be performed:
1. Setting analog input pins
2. Setting the input clock
3. Selectin g the analog-conversion start and end channels
4. Setti ng the A/ D conversion mo de
5. Selectin g a trigger
6. Setting the sampling time
7. Setting interrupt/IDMA/HSDMA
The following de scribes how t o set each item. For details on how to set the analog input pins, refer to the preceding
section. For details on how to set interrupt/DMA, refer to "A/D Converter Interrupt and DMA".
Note: Befo re maki ng these settings, make sure the A/D converter is disabled (ADE (D2) / A/D enable
register (0 x40244) = "0"). Changing the settings while the A/D converter is enabled could cause a
malfunction.
Setting the input clock
As explained in "Prescaler", the A/D conversion clock can be selected from among the eight types shown in
Tabl e 2.2 below . Use PSAD[2:0] (D[2:0]) / A/D clo ck control register (0x4014F) for this selection.
Table 2.2 Input Clock Selection
PSAD2 PSAD1 PSAD0 Division ratio
111fPSCIN/256
110fPSCIN/128
101fPSCIN/64
100fPSCIN/32
011fPSCIN/16
010fPSCIN/8
001fPSCIN/4
000fPSCIN/2
fPSCIN: Prescaler input clock frequency
The selected c lock is output from the prescaler to the A/D converter by w riting "1" to PSONAD (D3) / A/D
clock control register (0x4014F).
Notes:•The A/D converter operates only when the prescaler is operating.
•The recommended i nput clock fre quenc y is a maximum of 2 MHz.
•Do not start an A/D conversion when the clock output from the prescaler to the A/D converter is
turned off, and do not turn off the prescaler's clock output when an A/D conversion is underway.
This could cause the A/D converter to operat e errat icall y.
Selecting anal o g -conversio n start and end ch ann els
Select the channel in which the A/D conversion is to be performed from among the pins (channels) that have
been set for analog input. To enable A/D conversions in multiple channels to be performed successively
through one convert operation, specify the conversion start and conversion end channels.
Conversion start ch an ne l: C S[ 2:0 ] (D [2 :0 ]) / A /D chan ne l regi ster (0x4 02 43)
Conversion e nd chan ne l: CE[2:0 ] (D [5:3]) / A /D chan nel regi ster (0x4 0243 )
IV ANALOG BLOC K: A/D CONVERTER
B-IV-2-4 EPSON S1C33L03 FUNCTION PART
Table 2.3 Relationship between CS/CE and Input Channel
CS2/CE2 CS1/CE1 CS0/CE0 Channel selected
11 1 AD7
11 0 AD6
10 1 AD5
10 0 AD4
01 1 AD3
01 0 AD2
00 1 AD1
00 0 AD0
Example: Operation of one A/D conversion
CS[2:0] = "0", CE[2:0] = "0": Converted only in AD0
CS[2:0] = "0", CE[2:0] = "3": Converted in the following order: AD0→AD1→AD2→AD3
CS[2:0] = "5", CE[2:0] = "1": Converted in the following order: AD5→AD6→AD7→AD0→AD1
Note: Only co nv ersion-channel input pins that have been set for use wi th the A/D converter can be se t
using the CS and CE bits.
Setting the A/D conversion mode
The A/ D conve rt er can operate in one of the following two modes. This operation mode is selected using MS
(D5) / A/D trigger register (0x40242).
1. Normal mode (MS = "0" )
All inputs in the range of channels set using the CS and CE bits are A/D converted once and then
stopped.
2. Conti nuous mo de (MS = "1" )
A/D c onversi ons in the range of channels set using the CS and CE bits are executed successively until
stopped by the software.
At i nitial reset, the normal mode is selected.
Selecting a trigger
Use TS[1:0] (D[4:3]) / A/D trigger register (0x40242) to select a trigger to start A/D conversion from among
the four types shown in Table 2.4.
Table 2.4 Trigger Selection
TS1 TS0 Trigger
11External trig ge r (K52/#ADTRG)
108-bit programmable timer 0
0116-bit programmable timer 0
00Software
1. External trigger
The signal input to the #ADTRG pin is used as a trigger.
Whe n this trigger is used, the K52 pin must be set for #ADTRG in advance by writing "1" to CFK52
(D2 ) / K5 fu nction select regist e r (0x4 02 C 0).
A/D c onversi on is started at a falling edge of the #ADTRG signal.
2. Programmable timer
The unde rflow signal of 8-bit programm able tim er 0 or the coma rison ma tch B signal of the 16-bit
programmable timer 0 is used as a trigger. Since the cycle can be programmed using each timer, this
trigger is effective when cyclic A/D conversions are required.
For details on how to set a timer, refer to the explanation of each programmable timer in this manual.
3. Software trigger
Writing "1" to ADST (D1) / A/D enable register (0x40244) in the software serves as a trigger to start
A/D c onversi on.
IV ANALOG BLOC K: A/D CONVERTER
S1C33L03 FUNCTION PART EPSON B-IV-2-5
A-1
B-IV
A/D
Setting the sampling time
The A/ D conve rt er co ntains ST[1:0] (D[1:0]) / A/D sampling register (0x40245) that allows the analog-signal
input sampling time to be set in four steps (3, 5, 7, or 9 times the input clock period).
However, this regist er should be used as set by default (ST = "11"; x9 clock periods).
Control and Operation of A/D Conversion
Figure 2.2 shows the operation of the A/D converter.
ADE
Trigger
ADST
A/D operation
ADD
ADF
Conversion-result read
OWE
Interrupt request
AD0 AD0
Sampling Conversion
AD1 AD1
Sampling Conversion
AD2
AD0 converted data AD1 converted data
(When AD0 to AD2 are converted)
AD2 converted data
ADD is overwritten
AD2
Sampling Conversion
(1) Normal mode
ADE
Trigger
ADST
A/D operation
ADD
ADF
Conversion-result read
OWE
Interrupt request
AD0-1 AD0-1
Sampling Conversion AD0-2 AD0-2
Sampling Conversion AD0-3
AD0-1 converted data AD0-2 converted data
(When only AD0 is converted) Reset in software
invalid
Sampling Conversion
(2) Continuous mode
Figur e 2.2 Operation of A/D Converter
Starting up the A/D converter circuit
After the settings specified in the preceding section have been made, write "1" to ADE (D2) / A/D enable
register (0x40244) to enable the A/D converter. The A/D converter is thereby readied to accept a trigger to
start A/D conversion. To set the A/D converter again, or if it is not be used, set ADE to "0".
Starting A/D conversion
When a trigger is input while ADE = "1", A/D conversion is started. If a software trigger has been selected,
A/D convers ion is star te d by writi ng "1" to ADST (D1) / A/D e nable reg is ter (0x 40244).
Only the trigger selected using TS[1:0] (D[4:3]) / A/D trigger register (0x40242) are valid; no other trigger is
accepted.
IV ANALOG BLOC K: A/D CONVERTER
B-IV-2-6 EPSON S1C33L03 FUNCTION PART
When a trigger is input, the A/D converter samples and A/D-converts the analog input signal, beginning with
the conversion start channel selected by CS[2:0].
Upon comple tion of the A/D conversion in that channel, the A/D converter stores the conversion result, in 10-
bit data registers ADD[9:0] (ADD[9:8] = D[1:0]/0x40241, ADD[7:0] = D[7:0]/0x40240), and sets the
conversion-complete flag ADF (D3) / A/D enable register (0x40244) and interrupt factor flag FADE (D0) /
Port inp ut 4–7, clock timer and A/D interrupt factor flag register (0x40287). If multiple channels are specified
using CS[2 :0] and CE[2:0], A/D conversions in the subsequent channels are performed in succession.
The ADST us ed for the software trigger is set to "1" during A/D conversion, even when it is started by some
other trigger, so it can be used a s an A/D -co nve rsion status bit.
The channel in which conversion is underway can be identified by reading CH[2:0] (D[2:0]) / A/D trigger
register (0x40242).
Reading out A/D conversion results
As explained earlier, the results of A/D conversion are stored in the ADD[9:0] register each time conversion
in one ch an ne l is complete d. S inc e an inte rru pt ca n b e gene ra ted simu lt an eou sl y, th is in terru pt is norm a lly
used to read out the converted data. In addition, be sure to reset the interrupt factor flag (by writing "0") to
prepare the A/D converter for the next operation.
Since the interrupt factor of the A/D converter can also be used to invoke DMA, the conversion results can
automatically be transferred to a specified memory location.
If multiple A/D conversion channels are specified, the conversion results in one channel must be read out
prior to completion of conversion in the next channel. If the A/D conversion currently under way is
completed before the previous conversion results are read out, the ADD[9:0] register is overwritten with the
new con versio n re su lts .
If ADD[9:0] is updated when the conversion-complete flag ADF = "1" (before the converted data is read out),
the overwrite-error flag OWE (D0) / A/D enable register (0x40244) is set to "1". The conversion-complete
flag ADF is reset to "0" when the converted data is read out. If ADD[9:0] is updated when ADF = "0", OWE
remains at "0", indicating that the operation has been completed normally. When reading out data, also read
the OWE flag also to make sure the data is valid. Once OWE is set, it remains set until it is reset to "0" in the
software. Note also that if OWE is set, ADF also is set. In this case, read out the converted data and reset
ADF.
Terminating A/D conversion
•For normal mode (MS = "1")
In the normal mode, A/D conversion is performed successively from the conversion start channel specified
using CS[2 :0] to the conversion end channel specified using CE[2:0], and is completed after these
conversions are executed in one operation. ADST is reset to "0" upon completion of the conversion.
•For continuous mode (MS = "0")
In the continuous mode, A/D conversion from the conversion-start to the conversion-end channels is executed
repeatedly, without being stopped in the hardware. To terminate conversion, therefore, ADST must be reset to
"0" in the software. However, the A/D conversion being executed will be completed normally or forcibly
stopped depending on the timing of writing "0" to ADST. When the A/D conversion has completed normally,
AD F is set to "1" and the conversion results can be obtained. If it is forcibly stopped, ADF maintains its
previous status, therefore, conversion results cannot be obtained.
•Forced t e rm ina tion
In the continuous mode, A/D conversion is immediately terminated by writing "0" to ADST. The results of
the conversion then under-way cannot be obtained.
In the normal mode, writing "0" to ADST cannot terminate A/D conversion.
Note that writing "0" to ADE cannot terminate the A/D conversion under-way (ADST = "1").
Note: Once A/D conversion ends, further A/D conversion will not be performed correctly if restarted
within an interval shorter than one cycle of the A/D converter operati ng clock set by the prescaler.
IV ANALOG BLOC K: A/D CONVERTER
S1C33L03 FUNCTION PART EPSON B-IV-2-7
A-1
B-IV
A/D
A/D Converter Interrupt and DMA
Upon comple tion of A/D conversion in each channel, the A/D converter generates an interrupt and invokes the
DMA if necessary.
Control registers of the interrupt controller
The following shows the interrupt control registers available for the A/D converter:
Interrupt factor flag: FADE (D0) / Port input 4–7, clock timer, A/D interrupt factor flag register (0x40287)
Interrupt enable: EADE (D0) / Port input 4–7, clock timer, A/D interrupt enable register (0x40277)
Inte rrupt leve l: PA D[ 2: 0] (D [6 :4 ]) / Seri al I/F Ch.1 , A/ D inte rrupt p rio rity regi ster (0x4 02 6A )
The A/ D conve rt er sets the interrupt factor flag to "1" when A/D conversion in one channel is completed, and
the conversion results are stored in the ADD register. At this time, if the interrupt enable register bit has been
set to "1", an interrupt request is generated.
Interrupts can be disabled by leaving the interrupt enable register bit set to "0". The interrupt factor flag is set
to "1" upon completion of A/D conversion in each channel, regardless of the setting of the interrupt enable
register (even when it is set to "0").
The interrupt priority register sets the priority level (0 to 7) of an interrupt. An interrupt request to the CPU is
accepted no other interrupt request of a h igh er prio rity has been generated.
In addition, it is only when the PSR's IE bit = "1" (interrupts enabled) and the set value of the IL is smaller
than the A/D-converter interrupt level set by the interrupt priority register, that the A/D converter's interrupt
request is actually accepted by the CPU.
For details on these interrupt control registers, as well as the device operation when an interrupt has occurred,
refer to "ITC (Interrupt Controller)".
Int e ll ig e nt D M A
The A/D converter can invoke the intelligent DMA (IDMA) through the use of its interrupt factor. This
allows the conversion results to be transferred to a specified memory location with no need to execute an
inte rrupt p roc es sin g ro utine.
The IDMA channel number assigned to the A/D converter is 0x1B.
Before IDMA can be invoked, the IDMA request and IDMA enable bits must be set to "1". Transfer
conditions on the IDMA side must also be set in advance.
IDMA request: RADE (D2) / Serial I/F Ch.1, A/D, Port input 4–7 IDMA request register (0x40293)
IDMA enable: DEADE (D2) / Serial I/F Ch.1, A/D, Port input 4–7 IDMA enable register (0x40297)
If an interrupt factor occurs when the IDMA request and IDMA enable bits are set to "1", IDMA is invoked.
No interrupt request is generated at that point. An interrupt request is generated upon completion of the DMA
transfer. Otherwise, the bit can be set so as not to generate an interrupt, with only a DMA transfer performed.
For details on DMA transfers and how to control interrupts upon completion of a DMA transfer, refer to
"IDMA (Int elligent DMA)".
Hig h -speed DM A
The A/ D interr upt fa cto r ca n al so invoke hi gh -s pe ed D M A (H S DMA ).
The f ol lowing shows the HSDMA channel number and trigger set-up bit:
Table 2.5 HSDMA Trigger Set-up Bits
HSDMA channel Trigger set-up bits
0HSD0S[3:0] (D[3:0]) / HSDMA Ch.0/1 trigger set-up register (0x40298)
1HSD1S[3:0] (D[7:4]) / HSDMA Ch.0/1 trigger set-up register (0x40298)
2HSD2S[3:0] (D[3:0]) / HSDMA Ch.2/3 trigger set-up register (0x40299)
3HSD3S[3:0] (D[7:4]) / HSDMA Ch.2/3 trigger set-up register (0x40299)
For HSDMA t o be invok ed, the trigger set-up bits should be set to "1100" in advance. Transfer conditions, etc.
must also be set on the HSDMA side.
If the A/D interrupt factor is selected as the HSDMA trigger, the HSDMA channel is invoked through
generation of the interrupt factor.
For details on HSDMA transfer, refer to "HSDMA (High-Speed DMA)".
IV ANALOG BLOC K: A/D CONVERTER
B-IV-2-8 EPSON S1C33L03 FUNCTION PART
Trap vector
The A/ D conve rt er's interrupt trap-vector default address is set to 0x0C00100.
The bas e address of the trap table can be changed using the TTBR register (0x48134 to 0x48137).
IV ANALOG BLOC K: A/D CONVERTER
S1C33L03 FUNCTION PART EPSON B-IV-2-9
A-1
B-IV
A/D
I/O Memo ry of A/D Converter
Table 2.6 shows t he control bits of the A/D converter.
For details on the I/O memory of the prescaler used to set clocks, refer to "Prescaler". For details on the I/O
memory of the pr ogrammab le timers used for a trigger, refer to "8-Bit Programmable Timers" or "16-Bit
Programmable Timers".
Table 2.6 Control Bits of A/D Converter
NameAddressRegister name Bit Function Setting Init. R/W Remarks
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
D7
D6
D5
D4
D3
D2
D1
D0
A/D converted data
(low-order 8 bits)
ADD0 = LSB
0x0 to 0x3FF
(low-order 8 bits) 0
0
0
0
0
0
0
0
R0040240
(B)
A/D conversion
result (low-
order) register
0x0 to 0x3FF
(high-order 2 bits)
––
ADD9
ADD8
D7–2
D1
D0
–
A/D converted data
(high-order 2 bits) ADD9 = MSB
–
0
0
–
R0 when being read.0040241
(B)
A/D conversion
result (high-
order) register
–
MS
TS1
TS0
CH2
CH1
CH0
D7–6
D5
D4
D3
D2
D1
D0
–
A/D conversion mode selection
A/D conversion trigger selection
A/D conversion channel status
1
1
0
0
1
0
1
0
TS[1:0]
–
Trigger
#ADTRG pin
8-bit timer 0
16-bit timer 0
Software
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
CH[2:0] Channel
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
–
0
0
0
0
0
0
–
R/W
R/W
R
0 when being read.0040242
(B) 1 Continuous 0 Normal
A/D trigger
register
–
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
CE[2:0] End channel
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
CS[2:0] Start channel
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
–
CE2
CE1
CE0
CS2
CS1
CS0
D7–6
D5
D4
D3
D2
D1
D0
–
A/D converter
end channel selection
A/D converter
start channel selection
–
0
0
0
0
0
0
–
R/W
R/W
0 when being read.0040243
(B)
A/D channel
register
–
ADF
ADE
ADST
OWE
D7–4
D3
D2
D1
D0
–
Conversion-complete flag
A/D enable
A/D conversion control/status
Overwrite error flag
– –
0
0
0
0
–
R
R/W
R/W
R/W
0 when being read.
Reset when ADD is read.
Reset by writing 0.
0040244
(B)
A/D enable
register 1 Enabled 0 Disabled
1 Completed 0
Run/Standby
1 Start/Run 0 Stop
1 Error 0 Normal
–
ST1
ST0
D7–2
D1
D0
–
Input signal sampling time setup –
1
1
0
0
1
0
1
0
ST[1:0] Sampring time
9 clocks
7 clocks
5 clocks
3 clocks
–
1
1
–
R/W 0 when being read.
Use with 9 clocks.
0040245
(B)
A/D sampling
register
IV ANALOG BLOC K: A/D CONVERTER
B-IV-2-10 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
0 to 7
0 to 7
–
–
PAD2
PAD1
PAD0
–
PSIO12
PSIO11
PSIO10
D7
D6
D5
D4
D3
D2
D1
D0
reserved
A/D converter interrupt level
reserved
Serial interface Ch.1
interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
004026A
(B)
Serial I/F Ch.1,
A/D interrupt
priority register
–
EP7
EP6
EP5
EP4
ECTM
EADE
D7–6
D5
D4
D3
D2
D1
D0
reserved
Port input 7
Port input 6
Port input 5
Port input 4
Clock timer
A/D converter
– –
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.0040277
(B) 1 Enabled 0 Disabled
Port input 4–7,
clock timer,
A/D interrupt
enable register
–
FP7
FP6
FP5
FP4
FCTM
FADE
D7–6
D5
D4
D3
D2
D1
D0
reserved
Port input 7
Port input 6
Port input 5
Port input 4
Clock timer
A/D converter
– –
X
X
X
X
X
X
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.0040287
(B) 1 Factor is
generated 0 No factor is
generated
Port input 4–7,
clock timer, A/D
interrupt factor
flag register
RP7
RP6
RP5
RP4
–
RADE
RSTX1
RSRX1
D7
D6
D5
D4
D3
D2
D1
D0
Port input 7
Port input 6
Port input 5
Port input 4
reserved
A/D converter
SIF Ch.1 transmit buffer empty
SIF Ch.1 receive buffer full
0
0
0
0
–
0
0
0
R/W
R/W
R/W
R/W
–
R/W
R/W
R/W
0 when being read.
0040293
(B) 1 IDMA
request 0 Interrupt
request
1 IDMA
request 0 Interrupt
request
–
Serial I/F Ch.1,
A/D,
port input 4–7
IDMA request
register
DEP7
DEP6
DEP5
DEP4
–
DEADE
DESTX1
DESRX1
D7
D6
D5
D4
D3
D2
D1
D0
Port input 7
Port input 6
Port input 5
Port input 4
reserved
A/D converter
SIF Ch.1 transmit buffer empty
SIF Ch.1 receive buffer full
0
0
0
0
–
0
0
0
R/W
R/W
R/W
R/W
–
R/W
R/W
R/W
0 when being read.
0040297
(B) 1 IDMA
enabled 0 IDMA
disabled
1 IDMA
enabled 0 IDMA
disabled
–
Serial I/F Ch.1,
A/D,
port input 4–7
IDMA enable
register
–
CFK54
CFK53
CFK52
CFK51
CFK50
D7–5
D4
D3
D2
D1
D0
reserved
K54 function selection
K53 function selection
K52 function selection
K51 function selection
K50 function selection
– –
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
0 when being read.00402C0
(B) 1
#DMAREQ3
0 K54
1
#DMAREQ2
0 K53
1 #ADTRG 0 K52
1
#DMAREQ1
0 K51
1
#DMAREQ0
0 K50
K5 function
select register
CFK67
CFK66
CFK65
CFK64
CFK63
CFK62
CFK61
CFK60
D7
D6
D5
D4
D3
D2
D1
D0
K67 function selection
K66 function selection
K65 function selection
K64 function selection
K63 function selection
K62 function selection
K61 function selection
K60 function selection
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00402C3
(B) 1 AD7 0 K67
1 AD6 0 K66
1 AD5 0 K65
1 AD4 0 K64
1 AD3 0 K63
1 AD2 0 K62
1 AD1 0 K61
1 AD0 0 K60
K6 function
select register
CFK52: K52 pin fu ncti on sel ection (D2) / K5 fun ction selec t regis ter (0x 402C0)
CFK67–CFK60: K6[ 7:0] p i n func tio n select io n (D[7:0 ]) / K 6 functio n select regi st er (0x4 0 2C3 )
Selects the pins used by the A/D converter.
Write "1": A/D converter
Write "0": Input port
Read: Valid
When an external trigger is used, write "1" to CFK52 to set the K52 pin for external trigger input #ADTRG. Select
the pin used for analog input from among K60 (AD0) through K67 (AD7) by writing "1" to CFK60 through
CFK67.
If the function select bit for a pin is set to "0", the pin is set for an input port.
At c old start, CFK is set to "0" (input port). At hot start, CFK retains its state from prior to the initial reset.
IV ANALOG BLOC K: A/D CONVERTER
S1C33L03 FUNCTION PART EPSON B-IV-2-11
A-1
B-IV
A/D
ADD9–ADD0: A/D converte d data (D[1 :0 ]) / A/ D con vers i on result (high-order) register (0x40241)
(D[7:0]) / A/D conversion result (low-order) register (0x40240)
Stores t he results of A/D conversion.
The LSB is stored in ADD0, and the MSB is sto re d in ADD9. ADD0 and ADD1 are mapped to bits D0 and D1 at
the address 0x40241, but bits D2 through D7 are always 0 when read.
This is a read-only register, so writing to this register is ignored.
At initial reset, the data in this register is cleared to "0".
MS: A/D conversion mo de selection (D5) / A/D trigger registe r (0x40242)
Selects an A/D conversion mode.
Write "1": C ontinuous mode
Write "0": N ormal mode
Read: Valid
The A/ D conve rt er is set for the continuous mode by writing "1" to MS. In this mode, A/D conversions in the range
of the channels selected using CS and CE are executed continuously until stopped in the software.
When MS = "0", the A/D converter operates in the normal mode. In this mode, A/D conversion is completed after
all inputs in the range of the channels selected by CS and CE are converted in one operation.
At i nitial reset, MS is set to "0" (normal mode).
TS1–TS0: T rig ger s ele ct io n (D[4:3 ]) / A /D trigg e r regi st er (0x 4 02 42)
Selects a trigger to start A/D conversion.
Table 2.7 Trigger Selection
TS1 TS0 Trigger
11External trig ge r (K52/#ADTR G)
108-bit programmable timer 0
0116-bit programmable timer 0
00Software
When an external trigger is used, use the CFK52 bit to set the K52 pin for #ADTRG.
When a programmable timer is used, since its underflow signal (8-bit timer) or comparison match B signal (16-bit
timer) serves as a trigger, set the cycle and other parameters for the programmable timer.
At i nitial reset, TS is set to "0" (software trigger).
CH2–CH0: Conve rs io n c hann el stat us (D[2 :0 ]) / A /D trigg e r regi st er (0x 4 02 42 )
Indicates the channel number (0 to 7) currently being A/D-converted.
When A/D conversion is performed in multiple channels, read this bit to identify the channel in which conversion
is underway.
At i nitial reset, CH is set to "0" (AD0).
CE2–CE0: Conversion end-chan nel setup (D[5:3] ) / A/D ch anne l regis ter (0x40243)
Sets the conversion end channel by selecting a channel number from 0 to 7.
Anal og inputs can be A/D-converted successively from the channel set using CS to the channel set using this bit in
one ope ration. I f only one channel is to be A/D converted, set the same channel number in both the CS and CE bits.
At i nitial reset, CE is set to "0" (AD0).
CS2–CS0: Conversion start-channel set up (D[2:0]) / A/D ch anne l r egister (0x40243)
Sets the conversion start channel by selecting a channel number from 0 to 7.
Anal og inputs can be A/D-converted successively from the channel set using this bit to the channel set using CE in
one ope ration. I f only one channel is to be A/D converted, set the same channel number in both the CS and CE bits.
At i nitial reset, CS is set to "0" (AD0).
IV ANALOG BLOC K: A/D CONVERTER
B-IV-2-12 EPSON S1C33L03 FUNCTION PART
ADF: Conversion-complete fla g (D3) / A/D enable registe r (0x40244)
Indicates that A/D conversion has been completed.
Read "1": Conversion completed
Read "0" : Be ing convert ed or standing by
Write: Invalid
This flag is set to "1" when A/D conversion is completed, and the converted data is stored in the data register and is
reset to "0" when the converted data is read out. When A/D conversion is performed in multiple channels, if the
next A/D conversion is completed while ADF = "1" (before the converted data is read out), the data register is
overwritten with the new conversion results, causing an overrun error to occur. Therefore, ADF must be reset by
reading out the converted data before the next A/D conversion is completed.
At i nitial reset, ADF is set to "0" (being converted or standing by).
ADE: A/D enable (D2) / A/D enable regis ter (0x 40244 )
Enables the A/D converter (readied for conversion).
Write "1": Ena bled
Write "0": Disabl ed
Read: Valid
When ADE is set to "1", the A/D converter is enabled, meaning it is ready to start A/D conversion (i.e., ready to
accept a trigger). When ADE = "0", the A/D converter is disabled, meaning it is unable to accept a trigger.
Before setting the conversion mode, start/end channels, etc. for the A/D converter, be sure to reset ADE to "0".
This helps to prevent the A/D converter from operating erratically.
At i nitial reset, ADE is set to "0" (disabled).
ADST: A/D conversi on co ntrol /stat us (D 1) / A/D en able register (0x40244)
Cont rols A/D c onversi on.
Write "1": S oftwar e trigger
Write "0": A/D conversion is st op pe d
Read: Valid
If A/D conversion is to be started by a software trigger, set ADST to "1". If any other trigger is used, ADST is
automatically set to "1" by the hardware.
ADST remains set while A/D conversi on is unde rway.
In normal mode, upon completion of A/D conversion in selected channels, ADST is reset to "0" and the A/D
conversion circuit is turned off. To stop A/D conversion during operation in continuous mode, reset ADST by
writing "0".
When ADE = "0" (A/D conversion disabled), ADST is fixed to "0", with no trigger accepted. However, when "0"
is written to ADE during A/D conversion, A/D conversion cannot be terminated.
At i nitial reset, ADST is set to "0" (A/D conversion stopped).
OWE: Overwrite-error flag (D0) / A/D enable regis ter (0x 40244 )
Indicates that the converted data has been overwritten.
Read "1": Overwritten
Read "0": Normal
Write "1": Invalid
Write "0": Flag is set
During A/D conversion in multiple channels, if the conversion results for the next channel are written to the
converted-data register (overwritten) before the converted data is read out to reset the conversion-complete flag
AD F that has been set through conversion of the preceding channel, OWE is set to "1". When ADF is reset,
because this means that the converted data has been read out, OWE is not set.
Once OW E is set to "1", it remains set until it is reset by writing "0" in the software.
At i nitial reset, OWE is set to "0" (normal).
IV ANALOG BLOC K: A/D CONVERTER
S1C33L03 FUNCTION PART EPSON B-IV-2-13
A-1
B-IV
A/D
ST1–ST0: S amp lin g- time setu p (D[1 :0 ]) / A /D samp lin g regist er (0x4 0 24 5)
Sets the analog input sampling time.
Table 2.8 Sampling Time
ST1 ST0 Sampling Time
11 9-clock pe r iod
10 7-clock pe r iod
01 5-clock pe r iod
00 3-clock pe r io d
The A/D converter input clock is used for counting.
At i nitial reset, ST is set to "11" (9-clock period).
To maintain the conversion accuracy, use ST as set by default (9-clock period).
PAD2–PAD0: A/D converter interrupt level (D[6:4]) / Serial I/F Ch.1, A/D interrupt priority register (0x4026A)
Sets the priority level of the A/D-converter interrupt in the range of 0 to 7.
At i nitial reset, PAD becomes indeterminate.
EADE: A/D co nv er ter int err up t en ab le ( D0) / Po rt i nput 4–7, cl ock tim er , A/D i nter rupt en abl e reg iste r (0x 402 77)
Enabl es or disables an interrupt to the CPU generated by the A/D converter.
Write "1": Inte rrupt enabled
Write "0": Inte rrupt disabled
Read: Valid
EA DE is an interrupt enable bit to control the A/D converter interrupt.
When EADE is set to "1", the A/D converter interrupt is enabled. When EADE is set to "0", the A/D-converter
inte rru pt is disa ble d.
At i nitial reset, EADE is set to "0" (interrupt disabled).
FADE: A/D converter interrupt factor flag (D0) / Port input 4–7, clock timer, A/D interrupt factor flag register (0x40287)
Indicates the status of an A/D-converter interrupt factor generated.
When read
Read "1": Interrupt facto r has o ccu rred
Read "0": No inte rrupt fa ctor h as o ccu rred
When written using the rese t-onl y m etho d (d ef au lt)
Write "1": Interrupt factor flag is reset
Write "0": Invalid
When written using the read /w rite m et ho d
Write "1": Interrupt flag is set
Write "0": Interrupt flag is reset
FA DE is the interrupt factor flag of the A/D converter. It is set to "1" upon completion of A/D conversion in one
channel (i.e., when the conversion results are written into the ADD register).
At t his time, if the following conditions are met, an interrupt to the CPU is generated:
1. The corresponding interrupt enable register bit is set to "1".
2. No other interrupt request of a higher prior ity has been generated.
3. The IE bit of the PSR is set to "1" (interrupts enabled).
4. The value set in the corresponding interrupt priority register is higher than the interrupt level (IL) of the CPU.
When using the interrupt factor of the A/D converter to request IDMA, note that even when the above conditions
are met, no interrupt request to the CPU is generated for the interrupt factor that has occurred. If interrupts are
enabled at the setting of IDMA, an interrupt is generated under the above conditions after the data transfer by
IDMA is completed.
IV ANALOG BLOC K: A/D CONVERTER
B-IV-2-14 EPSON S1C33L03 FUNCTION PART
The interrupt factor flag is set to "1" whenever interrupt generation conditions are met, regardless of how the
inte rrupt en ab le and in te rru pt p riority regi ste rs are set.
If the next interrupt is to be accepted after an interrupt has occurred, it is necessary that the interrupt factor flag be
reset, and that the PSR be set again (by setting the IE bit to "1" after setting the IL to a value lower than the level
indicated by the interrupt priority register, or by executing the reti instruction).
The interrupt factor flag can be reset only by writing to it in the software. Note that if the PSR is set again to accept
interrupts generated (or if the reti instruction is executed) without resetting the interrupt factor flag, the same
interrupt occurs again. Note also that the value to be written to reset the flag is "1" when the reset-only method
(RSTONLY = " 1" ) is used, and "0" wh en the r ead/wri te method (RSTONLY = "0") i s us ed.
At i nitial reset, the content of FADE becomes indeterminate, so be sure to reset it in the software.
RADE: A/D convert er I D M A reques t (D2) / Serial I /F Ch.1, A/D, port input 4–7 I D M A request regis ter (0x40293)
Specifies whether to invoke IDMA when an interrupt factor occurs.
When using the se t-o n ly m et ho d (d ef ault)
Write "1": IDMA request
Write "0": Not changed
Read: Valid
When using the read /w rite m et ho d
Write "1": IDMA request
Write "0": Inte rrupt request
Read: Valid
When RADE is set to "1", IDMA is invoked when an interrupt factor occurs, thereby performing a programmed
data transfer. If RADE is set to "0", normal interrupt processing is performed, without invoking IDMA.
For details on IDMA, refer to "IDMA (Intelligent DMA)".
At i nitial reset, RADE is set to "0" (interrupt request).
DEADE: A/D convert er I D M A enabl e (D2) / Seria l I /F Ch.1, A/D, por t inp ut 4–7 IDMA enabl e regis ter ( 0x40297)
Enables ID M A transfer by means of an interrupt factor.
When using the se t-o n ly m et ho d (d ef ault)
Write "1": IDMA enabled
Write "0": Not changed
Read: Valid
When using the read /w rite m et ho d
Write "1": IDMA enabled
Write "0": IDMA disabled
Read: Valid
If DEADE is set to "1", the IDMA request by the interrupt factor is enabled. If this bit is set to "0", the IDMA
request is disabled.
Aft er an initial reset, DEADE is set to "0" (IDMA disabled).
IV ANALOG BLOC K: A/D CONVERTER
S1C33L03 FUNCTION PART EPSON B-IV-2-15
A-1
B-IV
A/D
Pr ogramming Notes
(1) Before setting the conversion mode, start/end channels, etc. for the A/D converter, be sure to disable the A/D
converter (ADE (D2) / A/D enable register (0x40244) = "0"). A change in settings while the A/D converter is
enabled could cause it to operate erratically.
(2) The A/D converter operates only when the prescaler is operating.
When the A/D c onverter registers are set up, the prescaler must be operating. Therefore, start the prescaler
first and make sure the A/D converter is supplied with its operating clock before setting up the A/D converter
registers.
In consideration of the conversion accuracy, we recommend that the A/D converter operating clock be min.
32 kHz to max. 2 MHz.
(3) Do not start an A/D conversion when the clock supplied from the prescaler to the A/D converter is turned off,
and do not turn off the prescaler's clock output when an A/D conversion is underway, as doing so could cause
the A/D converter to operate erratically.
(4) After an initial reset, the interrupt factor flag (FADE) becomes indeterminate. To prevent generation of an
unw anted interrupt or IDMA reque st, be sure to reset this flag and register in a program.
(5) To prevent the regeneration of interrupts due to the same factor following the occurrence an interrupt, always
be sure to reset the interrupt factor flag before setting the PSR again or executing the reti instruction.
(6) When the A/D converter is set to enabled state, a current flows between AVDDE and VSS, and p ow er is
consumed, even when A/D operations are not performed. Therefore, when the A/D converter is not used, it
must be set to the disabled state (default "0" setting of ADE (D2) in the A/D enable register (0x40244)).
(7) Once A/D conversion ends, further A/D conversion will not be performed correctly if restarted within an
interval shorter than one cycle of the A/D converter operating clock set by the prescaler.
(8) When the 8-bit programmable timer 0 underflow signal or the 16-bit programmable timer 0 compare match B
signal is used as a trigger factor, the division ratio of the prescaler used by the relevant timer m ust not be set
to θ/1.
(9) ADD[9:0] (A/D conversion results) is read twice, once in the low-order 8 bits and once in the high-order 2
bits. (The hardware loads the results in this manner even if the software reads the register in 16 bits.)
In continuous mode or when two or more channels are converted successively in normal mode, ADD[9:0]
may be overwr itten with the new conversion results between reading of the low-order 8 bits and high-order 2
bits. In this case, correct conversion results cannot be obtained because the low-order 8 bits and the high-
order 2 bits are not the results of the same conversion.
At t he 1st reading of the conversion results after an A/D conversion has completed (when the conversion-
complete flag ADF is set to "1"), the overwrite-error flag OWE is set to "1" if ADD[9:0] is overwritten
between reading of the low-order 8 bits and high-order 2 bits. Note, however, that OWE is not set to "1" even
if ADD[9:0] is overwritten when the same conversion results have already been read (when ADF is reset to
"0"). This may occur when the program reads the same results twice or more for verification or other
purposes.
IV ANALOG BLOC K: A/D CONVERTER
B-IV-2-16 EPSON S1C33L03 FUNCTION PART
TH IS PAGE IS BLANK.
S1C33L03 FUNCTION PART
V DMA BLOCK
V DMA BLOCK: INTRODUCTION
S1C33L03 FUNCTION PART EPSON B-V-1-1
A-1
B-V
Intro
V-1 INTRODUCTION
The D M A Bloc k is configu red with two types of DMA controllers: HSDMA (High-Speed DMA) that has on-
chip registers for controlling DMA command information and IDMA (Intelligent DMA) that uses a memory area
for storing DMA command information.
CORE_PAD
Pads
C33_SBUS
C33 Core Block
C33 LCD Controller Block
Pads
PERI_PAD
Pads
C33_PERI
(Prescaler, 8-bit timer, 16-bit timer,
Clock timer, Serial interface, Ports)
C33 Peripheral BlockC33 Analog Block
C33_CORE
(CPU, BCU, ITC, CLG, DBG)
C33_ADC
(A/D converter)
C33 Internal Memory Block
Internal RAM
(Area 0)
Internal ROM
(Area 10)
C33 DMA Block
C33_DMA
(IDMA, HSDMA)
C33_SDRAMC
(SDRAM interface)
C33_LCDC
(LCD panel interface)
C33 SDRAM Controller Block
Figure 1.1 DMA Block
Note: In te rn al RO M is not prov ided in the S 1C33L03 .
V DMA BLOCK: INTRODUCTION
B-V-1-2 EPSON S1C33L03 FUNCTION PART
TH IS PAGE IS BLANK.
V DMA BLOCK: HSDMA (Hi gh-Speed DMA)
S1C33L03 FUNCTION PART EPSON B-V-2-1
A-1
B-V
HSDMA
V-2 HSDMA (High-Speed DMA)
Functional Outline of HSDMA
The DMA Block contains four channels of HSDMA (High-Speed DMA) circuits that support dual-address transfer
and single-address transfer methods.
Since the control registers required for the DMA function are built into the chip, DMA requests for data transfer
can be responded to instantaneously.
Dual-address transfer
In this m et ho d, a so urce address and a d estina tion ad dress for DMA tr ansfe r can b e spec ifi ed and a D M A
transfer is performed in two phases. The first phase reads data at the source address into the on-chip
temporary register. The second phase writes the temporary register data to the destination address.
Unlike IDMA (Intelligent DMA), which has transfer information in memory, this DMA method does not
support a DMA link function but allows high-speed data transfers because it is not necessary to read transfer
information from a memory.
Memory, I/O
Data bus
Address bus
BCU
Memory, I/O
Data transfer
(1)(2)
SourceDestination
High-speed
DMA
DMA request
End of DMA
#DMAREQx
#DMAENDx
Figur e 2.1 Dual-Address Transfer Method
Single-addr ess transfer
In this method, data transfers that are normally accomplished by executing data read and write operations
back-to-back are executed on the external bus collectively at one time, thus further speeding up the transfer
operation. The #DMAACKx and #D M A ENDx signals are used to control data transfer.
Unlike dual- address transfer, th is metho d does not al lo w memo ry to memo ry d ata tran sfe r but d ata tran sfe rs
can be performed in minimu m cycles.
High-speed
DMA External I/O
Data bus
Address bus
BCU Memory
I/O
Bus control signals
DMA request
DMA reception
End of DMA
#RD/#WR
#DMAREQx
#DMAACKx
#DMAENDx
Data transfer
Note:
Single-address mode
does not allow data transfer
between memory devices.
Figur e 2.2 Single-Address Transfer Method
Notes: •Channels 0 to 3 are configu red in the same way an d have the sam e functionality. Signal an d
control bit names ar e assigned ch anne l numbe rs 0 to 3 to distin guish them from other channe ls.
In this manual, however, channe l numbers 0 to 3 are desi gnated with an "x" except where they
must be di stinguished, as the explanation is the same for al l channe ls.
•The single-address transfer method does not allow data tran sf er to/fr om the SDRA M.
V DMA BLOCK: HSDMA (Hi gh-Speed DMA)
B-V-2-2 EPSON S1C33L03 FUNCTION PART
I/O Pins of HSDMA
Table 2.1 lists t he I/O pins used for H SDMA.
Table 2.1 I/O Pins of HSDMA
Pin name I/O Function Function select bit
K50/#DMAREQ0 I Input port / High-speed DMA request 0 CFK50(D0)/K5 function select register(0x402C0)
K51/#DMAREQ1 I Input port / High-speed DMA request 1 CFK51(D1)/K5 function select register(0x402C0)
K53/#DMAREQ2 I Input port / High-speed DMA request 2 CFK53(D3)/K5 function select register(0x402C0)
K54/#DMAREQ3 I Input port / High-speed DMA request 3 CFK54(D4)/K5 function select register(0x402C0)
P04/SIN1/
#DMAACK2 I/O I/O port / Serial IF Ch.1 data input /
#DMAACK2 output (Ex) CFEX4(D4)/Port function extension register(0x402DF)
P05/SOUT1/
#DMAEND2 I/O I/O port / Serial IF Ch.1 data output /
#DMAEND2 output (Ex) CFEX5(D5)/Port function extension register(0x402DF)
P06/#SCLK1/
#DMAACK3 I/O I/O port / Serial IF Ch.1 clock input/output /
#DMAACK3 output (Ex) CFEX6(D6)/Port function extension register(0x402DF)
P07/#SRDY1/
#DMAEND3 I/O I/O port / Serial IF Ch.1 ready input/output /
#DMAEND3 output (Ex) CFEX7(D7)/Port function extension register(0x402DF)
P15/EXCL4/
#DMAEND0 I/O I/O port / 16-bit timer 4 event counter input (I) /
#DMAEND0 output (O) CFP15(D5)/P1 function select register(0x402D4)
P16/EXCL5/
#DMAEND1 I/O I/O port / 16-bit timer 5 event counter input (I) /
#DMAEND1 output (O) CFP16(D6)/P1 function select register(0x402D4)
P32/#DMAACK0 I/O I/O port / #DMAACK0 output CFP32(D2)/P3 function select register(0x402DC)
P33/#DMAACK1 I/O I/O port / #DMAACK1 output CFP33(D3)/P3 function select register(0x402DC)
(I): Input mode, (O): Output mode, (Ex): Extend ed f u nct ion
#DMAREQx (DMA request input pin)
This pin is used to input a DMA request signal from an external peripheral circuit. One data transfer
operation is performed by this trigger (either the rising edge or the falling edge of the signal can be selected).
The #DMAREQ0 to #DMAREQ3 pins cor respond to channel 0 to channel 3, respectively.
In addition to this external input, software trigger or an interrupt factor can be selected for the HSDMA
trigger factor using the register in the interrupt controller.
#DM AACKx (D M A acknow ledge signal output pin for single-address mode)
This signal is output to indicate that a DMA request has been acknowledged by the DMA controller.
In single-address mode, the I/O device that is the source or destination of transfer outputs data to the external
bus or takes in data from the external data synchronously with this signal.
The #D MAACK0 to #D MAACK3 pins c orrespo nd to channel 0 to channel 3, respectively.
This signal is not output in dual-address mode.
#DMAENDx (End-of-transfer si gnal output pin)
This signal is output to indicate that the number of data transfer operations that is set in the control register
have been com pleted. The #DMAEND0 to #DMAEND3 pins correspond to channel 0 to channel 3,
respectively.
Method for setting HSDMA I/O pins
As shown in Table 2.1, the pins used for HS D MA are shared with input ports and I/O ports. At cold start, all
of these are set as input and I/O port pins (function select register = "0"). According to the signals to be used,
set the corresponding pin function select bit by writing "1". At hot start, the register retains the previous status
before a reset.
The #D MAEND3, #DMAACK3, #DMAEND2 and #DMAACK2 outputs are the exten ded functions of the
P04 to P07 por ts. When using these signals, the extended function bit (CFEX[7:4]) must be set to "1".
In addition, setup of the #DMAEND0 pin or #D M A END1 pin further requires sett ing the I/O por t's I/O
control bit IOC15 (D5) or IOC16 (D6) / P1 I/O control register (0x402D6) by writing "1" in order to direct
the pin for output. If this pin is directed for input, it functions as a 16-bit programmable timer's event counter
input and cannot be used to output the #DMAENDx signal. At cold start, this pin is set for input. At hot start,
it retains the previous status.
V DMA BLOCK: HSDMA (Hi gh-Speed DMA)
S1C33L03 FUNCTION PART EPSON B-V-2-3
A-1
B-V
HSDMA
Programming Control Inf orm ation
The HSDMA opera tes according to the control information set in the registers.
Note that some control bits change their functions according to the address mode.
The following explains how to set the contents of control information. Before using HSDMA, make each the
settings described below .
Setting the Registers in Dual-Address Mode
Make sure that the HSDMA channel is disabled (HSx_EN = "0") before setting the control information.
Address mode
The add ress mode select bit DUALMx should be set to "1" (dual-address mode). This bit is set to "0" (single-
address mode) at initial reset.
DUALM0: Ch. 0 address mode selection (DF) / HSDMA Ch. 0 control register (0x48222)
DUALM1: Ch. 1 address mode selection (DF) / HSDMA Ch. 1 control register (0x48232)
DUALM2: Ch. 2 address mode selection (DF) / HSDMA Ch. 2 control register (0x48242)
DUALM3: Ch. 3 address mode selection (DF) / HSDMA Ch. 3 control register (0x48252)
Transfer m o de
A trans fer mode should be set using the DxMOD[1:0] bits.
D0MOD[1:0]: Ch. 0 transfer mode (D[F:E]) / HSDMA Ch. 0 high-order destination addre ss set-up register (0x4822A)
D1MOD[1:0]: Ch. 1 transfer mode (D[F:E]) / HSDMA Ch. 1 high-order destination addre ss set-up register (0x4823A)
D2MOD[1:0]: Ch. 2 transfer mode (D[F:E]) / HSDMA Ch. 2 high-order dest i na tio n addre ss set-up register (0x4824A)
D3MOD[1:0]: Ch. 3 transfer mode (D[F:E]) / HSDMA Ch. 3 high-order destination addre ss set-up register (0x4825A)
The following three transfer modes are available:
Single t ransfer mode (DxM OD = "00" , default)
In this mode, a transfer operation invoked by one trigger is completed after transferring one unit of data of the
size set by DATSIZEx. If data transfer need to be performed a number of times as set by the transfer counter,
an equal number of triggers are required.
Success ive transfer mode (DxM O D = "01")
In this mode, data transfer operations are performed by one trigger a number of times as set by the transfer
counter. The transfer counter is decremented to 0 each time data is transferred.
Block transfer mode (DxMOD = "10" )
In this mode, a transfer operation invoked by one trigger is completed after transferring one block of data of
the size set by BLKLENx. If a block transfer need to be performed a number of times as set by the transfer
counter, an equal number of triggers are required.
Transfer data size
The DATSI ZEx bit is used to set the unit size of data to be transferred.
A hal f-word size (16 bits) is assumed if this bit is "1" and a byte size (8 bits) is assumed if this bit is "0"
(default).
DATSIZE0: Ch. 0 transfer data size (DE) / HSDMA Ch. 0 high-order source ad dress s et-up reg ister ( 0x4 8226 )
DATSIZE1: Ch. 1 transfer data size (DE) / HSDMA Ch. 1 high-order source ad dress s et-up reg ister ( 0x4 8236 )
DATSIZE2: Ch. 2 transfer data size (DE) / HSDMA Ch. 2 high-order source ad dress s et-up reg ister ( 0x4 8246 )
DATSIZE3: Ch. 3 transfer data size (DE) / HSDMA Ch. 3 high-order source ad dress s et-up reg ister ( 0x4 8256 )
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B-V-2-4 EPSON S1C33L03 FUNCTION PART
Block length
When using bl ock transfer mode (DxMOD = "10"), the data block length (in units of DA TSIZE x) should be
set using the BLKLENx[7:0] bits.
BLK LEN0[ 7:0]: Ch. 0 block length (D[7:0]) / HSDMA Ch. 0 transfer counter register (0x48220)
BL KL EN1[ 7:0]: Ch. 1 block len gth (D[7:0]) / HSDMA Ch. 1 tra nsfer counter register (0x482 30)
BLK LEN2[ 7:0]: Ch. 2 block length (D[7:0]) / HSDMA Ch. 2 transfer counter register (0x48240)
BLK LEN3[ 7:0]: Ch. 3 block length (D[7:0]) / HSDMA Ch. 3 transfer counter register (0x48250)
Note: The bl ock size thus set is decremented ac cording to t h e transfers performed. If the block size is
set to 0, i t i s decremented to all Fs by the first transfer performed. This means that you have set
the maximum value that is determined by the number of bits available.
In single transfer and successive transfer modes, these bits are used as the bits7–0 of the transfer counter.
Transfer counter
Block transfe r mode
In block transfer mode, up to 16 bit s of transfer count can be specified.
TC 0_L[7:0]: Ch. 0 tra nsfer counter [7:0] (D[F:8]) / HSDMA Ch. 0 transfer counter register (0x48220)
TC 1_L[7:0]: Ch. 1 tra nsfer counter [7:0] (D[F:8]) / HSDMA Ch. 1 transfer counter register (0x48230)
TC 2_L[7:0]: Ch. 2 tra nsfer counter [7:0] (D[F:8]) / HSDMA Ch. 2 transfer counter register (0x48240)
TC 3_L[7:0]: Ch. 3 transfer counter [7:0] (D[F:8]) / HSDMA Ch. 3 transfer counter register (0x48250)
TC 0_H[ 7:0]: Ch. 0 tra nsfer counter [15:8] (D[7:0]) / H SD MA Ch. 0 control register (0x48222)
TC 1_H[ 7:0]: Ch. 1 tra nsfer counter [15:8] (D[7:0] ) / HS D M A Ch. 1 control register (0x48232)
TC 2_H[ 7:0]: Ch. 2 tra nsfer counter [15:8] (D[7:0]) / H SD MA Ch. 2 control register (0x48242)
TC 3_H[ 7:0]: Ch. 3 tra nsfer counter [15:8] (D[7:0]) / H SD MA Ch. 3 control register (0x48252)
Single transf er and succ essive transfer modes
In single transfer and successive transfer modes, up to 24 bits of transfer count can be specified.
BLKLEN0[7:0]: Ch. 0 transfer counter [7:0] (D[7:0]) / HSDMA Ch.0 transfer counter register (0x48220)
BLKLEN1[7:0]: Ch. 1 transfer counter [7:0] (D[7:0]) / HSDMA Ch.1 transfer counter register (0x48230)
BLKLEN2[7:0]: Ch. 2 transfer counter [7:0] (D[7:0]) / HSDMA Ch.2 transfer counter register (0x48240)
BLKLEN3[7:0]: Ch. 3 transfer counter [7:0] (D[7:0]) / HSDMA Ch.3 transfer counter register (0x48250)
TC 0_L[7:0]: Ch. 0 transfer counter [15:8] (D[F:8]) / HSDMA Ch. 0 transfer counter register (0x48220)
TC 1_L[7:0]: Ch. 1 tra nsfer counter [15:8] (D[F:8]) / HSDMA Ch. 1 transfer counter register (0x48230)
TC 2_L[7:0]: Ch. 2 tra nsfer counter [15: 8] (D[F :8]) / H SD MA Ch. 2 tran sf er coun ter registe r (0x48240 )
TC 3_L[7:0]: Ch. 3 tra nsfer counter [15:8] (D[F:8]) / HSDMA Ch. 3 transfer counter register (0x48250)
TC0_H[7:0]: Ch. 0 transfer counter [23:16] (D[7:0]) / HSDMA Ch. 0 control register (0x48222)
TC1_H[7:0]: Ch. 1 transfer counter [23:16] (D[7:0]) / HSDMA Ch. 1 control register (0x48232)
TC2_H[7:0]: Ch. 2 transfer counter [23:16] (D[7:0]) / HSDMA Ch. 2 control register (0x48242)
TC3_H[7:0]: Ch. 3 transfer counter [23:16] (D[7:0]) / HSDMA Ch. 3 control register (0x48252)
Note: The transfer count thus set is decremented acco rding to the transfers performed. If the transfer
count is set to 0, it is de crem ented to all Fs by the first transfer performed. This means that you
have set the maximum value that is determined by the number of bi ts avai lable.
Source and destination addresses
In dual-address mode, a source address and a destination address for DMA transfer can be specified.
S0ADRL[15:0]: Ch. 0 source address [15:0] (D[F:0]) / Ch. 0 low-ord er so urc e ad dre ss set-up register (0x48224)
S1ADRL[15:0]: Ch. 1 source address [15:0] (D[F:0]) / Ch. 1 low-ord er so urc e ad dre ss set-up register (0x48234)
S2ADRL[15:0]: Ch. 2 source address [15:0] (D[F:0]) / Ch. 2 low-ord er so urc e ad dre ss set-up register (0x48244)
S3ADRL[15:0]: Ch. 3 source address [15:0] (D[F:0]) / Ch. 3 low-ord er so urc e ad dre ss set-up register (0x48254)
S0ADRH[11:0]: Ch. 0 source addre ss [27:16] (D[B:0]) / Ch. 0 high-order source address set-up register (0x48226)
S1ADRH[11:0]: Ch. 1 source addre ss [27:16] (D[B:0]) / Ch. 1 high-order source address set-up register (0x48236)
S2ADRH[11:0]: Ch. 2 source addre ss [27:16] (D[B:0]) / Ch. 2 high-order source address set-up register (0x48246)
S3ADRH[11:0]: Ch. 3 source addre ss [27:16] (D[B:0]) / Ch. 3 high-order source address set-up register (0x48256)
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D0ADRL[15:0]: Ch. 0 destination address [15:0] (D[F:0]) / Ch. 0 low-or de r d esti na tio n a dd re ss set- up reg ist e r (0 x4 8228 )
D1ADRL[15:0]: Ch. 1 destination address [15:0] (D[F:0]) / Ch. 1 low-or de r d esti na t ion a dd re ss se t- up reg ist e r (0 x4 82 38)
D2ADRL[15:0]: Ch. 2 destination address [15:0] (D[F:0]) / Ch. 2 low-or de r d esti na tio n a dd re ss set- up reg ist e r (0 x4 8248 )
D3ADRL[15:0]: Ch. 3 destination address [15:0] (D[F:0]) / Ch. 3 low-or de r d esti na t ion a dd re ss se t- up r egister (0x48258)
D0ADRH[11:0]: Ch. 0 destination address [27:16] (D [B:0 ]) / Ch. 0 h igh-orde r dest inatio n a ddre s s s et- up register (0x4 822A)
D1ADRH[11:0]: Ch. 1 destination address [27:16] (D [B:0 ]) / Ch. 1 h igh-orde r dest inatio n a ddre s s s et- up register (0x4 823A)
D2ADRH[11:0]: Ch. 2 destination address [27:16] (D [B:0 ]) / Ch. 2 h igh-orde r dest inatio n a ddre s s s et- up register (0x4 824A)
D3ADRH[11:0]: Ch. 3 destination address [27:16] (D [B:0 ]) / Ch. 3 h igh-orde r dest inatio n a ddre s s s et- up register (0x4 825A)
Address increment/decremen t co ntrol
The sou rce and/or destination addresses can be incremented or decremented when one data transfer is
com pl eted. T he SxIN [1 :0 ] bits (f or so urce addres s) and D xI N[ 1:0 ] b its (for destina tion ad dress) are used to
set this function.
S0IN[1:0]: Ch. 0 source address cont rol (D[D:C]) / Ch. 0 high-orde r source address set-up register (0x4 8226 )
S1IN[1:0]: Ch. 1 source address cont rol (D[D:C]) / Ch. 1 high-orde r source address set-up register (0x4 8236 )
S2IN[1:0]: Ch. 2 source address control (D[D: C ]) / Ch. 2 high-order source ad dress set-up register (0x48246)
S3IN[1:0]: Ch. 3 source address cont rol (D[D:C]) / Ch. 3 high-orde r source address set-up register (0x4 8256 )
D0IN[1:0]: Ch. 0 destination address cont rol (D[ D :C]) / Ch. 0 high- order destination address set-u p register (0x4822A )
D1IN[1:0]: Ch. 1 destination address cont rol (D[ D :C]) / Ch. 1 high- order destination address set-u p register (0x4823A )
D2IN[1:0]: Ch. 2 destination address cont rol (D[ D :C]) / Ch. 2 high- order dest inati on ad dress set-up re gister (0x4824A)
D3IN[1:0]: Ch. 3 destination address cont rol (D[ D :C]) / Ch. 3 high- order destination address set-u p register (0x4825A )
SxIN/DxIN = "00": address fixed (def ault)
The add ress is not changed by a data transfer performed. Even when transferring multiple data, the transfer
data is always read/write from/to the same address.
SxIN/DxIN = "01": address decrem ented without initialization
The add ress is decremented by an amount equal to the data size set by DATSIZEx when one data transfer is
completed. The address that has been decremented during transfer does not return to the initial value.
SxIN/DxIN = "10": address incremented with ini ti alizatio n
If this function is selected in single and successive transfer modes, the address is incremented by an amount
equal to the data size set by DATSIZEx when one data transfer is completed. The address that has been
incremented during transfer does not return to the initial value.
In block transfer mode too, the address is incremented when one data unit is transferred. However, the
address that has been incremented during a block transfer recycles returns to the initial value when the block
transfer is completed.
SxIN/DxIN = "11": address incremented without i nitia li zation
The add ress is incremented by an amount equal to the data size set by DATSIZEx when one data transfer is
completed. The address that has been incremented during transfer does not return to the initial value.
V DMA BLOCK: HSDMA (Hi gh-Speed DMA)
B-V-2-6 EPSON S1C33L03 FUNCTION PART
Setting the Registers in Single-Address Mode
Make sure that the HSDMA channel is disabled (HSx_EN = "0") before seffing the control information.
Address mode
The add ress mode select bit DUALMx should be set to "0" (single-address mode). This bit is set to "0" at
initial re set.
Transfer m o de
A trans fer mode should be set using the DxMOD[1:0] bits.
• Single transfer mode (DxMOD = "00", def ault)
• Successive transfer mode (DxMOD = "01")
• Block transfer mode (DxMOD = "10")
Refer to the explanation in "Setting the Registers in Dual-Address Mode".
Dir ecti o n of transfer
The direction of data t ransfer should be set using DxDIR.
D0DIR: Ch. 0 transfer direction control (DE) / HSDMA Ch. 0 control register (0x48222)
D1DIR: Ch. 1 transfer direction control (DE) / HSDMA Ch. 1 control register (0x48232)
D2DIR: Ch. 2 transfer direction control (DE) / HSDMA Ch. 2 control register (0x48242)
D3DIR: Ch. 3 transfer direction control (DE) / HSDMA Ch. 3 control register (0x48252)
Memory wr ite operations (data transfer from I/O device to memory) are specified by writing "1" and memory
read operations (data transfer from memory to I/O device) are specified by writing "0".
Transfer data size
The DATSI ZEx bit is used to set the unit size of data to be transferred.
A hal f-word size (16 bits) is assumed if this bit is "1" and a byte size (8 bits) is assumed if this bit is "0"
(default).
Block length
When using bl ock transfer mode (DxMOD = "10"), the data block length (in units of DATSIZEx) should be
set using the BLKLENx[7:0] bits.
In single transfer and successive transfer modes, BLKLENx[7:0] is used as the bits7–0 of the transfer
counter.
Transfer counter
Block transfe r mode
In block transfer mode, up to 16 bits of transfer count can be specified us ing TCx_L[7: 0] and TCx_H[7:0].
Single transf er and succ essive transfer modes
In single transfer and successive transfer modes, up to 24 bits of transfer count can be specified using
BL KL ENx[ 7:0], TCx_L[7: 0] and TC x_H[7:0].
Memory address
In single-address mode, SxADRL[15:0] and SxADRH[11:0] are used to specify a memory address.
S0ADRL[15:0]: Ch. 0 memory address [15:0] (D[F:0]) / Ch. 0 low-order source ad dress set- up register (0x48224)
S0ADRH[11:0]: Ch. 0 memory addre ss [27:16] (D[B:0]) / Ch. 0 high-order source address set-up register (0x48226)
S1ADRL[15:0]: Ch. 1 memory address [15:0] (D[F:0]) / Ch. 1 low-order source ad dress set- up register (0x48234)
S1ADRH[11:0]: Ch. 1 memory addre ss [27:16] (D[B:0]) / Ch. 1 high-order source address set-up register (0x48236)
S2ADRL[15:0]: Ch. 2 memory address [15:0] (D[F:0]) / Ch. 2 low-order source ad dress set- up register (0x48244)
S2ADRH[11:0]: Ch. 2 memory addre ss [27:16] (D[B:0]) / Ch. 2 high-order source address set-up register (0x48246)
S3ADRL[15:0]: Ch. 3 memory address [15:0] (D[F:0]) / Ch. 3 low-order source address set-up regist er (0x48254)
S3ADRH[11:0]: Ch. 3 memory addre ss [27:16] (D[B:0]) / Ch. 3 high-order source address set-up register (0x48256)
V DMA BLOCK: HSDMA (Hi gh-Speed DMA)
S1C33L03 FUNCTION PART EPSON B-V-2-7
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HSDMA
In single-address mode, data transfer is performed between the memory connected to the system interface and
an external I/O device. The I/O device is accessed directly by the #DMAACKx signal, so it is unnecessary to
specify an address. DxADRL[15:0] and DxADRH[11:0] are not used in single-address mode.
Address increm en t/ d ecrement cont ro l
The me mory address es can be incremented or decremented when one data transfer is completed. SxIN[1:0] is
used to set this function.
S0IN[1:0]: Ch. 0 memory addre ss co ntro l (D[D:C]) / Ch. 0 high-order source addre ss set-up register (0x48226)
S1IN[1:0]: Ch. 1 memory addre ss co ntro l (D[D:C]) / Ch. 1 high-order source addre ss set-up register (0x48236)
S2IN[1:0]: Ch. 2 memory addre ss co ntro l (D[D:C]) / Ch. 2 high-order source addre ss set-up register (0x48246)
S3IN[1:0]: Ch. 3 memory addre ss co ntro l (D[D:C]) / Ch. 3 high-order source addre ss set-up register (0x48256)
SxIN = "00": address fixed (default)
SxIN = "01": address decremented without initialization
SxIN = "10": address incremented with initialization
SxIN = "11": address incremented without initialization
Refer to the explanation in "Setting the Registers in Dual-Address Mode".
DxIN[1:0] is not used in single-address mode.
Enabling/Disabling DMA T ransfer
The HSDMA transfer is e nabled by writing "1" to the enable bit HSx_EN.
HS0_EN: Ch . 0 enable ( D 0) / Ch. 0 enable register (0x4822C)
HS1_EN: Ch . 1 enable ( D 0) / Ch. 1 enable register (0x4823C)
HS2_EN: Ch . 2 enable ( D 0) / Ch. 2 enable register (0x4824C)
HS3_EN: Ch . 3 enable ( D 0) / Ch. 3 enable register (0x4825C)
However, the contr ol information must always be set correctly before enabling a DMA transfer.
Note that the control information cannot be set when HSx_EN = "1".
When HSx_EN is set to "0", HSDMA requests are no longer accepted.
When a DMA transfer is completed (transfer counter = 0), HSx_EN is reset to "0" to disable the following trigger
inputs.
V DMA BLOCK: HSDMA (Hi gh-Speed DMA)
B-V-2-8 EPSON S1C33L03 FUNCTION PART
Trigger Factor
A HSDMA tigger factor can be selected from a m ong 13 types using the H SDMA trigger set-up register for each
channel. This function is supported by the interrupt controller.
HSD0S[3:0]: Ch. 0 trigger se t-u p (D[3 :0 ]) / H SD MA Ch. 0/1 tr igg er set-u p re gi ster (0x4 02 98)
HSD1S[3:0]: Ch. 1 trigger set-u p (D[7 :4 ]) / H SD MA Ch. 0/1 tr igg er set-u p re gi ster (0x4 02 98)
HSD2S[3:0]: Ch. 2 trigger set-u p (D[3 :0 ]) / H SD MA Ch. 2/3 tr igg er set-u p re gi ster (0x4 02 99)
HSD3S[3:0]: Ch. 3 trigger set-u p (D[7 :4 ]) / H SD MA Ch. 2/3 tr igg er set-u p re gi ster (0x4 02 99)
Table 2.2 shows t he setting value and the corresponding trigger factor.
Table 2.2 HSDMA Trigger Factor
Value Ch.0 trigger factor Ch.1 trigger factor Ch.2 trigger factor Ch.3 trigger factor
0000 Software trigger Software trigger Software trigger Software trigger
0001 K50 port input (falling edge) K51 port input (falling edge) K53 port input (falling edge) K54 port input (falling edge)
0010 K50 port input (rising edge) K51 port input (rising edge) K53 port input (rising edge) K54 port input (rising edge)
0011 Port 0 input Port 1 input Port 2 input Port 3 input
0100 Port 4 input Port 5 input Port 6 input Port 7 input
0101 8-bit timer 0 underflow 8-bit timer 1 underflow 8-bit timer 2 underflow 8-bit timer 3 underflow
0110 16-bit timer 0 compare B 16-bit timer 1 compare B 16-bit timer 2 compare B 16-bit timer 3 compare B
0111 16-bit timer 0 compare A 16-bit timer 1 compare A 16-bit timer 2 compare A 16-bit timer 3 compare A
1000 16-bit timer 4 compare B 16-bit timer 5 compare B 16-bit timer 4 compare B 16-bit timer 5 compare B
1001 16-bit timer 4 compare A 16-bit timer 5 compare A 16-bit timer 4 compare A 16-bit timer 5 compare A
1010 Serial I/F Ch.0 Rx buffer full Serial I/F Ch.1 Rx buffer full Serial I/F Ch.0 Rx buffer full Serial I/F Ch.1 Rx buffer full
1011 Serial I/F Ch.0 Tx buffer empty Serial I/F Ch.1 Tx buffer empty Serial I/F Ch.0 Tx buffer empty Serial I/F Ch.1 Tx buffer empty
1100 A/D conversion completion A/D conversion completion A/D conversion completion A/D conversion completion
By selec ting an interrupt factor with the HSDMA trigger set-up register, the HSDMA channel is invoked when the
selected interrupt factor occurs. The interrupt control bits (interrupt factor flag, interrupt enable register, IDMA
requ es t regi ster, in te rru pt p rio rity regi ste r) d o not af fe ct th is in vo ca tion. The inte rru pt fa cto r th at invo ke s HSDMA
sets the interrupt factor flag. and HSDMA does not reset the flag. Consequently, when the DMA transfer is
completed (even if the transfer counter is not 0), an interrupt request to the CPU will be generated if the interrupt
has been enabled. To generate an interrupt only when the transfer counter reaches 0, disable the interrupt by the
interrupt factor that invokes HSDMA and use the HSDMA transfer completion interrupt.
When so ftware trigger is selected, the HSDMA channel can be invoked by writing "1" to the HSTx bit.
HST0: Ch. 0 sof tware trigger (D0) / HSDMA software trigger register (0x4029A)
HST1: Ch. 1 sof tware trigger (D1) / HSDMA software trigger register (0x4029A)
HST2: Ch. 2 sof tware trigger (D2) / HSDMA software trigger register (0x4029A)
HST3: Ch. 3 sof tware trigger (D3) / HSDMA software trigger register (0x4029A)
When the selected trigger factor occurs, the trigger flag is set to "1" to invoke the HSDMA channel.
The HSDMA star ts a DMA trans fer if it has been enabled and the trigger flag is cleared by the hardware at the
same time. This makes it possible to queue the HSDMA triggers that have been generated.
The trigger flag can be read and cleared using the HSx_TF bit.
HS0_TF: Ch. 0 trigger flag status/clear (D0) / Ch. 0 trigger flag register (0x4822E)
HS1_TF: Ch. 1 trigger flag stat us/clear ( D 0) / Ch. 1 trigger flag register (0x4823E)
HS2_TF: Ch. 2 trigger flag stat us/clear ( D 0) / Ch. 2 trigger flag register (0x4824E)
HS3_TF: Ch. 3 trigger flag stat us/clear ( D 0) / Ch. 3 trigger flag register (0x4825E)
By writing "1" to this bit, the set trigger flag can be cleared if the DMA transfer has not been started.
When this bit is read, "1" indicates that the flag is set and "0" indicates that the flag is cleared.
V DMA BLOCK: HSDMA (Hi gh-Speed DMA)
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Operation of HSDMA
An HSDMA c hannel s ta rts data t ra nsfer by th e selected trigger factor.
Make sure that transfer conditions and a trigger factor are set and the HSDMA channel is enabled before starting a
DMA transfer.
Operation in Dual-Address Mode
In dual-address mode, both the source and destination addresses are accessed according to the bus condition set by
the BCU.
HSDMA ha s three transfer modes, in each of which data transfer operates differently. The following describes the
operation of HS D M A in each transfer mode.
Single transfer mode
The c hannel f or which DxMOD i n control information is set to "00" operates in single transfer mode. In this
mode , a transfer operation invoked by one trigger is completed after transferring one data unit of the size set
by D ATSIZE x. If a data transfer needs to be perform ed a num ber of times as set by the transfer count er, an
equal number of triggers are required.
The ope ration of HSDMA in single transfer mode is shown by the flow chart in Figure 2.3.
START
END
Data read from source
(1 byte or 1 half word)
Clear trigger flag HSx_TF
to accept next trigger
Clear HSDMA enable bit
HSx_EN
Data write to destination
(1 byte or 1 half word)
Transfer counter - 1
Set interrupt factor flag
FHDMx
Transfer
counter = 0 N
Y
Increment/decrement
address ∗
∗: according to SxIN/DxIN
settings
Figur e 2.3 Operation Flow in Single Transfer Mode
(1) When a trigger is accepted, the trigger flag HSx_TF is cleared and then data of the size set in the control
information is read from the source address.
(2) The read data is written to the destination address.
(3) The addresses are incremented or decremented according to the SxIN/DxIN settings.
(4) The transfer counter is decremented.
(5) The HSDMA enable bit HSx_EN is cleared and HSDMA interrupt factor flag in ITC is set when the
transfer counter reaches 0 (when DINTENx = "1").
V DMA BLOCK: HSDMA (Hi gh-Speed DMA)
B-V-2-10 EPSON S1C33L03 FUNCTION PART
Successive transfer mode
The c hannel f or which DxMOD i n control information is set to "01" operates in successive transfer mode. In
this mode, a data transfer is performed by one trigger a number of times as set by the transfer counter. The
transfer counter is decremented to "0" by one transfer executed.
The ope ration of HSDMA in successive transfer mode is shown by the flow chart in Figure 2.4.
START
END
Transfer counter - 1
Transfer
counter = 0
N
Y
Increments/decrements
address ∗
∗: according to SxIN/DxIN
settings
Data read from source
(1 byte or 1 half word)
Data write to destination
(1 byte or 1 half word)
Clear trigger flag HSx_TF
to accept next trigger
Clear HSDMA enable bit
HSx_EN
Set interrupt factor flag
FHDMx
Figur e 2.4 Operation Flow in Successive Transfer Mode
(1) When a trigger is accepted, the trigger flag HSx_TF is cleared and then data of the size set in the control
information is read from the source address.
(2) The read data is written to the destination address.
(3) The addresses are incremented or decremented according to the SxIN/DxIN settings.
(4) The transfer counter is decremented.
(5) Steps (1) to (4) are repeated until the transfer counter reaches 0.
(6) The HSDMA enable bit HSx_EN is cleared and HSDMA interrupt factor flag in ITC is set when the
transfer counter reaches 0 (when DINTENx = "1").
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HSDMA
Block transfer mode
The c hannel f or which DxMOD i n control information is set to "10" operates in block transfer mode. In this
mode , a transfer operation invoked by one trigger is completed after transferring one bloc k of dat a of the size
set by BLKLENx. I f a block transfer needs to be performed a number of times as set by the transfer counter,
an equal number of triggers are required.
The ope ration of HSDMA in block transfer mode is shown by the flow c hart in Figure 2. 5.
START
END
Block size - 1
Restores initial values to
block size and address ∗
Block
size = 0
1-block transfer
N
Y
Transfer counter - 1
Transfer
counter = 0 N
Y
∗: according to SxIN/DxIN
settings
Data read from source
(1 byte or 1 half word)
Data write to destination
(1 byte or 1 half word)
Increments/decrements
address ∗
∗: according to SxIN/DxIN
settings
Clear trigger flag HSx_TF
to accept next trigger
Clear HSDMA enable bit
HSx_EN
Set interrupt factor flag
FHDMx
Figur e 2.5 Operation Flow in Block Transfer Mode
(1) When a trigger is accepted, the trigger flag HSx_TF is cleared and then data of the size set in the control
information is read from the source address.
(2) The read data is written to the destination address.
(3) The address is incremented or decremented and BLKLENx is decremented.
(4) Steps (1) to (3) are repeated until BLKLEN reaches 0.
(5) If SxIN or DxIN is "10", the address is recycled to the initial value.
(6) The transfer counter is decremented.
(7) The HSDMA enable bit HSx_EN is cleared and HSDMA interrupt factor flag in ITC is set when the
transfer counter reaches 0 (when DINTENx = "1").
V DMA BLOCK: HSDMA (Hi gh-Speed DMA)
B-V-2-12 EPSON S1C33L03 FUNCTION PART
Operation in Single-Address Mode
The ope ration of each transfer mode is almost the same as that of dual-address mode (see the previous section).
However, data read/write op eration is performed simultaneously in single-address mode.
The following explains the data transfer operation different from dual-address mode.
#DM AACKx sig n al output and bus operation
When the HSDMA circuit accepts the DMA request, it outputs a low-level pulse from the #DMAACKx pin
and starts bus operation for the memory at the same time.
The con tents of this bus operation are as follows:
•Data tran sf er fr om I/O d evi c e to me mo ry
The add ress that has been set in the memory address register is output to the address bus.
A wri te operation is performed under the interface conditions set on the area to which the memory at the
destination of transfer belongs. The data bus is left floating.
The external I/O device outputs the transfer data onto the data bus using the #DMAACKx signal as the read
signal. The memory takes in this data using the write signal.
•Data transfer from m e mo ry to an I/ O device
The add ress that has been set in the memory address register is output to the address bus.
A read operation is performed under the interface conditions set on the area to which the memory at the
source of transfer belongs.
The me mory outputs the transfer data onto the data bus using the read signal.
The external I/O device takes in the data from the data bus using the #DMAACKx signal as the write signal.
If the transfer data size is 16 bits and the I/O device is an 8-bit device, two bus operations are performed.
Otherwise, transfer is completed in one bus operation.
#DMAENDx signal output
When the transfer counter reaches 0, the end-of-transfer signal is output from the #DMAENDx pin indicating
that a specified number of transfers has been completed. At the same time, the interrupt factor for the
completion of HSDMA is gen er ated.
V DMA BLOCK: HSDMA (Hi gh-Speed DMA)
S1C33L03 FUNCTION PART EPSON B-V-2-13
A-1
B-V
HSDMA
Timing Chart
Dual-address mode
(1) S RAM
Example: W hen 2 (R D )/1 (WR) wai t c ycles are inserted
BCLK
A[23:0]
#CE(src)
#CE(dst)
#RD
#WRH/#WRL
#DMAEND
;;;
;;;
source address destination address
Read cycle Write cycle
Figur e 2.6 #DMAEND Signal Output Timing (SRAM)
(2) D RAM
Example: Page mode, RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle
BCLK
A[11:0]
#RASx
#HCAS/
#LCAS
#RD
#WR
#DMAEND
;;;;
;;;;
;;;;
;;;;
ROW COL #1 COL #2 ROW COL #1 COL #2
Read cycle Write cycle
Figur e 2.7 #DMAEND Signal Output Timing (DRAM)
V DMA BLOCK: HSDMA (Hi gh-Speed DMA)
B-V-2-14 EPSON S1C33L03 FUNCTION PART
Single-addr ess mode
(1) S RAM
Example: W hen 2 (R D )/1 (WR) wai t c ycles are inserted
BCLK
A[23:0]
#CExx
#RD
#WRH/#WRL
#DMAACK
#DMAEND
;;;
;;;
addr
Figur e 2.8 #DMAACK/#DMAEND Signal Output Timing (SRAM)
(2) B ur st ROM
Ex ampl e: When 4-con secu tiv e-bu rst and 2-wait cycles are set during the first access
BCLK
A[23:2]
A[1:0]
#CE10(9)
D[15:0]
#RD
#DMAACK
#DMAEND
;;;
;;;
addr[23:2]
;;;
;;;
"11""10""01""00"
;;;;
;;;;
;;;;
;;;;
;;;;
;;;;
;;;;;;;;;;;;;;
;;;;;;;;;;;;;;
Figur e 2.9 #DMAACK/#DMAEND Signal Output Timing (Burst ROM)
(3) D RAM
Example: Page mode, RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle
BCLK
A[11:0]
#RASx
#HCAS/
#LCAS
#RD
#WR
#DMAACK
#DMAEND
;;;;;;;
;;;;;;;
ROW COL #1 COL #2
Figur e 2.10 #DMAACK/#DMAEND Signal Output Timing (DRAM)
Note: The si ngle-address transfer method does not allow data transfer to/from the SDRAM.
V DMA BLOCK: HSDMA (Hi gh-Speed DMA)
S1C33L03 FUNCTION PART EPSON B-V-2-15
A-1
B-V
HSDMA
Inter ru pt Fu nc tion of HSDMA
The DM A con tr oller can generate an interrupt when the transfer counter in each HSDMA channel reaches 0.
Furthermore, channels 0 and 1 can invoke IDMA using their interrupt factor.
Control registers of the interrupt controller
Table 2.3 shows t he control registers of the interrupt controller that are provided for each channel.
Table 2.3 Control Registers of Interrupt Controller
Channel Interrupt factor flag Interrupt enable register Interrupt priority register
Ch. 0 FHDM0 (D0/0x40281) EHDM0(D0/0x40271) PHSD0L[2:0](D[2:0]/0x40263)
Ch. 1 FHDM1 (D1/0x40281) EHDM1(D1/0x40271) PHSD1L[2:0](D[6:4]/0x40263)
Ch. 2 FHDM2 (D2/0x40281) EHDM2(D2/0x40271) PHSD2L[2:0](D[2:0]/0x40264)
Ch. 3 FHDM3 (D3/0x40281) EHDM3(D3/0x40271) PHSD3L[2:0](D[6:4]/0x40264)
The HSDMA controller s et s t he HSDMA interrupt factor flag to "1" when the transfer counter reaches 0 after
completing a series of HSDMA transfers. If the corresponding bit of the interrupt enable register is set to "1"
at this time, an interrupt request is generated. Interrupts can be disabled by leaving the interrupt enable
register bit set to "0". The HSDMA interrupt factor flag is always set to "1" when the data transfer in each
channel is completed no matter what value the interrupt enable register bit is set to. (This is true even when it
is set to "0".)
The interrupt priority register sets an interrupt priority level (0 to 7). An interrupt request to the CPU is
accepted only when there is no other interrupt request of higher priority. Furthermore, it is only when the
PSR's IE bit = "1" (interrupt enable) and the set value of IL is smaller than the HSDMA interrupt level which
is set in the interrupt priority register that the CPU actually accepts a HSDMA interrupt. For details about the
interrupt control register and for the device operation when an interrupt occurs, refer to "ITC (Interrupt
Controller)".
V DMA BLOCK: HSDMA (Hi gh-Speed DMA)
B-V-2-16 EPSON S1C33L03 FUNCTION PART
Int e ll ig e nt D M A
Intelligent DMA (IDMA) can be invoked by the end-of-transfer interrupt factor of channels 0 and 1 of
HSDMA. The following shows the IDMA chann el s set in HSDMA:
IDMA channel
Channe l 0 end-of-transfer interr upt : 0x05
Channe l 1 end-of-transfer interr upt : 0x06
Before IDMA c an be invoked, the cor responding bits of t he ID M A request and IDMA enable registers must
be set to "1". Settings of transfer conditions on the IDMA side are also required.
Table 2.4 Control Bits fo r IDMA Transfe r
Channel IDMA request bit IDMA enable bit
Ch. 0 RHDM0(D4/0x40290) DEHDM0(D4/0x40294)
Ch. 1 RHDM1(D5/0x40290) DEHDM1(D5/0x40294)
If the IDMA request and enable bits are set to "1", IDMA is invoked through generation of an interrupt factor.
No interrupt request is generated at that point. An interrupt request is generated after the DMA transfer is
completed. The registers can also be set so as not to generate an interrupt, with only a DMA transfer
performed.
For details on IDMA transfers and interrupt control upon completion of IDMA transfer, refer to "IDMA
(Intelligent DMA)".
Trap vector
The trap vector addresses for interrupt factors in each channel are set by default as follows:
Channel 0 end-of-transfer interrupt: 0x0C00058
Channel 1 end-of-transfer interrupt: 0x0C0005C
Channel 2 end-of-transfer interrupt: 0x0C00060
Channel 3 end-of-transfer interrupt: 0x0C00064
Note that the trap table base address can be modified using the TTBR registers (0x48134 to 0x48137).
V DMA BLOCK: HSDMA (Hi gh-Speed DMA)
S1C33L03 FUNCTION PART EPSON B-V-2-17
A-1
B-V
HSDMA
I/O Memo ry of HSDM A
Table 2.5 shows the control bits of HSDMA.
Table 2.5 Control Bits of HSDMA
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
0 to 7
0 to 7
–
–
PHSD1L2
PHSD1L1
PHSD1L0
–
PHSD0L2
PHSD0L1
PHSD0L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
High-speed DMA Ch.1
interrupt level
reserved
High-speed DMA Ch.0
interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040263
(B)
High-speed
DMA Ch.0/1
interrupt
priority register
–
0 to 7
0 to 7
–
–
PHSD3L2
PHSD3L1
PHSD3L0
–
PHSD2L2
PHSD2L1
PHSD2L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
High-speed DMA Ch.3
interrupt level
reserved
High-speed DMA Ch.2
interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040264
(B)
High-speed
DMA Ch.2/3
interrupt
priority register
–
EIDMA
EHDM3
EHDM2
EHDM1
EHDM0
D7–5
D4
D3
D2
D1
D0
reserved
IDMA
High-speed DMA Ch.3
High-speed DMA Ch.2
High-speed DMA Ch.1
High-speed DMA Ch.0
– –
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
0 when being read.0040271
(B) 1 Enabled 0 Disabled
DMA interrupt
enable register
–
FIDMA
FHDM3
FHDM2
FHDM1
FHDM0
D7–5
D4
D3
D2
D1
D0
reserved
IDMA
High-speed DMA Ch.3
High-speed DMA Ch.2
High-speed DMA Ch.1
High-speed DMA Ch.0
– –
X
X
X
X
X
–
R/W
R/W
R/W
R/W
R/W
0 when being read.0040281
(B)
DMA interrupt
factor flag
register 1 Factor is
generated 0 No factor is
generated
R16TC0
R16TU0
RHDM1
RHDM0
RP3
RP2
RP1
RP0
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 0 comparison A
16-bit timer 0 comparison B
High-speed DMA Ch.1
High-speed DMA Ch.0
Port input 3
Port input 2
Port input 1
Port input 0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0040290
(B) 1 IDMA
request 0 Interrupt
request
Port input 0–3,
high-speed
DMA Ch. 0/1,
16-bit timer 0
IDMA request
register
DE16TC0
DE16TU0
DEHDM1
DEHDM0
DEP3
DEP2
DEP1
DEP0
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 0 comparison A
16-bit timer 0 comparison B
High-speed DMA Ch.1
High-speed DMA Ch.0
Port input 3
Port input 2
Port input 1
Port input 0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0040294
(B) 1 IDMA
enabled 0 IDMA
disabled
Port input 0–3,
high-speed
DMA Ch. 0/1,
16-bit timer 0
IDMA enable
register
V DMA BLOCK: HSDMA (Hi gh-Speed DMA)
B-V-2-18 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
HSD1S3
HSD1S2
HSD1S1
HSD1S0
HSD0S3
HSD0S2
HSD0S1
HSD0S0
D7
D6
D5
D4
D3
D2
D1
D0
High-speed DMA Ch.1
trigger set-up
High-speed DMA Ch.0
trigger set-up
0
0
0
0
0
0
0
0
R/W
R/W
0040298
(B) 0
1
2
3
4
5
6
7
8
9
A
B
C
Software trigger
K51 input (falling edge)
K51 input (rising edge)
Port 1 input
Port 5 input
8-bit timer Ch.1 underflow
16-bit timer Ch.1 compare B
16-bit timer Ch.1 compare A
16-bit timer Ch.5 compare B
16-bit timer Ch.5 compare A
SI/F Ch.1 Rx buffer full
SI/F Ch.1 Tx buffer empty
A/D conversion completion
0
1
2
3
4
5
6
7
8
9
A
B
C
Software trigger
K50 input (falling edge)
K50 input (rising edge)
Port 0 input
Port 4 input
8-bit timer Ch.0 underflow
16-bit timer Ch.0 compare B
16-bit timer Ch.0 compare A
16-bit timer Ch.4 compare B
16-bit timer Ch.4 compare A
SI/F Ch.0 Rx buffer full
SI/F Ch.0 Tx buffer empty
A/D conversion completion
High-speed
DMA Ch.0/1
trigger set-up
register
HSD3S3
HSD3S2
HSD3S1
HSD3S0
HSD2S3
HSD2S2
HSD2S1
HSD2S0
D7
D6
D5
D4
D3
D2
D1
D0
High-speed DMA Ch.3
trigger set-up
High-speed DMA Ch.2
trigger set-up
0
0
0
0
0
0
0
0
R/W
R/W
0040299
(B) 0
1
2
3
4
5
6
7
8
9
A
B
C
Software trigger
K54 input (falling edge)
K54 input (rising edge)
Port 3 input
Port 7 input
8-bit timer Ch.3 underflow
16-bit timer Ch.3 compare B
16-bit timer Ch.3 compare A
16-bit timer Ch.5 compare B
16-bit timer Ch.5 compare A
SI/F Ch.1 Rx buffer full
SI/F Ch.1 Tx buffer empty
A/D conversion completion
0
1
2
3
4
5
6
7
8
9
A
B
C
Software trigger
K53 input (falling edge)
K53 input (rising edge)
Port 2 input
Port 6 input
8-bit timer Ch.2 underflow
16-bit timer Ch.2 compare B
16-bit timer Ch.2 compare A
16-bit timer Ch.4 compare B
16-bit timer Ch.4 compare A
SI/F Ch.0 Rx buffer full
SI/F Ch.0 Tx buffer empty
A/D conversion completion
High-speed
DMA Ch.2/3
trigger set-up
register
–
HST3
HST2
HST1
HST0
D7–4
D3
D2
D1
D0
reserved
HSDMA Ch.3 software trigger
HSDMA Ch.2 software trigger
HSDMA Ch.1 software trigger
HSDMA Ch.0 software trigger
–
0
0
0
0
–
W
W
W
W
0 when being read.004029A
(B) –
1 Trigger 0 Invalid
High-speed
DMA software
trigger
register
–
CFK54
CFK53
CFK52
CFK51
CFK50
D7–5
D4
D3
D2
D1
D0
reserved
K54 function selection
K53 function selection
K52 function selection
K51 function selection
K50 function selection
– –
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
0 when being read.00402C0
(B) 1
#DMAREQ3
0 K54
1
#DMAREQ2
0 K53
1 #ADTRG 0 K52
1
#DMAREQ1
0 K51
1
#DMAREQ0
0 K50
K5 function
select register
V DMA BLOCK: HSDMA (Hi gh-Speed DMA)
S1C33L03 FUNCTION PART EPSON B-V-2-19
A-1
B-V
HSDMA
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
CFP16
CFP15
CFP14
CFP13
CFP12
CFP11
CFP10
D7
D6
D5
D4
D3
D2
D1
D0
reserved
P16 function selection
P15 function selection
P14 function selection
P13 function selection
P12 function selection
P11 function selection
P10 function selection
–
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.
Extended functions
(0x402DF)
00402D4
(B) 1 EXCL5
#DMAEND1
0 P16
1 EXCL4
#DMAEND0
0 P15
1 EXCL3
T8UF3 0 P13
1 EXCL2
T8UF2 0 P12
1 EXCL1
T8UF1 0 P11
1 EXCL0
T8UF0 0 P10
–P1 function
select register
1 FOSC1 0 P14
–
IOC16
IOC15
IOC14
IOC13
IOC12
IOC11
IOC10
D7
D6
D5
D4
D3
D2
D1
D0
reserved
P16 I/O control
P15 I/O control
P14 I/O control
P13 I/O control
P12 I/O control
P11 I/O control
P10 I/O control
–
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.
This register
indicates the values
of the I/O control
signals of the ports
when it is read. (See
detailed explanation.)
00402D6
(B) 1Output 0Input
–P1 I/O control
register
–
CFP35
CFP34
CFP33
CFP32
CFP31
CFP30
D7–6
D5
D4
D3
D2
D1
D0
reserved
P35 function selection
P34 function selection
P33 function selection
P32 function selection
P31 function selection
P30 function selection
–
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.
Ext. func.(0x402DF)
00402DC
(B) –P3 function
select register 1 #BUSACK 0 P35
1 #BUSREQ
#CE6 0 P34
1
#DMAACK0
0 P32
1 #BUSGET 0 P31
1 #WAIT
#CE4/#CE5 0 P30
1
#DMAACK1
0 P33
CFEX7
CFEX6
CFEX5
CFEX4
CFEX3
CFEX2
CFEX1
CFEX0
D7
D6
D5
D4
D3
D2
D1
D0
P07 port extended function
P06 port extended function
P05 port extended function
P04 port extended function
P31 port extended function
P21 port extended function
P10, P11, P13 port extended
function
P12, P14 port extended function
0
0
0
0
0
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00402DF
(B)
Port function
extension
register
1
#DMAEND3
0 P07, etc.
1
#DMAACK3
0 P06, etc.
1
#DMAEND2
0 P05, etc.
1
#DMAACK2
0 P04, etc.
1 #GARD 0 P31, etc.
1 #GAAS 0 P21, etc.
1 DST0
DST1
DPC0
0 P10, etc.
P11, etc.
P13, etc.
1 DST2
DCLK 0 P12, etc.
P14, etc.
TC0_L7
TC0_L6
TC0_L5
TC0_L4
TC0_L3
TC0_L2
TC0_L1
TC0_L0
BLKLEN07
BLKLEN06
BLKLEN05
BLKLEN04
BLKLEN03
BLKLEN02
BLKLEN01
BLKLEN00
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.0 transfer c
ounter[7:0]
(block transfer mode)
Ch.0 transfer counter[15:8]
(single/successive transfer mode)
Ch.0 block length
(block transfer mode)
Ch.0 transfer counter[7:0]
(single/successive transfer mode)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
0048220
(HW)
High-speed
DMA Ch.0
transfer
counter
register
V DMA BLOCK: HSDMA (Hi gh-Speed DMA)
B-V-2-20 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
–
DUALM0
D0DIR
–
TC0_H7
TC0_H6
TC0_H5
TC0_H4
TC0_H3
TC0_H2
TC0_H1
TC0_H0
DF
DE
DD–8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.0 address mode selection
D) Invalid
S) Ch.0 transfer direction control
reserved
Ch.0 transfer counter[15:8]
(block transfer mode)
Ch.0 transfer counter[23:16]
(single/successive transfer mode)
1 Dual addr 0 Single addr
1
Memory WR
0
Memory RD
0
–
0
–
X
X
X
X
X
X
X
X
R/W
–
R/W
–
R/W Undefined in read.
0048222
(HW)
High-speed
DMA Ch.0
control register
Note:
D) Dual address
mode
S) Single
address
mode
S0ADRL15
S0ADRL14
S0ADRL13
S0ADRL12
S0ADRL11
S0ADRL10
S0ADRL9
S0ADRL8
S0ADRL7
S0ADRL6
S0ADRL5
S0ADRL4
S0ADRL3
S0ADRL2
S0ADRL1
S0ADRL0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D) Ch.0 source address[15:0]
S) Ch.0 memory address[15:0] X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048224
(HW)
High-speed
DMA Ch.0
low-order
source address
set-up register
Note:
D) Dual address
mode
S) Single
address
mode
–
DATSIZE0
S0IN1
S0IN0
S0ADRH11
S0ADRH10
S0ADRH9
S0ADRH8
S0ADRH7
S0ADRH6
S0ADRH5
S0ADRH4
S0ADRH3
S0ADRH2
S0ADRH1
S0ADRH0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Ch.0 transfer data size
D) Ch.0 source address control
S) Ch.0 memory address control
D) Ch.0 source address[27:16]
S) Ch.0 memory address[27:16]
–
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
–
R/W
R/W
R/W
0048226
(HW) 1 Half word 0 Byte
High-speed
DMA Ch.0
high-order
source address
set-up register
Note:
D) Dual address
mode
S) Single
address
mode
1
1
0
0
1
0
1
0
S0IN[1:0] Inc/dec
Inc.(no init)
Inc.(init)
Dec.(no init)
Fixed
–
D0ADRL15
D0ADRL14
D0ADRL13
D0ADRL12
D0ADRL11
D0ADRL10
D0ADRL9
D0ADRL8
D0ADRL7
D0ADRL6
D0ADRL5
D0ADRL4
D0ADRL3
D0ADRL2
D0ADRL1
D0ADRL0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D) Ch.0 destination address[15:0]
S) Invalid X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048228
(HW)
High-speed
DMA Ch.0
low-order
destination
address set-up
register
Note:
D) Dual address
mode
S) Single
address
mode
V DMA BLOCK: HSDMA (Hi gh-Speed DMA)
S1C33L03 FUNCTION PART EPSON B-V-2-21
A-1
B-V
HSDMA
NameAddressRegister name Bit Function Setting Init. R/W Remarks
D0MOD1
D0MOD0
D0IN1
D0IN0
D0ADRH11
D0ADRH10
D0ADRH9
D0ADRH8
D0ADRH7
D0ADRH6
D0ADRH5
D0ADRH4
D0ADRH3
D0ADRH2
D0ADRH1
D0ADRH0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.0 transfer mode
D) Ch.0 destination address
control
S) Invalid
D) Ch.0 destination
address[27:16]
S) Invalid
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
004822A
(HW)
High-speed
DMA Ch.0
high-order
destination
address set-up
register
Note:
D) Dual address
mode
S) Single
address
mode
1
1
0
0
1
0
1
0
D0MOD[1:0] Mode
Invalid
Block
Successive
Single
1
1
0
0
1
0
1
0
D0IN[1:0] Inc/dec
Inc.(no init)
Inc.(init)
Dec.(no init)
Fixed
––
HS0_EN
DF–1
D0
reserved
Ch.0 enable 1 Enable 0 Disable
–
0
–
R/W
Undefined in read.004822C
(HW)
High-speed
DMA Ch.0
enable register
––
HS0_TF
DF–1
D0
reserved
Ch.0 trigger flag clear (writing)
Ch.0 trigger flag status (reading) 1 Clear 0
No operation
1 Set 0 Cleared
–
0
–
R/W
Undefined in read.004822E
(HW)
High-speed
DMA Ch.0
trigger flag
register
TC1_L7
TC1_L6
TC1_L5
TC1_L4
TC1_L3
TC1_L2
TC1_L1
TC1_L0
BLKLEN17
BLKLEN16
BLKLEN15
BLKLEN14
BLKLEN13
BLKLEN12
BLKLEN11
BLKLEN10
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.1 transfer c
ounter[7:0]
(block transfer mode)
Ch.1 transfer counter[15:8]
(single/successive transfer mode)
Ch.1 block length
(block transfer mode)
Ch.1 transfer counter[7:0]
(single/successive transfer mode)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
0048230
(HW)
High-speed
DMA Ch.1
transfer
counter
register
–
–
DUALM1
D1DIR
–
TC1_H7
TC1_H6
TC1_H5
TC1_H4
TC1_H3
TC1_H2
TC1_H1
TC1_H0
DF
DE
DD–8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.1 address mode selection
D) Invalid
S) Ch.1 transfer direction control
reserved
Ch.1 transfer counter[15:8]
(block transfer mode)
Ch.1 transfer counter[23:16]
(single/successive transfer mode)
1 Dual addr 0 Single addr
1
Memory WR
0
Memory RD
0
–
0
–
X
X
X
X
X
X
X
X
R/W
–
R/W
–
R/W Undefined in read.
0048232
(HW)
High-speed
DMA Ch.1
control register
Note:
D) Dual address
mode
S) Single
address
mode
V DMA BLOCK: HSDMA (Hi gh-Speed DMA)
B-V-2-22 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
S1ADRL15
S1ADRL14
S1ADRL13
S1ADRL12
S1ADRL11
S1ADRL10
S1ADRL9
S1ADRL8
S1ADRL7
S1ADRL6
S1ADRL5
S1ADRL4
S1ADRL3
S1ADRL2
S1ADRL1
S1ADRL0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D) Ch.1 source address[15:0]
S) Ch.1 memory address[15:0] X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048234
(HW)
High-speed
DMA Ch.1
low-order
source address
set-up register
Note:
D) Dual address
mode
S) Single
address
mode
–
DATSIZE1
S1IN1
S1IN0
S1ADRH11
S1ADRH10
S1ADRH9
S1ADRH8
S1ADRH7
S1ADRH6
S1ADRH5
S1ADRH4
S1ADRH3
S1ADRH2
S1ADRH1
S1ADRH0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Ch.1 transfer data size
D) Ch.1 source address control
S) Ch.1 memory address control
D) Ch.1 source address[27:16]
S) Ch.1 memory address[27:16]
–
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
–
R/W
R/W
R/W
0048236
(HW) 1 Half word 0 Byte
High-speed
DMA Ch.1
high-order
source address
set-up register
Note:
D) Dual address
mode
S) Single
address
mode
1
1
0
0
1
0
1
0
S1IN[1:0] Inc/dec
Inc.(no init)
Inc.(init)
Dec.(no init)
Fixed
–
D1ADRL15
D1ADRL14
D1ADRL13
D1ADRL12
D1ADRL11
D1ADRL10
D1ADRL9
D1ADRL8
D1ADRL7
D1ADRL6
D1ADRL5
D1ADRL4
D1ADRL3
D1ADRL2
D1ADRL1
D1ADRL0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D) Ch.1 destination address[15:0]
S) Invalid X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048238
(HW)
High-speed
DMA Ch.1
low-order
destination
address set-up
register
Note:
D) Dual address
mode
S) Single
address
mode
V DMA BLOCK: HSDMA (Hi gh-Speed DMA)
S1C33L03 FUNCTION PART EPSON B-V-2-23
A-1
B-V
HSDMA
NameAddressRegister name Bit Function Setting Init. R/W Remarks
D1MOD1
D1MOD0
D1IN1
D1IN0
D1ADRH11
D1ADRH10
D1ADRH9
D1ADRH8
D1ADRH7
D1ADRH6
D1ADRH5
D1ADRH4
D1ADRH3
D1ADRH2
D1ADRH1
D1ADRH0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.1 transfer mode
D) Ch.1 destination address
control
S) Invalid
D) Ch.1 destination
address[27:16]
S) Invalid
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
004823A
(HW)
High-speed
DMA Ch.1
high-order
destination
address set-up
register
Note:
D) Dual address
mode
S) Single
address
mode
1
1
0
0
1
0
1
0
D1MOD[1:0] Mode
Invalid
Block
Successive
Single
1
1
0
0
1
0
1
0
D1IN[1:0] Inc/dec
Inc.(no init)
Inc.(init)
Dec.(no init)
Fixed
––
HS1_EN
DF–1
D0
reserved
Ch.1 enable 1 Enable 0 Disable
–
0
–
R/W
Undefined in read.004823C
(HW)
High-speed
DMA Ch.1
enable register
––
HS1_TF
DF–1
D0
reserved
Ch.1 trigger flag clear (writing)
Ch.1 trigger flag status (reading) 1 Clear 0
No operation
1 Set 0 Cleared
–
0
–
R/W
Undefined in read.004823E
(HW)
High-speed
DMA Ch.1
trigger flag
register
TC2_L7
TC2_L6
TC2_L5
TC2_L4
TC2_L3
TC2_L2
TC2_L1
TC2_L0
BLKLEN27
BLKLEN26
BLKLEN25
BLKLEN24
BLKLEN23
BLKLEN22
BLKLEN21
BLKLEN20
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.2 transfer c
ounter[7:0]
(block transfer mode)
Ch.2 transfer counter[15:8]
(single/successive transfer mode)
Ch.2 block length
(block transfer mode)
Ch.2 transfer counter[7:0]
(single/successive transfer mode)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
0048240
(HW)
High-speed
DMA Ch.2
transfer
counter
register
–
–
DUALM2
D2DIR
–
TC2_H7
TC2_H6
TC2_H5
TC2_H4
TC2_H3
TC2_H2
TC2_H1
TC2_H0
DF
DE
DD–8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.2 address mode selection
D) Invalid
S) Ch.2 transfer direction control
reserved
Ch.2 transfer counter[15:8]
(block transfer mode)
Ch.2 transfer counter[23:16]
(single/successive transfer mode)
1 Dual addr 0 Single addr
1
Memory WR
0
Memory RD
0
–
0
–
X
X
X
X
X
X
X
X
R/W
–
R/W
–
R/W Undefined in read.
0048242
(HW)
High-speed
DMA Ch.2
control register
Note:
D) Dual address
mode
S) Single
address
mode
V DMA BLOCK: HSDMA (Hi gh-Speed DMA)
B-V-2-24 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
S2ADRL15
S2ADRL14
S2ADRL13
S2ADRL12
S2ADRL11
S2ADRL10
S2ADRL9
S2ADRL8
S2ADRL7
S2ADRL6
S2ADRL5
S2ADRL4
S2ADRL3
S2ADRL2
S2ADRL1
S2ADRL0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D) Ch.2 source address[15:0]
S) Ch.2 memory address[15:0] X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048244
(HW)
High-speed
DMA Ch.2
low-order
source address
set-up register
Note:
D) Dual address
mode
S) Single
address
mode
–
DATSIZE2
S2IN1
S2IN0
S2ADRH11
S2ADRH10
S2ADRH9
S2ADRH8
S2ADRH7
S2ADRH6
S2ADRH5
S2ADRH4
S2ADRH3
S2ADRH2
S2ADRH1
S2ADRH0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Ch.2 transfer data size
D) Ch.2 source address control
S) Ch.2 memory address control
D) Ch.2 source address[27:16]
S) Ch.2 memory address[27:16]
–
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
–
R/W
R/W
R/W
0048246
(HW) 1 Half word 0 Byte
High-speed
DMA Ch.2
high-order
source address
set-up register
Note:
D) Dual address
mode
S) Single
address
mode
1
1
0
0
1
0
1
0
S2IN[1:0] Inc/dec
Inc.(no init)
Inc.(init)
Dec.(no init)
Fixed
–
D2ADRL15
D2ADRL14
D2ADRL13
D2ADRL12
D2ADRL11
D2ADRL10
D2ADRL9
D2ADRL8
D2ADRL7
D2ADRL6
D2ADRL5
D2ADRL4
D2ADRL3
D2ADRL2
D2ADRL1
D2ADRL0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D) Ch.2 destination address[15:0]
S) Invalid X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048248
(HW)
High-speed
DMA Ch.2
low-order
destination
address set-up
register
Note:
D) Dual address
mode
S) Single
address
mode
V DMA BLOCK: HSDMA (Hi gh-Speed DMA)
S1C33L03 FUNCTION PART EPSON B-V-2-25
A-1
B-V
HSDMA
NameAddressRegister name Bit Function Setting Init. R/W Remarks
D2MOD1
D2MOD0
D2IN1
D2IN0
D2ADRH11
D2ADRH10
D2ADRH9
D2ADRH8
D2ADRH7
D2ADRH6
D2ADRH5
D2ADRH4
D2ADRH3
D2ADRH2
D2ADRH1
D2ADRH0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.2 transfer mode
D) Ch.2 destination address
control
S) Invalid
D) Ch.2 destination
address[27:16]
S) Invalid
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
004824A
(HW)
High-speed
DMA Ch.2
high-order
destination
address set-up
register
Note:
D) Dual address
mode
S) Single
address
mode
1
1
0
0
1
0
1
0
D2MOD[1:0] Mode
Invalid
Block
Successive
Single
1
1
0
0
1
0
1
0
D2IN[1:0] Inc/dec
Inc.(no init)
Inc.(init)
Dec.(no init)
Fixed
––
HS2_EN
DF–1
D0
reserved
Ch.2 enable 1 Enable 0 Disable
–
0
–
R/W
Undefined in read.004824C
(HW)
High-speed
DMA Ch.2
enable register
––
HS2_TF
DF–1
D0
reserved
Ch.2 trigger flag clear (writing)
Ch.2 trigger flag status (reading) 1 Clear 0
No operation
1 Set 0 Cleared
–
0
–
R/W
Undefined in read.004824E
(HW)
High-speed
DMA Ch.2
trigger flag
register
TC3_L7
TC3_L6
TC3_L5
TC3_L4
TC3_L3
TC3_L2
TC3_L1
TC3_L0
BLKLEN37
BLKLEN36
BLKLEN35
BLKLEN34
BLKLEN33
BLKLEN32
BLKLEN31
BLKLEN30
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.3 transfer c
ounter[7:0]
(block transfer mode)
Ch.3 transfer counter[15:8]
(single/successive transfer mode)
Ch.3 block length
(block transfer mode)
Ch.3 transfer counter[7:0]
(single/successive transfer mode)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
0048250
(HW)
High-speed
DMA Ch.3
transfer
counter
register
–
–
DUALM3
D3DIR
–
TC3_H7
TC3_H6
TC3_H5
TC3_H4
TC3_H3
TC3_H2
TC3_H1
TC3_H0
DF
DE
DD–8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.3 address mode selection
D) Invalid
S) Ch.3 transfer direction control
reserved
Ch.3 transfer counter[15:8]
(block transfer mode)
Ch.3 transfer counter[23:16]
(single/successive transfer mode)
1 Dual addr 0 Single addr
1
Memory WR
0
Memory RD
0
–
0
–
X
X
X
X
X
X
X
X
R/W
–
R/W
–
R/W Undefined in read.
0048252
(HW)
High-speed
DMA Ch.3
control register
Note:
D) Dual address
mode
S) Single
address
mode
V DMA BLOCK: HSDMA (Hi gh-Speed DMA)
B-V-2-26 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
S3ADRL15
S3ADRL14
S3ADRL13
S3ADRL12
S3ADRL11
S3ADRL10
S3ADRL9
S3ADRL8
S3ADRL7
S3ADRL6
S3ADRL5
S3ADRL4
S3ADRL3
S3ADRL2
S3ADRL1
S3ADRL0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D) Ch.3 source address[15:0]
S) Ch.3 memory address[15:0] X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048254
(HW)
High-speed
DMA Ch.3
low-order
source address
set-up register
Note:
D) Dual address
mode
S) Single
address
mode
–
DATSIZE3
S3IN1
S3IN0
S3ADRH11
S3ADRH10
S3ADRH9
S3ADRH8
S3ADRH7
S3ADRH6
S3ADRH5
S3ADRH4
S3ADRH3
S3ADRH2
S3ADRH1
S3ADRH0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Ch.3 transfer data size
D) Ch.3 source address control
S) Ch.3 memory address control
D) Ch.3 source address[27:16]
S) Ch.3 memory address[27:16]
–
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
–
R/W
R/W
R/W
0048256
(HW) 1 Half word 0 Byte
High-speed
DMA Ch.3
high-order
source address
set-up register
Note:
D) Dual address
mode
S) Single
address
mode
1
1
0
0
1
0
1
0
S3IN[1:0] Inc/dec
Inc.(no init)
Inc.(init)
Dec.(no init)
Fixed
–
D3ADRL15
D3ADRL14
D3ADRL13
D3ADRL12
D3ADRL11
D3ADRL10
D3ADRL9
D3ADRL8
D3ADRL7
D3ADRL6
D3ADRL5
D3ADRL4
D3ADRL3
D3ADRL2
D3ADRL1
D3ADRL0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D) Ch.3 destination address[15:0]
S) Invalid X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048258
(HW)
High-speed
DMA Ch.3
low-order
destination
address set-up
register
Note:
D) Dual address
mode
S) Single
address
mode
V DMA BLOCK: HSDMA (Hi gh-Speed DMA)
S1C33L03 FUNCTION PART EPSON B-V-2-27
A-1
B-V
HSDMA
NameAddressRegister name Bit Function Setting Init. R/W Remarks
D3MOD1
D3MOD0
D3IN1
D3IN0
D3ADRH11
D3ADRH10
D3ADRH9
D3ADRH8
D3ADRH7
D3ADRH6
D3ADRH5
D3ADRH4
D3ADRH3
D3ADRH2
D3ADRH1
D3ADRH0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.3 transfer mode
D) Ch.3 destination address
control
S) Invalid
D) Ch.3 destination
address[27:16]
S) Invalid
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
004825A
(HW)
High-speed
DMA Ch.3
high-order
destination
address set-up
register
Note:
D) Dual address
mode
S) Single
address
mode
1
1
0
0
1
0
1
0
D3MOD[1:0] Mode
Invalid
Block
Successive
Single
1
1
0
0
1
0
1
0
D3IN[1:0] Inc/dec
Inc.(no init)
Inc.(init)
Dec.(no init)
Fixed
––
HS3_EN
DF–1
D0
reserved
Ch.3 enable 1 Enable 0 Disable
–
0
–
R/W
Undefined in read.004825C
(HW)
High-speed
DMA Ch.3
enable register
––
HS3_TF
DF–1
D0
reserved
Ch.3 trigger flag clear (writing)
Ch.3 trigger flag status (reading) 1 Clear 0
No operation
1 Set 0 Cleared
–
0
–
R/W
Undefined in read.004825E
(HW)
High-speed
DMA Ch.3
trigger flag
register
CFK51–CFK50: K5[ 1:0] p i n func tio n select io n (D[1:0 ]) / K 5 func tio n select regi st er (0 x40 2C 0 )
CFK54–CFK53: K5[ 4:3] p in fu nc tio n select io n (D[4:3 ]) / K 5 func tio n select reg ist er (0x40 2C0 )
Set the #DMAREQx pin of HSDMA.
Write "1": # DMAREQx input
Write "0": Input port
Read: Valid
CFK50, CFK51, CFK53 and CFK54 are the function select bits for K50 (#DMAREQ0), K51 (#DMAREQ1), K53
(#DMAREQ 2) and K54 ( #DMAREQ 3), respect ively. W hen using the #D MAREQx signal, wri te "1" to CF K5x to
set the K5x port for inputting the signal.
If this bit is set to "0", the pin is set for an input port.
At c old start, CFK5x is set to "0" (input port). At hot start, CFK5x retains the previous status before an initial reset.
CFP16–CFP15: P1[ 6:5 ] p in func tio n select io n (D[6:5 ]) / P 1 fu nctio n sele ct regist er (0 x4 0 2D4 )
Set the #DMAENDx pin of HSDMA.
Write "1": # DMAENDx output
Write "0": I/O port
Read: Valid
When using the #DMAEND0 signal, set the P15 pin for the #DMAEN D0 output pin by writing " 1" to CFP15.
Sim ilarly, w hen using the #DMAEND1 signal, set the P16 pin for the #DMAEND1 output pin by writing "1" to
CFP16. Furthermore, direct these pins for output by writing "1" to the corresponding I/O control register.
If CFP1x is set to "0", the pin is set for an I/O port.
At c old start, CFP1x is set to "0" (I/O port). At hot start, CFP1x retains the previous status before an initial reset.
V DMA BLOCK: HSDMA (Hi gh-Speed DMA)
B-V-2-28 EPSON S1C33L03 FUNCTION PART
IOC16–IOC15: P1[6:5 ] p ort I/O con tro l (D[6:5 ]) / P 1 I/ O con tro l regi st er (0 x40 2D 6 )
Directs P15 and P16 for input or output and indicates the I/O control signal value of the port.
When writing data
Write "1": O utput mode
Write "0": Input mode
To use the #D M A END0 pi n (channel 0), dir ect the pin for output by w riti ng "1" to IOC15; to use the #DMAEND1
pin (channel 1), direct the pin for output by writing "1" to IOC16. If these pins are set for input, the P15 and P16
pins do not functi on as the #DM A ENDx output pin s even when CFP1 5 and CFP16 are set to "1".
When re ad in g d ata
Read "1": I/O control signal (output)
Read "0": I/O control signal (input)
The I/O control signal value for the port pin is read from this register. When I/O port function is selected using the
CFP1x r egist er, the value written to the IOC register is read out as is. When peripheral function is selected, the read
value dep ends on the per ipheral circuit s tatus and may not ind icate the value written to the IOC register.
At c old start, IOC1x is set to "0" (input mode). At hot start, the bit retains its state from prior to the initial reset.
CFP33–CFP32: P3[ 3:2 ] p in func tio n select io n (D[3:2 ]) / P 3 fu nctio n sele ct regist er (0 x4 0 2DC )
Set the #DMAACKx pin of HSDMA.
Write "1": # DMAAC Kx ou tput
Write "0": I/O port
Read: Valid
When using the #DMAACK0 signal, set the P32 pin for the #DMAACK0 ou tput pin by w riti ng "1" to CFP32.
Sim ilarly, w hen using the #DMAACK1 signal, set the P33 pin for the #DMAACK1 output pin by writing "1" to
CFP33.
If CFP3x is set to "0", the pin is set for an I/O port.
At c old start, CFP3x is set to "0" (I/O port). At hot start, CFP3x retains the previous status before an initial reset.
CFEX7–CFEX4: P0[ 7:4] pin fu nctio n exte nsio n (D [7 :4 ]) / Por t func tio n exten sio n regi st er (0x40 2D F)
Set the #DMAACKx and #DMAENDx pin s of HSDMA.
Write "1": HSDMA outpu t
Write "0": I/O- port/serial interface I/O
Read: Valid
CFEX4, CFEX5, CFEX6 and CFEX7 are the function extention bits for P04 (#DMAACK2), P05 (#DMAEND2),
P06 ( #DMAACK3) and P07 (#DMAEND 3), respect ively. When using t he HSDMA signal , wr ite "1" to CFEXx to
set the P0x port for outputting the signal.
When CFEXx is set to "0", the corresponding CFP bit becomes effective.
At c old start, these bits are set to "0" (I/O-port/serial interface I/O pin). At hot start, these bits retain the previous
status before an initial reset.
V DMA BLOCK: HSDMA (Hi gh-Speed DMA)
S1C33L03 FUNCTION PART EPSON B-V-2-29
A-1
B-V
HSDMA
HSD0S3–HSD0S0: Ch. 0 trigger set-up (D[3:0]) / HSDMA Ch. 0/1 trigger set-up register (0x40298)
HSD1S3–HSD1S0: Ch. 1 trigger set-up (D[7:4]) / HSDMA Ch. 0/1 trigger set-up register (0x40298)
HSD2S3–HSD2S0: Ch. 2 trigger set-up (D[3:0]) / HSDMA Ch. 2/3 trigger set-up register (0x40299)
HSD3S3–HSD3S0: Ch. 3 trigger set-up (D[7:4]) / HSDMA Ch. 2/3 trigger set-up register (0x40299)
Select a trigger factor for each HSDMA channel.
Table 2.6 HSDMA Trigger Factor
Value Ch.0 trigger factor Ch.1 trigger factor Ch.2 trigger factor Ch.3 trigger factor
0000 Software trigger Software trigger Software trigger Software trigger
0001 K50 port input (falling edge) K51 port input (falling edge) K53 port input (falling edge) K54 port input (falling edge)
0010 K50 port input (rising edge) K51 port input (rising edge) K53 port input (rising edge) K54 port input (rising edge)
0011 Port 0 input Port 1 input Port 2 input Port 3 input
0100 Port 4 input Port 5 input Port 6 input Port 7 input
0101 8-bit timer 0 underflow 8-bit timer 1 underflow 8-bit timer 2 underflow 8-bit timer 3 underflow
0110 16-bit timer 0 compare B 16-bit timer 1 compare B 16-bit timer 2 compare B 16-bit timer 3 compare B
0111 16-bit timer 0 compare A 16-bit timer 1 compare A 16-bit timer 2 compare A 16-bit timer 3 compare A
1000 16-bit timer 4 compare B 16-bit timer 5 compare B 16-bit timer 4 compare B 16-bit timer 5 compare B
1001 16-bit timer 4 compare A 16-bit timer 5 compare A 16-bit timer 4 compare A 16-bit timer 5 compare A
1010 Serial I/F Ch.0 Rx buffer full Serial I/F Ch.1 Rx buffer full Serial I/F Ch.0 Rx buffer full Serial I/F Ch.1 Rx buffer full
1011 Serial I/F Ch.0 Tx buffer empty Serial I/F Ch.1 Tx buffer empty Serial I/F Ch.0 Tx buffer empty Serial I/F Ch.1 Tx buffer empty
1100 A/D conversion completion A/D conversion completion A/D conversion completion A/D conversion completion
At i nitial reset, HSDxS is set to "0000" (software trigger).
HST0: Ch. 0 software trigger (D0) / HSDMA software trigger register (0x4029A)
HST1: Ch. 1 software trigger (D1) / HSDMA software trigger register (0x4029A)
HST2: Ch. 2 software trigger (D2) / HSDMA software trigger register (0x4029A)
HST3: Ch. 3 software trigger (D3) / HSDMA software trigger register (0x4029A)
Start a DMA tran sfer.
Write "1": Trigge r
Write "0": Invalid
Read: Invalid
Writing "1" to HSTx generates a trigger pulse that starts a DMA transfer.
HSTx is effective only when software trigger is selected as the trigger factor of the HSDMA channel by the
HSDxS bits.
At i nitial reset, HSTx is set to "0".
HS0_TF: Ch. 0 trigger flag clear/s tatus (D0) / HSDMA Ch. 0 trigger f lag reg ister (0x4822E)
HS1_TF: Ch. 1 trigger flag clear/s tatus (D0) / HS DMA Ch. 1 trigger flag registe r (0x4823E)
HS2_TF: Ch. 2 trigger flag clear/s tatus (D0) / HSDMA Ch. 2 trigger f lag reg ister (0x4824E)
HS3_TF: Ch. 3 trigger flag clear/s tatus (D0) / HSDMA Ch. 3 trigger f lag reg ister (0x4825E)
These bits are used to check and clear the trigger flag status.
Write "1": Trigge r flag clear
Write "0": Invalid
Read "1": Trigger flag has been set
Read "0": Trigger flag has been cleared
The trigger flag is set when the trigger factor is input to the HSDMA channel and is cleared when the HSDMA
channel starts a data transfer. By reading HSx_TF, the flag status can be checked. Writing "1" to HSx_TF clears
the trigger flag if the DMA transfer has not been started.
At i nitial reset, HSx_TF is set to "0".
V DMA BLOCK: HSDMA (Hi gh-Speed DMA)
B-V-2-30 EPSON S1C33L03 FUNCTION PART
HS0_EN: Ch. 0 enable (D0) / HS DMA Ch. 0 enable r egiste r (0x4822C)
HS1_EN: Ch. 1 enable (D0) / HSDMA Ch. 1 enable registe r (0x4823C)
HS2_EN: Ch. 2 enable (D0) / HSDMA Ch. 2 enable registe r (0x4824C)
HS3_EN: Ch. 3 enable (D0) / HSDMA Ch. 3 enable registe r (0x4825C)
Enable a DMA tr a n s fer.
Write "1": Ena bled
Write "0": Disabl ed
Read: Valid
DMA transfer is enabled by writing "1" to this bit.
HSDMA is placed in a state ready to accept a DMA request from the #DMAREQx pin or by the selected trigger
factor.
DMA transfer is disabled by writing "0" to this bit.
When DMA transfers are completed (transfer counter = 0), HSx_EN is cleared by the hardware.
Be sure to disable DMA transfers (HSx_EN = "0") before setting the transfer condition.
At i nitial reset, HSx_EN is set to "0" (disabled).
DUALM0: Ch. 0 address mo de selection (DF) / HS DM A Ch. 0 control register (0x48222)
DUALM1: Ch. 1 address mo de selection (DF) / HS DM A Ch. 1 control register (0x48232)
DUALM2: Ch. 2 address mo de selection (DF) / HS DM A Ch. 2 control register (0x48242)
DUALM3: Ch. 3 address mo de selection (DF) / HS DM A Ch. 3 control register (0x48252)
Select an address mode.
Write "1": Dual-a ddress mode
Write "0": S ingle-addr ess mode
Read: Valid
When "1" is written to DUALMx, the HSDMA channel enters dual-address mode that allows specification of
source and destination addresses. When "0" is written, the HSDMA channel enters single-address mode for high-
speed data transfer between the external memory and an I/O device.
At i nitial reset, DUALMx is set to "0" (single-address mode).
D0DIR: Ch. 0 transfer direction control (DE) / HSDMA Ch.0 co ntrol register (0x48222)
D1DIR: Ch. 1 transfer direction control (DE) / HSDMA Ch.1 co ntrol register (0x48232)
D2DIR: Ch. 2 transfer direction control (DE) / HSDMA Ch.2 co ntrol register (0x48242)
D3DIR: Ch. 3 transfer direction control (DE) / HSDMA Ch.3 co ntrol register (0x48252)
Control the direction of data transfer in single-address mode.
Write "1": Memo ry write (I/O to memory)
Write "0": Memo ry read (memory to I/O)
Read: Valid
Data transfer from an external I/O device to external memory is performed by writing "1" to DxDIR. Data transfer
from external memory to an external I/O is performed by writing "0".
At i nitial reset, DxDIR is set to "0" (memory to I/O).
This bit is effective only in single-address mode.
V DMA BLOCK: HSDMA (Hi gh-Speed DMA)
S1C33L03 FUNCTION PART EPSON B-V-2-31
A-1
B-V
HSDMA
D0MOD1–D0MOD0: Ch. 0 transfer mode (D[F:E]) / Ch. 0 hi gh- o r der de st i nat ion addr es s s et- up register (0x48 22A )
D1MOD1–D1MOD0: Ch. 1 transfer mode (D[F:E]) / Ch. 1 hi gh- o r der de st i nat ion addr es s s et- up register (0x48 23A )
D2MOD1–D2MOD0: Ch. 2 transfer mode (D[F:E]) / Ch. 2 hi gh- o r der de st i nat ion addr es s s et- up register (0x48 24A )
D3MOD1–D3MOD0: Ch. 3 transfer mode (D[F:E]) / Ch. 3 hi gh- o r der de st i nat ion addr es s s et- up register (0x48 25A )
Select a tran sfer mo de.
Table 2.7 Transfer Mode
DxMOD1 DxMOD0 Mode
11Invalid
10Block transfer mode
01Successive transfer mode
00Single transfer mode
In single transfer mode, a transfer operation invoked by one trigger is completed after transferring one unit of data
of the size set by DATSIZEx.
In successive transfer mode, data transfer operations are per form ed by one trigger a num ber of times as set by the
transfer counter.
In block transfer mode, a transfer operation invoked by one trigger is completed after transferring one block of data
of the size s et by BLKLE N x.
At i nitial reset, DxMOD is set to "00" (single transfer mode).
DATSIZE0: Ch. 0 transfer data size (DE) / Ch. 0 high-order source ad dress reg ister (0x48226)
DATSIZE1: Ch. 1 transfer data size (DE) / Ch. 1 high-order source ad dress reg ister (0x48236)
DATSIZE2: Ch. 2 transfer data size (DE) / Ch. 2 high-order source ad dress reg ister (0x48246)
DATSIZE3: Ch. 3 transfer data size (DE) / Ch. 3 high-order source address register (0x48256)
Select the data size to be transferred.
Write "1": Half-word (16 bits)
Write "0": Byte (8 bits)
Read: Valid
The transfer data size is set to 16 bits by writing "1" to DATSIZEx and set to 8 bits by writing "0".
At initial reset, DATSIZEx is set to "0" (8 bits).
S0IN1–S0IN0: Ch. 0 source address control (D[D:C]) / Ch. 0 high-order source address set-up register (0x48226)
S1IN1–S1IN0: Ch. 1 source address control (D[D:C]) / Ch. 1 high-order source address set-up register (0x48236)
S2IN1–S2IN0: Ch. 2 source address control (D[D:C]) / Ch. 2 high-order source address set-up register (0x48246)
S3IN1–S3IN0: Ch. 3 source address control (D[D:C]) / Ch. 3 high-order source address set-up register (0x48256)
Control the incrementing or decrementing of the memory address.
Table 2.8 Address Control
SxIN1 SxIN0 Address control
11Increment without initialization
10Increment with initialization
01Decrement without initialization
00Fixed
In dual-address mode, this setting applies to the source address. In single-address mode, this setting applies to the
external memory address.
When "address fixed" (00) is selected, the source address is not changed by a data transfer performed. Even when
transferring multiple data, the transfer data is always read from the same address.
When "address increment" (11 or 10) is selected in single and successive transfer modes, the source address is
incremented by an amount equal to the data size set by DATSIZEx when one data transfer is completed.
When "address decrement" (01) is selected, the source address is decremented in the same way.
In block transfer mode too, the source address is incremented or decremented when one data unit is transferred.
However, if SxIN is set to "10", the source address that has been incremented during a block transfer recycles back
to the initial value when the block transfer is completed.
At i nitial reset, SxIN is set to "00" (Fixed).
V DMA BLOCK: HSDMA (Hi gh-Speed DMA)
B-V-2-32 EPSON S1C33L03 FUNCTION PART
D0IN1–D0IN0: Ch . 0 destinat ion addres s cont rol (D[D :C]) / Ch. 0 high-or der de stinat ion address s et-up re gist er (0x48 22A)
D1IN1–D1IN0: Ch . 1 destinat ion addres s cont rol (D[D :C]) / Ch. 1 high-or der de stinat ion address s et-up re gist er (0x48 23A)
D2IN1–D2IN0: Ch . 2 de st i nat i on address c ont rol (D[D :C ]) / Ch. 2 high-order desti nation address set- up regi st er (0x4824A)
D3IN1–D3IN0: Ch . 3 destinat ion addres s cont rol (D[D :C]) / Ch. 3 high-or der de stinat ion address s et-up re gist er (0x48 25A)
Control the incrementing or decrementing of the memory address.
Table 2.9 Address Control
DxIN1 DxIN0 Address control
11Increment without initialization
10Increment with initialization
01Decrement without initialization
00Fixed
In dual-address mode, this setting applies to the destination address. In single-address mode, these bits are not
used.
When "address fixed" (00) is selected, the destination address is not changed by a data transfer performed. Even
when transf erring multiple data, the transfer data is always written to the same address.
When "address increment" (11 or 10) is selected in single and successive transfer modes, the destination address is
incremented by an amount equal to the data size set by DATSIZEx when one data transfer is completed.
When "address decrement" (01) is selected, the destination address is decremented in the same way.
In block transfer mode too, the destination address is incremented or decremented when one data unit is transferred.
However, if DxIN is set to "10", the destination address that has been incremented during a block transfer recycles
back to the initial value when the block transfer is completed.
At i nitial reset, DxIN is set to "00" (Fixed).
BLKLEN07–BLKLEN00: Ch . 0 bloc k length/transf er counter[7: 0] (D[7 :0]) / Ch. 0 trans f e r count er regist er (0x48220)
BLKLEN17–BLKLEN10: Ch . 1 bloc k length/transf er counter[7: 0] (D[7 :0] ) / Ch. 1 t ransfe r count er regist er (0x48230)
BLKLEN27–BLKLEN20: Ch . 2 bloc k length/transf er c ounter[ 7:0] (D[7 :0] ) / Ch . 2 trans fer c ounter re gi ster (0x48240)
BLKLEN37–BLKLEN30: Ch . 3 bloc k length/transf er counter[7: 0] (D[7 :0] ) / Ch. 3 t ransfe r count er regist er (0x48250)
In block transfer mode, these bits are used to specify a transfer block size. A transfer operation invoked by one
trigger is completed after transferring one block of data of the size set by BLKLENx.
In single or successive transfer mode, these bits are used to specifythe 8 low-order bits of the transfer counter.
At i nitial reset, these bits are not initialized.
TC0_L7–TC0_L0:Ch. 0 tran sf er c ou nt er[ 7: 0] /[1 5: 8] (D[F :8 ]) / C h. 0 transfer co u nter register (0 x48220)
TC0_H7–TC0_H0:Ch. 0 transfer counter[15:8]/[23:16] (D[7:0]) / Ch. 0 control register (0x48222)
TC1_L7–TC1_L0:Ch. 1 tran sf er c ou nt er[ 7: 0] /[1 5: 8] (D[F :8 ]) / C h. 1 transfer co u nter register (0 x48230)
TC1_H7–TC1_H0:Ch. 1 transfer counter[15:8]/[23:16] (D[7:0]) / Ch. 1 control register (0x48232)
TC2_L7–TC2_L0:Ch. 2 tran sf er c ou nt er[ 7: 0] /[1 5: 8] (D[F :8 ]) / C h. 2 transfer co u nter register (0 x48240)
TC2_H7–TC2_H0:Ch. 2 transfer counter[15:8]/[23:16] (D[7:0]) / Ch. 2 control register (0x48242)
TC3_L7–TC3_L0:Ch. 3 tran sf er c ou nt er[ 7: 0] /[1 5: 8] (D[F :8 ]) / C h. 3 transfer co u nter register (0 x48250)
TC3_H7–TC3_H0:Ch. 3 transfer counter[15:8]/[23:16] (D[7:0]) / Ch. 3 control register (0x48252)
Set the data transfer count.
In block transfer mode, TCx_L[7:0] is bits[7:0] of the transfer cou nter, and TCx_H[7:0] is bit s[15:8] of the transfer
counter.
In single or successive transfer mode , TCx_L[7:0] is bits[15:8] of the transfer counter, and TCx_H[ 7:0] is
bits[23:16] of the transfer c ounter. The 8 low-order bits are specified by BLKLENx[7:0].
This cou nter is decremented each time a DMA transfer in the corresponding channel is performed. When the
counter reaches 0, an interrupt factor is generated. In single-address mode, the end-of-transfer signal is output from
the #DMAENDx pin at the same time.
Even when the cou nter is 0, a DMA request is accepted and the counter is decremented to "0xFFFF" (or
"0xFFFFFF").
Be sure to disable DMA transfers (HSx_EN = "0") before writing and reading to and from the counter.
At i nitial reset, these bits are not initialized.
V DMA BLOCK: HSDMA (Hi gh-Speed DMA)
S1C33L03 FUNCTION PART EPSON B-V-2-33
A-1
B-V
HSDMA
S0ADRL15–S0ADRL0:Ch. 0 source address[15:0]
(D[F :0 ]) / C h. 0 low-or der s ou rc e address set-up register (0x48224)
S0ADRH11–S0ADRH0:Ch. 0 source address[27:16]
(D[B:0]) / Ch. 0 high-order source addr ess se t-up register (0x48226)
S1ADRL15–S1ADRL0:Ch. 1 source address[15:0]
(D[F :0 ]) / C h. 1 low-or der s ou rc e address set-up register (0x48234)
S1ADRH11–S1ADRH0:Ch. 1 source address[27:16]
(D[B:0]) / Ch. 1 high-order source addr ess se t-up register (0x48236)
S2ADRL15–S2ADRL0:Ch. 2 source address[15:0]
(D[F :0 ]) / C h. 2 low-or der s ou rc e address set-up register (0x48244)
S2ADRH11–S2ADRH0:Ch. 2 source address[27:16]
(D[B:0]) / Ch. 2 high-order source addr ess se t-up register (0x48246)
S3ADRL15–S3ADRL0:Ch. 3 source address[15:0]
(D[F :0 ]) / C h. 3 low-or der s ou rc e address set-up register (0x48254)
S3ADRH11–S3ADRH0:Ch. 3 source address[27:16]
(D[B:0]) / Ch. 3 high-order source addr ess se t-up register (0x48256)
In dual-address mode, these bits are used to specify a source address. In single-address mode, an external memory
address at the destination or source of transfer is specified.
Use SxADRL t o set the 16 low-order bits of the address and SxADRH to set the 12 high-order bits.
Be sure to disable DMA transfers (HSx_EN = "0") before writing or reading to and from these registers.
The add ress is incremented or decremented (as set by SxIN) according to the transfer data size each time a DMA
transfer in the corresponding channel is performed.
At i nitial reset, these bits are not initialized.
D0ADRL15–D0ADRL0:Ch. 0 de stinatio n address[15:0]
(D[F :0 ]) / C h. 0 low-or de r d estin at ion addr ess se t-up regis ter (0x48228)
D0ADRH11–D0ADRH0:Ch. 0 destination address[27:16]
(D[B:0]) / Ch. 0 high-order destination ad dress set-up register (0x 4822A )
D1ADRL15–D1ADRL0:Ch. 1 de stinatio n address[15:0]
(D[F :0 ]) / C h. 1 low-or de r d estin at ion addr ess se t-up regis ter (0x48238)
D1ADRH11–D1ADRH0:Ch. 1 destination address[27:16]
(D[B:0]) / Ch. 1 high-order destination ad dress set-up register (0x 4823A )
D2ADRL15–D2ADRL0:Ch. 2 de stinatio n address[15:0]
(D[F :0 ]) / C h. 2 low-or de r d estin at ion addr ess se t-up regis ter (0x48248)
D2ADRH11–D2ADRH0:Ch. 2 destination address[27:16]
(D[B:0]) / Ch. 2 high-order destination ad dress set-up register (0x 4824A )
D3ADRL15–D3ADRL0:Ch. 3 de stinatio n address[15:0]
(D[F :0 ]) / C h. 3 low-or de r d estin at ion addr ess se t-up regis ter (0x48258)
D3ADRH11–D3ADRH0:Ch. 3 destination address[27:16]
(D[B:0]) / Ch. 3 high-order destination ad dress set-up register (0x 4825A )
In dual-address mode, these bits are used to specify a destination address. In single-address mode, these bits are not
used.
Be sure to disable DMA transfers (HSx_EN = "0") before writing or reading to and from these registers.
The add ress is incremented or decremented (as set by DxIN) according to the transfer data size each time a DMA
transfer in the corresponding channel is performed.
At i nitial reset, these bits are not initialized.
PHSD0L2–PHSD0L0: Ch. 0 interrupt level (D[2:0]) / HSDMA Ch. 0/1 interrupt priority register (0x40263)
PHSD1L2–PHSD1L0: Ch. 1 interrupt level (D[6:4]) / HSDMA Ch. 0/1 interrupt priority register (0x40263)
PHSD2L2–PHSD2L0: Ch. 2 interrupt level (D[2:0]) / HSDMA Ch. 2/3 interrupt priority register (0x40264)
PHSD3L2–PHSD3L0: Ch. 3 interrupt level (D[6:4]) / HSDMA Ch. 2/3 interrupt priority register (0x40264)
Set the priority level of an end-of-DMA interrupt in the range of 0 to 7.
At i nitial reset, these registers become indeterminate.
V DMA BLOCK: HSDMA (Hi gh-Speed DMA)
B-V-2-34 EPSON S1C33L03 FUNCTION PART
EHDM0: Ch. 0 interrupt enable (D0) / DMA interrupt enable regist er (0x40271)
EHDM1: Ch. 1 interrupt enable (D1) / DMA interrupt enable regist er (0x40271)
EHDM2: Ch. 2 interrupt enable (D2) / DMA interrupt enable register (0x40271)
EHDM3: Ch. 3 interrupt enable (D3) / DMA interrupt enable regist er (0x40271)
Enable or disable interrupt g ene ra tio n to the CPU.
Write "1": Inte rrupt enabled
Write "0": Inte rrupt disabled
Read: Valid
EH DM x is the interrupt enable bit for HSDMA channel x. The interrupt is enabled when EHDMx is set to "1" and
disabled when EHDMx is set to "0".
At i nitial reset, EHDMx is set to "0" (interrupt disabled).
FHDM0: Ch. 0 interrupt factor flag (D0) / DMA interrupt factor flag register (0x40281)
FHDM1: Ch. 1 interrupt factor flag (D1) / DMA interrupt factor flag register (0x40281)
FHDM2: Ch. 2 interrupt factor flag (D2) / DMA interrupt factor flag register (0x40281)
FHDM3: Ch. 3 interrupt factor flag (D3) / DMA interrupt factor flag register (0x40281)
Indicate the occurrence status of HSDMA interrupt factor.
When read
Read "1": Interrupt factor generated
Read "0": No inte rrupt fa cto r g ene ra ted
When written using the rese t-onl y m etho d (d ef au lt)
Write "1": Factor flag is reset
Write "0": Invalid
When written using the read /w rite m et ho d
Write "1": F actor flag is set
Write "0": Factor flag is reset
FHDMx is the interrupt factor flag for HSDMA channel x. These flags are set to "1" when the transfer counter
reaches 0. An interrupt to the CPU is generated if the following conditions are met at this time:
1. The corresponding interrupt enable register is set to "1".
2. No other interrupt request of hi ghe r priority is generated.
3. The IE bit of the PSR is set to "1" (interrupt enable).
4. The corresponding interrupt priori ty register is set to a level higher than the CPU's interrupt level (IL).
When using an interrupt factor to request IDMA, note that even when the above conditions are met, no interrupt
request to the CPU is generated for the interrupt factor that has occurred. If interrupts are enabled at the setting of
the IDMA side, an interrupt is generated under the above conditions after the data transfer by IDMA is completed.
The interrupt factor flag is always set to "1" when an interrupt factor occurs no matter how the interrupt enable and
inte rrupt p rio rity regi ste rs are set.
In order for the next interrupt to be accepted after interrupt generation, the interrupt factor flag must be reset and
the PSR must be set up again (by setting the IL below the level indicated by the interrupt priority register and
setting the IE bit to "1" or executing the reti instruction).
The interrupt factor flag can only be reset by a write instruction in the software application. If the PSR is again set
up to accept interrupts (or the reti instruction is executed) without resetting the interrupt factor flag, the same
interrupt may occur again. Note also that the value to be written to reset the flag is "1" when using the reset-only
meth od (RST ONLY = "1") and "0" when using t he read/ write me thod (RSTONLY = " 0"). Be car ef ul not to
confuse these two cases.
The FHDM x flag be comes indeterminate when initially reset, so be sure to reset the flag in the software
application.
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HSDMA
RHDM0: Ch.0 IDMA r eques t ( D4) / Po rt i np ut 0– 3, H SD MA, 16 - bit t imer 0 ID MA r eques t reg iste r (0x 402 90 )
RHDM1: Ch.1 IDMA r eques t ( D5) / Po rt i np ut 0– 3, H SD MA, 16 - bit t imer 0 ID MA r eques t reg iste r (0x 402 90 )
Specify whether IDM A nee d to b e invo ke d w h en an inte rrupt fa ctor o ccurs .
When using the se t-o n ly m et ho d (d ef ault)
Write "1": IDMA request
Write "0": Not changed
Read: Valid
When using the read /w rite m et ho d
Write "1": IDMA request
Write "0": Inte rrupt request
Read: Valid
RHDM0 and RHDM1 are the IDMA request bits for HSDMA channels 0 and 1, respectively. If the bit is set to "1",
IDMA is invoked when an interrupt factor occurs, thus performing a programmed data transfer. If the register is set
to "0", regular interrupt processing is performed without ever invoking IDMA.
For details on IDMA, refer to "IDMA (Intelligent DMA)".
At i nitial reset, RHDMx is set to "0" (interrupt request).
DEHDM0: Ch .0 IDMA enabl e ( D4) / Port inp ut 0– 3, HS DMA, 16- bit t imer 0 IDMA en ab le r eg iste r ( 0x 40294 )
DEHDM1: Ch .1 IDMA enabl e ( D5) / Port inp ut 0– 3, HS DMA, 16- bit t imer 0 IDMA en ab le r eg iste r ( 0x 40294 )
Enables ID M A transfer by means of an interrupt factor.
When using the se t-o n ly m et ho d (d ef ault)
Write "1": IDMA enabled
Write "0": Not changed
Read: Valid
When using the read /w rite m et ho d
Write "1": IDMA enabled
Write "0": IDMA disabled
Read: Valid
DEHDM0 and DEHDM1 are t he IDMA ena bl e bits for HS DMA channels 0 and 1, respectively. If DEHDMx is set
to "1", the IDMA request by the interrupt factor is enabled. If the bit is set to "0", the IDMA request is disabled.
At i nitial reset, DEHDMx is set to "0" (IDMA disabled).
V DMA BLOCK: HSDMA (Hi gh-Speed DMA)
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Pr ogramming Notes
(1) When setting the transfer conditions, always make sure the DMA controller is inactive (HSx_EN = "0").
(2) After an initial reset, the interrupt factor flag (FHDMx) becomes indeterminate. Always be sure to reset the
flag to prevent interrupts or IDMA requests from being generated inadvertently.
(3) To prevent an interrupt from being generated repeatedly for the same factor, be sure to reset the interrupt
factor flag before setting up the PSR again or executing the reti instruction.
(4) HSDMA is given higher priority over IDMA (intelligent DMA) and the CPU. However, since HSDMA and
IDMA share the same circuit, HSDMA cannot gain the bus ownership while an IDMA transfer is under way.
Requ ests for HSDMA invocation that have occurred during an IDMA transfer are kept pending until the
IDMA transfer is completed.
A req uest for IDMA invocation or an interrupt request that has occurred during a HSDMA transfer are
accepted after completion of the HSDMA transfer.
(5) In HALT mode, since the DMA and BCU clocks operate, if the next operation is performed in HALT mode,
not HALT2 mode, with a settin g of 0 in clock option regis ter HLT2OP (D3 /0x40190), that operati on wi ll be
an unpredictable erroneous operation.
If a DMA trigger occurs and DMA is invoked while the CPU is stopped after HALT mode execution,
erroneous operation will result. Ensure that DMA is not invoked in HALT mode.
In HALT2 mode, DMA is not invoked since the DMA and BCU clocks are stopped.
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IDMA
V-3 IDMA (Intelligent DMA)
Functional Outline of IDMA
The DMA Block contains an intelligent DMA (IDMA), a function that allows control information to be
programmed in RAM. Up to 128 channels can be programmed, including 31 channels that are invoked by an
interrupt factor that occurs in some internal peripheral circuit.
Although an additional overhead for loading and storing control information in RAM may be incurred, this
intelligent DMA supports such functions as successive transfers, block transfers, and linking to another IDMA.
IDMA is invoked by an interrupt factor that occurs in some internal peripheral circuit or a software trigger, thereby
performing a data transfer according to the control information in RAM. When the transfer is completed, IDMA
can generate an interrupt or invoke another IDMA according to link settings.
Programming Control Inf orm ation
The intelligent DMA operates according to the control information prepared in RAM. The control information can
be stored in either internal RAM or external RAM should the necessary area be allocated.
The con trol information is 3 words (12 bytes) per channel in size, and must be located at contiguous addresses
beginning with the base address that is set in the software application as the starting address of channel 0.
Conseq uently, an area of 384 words (1,536 bytes) in RAM is required in order for all of 128 cha nnels to be used.
The following explains how to set the base address and the contents of control information. Before using IDMA,
make each the settings des cribed below .
Setting the base address
Set the starting address of control information (starting address of channel 0) in the IDMA base address
register.
16 low- order bits: DBASEL[15:0] (D[F:0]) / IDMA base address low-order register (0x48200)
12 high-order bits: DBASEH[11:0] (D[B:0]) / IDMA base address high-order register (0x48202)
When initially reset, the base address is set to 0x0C003A0.
Notes:•The address you set in the IDMA base address register must always be a wo rd (32-bit )
boundary address.
•Be sure to disable DMA transfers (IDMAEN = "0") before setting the base addres s. Wr iting t o the
IDMA base address regis ter is i gnored when th e DM A t r ansfer is enabled (IDM AEN = "1 " ).
When the register is read, the read data is indeterminate.
Control informati on
Write the control information for the IDMA channels used to RAM.
The add resses at which the control information of each channel is placed are determined by the base address
and a chan nel num be r.
Starti ng address of channel = base address + (chann el number × 12 [bytes])
Note:The control information must be written only when the channel to be set does not start a DMA
transfer. If a DMA transfer starts when the control information is being written to the RAM, proper
transfer c an not performed. Reading the control informa ti on ca n always be done.
V DMA BLOCK: IDMA (Intelligent DMA)
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The con tents of control information (3 words) in each channel are shown in the table below.
Table 3.1 IDMA Control Information
Word Bit NameFunction
1st D31 LNKEN IDMA link enable "1" = Enabled, "0" = Disabled
D30–24 LNKCHN[6:0] IDMA link field
D23–8 TC[15:0] Transfer counter (block transfer mode)
Transfer counter - high-order 16 bits (single or successive transfer mode)
D7–0 BLKLEN[7:0] Block size (block transfer mode)
Transfer counter - low-order 8 bits (single or successive transfer mode)
2nd D31 DINTEN End-of-transfer interrupt enable "1" = Enabled, "0" = Disabled
D30 DATSIZ Data size control "1" = Half-word, "0" = Byte
D29–28 SRINC[1:0] Source address control
SRINC1 SRINC0 Setting contents
11Address incremented
(In block transfer mode, the transfer address is
updated without reset using the initial value.)
10Address incremented
(In block transfer mode, the transfer address is
updated with the initial value.)
01Address decremented
(In block transfer mode, the transfer address is
updated without reset using the initial value.)
00Address fixed
D27–0 SRADR[27:0] Source address
3rd D31–30 DMOD[1:0] Transfer mode (Do not set to "11".)
DMOD1 DMOD0 Setting contents
10Block transfer mode
01Successive transfer mode
00Single transfer mode
D29–28 DSINC[1:0] Destination address control
DSINC1 DSINC0 Settin g contents
11Address incremented
(In block transfer mode, the transfer address is
updated without reset using the initial value.)
10Address incremented
(In block transfer mode, the transfer address is
updated with the initial value.)
01Address decremented
(In block transfer mode, the transfer address is
updated without reset using the initial value.)
00Address fixed
D27–0 DSADR[27:0] Destination address
LN KEN: IDMA link enable (D31/1st Word)
If this bit remains set (= "1"), the IDMA channel that is set in the IDMA link field is invoked after the
com pl eti on of a DMA tr an sfe r in this ch an ne l. D M A tr an sfe rs in mul tip le ch an ne ls can b e perf orm e d
successively by merely triggering the first channel to be executed. There is no limit to the number of channels
linked. Set this link in order of the IDMA channels you want to be executed.
If this bit is "0", IDMA is completed by merely executing a DMA transfer in this channel.
LN KCHN[6:0 ]: IDMA link field (D[ 30:24] /1st Word)
If you want IDM A to be linked, set the channel numbers (0 to 127) to be executed next.
The data in this field is valid only when LINKEN = "1".
TC [15:0]: Tran sfer coun ter (D[23:8]/1st Word)
In block transfer mode, a transfer count can be specified using up to 16 bits. Set this value here. In single
transfer and successive transfer modes, a transfer count can be specified using up to 24 bits. Set a 16-bit high-
order value here.
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BLKLEN[7:0]: Blo ck size/transf e r counter (D[7:0]/1st Word)
In block transfer mode, set the size of a block that is transferred in one operation (in units of DATSIZ). In
single transfer and successive transfer modes, set an 8-bit low-order value for the transfer count here.
Note: The transfer count and block size thus set are decrem ented acco rding t o the transfers performed.
If the transfer count or block size is set to 0, it is decremented to all Fs by the first transfer
performed. This means that you have set the ma ximum value that is determined by the number of
bits avai lable.
DINTEN: End-of-t ransfer inte rrup t enabl e (D 3 1/ 2n d Wo rd )
If this bit is left set (= "1"), when the transfer counter reaches 0, an interrupt request to the CPU is generated
based on the interru pt facto r flag by which IDMA has been invoked.
If this bit is "0", no interrupt request to the CPU is generated even when the transfer counter has reached 0.
DATSIZ: Data size control (D30/2nd Word)
Set the unit size of data to be transferred.
A hal f-word size (16 bits) is assumed if this bit is "1" and a byte size (8 bits) is assumed if this bit is "0".
SR INC[1:0]: So urce address control (D[29:28]/2 nd Word)
Set the source address updating format.
If the format is set for "address fixed" (00), the source address is not changed by a data transfer performed.
Even when transferring multiple data, the transfer data is always read from the same address.
If the format is set for "address increment" (11 or 10) in single and successive transfer modes, the source
address is incremented by an amount equal to the data size set by DATSIZ when one data transfer is
completed. If the format is set for "address decrement" (01), the source address is decremented in the same
way.
In block transfer mode too, the source address is incremented or decremented when one data unit is
transferred. However, if the set format is "10", the source address that has been incremented during a block
transfer recycles back to the initial value when the block transfer is completed.
SR ADR[27:0]: So urce address (D[27: 0]/2nd Word)
Use these bits to set the starting address at the source of transfer. The content set here is updated according to
the setting of SRINC.
DMOD[1:0]: Transfer mode (D[31:30]/3 rd Wor d)
Use these bits to set the desired transfer mode.
The transfer modes are outlined below (to be detailed later):
• Single transfer mode (00)
In this mode, a transfer operation invoked by one trigger is completed after transferring one unit of data of
the size set by DATSIZ. If data transfer need to be performed a number of times as set by the transfer
counter, an equal number of triggers are required.
• Successive transf er mode (01)
In this mode, data transfer operations are perform ed by one trigger a number of times as set by the transfer
counter. The transfer counter is decremented to 0 each time data is transferred.
• Block transfer mode (10)
In this mode, a transfer operation invoked by one trigger is completed after transferring one block of data
of the size set by BLKL EN. If a block tra nsfer need to be performed a number of tim es as set by the
transfer counter, an equal number of triggers are required.
V DMA BLOCK: IDMA (Intelligent DMA)
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DS INC[1: 0]: Destinat ion address control (D[29:28]/3rd Word)
Set the destination address update format.
If the format is set for "address fixed" (00), the destination address is not changed by the performance of a
data transfer operation. Even when transferring multiple data, the transfer data is always written to the same
address.
If the format is set for "address increment" (11 or 10) in single and successive transfer modes, the destination
address is incremented by an amount equal to the data size set by DATSIZ when one data transfer is
completed. If the format is set for "address decrement" (01), the destination address is decremented in the
same way.
In block transfer mode as well, the destination address is incremented or decremented when one data unit is
transferred. However, if the set format is "10", the destination address that has been incremented during a
block transfer recycles back to the initial value when the block transfer is completed.
DS ADR[27:0]: Destinat ion address (D[27:0]/3rd Word)
Use these bits to set the starting address at the destination of transfer. The content set here is updated
according to the setting of DSINC.
Since the control information is placed in RAM, it can be rewritten. However, before rewriting the content of
this information, make sure that no DMA transfer is generated in the channel whose information you are
going to rewrite.
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IDMA
IDMA Invocation
The triggers by which IDMA is invoked have the following three causes:
1. Interrupt factor in an internal peripheral circuit
2. Trigger in the software application
3. Link setting
Enabling/di sabling DMA transfer
The IDMA controller is enabled by writing "1" to the IDMA enable bit IDMAEN (D0) / IDMA enable
register (0x48205), and is ready to accept the triggers described above. However, before enabling a DMA
transfer, be sure to set the base address and the control information for the channel to be invoked correctly. If
IDMAEN is set to "0", no IDMA invocation request is accepted.
IDMA invocation by an interrupt factor in internal peripheral circuits
Some internal peripheral circuits that have an interrupt generating function can invoke IDMA by an interrupt
factor in that circuit. The IDMA channel numbers corresponding to such IDMA invocation are predetermined.
The relationship between the interrupt factors that have this function and the IDMA channels is shown in
Table 3.2.
Table 3.2 Interrupt Factors Used to Invoke IDMA
Peripheral circuit Interrupt factor IDMA Ch. IDMA request bit IDMA enable bit
Ports Port input 0 1 RP0 (D0/0x40290) DEP0 (D0/0x40294)
Port input 1 2 RP1 (D1/0x40290) DEP1 (D1/0x40294)
Port input 2 3 RP2 (D2/0x40290) DEP2 (D2/0x40294)
Port input 3 4 RP3 (D3/0x40290) DEP3 (D3/0x40294)
High-speed DMA Ch.0, end of transfer 5 RHDM0 (D4/0x40290) DEHDM0 (D4/0x40294)
Ch.1, end of transfer 6 RHDM1 (D5/0x40290) DEHDM1 (D5/0x40294)
16-bit programmable Timer 0 comparison B 7 R16TU0 (D6/0x40290) DE16TU0 (D6/0x40294)
timer Timer 0 comparison A 8 R16TC0 (D7/0x40290) DE16TC0 (D7/0x40294)
Timer 1 comparison B 9 R16TU1 (D0/0x40291) DE16TU1 (D0/0x40295)
Timer 1 comparison A 10 R16TC1 (D1/0x40291) DE16TC1 (D1/0x40295)
Timer 2 comparison B 11 R16TU2 (D2/0x40291) DE16TU2 (D2/0x40295)
Timer 2 comparison A 12 R16TC2 (D3/0x40291) DE16TC2 (D3/0x40295)
Timer 3 comparison B 13 R16TU3 (D4/0x40291) DE16TU3 (D4/0x40295)
Timer 3 comparison A 14 R16TC3 (D5/0x40291) DE16TC3 (D5/0x40295)
Timer 4 comparison B 15 R16TU4 (D6/0x40291) DE16TU4 (D6/0x40295)
Timer 4 comparison A 16 R16TC4 (D7/0x40291) DE16TC4 (D7/0x40295)
Timer 5 comparison B 17 R16TU5 (D0/0x40292) DE16TU5 (D0/0x40296)
Timer 5 comparison A 18 R16TC5 (D1/0x40292) DE16TC5 (D1/0x40296)
8-bit programmable Timer 0 underflow 19 R8TU0 (D2/0x40292) DE8TU0 (D2/0x40296)
timer Timer 1 un der f low 20 R8TU 1 (D 3/0 x4 0292) DE 8TU 1 (D3/0 x4 029 6)
Timer 2 un der f low 21 R8T U2 ( D4/0x4 0292) DE 8TU 2 (D4/0 x4 029 6)
Timer 3 un der f low 22 R8T U3 ( D5/0x4 0292) DE 8TU 3 (D5/0 x4 029 6)
Serial interface Ch.0 receive bu ffer f u ll 23 RS R X0 (D6/0 x4 029 2) D ES RX 0 (D6/0 x4 029 6)
Ch.0 transmit buffer empty 24 RS TX0 ( D7/ 0 x4 029 2) D ES TX0 ( D7/0x4 0296)
Ch.1 rec eive bu ffer full 25 RSRX1 (D0/0x40293) DESRX1 (D0/0x40297)
Ch.1 transmit buffer empty 26 RS TX1 ( D1/ 0 x4 029 3) D ES TX1 ( D1/0x4 0297)
A/D converter End of A/D conversion 27 RADE (D2/0x40293) DEADE (D2/0x40297)
Ports Port input 4 28 RP4 (D4/0x40293) DEP4 (D4/0x40297)
Port input 5 29 RP5 (D5/0x40293) DEP5 (D5/0x40297)
Port input 6 30 RP4 (D6/0x40293) DEP4 (D6/0x40297)
Port input 7 31 RP7 (D7/0x40293) DEP7 (D7/0x40297)
V DMA BLOCK: IDMA (Intelligent DMA)
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These interrupt factors are used in common for interrupt requests and IDMA invocation requests.
To invoke IDMA upon the occurrence of an interrupt factor, set the corresponding bits of the IDMA request
and IDMA enable registers shown in the table by writing "1". Then when an interrupt factor occurs, an
interrupt request to the CPU is kept pending and the corresponding IDMA channel is invoked.
The interrupt factor flag that has been set to "1" remains set until the DMA transfer invoked by it is
completed. If the following two conditions are met when one DMA transfer is completed, an interrupt request
is generated without resetting the interrupt factor flag.
• The transfer counter has reached 0.
• DINT EN in control information is set to "1" (interrupt enabled).
In this case, the IDMA request register is cleared to "0". Therefore, if IDMA needs to be invoked when an
interrupt factor occurs next time, this register must be set up again. To prevent unwanted IDMA requests
from being generated, this setting must be performed before enabling interrupts and after resetting the
interrupt factor flag. The IDMA enable bit is not cleared and remains set to "1".
If the transfer counter is not 0, the interrupt factor flag is reset when the DMA transfer is completed, so that
no interrupt is generated. In this case, the IDMA request bit and IDMA enable bit are not cleared and remain
set to "1".
When DINTEN in c ontrol information has been set to "0", the interrupt factor flag is reset even if the transfer
counter reaches 0, so that no interrupt is generated. In this case, the IDMA request bit is not cleared but the
IDMA enable bit is cleared.
If the IDMA request register bit is left reset to "0", the relevant interrupt factor generates an interrupt request
and n ot a ID M A reque st .
The con trol registers (interrupt enable register and interrupt priority register) corresponding to the interrupt
factor do not affect IDMA invocation. IDMA can be invoked even if the interrupt enable bit in ITC is set to
"0" (interrupt disab led ). However, the se r egister must be set to enable the interrupt when generating the
interrupt after completing the DMA transfer.
IDMA invocation by a trigger in the software application
All IDMA channels for which control information is set, including those corresponding to interrupt factors
described abo ve, can be invoked by a trigger in the software app lication.
The following bits are used for this control:
IDMA channel number set-up: DCHN[6:0] (D[6:0]) / IDMA start register (0x48204)
IDMA start control: DSTART (D7) / IDMA start register (0x48204)
When th e IDMA channel number to be invoked (0 to 127) is written to DCHN and DSTART is set to "1", the
specified IDMA channel starts a DMA transfer.
DSTART remains set (= "1") during a DMA transfer and is reset to "0" in hardware when one DMA transfer
operation is completed.
Do not modify these b its d uri ng a DMA tr an sfer.
If DINTEN is set to "1" (interrupt enabled), an interrupt factor for the completion of IDMA transfer is
generated w hen one DMA tran sfer is com pl ete d.
IDMA invocation by link setting
If LNKEN in the control information is set to "1" (link enabled), the IDMA channel that is set in the IDMA
link field "LNKCHN" is invoked successively after a DMA transfer in the link-enabled channel is completed.
The interrupt request by the first channel is generated after transfers in all linked channels are completed if
the inte rru pt co nd ition s are met .
To generate an interrupt at the end of an IDMA transfer, the DINTEN (end-of-transfer interrupt enable) bits
in the IDMA control information for the first IDMA channel to be invoked and all the channels to be linked
must be set to "1".
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IDMA invocation request during a DMA transfer
An IDMA invocation request to another channel that is generated during a DMA transfer is kept pending until
the DMA transfer that was being executed at the time is completed. Since an invocation request is not cleared,
new requests will be accepted when the DMA transfer under execution is completed.
An IDMA invocation request to the same channel canot be accepted while the channel is executing a DMA
transfer because the same interrupt factor is used. Therefore, an interval longer than the DMA transfer period
is required when invoking the same channel.
IDMA invocation request when DMA transfer is disabled
An IDMA invocation request generated when IDMAEN is "0" (DMA transfer disabled) is kept pending until
IDMAEN is set to "1". Since an invocation request is not cleared, it is accepted when DMA transfer is
enabled.
Simultaneous generation of a software trigger and a hardware trigger
When a software trigger and the hardware trigger for the same channel are generated simultaneously, the
software trigger starts IDMA transfer. The IDMA transfer by the hardware trigger is not executed since the
interrupt factor is reset when the DMA transfer is completed. However, an operation like this cannot be
recommended.
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Operation of IDMA
IDMA has three transfer modes, in each of which data transfer operates differently. Furthermore, an interrupt factor
is processed differ ent ly depen ding on the typ e of trigger. The following des cribes the operation of IDMA in each
transfer mode and how an interrupt factor is processed for each type of trigger.
Single transfer mode
The channels for which DMOD in control information is set to "00" operate in single transfer mode. In this
mode , a transfer operation invoked by one trigger is completed after transferring one data unit of the size set
by D ATSI Z . If a data tra nsfer needs to be performed a number of times as set by the transfer counter, an
equal number of triggers are required.
The ope ration of IDMA i n single transfer mode is shown by the flow chart in Figure 3.1.
START
END
Calculates address of
control information
Loads channel
control information
Transfers one unit of data
Transfer counter - 1
Saves channel
control information
IDMA interrupt processing
(if interrupt is enabled)
Transfer
counter = 0
A
Base address + (Channel number × 12)
B (3 words)
C (Data read from source of transfer)
D (Data write to destination of transfer)
E
F (3 words)
N
Trigger
Y
AB1 B2 B3 C D E F1 F2 F3
Figur e 3.1 Operation Flow in Single Transfer Mode
(1) When a trigger is accepted, the address for control information is calculated from the base address and
channel number.
(2) Control information is read from the calculated address into the internal temporary register.
(3) Data of the size set in the control information is read from the source address.
(4) The read data is written to the destination address.
(5) The address is incremented or decremented and the transfer counter is decremented.
(6) The modified control information is written to RAM.
(7) In the case of a hardware trigger, the interrupt control bits are processed before completing IDMA.
Condition Interrupt factor flag IDMA request bit IDMA enable bit
Transfer counter ≠ "0": Reset ("0 ") Not changed ("1") Not changed ("1")
Transfer counter = "0", DINTEN = "1": Not changed ("1") Reset ("0") Not changed ("1")
Transfer counter = "0", DINTEN = "0": Reset ("0") Not changed ("1") Reset ("0")
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Successive transfer mode
The channels for which DMOD in control information is set to "01" operate in successive transfer mode. In
this mode, a data transfer is performed by one trigger a number of times as set by the transfer counter. The
transfer counter is decremented to "0" by one transfer executed.
The ope ration of IDMA i n successive transfer mode is shown by the flow chart in Figure 3.2.
START
END
Calculates address of
control information
Loads channel
control information
Transfers one unit of data
Transfer counter - 1
Saves channel
control information
IDMA interrupt processing
(if interrupt is enabled)
Transfer
counter = 0
A
Base address + (Channel number × 12)
B (3 words)
C (Data read from source of transfer)
D (Data write to destination of transfer)
E
F (3 words)
N
Trigger
Y
AB1 B2 B3 C1 D1 E1 Cn Dn En F1 F2 F3
Figur e 3.2 Operation Flow in Succes sive Transfer Mode
(1) When a trigger is accepted, the address for control information is calculated from the base address and
channel number.
(2) Control information is read from the calculated address into the internal temporary register.
(3) Data of the size set in the control information is read from the source address.
(4) The read data is written to the destination address.
(5) The address is incremented or decremented and the transfer counter is decremented.
(6) Steps (3) to (5) are repeated until the transfer counter reaches 0.
(7) The modified control information is written to RAM.
(8) In the case of a hardware trigger, the interrupt control bits are processed before completing IDMA.
Condition Interrupt factor flag IDMA request bit IDMA enable bit
Transfer counter ≠ "0": Reset ("0 ") Not changed ("1") Not changed ("1")
Transfer counter = "0", DINTEN = "1": Not changed ("1") Reset ("0") Not changed ("1")
Transfer counter = "0", DINTEN = "0": Reset ("0") Not changed ("1") Reset ("0")
V DMA BLOCK: IDMA (Intelligent DMA)
B-V-3-10 EPSON S1C33L03 FUNCTION PART
Block transfer mode
The channels for which DMOD in control information is set to "10" operate in block transfer mode. In this
mode , a transfer operation invoked by one trigger is completed after transferring one bloc k of dat a of the size
set by BLKLEN. If a block transfer needs to be performed a number of times as set by the transfer counter, an
equal number of triggers are required.
The ope ration of IDMA i n block transfer mode is shown by the flow cha rt in Fi gur e 3.3.
START
END
Calculates address of
control information
Loads channel
control information
Transfers one unit of data
Block size - 1
Restores initial values to
block size and address ∗
IDMA interrupt processing
(if interrupt is enabled)
Block
size = 0
A
Base address + (Channel number × 12)
B (3 words)
C (Data read from source of transfer)
D (Data write to destination of transfer)
E
1-block transfer
F
G
N
Trigger
Y
A B1 B2 B3 C1 D1 E1 Cn Dn En
F G
H1 H2 H3
Transfer counter - 1
Saves channel
control information
Transfer
counter = 0
H (3 words)
N
Y
∗: according to SRINC/DSINC
settings
Figur e 3.3 Operation Flow in Block Transfer Mode
(1) When a trigger is accepted, the address for control information is calculated from the base address and
channel number.
(2) Control information is read from the calculated address into the internal temporary register.
(3) Data of the size set in the control information is read from the source address.
(4) The read data is written to the destination address.
(5) The address is incremented or decremented and BLKLEN is decremented.
(6) Steps (3) to (5) are repeated until BLKLEN reaches 0.
(7) If SRINC and DSINC are "10", the address is recycled to the initial value.
(8) The transfer counter is decremented.
(9) The modified control information is written to RAM.
(10) In the case of a hardware trigger, the interrupt control bits are processed before completing IDMA.
Condition Interrupt factor flag IDMA request bit IDMA enable bit
Transfer counter ≠ "0": Reset ("0 ") Not changed ("1") Not changed ("1")
Transfer coun ter = "0", DINTEN = "1": Not changed ("1") Reset ("0") Not changed ("1")
Transfer counter = "0", DINTEN = "0": Reset ("0") Not changed ("1") Reset ("0")
V DMA BLOCK: IDMA (Intelligent DMA)
S1C33L03 FUNCTION PART EPSON B-V-3-11
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IDMA
Processing of i n terru pt factors by type of trigger
•When invoked by an interrupt factor
The interrupt factor flag by w hich IDMA has been invoked remains set even during a DMA transfer.
If the transfer counter is decremented to 0 and DINTEN = "1" (interrupt enabled) when one DMA transfer is
completed, the interrupt factor that has invoked IDMA is not reset and an interrupt request is generated. At
the same time, the IDMA request register is cleared to "0". The IDMA enable bit is not cleared and remains
set to "1".
If the transfer counter is not 0, the interrupt factor flag is reset when the DMA transfer is completed, so that
no interrupt is generated. In this case, the IDMA request bit and IDMA enable bit are not cleared and remain
set to "1".
When DINTEN has been set to "0" ( interrupt disabled), the interrupt factor flag is reset even if the transfer
counter reaches 0, so that no interrupt is generated. In this case, the IDMA request bit is not cleared but the
IDMA enable bit is cleared.
2 1 0
Trigger by interrupt factor
Data transfer
Transfer counter
DINTEN
IDMA request bit
IDMA enable bit
Interrupt factor flag
Interrupt request
1 0
Figur e 3.4 Operation when Invoked by Interrupt Factor
When IDMA is invoked by the software trigger, the IDMA interrupt factor flag FIDMA (D4)/DMA interrupt
factor flag register (0x40281) will not be set.
•When invoked by a software trigger
If the transfer counter is decremented to 0 and DINTEN = "1" (interrupt enabled) when one DMA transfer is
com pl ete d, th e IDM A inte rrupt fa cto r fl ag FID MA (D 4 )/D MA inte rru pt fa ctor flag registe r (0x4 0281 ) is set,
thereby generating an interrupt request.
If the transfer counter is not 0 or DINTEN = "0" (interrupt disabled), the FIDMA flag is not set.
If the interrupt factor flag for the same channel is set during a software-triggered transfer, the IDMA
invocation request by that interrupt factor flag is kept pending. However, the interrupt factor flag will be reset
when the current execution is completed, so there will be no DMA transfer by the interrupt factor flag.
2 1 0
Software trigger
Data transfer
Transfer counter
DINTEN
FIDMA (D4/0x40281)
Interrupt request
1 0
Figur e 3.5 Operation when Invoked by Software Trigger
V DMA BLOCK: IDMA (Intelligent DMA)
B-V-3-12 EPSON S1C33L03 FUNCTION PART
Linking
If the IDMA channel number to be executed next is set in the IDMA link field "LNKCHN" of control information
and LNKEN is set to "1" (link enabled), DMA successive transfer in that IDMA channel can be performed.
An example of link setting is shown in Figure 3.6.
Ch.3Trigger
After transfer TC = 0
LNKEN = 1
LNKCHN = 5
DMOD = 01
DINTEN = 1
TC = 1024
Ch.5
TC = 7
LNKEN = 1
LNKCHN = 7
DMOD = 00
DINTEN = 1
TC = 8
Ch.7
TC = 0
LNKEN = 0
LNKCHN = 9
DMOD = 10
DINTEN = 1
TC = 1
Figur e 3.6 Example of Link Setting
For the above example, IDMA operates as described below.
•For trigge r in hardw a re
(1) The IDMA channel 3 is invoked by an interrupt factor and the DMA transfer that is set is performed.
Since the IDMA is operating in successive transfer mode and the transfer counter is decremented to 0
and DINTEN is set to "1", the interrupt factor flag by which the channel 3 has been invoked remains set.
(2) Next, a DMA transfer is performed via the linked IDMA channel 5. Channel 5 is set for single transfer
mode and the transfer counter in this transfer is decremented by 1.
(3) Finally, a DMA transfer in IDMA channel 7 is performed. Although the channel 7 is set for block
transfer mode, the transfer counter is decremented to 0 when the transfer is completed because the
number of transfers to be per form ed is 1.
(4) Since the interrupt factor flag that has invoked IDMA channel 3 in (1) remains set, an interrupt is
generated w hen the IDM A transfer (channel 7) in (3) is completed. The transfer result does not affect the
interrupt factor flag of channel 3.
To generate an interrupt at the end of an IDMA transfer, the DINTEN (end-of-transfer interrupt enable)
bits in the IDMA control information for the first IDMA channel to be invoked and all the channels to be
linked must be set to "1".
•For trigg er in the software application
(1) The IDMA channel 3 is invoked by a trigger in the software application and the DMA transfer that is set
is performed.
Since the IDMA is operating in successive transfer mode and the transfer counter is decremented to 0
and DINTEN is set to "1", the IDMA interrupt factor flag FIDMA (D4)/DMA interrupt factor flag
register (0x40281) is set when the transfer is completed.
(2) Next, a DMA transfer is performed in the linked IDMA channel 5. The channel 5 is set for the single
transfer mode and the transfer counter in this transfer is decremented by 1.
(3) Finally, a DMA transfer in IDMA channel 7 is performed. Although channel 7 is set for the block
transfer mode, the transfer counter is decremented to 0 when the transfer is completed because the
number of trans fers to be perform ed is 1. The comp letion of this transfer also causes the FIDMA flag to
be set to "1" . However, the FIDMA flag has already been set when the transfer is completed in (1) above.
(4) Since the FIDMA flag is set, an interrupt request is generated here. In cases when IDMA has been
invoked by a trigger in the software application, if the transfer counter in any one of the linked channels
is decremented to 0 and DINTEN for that channel is set to "1", an interrupt request for the completion of
IDMA transfer is generated when a transfer operation in each of the linked channels is completed. The
channel in which an interrupt request has been generated can be verified by reading out the transfer
counter.
Transfer operations in each channel are performed as described earlier.
V DMA BLOCK: IDMA (Intelligent DMA)
S1C33L03 FUNCTION PART EPSON B-V-3-13
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IDMA
Inter ru pt Fu nc tion of Intelligent DMA
IDMA can generate an interrupt that causes invocation of IDMA and an interrupt for the completion of IDMA
transfer itself.
Interrupt when invoked by an i n terru pt factor
If the corresponding bits of the IDMA request and interrupt enable registers are left set (= "1"), assertion of an
interrupt request is kept pending even when the enabled interrupt factor has occurred and the IDMA channel
assigned to that interrupt factor is invoked.
If the transfer counter is decremented to 0 and DINTEN = "1" (interrupt enabled) when one DMA transfer is
completed, the interrupt factor that has invoked IDMA is not reset and an interrupt request is generated. At
the same time, the IDMA request register is cleared to "0". The IDMA enable bit is not cleared and remains
set to "1".
If the transfer counter is not 0, the interrupt factor flag is reset when the DMA transfer is completed, so that
no interrupt is generated. In this case, the IDMA request bit and IDMA enable bit are not cleared and remain
set to "1".
When DINTEN has been set to "0" ( interrupt disabled), the interrupt factor flag is reset even if the transfer
counter reaches 0, so that no interrupt is generated. In this case, the IDMA request bit is not cleared but the
IDMA enable bit is cleared.
When IDMA is invoked by the software trigger, the IDMA interrupt factor flag FIDMA (D4)/DMA interrupt
factor flag register (0x40281) will not be set.
For details about the interrupt factors that can be used to invoke IDMA and the interrupt control registers,
refer to the descriptions of the peripheral circuits in this manual.
Note that the priority levels of interrupt factors are set by the interrupt priority register. Refer to "ITC
(Interrupt Controller)". However, when compared between IDMA and interrupt requests, IDMA is given
higher priority ove r the other. Consequently, even when an interrupt factor occurri ng du ring an IDMA
transfer has higher priority than the interrupt factor that invoked the IDMA transfer, an interrupt request for it
or a new ID MA invocation request is not accepted until after the current IDMA transfer is completed.
Software-triggered interrupts
If the transfer counter is decremented to 0 and DINTEN = "1" (interrupt enabled) when one DMA transfer
operation is completed, the IDMA interrupt factor flag FIDMA (D4)/DMA interrupt factor flag register
(0x40281) is set, thereby generating an interrupt request. If the transfer counter is not 0 or DINTEN = "0"
(interrupt disabled), the FIDMA flag is not set.
IDMA interrupt control register in the interrupt controller
The following registers are used to control an interrupt for the completion of IDMA transfer:
Inte rrupt facto r flag : F ID M A (D4 ) / DMA in te rru pt facto r flag register (0x4 02 81 )
Inte rrupt enab le : EIDM A (D4 ) / DMA interru pt en able register (0x4 02 71 )
Interrupt level: PDM[2:0] (D[2:0]) / IDMA interrupt priority register (0x40265)
When a DMA transfer in the IDMA channel invoked by a trigger in the software application or subsequent
link is completed and the transfer counter is decremented to 0, the interrupt factor flag for the completion of
IDMA transfer is set to "1". However, this requires as a precondition that interrupt be enabled (DINTEN =
"1") in the control information for that channel. If the interrupt enable register bit remains set (= "1") when
the flag is set, an interrupt request is generated. Interrupts can be disabled by leaving the interrupt enable
register bit cleared (= "0"). Use the interrupt priority register to set interrupt priority levels (0 to 7). An
interrupt request to the CPU is accepted on condition that no other interrupt request of higher priority is
generated.
Furthermore, it is only when the PSR's IE bit = "1" (interrupt enabled) and the set value of IL is smaller than
the IDMA interrupt level which is set by the interrupt priority register that the CPU actually accepts an IDMA
inte rrupt re qu es t.
For details about these interrupt control registers, and for information on device operation when an interrupt
occurs, refer to "ITC (Interrupt Controller)".
V DMA BLOCK: IDMA (Intelligent DMA)
B-V-3-14 EPSON S1C33L03 FUNCTION PART
Trap vector
The trap vector address for an interrupt upon c om pletion of IDM A transfer by default i s set to 0x0C00 068.
The trap table base address can be changed using the TTBR registers (0x48134 to 0x48137).
I/O Memo ry of Intelli gent DMA
Table 3.3 shows the control bits of IDMA.
Table 3.3 Control Bits of IDMA
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
0 to 7
–
PDM2
PDM1
PDM0
D7–3
D2
D1
D0
reserved
IDMA interrupt level –
X
X
X
–
R/W 0 when being read.0040265
(B)
IDMA interrupt
priority register
–
EIDMA
EHDM3
EHDM2
EHDM1
EHDM0
D7–5
D4
D3
D2
D1
D0
reserved
IDMA
High-speed DMA Ch.3
High-speed DMA Ch.2
High-speed DMA Ch.1
High-speed DMA Ch.0
– –
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
0 when being read.0040271
(B) 1 Enabled 0 Disabled
DMA interrupt
enable register
–
FIDMA
FHDM3
FHDM2
FHDM1
FHDM0
D7–5
D4
D3
D2
D1
D0
reserved
IDMA
High-speed DMA Ch.3
High-speed DMA Ch.2
High-speed DMA Ch.1
High-speed DMA Ch.0
– –
X
X
X
X
X
–
R/W
R/W
R/W
R/W
R/W
0 when being read.0040281
(B)
DMA interrupt
factor flag
register 1 Factor is
generated 0 No factor is
generated
DBASEL15
DBASEL14
DBASEL13
DBASEL12
DBASEL11
DBASEL10
DBASEL9
DBASEL8
DBASEL7
DBASEL6
DBASEL5
DBASEL4
DBASEL3
DBASEL2
DBASEL1
DBASEL0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
IDMA base address
low-order 16 bits
(Initial value: 0x0C003A0)
0
0
0
0
0
0
1
1
1
0
1
0
0
0
0
0
R/W0048200
(HW)
IDMA base
address low-
order register
––
DBASEH11
DBASEH10
DBASEH9
DBASEH8
DBASEH7
DBASEH6
DBASEH5
DBASEH4
DBASEH3
DBASEH2
DBASEH1
DBASEH0
DF–C
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
IDMA base address
high-order 12 bits
(Initial value: 0x0C003A0)
–
0
0
0
0
1
1
0
0
0
0
0
0
–
R/W Undefined in read.0048202
(HW)
IDMA base
address
high-order
register
0 to 127
DSTART
DCHN
D7
D6–0 IDMA start
IDMA channel number 1 IDMA start 0 Stop 0
0R/W
R/W
0048204
(B)
IDMA start
register
––
IDMAEN
D7–1
D0 reserved
IDMA enable 1 Enabled 0 Disabled –
0–
R/W
0048205
(B)
IDMA enable
register
V DMA BLOCK: IDMA (Intelligent DMA)
S1C33L03 FUNCTION PART EPSON B-V-3-15
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IDMA
DBASEL[15:0]: IDMA base address [15:0] (D[F:0]) / IDMA base ad dres s low -o rd er r eg iste r ( 0x 482 00)
DBASEH[11:0]: IDMA base address [27:16] (D[B:0]) / IDMA base addr ess high-or der registe r (0x482 02)
Specify the starting address of the control information to be placed in RAM.
Use DBASEL t o set the 16 low-order bits of the address and DBASEH to set the 12 high-order bits.
The add ress to be set in these registers must always be a word (32-bit) boundary address.
These registers cannot be read or writt en in byt es. The registers mu st be accessed in words for read/write
operations to address 0x48 200, and in half- w or ds for read/write operations to addresses 0x48200 and 0x4820 2.
Write operations in half-words must be perform ed in order of 0x48200 a nd 0x48 202. Read ope rations in half-
words may be performed in any order.
Write operations to the IDMA base address registers during a DMA transfer are ignored. When the register is read
during a DMA transfer, the read data is indeterminate.
At i nitial reset, the base address is set to 0xC003A0.
IDMAEN: D MA e nable (D0) / DMA enable regis ter (0x 48205 )
Enable a IDMA transfer.
Write "1": Ena bled
Write "0": Disabl ed
Read: Valid
A data transfer operation by intelligent DMA is enabled by writing "1" to IDMAEN.
IDMA transfer is disabled by writing "0" to IDMAEN.
At i nitial reset, IDMAEN is set to "0" (disabled).
DCHN[6:0]: IDMA channel number (D[6:0]) / IDMA start register (0x48204)
Set the channel numbers (0 to 127) to be invoked by a trigger in the software application.
At i nitial reset, DCHN is set to "0".
DSTART: IDMA start (D7) / IDMA start register (0x48204)
Use this register for a trigger in the software application and for monitoring the operation of IDMA.
When written
Write "1": IDMA started
Write "0": Invalid
When read
Read "1": IDMA operating (only when invoked by software trigger)
Read "0": IDMA inactive
When DSTA RT is set to "1", it functions as a trigger in the software application, invoking the IDMA channel that
is set in the DCHN register.
At i nitial reset, DSTART is set to "0".
PDM2–PDM0: IDMA inte rru pt level (D[2:0 ]) / ID M A inte rru pt prio rit y regist er (0x40 26 5)
Set the priority level of the interrupt upon completion of IDMA transfer in the range of 0 to 7.
At i nitial reset, the contents of this register are indeterminate.
EIDMA: IDMA interrupt enable (D4) / DMA interrupt enable register (0x40271)
Enabl e or disable occurrence of an interrupt to the CPU.
Write "1": Inte rrupt enabled
Write "0": Inte rrupt disabled
Read: Valid
This bit controls the interrupt generated upon completion of IDMA transfer. The interrupt is enabled by setting this
bit to "1" and disabled by setting this bit to "0".
At i nitial reset, EIDMA is set to "0" (interrupt disable).
V DMA BLOCK: IDMA (Intelligent DMA)
B-V-3-16 EPSON S1C33L03 FUNCTION PART
FIDMA: IDMA interrupt factor flag (D4) / DMA interrupt factor flag register (0x40281)
Indicate the occurrence status of an IDMA interrupt request.
When read
Read "1": Interrupt factor occurred
Read "0": No inte rrupt fa cto r o ccu rr ed
When written usin g re se t-o nly m etho d (d efau l t)
Write "1": Interrupt factor flag is reset
Write "0": Invalid
When written using the read /w rite m et ho d
Write "1": Inte rrupt factor flag is set
Write "0": Interrupt factor flag is reset
This flag is set to "1" when one DMA transfer initiated by a software trigger or subsequent link is completed and
the transfer counter is decremented to 0. However, this requires as a precondition that interrupts be enabled in
control information (DINTEN = "1").
At t his time, an interrupt to the CPU is generated if the following conditions are met:
1. The corresponding interrupt enable register bit is set to "1".
2. No interrupt request of higher priority is generated.
3. The IE bit of the PSR is set to "1" (interrupt enable).
4. The corresponding interrupt priority register is set to a level higher than the CPU's interrupt level (IL).
In order for the next interrupt to be accepted after interrupt generation, the interrupt factor flag must be reset and
the PSR must be set up again (by setting the IL below the level indicated by the interrupt priority register and
setting the IE bit to "1" or executing a reti instruction).
The interrupt factor flag can only be reset by a write instruction in the software application. If the PSR is set up
again to accept interrupts (or the reti instruction is executed) without resetting the interrupt factor flag, the same
interrupt may occur again. Note also that the value to be written to reset the flag is "1" when using the reset-only
meth od (RST ONLY = "1") and "0" when using t he read/ write me thod (RSTONLY = " 0"). Be car ef ul not to
confuse these two cases.
This fla g becomes indeterminate when initially reset, so be sure to reset it in the software application.
V DMA BLOCK: IDMA (Intelligent DMA)
S1C33L03 FUNCTION PART EPSON B-V-3-17
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IDMA
Pr ogramming Notes
(1) Before setting the IDMA base address, be sure to disable DMA transfers (IDMAEN = "0"). Writing to the
IDMA base address register is ignored when the DMA transfer is enabled (IDMAEN = "1"). Also, when the
register is read during a DMA transfer, the data is indeterminate. When setting or rewriting control
information for each channel, make sure that DMA transfers will not occur in any channel.
(2) The address that is set in the IDMA base address register must always be a word (32-bit) boundary address.
(3) After an initial reset, the interrupt factor flag (FIDMA) becomes indeterminate. To prevent unwanted
interrupts from occurring, be sure to reset the flag in a program.
(4) Once an interrupt occurs, be sure to reset the interrupt factor flag (FIDMA) before setting up the PSR again or
executing the reti instruction. This ensures that an interrupt will not be generated for the same factor.
(5) If all the following conditions are met, the transfer counter value becomes invalid during IDMA transfer so
data cannot be transferred properly.
1. The IDMA control information (source/destination addresses, transfer counter, etc.) is placed in the
external EDO DRAM.
2. The D RAM access timing condition is set to EDO mode by the BCU register.
3. The bus clock is set to x2 speed mode (#X2SPD pin = "0").
When plac ing t he control information in the EDO DRAM in x2 speed mode, the DRAM access timing
condition must be set to high-speed p age mod e.
Or place the control information in the internal RAM. Using the internal RAM increases the performance
because the overhead during IDMA transfer is decreased to 6 cycles on both load/store operations.
(6) In HALT mode, since the DMA and BCU clocks operate, if the next operation is performed in HALT mode,
not HALT2 mode, with a settin g of 0 in clock option regis ter HLT2OP (D3 /0x40190), that operati on wi ll be
an unpredictable erroneous operation.
If a DMA trigger occurs and DMA is invoked while the CPU is stopped after HALT mode execution,
erroneous operation will result. Ensure that DMA is not invoked in HALT mode.
In HALT2 mode, DMA is not invoked since the DMA and BCU clocks are stopped.
V DMA BLOCK: IDMA (Intelligent DMA)
B-V-3-18 EPSON S1C33L03 FUNCTION PART
TH IS PAGE IS BLANK.
S1C33L03 FUNCTION PART
VI SDRAM CONTROLLER BLOCK
VI SDRAM CONTROLLER BLOCK: INTRODUCTION
S1C33L03 FUNCTION PART EPSON B-VI-1-1
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B-VI
Intro
VI-1 INTRODUCTION
The SDRAM controller block provides a SDRAM interface that allows direct connection of external SDRAM
chips via the BCU.
CORE_PAD
Pads
C33_SBUS
C33 Core Block
C33 LCD Controller Block
Pads
PERI_PAD
Pads
C33_PERI
(Prescaler, 8-bit timer, 16-bit timer,
Clock timer, Serial interface, Ports)
C33 Peripheral BlockC33 Analog Block
C33_CORE
(CPU, BCU, ITC, CLG, DBG)
C33_ADC
(A/D converter)
C33 Internal Memory Block
Internal RAM
(Area 0)
Internal ROM
(Area 10)
C33 DMA Block
C33_DMA
(IDMA, HSDMA)
C33_SDRAMC
(SDRAM interface)
C33_LCDC
(LCD panel interface)
C33 SDRAM Controller Block
Figure 1.1 SDRAM Controller Block
Note: Internal ROM is not provided in the S1C33L03.
VI SDRAM CONTROLLER BLOCK: INTRODUCTION
B-VI-1-2 EPSON S1C33L03 FUNCTION PART
THIS PAGE IS BLANK.
VI SDRAM CONTROL LER BLOC K: S DRAM INTERFACE
S1C33L03 FUNCTION PART EPSON B-VI-2-1
A-1
B-VI
SDRAM
VI-2 SDRAM INTERFACE
The SDRAM contr oller allows up to 32MB of SDRAM to be connected directly to areas 7 and 8 or areas 13 and
14. This chapter descri bes ho w to control the SDRAM interface, and how it operates. For the conditions and
parameters used to configure the external bus except for the SDRAM interface, refer to Chapter II-4, "BCU (Bus
Control Unit)".
Outline of SDRAM Interface
The following shows the main features and specifications of the SDRAM interface.
•Supports 8 or 16 -bit SDRAM.
•Two SDRAM areas (areas 7 and 8 or areas 13 and 14)
The following SDRAM configuration (maximum) is possible, connected directly to each area.
- 16M × 16 bi ts × 1 chip
- 8M × 16 bit s × 2 chips
- 32M × 8 bit s × 1 chi p
- 16M × 8 bit s × 2 chi ps
•Supports 2 or 4- bank SDRAM (BA1 and BA 0 outputs) .
Row address range: 2K (A10–A0), 4K (A11–A0), or 8K (A12–A0)
Column address range: 25 6 (A7–A0), 512 (A8–A0), or 1K (A9–A0)
•Incorporates a programmable 12-bit auto refresh counter.
The SDRAM can be refreshed as necessary, irrespective of the clock frequency used.
•Intelligent self-refresh mode for low-power operation
•Two power-up options:
- Precha rge → Refresh → Mode Register Set
- Precha rge → Mode Register Se t → Refresh
•CAS latency: 2
•Burst length: Can be set to 1, 2, 4, or 8 words.
SDRAM Controller Block Diagram
Figure 2.1 shows the block diagram of the SDRAM controller. Note that the signals described in the figure are
internal use, not external signals.
Bus
multiplex
Control
registers
SDRAM state
control
Address[23:0]
Bus Size
Data[15:0]
addr[23:0]
D[15:0]
SDA[12:11], SDA[9:0]
SDA10, SDCKE, #SDCE0/1
#SDCAS, #SDRAS
#SDWE, HDQM, LDQM
Bus command
decoder SDRAM
command
decoder
Refresh
counter
Bus Mode
Internal #CE6
Internal #CE7/13
Internal #CE8/14
Internal #WAIT
OSC3 clock
User logic signals
Figur e 2.1 SDRAM Controller Block Diagram
VI SDRAM CONTROL LER BLOC K: S DRAM INTERF ACE
B-VI-2-2 EPSON S1C33L03 FUNCTION PART
I/O Pins and Connection
I/O Pins
Table 2.1 list s the pins used for the SDRAM interface.
Table 2.1 I/O Pin List
Pin name I/O Function
A[13:12]/SDA[12:11],
A[10:1]/SDA[9:0] OAddress bus
A[15:14]/SDBA[1:0] O SDRAM bank select signals
D[15:0] I/O Data bus (D0–D15)
#CE8/#RAS1/#CE14/#RAS3/#SDCE1 O Area 8/14 chip enable / DRAM Row strobe / SDRAM chip enable 1
#CE7/#RAS0/#CE13/#RAS2/#SDCE0 O Area 7/13 chip enable / DRAM Row strobe / SDRAM chip enable 0
#HCAS/#SDCAS O DRAM column address strobe (High-byte) / SDRAM column address
strobe
#LCAS/#SDRAS O DRAM column address strobe (Low-byte) / SDRAM row address strobe
BCLK/SDCLK O Bus clock output / SDRAM operating clock
P20/#DRD/SDCKE I/O I/O port / DRAM read / SDRAM cl ock enable
P21/#DWE/#GAAS/#SDWE I/O I/O port / DRAM write (Low-byte) / Area address strobe output for GA /
SDRAM write
P33/#DMAACK1/SIN3/SDA10 I/O I/O port / HSDMA Ch. 1 acknowledge output / Serial I/F Ch. 3 data input /
SDRAM addr es s bu s 10
P32/#DMAACK0/#SRDY3/HDQM I/O I/O port / HSDMA Ch. 0 acknowledge output / Serial I/F Ch. 3 ready signal
output / SDRAM data (High-byte) input/output mask signal output
P15/EXCL4/#DMAEND0/#SCLK3/
LDQM I/O I/O port / 16-bit timer 4 event counter input / HSDMA Ch. 0 end-of-transfer
signal output / Serial I/F Ch. 3 clock input/output / SDRAM data (Lo w-byte)
input/output mask signal output
Connection Examples
Figures 2.2 and 2.3 show examples of how to connect 16-bit SDRAMs to the S1C33. Figure 2.4 shows an example
of how t o connect an 8-bit SDRAM to the S1C33.
SDA[12:11](A[13:12])
SDA10(P33)
SDA[9:0](A[10:1])
SDBA[1:0](A[15:14])
D[15:0]
BCLK
SDCKE(P20)
#SDCE0/1(#CE7/8)
#SDCAS(#HCAS)
#SDRAS(#LCAS)
#SDWE(P21)
HDQM(P32)
LDQM(P15)
S1C33
A[12:11]
A10
A[9:0]
BA[1:0]
DQ[15:0]
CLK
CKE
#CS
#CAS
#RAS
#WE
DQMU
DQML
256M SDRAM
(4M x 16 bits x 4 banks)
Figur e 2.2 Connecting a 16-bit SDRAM (32MB)
VI SDRAM CONTROL LER BLOC K: S DRAM INTERFACE
S1C33L03 FUNCTION PART EPSON B-VI-2-3
A-1
B-VI
SDRAM
SDA11(A12)
SDA10(P33)
SDA[9:0](A[10:1])
SDBA[1:0](A[15:14])
D[15:0]
BCLK
SDCKE(P20)
#SDCE0(#CE7)
#SDCE1(#CE8)
#SDCAS(#HCAS)
#SDRAS(#LCAS)
#SDWE(P21)
HDQM(P32)
LDQM(P15)
S1C33
A11
A10
A[9:0]
BA[1:0]
DQ[15:0]
CLK
CKE
#CS
#CAS
#RAS
#WE
DQMU
DQML
128M SDRAM
(2M x 16 bits x 4 banks)
A11
A10
A[9:0]
BA[1:0]
DQ[15:0]
CLK
CKE
#CS
#CAS
#RAS
#WE
DQMU
DQML
128M SDRAM
(2M x 16 bits x 4 banks)
Figur e 2.3 Connecting two 16-bit SDRAMs (32MB)
SDA[12:11](A[13:12])
SDA10(P33)
SDA[9:0](A[10:1])
SDBA[1:0](A[15:14])
D[7:0]
BCLK
SDCKE(P20)
#SDCE0/1(#CE7/8)
#SDCAS(#HCAS)
#SDRAS(#LCAS)
#SDWE(P21)
LDQM(P15)
S1C33
A[12:11]
A10
A[9:0]
BA[1:0]
DQ[7:0]
CLK
CKE
#CS
#CAS
#RAS
#WE
DQM
128M SDRAM
(4M x 8 bits x 4 banks)
For little endian
SDA[12:11](A[13:12])
SDA10(P33)
SDA[9:0](A[10:1])
SDBA[1:0](A[15:14])
D[15:8]
BCLK
SDCKE(P20)
#SDCE0/1(#CE7/8)
#SDCAS(#HCAS)
#SDRAS(#LCAS)
#SDWE(P21)
HDQM(P32)
S1C33
A[12:11]
A10
A[9:0]
BA[1:0]
DQ[7:0]
CLK
CKE
#CS
#CAS
#RAS
#WE
DQM
128M SDRAM
(4M x 8 bits x 4 banks)
For big endian
Figur e 2.4 Connecting an 8-bit SDRAM (16MB)
VI SDRAM CONTROL LER BLOC K: S DRAM INTERF ACE
B-VI-2-4 EPSON S1C33L03 FUNCTION PART
Notes:•Because the SDRAM ad dress bus pins di ffer in bit num bers from ordinary external ad dress pin
nam es, care must be taken when connecti ng an SDRAM t o the S1C33. (SDRAM address
SD A0 is out put fro m the A1 pin, and SDA12 is ou tput f rom the A13 pin.) Fu rt herm ore, t he
SD A10 signal with a spec ial fun ction is assigned to the P33 pin, and not to t he address bu s
A11.
•If designated pins (e. g., CKE and DQM [1:0] pins) must be driven hig h before the SD RAM can
be powe red on, add external pull-up resistors or use a separate power supply f or the SD RAM.
•To prevent a malfunction, t ake me asures against noise when designing the board patterns for
the SDR A M.
Table 2.2 lists several examples of SDRAM chip configurations. All of these examples use only one area of the
S1C33. If your design uses t w o areas, the same type of memory needs to be used in each area because SDRAM-
related settings are common to both areas.
Table 2.2 Chip Configuration Example (when one area only is used)
SDRAM Number of
devices Memory size
256M (4M x 16 bits x 4 banks) 1 32M bytes
256M (8M x 8 bits x 4 banks) 1 32M bytes
128M (2M x 16 bits x 4 banks) 1 16M bytes
128M (4M x 8 bits x 4 banks) 1 16M bytes
232M bytes
64M (1M x 16 bits x 4 banks) 1 8M bytes
64M (2M x 8 bits x 4 banks) 1 8M bytes
216M bytes
16M (512 x 16 bits x 2 banks) 1 2M bytes
16M (1M x 8 bits x 2 banks) 1 2M bytes
24M bytes
VI SDRAM CONTROL LER BLOC K: S DRAM INTERFACE
S1C33L03 FUNCTION PART EPSON B-VI-2-5
A-1
B-VI
SDRAM
SDRAM Controller Configuration
Setting PLL
When using the SDRAM controller, always enable the PLL. Refer to "PLL" in Section II-6, "CLG (Clock
Generator)", for setting the PLL.
The following shows the operating range of the SDRAM controller when the PLL is enabled.
#X 2SPD pin = "1" (x1 speed mo de): 25 MHz max. ( C PU ope rating frequency = 25 MHz), voltage 3.3±0.3 V
#X 2SPD pin = "0" (x2 speed mo de): 17.5 MHz m ax. (CPU operati ng frequency = 20 MHz), voltage 3.3±0. 3 V
BCU Configuration
The SDRAM interface control registers are allocated to addresses 0x39FFC0–0x39FFCA in area 6. Therefore,
before the control registers can be accessed, the BCU must be set up following the procedure described below.
1. CEFUNC[1:0] (D[A:9])/DRAM timing set-up register (0x48130) = "00" (default) or "01"
Set CEFUNC[1:0] = "00" to use SDRAM in areas 7/8 or CEFUNC[1:0] = "01" to use S DRA M in areas
13/14. Table 2.3 Switching of #CE Output
PinCEFUNC = "00" CEFUNC = "01" CEFUNC = "1x"
#CE7/#SDCE0 #CE7/#SDCE0 #CE13/#SDCE0 #CE13/#SDCE0
#CE8/#SDCE1 #CE8/#SDCE1 #CE14/#SDCE1 #CE14/#SDCE1
(Default: CEFUNC = "00")
2. A6IO (D9)/Access con trol register (0x48132) = "1"
This ens ures that the internal devices are accessed in area 6.
3. A6WT[2:0] ( D [A: 8])/Are as 6–4 set-up reg ister (0x48 12A) = "010"
This cau ses two wait cycles to be inserted when accessing area 6. With a different number of wait cycles, data
may not be written to the control registers normally.
4. SWAITE (D0)/Bus control register (0x4812E) = "1"
This enables the #WAIT signal. The IC’s internal #WAIT signal is used when powering up the SDRAM.
5. A6EC (D1)/Access control r egist er (0x48132) = LCDCEC (D0)/LCD C syste m control r egist er (0x39FFFD)
Use these registers to match endian types when reading out area 6 and SDRAMC/LCDC. Both bits select
little endian when "0" or big endian when "1".
When the above settings are finished, the SDRAM control registers in area 6 can be accessed.
Next , set a reas 7/8 or areas 13/14 in which SDRAMs are connected.
A. When us ing areas 7/8 (CEFUNC = "00") Note: The same settings as those shown above are omitted.
A-1. A8IO (DA)/Access control register (0x4 81 32 ) = "1"
This sets areas 7/8 for internal access.
A-2. A8WT[2:0] (D[2:0])/Areas 8–7 set-up register (0x48128) = "000"
This sets areas 7/8 for no-wait access.
A-3. A8SZ (D6)/Ar eas 8–7 set-up regist er (0x48128) = SDRSZ (D 6)/SD RAM advanced con trol regis ter
(0x39FFC9)
Use these registers to ensure that the device size of areas 7/8 and that of the SDRAM controller are the same,
and are matched to the SDRAM data width. Both bits select 16 bits when "0" or 8 bits when "1".
A-4. A8D F [1 :0] (D [5:4])/Are as 8–7 set-up register (0x48 1 28)
If the system has an external memory device other than an SDRAM connected to it and accesses that memory
device and SD RAM in successi on, set the output dis able delay time of areas 7/8 to 2. 5 cyc les (A8DF[1:0] =
"10").
When only the SDRAM is read and no other external device is accessed, set the output disable delay time of
areas 7/8 to 0.5 cycles (A8DF[1:0] = "00") in order to reduce the SDRAM access time.
VI SDRAM CONTROL LER BLOC K: S DRAM INTERF ACE
B-VI-2-6 EPSON S1C33L03 FUNCTION PART
B. When us ing areas 13/14 (CEFUNC = "01")
B-1. A14IO (DD)/Ac cess control register (0x48132 ) = "1 "
This sets areas 13/14 for internal access.
B-2. A14WT[2:0] (D[2:0])/Areas 14–13 set-up register (0x48122) = "000"
This sets areas 13/14 for no-wait access.
B-3. A14SZ ( D6)/Areas 14–13 set-up regist er (0x48122) = SDRSZ (D6)/SDRAM advanced control register
(0x39FFC9)
Use these registers to ensure that the device size of areas 13/14 and that of the SDRAM controller are the
same, and are matched to the SDRAM data width. Both bits select 16 bits when "0" or 8 bits when "1".
B-4. A14DF[ 1:0] (D[5:4])/Areas 14–13 set-up regist er (0x48122)
If the system has an external memory device other than an SDRAM connected to it and accesses that memory
device and SDRAM in succession, set the output disable delay time of areas 13/14 to 2.5 cycles (A14DF[1:0]
= "10").
When only the SDRAM is read and no other external device is accessed, set the output disable delay time of
areas 13/14 to 0.5 cycles (A14DF[1:0] = "00") in order to reduce the SDRAM access time.
This completes the BCU settings necessary to access the SDRAM.
Make sure the BCU pa rameters other than those discussed above are set appropriately for the system.
SDRA M Setting Conditions
The SDRAM interface allows the following conditions to be selected. Although SDRAM can be used in areas 7
and 8 or areas 13 and 14, these conditions are applied to all four areas and cannot be set individually for each area.
Table 2.4 SDRAM Interfa ce Parame ters
Parameter Selectable condition Initial setting Control bits
Area 7/13 configuration SDRAM or Another Another device SDRAR0(D7)/SDRAM area configuration register(0x39FFC0)
Area 8/14 configuration SDRAM or Another Another device SDRAR1(D6)/SDRAM area configuration register(0x39FFC0)
#CE7/13 pin configuration #SDCE0 or #CE7/13 #CE7/13 SDRPC0(D3)/SDRAM area configuration register(0x39FFC0)
#CE8/14 pin configuration #SDCE1 or #CE8/14 #CE8/14 SDRPC1(D2)/SDRAM area configuration register(0x39FFC0)
Page size 256, 512 or 1K 256 SDRCA[1:0](D[6:5])
/SDRAM address configuration register(0x39FFC2)
Row addressing range 2K, 4K or 8K 2K SDRRA[1:0](D[3:2])
/SDRAM address configuration register(0x39FFC2)
Number of banks 4 or 2 2 SDRBA(D1)
/SDRAM address configuration register(0x39FFC2)
Initial command sequence 1. Precharge
2. Refresh
3. Mode register
or
1. Precharge
2. Mode register
3. Refresh
1. Precharge
2. Refresh
3. Mode register
SDRIS(D4)/SDRAM control register(0x39FFC1)
Burst length 1, 2, 4 or 8 8 SDRBL[1:0](D[3:2])/SDRAM mode set-up register(0x39FFC3)
CAS latency 2 – *SDRCL[1:0](D[6:5])/SDRAM mode set-up register(0x39FFC3)
tRAS 1 to 8 clocks 8 clocks SDRTRAS[2:0](D[7:5])/SDRAM timing set-up register 1
(0x39FFC4)
tRP 1 to 4 clocks 4 clocks SDRTRP[1:0](D[4:3])/SDRAM timing set-up register 1
(0x39FFC4)
tRC 1 to 8 clocks 8 clocks SDRTRC[2:0](D[2:0])/SDRAM timing set-up register 1
(0x39FFC4)
tRCD 1 to 4 clocks 4 clocks SDRTRCD[1:0](D[7:6])/SDRAM timing set-up register 2
(0x39FFC5)
tRSC 1 or 2 clocks 2 clocks SDRTRSC(D5)/SDRAM timing set-up register 2 (0x39FFC5)
tRRD 1 to 4 clocks 4 clocks SDRTRRD[1:0](D[4:3])/SDRAM timing set-up register 2
(0x39FFC5)
∗ Always set CAS latency to 2.
VI SDRAM CONTROL LER BLOC K: S DRAM INTERFACE
S1C33L03 FUNCTION PART EPSON B-VI-2-7
A-1
B-VI
SDRAM
Memory Configuration
Use the regis ters described below to select the area in which SDRAMs are connected and the chip enable
output pin to be used for SDRAMs.
Selecti ng areas
Area 7 or 13: SDRA R0 ( D7)/SDRAM area conf igurati o n re gister (0x39F FC0 )
Area 8 or 14: SDRA R1 ( D6)/SDRAM area conf igurati o n re gister (0x39F FC0 )
Writing "1" to SDRARx sets the corresponding area for SDRAM use. When SDRARx = "0" (default), the
area is used for devices other than SDRAM that are controlled only by the BCU.
Selecti ng chip enab le
#SDCE0(#CE7/13): SDRPC0 (D3)/SDRAM area configuration register (0x39FFC0)
#SDCE1(#CE8/14): SDRPC1 (D2)/SDRAM area configuration register (0x39FFC0)
Writing "1" to SDRPCx sets the corresponding pin for SDRAM chip enable output. When SDRPCx = "0"
(default), the pin is used for devices other than SDRAM that are controlled only by the BCU.
Although #SDCE0 and #SDCE1 are assigned to the #CE7 and #CE8 pins, respectively, they are not
necessarily fixed to either area. For example, even when using area 7 or 13 for SDRAMs, the chip enable
used for the SDRAM can be #SDCE 1 (#CE8/14).
Table 2.5 list s the chip enable address ranges and the SDRAM sizes that can be connected when the area(s)
and chip enable are selected according to the above.
Table 2.5 Chip Enable Configuration
CEFUNC SDRAR0 SDRAR1 SDRPC0 SDRPC1 #SDCE0
address range #SDCE1
address range SDRAM size
(16-bit)
00XX N/A N/A 0
XX XX00 N/A N/A 0
1010Area 7 N/A 2MB
1001 N/A Area 72MB
1011Area 7 N/A 2MB
0110Area 8 N/A 2MB
0101 N/A Area 82MB
0111 N/A Area 82MB
1110Area 7&8N/A 4MB
1101 N/AArea 7&84MB
00
(default)
1111Area 7Area 82MB x 2
1010Area 13 N/A 16MB
1001 N/A Area 1316MB
1011Area 13 N/A 16MB
0110Area 14 N/A 16MB
0101 N/A Area 1416MB
0111 N/A Area 1416MB
1110Area 13&14N/A 32MB
1101 N/AArea 13&1432MB
01
10
11
1111Area 13Area 1416MB x 2
Area 7 = 0x400000–0x5FFFFF, Area 8 = 0x600000–0x7FFFFF, Area 7&8 = 0x400000–0x7FFFFF
Area 13 = 0x2000000–0x2FFFFFF, Area 14 = 0x3000000–0x3FFFFFF, Area 13&14 = 0x2000000–0x3FFFFFF
VI SDRAM CONTROL LER BLOC K: S DRAM INTERF ACE
B-VI-2-8 EPSON S1C33L03 FUNCTION PART
Ba nk, ro w , and column address configuration
An SDRAM memory array consists of two or four banks, with each bank divided into pages. For this reason,
SD RA M s have a bank select pin which is not foun d in asynchronous DRAMs. Inside the Bank, the Column
(Page) address and the Row address are selected by #CAS and #RAS, respectively, in the same way as with
asynchronous DRAMs.
For the SDRAM addresses to be generated correctly, it is necessary that the bank size and the column and
row address ranges be set in the SDRAM controller according to the SDRAMs used. For these settings, use
the registers shown below.
Bank size: SDRBA (D1) /SDRAM address configuration register (0x39FFC2)
Column addres sing ra nge: S DRC A[ 1: 0] (D [6 :5 ])/SD R AM ad dress config uratio n register (0x3 9F F C2 )
Row addressing ra ng e: SDR R A[ 1: 0] (D [3 :2 ])/ SD R AM ad dress config uratio n registe r (0x3 9F F C2 )
Table 2.6 Setting Bank Size
SDRBA Number of banks Bank address (pin) used
02SDBA0 (default)
14SDBA0–SDBA1
Table 2.7 Setting Column Addressing Range (Page Size)
SDRCA1 SDRCA0 Column size Column address (pin) used
00 256SDA0–SDA7 (default)
01 512 SDA0–SDA8
10 1,024 SDA0–SDA9
11 – –
Table 2.8 Setting Row Addressing Range
SDRRA1 SDRRA0 Row size Row address (pin) used
00 2KSDA0–SDA10 (default)
01 4K SDA0–SDA11
10 8K SDA0–SDA12
11 – –
The SDRAM contr oller uses only the lower 24 bits of the 28-bit address bus. The relationship between the
CPU addresses and the Bank, Column, and Row addresses is shown below.
16-bit SD RAM interface (SDRSZ = " 1")
A(m+n+p) A(m+n+1) A(m+n) ··· A(m+1) A(m) ··· A1 A0
Bank address Row address Column address DQM
When reading/writing byte data, the SDRAM controller decodes A0/BSL and WRH/BSH into LDQM and
HDQM.
8-bi t SD RAM inter face ( S DRSZ = "0" )
A(m+n+p-1) A(m+n) A(m+n-1) ··· A(m) A(m-1) ··· A0
Bank address Row address Column address
m: Column address size (number of bits)
n: Row address size (number of bits)
p: Bank address size (number of bits)
Uppe r address bits that are not used (depending on memory size) are all set to 0s.
In cases when two areas are selected (SDRAR[1:0] = "11") and only one chip enable is enabled (SDRPC[1:0]
= "01" or "10"), the MSB of the bank address (A(m+n+p) for 16 bits or A(m+n+p-1) for 8 bits) is replaced
with the value shown below.
• Value is "0" when accessing area 7/13
• Value is "1" when accessing area 8/14
VI SDRAM CONTROL LER BLOC K: S DRAM INTERFACE
S1C33L03 FUNCTION PART EPSON B-VI-2-9
A-1
B-VI
SDRAM
Selecting initialization sequence
The SD RAM command sequence that is run immediately after SDRAM power-up can be selected to suit the
specifications of the SDRAM used. For this setting, use the SDRIS (D4)/SDRAM control register
(0x39FFC1).
SD RIS = "0" : 1. Pr echarge → 2. Ref resh → 3. Mode Register Set
SD RIS = "1" : 1. Pr echarge → 2. Mode Register Set → 3. Refresh
If no problems are incurred in either setting, SDRIS = "1" is recommended.
Burst length
The bur st length can be selected using the SDRBL[1:0] (D[3:2])/SDRAM mode set-up register (0x39FFC3).
Table 2.9 Setting Burst Length
SDRBL1 SDRBL0 Burst length (word)
00 1
01 2
10 4
11 8 (default)
Notes:•Burst transfers are effective only when reading data from SDRAM. When writing to SDRAM,
data are always written in a si ngle operation, not in bursts, no m atter what burst length is
selected.
•The SDRAM controlle r is designe d in such a way that when one cycle of burst read is fin ished,
it automatically issues the READ command to continue with transfers. Therefore, unless
SD RBL[1 :0] = "00" , the speed at wh ich SD RAM i s acce ss ed does not var y wit h the bur st len gth
involved.
Setting CAS latency
The CAS l atency is defined by the number of clock cycles before dat a is output from SDRAM after iss uing
the READ command and this SDRAM controller supports only 2 clocks of CAS latency. Set the SDRCL[1:0]
(D[6:5])/SDRAM mode set-up register (0x39FFC3) to "10" (CAS latency = 2) before accessing the SDRAM.
BCLK
Command
SDCKE
#SDCEx
#SDRAS
#SDCAS
#SDWE
SDBA[1:0]
SDA[12:0]
DQ[15:0]
ACTVNOP NOP NOPREAD
BA BA
ROW COL
DATA
tRCD
CAS latency = 2
Figur e 2.5 CAS Latency
VI SDRAM CONTROL LER BLOC K: S DRAM INTERF ACE
B-VI-2-10 EPSON S1C33L03 FUNCTION PART
Enabling/di sabling bank interleaved access
A ban k cannot be accessed at the same time it is being precharged, so another bank may be accessed during
that period, which results in increased access speed. For this purpose, the SDRAM controller supports a
feature known as Bank Interleaved Access.
Specify whether or not to use this feature with the SDRBI (D5)/SDRAM advanced control register
(0x39FFC9).
SD RBI = "1": Bank interlea ved access function is used
SD RBI = "0" : Bank interlea ved access function is not used (one bank only is accessed at a time)
BCLK
Command
SDCKE
#SDCEx
#SDRAS
#SDCAS
#SDWE
SDBA[1:0]
SDA[10]
SDA[12:11, 9:0]
LDQM/HDQM
DQ[15:0]
Bank 1
Bank 2
ACTV
H
NOP NOP NOPACTV READ READ READ
BA1 BA1
ROW2
D(n)
t
RRD
t
RP
(Bank 1 cannot be accessed)
CAS latency
= 2
(CAS latency = 2, t
RCD
= 2)
ROW2
ROW1
ROW1
Active Read Precharge
Active Read
COLn
BA2
COLm
BA1
COLl
BA2
PRE NOP NOP
BA1
D(m) D(l)
ACTV
BA1
ROW3
ROW3
BCLK
Command
SDCKE
#SDCEx
#SDRAS
#SDCAS
#SDWE
SDBA[1:0]
SDA[10]
SDA[12:11, 9:0]
LDQM/HDQM
DQ[15:0]
Bank 1
Bank 2
H
NOP NOPACTV READ PRE NOPPRE
BA1 BA1
D(n)
(CAS latency = 2, t
RCD
= 2)
ROW1
ROW1
ROW2
ROW2
Active Read Precharge
Active Read Precharge
COLn
BA1 BA2
ACTV NOP ACTVNOP
BA2
ROW3
ROW3
BA1
D(m)
READ
BA2
CONm
When SDRBI = "0"
When SDRBI = "1"
Figur e 2.6 Bank Interleaved Access
When SDRBI is set to "0", the SDRAM controller issues the precharge command every time the bank to be
accessed is changed. This reduces current consumption than that of the bank interleaved access, so set SDRBI
to "0" if bank is hardly changed through a series of access.
VI SDRAM CONTROL LER BLOC K: S DRAM INTERFACE
S1C33L03 FUNCTION PART EPSON B-VI-2-11
A-1
B-VI
SDRAM
Timing setup
The following parameters can be set in conformity with SDRAM specifications before use.
Table 2.10 SDRAM Parameters
Symbol SDRAM parameter Set values
(# of clocks) Control bits
tRC ACTIVE to ACTIVE command period 1 to 8 SDRTRC[2:0] (D[2:0])/SDRAM
AUTO REFRESH command period timing set-up register 1 (0x39FFC4)
Exit SELF REFRESH to ACTIVE command period
tRAS ACTIVE to PRECHARGE command period 1 to 8 SDRTRAS[2:0] (D[7:5])/SDRAM
Minimum SELF REFRESH period timing set-up register 1 (0x39FFC4)
tRCD ACTIVE to READ or WRITE delay time 1 to 4 SDRTRCD[1:0] (D[7:6])/SDRAM
timing set-up register 2 (0x39FFC5)
tRP PRECHARGE command period 1 to 4 SDRTRP[1:0] (D[4:3])/SDRAM
timing set-up register 1 (0x39FFC4)
tRRD ACTIVE bank (a) to ACTIVE bank (b) period 1 to 4 SDRTRRD[1:0] ( D[4:3])/SDRAM
timing set-up register 2 (0x39FFC5)
tRSC MODE REGISTER S E T cycle t ime 1 or 2 SDRTRSC (D5)/SDRAM timing set-
up register 2 (0x39FFC5)
BCLK
Command
SDBA[1:0]
SDA[12:11, 9:0]
SDA10
DQ[15:0]
ACTVNOP NOP NOP NOP NOP PREREAD
BA BA
ROW COL
ROW
BA
ROW
ROW
DATA DATA DATA DATA
t
RCD
t
RAS
t
RC
t
RP
CAS latency
(Burst length = 4)
NOP ACTV
BA
BKsel
BCLK
Command
SDBA[1:0]
SDA[12:11, 9:0]
SDA10
DQ[15:0]
ACTVNOP NOP NOP ACTV NOP READREAD
BAa BAa
ROWa COLa
BAb
ROWb
ROWa ROWb
COLb
Da DbDa
+1
Da
+2
Da
+3
t
RRD
(Burst length = 4)
(a) Burst read
(b) Bank interleaved access
NOP NOP
BAb
Figur e 2.7 SDRAM Parameters
Note:When the auto-refr esh co m m and is executed, t he foll owing command ma y be issued 3 or 4
CPU_CLK cycl es from that point regardless of the tRC value set in the SDRT R C[2:0 ]
(D[2:0])/SDRAM timing set-up register 1 (0x39FFC4). Therefore, use SDRAMs wit h 75 ns or less
of tRC.
VI SDRAM CONTROL LER BLOC K: S DRAM INTERF ACE
B-VI-2-12 EPSON S1C33L03 FUNCTION PART
SDR A M Operation
Synchronous Clock
The SDRAM contr oller uses the BCLK pin as it outputs the SDRAM clock.
High-speed (OSC3)
oscillation circuit
CLKCHGCLKDT[1:0]
PLLS[1:0] pins #X2SPD pin To CPU
OSC3_CLK
PLL_CLK
ACPU_CLK BCU_CLK
CPU_CLK
OSC3_CLK
PLL_CLK
Bus clock
PLL
Low-speed (OSC1)
oscillation circuit
CLG BCU
1/1 or 1/2
1/1–1/8 BCLKSEL[1:0]
SDRENA
SD_CLK
SDRAMC
1/1 or 1/2
Refresh
counter
BCLK pin
Figure 2.8 SDRAM Clock System
Normally output from the BCLK pin is a clock selected with the BCU’s BCLKSEL[1:0] (D[1:0])/BCLK select
register (0x4813A) (which is, by default, the CPU clock). Before SDRAM can be used, the SDRAM clock can be
enabled for output by writing "1" to the SDRENA (D7)/SDRAM control register (0x39FFC1).
The SDRAM clock has its fre quency determined by how the #X2S PD pin is set, as does the BCU op erati ng clock
(BCU_CLK).
#X 2SPD = " 1" : CPU–SD RA M clock ratio is set to 1 : 1. The SDRAM clock and the CPU system clock will be
the same.
#X 2SPD = " 0" : CPU–SD RA M clock ratio is set to 2 : 1. The SDRAM clock frequency becomes half of the CPU
system clock.
While the SDRAM is self-refreshed, the SDRAM clock output can be turned off in order to reduce the chip’s
current consumption. To set this feature, use the SDRCLK (D3)/SDRAM control register (0x39FFC1).
SD RCLK = "1" : The BCLK pin alw ays out puts SDRAM c lock (default).
SD RCLK = "0": The BCLK pin is fix ed low wh il e the SDRAM is self-refreshed. It is placed in the high-
impedance state while control of the bus is released.
#SDCEx
OSC3 (CPU_CLK)
BCLK (BCU_CLK)
BCLK (SD_CLK when SDRCLK = "1")
BCLK (SD_CLK when SDRCLK = "0")
SDCKE
Access to
the SDRAM Access to other
external memory Access to the
internal memory
When #X2SPD = "1"
Self
refresh
#SDCEx
OSC3 (CPU_CLK)
BCLK (BCU_CLK)
BCLK (SD_CLK when SDRCLK = "1")
BCLK (SD_CLK when SDRCLK = "0")
SDCKE
Access to
the SDRAM Access to other
external memory Access to the
internal memory
When #X2SPD = "0"
Self
refresh
Figur e 2.9 SDRAM Clock Operation
VI SDRAM CONTROL LER BLOC K: S DRAM INTERFACE
S1C33L03 FUNCTION PART EPSON B-VI-2-13
A-1
B-VI
SDRAM
Power-up and Initialization
The following de scribes the processing sequence for powering up the SDRAM.
1. Setting the BCU and SDRAM access conditions
Set the BCU and the SDRAM controller as explained in "SDRAM Configuration".
2. SDRENA ( D7)/SDRAM control register (0x39FFC1) = "1"
This cau ses the pins shown in Table 2.1 to be switched for SDRAM signal use. (The contents set in the port
func tio n se lect an d p ort func tio n ex te ns ion regi sters d o not af fe ct th is sw it ching .) Also , the BCLK pin start s
outputtin g th e SDRAM clock.
Until this stage, the SDRAM pins shared with I/O ports are set for general-purpose input and placed in the high-
impedance state. If the power to the SDRAM is designed to be turned on simultaneously with the CPU, the
SDCKE (P20), HDQM (P32), and LDQM (P15) pins left floating may adversely affect the SDRAM, depending
on its specifications. (For example, unnecessary data may be output.) In such a case, these pins must be pulled
high, external to the chip. If the CPU and SDRAM are powered from separate power supplies and the power to
the SDRAM is turned on after writing "1" to SDRENA, the problem mentioned above does not occur, because
the signals for SDRAM use are being output.
3. Wa it for 100 µs or more after turning on the power to t he SDRAM
After the power to the SDRAM is turned on, the SDRAM must be held in an NOP state (#SDCEx = high) for at
least 100 µs. Because the duration of this period varies with each SDRAM, consult the specifications for your
SDRAM.
4. SDRINI (D6)/SDRAM c ontrol regis ter (0x39FFC1) = "1"
This cau ses the SDRAM controller to output the commands in the order specified by the SDRIS (D4)/SDRAM
control register (0x39FFC1) in order to initialize the SDRAM. (Data are not initialized.)
SD RIS = "0" : 1. Pr echarge → 2. Ref resh → 3. Mode Register Set
SD RIS = "1" : 1. Pr echarge → 2. Mode Register Set → 3. Refresh
Writing "1" to SDRINI has no effect when SDRENA = "0".
5. Checking SDRM RS (D 7)/SDRAM stat us regis ter (0x39FFCA )
SD RM RS is r eset to "1" after power-on, and is set to "0" by executing the MRS (Mode Register Set) command.
Because the MRS command uses an external address bus, no other external devices can be accessed until its
output is finished. The SDRAM controller asserts the #WAIT signal provided for the user logic and keeps it
active until the MRS command output is finished after writing "1" to SDRINI, thus disabling external access
during that time. The CPU also ignores the no-wait access specified by SWAITE (D0/0x4812E) = "0". Before
initiating external access, however, be sure to check that SDRMRS is set to "0".
In addition to being reset at power-on, SDRMRS is reset to "1" by writing "0" to SDRENA or writing "1" to
SDRINI.
This completes the SDRAM initialization sequence, allowing access to the SDRAM.
VI SDRAM CONTROL LER BLOC K: S DRAM INTERF ACE
B-VI-2-14 EPSON S1C33L03 FUNCTION PART
SDRAM power
BCLK
Command
SDCKE
#SDCEx
#SDRAS
#SDCAS
#SDWE
HDQM/LDQM
SDRENA bit
SDRIS bit
SDRINI bit
SDRMRS bit
Internal #WAIT
SDA10
SDBA[1:0]
SDA[12:11, 9:0]
PALLNOP
H
H
MRS REF REF CMD
Valid
Valid
Valid
Valid
Valid
Valid
100 µs min. t
RP
t
RSC
t
RC
t
RC
VCC(Min.)
Figur e 2.10 SDRAM Power-up and Initialization
SDRAM Co mmands
The SDRAM is con trolled by commands that are comprised of a combination of high or low logic level signals.
Table 2.11 lis ts the comm and s output by the SDRAM contr oller.
Table 2.11 List of the Supported SDRAM Commands
Command Pins
Function Symbol SDCKE DQM
H/LDQM Bank
A[15:14] SDA10 SDA
A[13:12]
A[10:1] #SDCEx #SDRAS #SDCAS #SDWE
Bank Active ACTV H X V V V L L H H
Bank Precharge PRE H X V L X L L H L
Precharge All PALL H X X H X L L H L
Write WRIT H XVLVLHLL
Read READ H XVLVLHLH
Mode Register Set MRS H X V V V LLLL
Deselect / NOP NOP HXXXXHXXX
Auto Refresh REF H X X X X L L L H
Self Refr esh Entry SELF H → LX XXXLLLH
Self Refresh Exit – L → HX XXXHXXX
Data Write/Output
Enable –HLXXXXXXX
Data Write/Output
Disable –HHXXXXXXX
V = valid, X = don’t care, L = low level, H = high level
Because all of these commands are output by the SDRAM controller as necessary, they do not need to be
controlled by a user program, except for the commencement of initialization by SDRINI.
VI SDRAM CONTROL LER BLOC K: S DRAM INTERFACE
S1C33L03 FUNCTION PART EPSON B-VI-2-15
A-1
B-VI
SDRAM
Burst Read Cycle
Except w hen the burst length is set to 1 (SDRBL[1:0] ≠ "00"), the SDRAM controller always reads data from the
SD RAM in bursts.
Figure 2.11 show s sev eral examples of timing charts when reading out 4-word data from the same row address in
varying bu rst lengths.
Example of parameter set tings: CAS latency = 2, tRCD = 2 cycles, tRP = 2 cycles
(1) B ur st le ngth = 8
BCLK
Command
SDCKE
#SDCEx
#SDRAS
#SDCAS
#SDWE
SDBA[1:0]
SDA[10]
SDA[12:11, 9:0]
LDQM/HDQM
DQ[15:0]
ACTVNOP
H
NOP NOPPRE NOP READ
BA BA
ROW
D(1) D(2) D(3) D(4) D(5) D(6)
tRCDtRP CAS latency
= 2
ROW COL
BA
(2) B ur st le ngth = 4
BCLK
Command
SDCKE
#SDCEx
#SDRAS
#SDCAS
#SDWE
SDBA[1:0]
SDA[10]
SDA[12:11, 9:0]
LDQM/HDQM
DQ[15:0]
ACTVNOP
H
NOP NOPPRE NOP READ
BA BA
ROW
D(1) D(2) D(3) D(4)
tRCDtRP CAS latency
= 2
ROW COL
BA
(3) B ur st le ngth = 2
BCLK
Command
SDCKE
#SDCEx
#SDRAS
#SDCAS
#SDWE
SDBA[1:0]
SDA[10]
SDA[12:11, 9:0]
LDQM/HDQM
DQ[15:0]
ACTVNOP
H
NOP NOPPRE NOP READ NOP READ
BA BA
ROW
D(1-1) D(1-2) D(2-1) D(2-2)
tRCDtRP CAS latency
= 2 CAS latency
= 2
ROW COL1
BA
COL2
BA
Figure 2.11 Burst Read in the Same Page
VI SDRAM CONTROL LER BLOC K: S DRAM INTERF ACE
B-VI-2-16 EPSON S1C33L03 FUNCTION PART
Figure 2.12 sho ws an example of a timing chart in cases where the row address is varied during burst read.
BCLK
Command
SDCKE
#SDCEx
#SDRAS
#SDCAS
#SDWE
SDBA[1:0]
SDA[10]
SDA[12:11, 9:0]
LDQM/HDQM
DQ[15:0]
ACTVNOP
H
NOP NOP NOPPRE NOP READ
BA BA
ROW1
D
(n)
D
(n+1)
D
(n+2)
D
(0)
D
(1)
D
(2)
tRCDtRP tRCD
tRAS
tRPCAS latency
= 2 CAS latency
= 2
ROW1 COLn
BA
ACTV NOPPRE NOP READ
BA BA
ROW2
ROW2 COL0
BA
Figur e 2.12 Changing Row Address During Burst Read
Single Read/Single Write
If the burst length is set to "1" (SDRBL[1:0] = "00"), the SDRAM controller reads data from the SDRAM in a
si ng le o per ation.
When writ ing to the SDRAM, data are always written in a single operation, no matter what burst length is selected.
BCLK
Command
SDCKE
#SDCEx
#SDRAS
#SDCAS
#SDWE
SDBA[1:0]
SDA[10]
SDA[12:11, 9:0]
LDQM/HDQM
DQ[15:0]
ACTVNOP
H
NOP NOPPRE NOP READ
BA1 BA1
ROW1
D(1)
tRCDtRP tRCDtRPCAS latency
= 2
ROW1 COL1
BA1
ACTV NOPPRE NOP
BA2 BA2
ROW2
ROW2 COL2
BA2
D(2)
WRIT
Figure 2.13 Single Read to Single Write (different page)
BCLK
Command
SDCKE
#SDCEx
#SDRAS
#SDCAS
#SDWE
SDBA[1:0]
SDA[10]
SDA[12:11, 9:0]
LDQM/HDQM
DQ[15:0]
ACTVNOP
H
NOP NOP NOPPRE NOP READ
BA BA
ROW1
D(n) D(n+1) D(n+2) D(m)
tRCDtRP CAS latency
= 2
ROW1 COLn
BA
WRIT NOP PRE
BA
COLm
BA
Figure 2.14 Burst Read to Single Write (same page)
VI SDRAM CONTROL LER BLOC K: S DRAM INTERFACE
S1C33L03 FUNCTION PART EPSON B-VI-2-17
A-1
B-VI
SDRAM
Refresh Mode
The SDRAM contr oller supports two SDRAM refresh modes: auto refresh and self-refresh.
Auto refresh
The SDRAM contr oller incorporates a 12-bit auto refresh counter. This counter continues counting on OSC3
clock edges, and when a specified count is reached, commands are sent to the SDRAM that precharges and
auto-refreshes all banks. The counter is reset at that time, and starts counting for the next refresh period. The
counter is also reset by self-refresh.
The auto-refresh period is determined by the OSC3 clock frequency and the count value set in the SDRARFC
[11:0] (D[B:0])/Auto refresh count register (0x39FFC6). For SDRARFC, set the appropriate value meeting
the specifications of your SDRAM. The count value is obtained by the equation below.
RFP
SDRARFC ≤–––––––– × fOSC3 - BL - CL - 2 × tRP - tRCD - 3
ROWS
RFP: Maximum refresh period [s]
ROW S:Row address size
fOSC3:OSC3 clock frequency [Hz]
BL: Burst length [word]
CL : CAS late ncy [N umber of SD_CLK cycles]
tRP:PRECHARGE command period [Number of SD_CLK cycles]
tRCD:ACTIVE to READ or WRITE delay tim e [Number of SD_CLK cycles]
If RFP = 64 ms, ROWS = 4,096, fOSC3 = 20 MHz, BL = 8, CL = 3, tRP = 4, a nd tRCD = 4, for example, the
value to set is calculated as follows:
0.064
SDRARFC ≤–––––––– × 20,000,000 - 8 - 3 - 2 × 4 - 4 - 3 = 286
4,096
There fore, set any value equal to or less than 286 (0x11E) for SDRARFC.
BCLK
Command
SDCKE
#SDCEx
#SDRAS
#SDCAS
#SDWE
SDBA[1:0]
SDA[10]
SDA[12:11, 9:0]
LDQM/HDQM
DQ[15:0]
REF REFNOP
H
L
NOP NOPPALL NOP
t
RC
t
RP
Figure 2.15 Auto Refresh
VI SDRAM CONTROL LER BLOC K: S DRAM INTERF ACE
B-VI-2-18 EPSON S1C33L03 FUNCTION PART
Self refresh
Self-refresh uses the SDRAM’s self-refresh function and does not require clock pulses during the refresh
period, thus helping to reduce the chip’s power consumption. This self-refresh function is also used for data
retention during power-d ow n mode.
To cause the SDRAM to be self-refreshed, set the SDRSRF (D5)/SDRAM control register (0x39FFC1) to "1".
This enables the SDRAM controller to send the self-refresh command (which sets the SDCKE output to low)
to the SDRAM. The command is actually sent a certain time after accessing or auto-refreshing the SDRAM,
so the SDRAM controller contains a 4-bit self-refresh counter to count this time. The counter counts on
SD RAM clock (SD_CLK) edges, and when the designated count is reached, the SDRAM controller sends the
refresh command to the SDRAM. When an SDRAM access or auto-refresh command is issued, the counter is
reset and starts counting again. The designated value for the counter can be specified in a range of 2 to 15 by
using the SDRSRFC[3:0] (D[3:0])/SDRAM self refresh count register (0x39FFC8). Always set the SDRAM
self refresh count register to 2 or more. If it is set to less than 2, the SDRAM cannot exit self-refresh mode.
When an SDRAM access occurs during self-refresh mode, SDCKE is returned high and the SDRAM is taken
ou t of self-refresh mode.
BCLK
Command
SDCKE
#SDCEx
#SDRAS
#SDCAS
#SDWE
SDBA[1:0]
SDA[10]
SDA[12:11, 9:0]
LDQM/HDQM
DQ[15:0]
SDRSRM
SELFNOP
L
NOPPALL NOP
Self refresh mode
Enters self refresh mode
1 clock cycle
Exits self refresh mode
t
RP
The SDRAM clock stops when SDRCLK = "0".
Figure 2.16 Self Refresh
During self-refresh (while SDCKE = low), the SDRSRM (D6)/SDRAM status register (0x39FFCA) remains
"0". Therefore, it is possible to determine whether or not self-refresh is in operation by reading this status
register.
Furthermore, SDRAM clock output during self-refresh can be turned off in order to reduce the chip’s power
consumption by setting the SDRCLK (D3)/SDRAM control register (0x39FFC1) to "0".
VI SDRAM CONTROL LER BLOC K: S DRAM INTERFACE
S1C33L03 FUNCTION PART EPSON B-VI-2-19
A-1
B-VI
SDRAM
Power-down Mode
The SDRAM contr oller supports three power-down modes for the S1C33 Core (HALT, HALT2, and SLEEP).
In HALT mode, the bus clock is not turned off. Therefore, this mode can be set at any time.
In HALT2 and SLEEP modes, the SDRAM’s auto-refresh function is disabled. Therefore, the SDRAM must be
placed in self-r efresh mo de before enteri ng HALT2 or SLEE P m ode , by following the procedure descri bed be low .
1. Set SD RSRF (D 5/0x39FFC1) to "1" in or der to enable the SDRAM’s self-refresh function.
2. Check to s ee that SDRSRM ( D6/0x39FFCA ) = "0" (i.e., SDRAM is being self-refreshed).
3. Execute the HALT or SLP instruction.
Because the OSC3 clock is required for the SDRAM controller to be able to operate, the SDRAM must also be
placed in self-refresh mode following the above procedure before switching the CPU clock to OSC1 or turning the
OSC3 clock off.
Note:Because the SDRAM is taken out of se lf- ref resh mo de wh en acce ss ed , ste ps 2 and 3 of t he ab ov e
procedure mu st be executed on other me m ory than SDRAMs.
Bus Release Procedure
When the CPU releases the external bus, all of the SDRAM signal input/output pins, except for BCLK output when
SD RCLK = "1", are placed in the high-impedance state or set for input mode. As a result, another device acting as
the bus master gains control of the SDRAM.
The following illustrates a procedure where control of the SDRAM is switched.
BCLK
INTX (external device)
#BUSREQ
#BUSACK
D[15:0]
A[23:0], #RD, #WR
SDRAM status
CKE (external device)
SDCKE (S1C33)
SDRAM control (S1C33)
SDRAM control (external device)
1 cycle
Synchronization
Synchronization
S1C33 terminates
the current bus cycle. S1C33 controls
bus cycles.
1 cycle
Hi-Z
Hi-Z
Hi-Z
Hi-ZHi-Z
Hi-Z
Hi-Z
1 cycle
CMD Self refresh
Self refresh CMD Self refresh
Self refresh CMD Self refresh
Self refresh
The external bus
master controls
bus cycles.
Figur e 2.17 Bus Release Procedure
VI SDRAM CONTROL LER BLOC K: S DRAM INTERF ACE
B-VI-2-20 EPSON S1C33L03 FUNCTION PART
1. The device act ing as the external bus master prompts the S1C33 to be prepared to release the bus by means of
an interrupt or some other means.
2. When the S1C33 bec omes r eady to release the bus, it sets SDRSRF (D5/0x39FFC1) to "1" to place the SDRAM
in self-refresh mode. The S1C33 should stop accessing the SDRAM thereafter.
3. After the SDRAM is placed in self-refresh mode, the external device outputs a bus request.
4. Simultaneously with 3, the external device pulls the SDCKE signal low to ensure that the SDRAM will not be
taken out of self-refresh mode when the bus is released.
5. In response to the bus request, the S1C33 releases the external bus. The external bus, including the SDRAM
interface pins, goes to a high-impedance state.
6. The exter nal bus master takes over control of the SDRAM. If SDRCLK (D3/0x39FFC1) = "1", a clock for the
SD RAM is output from the BCLK pin. Therefore, the external bus master must control the SDRAM
synchronously with that clock. If SDRCLK = "0", BCLK also goes to a high-impedance state at the same time
the bus is released. Therefore, the external bus master supplies a clock to the SDRAM.
Note:If the SDRAM is not accessed after the bus is released, pull the SDRAM’s CKE pin down to low to
keep the self-r efresh mo de in order to maintain the SDRAM data while th e b us is released.
VI SDRAM CONTROL LER BLOC K: S DRAM INTERFACE
S1C33L03 FUNCTION PART EPSON B-VI-2-21
A-1
B-VI
SDRAM
I/O Memo ry of SDRAM Interfac e
Table 2.12 shows t he control bits of the SDRAM interface. These registers are mapped into area 6 (0x39FFC0 to
0x39FFCA). Table 2.12 Control Bits of SDRAM Interface
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
–
SDRAR0
SDRAR1
–
SDRPC0
SDRPC1
–
D7
D6
D5–4
D3
D2
D1–0
Area 7/13 configuration
Area 8/14 configuration
reserved
#CE7/13 pin configuration
#CE8/14 pin configuration
reserved
0
0
–
0
0
–
R/W
R/W
–
R/W
R/W
–
0 when being read.
0 when being read.
039FFC0
(B) 1SDRAM 0
Not SDRAM
1SDRAM 0
Not SDRAM
1#SDCE0 0#CE7/13
1#SDCE1 0#CE8/14
SDRAM area
configuration
register
–
SDRENA
SDRINI
SDRSRF
SDRIS
SDRCLK
–
D7
D6
D5
D4
D3
D2–0
Enable SDRAM signals
Start SDRAM power up
Enable SDRAM self-refresh
Initial command sequence
Keep SDCLK during self-refresh
reserved
0
0
0
0
1
–
R/W
R/W
R/W
R/W
R/W
–
0 when being read.
0 when being read.
039FFC1
(B) 1Enabled 0Disabled
1Start 0 –
11 precharge
2 set reg.
3 refresh
01 precharge
2 refresh
3 set reg.
1Enabled 0Disabled
1Kept 0Stopped
SDRAM
control register
–
–
––
SDRCA1
SDRCA0
–
SDRRA1
SDRRA0
SDRBA
–
D7
D6–5
D4
D3–2
D1
D0
reserved
SDRAM page size
(column range)
reserved
SDRAM row addressing range
Number of SDRAM banks
reserved
–
0
0
–
0
0
0
–
–
R/W
–
R/W
R/W
–
0 when being read.
0 when being read.
0 when being read.
039FFC2
(B)
14 banks 02 banks
SDRAM
address
configuration
register
1
1
0
0
1
0
1
0
SDRRA[1:0] Addressing range
reserved
8K (SDA[12:0])
4K (SDA[11:0])
2K (SDA[10:0])
1
1
0
0
1
0
1
0
SDRCA[1:0] Page size
reserved
1K (SDA[9:0])
512 (SDA[8:0])
256 (SDA[7:0])
–
–
––
SDRCL1
SDRCL0
–
SDRBL1
SDRBL0
–
D7
D6–5
D4
D3–2
D1–0
reserved
SDRAM CAS latency
reserved
SDRAM burst length
reserved
–
1
1
–
1
1
–
–
R/W
–
R/W
–
0 when being read.
0 when being read.
0 when being read.
039FFC3
(B)
SDRAM
mode set-up
register 1 0
SDRCL[1:0] CAS latency
2 CAS latency
1
1
0
0
1
0
1
0
SDRBL[1:0] Burst length
8
4
2
1
SDRTRAS2
SDRTRAS1
SDRTRAS0
SDRTRP1
SDRTRP0
SDRTRC2
SDRTRC1
SDRTRC0
D7–5
D4–3
D2–0
SDRAM t
RAS
spec
SDRAM t
RP
spec
SDRAM t
RC
spec
0
0
0
0
0
0
0
0
R/W
R/W
R/W
039FFC4
(B)
SDRAM
timing set-up
register 1 1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
SDRTRAS[2:0]
Number of clocks
7
6
5
4
3
2
1
8
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
SDRTRC[2:0]
Number of clocks
7
6
5
4
3
2
1
8
1
1
0
0
1
0
1
0
SDRTRP[1:0]
Number of clocks
3
2
1
4
VI SDRAM CONTROL LER BLOC K: S DRAM INTERF ACE
B-VI-2-22 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
SDRTRCD1
SDRTRCD0
SDRTRSC
SDRTRRD1
SDRTRRD0
–
D7–6
D5
D4–3
D2–0
SDRAM t
RCD
spec
SDRAM t
RSC
spec
SDRAM t
RRD
spec
reserved
0
0
0
0
0
–
R/W
R/W
R/W
–0 when being read.
039FFC5
(B)
SDRAM
timing set-up
register 2 1
1
0
0
1
0
1
0
SDRTRCD[1:0]
Number of clocks
3
2
1
4
1
1
0
0
1
0
1
0
SDRTRRD[1:0]
Number of clocks
3
2
1
4
–
11 clock 02 clocks
–
SDRARFC11
SDRARFC10
SDRARFC9
SDRARFC8
SDRARFC7
SDRARFC6
SDRARFC5
SDRARFC4
SDRARFC3
SDRARFC2
SDRARFC1
SDRARFC0
DF–C
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
SDRAM auto refresh count [11:0] –
1
1
1
1
1
1
1
1
1
1
1
1
–
R/W 0 when being read.039FFC6
(HW)
SDRAM
auto refresh
count register 0 to 4096
–
–
SDRSRFC3
SDRSRFC2
SDRSRFC1
SDRSRFC0
D7–4
D3
D2
D1
D0
reserved
SDRAM self refresh count [3:0] –
1
1
1
1
–
R/W 0 when being read.
This register must
not be set less than
"0x02".
039FFC8
(B)
SDRAM
self refresh
count register 2 to 15
–
–
––
SDRSZ
SDRBI
–
D7
D6
D5
D4–0
reserved
SDRAM data path bit width
SDRAM bank interleaved access
reserved
–
0
0
–
–
R/W
R/W
–
0 when being read.
0 when being read.
039FFC9
(B) 18 bits 016 bits
1Interleaved 0One bank
SDRAM
advanced
control
register
–
SDRMRS
SDRSRM
–
D7
D6
D5–0
SDRAM mode register set flag
SDRAM current refresh mode
reserved
1
1
–
R
R
–0 when being read.
039FFCA
(B) 1Not finished 0Done
1
Auto refresh
0Self refresh
SDRAM
status register
Note:Do not acce ss addresses 0x03 9FFCB to 0x039FFCD, beca use they are reserved for t esting the
SDRAM controller.
VI SDRAM CONTROL LER BLOC K: S DRAM INTERFACE
S1C33L03 FUNCTION PART EPSON B-VI-2-23
A-1
B-VI
SDRAM
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
A14DRA
A13DRA
A14SZ
A14DF1
A14DF0
–
A14WT2
A14WT1
A14WT0
DF–9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Area 14 DRAM selection
Area 13 DRAM selection
Areas 14–13 device size selection
Areas 14–13
output disable delay time
reserved
Areas 14–13 wait control
–
–
1Used 0Not used
1Used 0Not used
18 bits 016 bits
–
0
0
0
1
1
–
1
1
1
–
R/W
R/W
R/W
R/W
–
R/W
0 when being read.
0 when being read.
0048122
(HW)
1
1
0
0
1
0
1
0
A14DF[1:0] Number of cycles
3.5
2.5
1.5
0.5
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A14WT[2:0] Wait cycles
7
6
5
4
3
2
1
0
Areas 14–13
set-up register
–
A8DRA
A7DRA
A8SZ
A8DF1
A8DF0
–
A8WT2
A8WT1
A8WT0
DF–9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Area 8 DRAM selection
Area 7 DRAM selection
Areas 8–7 device size selection
Areas 8–7
output disable delay time
reserved
Areas 8–7 wait control
–
–
1Used 0Not used
1Used 0Not used
18 bits 016 bits
–
0
0
0
1
1
–
1
1
1
–
R/W
R/W
R/W
R/W
–
R/W
0 when being read.
0 when being read.
0048128
(HW)
Areas 8–7
set-up register
1
1
0
0
1
0
1
0
A8DF[1:0] Number of cycles
3.5
2.5
1.5
0.5
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A8WT[2:0] Wait cycles
7
6
5
4
3
2
1
0
–
A6DF1
A6DF0
–
A6WT2
A6WT1
A6WT0
–
A5SZ
A5DF1
A5DF0
–
A5WT2
A5WT1
A5WT0
DF–E
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Area 6
output disable delay time
reserved
Area 6 wait control
reserved
Areas 5–4 device size selection
Areas 5–4
output disable delay time
reserved
Areas 5–4 wait control
–
–
–
18 bits 016 bits
–
1
1
–
1
1
1
–
0
1
1
–
1
1
1
–
R/W
–
R/W
–
R/W
R/W
–
R/W
0 when being read.
0 when being read.
0 when being read.
0 when being read.
004812A
(HW)
Areas 6–4
set-up register 1
1
0
0
1
0
1
0
A6DF[1:0] Number of cycles
3.5
2.5
1.5
0.5
1
1
0
0
1
0
1
0
A5DF[1:0] Number of cycles
3.5
2.5
1.5
0.5
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A6WT[2:0] Wait cycles
7
6
5
4
3
2
1
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A5WT[2:0] Wait cycles
7
6
5
4
3
2
1
0
VI SDRAM CONTROL LER BLOC K: S DRAM INTERF ACE
B-VI-2-24 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
RBCLK
–
RBST8
REDO
RCA1
RCA0
RPC2
RPC1
RPC0
RRA1
RRA0
–
SBUSST
SEMAS
SEPD
SWAITE
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BCLK output control
reserved
Burst ROM burst mode selection
DRAM page mode selection
Column address size selection
Refresh enable
Refresh method selection
Refresh RPC delay setup
Refresh RAS pulse width
selection
reserved
External interface method selection
External bus master setup
External power-down control
#WAIT enable
–
–
1Fixed at H 0Enabled
1
8-successive
0
4-successive
1Enabled 0Disabled
1Self-refresh 0
CBR-refresh
12.0 01.0
1#BSL 0A0
1Existing 0Nonexistent
1Enabled 0Disabled
1Enabled 0Disabled
1EDO 0Fast page
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
–
R/W
R/W
R/W
R/W
Writing 1 not allowed.
Writing 1 not allowed.
004812E
(HW)
1
1
0
0
1
0
1
0
RCA[1:0] Size
11
10
9
8
1
1
0
0
1
0
1
0
RRA[1:0] Number of cycles
5
4
3
2
Bus control
register
1Successive 0Normal
–
A3EEN
CEFUNC1
CEFUNC0
CRAS
RPRC1
RPRC0
–
CASC1
CASC0
–
RASC1
RASC0
DF–C
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Area 3 emulation
#CE pin function selection
Successive RAS mode setup
DRAM
RAS precharge cycles selection
reserved
DRAM
CAS cycles selection
reserved
DRAM
RAS cycles selection
– –
1
0
0
0
0
0
–
0
0
–
0
0
–
R/W
R/W
R/W
R/W
–
R/W
–
R/W
0 when being read.
0 when being read.
0 when being read.
0048130
(HW)
1
0
0
x
1
0
CEFUNC[1:0]
#CE output
#CE7/8..#CE17/18
#CE6..#CE17
#CE4..#CE10
1
1
0
0
1
0
1
0
RPRC[1:0] Number of cycles
4
3
2
1
–
1
1
0
0
1
0
1
0
CASC[1:0] Number of cycles
4
3
2
1
–
1
1
0
0
1
0
1
0
RASC[1:0] Number of cycles
4
3
2
1
DRAM timing
set-up register 1
Internal ROM
0Emulation
–
1Internal
access 0External
access
1Internal
access 0External
access
1Big endian 0
Little endian
A18IO
A16IO
A14IO
A12IO
–
A8IO
A6IO
A5IO
A18EC
A16EC
A14EC
A12EC
A10EC
A8EC
A6EC
A5EC
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Area 18, 17 internal/external access
Area 16, 15 internal/external access
Area 14, 13 internal/external access
Area 12, 11 internal/external access
reserved
Area 8, 7 internal/external
access
Area 6 internal/external
access
Area 5, 4 internal/external
access
Area 18, 17 endian control
Area 16, 15 endian control
Area 14, 13 endian control
Area 12, 11 endian control
Area 10, 9 endian control
Area 8, 7 endian control
Area 6 endian control
Area 5, 4 endian control
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.
0048132
(HW)
Access control
register
VI SDRAM CONTROL LER BLOC K: S DRAM INTERFACE
S1C33L03 FUNCTION PART EPSON B-VI-2-25
A-1
B-VI
SDRAM
A14SZ:Areas 14–13 device size selecti on (D 6) / Areas 14–13 set-up register (0x48122)
A8SZ:Areas 8–7 device si ze se lecti on (D 6) / Areas 8–7 set-up registe r (0x48128)
Select the size of the device connected to each area.
Write "1": 8 bits
Write "0": 1 6 bits
Read: Valid
Set the device size of the area used for an SDRAM in the same manner as that specified for SDRSZ
(D6/0x39FFC9).
At c old start, these bits are set to "0" (16 bits). At hot start, these bits retain their status before being initialized.
A14WT2–A14WT0:Areas 14–13 wa it control ( D [2:0] ) / Areas 14–13 set-up regis ter (0x48122)
A8WT2–A8WT0:Areas 8–7 wait control ( D [2:0] ) / Areas 8–7 set-up register (0x48128)
A6WT2–A6WT0:Area 6 wait contr ol (D[A:8] ) / Areas 6–4 set-up register (0x4812A )
Set the number of wait cycles to be inserted when accessing the internal device.
The values 0 through 7 wr itten to the control bits equal the number of wait cycles inserted.
Alwa ys make sure the number of wait cycles in area 6 (where the SDRAM controller is allocated) is 2 (A6WT =
"010"). Wit h an y other number of specified wait cycles, da ta ma y not be written normally to the SDRAM control
registers.
The number of wait cycles in areas used for SDRAMs should be set to 0 (A8WT/A14WT = "000").
At c old start, these bits are set to "111" (7 cycles). At hot start, the bits retain their status before being initialized.
A14DF1–A14DF0:Ar ea s 14 –1 3 ou t put di s able de lay tim e (D[ 5: 4]) / Area s 14 –1 3 set -up r eg iste r (0x 481 22 )
A8DF1–A8DF0:Area s 8–7 ou t put dis ab le de l ay t ime ( D[ 5:4] ) / Ar eas 8– 7 se t-u p reg is ter ( 0x481 28 )
Set the output-disable delay time. Table 2.13 Output Disable Delay Time
AxxDF1 AxxDF0 Delay time
113.5 cycles
102.5 cycles
011.5 cycles
000.5 cycles
If the system has an external memory device other than the SDRAM connected to it and accesses that memory
device and reads the SDRAM in succession, set the output disable delay time for the areas used for the SDRAM to
2.5 cycles (A8DF/A14DF = "10").
Otherwise, set the output disable delay time to 0.5 cycles (A8DF/A14DF = "00") in order to reduce the SDRAM
access time.
At c old start, these bits are set to "11" (3.5 cycles). At hot start, the bits retain their status before being initialized.
SWAITE: #WAI T en able (D0) / Bus control r egister (0x 4812E )
Enabl e or disable wai t c ycle control.
Write "1": Ena bled
Write "0": Disabl ed
Read: Valid
Because the SDRAM controller controls wait cycles internally in the IC, SWAITE must be set to "1".
At c old start, SWAITE is set to "0" (disabled). At hot start, SWAITE retains its status before being initialized.
VI SDRAM CONTROL LER BLOC K: S DRAM INTERF ACE
B-VI-2-26 EPSON S1C33L03 FUNCTION PART
CEFUNC1–CEFUNC0: #CE pin function selection (D[A:9]) / DRAM timing set-up register (0x48130)
Select an area for connection with an SDRAM.
Table 2.14 #CE Output Assignment
PinCEFUNC = "00" CEFUNC = "01" CEFUNC = "1x"
#CE7/#SDCE0 #CE7/#SDCE0 #CE13/#SDCE0 #CE13/#SDCE0
#CE8/#SDCE1 #CE8/#SDCE1 #CE14/#SDCE1 #CE14/#SDCE1
(Default: CEFUNC = "00")
Set CEFUNC = " 00" to use areas 7/8 for SDRAMs or CEFUNC = "01" to use areas 13/14 for SDRAMs.
At c old start, CEFUNC is set to "00". At hot start, CEFUNC retains its status before being initialized.
A14IO:Areas 14–1 3 inter nal/external access selection ( DD) / Access cont rol regis ter (0x48132)
A8IO:Areas 8–7 internal/external access selection (DA) / Access control register (0x48132)
A6IO:Area 6 internal/external access selection (D9) / Access control register (0x48132)
Select either internal access or external access for each area.
Write "1": Inte rnal access
Write "0": Extern al access
Read: Valid
Before the SDRAM controller can be used, A6IO must be set to "1" (internal access). Also, set A8IO to "1" to use
areas 7/8 for SDRAMs or set A14IO to "1" to use areas 13/14 for SDRAMs.
At c old start, these bits are set to "0" (external access). At hot start, these bits retain their status before being
initialized.
A6EC: Area 6 little/big endian method selection (D1) / Access control register (0x48132)
Select either little endian or big endian method for accessing each area.
Write "1": Big endian
Write "0 " : L ittle endi an
Read: Valid
Set this register bit in the same way as set by LCDCEC (D0/0x39FFFD).
At cold start, this bit is set to "0" (little endian). At hot start, this bit retains its status before being initialized.
SDRAR1:Area 8/14 configuration (D6) / SDRAM area configuration register (0x39FFC0)
SDRAR0:Area 7/13 configuration (D7) / SDRAM area configuration register (0x39FFC0)
Set the area to be used for an SDRAM.
Write "1": For SDRAM
Write "0": For other devices
Read: Valid
SD RAM s can be connected to areas 7/8 or to areas 13/14. Write "1" to SDRAR0 to set area 7 or 13 for SDRAM
use. Similar ly, write "1" to SDRAR1 to set area 8 or 14 for SDRAM use. Writing a "0" to either bit sets the
corresponding area to be used for devices other than an SDRAM.
At c old start, these bits are set to "0" (For a device not SDRAM). At hot start, these bits retain their status before
being initialized.
VI SDRAM CONTROL LER BLOC K: S DRAM INTERFACE
S1C33L03 FUNCTION PART EPSON B-VI-2-27
A-1
B-VI
SDRAM
SDRPC1:#CE8/14 pin configuration (D2) / SDRAM area configuration register (0x39FFC0)
SDRPC0:#CE7/13 pin configura tion (D3) / SDRAM ar ea configuration register (0x39FFC0)
Set the chip-enable pin for an SDRAM.
Write "1": # SDCEx (for SDRAM)
Write "0": # CExx (f or o ther devices)
Read: Valid
Select the pin to be used as a chip enable for the SDRAM connected to the S1C33. Write "1" to SDRPC0 to set the
#C E7/13 pin for SDRAM use (#SDCE0). Similarly, write "1" to SDRPC1 to set the #CE8/14 pin for SDRAM use
(#SDCE1). Writing "0" to either bit sets the corresponding pin to be used as chip-enable out put for other devices.
SD RAM s and the BCU are used differently—with SDRAMS, the areas and the pins used are not associated with
each other. Consequently, when using area 7 for an SDRAM, for exam ple, it is po ssible to us e #CE8 /14 as the
chip-enable pin for the SDRAM. Or while using both areas 7 and 8, it is possible to use only #CE7/13 as the chip-
enable pin. See Table 2.5 for the combinations of areas and pins used.
At c old start, these bits are set to "0" (#CExx). At hot start, these bits retain their status before being initialized.
SDRENA: Enabl e SDRAM si gnal s (D7) / S DR A M control register (0 x39FFC 1)
Enable the pins used for the SDRAM.
Write "1": Ena bled
Write "0": Disabl ed
Read: Valid
Writing "1" to SDRENA sets the pins shared with other functions to be used for the SDRAM, with the SDRAM
clock output from the BCLK pin. If SDRENA = "0", the shared pins serve other functions.
The SDRAM clock output from the BCLK pin is stopped in the HALT2 and the SLEEP modes.
At c old start, SDRENA is set to "0" (disabled). At hot start, SDRENA retains its status before being initialized.
SDRINI: Initialize SDRAM (D6) / SDRAM control register (0x39FFC1)
Initiate the SDRAM initialization sequence.
Write "1": Star t
Write "0": No operation
Read: Valid
Writing "1" to SDRINI initiates the SDRAM initialization sequence at SDRAM power-up, as specified by SDRIS
(D4/0x39FFC1). This operation must be performed after holding the SDRAM in an NOP state for at least 100 µs
(this varies with each SDRAM) after powering up the SDRAM.
At c old or ho t sta rt, SDRINI is set to "0".
SDRSRF: Enable S DRA M self-refre s h (D5) / S DR A M con tro l regi st er (0 x3 9F FC1 )
Enable the SDRAM's self-refresh control function.
Write "1": Ena bled
Write "0": Disabl ed
Read: Valid
Writing "1" to SDRSRF enables the SDRAM controller to start self-refreshing the SDRAM (by setting SDCKE
output low). Note that self-refreshing of the SDRAM actually begins a certain time after accessing or auto-
refreshing the SDRAM. The duration of this elapsed time is defined by the number of clock cycles in
SD RSRFC[ 3:0] (D[3: 0]/0x39FFC8).
SD RSRF = "0" disables the self-refresh function.
At c old start, SDRSRF is set to "0" (disabled). At hot start, SDRSRF retains its status before being initialized.
VI SDRAM CONTROL LER BLOC K: S DRAM INTERF ACE
B-VI-2-28 EPSON S1C33L03 FUNCTION PART
SDRIS: Initial c omm and sequence (D4) / SDRAM control r egister (0x 39FF C1)
Select the SDRAM initialization sequence.
Write "1": 1 . Precharge → 2. Mode Register Set → 3. Refresh
Write "0": 1 . Precharge → 2. Refresh → 3. Mode Register Set
Read: Valid
In accordance with the specifications of the SDRAM, select a sequence to determine the order the commands are
sent to initialize the SDRAM. Initialization of the SDRAM is initiated by writing "1" to SDRINI (D6/0x39FFC1).
At c old start, SDRIS is set to "0" (1. Precharge → 2. Refresh → 3. M ode Registe r Set). At ho t start, SDRIS retains
its status before being initialized.
SDRCLK: Keep S DRA M cloc k d uri ng self -re fre s h (D3) / S DRA M con tro l regi st er (0 x3 9F FC1 )
Select whether or not to stop the SDRAM clock during self-refresh.
Write "1": Kept outputting
Write "0": Stopped
Read: Valid
Writing "0" to SDRCLK causes the SDRAM clock out put from the BCLK pin to stop and to remain off while the
SD RAM is self-refreshed. This helps to reduce the chip's current consumption. Note that when the bus is released,
the BCLK pin goes into a high-impedance state.
If SDRCLK = "1", the SDRAM clock is always output from the BCLK pin even while the SDRAM is self-
refreshed or the bus is released.
At c old start, SDRCLK is set to "1" (kept outputting). At hot start, SDRCLK retains its status before being
initialized.
SDRCA1–SDRCA0: SDRAM page size (D[6:5]) / SDRAM addres s conf iguratio n register (0 x39FFC 2)
Set the SDRAM page size (column ad dressi n g ra ng e).
Table 2.15 Setting Column Addressing Range (Page Size)
SDRCA1 SDRCA0 Column size Column address (pin) used
00 256SDA0–SDA7 (default)
01 512 SDA0–SDA8
10 1,024 SDA0–SDA9
11 – –
The con tents set here are applied to all of areas 7, 8, 13, and 14 that are set for SDRAM.
SD RCA can be read to obtain its set value.
At c old start, SDRCA is set to "0" (256). At hot start, SDRCA retain its status before being initialized.
SDRRA1–SDRRA0: SDRAM row addr essing range (D[3:2]) / SDRAM address configuration register (0x39FFC2)
Set the SDRAM row addressing range.
Table 2.16 Setting Row Addressing Range
SDRRA1 SDRRA0 Row size Row address (pin) used
00 2KSDA0–SDA10 (default)
01 4K SDA0–SDA11
10 8K SDA0–SDA12
11 – –
The con tents set here are applied to all of areas 7, 8, 13, and 14 that are set for SDRAM.
SD RRA can be r ead to obtain its set value.
At c old start, SDRRA is set to "0" (2K). At hot start, SDRRA retain its status before being initialized.
VI SDRAM CONTROL LER BLOC K: S DRAM INTERFACE
S1C33L03 FUNCTION PART EPSON B-VI-2-29
A-1
B-VI
SDRAM
SDRBA: Number of SDRAM bank s (D1) / SDRAM address co nfiguration register (0x 39FF C2)
Set the num ber of banks of the SDRAM.
Write "1": 4 banks
Write "0": 2 banks
Read: Valid
Set "1" when a SDRAM configured with 4 banks is used or set "0" when a SDRAM configured with 2 banks is
used.
The con tents set here are applied to all of areas 7, 8, 13, and 14 that are set for SDRAM.
At c old start, SDRBA is set to "0" (2 banks). At hot start, SDRBA retains its status before being initialized.
SDRCL1–SDRCL0: SDRAM CAS latency (D[6:5]) / SDRAM mode set-up register (0x39FFC3)
Set the CAS latency of the SDRAM.
Table 2.17 Setting CAS Latency
SDRCL1 SDRCL0 CAS latency (number of clocks)
10 2
Oth er setti ngs Not al lowe d
The SDRAM controller does not support CAS latencies other than 2.
At c old start, SDRCL is set to "11". Be sure to reset to "10" so that the CAS latency is set to 2. At hot start, SDRCL
retain it s status b efo re bein g in iti alize d.
SDRBL1–SDRBL0: SDRAM burst length (D[3:2]) / SDRAM mode set-up register (0x39FFC3)
Set the burst read length of the SDRAM.
Table 2.18 Setting Burst Length
SDRBL1 SDRBL0 Burst length (word)
00 1
01 2
10 4
11 8
The SDRAM contr oller does not support burst write, so the set burst length is effective only for read cycles.
At c old start, SDRBL is set to "11" (8). At hot start, SDRBL retain its status before being initialized.
SDRTRAS2–SDRTRAS0: SDRAM tRAS spec (D[7:5]) / SDRAM timing set-up register 1 (0x39FFC4)
Set the tRAS SDRAM parameter (ACTIVE to PRECHARGE command period).
In accordance with the specifications of the SDRAM, specify this parameter in terms of the number of SDRAM
clock cycles. Specifying 1–7 sets the period to 1–7 clock cycles. Specifying 0 sets the period to 8 clock cycles.
At c old start, SDRTRAS is set to "000" (8). At hot start, SDRTRAS retain its status before being initialized.
SDRTRP1–SDRTRP0: SDRAM tRP spec (D[4:3]) / SDRAM timing set-up register 1 (0x39FFC4)
Set the tRP SDRAM parameter (PRECHARGE command period).
In accordance with the specifications of the SDRAM, specify this parameter in terms of the number of SDRAM
clock cycles. Specifying 1–3 sets the period to 1–3 clock cycles. Specifying 0 sets the period to 4 clock cycles.
At c old start, SDRTRP is set to "00" (4). At hot start, SDRTRP retain its status before being initialized.
SDRTRC2–SDRTRC0: SDRAM tRC spec (D[2:0]) / SDRAM timing set-up register 1 (0x39FFC4)
Set the tRC SDRAM parameter (ACTIVE to ACTIVE command period).
In accordance with the specifications of the SDRAM, specify this parameter in terms of the number of SDRAM
clock cycles. Specifying 1–7 sets the period to 1–7 clock cycles. Specifying 0 sets the period to 8 clock cycles.
At c old start, SDRTRC is set to "000" (8). At hot start, SDRTRC retain its status before being initialized.
Note:When the auto-refr esh co m mand is executed, the fol lowing comm and may be i ssue d 3 or 4
CPU_CLK cycl es from that point regardless of the tRC value set in the SDRTRC register.
Therefore, us e SDRAMs with 75 ns or les s of tRC.
VI SDRAM CONTROL LER BLOC K: S DRAM INTERF ACE
B-VI-2-30 EPSON S1C33L03 FUNCTION PART
SDRTRCD1–SDRTRCD0: SDRAM tRCD spec (D[7:6]) / SDRAM timing set-up register 2 (0x39FFC5)
Set the tRCD SDRAM parameter (ACTIVE to READ or WRITE delay time).
In accordance with the specifications of the SDRAM, specify this parameter in terms of the number of SDRAM
clock cycles. Specifying 1–3 sets the period to 1–3 clock cycles. Specifying 0 sets the period to 4 clock cycles.
At c old start, SDRTRCD is set to "00" (4). At hot start, SDRTRCD retain its status before being initialized.
SDRTRSC: SDRAM tRSC spec (D5) / SDRAM timing set-up register 2 (0x39FFC5)
Set the tRSC SDRAM parameter (Mode Register Set cycle time).
Write "1": 1 cl ock
Write "0": 2 cl ocks
Read: Valid
In accordance with the specifications of the SDRAM, specify this parameter in terms of the number of SDRAM
clock cycles.
At c old start, SDRTRSC is set to "0" (2). At hot start, SDRTRSC retain its status before being initialized.
SDRTRRD1–SDRTRRD0: SDRAM tRRD spec (D[4:3]) / SDRAM timing set-up register 2 (0x39FFC5)
Set the tRRD SDRAM parameter (ACTIVE bank (a) to ACTIVE bank (b) period).
In accordance with the specifications of the SDRAM, specify this parameter in terms of the number of SDRAM
clock cycles. Specifying 1–3 sets the period to 1–3 clock cycles. Specifying 0 sets the period to 4 clock cycles.
At c old start, SDRTRRD is set to "00" (4). At hot start, SDRTRRD retain its status before being initialized.
SDRARFC11–SDRARFC0: SDRAM auto refresh count (D[B:0]) / SDRAM auto refresh count register (0x39FFC6)
Set the auto refresh counter value.
The auto-refresh counter counts up on the OSC3 clock edges beginning with 0, and when the count specified here
is reached, the SDRAM controller sends an auto-refresh command. The counter is reset at that point, and starts
counting the next refresh period. The counter is also reset by self-refresh.
The valu e calculated from t he equation below is the maximum count that can be set.
RFP
SDRARFC ≤–––––––– × fOSC3 - BL - CL - 2 × tRP - tRCD - 3
ROWS
RFP: Maximum refresh period [s]
ROW S:Row address size
fOSC3:OSC3 clock frequency [Hz]
BL: Burst length [word]
CL : CAS l atency [Number of SD _CLK c locks]
tRP:PRECHARGE command period [Number of SD_CLK clocks]
tRCD:ACTIVE to READ or WRITE delay tim e [Number of SD_CLK clocks]
At c old start, SDRARFC is set to "0xFFF" (4095). At hot start, SDRARFC retain its status before being initialized.
SDRSRFC3–SDRSRFC0: SDRAM self refresh count (D[3:0]) / SDRAM self refresh count register (0x39FFC8)
Set the self refresh counter value.
If SDRSRF (D5/0x39FFC1) is set to "1" (self-refresh-enabled), the self-refresh counter starts counting up on the
SD RAM clock edges beginning with 0 after accessing or auto-refreshing the SDRAM. When the count specified
here is reached, the SDCKE output is pulled low, causing the SDRAM to start self-refreshing. If an access to the
SD RAM occurs during self-refresh mode, SDCKE is returned high, thereby taking the SDRAM out of self-refresh
mode.
At c old start, SDRSRFC is set to "0xF" (15). At hot start, SDRSRFC retain its status before being initialized.
Note:Always set this register to 2 or more. If it is set to less than 2, the SDRAM cannot exit self-refresh
mode.
VI SDRAM CONTROL LER BLOC K: S DRAM INTERFACE
S1C33L03 FUNCTION PART EPSON B-VI-2-31
A-1
B-VI
SDRAM
SDRSZ: SDRAM data path bit width (D6) / SDRAM advanced co ntrol register (0x39FFC9)
Select the SDRAM data-path bit width.
Write "1": 8 bits
Write "0": 1 6 bits
Read: Valid
Set SDRSZ to "1" to use an 8-bit SDRAM or to "0" to use a 16-bit SDRAM.
At c old start, SDRSZ is set to "0" (16 bits). At hot start, SDRSZ retains its status before being initialized.
SDRBI: SDRA M bank interl eaved acce ss (D 5) / SDRAM adva nced co ntrol reg ister (0x39FFC9)
Enable the SDRAM's bank-interleaved access function.
Write "1": Inte rleaved
Write "0": One bank only
Read: Valid
Writing "1" to SDRBI activates multiple SDRAM banks at the same time, allowing for successive accesses of one
bank after another. If SDRBI = "0", multiple banks cannot be activated at the same time.
At c old start, SDRBI is set to "0" (one bank only). At hot start, SDRBI retains its status before being initialized.
SDRMRS: SDRA M mode regi st er s et fl ag (D7) / S DRA M status register (0x39FFCA)
Indicates the execution status of the MRS (Mode Register Set) command.
Read "1": Not finished
Read "0": Finished
Write: Invalid
SD RM RS is a utomatically set to "1" at power-on, and is reset to "0" by executing the MRS command in the
SD RAM initialization sequence. As the MRS command uses an external address bus, no other external devices can
be accessed until the command execution is finished. To access any external device other than the SDRAM
immediately after executing the SDRAM initialization sequence, read SDRMRS to confirm that the MRS
command execution is finished before attempting the intended access.
At c old start, SDRMRS is set to "1" (Not finished). At hot start, SDRMRS retains its status before being initialized.
SDRSRM: SDRAM current refresh mode (D6) / S DRA M stat us register (0x39FFCA)
Indicates the SDRAM refresh mode.
Read "1": Auto refresh mode
Read "0": Self refresh mode
Write: Invalid
SD RSRM i s " 0" while the SDRAM controller holds the SDCKE pin low (i.e., the SDRAM is in self-refresh mode).
Otherwise, SDRSRM = "1".
Before enter ing HA LT2 or SLEEP mode or rel easing the bus, always be sur e to read thi s bit using a program stored
elsewhere (i.e., not in the SDRAM) to confirm that the SDRAM is in self-refresh mode.
At c old start, SDRSRM is set to "1" (auto refresh mode). At hot start, SDRSRM retains its status before being
initialized.
VI SDRAM CONTROL LER BLOC K: S DRAM INTERF ACE
B-VI-2-32 EPSON S1C33L03 FUNCTION PART
Pr ogramming Notes
(1) Make sure that two wait cycles are inserted when accessing area 6, where the SDRAM controller is allocated.
With any other number of specified wait cycles, data may not be written normally to the SDRAM control
registers.
(2) Set the area used for an SDRAM for internal access (A8IO (DA/0x48132) = "1" or A14IO (DD/ 0x48 132) =
"1").
(3) Before entering HALT2 or SLEEP m ode , be sure to pl ace the SDRAM in sel f-refresh mode, because the
SD RAM cannot be auto-refreshed while in those modes. In that case, confirm that SDRSRM
(D6/0x39FFCA) = "0" (i.e., that the SDRAM is in self-refresh mode) before executing the HALT or SLP
instruction.
If an access to the SDRAM occurs while being self-refreshed, the SDRAM is taken out of self-refresh mode;
thus always make sure the SDRAM check and the HALT/SLP instruction execution are performed from
devices other than the SDRAM.
(4) Do not access addresses 0x039FFCB to 0x039FFCD, as the user program will not be able to control the CPU.
(5) If the program accesses an area out of the address range set using the address setting register (0x39FFC2), an
unintended area is accessed and the stored data may be overwritten. Therefore, do not access an area out of
the set range.
VI SDRAM CONTROL LER BLOC K: S DRAM INTERFACE
S1C33L03 FUNCTION PART EPSON B-VI-2-33
A-1
B-VI
SDRAM
Examples of SDRAM Controller Initialization Program
The following shows examples of the initialization program for using SDRAM.
Exam ple of initialization routine for 2M words × 16 bit s × 4 banks (16MB) of SD RAM
INIT_SDRAM_16MB:
;;;----------------------- SDRAM access configuration -----------------------------------
;;;*****************************************************************
;;;***************** C33 macro setting part ************************
;;;*****************************************************************
;;; set CEFUNC to use #CE13/1 4 (upper area) ... 1 (See "SDRAM Controller Configuration".)
xld.w %r0,0x48131
bset [%r0],0x1
;;; set area 6,13,14 to internal access ... 2, 5, B-1
xld.w %r0,0x48132
xld.w %r1,0x2200
ld.h [%r0], %r1
;;; area 6 -> output disable 0.5, wait 2 ... 3
xld.w %r0,0x4812A
xld.w %r1,0x0237
ld.h [%r0],%r1
;;; available #WAIT ... 4
xld.w %r0,0x04812E
bset [%r0],0x0
;;; area 13,14 -> 16bit device, output disable 2.5, wait 0 ... B-2, B-3, B-4
xld.w %r0,0x048122
xld.w %r1,0x30
ld.h [%r0],%r1
;;;*****************************************************************
;;;************** SDRAM Controller REG setting part ****************
;;;*****************************************************************
;;;-------------------------------------------------
;;;area13 0x2000000 - 0x2FFFFFF(16MB)
;;;area14 0x3000000 - 0x3FFFFFF(16MB)
;;;-------------------------------------------------
;///////////////////////////////////////////
;;; SDRAM area configuration register ... (note 1)
xld.w %r0,0x39FFC0 ;
xld.w %r1,0x88 ; set area13 to SDRAM area, #SDCE0(#CE13) available
ld.b [%r0],%r1 ; (16MB area available)
;///////////////////////////////////////////
;;; SDRAM control register
;;; xld.w %r0,0x39FFC1 ;
;;; xld.w %r1,0xff ; SDRAM self-refresh -> disable, initial sequence ->PRE REF MRS
;;; ld.b %r0],%r1 ; Little endian
;///////////////////////////////////////////
;;; SDRAM address configuration register ... (note 2)
xld.w %r0,0x39FFC2 ;
xld.w %r1,0x26 ; col 512 / row 4K / bank 4 -> 128Mb[16MB] available
ld.b [%r0],%r1 ;
;///////////////////////////////////////////
;;; SDRAM mode set-up register
xld.w %r0,0x39FFC3 ;
xld.w %r1,0x40 ; 2 CAS Latency ,burst length = 1
ld.b [%r0],%r1 ;
;///////////////////////////////////////////
;;; SDRAM timing set-up regi ster 1
xld.w %r0,0x39FFC4 ;
xld.w %r1,0x4A ; Tras=2,Trp=1,Trc=2 ... Recommended setting to operate with
ld.b [%r0],%r1 ; 2 5 MHz clock in x1 speed mode
;///////////////////////////////////////////
;;; SDRAM timing set-up regi ster 2
xld.w %r0,0x39FFC5 ;
xld.w %r1,0x48 ; Trcd=1,Trsc=2,Trrd=1
ld.b [%r0],%r1 ;
;///////////////////////////////////////////
;;; SDRAM auto refresh count low-order register
;;; xld.w %r0,0x39FFC6 ;
;;; xld.w %r1,0xff ;
;;; ld.b [%r0],%r1 ;
;///////////////////////////////////////////
VI SDRAM CONTROL LER BLOC K: S DRAM INTERF ACE
B-VI-2-34 EPSON S1C33L03 FUNCTION PART
;;; SDRAM auto refresh count high-order register
xld.w %r0,0x39FFC7 ;
xld.w %r1,0x00 ;
ld.b [%r0],%r1 ;
;///////////////////////////////////////////
;;; SDRAM self refresh count register
;;; xld.w %r0,0x39FFC8 ;
;;; xld.w %r1,0x0f ;
;;; ld.b [%r0],%r1 ;
;///////////////////////////////////////////
;;; SDRAM advanced control register
xld.w %r0,0x39FFC9 ;
xld.w %r1,0x20 ; data width -> 16bit, bank interleave -> on
ld.b [%r0],%r1 ;
;;;*****************************************************************
;;;***************** SDRAM controller power up *********************
;;;*****************************************************************
xld.w %r0,0x39FFC1 ; SDRAM control register
xld.w %r1,0x39FFCA ; SDRAM status register
xld.w %r2,0x0
xld.w %r3,0x10
;;; enable SDRAM signal
bset [%r0],0x7 ; set SDRENA[D7/0x39FFC1]
SDRAM_SIGNAL_EN:
add %r2,0x1 ; SDRAM signal enable waiting loop
cmp %r2,%r3
jrne SDRAM_SIGNAL_EN
;;; SDRAM power up
bset [%r0],0x6 ; set SDRINI[D6/0x39FFC1]
POWER_UP:
btst [%r1],0x7 ; SDRAM power-up waiting loop
jrne POWER_UP
;;;----------------- ------- end of SDRAM access conf iguration ------------ ---------------
ret
The SDRAM can be accessed after executing the above program.
Exam ple of initialization routine for 4M words × 16 bit s × 4 banks (32MB) of SD RAM
When using a 32MB SDRAM, modify two parts of the above program example indicated with (note 1) and (note
2) as follows:
(note 1 )
;///////////////////////////////////////////
;;; SDRAM area configuration register
xld.w %r0,0x39FFC0 ;
xld.w %r1,0xc8 ; set area13&14 to SDRAM area, #SDCE0(#CE13) available
ld.b [%r0],%r1 ; (32MB area available)
;///////////////////////////////////////////
(note 2 )
;///////////////////////////////////////////
;;; SDRAM address configuration register
xld.w %r0,0x39FFC2 ;
xld.w %r1,0x2a ; col 512 / row 8K / bank 4 -> 256Mb[32MB] available
ld.b [%r0],%r1 ;
;///////////////////////////////////////////
S1C33L03 FUNCTION PART
VII LCD CONTROLLER BLOCK
VII LCD CONTROLLER BLOC K: INTROD UCTION
S1C33L03 FUNCTION PART EPSON B-VII-1-1
A-1
B-VII
Intro
VII-1 INTRODUCTION
The LCD Controlle r Block provides LCD con tr ol signals for a 4- or 8-bit color/monochrome LCD panel.
CORE_PAD
Pads
C33_SBUS
C33 Core Block
C33 LCD Controller Block
Pads
PERI_PAD
Pads
C33_PERI
(Prescaler, 8-bit timer, 16-bit timer,
Clock timer, Serial interface, Ports)
C33 Peripheral BlockC33 Analog Block
C33_CORE
(CPU, BCU, ITC, CLG, DBG)
C33_ADC
(A/D converter)
C33 Internal Memory Block
Internal RAM
(Area 0)
Internal ROM
(Area 10)
C33 DMA Block
C33_DMA
(IDMA, HSDMA)
C33_SDRAMC
(SDRAM interface)
C33_LCDC
(LCD panel interface)
C33 SDRAM Controller Block
Figur e 1. 1 LCD Controller Bl ock
Note: In te rn al RO M is not prov ided in the S 1C33L03 .
VII LCD CONTROLLER BLOC K: INTROD UCTION
B-VII-1-2 EPSON S1C33L03 FUNCTION PART
TH IS PAGE IS BLANK.
VII LCD CONTROLLER BLOC K: LCD CONTROLLER
S1C33L03 FUNCTION PART EPSON B-VII-2-1
A-1
B-VII
LCDC
VII-2 LCD CONTROLLER
This section describes the functions and control procedures of the LCD con tr oller. For details on setting the
external display memory bus conditions and parameters, refer to Section II-4, "BCU (Bus Control Unit)", and
Section VI-2, "SDRAM Interface".
Overview
Features
The features of t he LC D con troll er (LCDC) are descri bed below .
S1C33 core CPU interface
• The control registers are mapped into the area-6 addresses 0x39FFE0 to 0x39FFFF (an internal #WAIT signal
is used).
• A dedicated DMA controller is built-in for the transferal of display data.
Comp atible d isplay typ es
• 4- or 8-bit monochrome LCD panel
• 4- or 8-bit color LCD panel
• Single-drive passive display, single panel
• Typical resolutions
640 × 480 (1-bpp mode ) * bpp = bits per pixel
640 × 240 (2-bpp mode )
320 × 240 (4-bpp mode )
240 × 160 (8-bpp mode )
Display mod es
• Portrait display (display screen rotated 90 degrees) is supported in the hardware.
• Due to frame rate modulation, grayscale display is possible in up to 16 shades of gray when a monochrome
passive LCD panel is used.
1-bpp mode: Two-shade display using a 2 × 4-bit look-up table
2-bpp mode: Four-shade display using a 4 × 4-bit look-up table
4-bpp mode: 16-shade display using a 16 × 4-bit look-up table
• Of 4,096 colors, a maximum of 256 colors can be simultaneously displayed on a color passive LCD panel.
1-bpp mode: Two-color display using three 2 × 4-bit look-up tables
2-bpp mode: Four-color display using three 4 × 4-bit look-up tables
4-bpp mode: 16-color dis play using three 16 × 4-bit look-up tables
8-bpp mode: 256-color displ ay us ing a 20 × 4-bit look-up table
• Two images can be simultaneously displayed on split screens of t h e LC D pan el (landscape display mode ).
• Virtual display (Images larger than the actual panel size can be displayed by panning or scrolling the screen.)
Display frame bu ffer
• A maximum of 256K by tes in mem ory conne cted to areas 7/8 or areas 13/14 can be used as a display frame
buffer.
• SDRAM is also supported by the 16 × 16-bit FIFO.
Clock
• The PCLK (pixel clock) and MCLK (memory clock) for the LCD controller can be selected from among four
clock frequencies derived from the BCU clock by dividing the BCU clock by 1, 2, 3, or 4.
• PCLK and MCLK frequencies: Maximum of 25 MHz
VII LCD CONTROLLER BLOC K: LCD CONTROL LER
B-VII-2-2 EPSON S1C33L03 FUNCTION PART
Power save
• DOZE mode suitable for Epson’s self-refresh-type LCD panels
• The status of the LCD controller can be checked using the power-save status bit.
Other
• Inverse display un der software cont ro l
• Software power-save mode
• LCD-panel power-down sequence supported
• LCD power-supply control
VII LCD CONTROLLER BLOC K: LCD CONTROLLER
S1C33L03 FUNCTION PART EPSON B-VII-2-3
A-1
B-VII
LCDC
Block Diagram
#BUSREQ
#BUSACK
#BUSGET
#CE7/13(8/14)
Address[23:0]
Data[15:0]
#CE6
FIFO Display
pipeline
Sequence
controller
DMA
interface
Bus
interface
Control
registers
Look-up
table
Frame rate
modulation LCD
interface
FPDAT[7:0]
FPFRAME
FPLINE
FPSHIFT
DRDY
LCDPWR
To SDRAM Controller
User logic signals
Figur e 2.1 Block Diagram of the LCD Controller
Bus interface
The LCD c ontroller is mapped into area 6, along with the SDRAM controller. Area 6 is internally accessed
for read/write to the control registers.
DMA interface
The display data is taken in from t he display frame buffer by means of a DMA transfer.
Address generator
This generates the memory addresses for the display data to be taken in by means of a DMA transfer.
FIFO
This is a 16 × 16-bit FIFO used to write data into the display frame buffer and look-up table.
Look-up table
This con sists of three 16 × 4-bit palettes (red, green, and blue).
During grayscale display mode, the grayscale data to be used is set in the green palette with 16 gray levels.
During color display mode, the red, green, and blue palettes are used, and the color data to be used is set from
among 4,096 col ors.
Sequence controller
The hor izontal and vertical display timing is controlled in accordance with the register settings.
LCD-panel interface
Dis play on the LCD panel is controlled through frame rate modulation, output-data pattern generation, and
the like.
VII LCD CONTROLLER BLOC K: LCD CONTROL LER
B-VII-2-4 EPSON S1C33L03 FUNCTION PART
I/O Pins of the LCD Controller
Table 2.1 lists the input/output pins of the LCD controller. Table 2.2 shows the pin configurations classified by
type of LC D panel.
Table 2.1 I/O Pins of the LCD Controller
Pin name I/O Description
FPDAT[7:4] O 4-bit LCD-panel data bus
8-bit LCD-panel data bus, four high-order bits
FPDAT[3:0]
GPO[6:3] O8-bit LCD-panel data bus, four low-order bits
General-purpose output when a 4-bit LCD panel is used
FPFRAME O Frame-pulse output
FPLINE O Line-pulse output
FPSHIFT O Shift-clock output
DRDY O LCD backpl ane bias (MOD)
Shift clock 2 (FPSHIFT2)
See Table 2.2.
LCDPWR O LCD power-supply control output (active high)
GPIO0
P34
#BUSREQ
#CE6
I/O GPIO0 See "Control of GPIO pins".
I/O port
Bus-release-request input
Area-6 chip enable
GPIO1
P35
#BUSACK
I/O GPIO1 See "Control of GPIO pins".
I/O port
Acknowledge output for bus release request
GPIO2
P31
#BUSGET
#GARD
I/O GPIO2 See "Control of GPIO pins".
I/O port
Bus-status-monitor signal output for bus release request
GA-area read signal output
Table 2.2 Pin Configurations by Type of LCD Panel
Monochrome passive panel Color passive panel
Pin name 4 bits 8 bits 4 bits 8-bit format 1 8-bit format 2
FPFRAME FPFRAME
FPLINE FPLINE
DRDY MOD MOD MOD FPSHIFT2 MOD
FPDAT7 D3 D7 D3 D7 D7
FPDAT6 D2 D6 D2 D6 D6
FPDAT5 D1 D5 D1 D5 D5
FPDAT4 D0 D4 D0 D4 D4
FPDAT3 GPO6 D3 GPO6 D3 D3
FPDAT2 GPO5 D2 GPO5 D2 D2
FPDAT1 GPO4 D1 GPO4 D1 D1
FPDAT0 GPO3 D0 GPO3 D0 D0
FPDAT[7:0]
FPSHIFT
FPFRAME
FPLINE
DRDY
LCDPWR
S1C33
D[7:0]
FPSHIFT
FPFRAME
FPLINE
MOD
LCD panel
FPDAT[3:0]
FPSHIFT
FPFRAME
FPLINE
DRDY
LCDPWR
S1C33
D[3:0]
FPSHIFT
FPFRAME
FPLINE
MOD
LCD panel
8-bit passive LCD panel 4-bit passive LCD panel
Figur e 2.2 Typical LCD-Panel Connections
VII LCD CONTROLLER BLOC K: LCD CONTROLLER
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LCDC
System S ett ing s
Setting the BCU
The con trol registers of the LCD controller are mapped into area-6 addresses 0x39FFE0 to 0x39FFFF. Therefore,
in order for the control registers to be accessed, the BCU must be set up in accordance with the procedure
described below.
1. A6IO (D9)/access control register (0x48132) = "1"
This sets area 6 so that the internal device will be accessed.
2. A6WT[2:0] ( D [A: 8])/are as 6–4 setup reg ister (0x48 1 2A) = "000"
This sets area 6 so that it can be accessed with no wait states.
3. SWAITE (D0)/bus control register (0x4812E) = "1"
This enables the #WAIT signal. This setting is necessary when SDRAM is used.
4. A6EC (D1)/ac cess control register ( 0x48132) = LC DCEC ( D 0)/LCDC system control r egist er (0x39FFFD)
Make sure the endian formats on the area 6 and LCDC (and SDRAMC) sides match when data is read. In
either register, setting the bit to "0" selects little endian (default), and setting the bit to "1" selects big endian.
Display Memory
The LCD controll er uses as display memor y a necessary am ount of me m ory (maxim um of 256K bytes ), beginning
with the start address of area 7 or 8 (or area 13 or 14 if CEFUNC[1:0] (D[A:9]/0x48130) = "01"). Therefore,
SD RAM or SR AM m ust be included for use as the display memory. The memory configurations and bus settings
made using the control registers of the LCD controller are described below.
Selecti ng the area
Use the VRAMAR ( D7)/LCD C system control register (0x39FFFD) to select the area to be used as the
display me m ory.
VRAMAR = " 1" : Area 8 (CEFUNC = "00" ) or area 14 (CEFUNC = "01" )
VRAMAR = " 0" : Area 7 (CEFUNC = "00" ) or area 13 (CEFUNC = "01" ) (default)
SR AM settings
When using SRAM as the display memory, set the interface method for access from the LCD controller
(A0/BSL) and the number of wait cycles to be inserted (0–7). Use the LCDCST (D1)/LCDC system control
register (0x39FFFD) to select the interface method.
LCDCST = "1": BSL method
LCDCST = "0": A0 method (default)
This bit must be set to the same value as in the SBUSST (D3)/bus control register (0x4812E) for the BCU.
Use the VRAMWT[ 2:0] (D[6:4])/LCDC system control register (0x39FFFD) to select the number of wait
cycles. The value set in these three bits (0–7) is the number of wait cycles inserted. When the same SRAM is
accessed from the CPU, the wait cycles set on the BCU side become effective and the VRAMWT value is
ignored.
The LCD c ontroller checks the BCU- and SDRAM-controller settings to determine whether SRAM is used.
When th e SDRAM controller is set to become effective, the above two register settings are ignored.
Settings for prioritized use of the bus
The LCD c ontroller reads display dat a from the display memor y via the system bus. Therefore, if the bus is
occupied by an external device, the LCD controller cannot update the display. To prevent this problem, the
LCD controller can disable DM A requ ests (# D MAR E Qx ) or bus re lea se requ ests (# B US R EQ) from outs id e
the chip while it remains enabled (LCDCEN (D5)/LCDC mode register 2 = "1").
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Use the EDMAEN (D3) /LCD C syste m control register (0x39FFFD) to mask the #DMAREQx signals.
ED M AEN = " 1": External DMA reques ts enab led
ED M AEN = "0": Exter nal DMA re qu es ts d isable d (d efault)
Use t he BREQEN (D2)/LCDC system con trol register (0x39 FFFD) to mask the #B USREQ sig nals.
BREQEN = "1": External bus re lea se requ ests enab led
BREQEN = "0": External bus release requ ests d isable d (d efau lt)
Other settings, such as memory specification-related settings, are made using the registers of the BCU and
SD RAM controllers. For details, refer to the description of the respective controllers.
LCD Controlle r Setting Procedure
Procedure to acc ess th e LCDC registers (when using #WAI T signa l )
1. A6IO (D9)/access control register (0x481 32 ) = "1"
This sets area 6 so that the internal device will be accessed.
2. A6WT[ 2:0 ] (D[ A :8])/area s 6–4 setup r egister (0x4812A) = "000"
This sets area 6 so that it can be accessed with no wait states.
3. SWAITE (D0)/bus control register (0x4812E) = "1"
This enables the #WAIT signal.
4. The LCDC r egist ers can b e accessed .
Procedure to enable the LCD panel
1. SEMAS (D2)/bus control register (0x4812E) = "1"
This enables an external bus master.
2. LC DE N (D5)/LCD C m ode regist er 2 (0x39FFE3) = "1"
This enables the LCD controller.
3. CFP3[5:4] (D[5:4])/P3 function select register (0x402DC) = "11"
This sets the P35 pin as the #BUSACK output and the P34 pin as the #BUSREQ input.
4. Initializing the LCDC registers
Setup the LCDC register as necessary except for the look-up table registers (0x39FFF5, 0x39FFF7) as
necessary.
5. LPSAVE[1:0] (D[1:0])/LCDC mode register 2 (0x39FFE3) = "11"
This sets the LCD controller in power save mode to normal operation mode. Wait until the LCD
controller completes the power-up sequence.
6. Setting the look-up table
Setup the look-up table by writing data to the look-up table address register (0x39FFF5) and look-up table
data register (0x39FFF7).
Setting the number of wait states for accessi ng th e LCDC registers (a rea 6) when
#WAIT signal is dis a ble d
• The LCDC r egist ers except for the look-up table data register (0x39FFF7) should be accessed with 4 wait
st ate s in se rte d.
• When writ ing data to the look-up table data register (0x39FFF7), red and green data should be written
with 4 wait states inserted (1st and 2nd writes in a sequence), and blue data should be written with 7 wait
states inserted (last write in a sequence).
Use A6WT[2:0] (D[A: 8])/areas 6–4 s etup reg ister (0x48 12A) to set the number of wa it states to be inserted
when area 6 is accessed.
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Clock
The LCD c ontrol ler us es the BCU clock as the source clock for its pixel clock PCLK and display memory clock
MCLK. The maximum clock frequency that can be supplied to the LCD controller is 25 MHz. The BCU clock
divide ratios can be set using the LCLKSEL[2:0] (D[2:0])/FIFO control register (0x39FFF4), as shown in Table
2.3 below.
LCLKSEL[2:0]
#X2SPD pin
To CPU
CPU_CLK BCU_CLK
Bus clock
LCDC clock (PCLK, MCLK)
BCUCLG
1/1 or 1/2
1/1
1/2
1/3
1/4
Figure 2.3 LCDC Clocks
Table 2.3 Selection of LCDC Clocks
LCLKSEL2 LCLKSEL1 LCLKSEL0 LCDC clock
000Turned of f
001Turned of f
010Turned of f
011Reserved (not allowed)
100BCU_CLK
101BCU_CLK/2
110BCU_CLK/3
111BCU_CLK/4
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Setting the LCD Pan el
Types of Panels
The LCD c ontroller supports the following types of single-LCD panels.
• 4- or 8-bit mo noch rome passive LCD pan el
• 4- or 8-bit color passive LCD panel
Dual panels are not supported.
The type of LC D pan el used mu st be set in the LCD controller in advance, using the control bits described below.
Selecting between color and monochrome
Use LDCOLOR (D5)/LCDC mode reg ister 0 (0x39FFE1) to select the type of LCD panel, either color or
monochrome.
LD COLOR = "1" : Colo r panel s el ected
LD COLOR = "0": Monochro me panel selected (default)
Selecti ng the data width
Use LDDW[1: 0] (D[1:0])/LCDC mode register 0 (0x39FFE1) to select the data width and format.
Table 2.4 Selection of the LCD Panel
LDCOLOR LDDW1 LDDW0 LCD panel
0Mono Single 4-bit passive LCD01Mono Single 8-bit passive LCD
0Reserved
0
11Reserved
0Color Single 4-bit passive LCD01Color Single 8-bit passive LCD format 1
0Reserved
1
11Color Single 8-bit passive LCD format 2
Resolution
Set the resolution of the LCD panel in accordance with the procedure specified below.
Horizo ntal resoluti on
Set the value shown below in the LDHSIZE[5:0] (D[5:0])/horizontal panel size register (0x39FFE4).
Horizont al resolution (number of pix els)
LDHSIZE[5:0] = —————————————————— - 1
16
For exam ple, if the LCD panel has a horizontal resolution of 320 dots, set 19 (= 0x13 ) in LDH SIZE .
Note:Do not set a value less than 1 in LDHSIZE.
Vertical resolution
Set the value shown below in LDVSIZE[9:0] (D[9:0])/vertical panel size register (0x39FFE6, 0x39FFE5).
LDVSIZE[9:0] = Vertical resolution (number of lines) - 1
For exam ple, if the LCD panel has a vertic al resolution of 240 lines, set 239 (= 0xEF ) in LD V SIZE .
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Display Modes
The number of gray levels in grayscale display and the num ber of colors in color display are determined by the
num ber of bits repres enting each pixel (bpp = bits per pixel). Write this bpp va lue to BPP[1:0] (D[7:6])/LCDC
mode register 1 ( 0x39 FFE2) in order to set the displa y m ode (numbe r of gray levels/col ors displayed).
Table 2.5 Specification of Display Modes
LDCOLOR BPP1 BPP0 Di splay mode
02 gray levels 1 bit -pe r-p ix el014 gray levels 2 bit-per-pixel
016 gray levels 4 bit-per-pixel
0
11Reserved
02 colors 1 bi t- pe r-p ix el014 colors 2 bi t-pe r-p ix el
016 colors 4 bit -pe r-p ix el
1
11256 colors 8 bit-per-pixel
(1) 1-bpp (2-gray-level/2-color) mode
One pixel is represented by 1 bi t, displayed in two gray levels or t wo colors.
For monochrome LC D pan els, 2-gray-l evel display can be obtained by a ssigning two gray levels from among
the 16 gray levels available, including black and white, to two entries in the green look-up table (described
later) (one each for bits = "0" and "1").
For color LCD panels, two colors from among the 4,096 colors available can be set in advance using two
entries for pixel data "0" and "1" in each of the red, green, and blue look-up tables.
Dat a for eight consecutive pixels is stored as one byte in the display memory.
A0 A1 A2 A3 A4 A5 A6 A7
A8 A9 A10 A11 A12 A13 A14 A15
P0 P1 P2 P3 P4 P5 P6 P7 P8
Display memory
Pn = (An)
LCD panel
Byte 0
Byte 1
(bit 7) (bit 0)
Figur e 2.4 Data Format in 1-bpp Mode
(2) 2-bpp (4-gray-level/4-color) mode
One pixel is represented by 2 bi ts, displayed in four gr ay levels or four colors.
For monochrome LC D pan els, 4-gray-level display can be obtained by a ssigning four gray levels from am ong
the 16 gray levels available, including black and white, to four entries in the green look-up table (one each for
bits = "00" to "11").
For color LCD panels, four colors from among the 4,096 colors available can be set in advance using four
entries for pixel data "00" to "11" in each of the red, green, and blue look-up tables.
Dat a for four consecutive pixels is stored as one byte in the display memory.
A0 B0 A1 B1 A2 B2 A3 B3
A4 B4 A5 B5 A6 B6 A7 B7
P0 P1 P2 P3 P4 P5 P6 P7
Pn = (An, Bn)
Byte 0
Byte 1
Display memory LCD panel
(bit 7) (bit 0)
Figur e 2.5 Data Format in 2-bpp Mode
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(3) 4 -b pp (16-gr ay -lev el/1 6-c ol o r) m o de
One pixel is represented by 4 bi ts, displayed in 16 gray levels or 16 colors.
For monochrome LC D pan els, 16-gray-level dis play can be obtained by a ssigning 16 gray levels, includi ng
black and white, to 16 entries in the green look-up table (one each for bits = "0000" to "1111").
For color LCD pan els, 16 colors from am ong the 4,096 colors available can be set in advance using 16 entries
for pixel data "0000" to "1111" in each of the red, green, and blue look-up tables.
Data for two consecutive pixels is stored as one byte in the display memory.
A0 B0 C0 D0 A1 B1 C1 D1
A2 B2 C2 D2 A3 B3 C3 D3
A4 B4 C4 D4 A5 B5 C5 D5 P0 P1 P2 P3 P4 P5 P6 P7
Pn = (An, Bn, Cn, Dn)
Byte 0
Byte 1
Byte 2
Display memory LCD panel
(bit 7) (bit 0)
Figur e 2.6 Data Format in 4-bpp Mode
(4) 8 -b pp (256-c o lo r) m o de
One pixel is represented by 8 bi ts, displayed in 256 colors. This mode is not available f or grayscale display.
In this mode, 256 discrete combinations are configured using eight entries in each of the red and green look-
up tables, and four entries in the blue look-up table.
Dat a for one pixel is stored as one byte in the display memory.
R0
2
R0
1
R0
0
G0
2
G0
1
G0
0
B0
1
B0
0
R1
2
R1
1
R1
0
G1
2
G1
1
G1
0
B1
1
B1
0
R2
2
R2 R2 G2
2
G2
1
G2
0
B2
1
B2
0
P0 P1 P2 P3 P4 P5 P6 P7
Pn = (Rn
2
, Rn
1
, Rn
0
, Gn
2
, Gn
1
, Gn
0
, Bn
1
, Bn
0
)
Byte 0
Byte 1
Byte 2
Display memory LCD panel
(bit 7) (bit 0)
Figur e 2.7 Data Format in 8-bpp Mode
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Look-up Tables
The LCD c ontroller contains a look-up table consisting of 16 4-bit entries, one for each of the RGB color elements
(red, green, and blue).
4-bit luminance data
Pixel data
The pixel data
selects an LUT entry.
4-bit display data (R)
Red look-up table
0
1
2
3
:
:
14
15
4-bit luminance data
Pixel data 4-bit display data (G or Gray)
Green look-up table
0
1
2
3
:
:
14
15
4-bit luminance data
Pixel data 4-bit display data (B)
Blue look-up table
0
1
2
3
:
:
14
15
Figur e 2.8 Configuration of the Look-up Tables
The pixel data in the display memory is used as an index to the look-up tables, so that luminance data is generated
based on the values in the entries indicated by the pixel data, before being output to the LCD panel.
The LCD controller can control re ve rs al of the display. Th is co ntr ol is exerc ised on the outpu t of the look -u p
tables.
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Grayscale-mode look-up tables
In grayscale mode, the LCD controller uses only the green look-up table. For display in grayscale mode,
select the data to be written to the look-up table from the 16 gray levels represented by 4 bits. The data 0x0,
0x1, 0x8, and 0xF represen t black, 93.75% gray, 50% gray, and white, respectively. The differences in
confi g ura t io n b et w ee n d isplay modes are sho w n below.
(1) 1-bpp (2-gray-level) mode
Use the first two entries of the green look-up table. Select two pieces of data from the 16 gray levels, and
write them to the respective entries. The data in entry 0 is output for pixel data "0", and the data in entry 1 is
outpu t for pixel data "1". For mo noch rome display, write 0x0 to entry 0 and 0xF to entry 1 before using the
LC D panel .
1-bit pixel data "0"
"1" 4-bit display data
Green look-up tableIndex
Unused
0
1
2
:
15
4-bit grayscale data for pixel data "0"
4-bit grayscale data for pixel data "1"
Figur e 2.9 Look-up Table in 1-bpp (2-Gray-Level) Mode
Table 2.6 shows an example of the basic data setting.
Table 2.6 Example of Look-up-Table Settings in 1-bpp (2-Gray-Level) Mode
Index R look-up table G look-up table B look-up table
0000
100xF0
2–15 0 0 0
(2) 2-bpp (4-gray-level) mode
Use the first four entries of the green look-up table. Select four pieces of data from the 16 gray levels, and
write them to the respective entries. The data in entry 0 is output for pixel data "00", and the data in entry 3 is
outpu t for pi xel data "11".
4-bit grayscale data for pixel data "00"
4-bit grayscale data for pixel data "01"
4-bit grayscale data for pixel data "10"
4-bit grayscale data for pixel data "11"
2-bit pixel data
"00"
"01"
"10"
"11"
4-bit display data
Green look-up tableIndex
Unused
0
1
2
3
4
:
15
Figur e 2.10 Look-up Table in 2-bpp (4-Gray-Level) Mode
Table 2.7 shows an example of the basic data setting.
Table 2.7 Example of Look-up-Table Settings in 2-bpp (4-Gray-Level) Mode
Index R look-up table G look-up table B look-up table
0000
1050
200xA0
300xF0
4–15 0 0 0
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(3) 4-bpp (16-gray-level) mode
Use a ll entries of the green look-up table. All 16 gray levels can be assigned to the look-up table. The data in
entry 0 is output for pixel data "0x0", and the data in entry 15 is output for pixel data "0xF".
4-bit grayscale data for pixel data 0x0
4-bit grayscale data for pixel data 0x1
4-bit grayscale data for pixel data 0x2
4-bit grayscale data for pixel data 0xF
4-bit grayscale data for pixel data 0xE
4-bit grayscale data for pixel data 0x3
4-bit pixel data
0x0
0x1
0x2
0x3
:
0xE
0xF
4-bit display data
Green look-up tableIndex
0
1
2
3
14
15
::
Figur e 2.11 Look-up Table in 4-bpp (16-Gray-Level) Mode
Table 2.8 shows an example of the basic data setting.
Table 2.8 Example of Look-up-Table Settings in 4-bpp (16-Gray-Level) Mode
Index R look-up table G look-up table B look-up table
0000
1010
2020
3030
4040
5050
6060
7070
8080
9090
10 0 0xA 0
11 0 0xB 0
12 0 0xC 0
13 0 0xD 0
14 0 0xE 0
15 0 0xF 0
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Color-mode look-up tables
In color mode, the LCD controller uses the red (R), green (G), and blue (B) look-up tables. Each color
element is represented by 4-bit data. RGB = 00 0 is black, RG B = F00 is red, RGB = 080 is 50% luminance
green, RGB = F0F is magent a, RGB = FFF is white, and so on. In this way, colors are determined by the
proportions of the three color elements. If the luminance of each color element is represented by 4 bits, then
we ob tain 16 × 16 × 16 = 4,096 colors. Of these, select as many pieces of color data as can be used for the
available display mode (2, 4, 16, or 256 colors), and write them to the valid entries of the look-up tables
before using the LCD pan el.
In personal-computer applications, the luminance of each color element is generally represented by 8 bits
(0x00 to 0xFF). To set up the LCD panel by referring to those colors, write the 4 high-order bits of that data
to the look-up tables.
The differences in configurations between display m ode s are show n below.
(1) 1-bpp (2-color) mode
Use the first two entries of each look-up table. Select 2-color data from among the 4,096 colors, and write it
to the respective entries. The RGB data in entry 0 is output for pixel data "0", and the RGB data in entry 1 is
outpu t for pixel data "1". For mo noch rome display, write 0x0 to entry 0 and 0xF to entry 1 in each of the red,
green, and blue look-up tables before using the LCD panel.
4-bit R display data
Red look-up tableIndex
Unused
0
1
2
:
15
4-bit R data for pixel data "0"
4-bit R data for pixel data "1"
4-bit G display data
Green look-up tableIndex
Unused
0
1
2
:
15
4-bit G data for pixel data "0"
4-bit G data for pixel data "1"
4-bit B display data
Blue look-up tableIndex
Unused
0
1
2
:
15
4-bit B data for pixel data "0"
4-bit B data for pixel data "1"
1-bit pixel data "0"
"1"
Figur e 2.12 Look-up Table in 1-bpp (2-Color) Mode
Table 2.9 shows an example of the basic data setting.
Table 2.9 Example of Look-up-Table Settings in 1-bpp (2-Color) Mode
Index R look-up table G look-up table B look-up table
0000
10xF0xF0xF
2–15 0 0 0
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(2) 2-bpp (4-color) mode
Use the first four entries of each look-up table. Select 4-color data from among the 4,096 colors, and write it
to the respective entries. The RGB data in entry 0 is output for pixel data "00", and the RGB data in entry 3 is
outpu t for pi xel data "11".
4-bit R data for pixel data "00"
4-bit R data for pixel data "01"
4-bit R data for pixel data "10"
4-bit R data for pixel data "11"
2-bit pixel data
"00"
"01"
"10"
"11"
4-bit R display data
Red look-up tableIndex
Unused
0
1
2
3
4
:
15
4-bit G data for pixel data "00"
4-bit G data for pixel data "01"
4-bit G data for pixel data "10"
4-bit G data for pixel data "11"
4-bit G display data
Green look-up tableIndex
Unused
0
1
2
3
4
:
15
4-bit B data for pixel data "00"
4-bit B data for pixel data "01"
4-bit B data for pixel data "10"
4-bit B data for pixel data "11"
4-bit B display data
Blue look-up tableIndex
Unused
0
1
2
3
4
:
15
Figur e 2.13 Look-up Table in 2-bpp (4-Color) Mode
Table 2.10 shows a n example of the basic data setting.
Table 2.10 Example of Look-up-Table Settings in 2-bpp (4-Color) Mode
Index R look-up table G look-up table B look-up table
0000
1777
20xA0xA0xA
30xF0xF0xF
4–15 0 0 0
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(3) 4-bpp (16-color) mode
Use a ll entries of each look-up table. Select 16-color data from among the 4,096 colors, and write it to the
respective entries. The RGB data in entry 0 is output for pixel data "0x0", and the RGB data in entry 15 is
outpu t for pi xel data "0xF".
4-bit R data for pixel data 0x0
4-bit R data for pixel data 0x1
4-bit R data for pixel data 0x2
4-bit R data for pixel data 0xF
4-bit R data for pixel data 0xE
4-bit R data for pixel data 0x3
4-bit pixel data
0x0
0x1
0x2
0x3
:
0xE
0xF
4-bit R display data
Red look-up tableIndex
0
1
2
3
14
15
::
4-bit G data for pixel data 0x0
4-bit G data for pixel data 0x1
4-bit G data for pixel data 0x2
4-bit G data for pixel data 0xF
4-bit G data for pixel data 0xE
4-bit G data for pixel data 0x3
4-bit G display data
Green look-up tableIndex
0
1
2
3
14
15
::
4-bit B data for pixel data 0x0
4-bit B data for pixel data 0x1
4-bit B data for pixel data 0x2
4-bit B data for pixel data 0xF
4-bit B data for pixel data 0xE
4-bit B data for pixel data 0x3
4-bit B display data
Blue look-up tableIndex
0
1
2
3
14
15
::
Figur e 2.14 Look-up Table in 4-bpp (16-Color) Mode
Table 2.11 shows a n example of the basic data setting.
Table 2.11 Example of Look-up-Table Settings in 4-bpp (16-Color) Mode (VGA 16-Color-Mode Compatible)
Index R look-up table G look-up table B look-up table
0000
1000xA
200xA0
300xA0xA
40xA0 0
50xA00xA
60xA0xA0
70xA0xA0xA
8000
9000xF
10 0 0xF 0
11 0 0xF 0xF
12 0xF 0 0
13 0xF 0 0xF
14 0xF 0xF 0
15 0xF 0xF 0xF
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B-VII
LCDC
(4) 8-bpp (256-color) mode
One pixel is represented by 8 bi ts, displayed in 256 colors. This mode is not available f or grayscale display.
In this mode, 256 discrete combinations are configured using eight entries in each of the red and green look-
up tables, and four entries in the blue look-up table. Bits 5–7 in one byte of pixel data are used as an index to
the red look-up table, while bits 2–4 and bits 0–1 are used as indices to the green and blue look-up tables,
respectively.
4-bit R data for R pixel data "000"
4-bit R data for R pixel data "001"
4-bit R data for R pixel data "010"
4-bit R data for R pixel data "111"
4-bit R data for R pixel data "100"4
74-bit R data for R pixel data "110"
4-bit R data for R pixel data "101"
4-bit R data for R pixel data "011"
3-bit
R pixel
data
"000"
"001"
"010"
"011"
"100"
"101"
"110"
"111"
4-bit R
display data
Red look-up tableIndex
0
1
2
3
5
6
4-bit G data for G pixel data "000"
4-bit G data for G pixel data "001"
4-bit G data for G pixel data "010"
4-bit G data for G pixel data "111"
4-bit G data for G pixel data "100"4
74-bit G data for G pixel data "110"
4-bit G data for G pixel data "101"
4-bit G data for G pixel data "011"
3-bit
G pixel
data
"000"
"001"
"010"
"011"
"100"
"101"
"110"
"111"
4-bit G
display data
Green look-up tableIndex
0
1
2
3
5
6
4-bit B data for B pixel data "00"
4-bit B data for B pixel data "01"
4-bit B data for B pixel data "10"
4-bit B data for B pixel data "11"
2-bit
B pixel
data
"00"
"01"
"10"
"11"
4-bit B
display data
Blue look-up tableIndex
0
1
2
3
R2 R1 R0 G2 G1 G0 B1 B0
Pixel data
(bit 7) (bit 0)
Figur e 2.15 Look-up Table in 8-bpp (256-Color) Mode
Table 2.12 shows a n exam ple of the basic data set ting, using the displ ay c olors shown i n Table 2.13.
Table 2.12 Example of Look-up-Table Settings in 8-bpp (256-Color) Mode
Index R look-up table G look-up table B look-up table
0000
1335
2550xA
3770xF
4990
50xB0xB0
60xD0xD0
70xF0xF0
8–15 0 0 0
Table 2.13 Display Colors in the Above Setup Example
Pixel data Color Pixel data Color
000 000 00 Black 000 000 00 Black
000 000 10 Dark blue 000 000 11 Bright blue
000 100 00 Dark green 000 111 00 Bright green
000 100 10 Dark cyan 000 111 11 Bright cyan
100 000 00 Dark red 111 000 00 Bright red
100 000 10 Dark magenta 111 000 11 Bright magenta
100 100 00 Dark yellow 111 111 00 Bright yellow
100 100 10 Gray 111 111 11 White
VII LCD CONTROLLER BLOC K: LCD CONTROL LER
B-VII-2-18 EPSON S1C33L03 FUNCTION PART
Setting data in the look- up tables
To set data in the look-up tables, use the look-up-table address register (0x39FFF5) and the look-up-table data
register (0x39FFF7). Follow the procedure specified below in programming.
1. To the look-up-table address register (0x39FFF5), write the index (address) at which setting is to be
started. When pro gram m ing new ly, write 0x0. When reading or writing to thi s register, be sure to access
it bytewise.
Writing any value to this register selects the specified index in the red look-up table. When 0x0 is written,
for example, the beginning entry R[0] of the red look-up table is selected.
2. Wr ite the 4-bit data in the entry R[0] specified in step 1 to LUTDT[3:0] (D[7:4])/look-up-table data
register (0x39FFF7). The data corresponds to the 4 high-order bits of t h e register. Wr ite 0 to t he 4 lo w-
order bits of the register. For grayscale mode , write 0x0 to this regist er.
Writing any value to this register moves the internal pointer to the next entry, G[0]. The pointer moves in
the following order each time data is written:
R[0] → G[0] → B[0] → R[1] → G[1] → B[1]
When the index (address) changes, the look-up-table address register (0x39FFF5) is automatically
incremented.
3. Wr ite all necessary dat a in order of RGB.
Notes:•Upon completion of writin g all RGB data (4 bits × 3) in the same index to the look-up-table data
register (0 x39FFF 7), the data is actually set in t he look-up table . Therefore, even when only the
green look-up table is used for displ ay in grayscal e mode, al ways be su re to write 0x0 to the red
and blue look-up tables.
•If the look-up-table address register (0x39FFF5) is se t newly again during wr iting to any look-up
table, the red l o ok- u p table is al w ay s sel e cted.
VII LCD CONTROLLER BLOC K: LCD CONTROLLER
S1C33L03 FUNCTION PART EPSON B-VII-2-19
A-1
B-VII
LCDC
Frame Rates
The fram e rate is calculated from the LCD panel’s resolution, non-display period, and pixel clock frequency, as
shown below.
fPCLK
Frame rate = ————————————————
(HDP + HNDP) × (VDP + VNDP)
fPCLK: PCLK frequency (Hz)
This is the input clock frequency for the LCD controller derived by dividing the BCU clock. The BCU-clock
division rat io can be set to 1/1, 1/2, 1/ 3, or 1/4 using the LCLKSEL[2:0] (D[2:0])/FIFO control register
(0x39FFF4). The LCD controller supports a PCLK clock of up to 25 MHz.
HDP: Horizontal display period
This is the LCD panel’s horizontal resolution (in pixels). From the set value of LDHSIZE[5:0]
(D[5:0])/horizontal panel size register (0x39FFE4), the horizontal display period is calculated as follows:
Horizontal disp lay period = ( LD HSIZE[5:0] + 1) × 16 (Ts) where Ts = PCLK clock cycle
HN DP: Horizontal non- displ ay perio d
This is a non-display period before the LCD panel starts displaying the next line after it has fin ished
displaying all pixels in one line. Set a value in 8 pixel units in the HNDP[4:0] (D[4:0])/horizontal non-display
period register (0x39FFE7).
Horizontal non-d is pl ay period = (HNDP[4:0] + 4) × 8 (Ts)
The value HDP described above plus H NDP comp rises the number of PCLK clock cycles per one-line period
(FPLINE pulse period).
VDP: Vertical display period
This is the LCD panel’s vertical resolution (number of display lines). From the set value of the
LDVSIZE[9:0] (D[9:0])/vertical panel size register (0x39FFE6, 0x39FFE5), the vertical display period is
calculated as follows:
Vertical di splay period = LDVSIZE[9:0] + 1 (lines)
VNDP: Vertical non-display period
This is a non-d isplay period before the LCD pan el starts displaying the next frame after it has fin ish ed
displaying all display lin es in one frame. Set this period based on the number of lines in the VNDP[5:0]
(D[5:0])/vertical non-display period register (0x39FFEA).
Vertical no n-d isplay pe riod = VN D P[5: 0] (lines)
From the above parameters, we obtain the number of PCLK clock cycles required for the display of one frame, as
determined by (HDP + HNDP) × (VDP + VNDP). The frame rate is calculated by dividing the PCLK clock
frequency by this value.
VII LCD CONTROLLER BLOC K: LCD CONTROL LER
B-VII-2-20 EPSON S1C33L03 FUNCTION PART
Other Settings
FPSHIFT mask
When a color passive LCD panel is used, FPSHIFT (shift clock) can be turned on or off during the non-
display period us ing FPSMASK (D 2)/LCDC mode reg ister 0 (0x 39FFE 1).
FPSM ASK = " 1": Tu rned off
FPSM ASK = "0" : Turned on (default)
FPSMASK can only be set when LDCOL OR (D5)/LCD C m ode register 0 (0x39FFE1) = "1" (color panel).
Otherwise, FPSMASK has no effect.
MOD rate
The period during w hich the MOD signal is switched can be set using the MODRATE[5:0] (D[5:0])/MOD
rate register (0x3 9F F EB ).
MODRATE = "0x0": MOD sign al switched at a period of the FPFRAME signal (default)
MODRATE = other tha n "0x 0": Switched at a period of MODRATE + 1 FPLINE pulses
Repeating of the FRM pattern
This setup item is provided for EL panels. Whether the frame-rate modulation pattern is to be repeated every
0x4000 0 frames (counted by the inter nal fram e counter) can be set using FRM R PT (D 2)/LCDC mode regist er
1 (0x39FFE2) .
FR M RPT = " 1": FRM pattern repeated
FR M RPT = "0": FRM pattern not re pe ated (d efau lt)
VII LCD CONTROLLER BLOC K: LCD CONTROLLER
S1C33L03 FUNCTION PART EPSON B-VII-2-21
A-1
B-VII
LCDC
Display Control
Controlling LCD Power Up/Down
The LCD c ontroller is activated to start up and generate LCD signals by setting LCDCEN (D5)/LCDC mode
register 2 (0x39FFE3) to "1". Setting LCDCEN to "0" causes the LCD controller to stop operating, with the LCD
signal output dropped low. For the LCD controller to start display correctly, the LCD-panel parameters and display
data must be set bef ore LCDCEN is set to "1".
If the power to the LCD panel is turned on or off while LCD signals are not being correctly output, the panel may
be damaged. Therefore, the power to the LCD panel must be turned on only after the LCD panel starts controlling
LC D signa ls. The signal used to control the power to the LCD panel for this purpose is LCDPWR. Once the output
pin for it is enabled, LCDPWR output is controlled in the hardware during the LCD power-up and power-down
sequences of the LCD controller. When LCD signals have no effect, the LCDPWR signal goes low; when LCD
signals become effective, the LCDPWR signal goes high. Controlling the power to the LCD panel using this signal
ensures that the LCD panel is powered up and p ow er ed d ow n sa fel y.
Control of t he LC DPWR pin by the LCD con tr oller is enabled by setting LPWREN (D4)/LCDC mode register 2
(0x39FFE3) to "1".
Following power-on, the LCD controller is set in such a way that LCDCEN = "0" and power-save mode is on.
Setting LCDCEN to "1" does not immediately cause the LCD panel to initiate a power-up sequence and start
displaying data. The LCD pan el is pl aced in pow er-save m ode , with all LCD signal output pins fixed l ow . The
LCDPWR signal is also fixed low, and the power to the LCD panel does not turn on.
To change the LCD controller from power-save mode back into normal mode, set LPSAVE[1:0] (D[1:0])/LCDC
mode register 2 ( 0x39FFE3) to "0b11". The LCD controller starts a power-up sequence from that point, and
outputs LCD signals while driving the LCDPWR signal high (to turn on the power to the LCD panel). This power-
up seq uenc e requires a one-frame period. Conv ersely, to change from normal mode to powe r-save mode, s et
LPSAVE to "0b00 ". The LCD controll er starts a power-down sequence from that point, and pulls the LCDPWR
signal low a one-frame period later (to turn off the power to the LCD panel) while driving the LCD signals low.
In power-save mode, furthermore, although the LCD control registers can be set, the look-up tables cannot be
accessed. Before setting the look-up tables following power-on, place the LCD controller in normal mode.
The pro cedure for initializing the LCD at power-on is summarized below.
1. Set the BCU, clock, and display memory area (refer to "System Settings").
2. Set the LC D-panel parameters and display mode (refer to "Setting the LCD Panel").
3. Write displa y data to the display me m ory.
4. Set the display start address (refer to "Setting the Display Start Address").
5. Enable contr ol of the LCDPWR signal (LPWREN = "1").
6. Enable the LCD controller (LCDCEN = "1").
7. Place the LCD controller in normal mode (LPSAVE = "0b11").
8. The LCD controller starts a power-up sequence and the power to the LCD panel turns on a one-frame period
later.
9. Set the look-up tables (refer to "Look-up Tables").
Thus, the above is the basic operation for starting up the display.
VII LCD CONTROLLER BLOC K: LCD CONTROL LER
B-VII-2-22 EPSON S1C33L03 FUNCTION PART
The following is the power-down procedure.
1. Place the LCD controller in power-save mode (LPSAVE = "0b00").
2. The LCD controller starts a power-down sequence and turns off the power to the LCD panel a one-frame period
later, then pulls LCD signals low.
3. Because the bus clock is tur ned off during HALT2 or SL EEP mode, t he one-frame period descri bed a bove mu st
elapse before the chip can be placed in standby mode.
The number of frames can be counted by r eading VNDPF (D7)/vertical non-display period regis ter
(0x39FFEA) repeatedly. VNDPF is set to "1" during the vertical non-display period (set to "0" during the
display period).
Depending on the powe r sup ply for the LCD panel, it may be necessary to sec ure mo re t han on e frame of po w er-on
time, otherwise electricity may not be fully discharged within a one-frame period following power-off. In such a
case, exclusive power-up/power-down sequences may be programmed. Control examples are shown below.
Exam ple of a power-up sequence
(for controlling the length of time before the LCD power turns on after LCD signals are asserted)
1. Set LPW R EN to "0". The LCDPWR signal is fixed low, with control by a power-up sequence disabled.
2. Release power-s ave mode (LPSAVE = "0b 11").
3. The LCD signal s go active a one-frame period after step 2.
4. Allow for a wait time until the power turns on. To set the wait time in terms of the number of frames, count the
occurrences of VNDPF = "1" (vertical non-display period).
5. Set LPWREN to "1" a specified length of time later. The LCDPWR pin goes high, causing the power to the
LC D panel to turn ON.
Exam ple of a power-down sequence
(for controlling the length of time before LCD signals are deasserted after the LCD power turns off)
1. Set LPWREN to "0". The LCDPWR pin goes low, and the power to the LCD panel turns off.
2. Allow for a wait time until LCD signals are deasserted. To set the wait time in terms of the number of frames,
count the occurrences of VNDPF = "1" (vertical non-display period).
3. Set power-save mode a specified length of time later (LPSAVE = "0b00").
4. LCD signals are deasserted a one-frame period after step 3.
Reading/Writing Display Data
The LCD c ontroller contains an exclusive DMA interface, allowing data to be taken in from the display memory by
means of DMA transfer. The di splay data read from the display memory is buffered in the internal 16 × 16-bit
FIFO, preventing the bus efficiency from decreasing. If the data in the FIFO decreases to (0xf - FIFOEO[3:0])
word s or less, the LCD controller outputs a DMA request to the CPU requesting that the data be read. Although
any value from 0 to 0xf can be written to FIFOEO[3:0] (D[6:3])/FIFO control register (0x39FFF4), we recommend
setting the value 8.
There are no timing limitations when data is written to the display memory by a user program using the above
DMA transfer. Data can be written asynchronously with the display.
Setting the Display Start Address
The LCD c ontroller is initially set in such a way that data is displayed beginning with the initial address of the
display me m ory (the area selected by the VRAMAR bit). Because the display memory address from which to start
display can be changed as desired using the screen 1 start a ddress regist er (0x39FFEC– 0x39 FFED, D 0/0x39F FF0),
it is possible to set a virtual screen for panning or scrolling, as will be described later. The start address set in the
screen 1 start address register corresponds to the upper left edge of the LCD panel.
The value that should actually be set in this register is an offset address from the beginning of the area in which the
display me m ory exists. When area 7 is used, for example, the start address of the display memory is 0x0, rather
than 0x400000. Be aware that the address set here is a halfword address (byte address for portrait mode; described
later).
VII LCD CONTROLLER BLOC K: LCD CONTROLLER
S1C33L03 FUNCTION PART EPSON B-VII-2-23
A-1
B-VII
LCDC
Split-Screen Display
The LCD c ontroller s uppor ts a sp lit-screen function, allowing different images to be displayed on two vertically
split screens on the LCD panel. To discriminate between these two screens, the upper half of the LCD panel is
referred to as "screen 1" and the lower half is referred to as "screen 2".
Screen 1 data
Screen 2 data
Screen 1 start address
Screen 2 start address
Display memory LCD panel
Screen 1
Screen 2
S1VSIZE
+ 1 (lines) LDVSIZE
+ 1 (lines)
(LDHSIZE + 1) × 16 (pixels)
Figur e 2.16 Split-Screen Display
A reg is ter similar to the screen 1 start address register described above is provided; it is called the "screen 2 start
address register (0x39FFEE, 0x39FFEF)". Use this register to set the start address of screen 2. In the initial state,
the start address of screen 2 is set to 0x0, as with screen 1.
Use the number of lines on screen 1 to specify the position at which to divide between the two screens. To evenly
split an LCD panel with 240 lines of vertical resolution into upper and lower halves, for example, set the value 119
in S1VSIZE[9:0] (D[9:0])/screen 1 vertical size register (0x39FFF3, 0x39FFF2). The LCD panel is separated into
screen 1 consisting of lines 0–119, and screen 2 consisti ng of lines 120–239.
In the initial state, S1VSIZE[9:0] is set to 0. As a result, screen 1 is nonexistent and screen 2 is displayed over the
entire p ane l.
To display only screen 1, s et the same value in S1VSIZE[9:0] as that set in the LDVSIZE[9:0] (D[9:0])/vertical
panel size register (0x39FFE6, 0x39FFE5). The entire screen can be changed instantaneously to different images
by swi tching between S1VSIZE = LDVSIZE and S1V SIZ E = 0.
Virtual Screen and View Port
The LCD c ontrol ler has a virtual-screen f unction that all ows any necessary portion of the screen to be displayed
through panning or scrolling, by holding in memory than that required to achieve the resolution. However, because
a virtual screen is configured within the display memory, it is limited in size to a maximum of 256K bytes. The
area corresponding to the actual LCD panel size is referred to as a view port, and can be relocated within the virtual
screen by changing the display start address.
Virtual screen
View port
(LCD panel size)
Figur e 2.17 Virtual Screen and View Port
The pro cedure for setting a virtual screen and panning or scrolling the view port is explained below, assuming that
screen 1 is used.
Because the view port than that required to achieve the resolution size is equal to that required to achieve the
resolution of the LCD panel, the values set in the horizontal panel size register (0x39FFE4) and vertical panel size
register (0x39FFE6, 0x39FFE5) are applied directly as they are.
VII LCD CONTROLLER BLOC K: LCD CONTROL LER
B-VII-2-24 EPSON S1C33L03 FUNCTION PART
The starting positi on of the view po rt is changed by modifying the screen 1 start address register described above.
For exam ple, when the start address is i ncremented by 16 bits, the pixel displayed at the 17th dot on line 1 m oves
to the beginning of the line, and the 16 leading pixels move off the screen. This is the basic operation for panning
an image. However, when this operation is performed, the 16 leading pixels on line 2 are normally displayed at the
end of line 1, resulting in dislocation of the image. To prevent this problem, set an address offset between the last
piece of pixel data on a line and the fir st piece of pixel data on the next lin e.
Virtual screen
View port
(LCD panel size)
Horizontal
panel size
Offset
A (HW)
Virtual screen
View port
(LCD panel size)
Horizontal
panel size
B
C
B + C = A (HW)
Figur e 2.18 Offsets Comprising a Virtual Screen
Set the offset value in the MADOFS[7:0] (D[7:0])/memory address offset register (0x39FFF1) as a halfword
address. Be aware that if this address is calculated from the number of pixels, the offset value may change
depen ding on the display m ode . When configuring a 248-pixel virtual scree n on a horizontal 200-pixel LCD pa nel,
for example, an offset of 48 pixels is required. The offset value in 1-bpp mo de is 3, whereas that in 8-bpp mode is
24.
This setting allows the view port to be moved horizontally (panned) by an amount equal to the offset, by changing
the screen 1 start address register. The values set in the screen 1 start address register are halfword addresses.
Therefore, the view po rt is moved in 16-pixel units in 1-bpp mode, in 8-pixel units in 2- bpp mo de, in 4-pixel units
in 4-bpp mode, and in 2-pixel units in 8-bpp mode.
Movement of the virtual screen in the vertic al direction is determined by the installed memory capacity, which is
limited to a maximum of 256K byt es of display memor y. To scroll the view port down by one line, s et a one-line-
equivalent address plus an offset address in the screen 1 start address register. To scroll the view port up,
decrement the register value. The view port can also be moved in a diagonal direction by controlling addresses. To
scroll the view port in only the horizontal direction, do not add an offset (leave it at 0).
Even when a virtual scree n is used, the split-screen display described above is possible. Scree n 2 can be pan ned or
scrolled in the same way as for screen 1. Figure 2.19 shows an LCD-panel configuration when a virtual screen and
split-screen dis play are used.
Screen 1
start
address S1VSIZE
+ 1 (lines) LDVSIZE
+ 1 (lines)
LCD panel
Screen 1
Screen 2
(LDHSIZE + 1) × 16 (pixels)
Virtual screen in the display memory
Screen 1 view port
Image 1
Image 2
Screen 2 view port
(LDHSIZE+1) × 16 / BPP
(HW)
BPP = 1, 2, 4, or 8 (bpp)
Screen 2
start
address
Offset
(HW)
Figur e 2.19 Virtual Screen and Split-Screen Display
Note:In po rtrai t mo de (described lat er), t he memory address offset reg ister (0x39FFF1) has no effect.
VII LCD CONTROLLER BLOC K: LCD CONTROLLER
S1C33L03 FUNCTION PART EPSON B-VII-2-25
A-1
B-VII
LCDC
Inverting and Blanking the Display
The display can be blanked (the entir e screen turned black) without rewriting the contents of the display memory.
Setting DBLAN K (D3) /LCD C mode regist er 1 (0x39FFE2) to "1" causes the FPDAT signal to go low, blanking
the display. Setting it to "0" turns the display back on.
Furthermore, the di spla y can be invert ed sim ply by mani pulating bits. Settin g INVDIS P (D0)/LCDC mode regis ter
1 (0x39FFE2) to "1" inverts the display, and setting it to "0" returns the display to normal. This is accomplished by
inverting the display data output from the look-up tables, rather than by inverting the pixel data in the display
memory.
The screen can be ma de to blink using these operations. Make sure switching tak es place w ithin the vertical non-
display period (VNDPF = "1" ).
Portrait Mode
Dependi ng on the a pplications used, the LCD panel ma y nor m ally be used wh ile positi oned horizontally, and ma y
sometimes need to be used after being turned 90 degrees into a vertical position. Generally, image data should be
rotated by software, which, however, adversely affects not only the display performance but also the performance
of the entire system. The LCD controller supports this function in the hardware, enabling images to be rotated 90
degrees without increasing the load on the CPU. This function can be accomplished by setting the LCD controller
to portrait mode. Dependi ng on differences in memory usage and performan ce, two types of portrait modes (default
and alternate portrait modes) are available.
Default portrait mode
Although inferior to alternate portrait mode in terms of display performan ce, default portrait mode is superior
in terms of current consumption, as it enables the use of a slower clock. In this mode, the horizontal size of
images must be increased by the power of 2. To display a horizontal 240-pixel im age in default portrait mode,
for example, memory must be available for 256 pixels (28) equi val en t of horizontal size.
Physical memory
start address
Screen 1
start address
Unused
area
240 pixels
240 lines
256 pixels
320 lines
320 pixels
Display memory LCD panel
Image
Line 1
Line 240
A B E
DC
Image
A B E
DC
Figure 2.20 Image Rotation in Default Portrait Mode
Figure 2.20 show s the relationship between the display memory and the LCD panel in cases in which a 320 ×
240-p ixel LCD pa nel is rot ated 90 degrees to display a 240 × 320-pixel imag e.
The con trol procedure descri bed below is based on the assum ption that the LCD panel is us ed in 8-bpp mode.
1. Make set tings necessary to use an LCD panel con sisting of 320 pixels horizontal ly and 240 lines
vertically. If necessary, set it f or display in nor m al (landsca pe) mode.
2. To swi tch from landscape mode to portr ait mode , temporarily clear the display memory in advance. If
switched over without clearing the display memory, the display may be distorted for a certain period.
3. If the LCD panel was s plit into two screens in landscape mode, reset the S1VSIZE[9:0] (D[9:0])/screen 1
vertical size r egister (0x39FFF 3, 0x39FFF2) by setting a new value above the vertical r esolution of the
LC D panel. In portr ait mode, the LCD pa nel cannot be split for display on screen 2.
VII LCD CONTROLLER BLOC K: LCD CONTROL LER
B-VII-2-26 EPSON S1C33L03 FUNCTION PART
4. Write a portrait-mode display image int o m emory, such as A → B ... C → D.
5. In the line byte-count register (0x39FFFC) for portrait-mode use, set the number of bytes equivalent to
one virtual line of por trait display (256 pix els). For 8-bpp mo de, with on e pixel per byte, it is 25 6 bytes
(0x100). Write 0x0 to the line byte-count register (0x39FFFC) for a one-byte line count. The value 0x0 is
assumed to be 25 6 bytes pe r line. Therefore, the horizontal size of an im age that can be displayed in 8-
bpp por trait m ode is 256 pixels at maximum. For 4-bpp mode, wit h 2 pixels per byte, the byte count is
256/2 = 12 8 (0x80). This value indicates the dist ance in m emor y betw een one piece of pixel data and the
next piece of pixel data when an image is displayed in portrait form .
6. Wr ite the display mem ory address at which pixel B exists to the screen 1 start address register
(0x39FFEC, 0x39FFED, D0/0x39FFF0). Although halfword addresses are set in this register in landscape
mode , addresses must be set in byte units in portrait mode. In the example discussed here, because pixel
A is at 0x 0, the offset from A to B is 240 - 1 = 23 9 (0xE F) bytes. For 4-bpp mo de, thi s is 240/2 - 1 = 119
(0x77) bytes.
7. If necessary, s elect the pixel c lock frequency for use in portr ait mode by using the PMODCLK [1:0]
(D[1:0])/portrait mode register (0x39FFFB). This clock division circuit is provided specifically for
portrait di splay on a smal l LCD pan el. If the pixel clock frequency is changed here, the frame rate must
be reviewed, including resetting of the non-display-period parameters.
Table 2.14 Clock Settings for Default Portrait Mode
PMODCLK1 PMODCLK0 Pixel clock PCLK Memory clock MCLK
00 CLK CLK
01 CLK/2 CLK/2
10 CLK/4 CLK/4
11 CLK/8 CLK/8
CLK denotes the LCDC clock selected using the LCLKSEL[2:0] (D[2:0])/FIFO control register
(0x39FFF4).
8. Set default portrait mode .
PMODEN (D7)/portrait mode register (0x39FFFB) = "1"
PMODSEL (D6)/portra it mode register (0x39FFFB) = "0"
Upon completion of the above setting, the display mode is switched to portrait mode.
In the example discussed here, the display memory contains blank space equivalent to 16 horizontal pixels.
This portion can be used in the same way as a me m ory address offset, which is set in order to configure a
virtual scr een in landscape mode. Therefore, images can be panned within the scope of this number of pixels.
The image dis played on the screen is moved to the left or right by incrementing or decrementing the screen 1
start address register in 1-byte units. Note that settings of the memory-address offset register have no effect in
portrait mode.
Images can also be scrolled in the vertical direction by changing the screen 1 start address register.
Note:In de fault por tr ait mode, the screen cann ot be scrolled i n the vertic al dir ection one line at a time.
Always ma ke sure the screen is scr olled t w o lines at a t ime. To this en d, increment or decrement
the s creen 1 start address register by an amount equal to twice the num ber of bytes set in t he line
byte count registe r (0x39FFFC) in st ep 5.
VII LCD CONTROLLER BLOC K: LCD CONTROLLER
S1C33L03 FUNCTION PART EPSON B-VII-2-27
A-1
B-VII
LCDC
Alternate por trait mode
Alternate portrait mode does not require extra display memory as in default portrait mode. To display the
same ho rizontal 240-pixel image as in the above exampl e, the display me m ory requires byte counts for only
240 pixels per line. Although alternate portrait mode pro vides higher display performan ce than de fault
portrait mode, it requires a clock twice as fast at the same frame rate, resulting in larger current consumption.
Physical memory
start address Screen 1
start address
240 pixels
240 lines
320 lines
320 pixels
Display memory LCD panel
Image
Line 1
Line 240
A B
DC
Image
A B
DC
Figure 2.21 Image Rotation in Alternate Portrait Mode
Figure 2.21 show s the relationship between the display memory and the LCD panel in cases in which a 320 ×
240-p ixel LCD pa nel is rot ated 90 degrees to display a 240 × 320-pixel imag e.
The con trol procedure descri bed below assume s that t he LCD panel is used in 8- bpp mo de.
1. Make set tings necessary to use an LCD panel con sisting of 320 pixels horizontal ly and 240 lines
vertically. If necessary, set it for display in norma l (landsca pe) mode.
2. To swi tch from landscape mode to portr ait mode , temporarily clear the display memory in advance. If
switched over without clearing the display memory, the display may be distorted for a certain period.
3. If the LCD panel was split into two screens in landscape mode, reset the S1VSIZE[9:0] (D[9:0])/screen 1
vertical size r egister (0x39FFF 2) by setting a new value above the vertical resolution of the LCD panel in
it. In portrait mode, the LCD panel cannot be split for display on screen 2.
4. Write a portrait-mode display image int o m emory, such as A → B ... C → D.
5. In the line byte-count register (0x39FFFC) for portrait-mode use, set the number of bytes equivalent to
one line of portrait di splay (240 pixels). For 8-bpp mode, wi th on e pixel per byte, it is 24 0 bytes (0xF0 ).
Write 0xF0 to the line byte-count register (0x39FFFC) for one-byte line count. Even in the case of
alternate portrait mode, the horizontal size of an image that can be displayed in 8-bpp por trait mode is
maximum of 256 pi xels. For 4-bpp mode , with 2 pixels per byte, t he by te count is 240/2 = 12 0 (0x78).
This value indicates the distance in memory between one piece of pixel data and the next piece of pixel
data wh en displaye d in portrait mode.
6. Wr ite the display mem ory address at which pixel B exists to the screen 1 start address register
(0x39FFEC, 0x39FFED, D0/0x39FFF0). Although halfword addresses are set in this register in landscape
mode , addresses must be set in byte units in portrait mode. In the exa m ple discussed here, because pixel
A is at 0x 0, the offset from A to B is 240 - 1 = 23 9 (0xE F) bytes. For 4-bpp mo de, thi s is 240/2 - 1 = 119
(0x77) bytes.
VII LCD CONTROLLER BLOC K: LCD CONTROL LER
B-VII-2-28 EPSON S1C33L03 FUNCTION PART
7. If necessary, s elect the pixel c lock frequency for use in portr ait mode by using the PMODCLK [1:0]
(D[1:0])/portrait mode register (0x39FFFB). Note that, in alternate portrait mode, the pixel clock
frequency is halved compared to that in landscape mode, without specifically changing register settings.
Therefore, the frame rate must be reviewed, including resetting of the non-display-period parameter. For
details on calculating the frame rate, refer to "Frame Rate".
Table 2.15 Clock Settings for Alternate Portrait Mode
PMODCLK1 PMODCLK0 Pixel clock PCLK Memory clock MCLK
00 CLK/2 CLK
01 CLK/2 CLK
10 CLK/4 CLK/2
11 CLK/8 CLK/4
CLK denotes the LCDC clock selected using the LCLKSEL[2:0] (D[2:0])/FIFO control register
(0x39FFF4).
8. Set alternate portrait mode.
PMODEN (D7)/portr ait- m ode regist er (0x39F FFB) = "1"
PMODSEL (D6)/portra it -mod e register (0x39FFFB) = "1"
Upon completion of the above setting, the display mode is switched to portrait mode.
When using an LCD pa nel with a vertical resolution of less than 256 lines, a virtual screen similar to the one
in default portrait mode can be configured. The screen can be panned or scrolled by setting a value (including
offset) in the line byte count register, and then controlling the screen 1 start address register.
In alternate portrait mode, the screen can be scrolled in the vertical direction one line at a time.
Comparison of portrait modes
The differences between default portra it mo de and alternate portrait m ode are sum m arized in Table 2.16.
Table 2.16 Differences between Portrait Modes
Parameter Default portrait mode Alternate po rtrait mode
Display
memory Sufficient display memory must be available
so that the horizontal size following rotation
is the original value to the power of 2. In
many cases, that value differs from the LCD
panel size, and an unused area occurs
unless the value is used as a virtual screen.
To display a 240 × 320-pixel image by
rotating a 32 0 × 240-pixel LCD panel 90
degrees, for example, as much display
memory as for a horizontal size of 28 = 256
pi xe ls mu st be avai labl e. Fo r 8-b pp mode,
this is normally 320 × 240 = 76,800 bytes,
but for portrait display, 256 × 320 = 81,920
bytes are required.
If a v irtual screen is not being configured, no
memory area other than that for the image
size is required.
Clock MCLK for display memory access and the
pixel clock PCLK for LCD display may be
used at the same speed.
MCLK must be twice as fast as PCLK.
PCLK cannot be set to above 12.5 MHz.
Power
consumption The LCD controller can operate at low
power. A greater amount of power than in default
portrait mode is consumed.
Vertical scroll Ca n be scrolled two lines at a time. Can be scrolled one line at a time.
Display
performance Standard performance. Higher performance than default portrait
mode.
VII LCD CONTROLLER BLOC K: LCD CONTROLLER
S1C33L03 FUNCTION PART EPSON B-VII-2-29
A-1
B-VII
LCDC
Power Save
The LCD controller ha s two types of pow er-save m ode s. Us e LPSAVE[ 1:0] (D[1:0])/LCDC mode register 2
(0x39FFE3) to set power-sav e modes.
Table 2.17 Settings of Power-Save Modes
LPSAVE1 LPSAVE0 Mode
00Power-save mode
01Reserved
10Doze mode
11Normal operation
Power-save m o de
When the LCD controller enters this mode, all LCD signal output pins, including the LCDPWR pin, are
dropped l o w , with the LCD panel placed in power-down mode. All operations of the LCD controller, other
than accessing of its control registers, are disabled. The look-up tables cannot be accessed.
The LCD controller i s placed in powe r-save mo de by setting LPSAVE to "00", thereby executing a power-
down sequence. The LCDPWR signal goes low a one-frame period later, and LCD signals are deasserted.
Note:Because the bus clock is turned off i n HALT2 or SLEEP mo de, the one-fra m e period describ ed
above must ela pse be fore the chip can be placed in standby mode. The nu mb er of f rames can be
counted by reading the VNDPF (D7)/vertical non-di splay period r egister (0x39FFEA) rep eatedly.
VN DPF is set to "1" during t he verti cal non-dis play period ( set to "0" during t he displ ay period).
The LCD controller i s taken out of power- save m ode by setting LPSAVE to "11", thereby executing a power-
up seq uence. The LCD signal output is enabled and the LCDPWR signal goes high a one-frame period after
po w er-sav e m ode is released.
The abo ve power-up/power-down sequences can be controlled with a user’s desired timing by using
LPWREN (D4)/LCD C m ode regist er 2 (0x39FFE3). For details on the control procedure, refer to
"Controlling LCD Power Up/Down".
Doze mode
Doze mode is a pow er-sav e m ode designed for use with Epso n’s MLS LC D drivers. Wh en MLS LCD drivers
are used, there is no need to send data constantly in order to refresh the display of the same image. The LCD
controller can be set in doze mode during this period. In doze mode, the FPDAT and FPSHIFT signals are
fixed low so that no access to the display memory occurs. Although the power-saving effects are not as
significant as in power-save mode, this mode helps reduce the current consumption in the LCD panel while
keeping the display on .
Comp ari so n of p ow er-save modes
The differences between pow er-save m ode s are summarized in Table 2.18.
Table 2.18 Differences between Power-Save Modes
Item Doze mode Power-save mode Normal
Accessing IO register s Ena ble d Ena ble d Ena ble d
Accessing lo ok -up ta ble Enabled Disabl ed Enable d
Sequence controller in LCDC Run Stop Run
Display Display Blank Display
LCDPWR signal Active Inactive Active
FPDAT[7:0], FPSHIFT signals Forced low Forced low Active
FPLINE, FPFRAME, DRDY signals Active Forced low Active
VII LCD CONTROLLER BLOC K: LCD CONTROL LER
B-VII-2-30 EPSON S1C33L03 FUNCTION PART
Controlling the GPIO Pins
The pin s described below can be used a s general-purpos e output (G PO) pi ns or gen eral-purpose input/output
(GPIO) pins, through panel selection or other settings.
General-purpose output (GPO) pins
The FPDAT[3 :0] signal output pins can be used as general-purp ose output GPO[6:3] pins when a 4-bit LCD
panel (LDDW[1:0] (D[1:0])/0x39FFE1) = "00") is used. The GPO output c ontrol bits are listed in Table 2.19.
Table 2.19 GOP Control Bits
Pin name GPO signal name Output control bit
FPDAT0 GPO3 GPO3D (D3)/GPIO status/control register(0x39FFF9)
FPDAT1 GPO4 GPO4D (D4)/GPIO status/control register(0x39FFF9)
FPDAT2 GPO5 GPO5D (D5)/GPIO status/control register(0x39FFF9)
FPDAT3 GPO6 GPO6D (D6)/GPIO status/control register(0x39FFF9)
Setting the GPOxD bit to 1 drives the GPOx output high, and setting the GPOxD bit to 0 drives the GPOx
output low.
Note:In po wer-save or doze mo de, these pins are fix ed low.
General-purpose input/output (GPIO) pins
While the LCD controller is enabled (LCDCEN (D5)/LCDC mode register 2 = "1"), bus release requests
(#BUSREQ) from outside the chip can be disabled. When the BREQEN (D2)/LCDC system control register
(0x39FFFD) is set to "0" (default), bus release requests from outside will no longer be accepted while
LCDCEN = "1". As a resu lt, the pins listed below will not be used for bus-release purposes, and can therefore
be use d as general-purp ose input/output (GPIO ) pins. Because these pins are usable only while the LCD
controller remains enabled, the control registers in the LCD controller block must be used to control their
direction for i nput or output, as well as to read/write data to and from them.
Table 2.20 GPIO Control Bits
Pin name GPIO signal
name I/O control bit I/O data
#BUSREQ/P34 GPIO0 GPIO0C (D0)/GPIO configuration
register(0x39FFF8) GPIO0D (D0)/GPIO status/control
register(0x39FFF9)
#BUSACK/P35 GPIO1 GPIO1C (D1)/GPIO configuration
register(0x39FFF8) GPIO1D (D1)/GPIO status/control
register(0x39FFF9)
#BUSGET/P31 GPIO2 GPIO2C (D2)/GPIO configuration
register(0x39FFF8) GPIO2D (D2)/GPIO status/control
register(0x39FFF9)
Set the GPIOxC bits to "0" (default) when the GPIOx pins are used as input ports, or "1" when the GPIOx
pins are used as output ports.
When the pins are set for input, it possible to determine their input-voltage level by reading GPIOxD. The
value "1" is indicated when the input voltage is high, and "0" indicated when the input voltage is low.
When the pins are set for output, write output data to GPIOxD. Setting the GPIOxD bit to "1" drives the
GPIOx ou tput high, and setting the G PIOxD bit to "0" drives the GPIOx output low.
VII LCD CONTROLLER BLOC K: LCD CONTROLLER
S1C33L03 FUNCTION PART EPSON B-VII-2-31
A-1
B-VII
LCDC
I/O Memory of LCD Controller
Table 2.21 shows t he control bits of the LCD controller. These registers are mapped into area 6 (0x39FFE0 to
0x39FFFD).
Table 2.21 Control Bits of LCD Controller
NameAddressRegister name Bit Function Setting Init. R/W Remarks
PCODE5
PCODE4
PCODE3
PCODE2
PCODE1
PCODE0
RCODE1
RCODE0
D7
D6
D5
D4
D3
D2
D1
D0
Product code
Revision code
0
0
0
0
1
0
0
0
R
R
039FFE0
(B)
Revision code
register 0b000010
–
–
–
LDCOLOR
–
FPSMASK
LDDW1
LDDW0
D7–6
D5
D4–3
D2
D1
D0
reserved
Color/monochrome select
reserved
Mask FPSHIFT signal
LCD data width/format
–
0
–
0
0
0
–
R/W
–
R/W
R/W
0 when being read.
0 when being read.
039FFE1
(B) 1Color 0Mono
1Masked 0Output
LCDC mode
register 0
1
0
0
x
1
0
LDDW[1:0] Monochrome
reserved
8 bits
4 bits
1
1
0
0
1
0
1
0
LDDW[1:0] Color
8 bits/format 2
reserved
8 bits/format 1
4 bits
–
–
BPP1
BPP0
–
DBLANK
FRMRPT
–
INVDISP
D7
D6
D5–4
D3
D2
D1
D0
Bit-per-pixel select
(Display mode)
reserved
Blank display
Frame repeat for EL panel
reserved
Invert display
0
0
–
0
0
–
0
R/W
–
R/W
R/W
–
R/W
0 when being read.
0 when being read.
039FFE2
(B)
1Repeated 0
Not repeated
1Inverted 0Normal
1Blank 0Normal
LCDC mode
register 1 1
1
0
0
1
0
1
0
BPP[1:0] Mode
8 bpp
4 bpp
2 bpp
1 bpp
–
–
–
LCDCEN
LPWREN
–
LPSAVE1
LPSAVE0
D7–6
D5
D4
D3–2
D1
D0
reserved
LCD controller enable
LCDPWR enable
reserved
Power save mode
–
0
0
–
0
0
–
R/W
R/W
–
R/W
0 when being read.
0 when being read.
039FFE3
(B) 1Enabled 0Disabled
1Enabled 0Disabled
LCDC mode
register 2
1
1
0
0
1
0
1
0
LPSAVE[1:0] Mode
Normal operation
Doze
reserved
Power save
–
LDHSIZE5
LDHSIZE4
LDHSIZE3
LDHSIZE2
LDHSIZE1
LDHSIZE0
D7–6
D5
D4
D3
D2
D1
D0
reserved
Horizontal panel size –
0
0
0
0
0
0
–
R/W 0 when being read.039FFE4
(B)
Horizontal
panel size
register
–
H resolution (pixels) - 1
16
LDVSIZE7
LDVSIZE6
LDVSIZE5
LDVSIZE4
LDVSIZE3
LDVSIZE2
LDVSIZE1
LDVSIZE0
D7
D6
D5
D4
D3
D2
D1
D0
Vertical panel size
(low-order 8 bits) 0
0
0
0
0
0
0
0
R/W039FFE5
(B)
Vertical
panel size
register 0
V resolution (lines) - 1
–
LDVSIZE9
LDVSIZE8
D7–2
D1
D0
reserved
Vertical panel size
(high-order 2 bits)
–
0
0
–
R/W 0 when being read.039FFE6
(B)
Vertical
panel size
register 1
–
V resolution (lines) - 1
–
HNDP4
HNDP3
HNDP2
HNDP1
HNDP0
D7–5
D4
D3
D2
D1
D0
reserved
Horizontal non-display period –
0
0
0
0
0
–
R/W 0 when being read.039FFE7
(B)
Horizontal
non-display
period register
–
Non-display period (pixels) - 4
8
VII LCD CONTROLLER BLOC K: LCD CONTROL LER
B-VII-2-32 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
VNDPF
–
VNDP5
VNDP4
VNDP3
VNDP2
VNDP1
VNDP0
D7
D6
D5
D4
D3
D2
D1
D0
Vertical non-display period status
reserved
Vertical non-display period
0
–
0
0
0
0
0
0
R
–
R/W 0 when being read.
039FFEA
(B)
Vertical
non-display
period register –
Non display period (lines)
1VNDP 0Display
–
MODRATE5
MODRATE4
MODRATE3
MODRATE2
MODRATE1
MODRATE0
D7–6
D5
D4
D3
D2
D1
D0
reserved
MOD rate –
0
0
0
0
0
0
–
R/W 0 when being read.039FFEB
(B)
MOD rate
register –
S1ADDR7
S1ADDR6
S1ADDR5
S1ADDR4
S1ADDR3
S1ADDR2
S1ADDR1
S1ADDR0
D7
D6
D5
D4
D3
D2
D1
D0
Screen 1 start address
(low-order 8 bits) 0
0
0
0
0
0
0
0
R/W039FFEC
(B)
Screen 1
start address
register 0
S1ADDR15
S1ADDR14
S1ADDR13
S1ADDR12
S1ADDR11
S1ADDR10
S1ADDR9
S1ADDR8
D7
D6
D5
D4
D3
D2
D1
D0
Screen 1 start address
(high-order 8 bits) 0
0
0
0
0
0
0
0
R/W039FFED
(B)
Screen 1
start address
register 1
S2ADDR7
S2ADDR6
S2ADDR5
S2ADDR4
S2ADDR3
S2ADDR2
S2ADDR1
S2ADDR0
D7
D6
D5
D4
D3
D2
D1
D0
Screen 2 start address
(low-order 8 bits) 0
0
0
0
0
0
0
0
R/W039FFEE
(B)
Screen 2
start address
register 0
S2ADDR15
S2ADDR14
S2ADDR13
S2ADDR12
S2ADDR11
S2ADDR10
S2ADDR9
S2ADDR8
D7
D6
D5
D4
D3
D2
D1
D0
Screen 2 start address
(high-order 8 bits) 0
0
0
0
0
0
0
0
R/W039FFEF
(B)
Screen 2
start address
register 1
–
S1ADDR16
D7–1
D0 reserved
Screen 1 start address (MSB)
(for portrait mode;
fix at 0 in landscape mode)
–
0–
R/W 0 when being read.039FFF0
(B)
Screen 1
start address
register 2
–
MADOFS7
MADOFS6
MADOFS5
MADOFS4
MADOFS3
MADOFS2
MADOFS1
MADOFS0
D7
D6
D5
D4
D3
D2
D1
D0
Memory address offset 0
0
0
0
0
0
0
0
R/W039FFF1
(B)
Memory
address offset
register
S1VSIZE7
S1VSIZE6
S1VSIZE5
S1VSIZE4
S1VSIZE3
S1VSIZE2
S1VSIZE1
S1VSIZE0
D7
D6
D5
D4
D3
D2
D1
D0
Screen 1 vertical size
(low-order 8 bits) 0
0
0
0
0
0
0
0
R/W039FFF2
(B)
Screen 1
vertical size
register 0
VII LCD CONTROLLER BLOC K: LCD CONTROLLER
S1C33L03 FUNCTION PART EPSON B-VII-2-33
A-1
B-VII
LCDC
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
S1VSIZE9
S1VSIZE8
D7–2
D1
D0
reserved
Screen 1 vertical size
(high-order 2 bits)
–
0
0
–
R/W 0 when being read.039FFF3
(B)
Screen 1
vertical size
register 1
–
–
FIFOEO3
FIFOEO2
FIFOEO1
FIFOEO0
LCLKSEL2
LCLKSEL1
LCLKSEL0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
FIFO empty offset
LCDC clock select
–
0
0
0
0
0
0
0
–
R/W
R/W
0 when being read.039FFF4
(B)
FIFO control
register –
Fix at 8 (0b1000)
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
LCLKSEL[2:0]
LCDC clock
BCU_CLK/4
BCU_CLK/3
BCU_CLK/2
BCU_CLK
reserved
Stop
Stop
Stop
–
LUTADDR3
LUTADDR2
LUTADDR1
LUTADDR0
D7–4
D3
D2
D1
D0
reserved
Look-up table address –
0
0
0
0
–
R/W 0 when being read.039FFF5
(B)
Look-up table
address
register
–
LUTDT3
LUTDT2
LUTDT1
LUTDT0
–
D7
D6
D5
D4
D3–0
Look-up table data
reserved
0
0
0
0
–
R/W
–0 when being read.
039FFF7
(B)
Look-up table
data register
–
–
GPIO2C
GPIO1C
GPIO0C
D7–3
D2
D1
D0
reserved
GPIO2 configuration
GPIO1 configuration
GPIO0 configuration
–
0
0
0
–
R/W
R/W
R/W
0 when being read.039FFF8
(B)
GPIO
configuration
register
–
1Output 0Input
1Output 0Input
1Output 0Input
–
GPO6D
GPO5D
GPO4D
GPO3D
GPIO2D
GPIO1D
GPIO0D
D7
D6
D5
D4
D3
D2
D1
D0
reserved
GPO6 data
GPO5 data
GPO4 data
GPO3 data
GPIO2 data
GPIO1 data
GPIO0 data
–
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.039FFF9
(B)
GPIO
status/control
register
–
1High 0Low
1High 0Low
1High 0Low
1High 0Low
1High 0Low
1High 0Low
1High 0Low
SP1A7
SP1A6
SP1A5
SP1A4
SP1A3
SP1A2
SP1A1
SP1A0
D7
D6
D5
D4
D3
D2
D1
D0
Scratch pad 0
0
0
0
0
0
0
0
R/W039FFFA
(B)
Scratch pad
register
–
PMODEN
PMODSEL
–
PMODCLK1
PMODCLK0
D7
D6
D5–2
D1
D0
Portrait mode enable
Portrait mode select
reserved
Portrait mode clock select
(LCDC clock division ratio)
Division ratio 1: Default mode
Division ratio 2: Alternate mode
P: Pixel clock, M: Memory clock
0
0
–
0
0
R/W
R/W
–
R/W 0 when being read.
039FFFB
(B) 1 Portrait 0 Landscape
1Alternate 0Default
Portrait mode
register
1
1
0
0
1
0
1
0
PMODCLK[1:0]
Division ratio 1
P: 1/8, M: 1/8
P: 1/4, M: 1/4
P: 1/2, M: 1/2
P: 1/1, M: 1/1
1
1
0
0
1
0
1
0
PMODCLK[1:0]
Division ratio 2
P: 1/8, M: 1/4
P: 1/4, M: 1/2
P: 1/2, M: 1/1
P: 1/2, M: 1/1
PMODLBC7
PMODLBC6
PMODLBC5
PMODLBC4
PMODLBC3
PMODLBC2
PMODLBC1
PMODLBC0
D7
D6
D5
D4
D3
D2
D1
D0
Line byte count 0
0
0
0
0
0
0
0
R/W039FFFC
(B)
Line byte
count register
for portrait
mode
VII LCD CONTROLLER BLOC K: LCD CONTROL LER
B-VII-2-34 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
VRAMAR
VRAMWT2
VRAMWT1
VRAMWT0
EDMAEN
BREQEN
LCDCST
LCDCEC
D7
D6
D5
D4
D3
D2
D1
D0
VRAM area select
VRAM wait control
(number of wait cycles for SRAM)
External DMA enable
External bus-request enable
A0/BSL select
Big/little endian select
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
039FFFD
(B) 1Area 8 0Area 7
1Enabled 0Disabled
1Enabled 0Disabled
1BSL 0A0
1Big endian 0
Little endian
LCDC
system control
register 0–7
Note:Addresses 0x39FFFE and 0x39FFFF are assigned for the purpose of inspectin g the LC D
controller . Writing da ta to t hese ad dresses may damage the LCD contr oller and the LCD pane l t o
which the LCD controll er is connected. Therefor e, make sure data is never wri tt en to that location.
PCODE[5:0]: Product code (D[7:2]) / Revision code register (0x39FFE0)
The LCD c ontroller’s product code (0b000010) is written here. These bits are read-only, and writing to them has
no effect.
RCODE[1:0]: Revision code (D[1:0]) / Revision code register (0x39FFE0)
The LCD c ontroller’s revision code (0b00) is written here. These bits are read-only, and writing to them has no
effect.
LDCOLOR: Color/monochrome sel ect ( D 5) / L CDC mode regis ter 0 ( 0x39FFE1)
Selects the type of connected LCD panel (color or monochrome).
Write "1": Col or panel
Write "0": Monochr ome panel
Read: Valid
Setting LDCOLOR to "1" selects a color panel drive method, and setting it to "0" selects a monochrome panel
drive m ethod.
At i nitial reset, LDCOLOR is set to "0" (monochrome panel).
FPSMASK: Mas k FPS H IF T sign al (D2) / LCDC mo de register 0 (0x39FFE1)
Selects the FPSHIF T m ask (effective only for color LCD panels).
Write "1": Maske d
Write "0": Out put
Read: Valid
When FPSM ASK is set to "1", the FPSHIFT signal is masked and is not output during the non-display period.
When FPSM ASK is set to "0", the FPSHIFT signal is output even during the non-display period. This setting is
effective only for color LCD panels (LDCOLOR = "1"). When a monochrome LCD panel is used, the FPSHIFT
signal is not masked regardless of the setting of this bit.
At i nitial reset, FPSMASK is set to "0" (output).
LDDW[1:0]: LCD data width/format (D[1:0]) / LCDC mode register 0 (0x39FFE1)
Selects the LCD panel’s data width and format. The contents of selection, including that of LDCOLOR, are listed
in Table 2.22.
Table 2.22 Selection of LCD Panels
LDCOLOR LDDW1 LDDW0 LCD panel
0Mono Single 4-bit passive LCD01Mono Single 8-bit passive LCD
0Reserved
0
11Reserved
0Color Single 4-bit passive LCD01Color Single 8-bit passive LCD format 1
0Reserved
1
11Color Single 8-bit passive LCD format 2
At i nitial reset, LDDW is set to "0b00" (4-bit panel).
VII LCD CONTROLLER BLOC K: LCD CONTROLLER
S1C33L03 FUNCTION PART EPSON B-VII-2-35
A-1
B-VII
LCDC
BPP[1:0]: Bit-per-pixel select (D[7:6]) / LCDC mode register 1 (0x39FFE2)
Selects display mode (bpp m ode). The con tents of selec tion, includi ng that of LDCOLOR, are l isted in Table 2.23.
Table 2.23 Specification of Display Modes
LDCOLOR BPP1 BPP0 Di splay mode
02 gray scal e 1 bi t- pe r-p ix el014 gray scale 2 bit-per-pixel
016 gray scale 4 bit-per-pixel
0
11Reserved
02 colors 1 bi t- pe r-p ix el014 colors 2 bi t-pe r-p ix el
016 colors 4 bit -pe r-p ix el
1
11256 colors 8 bit-per-pixel
At i nitial reset, BPP is set to "0b00" (1-bpp mode).
DBLANK: Blank display (D3) / LCDC mode register 1 (0x39FFE2)
Clears the display (entire screen turned black).
Write "1": Blank
Write "0": N ormal display
Read: Valid
When DBLANK is set to "1", all FPDAT signals are dropped low to clear the display. When DBLANK is set to
"0", d ata in the display memory is displayed on the LCD panel. This setting does not affect the display memory.
At i nitial reset, DBLANK is set to "0" (normal display).
FRMRPT: Frame repeat f or EL panel (D2) / LCDC mode registe r 1 (0x39FFE2)
Selects whether to repeat the frame-rate modulation pattern (effective only for EL panels).
Write "1": Repea ted
Write "0": Not repeated
Read: Valid
When FRMRPT is set to "1", the internal 19-bit frame counter is enabled and starts counting the number of frames.
Each time this counter overflows (0x40000 = 0), the frame-rate modulation pattern is repeated. When FRMRPT is
set to "0", the counter is disabled and the frame-rate modulation pattern is not repeated.
At i nitial reset, FRMRPT is set to "0" (not repeated).
INVDISP: Invert display (D0) / LCDC mo de register 1 (0x39FFE2)
Inverts th e disp lay.
Write "1": Inverted
Write "0": N ormal display
Read: Valid
When INVDI SP is set to "1", the di spla y on the LCD panel is inverted (displayed in inverse video). When
INVDISP is set to "0", normal di splay i s ma intained. Invers operation i s a pplied to ou tput of the look-up tables ,
and d oes not af fect th e disp lay memory.
At i ni tial reset, INVDISP is set to "0" (no rmal dis play).
LCDCEN: Enable LCDC (D5) / LCDC mode registe r 2 (0x 39FF E3)
Enables the LCD controller for use.
Write "1": Ena bled
Write "0": Disabl ed
Read: Valid
When LCDCEN is set to "1", the LCD controller is supplied with a clock and starts operating. When LCDCEN is
set to "0", the LCD controller stops operating. Note that if the power to the LCD panel turns on while LCD signals
are not output correctly, the LCD panel may be degraded or dam age d.
At i nitial reset, LCDCEN is set to "0" (disabled).
VII LCD CONTROLLER BLOC K: LCD CONTROL LER
B-VII-2-36 EPSON S1C33L03 FUNCTION PART
LPWREN: Enable LCDPWR (D4) / LCDC mode register 2 (0x39FFE3)
Enables LCDPWR output c ontrol by the LCD controller.
Write "1": Ena bled
Write "0": Disabl ed
Read: Valid
When LPWREN is set to "1", the LCDPWR output is controlled by the LCD controller’s power-up/down sequence,
allowing the power to the LCD panel to be turned ON or OFF using that signal. When LPWREN is set to "0", the
LCDPWR pin is fixed low.
At i nitial reset, LPWREN is set to "0" (disabled).
LPSAVE[1:0]: Power-s av e mod e (D[1:0 ]) / L CDC mode regis ter 2 ( 0x39FFE3)
Selects po w er-sav e m ode .
Table 2.24 Settings of Power-Save Modes
LPSAVE1 LPSAVE0 Mode
00Power-save mode
01Reserved
10Doze mode
11Normal operation
When plac ed in power-save mode, the LCD controller executes a power-down sequence; when taken out of power-
save mode, the LCD controller executes a power-up sequence (for details, refer to "Controlling LCD Power
Up/Down"). Doze m ode can only be selected w hen Epso n’s MLS LCD drivers are used.
At i nitial reset, LPSAVE is set to "0b00" (power-save mode).
LDHSIZE[5:0]: Horizontal panel size (D[5:0]) / Horizontal panel size registe r (0x39FFE4)
Sets the horizontal resolution of the LCD panel in 16-pixel units. Set the value obtained using the equation below.
Hori zontal res oluti on (in pixels)
LDHSIZE[5:0] = —————————————— - 1
16
For an LC D panel with a horizontal res olution of 320 dots, for exa m ple, set 19 (= 0x13) in LDH SIZE . Do not set
any value less than 1 in this register.
At i nitial reset, LDHSIZE is set to "0x0".
LDVSIZE[9:0]: Vertical panel size (D[9:0]) / Vertical panel size register (D[1:0]/0x39FFE6, 0x39FFE5)
Sets the vertical resolution of the LCD panel in units of lines. Set the value obtained using the equation below.
LDVSIZE[9:0] = Vertical resolution (in lines) - 1
For an LC D pan el with a vertic al resolution of 24 0 lines, f or exampl e, set 239 ( = 0xEF) in LD V SIZE .
At i nitial reset, LDVSIZE is set to "0x0".
HNDP[4:0]: Horizontal non-display period (D[4:0]) / Horizontal non-di splay period register (0x39FFE7)
Sets the horizontal non-display period i n 8-p ixel units. Set the value obtained using the equation below.
Horizont al non-dis play period ( in pix els)
HNDP[4:0] = ———————————————— —— - 4
8
At i nitial reset, HNDP is set to "0x0".
VNDP[5:0]: Ver tic al non -d isp la y period (D[5:0 ]) / V er tic al non-display period register (0x39FFEA)
Sets the vertical non-displ ay pe riod in units of lines. Set the value obtained using the equation below.
VN DP[5:0] = Verti cal non- display per iod (in lines )
At i nitial reset, VNDP is set to "0x0".
VII LCD CONTROLLER BLOC K: LCD CONTROLLER
S1C33L03 FUNCTION PART EPSON B-VII-2-37
A-1
B-VII
LCDC
VNDPF: Vertical non-display status (D7) / Vertical non-display period register (0x39FFEA)
Indicates whether the LCD panel is in a vertical non-display period.
Read "1" : Verti cal non-display perio d
Read "0" : Vertical display period
Write: Invalid
VNDPF is set to "1" during a ver tical non-display period, and set to " 0" during a vertical displ ay pe riod. To count
the number of frames in LCD power control, for example, read this bit and count the number of times it is set to
"1". O n other occasion s, such as when images must be switched without causing the screen to flicker, it is possible
to switch within a vertical non-display period by reading this bit.
At i nitial reset, VNDPF is set to "0" (vertical display period).
MODRATE[5:0]: MO D rate (D[5 :0 ]) / MO D ra te regist er (0x39F FEB )
Sets the cycle time at which to switch the MOD signal. When this register is 0x0, the MOD signal switches at the
cycle time of the FPFRAME signal. If another period is desired, set the FPLINE pulse-count value.
At i nitial reset, MODRATE is set to "0x0" (FPFRAME period).
S1ADDR[16:0]: Screen 1 sta rt address register ( D0/0x39FFF0, 0x39FF ED, 0x39FFEC)
Sets the screen 1 start address. Referencing the beginning of the display memory as address 0x0, write a halfword
address in 16-bit units in normal (landscape) mode, or a byte address in portra it mode. S1A DDR16 (D0/0x39FFF0 )
is provided for use in portrait mode. It is unuse d in normal (la nds cape ) m ode , so fix it to "0" .
At i nitial reset, S1ADDR is set to "0x0" (beginning of the display memory).
S1VSIZE[9:0]: Screen 1 ver ti cal size register (D[1:0]/0x 39FFF 3, 0x39FF F2)
Sets the vertical size of screen 1 in lines. If any number of lines less than the LCD panel’s vertical resolution
(LDVSIZE[9:0]) is set in this register, the LCD panel is divided into an upper half from line 1 to line (S1VSIZE -
1) as screen 1, and a lower half from that line down as screen 2. When the screen is not to be divided, set any value
equal to or greater than LDVSIZE in this register, so that only screen 1 will be displayed.
At i nitial reset, S1VSIZE is set to "0x0".
S2ADDR[15:0]: Screen 2 sta rt address r egister ( 0x39 FFEF, 0x39FFEE)
Sets the screen 2 start address. Referencing the beginning of the display memory as address 0x0, write a halfword
address in 16-bit units. This register is unused for portrait mode, as split-screen display is not supported in that
mode.
At i nitial reset, S2ADDR is set to "0x0" (beginning of the display memory).
MADOFS[7:0]: Memory address offset (D[7:0]) / Memory address offset register (0x39FFF1)
Sets an address offset in halfword units to configure a virtual screen in nor m al (landsca pe) mode. The offset set
here is added to the address of the last piece of pixel data on each display line, in order to determine the address at
which the next display line starts. The image area is extended in the horizontal direction by a distance equal to this
offset, so that the display area can be panned or scrolled by setting the start-address register as necessary. For
details, refer to "Virtual Screen and View Port".
This register i s unused in portrait mode.
At i nitial reset, MADOFS is set to "0x0" (no virtual screen area).
FIFOEO[3:0]: FIFO empty offset (D[6:3]) / FIFO control register (0x39FFF4)
The LCD c ontroller retrieves data from the display memory into its 16 × 16-bit FIFO by means of a DMA transfer.
If the amount of data in this FIFO decreases to (0xf - FIFOEO) words or less, the LCD controller sends a DMA
request to the CPU requesting that the data be read. Set the value 8 in FIFOEO.
At i nitial reset, FIFOEO is set to "0x0".
VII LCD CONTROLLER BLOC K: LCD CONTROL LER
B-VII-2-38 EPSON S1C33L03 FUNCTION PART
LCLKSEL[2:0]: LCDC clock select (D[2:0]) / FIFO control register (0x39FFF4)
Selects the operating clock for the LCD controller. The selected clock is used as the LCD controller’s pixel clock
PC LK and displa y m emor y clock MCLK. The maximum clock frequency that can be supplied to the LCD
controller is 25 MHz.
Table 2.25 Selection of LCDC Clocks
LCLKSEL2 LCLKSEL1 LCLKSEL0 LCDC clock
000Turned of f
001Turned of f
010Turned of f
011Reserved (not allowed)
100BCU_CLK
101BCU_CLK/2
110BCU_CLK/3
111BCU_CLK/4
At initial reset, LCLKSEL is set to "0x0" (clock turned off).
LUTADDR[3:0]: LUT address (D[3:0]) / Look-up t able address register (0x39FFF 5)
Specifies the initial address (entry) of the look-up table in which to write data. Writing data (0–15) to this register
selects an entry (0–15) in the red look-up table. When data is set in the look-up-table data registers in order of red,
green, and blue, the data is written to the specified entries in the red, green, and blue look-up tables. LUTADDR is
incremented at the same time data is written, indicating the next entry. Once an entry is specified, data can be
written to the look-up tables successively. The entry address is also incremented in the same way when data is read
from the look-up-table data registers. This register must always be accessed bytewise for both reading and writing.
At i nitial reset, LUTADDR is set to "0x0" (entry 0 in the red look-up table).
LUTDT[3:0]: LUT data (D[7:4]) / Look-up table data register (0x39FFF7)
Use this register to read or write to the look-up tables.
Each time this register is accessed, the look-up-table pointer changes in the order shown below (provided that the
look-up-table address register is set to 0x0).
R[0]→G[0]→B[0]→(LUTADDR incremented)→R[1]→G[1]→B[1]
The data set in the look-up tables can be read out by reading this register. When read, the 4 low-order bits of the
register are set to 0x0. The data written to this register are set in the look-up tables. Note, however, that no data is
set in the look-up tables until data is written to the register three times, in order of red, green, and blue. Write 0x0
to the 4 low-order bits of the register.
At i nitial reset, LUTDT is set to "0x0".
GPIO2C: GPIO2 configuration (D2) / GPIO configuration register (0x39FFF8)
GPIO1C: GPIO1 configuration (D1) / GPIO configuration register (0x3 9FFF8 )
GPIO0C: GPIO0 configuration (D0) / GPIO configuration register (0x39FFF8)
Selects the input/output modes of the GPIO[2:0] pins.
Write "1": Output mode
Write "0": Input mode
Read: Valid
Setting GP IOxC t o "1" di rects GPIOx for output, and se tting GPI Ox C to "0" directs GPIOx for input.
The GPIO [2:0] pins are shared with the bus release pins listed below. These pins can only be used as GPIO[2:0]
pins when LCDCEN (D5/0x39FFE3) = "1" and BREQEN (D2/0x39FFFD) = "0".
GPIO2: #BUSGET/P31
GPIO1: #B USACK/P35
GPIO0: #BUSREQ/P34
At i nitial reset, GPIOxC is set to "0" (input mode).
VII LCD CONTROLLER BLOC K: LCD CONTROLLER
S1C33L03 FUNCTION PART EPSON B-VII-2-39
A-1
B-VII
LCDC
GPIO2D: GPIO2 data (D2) / GPIO status/control register (0x39FFF9)
GPIO1D: GPIO1 data (D1) / GPIO status/control register (0x39FFF9)
GPIO0D: GPIO0 data (D0) / GPIO status/control register (0x39FFF9)
Input/output data for GPIO[2:0] pins.
In output mode
Write "1": High level
Write "0": Low level
Read: Valid
In input mode
Read "1": High level
Read "0": Low level
Write: Invalid
When GPIOx is set as the output mode, writing "1" to GPIOxD drives the GPIOx pin high, and writing "0" drives
the GPIOx pin low. In input mode, the value "1" is read from GPIOxD when the input-voltage level on the GPIOx
pin is high, and th e value "0" is read when the input-voltage level is low.
At i nitial reset, GPIOxD is set to "0" (low).
GPO6D: GPO6 data (D6) / GPIO status/control register (0x39FFF9)
GPO5D: GPO5 data (D5) / GPIO status/control register (0x39FFF9)
GPO4D: GPO4 data (D4) / GPIO status/control register (0x39FFF9)
GPO3D: GPO3 data (D3) / GPIO status/control register (0x39FFF9)
Sets the data to be output from the GPO[6:3] pins.
Write "1": High level
Write "0": Low level
Read: Valid
Writing "1" to GPOxD drives the GPOx pin high, and writing "0" drives the GPOx pin low.
The G PO[6:3] pins are shared with the LCD signal output pi ns listed below . These pins can only be used for
general-purp ose output when a 4-b it LCD pan el is selected.
GPO6: FPDAT3
GPO5: FPDAT2
GPO4: FPDAT1
GPO3: FPDAT0
At i nitial reset, GPOxD is set to "0" (low).
SP1A[7:0]: Scratch pad (D[7:0]) / Scratch pad register (0x39FFFA)
This is a readable/writable 8-bit general-purpose register. It does not affect the operation of the chip, including the
LCD controller itself.
At i nitial reset, SP1A is set to "0x0".
PMODEN: Enable portr ait mode (D7) / Por tra it m od e regi st er (0x3 9F FFB )
Sw itches the dis play to portrait mode.
Write "1": Portrait mode
Write "0": Landscape (norma l) mod e
Read: Valid
Setting PMODEN to "1" places the LCD controller in a type of portrait mode selected by PMODSEL
(D6/0x39FFFB), producing a display suitable for a 90-degree-rotated LCD panel. Setting PMODEN to "0" selects
normal landscape mode.
At i nitial reset, PMODEN is set to "0" (landscape mode).
VII LCD CONTROLLER BLOC K: LCD CONTROL LER
B-VII-2-40 EPSON S1C33L03 FUNCTION PART
PMODSEL: Portrait mode select (D6) / Portrait mode register (0x39FFFB)
Selects a type of portrait m ode .
Write "1": Alternate portrait mode
Write "0": Default portrait mode
Read: Valid
Settin g PMODSEL to "1" selects alternate portrait mode, and setting PMODSEL to "0" selects default portrait
mode. When PMODEN (D7/0x39FFFB) is set to "1", d ata is displayed in the selected portrait mode. For details,
refer to "Portrait Mode".
At i nitial reset, PMODSEL is set to "0" (default portrait mode).
PMODCLK[1:0]: Por tra it m ode cloc k s elect (D[1 :0 ]) / P or tra it mod e regi st er (0x39FFF B)
Selects the clock used in portrait mode.
In alternate portrait mode, the MCLK clock used for display memory access must be twice as fast as the pixel clock,
PC LK. Therefore, clock settings differ between the al ter na te an d defa ult portrait mod es .
Table 2.26 Clock Settings for Default Portrait Mode
PMODCLK1 PMODCLK0 Pixel clock PCLK Memory clock MCLK
00 CLK CLK
01 CLK/2 CLK/2
10 CLK/4 CLK/4
11 CLK/8 CLK/8
Table 2.27 Clock Settings for Alternate Portrait Mode
PMODCLK1 PMODCLK0 Pixel clock PCLK Memory clock MCLK
00 CLK/2 CLK
01 CLK/2 CLK
10 CLK/4 CLK/2
11 CLK/8 CLK/4
CL K deno tes the clock for landscape mode (PCLK = MCLK), which is selected by LCLKSEL[2:0]
(D[2:0]/0x39FFF4).
At i nitial reset, PMODCLK is set to "0b00".
PMODLBC[7:0]: Line byte count (D[7:0]) / Line byte count register (0x39FFFC)
Sets the num ber of bytes equ ivalent to one line in portrait mode. For this line byte count, write the number of
horizontal pixels converted into the num ber of bytes available in bpp mo de. These horizontal pixels include the
num ber of pixels in a virtual portio n of the screen that i s not displayed on the LC D pan el.
At i nitial reset, PMODLBC is set to "0x0".
VRAMAR: VRAM area select (D7) / LCDC system control register (0x39FFFD)
Selects the area in which the display memory is located.
Write "1": Area 8 (or 14)
Write "0": Area 7 (or 13)
Read: Valid
Setting VR AMAR to "1" s elects are a 8 (whe n CEFUNC[1:0] (D[A:9]/0x48130) = "0b00 ") or a rea 14 (whe n
CEFUNC = "0b01"), and setting VRAMAR to "0" selects area 7 (when CEFUNC = "0b00") or area 13 (when
CEFUNC = "0b01").
At i nitial reset, VRAMAR is set to "0" (area 7).
VRAMWT[2:0]: VRAM wait control (D[6:4]) / LCDC system control register (0x39FFFD)
Sets the number of wait cycles (0–7) for display memory access.
This setting is effective only when SRAM is used for the display memory. Settings of this register are ignored
when SDRAM is used. The number of wait cycles set here is inserted when the LCD controller accesses the
display me m ory. It does not affect display-memory access by the CPU. In that case, the number of wait cycles set
for the BCU is inserted.
At i nitial reset, VRAMWT is set to "0x0".
VII LCD CONTROLLER BLOC K: LCD CONTROLLER
S1C33L03 FUNCTION PART EPSON B-VII-2-41
A-1
B-VII
LCDC
EDMAEN: Enable external DMA (D3) / L CD C sys tem c on tro l regi st er (0x3 9FFF D )
Enables/di sables DMA requests from external devices while the LCD controller is in use.
Write "1": Enabled
Write "0": Disabled
Read: Valid
Setting EDMAEN to "1" enables DMA requests from other external devices even while the LCD controller is in
use. During a DMA transfer by one of these external devices, the LCD controller cannot access the display
memory and therefore cannot update the display. Setting EDMAEN to "0" disables DMA requests from external
devices only wh ile the LCD controller is in use (LCDCEN = "1").
At i nitial reset, EDMAEN is set to "0" (disabled).
BREQEN: Enable external bus reques t (D2) / LCDC system control register ( 0x39 FFFD)
Enabl es/disables bus release requests from external devices while the LCD controller is in use.
Write "1": Enabled
Write "0": Disabled
Read: Valid
Setting BREQEN to "1" enables bus release requests from other external devices even while the LCD controller is
in use. While the bus is being used by one of these external devices, the LCD controller cannot access the display
memory and therefore cannot update the display. Setting BREQEN to "0" disables bus release requests from
external devices only while the LCD controller is in use (LCDCEN = "1").
At i nitial reset, BREQEN is set to "0" (disabled).
LCDCST: A0/BSL select (D1) / LCDC system control register (0x39FFFD)
Selects the display memory (SRAM) interface method.
Write "1": BSL
Write "0": A0
Read: Valid
This setting is only effective when SRAM is used for the display memory.
Set the same value here as set in SBUSST (D3/0x4812E) for the BCU. When SDRAM is used, the settings of this
register are ignored.
At i nitial reset, LCDCST is set to "0" (A0).
LCDCEC: Big/Little endian select (D0) / LCDC system control r egiste r (0x39FFFD)
Selects the LCD controller’s access format (little or big endian).
Write "1": Big endian
Write "0": Little endian
Read: Valid
Setting LCDCEC to "1" causes the LCD controller to be accessed in big endian format, and setting LCDCEC to
"0" causes it to be accessed in little endian format. Set the same value here as set in A6EC (D1/0x48132) for area 6.
At initial reset, LCDCEC is set to "0" (little endian).
VII LCD CONTROLLER BLOC K: LCD CONTROL LER
B-VII-2-42 EPSON S1C33L03 FUNCTION PART
Pr ogramming Notes
(1) When the chip is set in HALT2 or SLEEP mode after the LCD controller is set in power-save mode, it is
necessary to wait until all LCD signals are turned off by the controller’s power-down sequence (by default, a
one-frame period). If the chip is placed in HALT2 or SLEEP mode while LCD signals are being output, the
LC D panel ma y be dam age d due to stoppage of the clock.
(2) When LPWREN (D4)/LCDC mode register 2 (0x39FFE3) is used to control the LCDPWR output, be careful
to ensure that LCD signals are not turned off while the power to the LCD panel remains on. During a power-
dow n state in particular, allow a sufficient wait time, after dropping the LCDPWR output low for LCD
pow er- dischargin g before turning the LCD signals off.
(3) I/O-area addresses 0x39FFFE and 0x39FFFF are assigned for use in inspection of the LCD controller.
Writing data to these addresses may damage the LCD controller and the LCD panel to which the LCD
controller is connected. Therefore, make sure data is never written to that location.
Precautions on Using ICD33
Follow the precautions described below wh en us ing the ICD33 (S5U1C 3300 0H ) for debug ging an app lication,
which uses this L CD cont ro lle r.
1. W hen #WAIT is enabled, do not dum p (including displays using the [Memory] window) or set t h e contents
from/to the LCDC register area (0x39FFE0–0x39FFFF). This operati on inserts wa it states permanent ly and
the debugger hangs. The same problem results when the target program accesses the LCDC register area
during execution.
When ICD33 is used for deb ugging, be sure to disable #W A IT (D0/0x4812E = "0") before the LCDC register
area is accessed in a debugging operation or from the target program.
2. W hen the tar get program stops e xecution by a break factor duri ng de bug ging with the ICD 33, the LCD
display goes off until t he pr ogram resumes execution.
Therefore, do not use the ICD3 3 for deb ugging a target system, which uses an EPSON MLS driver for
driving the LCD panel.
In this case, use the MON33 (S5U1C330M1D1 ) for debugging, since t he LCD display does not go off in a
break state so it allows debugging.
VII LCD CONTROLLER BLOC K: LCD CONTROLLER
S1C33L03 FUNCTION PART EPSON B-VII-2-43
A-1
B-VII
LCDC
Examples of LCD Controller Setting Program
(Wa it s ign al = ON)
;******************
;C33L03 ASM
;******************
;===================================
.org 0x0
.half 0x0008
.half 0x00c0
.org 0x0008
;---------------------------
;initial
;---------------------------
xld.w %r1, 0x1fff ;stack poiter
ld.w %sp, %r1
xld.w %r5, 0x48126 ;ROM access speed
xld.w %r1, 0x0
ld.b [% r5], %r1
xld.w %r5, 0x48128 ;Ram wait cycle 0 access speed
xld.w %r1, 0x00
ld.b [% r5], %r1
xld.w %r5, 0x4812a ;set area6 wait cycle
ld.h [% r5], %r1
xld.w %r5, 0x4812e ;set bus control register wait enable , a0 mode
xld.w %r1, 0x05
ld.b [% r5], %r1
xld.w %r5,0x48132 ;set area6 access control register
xld.w %r1,0xff00
ld.h [%r5],%r1
xld.w %r5,0x4813a ;select bclk output
xld.w %r1,0x01
ld.b [%r5],%r1
xld.w %r1, 0x39ffe3 ;lcd enable
xld.w %r2, 0x20
ld.b [% r1], %r2
xld.w %r5, 0x402dc ;set busack,req,wait
xld.w %r1, 0x30
ld.b [% r5], %r1
;******************************************************
;**
;**test color 4/8bit 1/2/4/8 bpp ,video invert,
;** segment ,common landscape mode/virtual image
;** display blank
;******************************************************
;set landscape mode
;***********************************
;color ,8bit , 8bpp,segment 32 x 3
;***********************************
xld.w %r1, 0x39ffe1 ; write-- set mono,4-bit
xld.w %r2, 0x04
ld.b [% r1], %r2
xld.w %r1, 0x39ffe2 ; write-- set 2bpp,no high performance,disable display bland
xld.w %r2, 0x40 ; no invert video
ld.b [% r1], %r2
xl d.w %r 1, 0x39ffe4 ; set se gment 32
xld.w %r2, 0x01
ld.b [% r1], %r2
xl d.w %r 1, 0x39ffe5 ; set co mmon
xld.w %r2, 0x01
ld.b [%r1], %r2
xl d.w %r 1, 0x39ffe8 ; set Ho rizontal Non-display pe riod
xld.w %r2, 0x01
VII LCD CONTROLLER BLOC K: LCD CONTROL LER
B-VII-2-44 EPSON S1C33L03 FUNCTION PART
ld.b [% r1], %r2
xld.w %r1, 0x39ffea ; se t Vertical Non-dis played Period
xld.w %r2, 0x01
ld.b [% r1], %r2
xld.w %r1, 0x39ffec ; set S1 start address aaaa
xld.w %r2, 0x0000
ld.h [% r1], %r2
xld.w %r1, 0x39ffee ; set S2 start address 5555
xld.w %r2, 0x0000
ld.h [% r1], %r2
xl d.w %r1, 0x39 fff1 ; set Memory addr ess offset 00
xld.w %r2, 0x00
ld.b [% r1], %r2
xld.w %r1, 0x39fff2 ; set S1 Vertical size 0x01df lsb
xld.w %r2, 0x0100
ld.h [% r1], %r2
xld.w %r1, 0x39fff4 ; se t clk ->osc3 , fifo ->0
xld.w %r2, 0x04
ld.b [% r1], %r2
;-----------------------------------
xld.w %r1, 0x39ffe3 ; LC D power on
xld.w %r2, 0x23
ld.b [% r1], %r2
;******************************************************
;** Initialize the LUT
;******************************************************
xld.w %r1, 0x39fff5 ; set lut addr ess
xld.w %r2, 0x39fff7
xld.w %r3, 0x00
ld.b [%r1], %r3
ld.b [% r2], %r3
ld.b [% r2], %r3
ld.b [% r2], %r3
S1C33L03 FUNCTION PART
Appendix I/O MAP
APPENDIX: I/O MAP
S1C33L03 FUNCTION PART EPSON B-APPENDIX-1
A-1
B-ap
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
P8TPCK5
P8TPCK4
D7–2
D1
D0
reserved
8-bit timer 5 clock selection
8-bit timer 4 clock selection
–
0
0
–
R/W
R/W
0 when being read.
θ: selected by
Prescaler clock select
register (0x40181)
0040140
(B) 1θ/1 0 Divided clk.
1θ/1 0 Divided clk.
8-bit timer 4/5
clock select
register
–
1On 0OffP8TON5
P8TS52
P8TS51
P8TS50
P8TON4
P8TS42
P8TS41
P8TS40
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 5 clock control
8-bit timer 5
clock division ratio selection
8-bit timer 4 clock control
8-bit timer 4
clock division ratio selection
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
θ: selected by
Prescaler clock select
register (0x40181)
8-bit timer 5 can
generate the clock for
the serial I/F Ch.3.
θ: selected by
Prescaler clock select
register (0x40181)
8-bit timer 4 can
generate the clock for
the serial I/F Ch.2.
0040145
(B) 1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
θ/256
θ/128
θ/64
θ/32
θ/16
θ/8
θ/4
θ/2
1On 0Off
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
θ/4096
θ/2048
θ/64
θ/32
θ/16
θ/8
θ/4
θ/2
8-bit timer 4/5
clock control
register
––
P8TPCK3
P8TPCK2
P8TPCK1
P8TPCK0
D7–4
D3
D2
D1
D0
reserved
8-bit timer 3 clock selection
8-bit timer 2 clock selection
8-bit timer 1 clock selection
8-bit timer 0 clock selection
–
0
0
0
0
–
R/W
R/W
R/W
R/W
0 when being read.
θ: selected by
Prescaler clock select
register (0x40181)
0040146
(B) 1θ/1 0 Divided clk.
1θ/1 0 Divided clk.
1θ/1 0 Divided clk.
1θ/1 0 Divided clk.
8-bit timer
clock select
register
––
P16TON0
P16TS02
P16TS01
P16TS00
D7–4
D3
D2
D1
D0
reserved
16-bit timer 0 clock control
16-bit timer 0
clock division ratio selection
–
0
0
0
0
–
R/W
R/W
0 when being read.
θ: selected by
Prescaler clock select
register (0x40181)
16-bit timer 0 can be
used as a watchdog
timer.
0040147
(B) 1On 0Off
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
P16TS0[2:0] Division ratio
θ/4096
θ/1024
θ/256
θ/64
θ/16
θ/4
θ/2
θ/1
16-bit timer 0
clock control
register
––
P16TON1
P16TS12
P16TS11
P16TS10
D7–4
D3
D2
D1
D0
reserved
16-bit timer 1 clock control
16-bit timer 1
clock division ratio selection
–
0
0
0
0
–
R/W
R/W
0 when being read.
θ: selected by
Prescaler clock select
register (0x40181)
0040148
(B) 1On 0Off
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
P16TS1[2:0] Division ratio
θ/4096
θ/1024
θ/256
θ/64
θ/16
θ/4
θ/2
θ/1
16-bit timer 1
clock control
register
––
P16TON2
P16TS22
P16TS21
P16TS20
D7–4
D3
D2
D1
D0
reserved
16-bit timer 2 clock control
16-bit timer 2
clock division ratio selection
–
0
0
0
0
–
R/W
R/W
0 when being read.
θ: selected by
Prescaler clock select
register (0x40181)
0040149
(B) 1On 0Off
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
P16TS2[2:0] Division ratio
θ/4096
θ/1024
θ/256
θ/64
θ/16
θ/4
θ/2
θ/1
16-bit timer 2
clock control
register
(B) in [Address] indicates an 8-bit register and (HW) indicates a 16-bit register.
The meaning of the symbols described in [Init.] are listed below:
0, 1: Initial values that are set at initial reset.
(However, the registers for the bus and input/output ports are not initialized at hot start.)
X: Not initialized at initial reset.
–: N ot s et in the circuit.
APPENDIX: I/O MAP
B-APPENDIX-2 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
––
P16TON3
P16TS32
P16TS31
P16TS30
D7–4
D3
D2
D1
D0
reserved
16-bit timer 3 clock control
16-bit timer 3
clock division ratio selection
–
0
0
0
0
–
R/W
R/W
0 when being read.
θ: selected by
Prescaler clock select
register (0x40181)
004014A
(B) 1 On 0 Off
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
P16TS3[2:0] Division ratio
θ/4096
θ/1024
θ/256
θ/64
θ/16
θ/4
θ/2
θ/1
16-bit timer 3
clock control
register
––
P16TON4
P16TS42
P16TS41
P16TS40
D7–4
D3
D2
D1
D0
reserved
16-bit timer 4 clock control
16-bit timer 4
clock division ratio selection
–
0
0
0
0
–
R/W
R/W
0 when being read.
θ: selected by
Prescaler clock select
register (0x40181)
004014B
(B) 1 On 0 Off
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
P16TS4[2:0] Division ratio
θ/4096
θ/1024
θ/256
θ/64
θ/16
θ/4
θ/2
θ/1
16-bit timer 4
clock control
register
––
P16TON5
P16TS52
P16TS51
P16TS50
D7–4
D3
D2
D1
D0
reserved
16-bit timer 5 clock control
16-bit timer 5
clock division ratio selection
–
0
0
0
0
–
R/W
R/W
0 when being read.
θ: selected by
Prescaler clock select
register (0x40181)
004014C
(B) 1 On 0 Off
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
P16TS5[2:0] Division ratio
θ/4096
θ/1024
θ/256
θ/64
θ/16
θ/4
θ/2
θ/1
16-bit timer 5
clock control
register
1 On 0 OffP8TON1
P8TS12
P8TS11
P8TS10
P8TON0
P8TS02
P8TS01
P8TS00
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 1 clock control
8-bit timer 1
clock division ratio selection
8-bit timer 0 clock control
8-bit timer 0
clock division ratio selection
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
θ: selected by
Prescaler clock select
register (0x40181)
8-bit timer 1 can
generate the OSC3
oscillation-stabilize
waiting period.
θ: selected by
Prescaler clock select
register (0x40181)
8-bit timer 0 can
generate the DRAM
refresh clock.
004014D
(B) 1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
P8TS1[2:0] Division ratio
θ/4096
θ/2048
θ/1024
θ/512
θ/256
θ/128
θ/64
θ/32
1 On 0 Off
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
P8TS0[2:0] Division ratio
θ/256
θ/128
θ/64
θ/32
θ/16
θ/8
θ/4
θ/2
8-bit timer 0/1
clock control
register
APPENDIX: I/O MAP
S1C33L03 FUNCTION PART EPSON B-APPENDIX-3
A-1
B-ap
NameAddressRegister name Bit Function Setting Init. R/W Remarks
1 On 0 OffP8TON3
P8TS32
P8TS31
P8TS30
P8TON2
P8TS22
P8TS21
P8TS20
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 3 clock control
8-bit timer 3
clock division ratio selection
8-bit timer 2 clock control
8-bit timer 2
clock division ratio selection
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
θ: selected by
Prescaler clock select
register (0x40181)
8-bit timer 3 can
generate the clock for
the serial I/F Ch.1.
θ: selected by
Prescaler clock select
register (0x40181)
8-bit timer 2 can
generate the clock for
the serial I/F Ch.0.
004014E
(B) 1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
P8TS3[2:0] Division ratio
θ/256
θ/128
θ/64
θ/32
θ/16
θ/8
θ/4
θ/2
1 On 0 Off
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
P8TS2[2:0] Division ratio
θ/4096
θ/2048
θ/64
θ/32
θ/16
θ/8
θ/4
θ/2
8-bit timer 2/3
clock control
register
–
PSONAD
PSAD2
PSAD1
PSAD0
D7–4
D3
D2
D1
D0
reserved
A/D converter clock control
A/D converter clock division ratio
selection
–
0
0
0
0
–
R/W
R/W
0 when being read.
θ: selected by
Prescaler clock select
register (0x40181)
004014F
(B)
A/D clock
control register
1 On 0 Off
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
P8TS0[2:0] Division ratio
θ/256
θ/128
θ/64
θ/32
θ/16
θ/8
θ/4
θ/2
–
–
TCRST
TCRUN
D7–2
D1
D0
reserved
Clock timer reset
Clock timer Run/Stop control
–
X
X
–
W
R/W
0 when being read.
0 when being read.
0040151
(B) 1 Reset 0 Invalid
1 Run 0 Stop
–Clock timer
Run/Stop
register
TCISE2
TCISE1
TCISE0
TCASE2
TCASE1
TCASE0
TCIF
TCAF
D7
D6
D5
D4
D3
D2
D1
D0
Clock timer interrupt factor
selection
Clock timer alarm factor selection
Interrupt factor generation flag
Alarm factor generation flag
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W Reset by writing 1.
Reset by writing 1.
0040152
(B)
1 Generated 0
Not generated
1 Generated 0
Not generated
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
TCISE[2:0] Interrupt factor
None
Day
Hour
Minute
1 Hz
2 Hz
8 Hz
32 Hz
1
X
X
0
X
1
X
0
X
X
1
0
TCASE[2:0] Alarm factor
Day
Hour
Minute
None
Clock timer
interrupt
control register
TCD7
TCD6
TCD5
TCD4
TCD3
TCD2
TCD1
TCD0
D7
D6
D5
D4
D3
D2
D1
D0
Clock timer data 1 Hz
Clock timer data 2 Hz
Clock timer data 4 Hz
Clock timer data 8 Hz
Clock timer data 16 Hz
Clock timer data 32 Hz
Clock timer data 64 Hz
Clock timer data 128 Hz
X
X
X
X
X
X
X
X
R
R
R
R
R
R
R
R
0040153
(B) 1 High 0 Low
1 High 0 Low
1 High 0 Low
1 High 0 Low
1 High 0 Low
1 High 0 Low
1 High 0 Low
1 High 0 Low
Clock timer
divider register
–
TCMD5
TCMD4
TCMD3
TCMD2
TCMD1
TCMD0
D7–6
D5
D4
D3
D2
D1
D0
reserved
Clock timer second counter data
TCMD5 = MSB
TCMD0 = LSB
–
X
X
X
X
X
X
–
R0 when being read.0040154
(B) –
0 to 59 seconds
Clock timer
second
register
APPENDIX: I/O MAP
B-APPENDIX-4 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
TCHD5
TCHD4
TCHD3
TCHD2
TCHD1
TCHD0
D7–6
D5
D4
D3
D2
D1
D0
reserved
Clock timer minute counter data
TCHD5 = MSB
TCHD0 = LSB
–
X
X
X
X
X
X
–
R/W 0 when being read.0040155
(B) –
0 to 59 minutes
Clock timer
minute register
0 to 23 hours
–
TCDD4
TCDD3
TCDD2
TCDD1
TCDD0
D7–5
D4
D3
D2
D1
D0
reserved
Clock timer hour counter data
TCDD4 = MSB
TCDD0 = LSB
–
X
X
X
X
X
–
R/W 0 when being read.0040156
(B)
Clock timer
hour register –
0 to 65535 days
(low-order 8 bits)
TCND7
TCND6
TCND5
TCND4
TCND3
TCND2
TCND1
TCND0
D7
D6
D5
D4
D3
D2
D1
D0
Clock timer day counter data
(low-order 8 bits)
TCND0 = LSB
X
X
X
X
X
X
X
X
R/W0040157
(B)
Clock timer
day (low-order)
register
0 to 65535 days
(high-order 8 bits) X
X
X
X
X
X
X
X
R/WTCND15
TCND14
TCND13
TCND12
TCND11
TCND10
TCND9
TCND8
D7
D6
D5
D4
D3
D2
D1
D0
Clock timer day counter data
(high-order 8 bits)
TCND15 = MSB
0040158
(B)
Clock timer
day (high-
order) register
0 to 59 minutes
(Note) Can be set within 0–63.
–
TCCH5
TCCH4
TCCH3
TCCH2
TCCH1
TCCH0
D7–6
D5
D4
D3
D2
D1
D0
reserved
Clock timer minute comparison
data
TCCH5 = MSB
TCCH0 = LSB
–
X
X
X
X
X
X
–
R/W 0 when being read.0040159
(B) –Clock timer
minute
comparison
register
0 to 23 hours
(Note) Can be set within 0–31.
–
TCCD4
TCCD3
TCCD2
TCCD1
TCCD0
D7–5
D4
D3
D2
D1
D0
reserved
Clock timer hour comparison data
TCCD4 = MSB
TCCD0 = LSB
–
X
X
X
X
X
–
R/W 0 when being read.004015A
(B) –Clock timer
hour
comparison
register
0 to 31 days
–
TCCN4
TCCN3
TCCN2
TCCN1
TCCN0
D7–5
D4
D3
D2
D1
D0
reserved
Clock timer day comparison data
TCCN4 = MSB
TCCN0 = LSB
–
X
X
X
X
X
–
R/W 0 when being read.
Compared with
TCND[4:0].
004015B
(B) –Clock timer
day
comparison
register
APPENDIX: I/O MAP
S1C33L03 FUNCTION PART EPSON B-APPENDIX-5
A-1
B-ap
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
PTOUT0
PSET0
PTRUN0
D7–3
D2
D1
D0
reserved
8-bit timer 0 clock output control
8-bit timer 0 preset
8-bit timer 0 Run/Stop control
–
0
–
0
–
R/W
W
R/W
0 when being read.
0 when being read.
0040160
(B) –
1 On 0 Off
1 Preset 0 Invalid
1 Run 0 Stop
8-bit timer 0
control register
0 to 255RLD07
RLD06
RLD05
RLD04
RLD03
RLD02
RLD01
RLD00
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 0 reload data
RLD07 = MSB
RLD00 = LSB
X
X
X
X
X
X
X
X
R/W0040161
(B)
8-bit timer 0
reload data
register
0 to 255PTD07
PTD06
PTD05
PTD04
PTD03
PTD02
PTD01
PTD00
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 0 counter data
PTD07 = MSB
PTD00 = LSB
X
X
X
X
X
X
X
X
R0040162
(B)
8-bit timer 0
counter data
register
–
PTOUT1
PSET1
PTRUN1
D7–3
D2
D1
D0
reserved
8-bit timer 1 clock output control
8-bit timer 1 preset
8-bit timer 1 Run/Stop control
–
0
–
0
–
R/W
W
R/W
0 when being read.
0 when being read.
0040164
(B) –
1 On 0 Off
1 Preset 0 Invalid
1 Run 0 Stop
8-bit timer 1
control register
0 to 255RLD17
RLD16
RLD15
RLD14
RLD13
RLD12
RLD11
RLD10
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 1 reload data
RLD17 = MSB
RLD10 = LSB
X
X
X
X
X
X
X
X
R/W0040165
(B)
8-bit timer 1
reload data
register
0 to 255PTD17
PTD16
PTD15
PTD14
PTD13
PTD12
PTD11
PTD10
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 1 counter data
PTD17 = MSB
PTD10 = LSB
X
X
X
X
X
X
X
X
R0040166
(B)
8-bit timer 1
counter data
register
–
PTOUT2
PSET2
PTRUN2
D7–3
D2
D1
D0
reserved
8-bit timer 2 clock output control
8-bit timer 2 preset
8-bit timer 2 Run/Stop control
–
0
–
0
–
R/W
W
R/W
0 when being read.
0 when being read.
0040168
(B) –
1 On 0 Off
1 Preset 0 Invalid
1 Run 0 Stop
8-bit timer 2
control register
0 to 255RLD27
RLD26
RLD25
RLD24
RLD23
RLD22
RLD21
RLD20
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 2 reload data
RLD27 = MSB
RLD20 = LSB
X
X
X
X
X
X
X
X
R/W0040169
(B)
8-bit timer 2
reload data
register
0 to 255PTD27
PTD26
PTD25
PTD24
PTD23
PTD22
PTD21
PTD20
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 2 counter data
PTD27 = MSB
PTD20 = LSB
X
X
X
X
X
X
X
X
R004016A
(B)
8-bit timer 2
counter data
register
APPENDIX: I/O MAP
B-APPENDIX-6 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
PTOUT3
PSET3
PTRUN3
D7–3
D2
D1
D0
reserved
8-bit timer 3 clock output control
8-bit timer 3 preset
8-bit timer 3 Run/Stop control
–
0
–
0
–
R/W
W
R/W
0 when being read.
0 when being read.
004016C
(B) –
1 On 0 Off
1 Preset 0 Invalid
1 Run 0 Stop
8-bit timer 3
control register
0 to 255RLD37
RLD36
RLD35
RLD34
RLD33
RLD32
RLD31
RLD30
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 3 reload data
RLD37 = MSB
RLD30 = LSB
X
X
X
X
X
X
X
X
R/W004016D
(B)
8-bit timer 3
reload data
register
0 to 255PTD37
PTD36
PTD35
PTD34
PTD33
PTD32
PTD31
PTD30
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 3 counter data
PTD37 = MSB
PTD30 = LSB
X
X
X
X
X
X
X
X
R004016E
(B)
8-bit timer 3
counter data
register
–
PTOUT4
PSET4
PTRUN4
D7–3
D2
D1
D0
reserved
8-bit timer 4 clock output control
8-bit timer 4 preset
8-bit timer 4 Run/Stop control
–
0
–
0
–
R/W
W
R/W
0 when being read.
0 when being read.
0040174
(B) –
1 On 0 Off
1 Preset 0 Invalid
1 Run 0 Stop
8-bit timer 4
control register
0 to 255RLD47
RLD46
RLD45
RLD44
RLD43
RLD42
RLD41
RLD40
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 4 reload data
RLD47 = MSB
RLD40 = LSB
X
X
X
X
X
X
X
X
R/W0040175
(B)
8-bit timer 4
reload data
register
0 to 255PTD47
PTD46
PTD45
PTD44
PTD43
PTD42
PTD41
PTD40
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 4 counter data
PTD47 = MSB
PTD40 = LSB
X
X
X
X
X
X
X
X
R0040176
(B)
8-bit timer 4
counter data
register
–
PTOUT5
PSET5
PTRUN5
D7–3
D2
D1
D0
reserved
8-bit timer 5 clock output control
8-bit timer 5 preset
8-bit timer 5 Run/Stop control
–
0
–
0
–
R/W
W
R/W
0 when being read.
0 when being read.
0040178
(B) –
1 On 0 Off
1 Preset 0 Invalid
1 Run 0 Stop
8-bit timer 5
control register
0 to 255RLD57
RLD56
RLD55
RLD54
RLD53
RLD52
RLD51
RLD50
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 5 reload data
RLD57 = MSB
RLD50 = LSB
X
X
X
X
X
X
X
X
R/W0040179
(B)
8-bit timer 5
reload data
register
0 to 255PTD57
PTD56
PTD55
PTD54
PTD53
PTD52
PTD51
PTD50
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 5 counter data
PTD57 = MSB
PTD50 = LSB
X
X
X
X
X
X
X
X
R004017A
(B)
8-bit timer 5
counter data
register
APPENDIX: I/O MAP
S1C33L03 FUNCTION PART EPSON B-APPENDIX-7
A-1
B-ap
NameAddressRegister name Bit Function Setting Init. R/W Remarks
WRWD
–
D7
D6–0 EWD write protection
–0
–R/W
–0 when being read.
0040170
(B) –
1
Write enabled
0
Write-protect
Watchdog
timer write-
protect register
–
–
–
EWD
–
D7–2
D1
D0
–
Watchdog timer enable
–
–
0
–
–
R/W
–
0 when being read.
0 when being read.
0040171
(B) 1
NMI enabled
0
NMI disabled
Watchdog
timer enable
register
APPENDIX: I/O MAP
B-APPENDIX-8 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
CLKDT1
CLKDT0
PSCON
–
CLKCHG
SOSC3
SOSC1
D7
D6
D5
D4–3
D2
D1
D0
System clock division ratio
selection
Prescaler On/Off control
reserved
CPU operating clock switch
High-speed (OSC3) oscillation On/Off
Low-speed (OSC1) oscillation On/Off
1 On 0 Off
1 OSC3 0 OSC1
1 On 0 Off
1 On 0 Off
0
0
1
0
1
1
1
R/W
R/W
–
R/W
R/W
R/W
Writing 1 not allowed.
0040180
(B) 1
1
0
0
1
0
1
0
CLKDT[1:0] Division ratio
1/8
1/4
1/2
1/1
–
Power control
register
–
PSCDT0
D7–1
D0 reserved
Prescaler clock selection 0
0–
R/W
0040181
(B) –Prescaler clock
select register 1 OSC1 0 OSC3/PLL
–
HLT2OP
8T1ON
–
PF1ON
D7–4
D3
D2
D1
D0
–
HALT clock option
OSC3-stabilize waiting function
reserved
OSC1 external output control
–
0
1
0
0
–
R/W
R/W
–
R/W
0 when being read.
Do not write 1.
0040190
(B) 1 On 0 Off
1 Off 0 On
1 On 0 Off
–
–
Clock option
register
Writing 10010110 (0x96)
removes the write protection of
the power control register
(0x40180) and the clock option
register (0x40190).
Writing another value set the
write protection.
CLGP7
CLGP6
CLGP5
CLGP4
CLGP3
CLGP2
CLGP1
CLGP0
D7
D6
D5
D4
D3
D2
D1
D0
Power control register protect flag 0
0
0
0
0
0
0
0
R/W004019E
(B)
Power control
protect register
APPENDIX: I/O MAP
S1C33L03 FUNCTION PART EPSON B-APPENDIX-9
A-1
B-ap
NameAddressRegister name Bit Function Setting Init. R/W Remarks
0x0 to 0xFF(0x7F)TXD07
TXD06
TXD05
TXD04
TXD03
TXD02
TXD01
TXD00
D7
D6
D5
D4
D3
D2
D1
D0
Serial I/F Ch.0 transmit data
TXD07(06) = MSB
TXD00 = LSB
X
X
X
X
X
X
X
X
R/W 7-bit asynchronous
mode does not use
TXD07.
00401E0
(B)
Serial I/F Ch.0
transmit data
register
0x0 to 0xFF(0x7F)RXD07
RXD06
RXD05
RXD04
RXD03
RXD02
RXD01
RXD00
D7
D6
D5
D4
D3
D2
D1
D0
Serial I/F Ch.0 receive data
RXD07(06) = MSB
RXD00 = LSB
X
X
X
X
X
X
X
X
R 7-bit asynchronous
mode does not use
RXD07 (fixed at 0).
00401E1
(B)
Serial I/F Ch.0
receive data
register
–
TEND0
FER0
PER0
OER0
TDBE0
RDBF0
D7–6
D5
D4
D3
D2
D1
D0
–
Ch.0 transmit-completion flag
Ch.0 flaming error flag
Ch.0 parity error flag
Ch.0 overrun error flag
Ch.0 transmit data buffer empty
Ch.0 receive data buffer full
–
0
0
0
0
1
0
–
R
R/W
R/W
R/W
R
R
0 when being read.
Reset by writing 0.
Reset by writing 0.
Reset by writing 0.
00401E2
(B) –
1 Error 0 Normal
1
Transmitting
0 End
1 Error 0 Normal
1 Error 0 Normal
1 Empty 0 Buffer full
1 Buffer full 0 Empty
Serial I/F Ch.0
status register
TXEN0
RXEN0
EPR0
PMD0
STPB0
SSCK0
SMD01
SMD00
D7
D6
D5
D4
D3
D2
D1
D0
Ch.0 transmit enable
Ch.0 receive enable
Ch.0 parity enable
Ch.0 parity mode selection
Ch.0 stop bit selection
Ch.0 input clock selection
Ch.0 transfer mode selection 1
1
0
0
1
0
1
0
SMD0[1:0] Transfer mode
8-bit asynchronous
7-bit asynchronous
Clock sync. Slave
Clock sync. Master
0
0
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Valid only in
asynchronous mode.
00401E3
(B) 1 Enabled 0 Disabled
1 Enabled 0 Disabled
1 With parity 0 No parity
1 Odd 0 Even
1 2 bits 0 1 bit
1 #SCLK0 0
Internal clock
Serial I/F Ch.0
control register
–
DIVMD0
IRTL0
IRRL0
IRMD01
IRMD00
D7–5
D4
D3
D2
D1
D0
–
Ch.0 async. clock division ratio
Ch.0 IrDA I/F output logic inversion
Ch.0 IrDA I/F input logic inversion
Ch.0 interface mode selection 1
1
0
0
1
0
1
0
IRMD0[1:0]
–
I/F mode
reserved
IrDA 1.0
reserved
General I/F
–
X
X
X
X
X
–
R/W
R/W
R/W
R/W
0 when being read.
Valid only in
asynchronous mode.
00401E4
(B) 1 1/8 0 1/16
1 Inverted 0 Direct
1 Inverted 0 Direct
Serial I/F Ch.0
IrDA register
APPENDIX: I/O MAP
B-APPENDIX-10 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
0x0 to 0xFF(0x7F)TXD17
TXD16
TXD15
TXD14
TXD13
TXD12
TXD11
TXD10
D7
D6
D5
D4
D3
D2
D1
D0
Serial I/F Ch.1 transmit data
TXD17(16) = MSB
TXD10 = LSB
X
X
X
X
X
X
X
X
R/W 7-bit asynchronous
mode does not use
TXD17.
00401E5
(B)
Serial I/F Ch.1
transmit data
register
0x0 to 0xFF(0x7F)RXD17
RXD16
RXD15
RXD14
RXD13
RXD12
RXD11
RXD10
D7
D6
D5
D4
D3
D2
D1
D0
Serial I/F Ch.1 receive data
RXD17(16) = MSB
RXD10 = LSB
X
X
X
X
X
X
X
X
R 7-bit asynchronous
mode does not use
RXD17 (fixed at 0).
00401E6
(B)
Serial I/F Ch.1
receive data
register
–
TEND1
FER1
PER1
OER1
TDBE1
RDBF1
D7–6
D5
D4
D3
D2
D1
D0
–
Ch.1 transmit-completion flag
Ch.1 flaming error flag
Ch.1 parity error flag
Ch.1 overrun error flag
Ch.1 transmit data buffer empty
Ch.1 receive data buffer full
–
0
0
0
0
1
0
–
R
R/W
R/W
R/W
R
R
0 when being read.
Reset by writing 0.
Reset by writing 0.
Reset by writing 0.
00401E7
(B) –
1 Error 0 Normal
1
Transmitting
0 End
1 Error 0 Normal
1 Error 0 Normal
1 Empty 0 Buffer full
1 Buffer full 0 Empty
Serial I/F Ch.1
status register
TXEN1
RXEN1
EPR1
PMD1
STPB1
SSCK1
SMD11
SMD10
D7
D6
D5
D4
D3
D2
D1
D0
Ch.1 transmit enable
Ch.1 receive enable
Ch.1 parity enable
Ch.1 parity mode selection
Ch.1 stop bit selection
Ch.1 input clock selection
Ch.1 transfer mode selection 1
1
0
0
1
0
1
0
SMD1[1:0] Transfer mode
8-bit asynchronous
7-bit asynchronous
Clock sync. Slave
Clock sync. Master
0
0
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Valid only in
asynchronous mode.
00401E8
(B)
Serial I/F Ch.1
control register 1 Enabled 0 Disabled
1 Enabled 0 Disabled
1 With parity 0 No parity
1 Odd 0 Even
1 2 bits 0 1 bit
1 #SCLK1 0
Internal clock
–
DIVMD1
IRTL1
IRRL1
IRMD11
IRMD10
D7–5
D4
D3
D2
D1
D0
–
Ch.1 async. clock division ratio
Ch.1 IrDA I/F output logic inversion
Ch.1 IrDA I/F input logic inversion
Ch.1 interface mode selection 1
1
0
0
1
0
1
0
IRMD1[1:0]
–
I/F mode
reserved
IrDA 1.0
reserved
General I/F
–
X
X
X
X
X
–
R/W
R/W
R/W
R/W
0 when being read.
Valid only in
asynchronous mode.
00401E9
(B) 1 1/8 0 1/16
1 Inverted 0 Direct
1 Inverted 0 Direct
Serial I/F Ch.1
IrDA register
0x0 to 0xFF(0x7F)TXD27
TXD26
TXD25
TXD24
TXD23
TXD22
TXD21
TXD20
D7
D6
D5
D4
D3
D2
D1
D0
Serial I/F Ch.2 transmit data
TXD27(26) = MSB
TXD20 = LSB
X
X
X
X
X
X
X
X
R/W00401F0
(B)
Serial I/F Ch.2
transmit data
register
0x0 to 0xFF(0x7F)RXD27
RXD26
RXD25
RXD24
RXD23
RXD22
RXD21
RXD20
D7
D6
D5
D4
D3
D2
D1
D0
Serial I/F Ch.2 receive data
RXD27(26) = MSB
RXD20 = LSB
X
X
X
X
X
X
X
X
R00401F1
(B)
Serial I/F Ch.2
receive data
register
–
TEND2
FER2
PER2
OER2
TDBE2
RDBF2
D7–6
D5
D4
D3
D2
D1
D0
reserved
Ch.2 transmit-completion flag
Ch.2 flaming error flag
Ch.2 parity error flag
Ch.2 overrun error flag
Ch.2 transmit data buffer empty
Ch.2 receive data buffer full
–
0
0
0
0
1
0
–
R
R/W
R/W
R/W
R
R
0 when being read.
Reset by writing 0.
Reset by writing 0.
Reset by writing 0.
00401F2
(B) –
1 Error 0 Normal
1
Transmitting
0 End
1 Error 0 Normal
1 Error 0 Normal
1 Empty 0 Buffer full
1 Buffer full 0 Empty
Serial I/F Ch.2
status register
APPENDIX: I/O MAP
S1C33L03 FUNCTION PART EPSON B-APPENDIX-11
A-1
B-ap
NameAddressRegister name Bit Function Setting Init. R/W Remarks
TXEN2
RXEN2
EPR2
PMD2
STPB2
SSCK2
SMD21
SMD20
D7
D6
D5
D4
D3
D2
D1
D0
Ch.2 transmit enable
Ch.2 receive enable
Ch.2 parity enable
Ch.2 parity mode selection
Ch.2 stop bit selection
Ch.2 input clock selection
Ch.2 transfer mode selection 1
1
0
0
1
0
1
0
SMD2[1:0] Transfer mode
8-bit asynchronous
7-bit asynchronous
Clock sync. Slave
Clock sync. Master
0
0
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Valid only in
asynchronous mode.
00401F3
(B)
Serial I/F Ch.2
control register 1 Enabled 0 Disabled
1 Enabled 0 Disabled
1 With parity 0 No parity
1 Odd 0 Even
1 2 bits 0 1 bit
1 #SCLK2 0
Internal clock
–
DIVMD2
IRTL2
IRRL2
IRMD21
IRMD20
D7–5
D4
D3
D2
D1
D0
reserved
Ch.2 async. clock division ratio
Ch.2 IrDA I/F output logic inversion
Ch.2 IrDA I/F input logic inversion
Ch.2 interface mode selection 1
1
0
0
1
0
1
0
IRMD2[1:0]
–
I/F mode
reserved
IrDA 1.0
reserved
General I/F
–
X
X
X
X
X
–
R/W
R/W
R/W
R/W
0 when being read.
Valid only in
asynchronous mode.
00401F4
(B) 1 1/8 0 1/16
1 Inverted 0 Direct
1 Inverted 0 Direct
Serial I/F Ch.2
IrDA register
0x0 to 0xFF(0x7F)TXD37
TXD36
TXD35
TXD34
TXD33
TXD32
TXD31
TXD30
D7
D6
D5
D4
D3
D2
D1
D0
Serial I/F Ch.3 transmit data
TXD37(36) = MSB
TXD30 = LSB
X
X
X
X
X
X
X
X
R/W00401F5
(B)
Serial I/F Ch.3
transmit data
register
0x0 to 0xFF(0x7F)RXD37
RXD36
RXD35
RXD34
RXD33
RXD32
RXD31
RXD30
D7
D6
D5
D4
D3
D2
D1
D0
Serial I/F Ch.3 receive data
RXD37(36) = MSB
RXD30 = LSB
X
X
X
X
X
X
X
X
R00401F6
(B)
Serial I/F Ch.3
receive data
register
–
TEND3
FER3
PER3
OER3
TDBE3
RDBF3
D7–6
D5
D4
D3
D2
D1
D0
reserved
Ch.3 transmit-completion flag
Ch.3 flaming error flag
Ch.3 parity error flag
Ch.3 overrun error flag
Ch.3 transmit data buffer empty
Ch.3 receive data buffer full
–
0
0
0
0
1
0
–
R
R/W
R/W
R/W
R
R
0 when being read.
Reset by writing 0.
Reset by writing 0.
Reset by writing 0.
00401F7
(B) –
1 Error 0 Normal
1
Transmitting
0 End
1 Error 0 Normal
1 Error 0 Normal
1 Empty 0 Buffer full
1 Buffer full 0 Empty
Serial I/F Ch.3
status register
TXEN3
RXEN3
EPR3
PMD3
STPB3
SSCK3
SMD31
SMD30
D7
D6
D5
D4
D3
D2
D1
D0
Ch.3 transmit enable
Ch.3 receive enable
Ch.3 parity enable
Ch.3 parity mode selection
Ch.3 stop bit selection
Ch.3 input clock selection
Ch.3 transfer mode selection 1
1
0
0
1
0
1
0
SMD3[1:0] Transfer mode
8-bit asynchronous
7-bit asynchronous
Clock sync. Slave
Clock sync. Master
0
0
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Valid only in
asynchronous mode.
00401F8
(B)
Serial I/F Ch.3
control register 1 Enabled 0 Disabled
1 Enabled 0 Disabled
1 With parity 0 No parity
1 Odd 0 Even
1 2 bits 0 1 bit
1 #SCLK3 0
Internal clock
–
DIVMD3
IRTL3
IRRL3
IRMD31
IRMD30
D7–5
D4
D3
D2
D1
D0
reserved
Ch.3 async. clock division ratio
Ch.3 IrDA I/F output logic inversion
Ch.3 IrDA I/F input logic inversion
Ch.3 interface mode selection 1
1
0
0
1
0
1
0
IRMD3[1:0]
–
I/F mode
reserved
IrDA 1.0
reserved
General I/F
–
X
X
X
X
X
–
R/W
R/W
R/W
R/W
0 when being read.
Valid only in
asynchronous mode.
00401F9
(B) 1 1/8 0 1/16
1 Inverted 0 Direct
1 Inverted 0 Direct
Serial I/F Ch.3
IrDA register
APPENDIX: I/O MAP
B-APPENDIX-12 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
D7
D6
D5
D4
D3
D2
D1
D0
A/D converted data
(low-order 8 bits)
ADD0 = LSB
0x0 to 0x3FF
(low-order 8 bits) 0
0
0
0
0
0
0
0
R0040240
(B)
A/D conversion
result (low-
order) register
0x0 to 0x3FF
(high-order 2 bits)
––
ADD9
ADD8
D7–2
D1
D0
–
A/D converted data
(high-order 2 bits) ADD9 = MSB
–
0
0
–
R0 when being read.0040241
(B)
A/D conversion
result (high-
order) register
–
MS
TS1
TS0
CH2
CH1
CH0
D7–6
D5
D4
D3
D2
D1
D0
–
A/D conversion mode selection
A/D conversion trigger selection
A/D conversion channel status
1
1
0
0
1
0
1
0
TS[1:0]
–
Trigger
#ADTRG pin
8-bit timer 0
16-bit timer 0
Software
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
CH[2:0] Channel
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
–
0
0
0
0
0
0
–
R/W
R/W
R
0 when being read.0040242
(B) 1 Continuous 0 Normal
A/D trigger
register
–
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
CE[2:0] End channel
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
CS[2:0] Start channel
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
–
CE2
CE1
CE0
CS2
CS1
CS0
D7–6
D5
D4
D3
D2
D1
D0
–
A/D converter
end channel selection
A/D converter
start channel selection
–
0
0
0
0
0
0
–
R/W
R/W
0 when being read.0040243
(B)
A/D channel
register
–
ADF
ADE
ADST
OWE
D7–4
D3
D2
D1
D0
–
Conversion-complete flag
A/D enable
A/D conversion control/status
Overwrite error flag
– –
0
0
0
0
–
R
R/W
R/W
R/W
0 when being read.
Reset when ADD is read.
Reset by writing 0.
0040244
(B)
A/D enable
register 1 Enabled 0 Disabled
1 Completed 0
Run/Standby
1 Start/Run 0 Stop
1 Error 0 Normal
–
ST1
ST0
D7–2
D1
D0
–
Input signal sampling time setup –
1
1
0
0
1
0
1
0
ST[1:0] Sampring time
9 clocks
7 clocks
5 clocks
3 clocks
–
1
1
–
R/W 0 when being read.
Use with 9 clocks.
0040245
(B)
A/D sampling
register
APPENDIX: I/O MAP
S1C33L03 FUNCTION PART EPSON B-APPENDIX-13
A-1
B-ap
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
0 to 7
0 to 7
–
–
PP1L2
PP1L1
PP1L0
–
PP0L2
PP0L1
PP0L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Port input 1 interrupt level
reserved
Port input 0 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040260
(B)
Port input 0/1
interrupt
priority register
–
0 to 7
0 to 7
–
–
PP3L2
PP3L1
PP3L0
–
PP2L2
PP2L1
PP2L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Port input 3 interrupt level
reserved
Port input 2 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040261
(B)
Port input 2/3
interrupt
priority register
–
0 to 7
0 to 7
–
–
PK1L2
PK1L1
PK1L0
–
PK0L2
PK0L1
PK0L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Key input 1 interrupt level
reserved
Key input 0 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040262
(B)
Key input
interrupt
priority register
–
0 to 7
0 to 7
–
–
PHSD1L2
PHSD1L1
PHSD1L0
–
PHSD0L2
PHSD0L1
PHSD0L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
High-speed DMA Ch.1
interrupt level
reserved
High-speed DMA Ch.0
interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040263
(B)
High-speed
DMA Ch.0/1
interrupt
priority register
–
0 to 7
0 to 7
–
–
PHSD3L2
PHSD3L1
PHSD3L0
–
PHSD2L2
PHSD2L1
PHSD2L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
High-speed DMA Ch.3
interrupt level
reserved
High-speed DMA Ch.2
interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040264
(B)
High-speed
DMA Ch.2/3
interrupt
priority register
–
0 to 7
–
PDM2
PDM1
PDM0
D7–3
D2
D1
D0
reserved
IDMA interrupt level –
X
X
X
–
R/W 0 when being read.0040265
(B)
IDMA interrupt
priority register
–
0 to 7
0 to 7
–
–
P16T12
P16T11
P16T10
–
P16T02
P16T01
P16T00
D7
D6
D5
D4
D3
D2
D1
D0
reserved
16-bit timer 1 interrupt level
reserved
16-bit timer 0 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040266
(B)
16-bit timer 0/1
interrupt
priority register
–
0 to 7
0 to 7
–
–
P16T32
P16T31
P16T30
–
P16T22
P16T21
P16T20
D7
D6
D5
D4
D3
D2
D1
D0
reserved
16-bit timer 3 interrupt level
reserved
16-bit timer 2 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040267
(B)
16-bit timer 2/3
interrupt
priority register
–
0 to 7
0 to 7
–
–
P16T52
P16T51
P16T50
–
P16T42
P16T41
P16T40
D7
D6
D5
D4
D3
D2
D1
D0
reserved
16-bit timer 5 interrupt level
reserved
16-bit timer 4 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040268
(B)
16-bit timer 4/5
interrupt
priority register
APPENDIX: I/O MAP
B-APPENDIX-14 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
0 to 7
0 to 7
–
–
PSIO02
PSIO01
PSIO00
–
P8TM2
P8TM1
P8TM0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Serial interface Ch.0
interrupt level
reserved
8-bit timer 0–3 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
0040269
(B)
8-bit timer,
serial I/F Ch.0
interrupt
priority register
–
0 to 7
0 to 7
–
–
PAD2
PAD1
PAD0
–
PSIO12
PSIO11
PSIO10
D7
D6
D5
D4
D3
D2
D1
D0
reserved
A/D converter interrupt level
reserved
Serial interface Ch.1
interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
004026A
(B)
Serial I/F Ch.1,
A/D interrupt
priority register
–
0 to 7
–
PCTM2
PCTM1
PCTM0
D7–3
D2
D1
D0
reserved
Clock timer interrupt level –
X
X
X
–
R/W Writing 1 not allowed.004026B
(B)
Clock timer
interrupt
priority register
–
0 to 7
0 to 7
–
–
PP5L2
PP5L1
PP5L0
–
PP4L2
PP4L1
PP4L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Port input 5 interrupt level
reserved
Port input 4 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
004026C
(B)
Port input 4/5
interrupt
priority register
–
0 to 7
0 to 7
–
–
PP7L2
PP7L1
PP7L0
–
PP6L2
PP6L1
PP6L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Port input 7 interrupt level
reserved
Port input 6 interrupt level
–
X
X
X
–
X
X
X
–
R/W
–
R/W
0 when being read.
0 when being read.
004026D
(B)
Port input 6/7
interrupt
priority register
APPENDIX: I/O MAP
S1C33L03 FUNCTION PART EPSON B-APPENDIX-15
A-1
B-ap
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
EK1
EK0
EP3
EP2
EP1
EP0
D7–6
D5
D4
D3
D2
D1
D0
reserved
Key input 1
Key input 0
Port input 3
Port input 2
Port input 1
Port input 0
– –
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.0040270
(B) 1 Enabled 0 Disabled
Key input,
port input 0–3
interrupt
enable register
–
EIDMA
EHDM3
EHDM2
EHDM1
EHDM0
D7–5
D4
D3
D2
D1
D0
reserved
IDMA
High-speed DMA Ch.3
High-speed DMA Ch.2
High-speed DMA Ch.1
High-speed DMA Ch.0
– –
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
0 when being read.0040271
(B) 1 Enabled 0 Disabled
DMA interrupt
enable register
E16TC1
E16TU1
–
E16TC0
E16TU0
–
D7
D6
D5–4
D3
D2
D1–0
16-bit timer 1 comparison A
16-bit timer 1 comparison B
reserved
16-bit timer 0 comparison A
16-bit timer 0 comparison B
reserved
0
0
–
0
0
–
R/W
R/W
–
R/W
R/W
–
0 when being read.
0 when being read.
0040272
(B) 1 Enabled 0 Disabled
16-bit timer 0/1
interrupt
enable register –
1 Enabled 0 Disabled
–
E16TC3
E16TU3
–
E16TC2
E16TU2
–
D7
D6
D5–4
D3
D2
D1–0
16-bit timer 3 comparison A
16-bit timer 3 comparison B
reserved
16-bit timer 2 comparison A
16-bit timer 2 comparison B
reserved
0
0
–
0
0
–
R/W
R/W
–
R/W
R/W
–
0 when being read.
0 when being read.
0040273
(B) 1 Enabled 0 Disabled
16-bit timer 2/3
interrupt
enable register –
1 Enabled 0 Disabled
–
E16TC5
E16TU5
–
E16TC4
E16TU4
–
D7
D6
D5–4
D3
D2
D1–0
16-bit timer 5 comparison A
16-bit timer 5 comparison B
reserved
16-bit timer 4 comparison A
16-bit timer 4 comparison B
reserved
0
0
–
0
0
–
R/W
R/W
–
R/W
R/W
–
0 when being read.
0 when being read.
0040274
(B) 1 Enabled 0 Disabled
16-bit timer 4/5
interrupt
enable register –
1 Enabled 0 Disabled
–
–
E8TU3
E8TU2
E8TU1
E8TU0
D7–4
D3
D2
D1
D0
reserved
8-bit timer 3 underflow
8-bit timer 2 underflow
8-bit timer 1 underflow
8-bit timer 0 underflow
– –
0
0
0
0
–
R/W
R/W
R/W
R/W
0 when being read.0040275
(B) 1 Enabled 0 Disabled
8-bit timer
interrupt
enable register
–
ESTX1
ESRX1
ESERR1
ESTX0
ESRX0
ESERR0
D7–6
D5
D4
D3
D2
D1
D0
reserved
SIF Ch.1 transmit buffer empty
SIF Ch.1 receive buffer full
SIF Ch.1 receive error
SIF Ch.0 transmit buffer empty
SIF Ch.0 receive buffer full
SIF Ch.0 receive error
– –
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.0040276
(B) 1 Enabled 0 Disabled
Serial I/F
interrupt
enable register
–
EP7
EP6
EP5
EP4
ECTM
EADE
D7–6
D5
D4
D3
D2
D1
D0
reserved
Port input 7
Port input 6
Port input 5
Port input 4
Clock timer
A/D converter
– –
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.0040277
(B) 1 Enabled 0 Disabled
Port input 4–7,
clock timer,
A/D interrupt
enable register
APPENDIX: I/O MAP
B-APPENDIX-16 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
FK1
FK0
FP3
FP2
FP1
FP0
D7–6
D5
D4
D3
D2
D1
D0
reserved
Key input 1
Key input 0
Port input 3
Port input 2
Port input 1
Port input 0
– –
X
X
X
X
X
X
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.0040280
(B) 1 Factor is
generated 0 No factor is
generated
Key input,
port input 0–3
interrupt factor
flag register
–
FIDMA
FHDM3
FHDM2
FHDM1
FHDM0
D7–5
D4
D3
D2
D1
D0
reserved
IDMA
High-speed DMA Ch.3
High-speed DMA Ch.2
High-speed DMA Ch.1
High-speed DMA Ch.0
– –
X
X
X
X
X
–
R/W
R/W
R/W
R/W
R/W
0 when being read.0040281
(B)
DMA interrupt
factor flag
register 1 Factor is
generated 0 No factor is
generated
F16TC1
F16TU1
–
F16TC0
F16TU0
–
D7
D6
D5–4
D3
D2
D1–0
16-bit timer 1 comparison A
16-bit timer 1 comparison B
reserved
16-bit timer 0 comparison A
16-bit timer 0 comparison B
reserved
X
X
–
X
X
–
R/W
R/W
–
R/W
R/W
–
0 when being read.
0 when being read.
0040282
(B) 1 Factor is
generated 0 No factor is
generated
16-bit timer 0/1
interrupt factor
flag register –
1 Factor is
generated 0 No factor is
generated
–
F16TC3
F16TU3
–
F16TC2
F16TU2
–
D7
D6
D5–4
D3
D2
D1–0
16-bit timer 3 comparison A
16-bit timer 3 comparison B
reserved
16-bit timer 2 comparison A
16-bit timer 2 comparison B
reserved
X
X
–
X
X
–
R/W
R/W
–
R/W
R/W
–
0 when being read.
0 when being read.
0040283
(B) 1 Factor is
generated 0 No factor is
generated
16-bit timer 2/3
interrupt factor
flag register –
1 Factor is
generated 0 No factor is
generated
–
F16TC5
F16TU5
–
F16TC4
F16TU4
–
D7
D6
D5–4
D3
D2
D1–0
16-bit timer 5 comparison A
16-bit timer 5 comparison B
reserved
16-bit timer 4 comparison A
16-bit timer 4 comparison B
reserved
X
X
–
X
X
–
R/W
R/W
–
R/W
R/W
–
0 when being read.
0 when being read.
0040284
(B) 1 Factor is
generated 0 No factor is
generated
16-bit timer 4/5
interrupt factor
flag register –
1 Factor is
generated 0 No factor is
generated
–
–
F8TU3
F8TU2
F8TU1
F8TU0
D7–4
D3
D2
D1
D0
reserved
8-bit timer 3 underflow
8-bit timer 2 underflow
8-bit timer 1 underflow
8-bit timer 0 underflow
– –
X
X
X
X
–
R/W
R/W
R/W
R/W
0 when being read.0040285
(B) 1 Factor is
generated 0 No factor is
generated
8-bit timer
interrupt factor
flag register
–
FSTX1
FSRX1
FSERR1
FSTX0
FSRX0
FSERR0
D7–6
D5
D4
D3
D2
D1
D0
reserved
SIF Ch.1 transmit buffer empty
SIF Ch.1 receive buffer full
SIF Ch.1 receive error
SIF Ch.0 transmit buffer empty
SIF Ch.0 receive buffer full
SIF Ch.0 receive error
– –
X
X
X
X
X
X
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.0040286
(B) 1 Factor is
generated 0 No factor is
generated
Serial I/F
interrupt factor
flag register
–
FP7
FP6
FP5
FP4
FCTM
FADE
D7–6
D5
D4
D3
D2
D1
D0
reserved
Port input 7
Port input 6
Port input 5
Port input 4
Clock timer
A/D converter
– –
X
X
X
X
X
X
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.0040287
(B) 1 Factor is
generated 0 No factor is
generated
Port input 4–7,
clock timer, A/D
interrupt factor
flag register
APPENDIX: I/O MAP
S1C33L03 FUNCTION PART EPSON B-APPENDIX-17
A-1
B-ap
NameAddressRegister name Bit Function Setting Init. R/W Remarks
R16TC0
R16TU0
RHDM1
RHDM0
RP3
RP2
RP1
RP0
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 0 comparison A
16-bit timer 0 comparison B
High-speed DMA Ch.1
High-speed DMA Ch.0
Port input 3
Port input 2
Port input 1
Port input 0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0040290
(B) 1 IDMA
request 0 Interrupt
request
Port input 0–3,
high-speed
DMA Ch. 0/1,
16-bit timer 0
IDMA request
register
R16TC4
R16TU4
R16TC3
R16TU3
R16TC2
R16TU2
R16TC1
R16TU1
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 4 comparison A
16-bit timer 4 comparison B
16-bit timer 3 comparison A
16-bit timer 3 comparison B
16-bit timer 2 comparison A
16-bit timer 2 comparison B
16-bit timer 1 comparison A
16-bit timer 1 comparison B
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0040291
(B) 1 IDMA
request 0 Interrupt
request
16-bit timer 1–4
IDMA request
register
RSTX0
RSRX0
R8TU3
R8TU2
R8TU1
R8TU0
R16TC5
R16TU5
D7
D6
D5
D4
D3
D2
D1
D0
SIF Ch.0 transmit buffer empty
SIF Ch.0 receive buffer full
8-bit timer 3 underflow
8-bit timer 2 underflow
8-bit timer 1 underflow
8-bit timer 0 underflow
16-bit timer 5 comparison A
16-bit timer 5 comparison B
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0040292
(B) 1 IDMA
request 0 Interrupt
request
16-bit timer 5,
8-bit timer,
serial I/F Ch.0
IDMA request
register
RP7
RP6
RP5
RP4
–
RADE
RSTX1
RSRX1
D7
D6
D5
D4
D3
D2
D1
D0
Port input 7
Port input 6
Port input 5
Port input 4
reserved
A/D converter
SIF Ch.1 transmit buffer empty
SIF Ch.1 receive buffer full
0
0
0
0
–
0
0
0
R/W
R/W
R/W
R/W
–
R/W
R/W
R/W
0 when being read.
0040293
(B) 1 IDMA
request 0 Interrupt
request
1 IDMA
request 0 Interrupt
request
–
Serial I/F Ch.1,
A/D,
port input 4–7
IDMA request
register
DE16TC0
DE16TU0
DEHDM1
DEHDM0
DEP3
DEP2
DEP1
DEP0
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 0 comparison A
16-bit timer 0 comparison B
High-speed DMA Ch.1
High-speed DMA Ch.0
Port input 3
Port input 2
Port input 1
Port input 0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0040294
(B) 1 IDMA
enabled 0 IDMA
disabled
Port input 0–3,
high-speed
DMA Ch. 0/1,
16-bit timer 0
IDMA enable
register
DE16TC4
DE16TU4
DE16TC3
DE16TU3
DE16TC2
DE16TU2
DE16TC1
DE16TU1
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 4 comparison A
16-bit timer 4 comparison B
16-bit timer 3 comparison A
16-bit timer 3 comparison B
16-bit timer 2 comparison A
16-bit timer 2 comparison B
16-bit timer 1 comparison A
16-bit timer 1 comparison B
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0040295
(B) 1 IDMA
enabled 0 IDMA
disabled
16-bit timer 1–4
IDMA enable
register
DESTX0
DESRX0
DE8TU3
DE8TU2
DE8TU1
DE8TU0
DE16TC5
DE16TU5
D7
D6
D5
D4
D3
D2
D1
D0
SIF Ch.0 transmit buffer empty
SIF Ch.0 receive buffer full
8-bit timer 3 underflow
8-bit timer 2 underflow
8-bit timer 1 underflow
8-bit timer 0 underflow
16-bit timer 5 comparison A
16-bit timer 5 comparison B
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0040296
(B) 1 IDMA
enabled 0 IDMA
disabled
16-bit timer 5,
8-bit timer,
serial I/F Ch.0
IDMA enable
register
DEP7
DEP6
DEP5
DEP4
–
DEADE
DESTX1
DESRX1
D7
D6
D5
D4
D3
D2
D1
D0
Port input 7
Port input 6
Port input 5
Port input 4
reserved
A/D converter
SIF Ch.1 transmit buffer empty
SIF Ch.1 receive buffer full
0
0
0
0
–
0
0
0
R/W
R/W
R/W
R/W
–
R/W
R/W
R/W
0 when being read.
0040297
(B) 1 IDMA
enabled 0 IDMA
disabled
1 IDMA
enabled 0 IDMA
disabled
–
Serial I/F Ch.1,
A/D,
port input 4–7
IDMA enable
register
APPENDIX: I/O MAP
B-APPENDIX-18 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
HSD1S3
HSD1S2
HSD1S1
HSD1S0
HSD0S3
HSD0S2
HSD0S1
HSD0S0
D7
D6
D5
D4
D3
D2
D1
D0
High-speed DMA Ch.1
trigger set-up
High-speed DMA Ch.0
trigger set-up
0
0
0
0
0
0
0
0
R/W
R/W
0040298
(B) 0
1
2
3
4
5
6
7
8
9
A
B
C
Software trigger
K51 input (falling edge)
K51 input (rising edge)
Port 1 input
Port 5 input
8-bit timer Ch.1 underflow
16-bit timer Ch.1 compare B
16-bit timer Ch.1 compare A
16-bit timer Ch.5 compare B
16-bit timer Ch.5 compare A
SI/F Ch.1 Rx buffer full
SI/F Ch.1 Tx buffer empty
A/D conversion completion
0
1
2
3
4
5
6
7
8
9
A
B
C
Software trigger
K50 input (falling edge)
K50 input (rising edge)
Port 0 input
Port 4 input
8-bit timer Ch.0 underflow
16-bit timer Ch.0 compare B
16-bit timer Ch.0 compare A
16-bit timer Ch.4 compare B
16-bit timer Ch.4 compare A
SI/F Ch.0 Rx buffer full
SI/F Ch.0 Tx buffer empty
A/D conversion completion
High-speed
DMA Ch.0/1
trigger set-up
register
HSD3S3
HSD3S2
HSD3S1
HSD3S0
HSD2S3
HSD2S2
HSD2S1
HSD2S0
D7
D6
D5
D4
D3
D2
D1
D0
High-speed DMA Ch.3
trigger set-up
High-speed DMA Ch.2
trigger set-up
0
0
0
0
0
0
0
0
R/W
R/W
0040299
(B) 0
1
2
3
4
5
6
7
8
9
A
B
C
Software trigger
K54 input (falling edge)
K54 input (rising edge)
Port 3 input
Port 7 input
8-bit timer Ch.3 underflow
16-bit timer Ch.3 compare B
16-bit timer Ch.3 compare A
16-bit timer Ch.5 compare B
16-bit timer Ch.5 compare A
SI/F Ch.1 Rx buffer full
SI/F Ch.1 Tx buffer empty
A/D conversion completion
0
1
2
3
4
5
6
7
8
9
A
B
C
Software trigger
K53 input (falling edge)
K53 input (rising edge)
Port 2 input
Port 6 input
8-bit timer Ch.2 underflow
16-bit timer Ch.2 compare B
16-bit timer Ch.2 compare A
16-bit timer Ch.4 compare B
16-bit timer Ch.4 compare A
SI/F Ch.0 Rx buffer full
SI/F Ch.0 Tx buffer empty
A/D conversion completion
High-speed
DMA Ch.2/3
trigger set-up
register
–
HST3
HST2
HST1
HST0
D7–4
D3
D2
D1
D0
reserved
HSDMA Ch.3 software trigger
HSDMA Ch.2 software trigger
HSDMA Ch.1 software trigger
HSDMA Ch.0 software trigger
–
0
0
0
0
–
W
W
W
W
0 when being read.004029A
(B) –
1 Trigger 0 Invalid
High-speed
DMA software
trigger
register
–
DENONLY
IDMAONLY
RSTONLY
D7–3
D2
D1
D0
reserved
IDMA enable register set method
selection
IDMA request register set method
selection
Interrupt factor flag reset method
selection
– –
1
1
1
–
R/W
R/W
R/W
004029F
(B)
Flag set/reset
method select
register 1 Set only 0 RD/WR
1 Set only 0 RD/WR
1 Reset only 0 RD/WR
APPENDIX: I/O MAP
S1C33L03 FUNCTION PART EPSON B-APPENDIX-19
A-1
B-ap
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
CFK54
CFK53
CFK52
CFK51
CFK50
D7–5
D4
D3
D2
D1
D0
reserved
K54 function selection
K53 function selection
K52 function selection
K51 function selection
K50 function selection
– –
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
0 when being read.00402C0
(B) 1
#DMAREQ3
0 K54
1
#DMAREQ2
0 K53
1 #ADTRG 0 K52
1
#DMAREQ1
0 K51
1
#DMAREQ0
0 K50
K5 function
select register
–
K54D
K53D
K52D
K51D
K50D
D7–5
D4
D3
D2
D1
D0
reserved
K54 input port data
K53 input port data
K52 input port data
K51 input port data
K50 input port data
– –
–
–
–
–
–
–
R
R
R
R
R
0 when being read.00402C1
(B) 1 High 0 Low
K5 input port
data register
CFK67
CFK66
CFK65
CFK64
CFK63
CFK62
CFK61
CFK60
D7
D6
D5
D4
D3
D2
D1
D0
K67 function selection
K66 function selection
K65 function selection
K64 function selection
K63 function selection
K62 function selection
K61 function selection
K60 function selection
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00402C3
(B) 1 AD7 0 K67
1 AD6 0 K66
1 AD5 0 K65
1 AD4 0 K64
1 AD3 0 K63
1 AD2 0 K62
1 AD1 0 K61
1 AD0 0 K60
K6 function
select register
K67D
K66D
K65D
K64D
K63D
K62D
K61D
K60D
D7
D6
D5
D4
D3
D2
D1
D0
K67 input port data
K66 input port data
K65 input port data
K64 input port data
K63 input port data
K62 input port data
K61 input port data
K60 input port data
–
–
–
–
–
–
–
–
R
R
R
R
R
R
R
R
00402C4
(B) 1 High 0 LowK6 input port
data register
APPENDIX: I/O MAP
B-APPENDIX-20 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
T8CH5S0
SIO3TS0
T8CH4S0
SIO3RS0
SIO2TS0
SIO3ES0
SIO2RS0
SIO2ES0
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 5 underflow
SIO Ch.3 transmit buffer empty
8-bit timer 4 underflow
SIO Ch.3 receive buffer full
SIO Ch.2 transmit buffer empty
SIO Ch.3 receive error
SIO Ch.2 receive buffer full
SIO Ch.2 receive error
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00402C5Interrupt factor
FP function
switching
register
1 SIO Ch.3
TXD Emp. 0 FP6
1 SIO Ch.3
RXD Full 0 FP4
1 SIO Ch.2
TXD Emp. 0 FP3
1 SIO Ch.3
RXD Err. 0 FP2
1 SIO Ch.2
RXD Full 0 FP1
1 SIO Ch.2
RXD Err. 0 FP0
1 T8 Ch.5 UF 0 FP7
1 T8 Ch.4 UF 0 FP5
SPT31
SPT30
SPT21
SPT20
SPT11
SPT10
SPT01
SPT00
D7
D6
D5
D4
D3
D2
D1
D0
FPT3 interrupt input port selection
FPT2 interrupt input port selection
FPT1 interrupt input port selection
FPT0 interrupt input port selection
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
00402C6
(B)
Port input
interrupt select
register 1
11 10 01 00
P23 P03 K53 K63
11 10 01 00
P22 P02 K52 K62
11 10 01 00
P21 P01 K51 K61
11 10 01 00
P20 P00 K50 K60
11 10 01 00
P27 P07 P33 K67
11 10 01 00
P26 P06 P32 K66
11 10 01 00
P25 P05 P31 K65
11 10 01 00
P24 P04 K54 K64
SPT71
SPT70
SPT61
SPT60
SPT51
SPT50
SPT41
SPT40
D7
D6
D5
D4
D3
D2
D1
D0
FPT7 interrupt input port selection
FPT6 interrupt input port selection
FPT5 interrupt input port selection
FPT4 interrupt input port selection
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
00402C7
(B)
Port input
interrupt select
register 2
1 High level
or
Rising edge
0 Low level
or
Falling
edge
SPPT7
SPPT6
SPPT5
SPPT4
SPPT3
SPPT2
SPPT1
SPPT0
D7
D6
D5
D4
D3
D2
D1
D0
FPT7 input polarity selection
FPT6 input polarity selection
FPT5 input polarity selection
FPT4 input polarity selection
FPT3 input polarity selection
FPT2 input polarity selection
FPT1 input polarity selection
FPT0 input polarity selection
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00402C8
(B)
Port input
interrupt
input polarity
select register
1 Edge 0 LevelSEPT7
SEPT6
SEPT5
SEPT4
SEPT3
SEPT2
SEPT1
SEPT0
D7
D6
D5
D4
D3
D2
D1
D0
FPT7 edge/level selection
FPT6 edge/level selection
FPT5 edge/level selection
FPT4 edge/level selection
FPT3 edge/level selection
FPT2 edge/level selection
FPT1 edge/level selection
FPT0 edge/level selection
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00402C9
(B)
Port input
interrupt
edge/level
select register
–
SPPK11
SPPK10
SPPK01
SPPK00
D7–4
D3
D2
D1
D0
reserved
FPK1 i
nterrupt input port selection
FPK0 i
nterrupt input port selection
–
0
0
0
0
–
R/W
R/W
0 when being read.00402CA
(B)
Key input
interrupt select
register
–
11 10 01 00
P2[7:4] P0[7:4] K6[7:4] K6[3:0]
11 10 01 00
P2[4:0] P0[4:0] K6[4:0] K5[4:0]
T8CH5S1
T8CH4S1
SIO3ES1
SIO2ES1
SIO3TS1
SIO3RS1
SIO2TS1
SIO2RS1
D7
D6
D5
D4
D3
D2
D1
D0
8-bit timer 5 underflow
8-bit timer 4 underflow
SIO Ch.3 receive error
SIO Ch.2 receive error
SIO Ch.3 transmit buffer empty
SIO Ch.3 receive buffer full
SIO Ch.2 transmit buffer empty
SIO Ch.2 receive buffer full
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00402CBInterrupt factor
TM16 function
switching
register 1 SIO Ch.3
RXD Err. 0 TM16 Ch.3
comp.A
1 SIO Ch.2
RXD Err. 0 TM16 Ch.3
comp.B
1 SIO Ch.3
TXD Emp. 0 TM16 Ch.4
comp.A
1 SIO Ch.3
RXD Full 0 TM16 Ch.4
comp.B
1 SIO Ch.2
TXD Emp. 0 TM16 Ch.5
comp.A
1 SIO Ch.2
RXD Full 0 TM16 Ch.5
comp.B
1 T8 Ch.5 UF 0 TM16 Ch.2
comp.A
1 T8 Ch.4 UF 0 TM16 Ch.2
comp.B
APPENDIX: I/O MAP
S1C33L03 FUNCTION PART EPSON B-APPENDIX-21
A-1
B-ap
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
SCPK04
SCPK03
SCPK02
SCPK01
SCPK00
D7–5
D4
D3
D2
D1
D0
reserved
FPK04 input comparison
FPK03 input comparison
FPK02 input comparison
FPK01 input comparison
FPK00 input comparison
– –
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
0 when being read.00402CC
(B) 1 High 0 Low
Key input
interrupt
(FPK0) input
comparison
register
–
SCPK13
SCPK12
SCPK11
SCPK10
D7–4
D3
D2
D1
D0
reserved
FPK13 input comparison
FPK12 input comparison
FPK11 input comparison
FPK10 input comparison
– –
0
0
0
0
–
R/W
R/W
R/W
R/W
0 when being read.00402CD
(B) 1 High 0 Low
Key input
interrupt
(FPK1) input
comparison
register
–
SMPK04
SMPK03
SMPK02
SMPK01
SMPK00
D7–5
D4
D3
D2
D1
D0
reserved
FPK04 input mask
FPK03 input mask
FPK02 input mask
FPK01 input mask
FPK00 input mask
– –
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
0 when being read.00402CE
(B) 1 Interrupt
enabled 0 Interrupt
disabled
Key input
interrupt
(FPK0) input
mask register
–
SMPK13
SMPK12
SMPK11
SMPK10
D7–4
D3
D2
D1
D0
reserved
FPK13 input mask
FPK12 input mask
FPK11 input mask
FPK10 input mask
– –
0
0
0
0
–
R/W
R/W
R/W
R/W
0 when being read.00402CF
(B) 1 Interrupt
enabled 0 Interrupt
disabled
Key input
interrupt
(FPK1) input
mask register
CFP07
CFP06
CFP05
CFP04
CFP03
CFP02
CFP01
CFP00
D7
D6
D5
D4
D3
D2
D1
D0
P07 function selection
P06 function selection
P05 function selection
P04 function selection
P03 function selection
P02 function selection
P01 function selection
P00 function selection
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Extended functions
(0x402DF)
00402D0
(B) 1 #SRDY1 0 P07
1 #SCLK1 0 P06
1 SOUT1 0 P05
1 SIN1 0 P04
1 #SRDY0 0 P03
1 #SCLK0 0 P02
1 SOUT0 0 P01
1 SIN0 0 P00
P0 function
select register
P07D
P06D
P05D
P04D
P03D
P02D
P01D
P00D
D7
D6
D5
D4
D3
D2
D1
D0
P07 I/O port data
P06 I/O port data
P05 I/O port data
P04 I/O port data
P03 I/O port data
P02 I/O port data
P01 I/O port data
P00 I/O port data
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00402D1
(B) 1 High 0 LowP0 I/O port data
register
IOC07
IOC06
IOC05
IOC04
IOC03
IOC02
IOC01
IOC00
D7
D6
D5
D4
D3
D2
D1
D0
P07 I/O control
P06 I/O control
P05 I/O control
P04 I/O control
P03 I/O control
P02 I/O control
P01 I/O control
P00 I/O control
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
This register
indicates the values
of the I/O control
signals of the ports
when it is read. (See
detailed explanation.)
00402D2
(B) 1 Output 0 InputP0 I/O control
register
–
CFP16
CFP15
CFP14
CFP13
CFP12
CFP11
CFP10
D7
D6
D5
D4
D3
D2
D1
D0
reserved
P16 function selection
P15 function selection
P14 function selection
P13 function selection
P12 function selection
P11 function selection
P10 function selection
–
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.
Extended functions
(0x402DF)
00402D4
(B) 1 EXCL5
#DMAEND1
0 P16
1 EXCL4
#DMAEND0
0 P15
1 EXCL3
T8UF3 0 P13
1 EXCL2
T8UF2 0 P12
1 EXCL1
T8UF1 0 P11
1 EXCL0
T8UF0 0 P10
–P1 function
select register
1 FOSC1 0 P14
–
P16D
P15D
P14D
P13D
P12D
P11D
P10D
D7
D6
D5
D4
D3
D2
D1
D0
reserved
P16 I/O port data
P15 I/O port data
P14 I/O port data
P13 I/O port data
P12 I/O port data
P11 I/O port data
P10 I/O port data
–
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.00402D5
(B) 1 High 0 Low
–
P1 I/O port data
register
APPENDIX: I/O MAP
B-APPENDIX-22 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
IOC16
IOC15
IOC14
IOC13
IOC12
IOC11
IOC10
D7
D6
D5
D4
D3
D2
D1
D0
reserved
P16 I/O control
P15 I/O control
P14 I/O control
P13 I/O control
P12 I/O control
P11 I/O control
P10 I/O control
–
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.
This register
indicates the values
of the I/O control
signals of the ports
when it is read. (See
detailed explanation.)
00402D6
(B) 1Output 0Input
–P1 I/O control
register
–
SSRDY3
SSCLK3
SSOUT3
SSIN3
D7–4
D3
D2
D1
D0
reserved
Serial I/F Ch.3 SRDY selection
Serial I/F Ch.3 SCLK selection
Serial I/F Ch.3 SOUT selection
Serial I/F Ch.3 SIN selection
– –
0
0
0
0
–
R/W
R/W
R/W
R/W
00402D7Port SIO
function
extension
register
1 #SRDY3 0
P32/
#DMAACK0
1 #SCLK3 0
P15/EXCL4/
#DMAEND0
1 SOUT3 0
P16/EXCL5/
#DMAEND1
1 SIN3 0
P33/
#DMAACK1
CFP27
CFP26
CFP25
CFP24
CFP23
CFP22
CFP21
CFP20
D7
D6
D5
D4
D3
D2
D1
D0
P27 function selection
P26 function selection
P25 function selection
P24 function selection
P23 function selection
P22 function selection
P21 function selection
P20 function selection
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W Ext. func.(0x402DF)
00402D8
(B) 1 TM5 0 P27
1 TM4 0 P26
1 TM3 0 P25
1 TM2 0 P24
1 TM1 0 P23
1 TM0 0 P22
1 #DWE 0 P21
1 #DRD 0 P20
P2 function
select register
P27D
P26D
P25D
P24D
P23D
P22D
P21D
P20D
D7
D6
D5
D4
D3
D2
D1
D0
P27 I/O port data
P26 I/O port data
P25 I/O port data
P24 I/O port data
P23 I/O port data
P22 I/O port data
P21 I/O port data
P20 I/O port data
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00402D9
(B) 1 High 0 LowP2 I/O port data
register
IOC27
IOC26
IOC25
IOC24
IOC23
IOC22
IOC21
IOC20
D7
D6
D5
D4
D3
D2
D1
D0
P27 I/O control
P26 I/O control
P25 I/O control
P24 I/O control
P23 I/O control
P22 I/O control
P21 I/O control
P20 I/O control
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
This register
indicates the values
of the I/O control
signals of the ports
when it is read. (See
detailed explanation.)
00402DA
(B) 1 Output 0 InputP2 I/O control
register
–
SSRDY2
SSCLK2
SSOUT2
SSIN2
D7–4
D3
D2
D1
D0
reserved
Serial I/F Ch.2 SRDY selection
Serial I/F Ch.2 SCLK selection
Serial I/F Ch.2 SOUT selection
Serial I/F Ch.2 SIN selection
–
0
0
0
0
–
R/W
R/W
R/W
R/W
00402DB 1 #SRDY2 0 P24/TM2
1 #SCLK2 0 P25/TM3
1 SOUT2 0 P26/TM4
1 SIN2 0 P27/TM5
Port SIO
function
extension
register
–
–
CFP35
CFP34
CFP33
CFP32
CFP31
CFP30
D7–6
D5
D4
D3
D2
D1
D0
reserved
P35 function selection
P34 function selection
P33 function selection
P32 function selection
P31 function selection
P30 function selection
–
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.
Ext. func.(0x402DF)
00402DC
(B) –P3 function
select register 1 #BUSACK 0 P35
1 #BUSREQ
#CE6 0 P34
1
#DMAACK0
0 P32
1 #BUSGET 0 P31
1 #WAIT
#CE4/#CE5 0 P30
1
#DMAACK1
0 P33
–
P35D
P34D
P33D
P32D
P31D
P30D
D7–6
D5
D4
D3
D2
D1
D0
reserved
P35 I/O port data
P34 I/O port data
P33 I/O port data
P32 I/O port data
P31 I/O port data
P30 I/O port data
–
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.00402DD
(B) 1 High 0 Low
–
P3 I/O port data
register
–
IOC35
IOC34
IOC33
IOC32
IOC31
IOC30
D7–6
D5
D4
D3
D2
D1
D0
reserved
P35 I/O control
P34 I/O control
P33 I/O control
P32 I/O control
P31 I/O control
P30 I/O control
–
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.
This register
indicates the values
of the I/O control
signals of the ports
when it is read. (See
detailed explanation.)
00402DE
(B) 1 Output 0 Input
–P3 I/O control
register
APPENDIX: I/O MAP
S1C33L03 FUNCTION PART EPSON B-APPENDIX-23
A-1
B-ap
NameAddressRegister name Bit Function Setting Init. R/W Remarks
CFEX7
CFEX6
CFEX5
CFEX4
CFEX3
CFEX2
CFEX1
CFEX0
D7
D6
D5
D4
D3
D2
D1
D0
P07 port extended function
P06 port extended function
P05 port extended function
P04 port extended function
P31 port extended function
P21 port extended function
P10, P11, P13 port extended
function
P12, P14 port extended function
0
0
0
0
0
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00402DF
(B)
Port function
extension
register
1
#DMAEND3
0 P07, etc.
1
#DMAACK3
0 P06, etc.
1
#DMAEND2
0 P05, etc.
1
#DMAACK2
0 P04, etc.
1 #GARD 0 P31, etc.
1 #GAAS 0 P21, etc.
1 DST0
DST1
DPC0
0 P10, etc.
P11, etc.
P13, etc.
1 DST2
DCLK 0 P12, etc.
P14, etc.
–
–
A18SZ
A18DF1
A18DF0
–
A18WT2
A18WT1
A18WT0
–
A16SZ
A16DF1
A16DF0
–
A16WT2
A16WT1
A16WT0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Areas 18–17 device size selection
Areas 18–17
output disable delay time
reserved
Areas 18–17 wait control
reserved
Areas 16–15 device size selection
Areas 16–15
output disable delay time
reserved
Areas 16–15 wait control
–
–
–
1 8 bits 0 16 bits
1 8 bits 0 16 bits –
0
1
1
–
1
1
1
–
0
1
1
–
1
1
1
–
R/W
R/W
–
R/W
–
R/W
R/W
–
R/W
0 when being read.
0 when being read.
0 when being read.
0 when being read.
0048120
(HW)
Areas 18–15
set-up register
1
1
0
0
1
0
1
0
A18DF[1:0] Number of cycles
3.5
2.5
1.5
0.5
1
1
0
0
1
0
1
0
A16DF[1:0] Number of cycles
3.5
2.5
1.5
0.5
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A18WT[2:0] Wait cycles
7
6
5
4
3
2
1
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A16WT[2:0] Wait cycles
7
6
5
4
3
2
1
0
–
A14DRA
A13DRA
A14SZ
A14DF1
A14DF0
–
A14WT2
A14WT1
A14WT0
DF–9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Area 14 DRAM selection
Area 13 DRAM selection
Areas 14–13 device size selection
Areas 14–13
output disable delay time
reserved
Areas 14–13 wait control
–
–
1 Used 0 Not used
1 Used 0 Not used
1 8 bits 0 16 bits
–
0
0
0
1
1
–
1
1
1
–
R/W
R/W
R/W
R/W
–
R/W
0 when being read.
0 when being read.
0048122
(HW)
1
1
0
0
1
0
1
0
A14DF[1:0] Number of cycles
3.5
2.5
1.5
0.5
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A14WT[2:0] Wait cycles
7
6
5
4
3
2
1
0
Areas 14–13
set-up register
APPENDIX: I/O MAP
B-APPENDIX-24 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
A12SZ
A12DF1
A12DF0
–
A12WT2
A12WT1
A12WT0
DF–7
D6
D5
D4
D3
D2
D1
D0
reserved
Areas 12–11 device size selection
Areas 12–11
output disable delay time
reserved
Areas 12–11 wait control
–
–
1 8 bits 0 16 bits –
0
1
1
–
1
1
1
–
R/W
R/W
–
R/W
0 when being read.
0 when being read.
0048124
(HW)
Areas 12–11
set-up register
1
1
0
0
1
0
1
0
A18DF[1:0] Number of cycles
3.5
2.5
1.5
0.5
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A18WT[2:0] Wait cycles
7
6
5
4
3
2
1
0
–
A10IR2
A10IR1
A10IR0
–
A10BW1
A10BW0
A10DRA
A9DRA
A10SZ
A10DF1
A10DF0
–
A10WT2
A10WT1
A10WT0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Area 10 internal ROM size
selection
reserved
Areas 10–9
burst ROM
burst read cycle wait control
Area 10 burst ROM selection
Area 9 burst ROM selection
Areas 10–9 device size selection
Areas 10–9
output disable delay time
reserved
Areas 10–9 wait control
–
–
–
1 Used 0 Not used
1 Used 0 Not used
1 8 bits 0 16 bits
–
1
1
1
–
0
0
0
0
0
1
1
–
1
1
1
–
R/W
–
R/W
R/W
R/W
R/W
R/W
–
R/W
0 when being read.
0 when being read.
0 when being read.
0048126
(HW)
1
1
0
0
1
0
1
0
A10BW[1:0] Wait cycles
3
2
1
0
1
1
0
0
1
0
1
0
A10DF[1:0] Number of cycles
3.5
2.5
1.5
0.5
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A10IR[2:0] ROM size
2MB
1MB
512KB
256KB
128KB
64KB
32KB
16KB
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A10WT[2:0] Wait cycles
7
6
5
4
3
2
1
0
Areas 10–9
set-up register
–
A8DRA
A7DRA
A8SZ
A8DF1
A8DF0
–
A8WT2
A8WT1
A8WT0
DF–9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Area 8 DRAM selection
Area 7 DRAM selection
Areas 8–7 device size selection
Areas 8–7
output disable delay time
reserved
Areas 8–7 wait control
–
–
1 Used 0 Not used
1 Used 0 Not used
1 8 bits 0 16 bits
–
0
0
0
1
1
–
1
1
1
–
R/W
R/W
R/W
R/W
–
R/W
0 when being read.
0 when being read.
0048128
(HW)
Areas 8–7
set-up register
1
1
0
0
1
0
1
0
A8DF[1:0] Number of cycles
3.5
2.5
1.5
0.5
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A8WT[2:0] Wait cycles
7
6
5
4
3
2
1
0
APPENDIX: I/O MAP
S1C33L03 FUNCTION PART EPSON B-APPENDIX-25
A-1
B-ap
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
A6DF1
A6DF0
–
A6WT2
A6WT1
A6WT0
–
A5SZ
A5DF1
A5DF0
–
A5WT2
A5WT1
A5WT0
DF–E
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Area 6
output disable delay time
reserved
Area 6 wait control
reserved
Areas 5–4 device size selection
Areas 5–4
output disable delay time
reserved
Areas 5–4 wait control
–
–
–
18 bits 016 bits
–
1
1
–
1
1
1
–
0
1
1
–
1
1
1
–
R/W
–
R/W
–
R/W
R/W
–
R/W
0 when being read.
0 when being read.
0 when being read.
0 when being read.
004812A
(HW)
Areas 6–4
set-up register 1
1
0
0
1
0
1
0
A6DF[1:0] Number of cycles
3.5
2.5
1.5
0.5
1
1
0
0
1
0
1
0
A5DF[1:0] Number of cycles
3.5
2.5
1.5
0.5
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A6WT[2:0] Wait cycles
7
6
5
4
3
2
1
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A5WT[2:0] Wait cycles
7
6
5
4
3
2
1
0
TBRP7
TBRP6
TBRP5
TBRP4
TBRP3
TBRP2
TBRP1
TBRP0
D7
D6
D5
D4
D3
D2
D1
D0
TTBR register write protect 0
0
0
0
0
0
0
0
WUndefined in read.004812D
(B) Writing 01011001 (0x59)
removes the TTBR (0x48134)
write protection.
Writing other data sets the
write protection.
TTBR write
protect register
RBCLK
–
RBST8
REDO
RCA1
RCA0
RPC2
RPC1
RPC0
RRA1
RRA0
–
SBUSST
SEMAS
SEPD
SWAITE
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BCLK output control
reserved
Burst ROM burst mode selection
DRAM page mode selection
Column address size selection
Refresh enable
Refresh method selection
Refresh RPC delay setup
Refresh RAS pulse width
selection
reserved
External interface method selection
External bus master setup
External power-down control
#WAIT enable
–
–
1Fixed at H 0Enabled
1
8-successive
0
4-successive
1Enabled 0Disabled
1Self-refresh 0
CBR-refresh
12.0 01.0
1#BSL 0A0
1Existing 0Nonexistent
1Enabled 0Disabled
1Enabled 0Disabled
1EDO 0Fast page
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
–
R/W
R/W
R/W
R/W
Writing 1 not allowed.
Writing 1 not allowed.
004812E
(HW)
1
1
0
0
1
0
1
0
RCA[1:0] Size
11
10
9
8
1
1
0
0
1
0
1
0
RRA[1:0] Number of cycles
5
4
3
2
Bus control
register
APPENDIX: I/O MAP
B-APPENDIX-26 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
1 Successive 0 Normal
–
A3EEN
CEFUNC1
CEFUNC0
CRAS
RPRC1
RPRC0
–
CASC1
CASC0
–
RASC1
RASC0
DF–C
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Area 3 emulation
#CE pin function selection
Successive RAS mode setup
DRAM
RAS precharge cycles selection
reserved
DRAM
CAS cycles selection
reserved
DRAM
RAS cycles selection
– –
1
0
0
0
0
0
–
0
0
–
0
0
–
R/W
R/W
R/W
R/W
–
R/W
–
R/W
0 when being read.
0 when being read.
0 when being read.
0048130
(HW)
1
0
0
x
1
0
CEFUNC[1:0]
#CE output
#CE7/8..#CE17/18
#CE6..#CE17
#CE4..#CE10
1
1
0
0
1
0
1
0
RPRC[1:0] Number of cycles
4
3
2
1
–
1
1
0
0
1
0
1
0
CASC[1:0] Number of cycles
4
3
2
1
–
1
1
0
0
1
0
1
0
RASC[1:0] Number of cycles
4
3
2
1
DRAM timing
set-up register 1
Internal ROM
0 Emulation
–
1 Internal
access 0 External
access
1 Internal
access 0 External
access
1 Big endian 0
Little endian
A18IO
A16IO
A14IO
A12IO
–
A8IO
A6IO
A5IO
A18EC
A16EC
A14EC
A12EC
A10EC
A8EC
A6EC
A5EC
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Area 18, 17 internal/external access
Area 16, 15 internal/external access
Area 14, 13 internal/external access
Area 12, 11 internal/external access
reserved
Area 8, 7 internal/external
access
Area 6 internal/external
access
Area 5, 4 internal/external
access
Area 18, 17 endian control
Area 16, 15 endian control
Area 14, 13 endian control
Area 12, 11 endian control
Area 10, 9 endian control
Area 8, 7 endian control
Area 6 endian control
Area 5, 4 endian control
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.
0048132
(HW)
Access control
register
TTBR15
TTBR14
TTBR13
TTBR12
TTBR11
TTBR10
TTBR09
TTBR08
TTBR07
TTBR06
TTBR05
TTBR04
TTBR03
TTBR02
TTBR01
TTBR00
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Trap table base address [15:10]
Trap table base address [9:0] Fixed at 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R0 when being read.
Writing 1 not allowed.
0048134
(HW)
TTBR low-
order register
TTBR33
TTBR32
TTBR31
TTBR30
TTBR2B
TTBR2A
TTBR29
TTBR28
TTBR27
TTBR26
TTBR25
TTBR24
TTBR23
TTBR22
TTBR21
TTBR20
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Trap table base address [31:28]
Trap table base address [27:16]
Fixed at 0
0x0C0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
R
R/W
0 when being read.
Writing 1 not allowed.
0048136
(HW)
TTBR high-
order register
APPENDIX: I/O MAP
S1C33L03 FUNCTION PART EPSON B-APPENDIX-27
A-1
B-ap
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
1 Enabled 0 Disabled
1 Enabled 0 Disabled
A18AS
A16AS
A14AS
A12AS
–
A8AS
A6AS
A5AS
A18RD
A16RD
A14RD
A12RD
–
A8RD
A6RD
A5RD
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Area 18, 17 address strobe signal
Area 16, 15 address strobe signal
Area 14, 13 address strobe signal
Area 12, 11 address strobe signal
reserved
Area 8, 7 address strobe signal
Area 6 address strobe signal
Area 5, 4 address strobe signal
Area 18, 17 read signal
Area 16, 15 read signal
Area 14, 13 read signal
Area 12, 11 read signal
reserved
Area 8, 7 read signal
Area 6 read signal
Area 5, 4 read signal
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
–
R/W
R/W
R/W
0 when being read.
0 when being read.
0048138
(HW)
G/A read signal
control register
–
1 Enabled 0 Disabled
1 Enabled 0 Disabled
–
A1X1MD
–
BCLKSEL1
BCLKSEL0
D7–4
D3
D2
D1
D0
reserved
Area 1 access-speed
reserved
BCLK output clock selection 1
1
0
0
1
0
1
0
BCLKSEL[1:0]
–
–BCLK
PLL_CLK
OSC3_CLK
BCU_CLK
CPU_CLK
0
0
0
0
0
–
R/W
–
R/W
0 when being read.
x2 speed mode only
0 when being read.
004813A
(B)
BCLK select
register 1 2 cycles 0 4 cycles
APPENDIX: I/O MAP
B-APPENDIX-28 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
0 to 65535CR0A15
CR0A14
CR0A13
CR0A12
CR0A11
CR0A10
CR0A9
CR0A8
CR0A7
CR0A6
CR0A5
CR0A4
CR0A3
CR0A2
CR0A1
CR0A0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 0 comparison data A
CR0A15 = MSB
CR0A0 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048180
(HW)
16-bit timer 0
comparison
register A
0 to 65535CR0B15
CR0B14
CR0B13
CR0B12
CR0B11
CR0B10
CR0B9
CR0B8
CR0B7
CR0B6
CR0B5
CR0B4
CR0B3
CR0B2
CR0B1
CR0B0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 0 comparison data B
CR0B15 = MSB
CR0B0 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048182
(HW)
16-bit timer 0
comparison
register B
0 to 65535TC015
TC014
TC013
TC012
TC011
TC010
TC09
TC08
TC07
TC06
TC05
TC04
TC03
TC02
TC01
TC00
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 0 counter data
TC015 = MSB
TC00 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R0048184
(HW)
16-bit timer 0
counter data
register
–
SELFM0
SELCRB0
OUTINV0
CKSL0
PTM0
PRESET0
PRUN0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
16-bit timer 0 fine mode selection
16-bit timer 0 comparison buffer
16-bit timer 0 output inversion
16-bit timer 0 input clock selection
16-bit timer 0 clock output control
16-bit timer 0 reset
16-bit timer 0 Run/Stop control
0
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
W
R/W
0 when being read.
0 when being read.
0048186
(B) –
1 Enabled 0 Disabled
1 Fine mode 0 Normal
1 Invert 0 Normal
1
External clock
0
Internal clock
1 On 0 Off
1 Reset 0 Invalid
1 Run 0 Stop
16-bit timer 0
control register
APPENDIX: I/O MAP
S1C33L03 FUNCTION PART EPSON B-APPENDIX-29
A-1
B-ap
NameAddressRegister name Bit Function Setting Init. R/W Remarks
0 to 65535CR1A15
CR1A14
CR1A13
CR1A12
CR1A11
CR1A10
CR1A9
CR1A8
CR1A7
CR1A6
CR1A5
CR1A4
CR1A3
CR1A2
CR1A1
CR1A0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 1 comparison data A
CR1A15 = MSB
CR1A0 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048188
(HW)
16-bit timer 1
comparison
register A
0 to 65535CR1B15
CR1B14
CR1B13
CR1B12
CR1B11
CR1B10
CR1B9
CR1B8
CR1B7
CR1B6
CR1B5
CR1B4
CR1B3
CR1B2
CR1B1
CR1B0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 1 comparison data B
CR1B15 = MSB
CR1B0 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W004818A
(HW)
16-bit timer 1
comparison
register B
0 to 65535TC115
TC114
TC113
TC112
TC111
TC110
TC19
TC18
TC17
TC16
TC15
TC14
TC13
TC12
TC11
TC10
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 1 counter data
TC115 = MSB
TC10 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R004818C
(HW)
16-bit timer 1
counter data
register
–
SELFM1
SELCRB1
OUTINV1
CKSL1
PTM1
PRESET1
PRUN1
D7
D6
D5
D4
D3
D2
D1
D0
reserved
16-bit timer 1 fine mode selection
16-bit timer 1 comparison buffer
16-bit timer 1 output inversion
16-bit timer 1 input clock selection
16-bit timer 1 clock output control
16-bit timer 1 reset
16-bit timer 1 Run/Stop control
0
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
W
R/W
0 when being read.
0 when being read.
004818E
(B) –
1 Enabled 0 Disabled
1 Fine mode 0 Normal
1 Invert 0 Normal
1
External clock
0
Internal clock
1 On 0 Off
1 Reset 0 Invalid
1 Run 0 Stop
16-bit timer 1
control register
APPENDIX: I/O MAP
B-APPENDIX-30 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
0 to 65535CR2A15
CR2A14
CR2A13
CR2A12
CR2A11
CR2A10
CR2A9
CR2A8
CR2A7
CR2A6
CR2A5
CR2A4
CR2A3
CR2A2
CR2A1
CR2A0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 2 comparison data A
CR2A15 = MSB
CR2A0 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048190
(HW)
16-bit timer 2
comparison
register A
0 to 65535CR2B15
CR2B14
CR2B13
CR2B12
CR2B11
CR2B10
CR2B9
CR2B8
CR2B7
CR2B6
CR2B5
CR2B4
CR2B3
CR2B2
CR2B1
CR2B0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 2 comparison data B
CR2B15 = MSB
CR2B0 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048192
(HW)
16-bit timer 2
comparison
register B
0 to 65535TC215
TC214
TC213
TC212
TC211
TC210
TC29
TC28
TC27
TC26
TC25
TC24
TC23
TC22
TC21
TC20
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 2 counter data
TC215 = MSB
TC20 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R0048194
(HW)
16-bit timer 2
counter data
register
–
SELFM2
SELCRB2
OUTINV2
CKSL2
PTM2
PRESET2
PRUN2
D7
D6
D5
D4
D3
D2
D1
D0
reserved
16-bit timer 2 fine mode selection
16-bit timer 2 comparison buffer
16-bit timer 2 output inversion
16-bit timer 2 input clock selection
16-bit timer 2 clock output control
16-bit timer 2 reset
16-bit timer 2 Run/Stop control
0
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
W
R/W
0 when being read.
0 when being read.
0048196
(B) –
1 Enabled 0 Disabled
1 Fine mode 0 Normal
1 Invert 0 Normal
1
External clock
0
Internal clock
1 On 0 Off
1 Reset 0 Invalid
1 Run 0 Stop
16-bit timer 2
control register
APPENDIX: I/O MAP
S1C33L03 FUNCTION PART EPSON B-APPENDIX-31
A-1
B-ap
NameAddressRegister name Bit Function Setting Init. R/W Remarks
0 to 65535CR3A15
CR3A14
CR3A13
CR3A12
CR3A11
CR3A10
CR3A9
CR3A8
CR3A7
CR3A6
CR3A5
CR3A4
CR3A3
CR3A2
CR3A1
CR3A0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 3 comparison data A
CR3A15 = MSB
CR3A0 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048198
(HW)
16-bit timer 3
comparison
register A
0 to 65535CR3B15
CR3B14
CR3B13
CR3B12
CR3B11
CR3B10
CR3B9
CR3B8
CR3B7
CR3B6
CR3B5
CR3B4
CR3B3
CR3B2
CR3B1
CR3B0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 3 comparison data B
CR3B15 = MSB
CR3B0 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W004819A
(HW)
16-bit timer 3
comparison
register B
0 to 65535TC315
TC314
TC313
TC312
TC311
TC310
TC39
TC38
TC37
TC36
TC35
TC34
TC33
TC32
TC31
TC30
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 3 counter data
TC315 = MSB
TC30 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R004819C
(HW)
16-bit timer 3
counter data
register
–
SELFM3
SELCRB3
OUTINV3
CKSL3
PTM3
PRESET3
PRUN3
D7
D6
D5
D4
D3
D2
D1
D0
reserved
16-bit timer 3 fine mode selection
16-bit timer 3 comparison buffer
16-bit timer 3 output inversion
16-bit timer 3 input clock selection
16-bit timer 3 clock output control
16-bit timer 3 reset
16-bit timer 3 Run/Stop control
0
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
W
R/W
0 when being read.
0 when being read.
004819E
(B) –
1 Enabled 0 Disabled
1 Fine mode 0 Normal
1 Invert 0 Normal
1
External clock
0
Internal clock
1 On 0 Off
1 Reset 0 Invalid
1 Run 0 Stop
16-bit timer 3
control register
APPENDIX: I/O MAP
B-APPENDIX-32 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
0 to 65535CR4A15
CR4A14
CR4A13
CR4A12
CR4A11
CR4A10
CR4A9
CR4A8
CR4A7
CR4A6
CR4A5
CR4A4
CR4A3
CR4A2
CR4A1
CR4A0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 4 comparison data A
CR4A15 = MSB
CR4A0 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W00481A0
(HW)
16-bit timer 4
comparison
register A
0 to 65535CR4B15
CR4B14
CR4B13
CR4B12
CR4B11
CR4B10
CR4B9
CR4B8
CR4B7
CR4B6
CR4B5
CR4B4
CR4B3
CR4B2
CR4B1
CR4B0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 4 comparison data B
CR4B15 = MSB
CR4B0 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W00481A2
(HW)
16-bit timer 4
comparison
register B
0 to 65535TC415
TC414
TC413
TC412
TC411
TC410
TC49
TC48
TC47
TC46
TC45
TC44
TC43
TC42
TC41
TC40
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 4 counter data
TC415 = MSB
TC40 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R00481A4
(HW)
16-bit timer 4
counter data
register
–
SELFM4
SELCRB4
OUTINV4
CKSL4
PTM4
PRESET4
PRUN4
D7
D6
D5
D4
D3
D2
D1
D0
reserved
16-bit timer 4 fine mode selection
16-bit timer 4 comparison buffer
16-bit timer 4 output inversion
16-bit timer 4 input clock selection
16-bit timer 4 clock output control
16-bit timer 4 reset
16-bit timer 4 Run/Stop control
0
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
W
R/W
0 when being read.
0 when being read.
00481A6
(B) –
1 Enabled 0 Disabled
1 Fine mode 0 Normal
1 Invert 0 Normal
1
External clock
0
Internal clock
1 On 0 Off
1 Reset 0 Invalid
1 Run 0 Stop
16-bit timer 4
control register
APPENDIX: I/O MAP
S1C33L03 FUNCTION PART EPSON B-APPENDIX-33
A-1
B-ap
NameAddressRegister name Bit Function Setting Init. R/W Remarks
0 to 65535CR5A15
CR5A14
CR5A13
CR5A12
CR5A11
CR5A10
CR5A9
CR5A8
CR5A7
CR5A6
CR5A5
CR5A4
CR5A3
CR5A2
CR5A1
CR5A0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 5 comparison data A
CR5A15 = MSB
CR5A0 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W00481A8
(HW)
16-bit timer 5
comparison
register A
0 to 65535CR5B15
CR5B14
CR5B13
CR5B12
CR5B11
CR5B10
CR5B9
CR5B8
CR5B7
CR5B6
CR5B5
CR5B4
CR5B3
CR5B2
CR5B1
CR5B0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 5 comparison data B
CR5B15 = MSB
CR5B0 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W00481AA
(HW)
16-bit timer 5
comparison
register B
0 to 65535TC515
TC514
TC513
TC512
TC511
TC510
TC59
TC58
TC57
TC56
TC55
TC54
TC53
TC52
TC51
TC50
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 5 counter data
TC515 = MSB
TC50 = LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R00481AC
(HW)
16-bit timer 5
counter data
register
–
SELFM5
SELCRB5
OUTINV5
CKSL5
PTM5
PRESET5
PRUN5
D7
D6
D5
D4
D3
D2
D1
D0
reserved
16-bit timer 5 fine mode selection
16-bit timer 5 comparison buffer
16-bit timer 5 output inversion
16-bit timer 5 input clock selection
16-bit timer 5 clock output control
16-bit timer 5 reset
16-bit timer 5 Run/Stop control
0
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
W
R/W
0 when being read.
0 when being read.
00481AE
(B) –
1 Enabled 0 Disabled
1 Fine mode 0 Normal
1 Invert 0 Normal
1
External clock
0
Internal clock
1 On 0 Off
1 Reset 0 Invalid
1 Run 0 Stop
16-bit timer 5
control register
APPENDIX: I/O MAP
B-APPENDIX-34 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
DBASEL15
DBASEL14
DBASEL13
DBASEL12
DBASEL11
DBASEL10
DBASEL9
DBASEL8
DBASEL7
DBASEL6
DBASEL5
DBASEL4
DBASEL3
DBASEL2
DBASEL1
DBASEL0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
IDMA base address
low-order 16 bits
(Initial value: 0x0C003A0)
0
0
0
0
0
0
1
1
1
0
1
0
0
0
0
0
R/W0048200
(HW)
IDMA base
address low-
order register
––
DBASEH11
DBASEH10
DBASEH9
DBASEH8
DBASEH7
DBASEH6
DBASEH5
DBASEH4
DBASEH3
DBASEH2
DBASEH1
DBASEH0
DF–C
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
IDMA base address
high-order 12 bits
(Initial value: 0x0C003A0)
–
0
0
0
0
1
1
0
0
0
0
0
0
–
R/W Undefined in read.0048202
(HW)
IDMA base
address
high-order
register
0 to 127
DSTART
DCHN
D7
D6–0 IDMA start
IDMA channel number 1 IDMA start 0 Stop 0
0R/W
R/W
0048204
(B)
IDMA start
register
––
IDMAEN
D7–1
D0 reserved
IDMA enable 1 Enabled 0 Disabled –
0–
R/W
0048205
(B)
IDMA enable
register
APPENDIX: I/O MAP
S1C33L03 FUNCTION PART EPSON B-APPENDIX-35
A-1
B-ap
NameAddressRegister name Bit Function Setting Init. R/W Remarks
TC0_L7
TC0_L6
TC0_L5
TC0_L4
TC0_L3
TC0_L2
TC0_L1
TC0_L0
BLKLEN07
BLKLEN06
BLKLEN05
BLKLEN04
BLKLEN03
BLKLEN02
BLKLEN01
BLKLEN00
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.0 transfer c
ounter[7:0]
(block transfer mode)
Ch.0 transfer counter[15:8]
(single/successive transfer mode)
Ch.0 block length
(block transfer mode)
Ch.0 transfer counter[7:0]
(single/successive transfer mode)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
0048220
(HW)
High-speed
DMA Ch.0
transfer
counter
register
–
–
DUALM0
D0DIR
–
TC0_H7
TC0_H6
TC0_H5
TC0_H4
TC0_H3
TC0_H2
TC0_H1
TC0_H0
DF
DE
DD–8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.0 address mode selection
D) Invalid
S) Ch.0 transfer direction control
reserved
Ch.0 transfer counter[15:8]
(block transfer mode)
Ch.0 transfer counter[23:16]
(single/successive transfer mode)
1 Dual addr 0 Single addr
1
Memory WR
0
Memory RD
0
–
0
–
X
X
X
X
X
X
X
X
R/W
–
R/W
–
R/W Undefined in read.
0048222
(HW)
High-speed
DMA Ch.0
control register
Note:
D) Dual address
mode
S) Single
address
mode
S0ADRL15
S0ADRL14
S0ADRL13
S0ADRL12
S0ADRL11
S0ADRL10
S0ADRL9
S0ADRL8
S0ADRL7
S0ADRL6
S0ADRL5
S0ADRL4
S0ADRL3
S0ADRL2
S0ADRL1
S0ADRL0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D) Ch.0 source address[15:0]
S) Ch.0 memory address[15:0] X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048224
(HW)
High-speed
DMA Ch.0
low-order
source address
set-up register
Note:
D) Dual address
mode
S) Single
address
mode
–
DATSIZE0
S0IN1
S0IN0
S0ADRH11
S0ADRH10
S0ADRH9
S0ADRH8
S0ADRH7
S0ADRH6
S0ADRH5
S0ADRH4
S0ADRH3
S0ADRH2
S0ADRH1
S0ADRH0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Ch.0 transfer data size
D) Ch.0 source address control
S) Ch.0 memory address control
D) Ch.0 source address[27:16]
S) Ch.0 memory address[27:16]
–
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
–
R/W
R/W
R/W
0048226
(HW) 1 Half word 0 Byte
High-speed
DMA Ch.0
high-order
source address
set-up register
Note:
D) Dual address
mode
S) Single
address
mode
1
1
0
0
1
0
1
0
S0IN[1:0] Inc/dec
Inc.(no init)
Inc.(init)
Dec.(no init)
Fixed
–
APPENDIX: I/O MAP
B-APPENDIX-36 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
D0ADRL15
D0ADRL14
D0ADRL13
D0ADRL12
D0ADRL11
D0ADRL10
D0ADRL9
D0ADRL8
D0ADRL7
D0ADRL6
D0ADRL5
D0ADRL4
D0ADRL3
D0ADRL2
D0ADRL1
D0ADRL0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D) Ch.0 destination address[15:0]
S) Invalid X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048228
(HW)
High-speed
DMA Ch.0
low-order
destination
address set-up
register
Note:
D) Dual address
mode
S) Single
address
mode
D0MOD1
D0MOD0
D0IN1
D0IN0
D0ADRH11
D0ADRH10
D0ADRH9
D0ADRH8
D0ADRH7
D0ADRH6
D0ADRH5
D0ADRH4
D0ADRH3
D0ADRH2
D0ADRH1
D0ADRH0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.0 transfer mode
D) Ch.0 destination address
control
S) Invalid
D) Ch.0 destination
address[27:16]
S) Invalid
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
004822A
(HW)
High-speed
DMA Ch.0
high-order
destination
address set-up
register
Note:
D) Dual address
mode
S) Single
address
mode
1
1
0
0
1
0
1
0
D0MOD[1:0] Mode
Invalid
Block
Successive
Single
1
1
0
0
1
0
1
0
D0IN[1:0] Inc/dec
Inc.(no init)
Inc.(init)
Dec.(no init)
Fixed
––
HS0_EN
DF–1
D0
reserved
Ch.0 enable 1 Enable 0 Disable
–
0
–
R/W
Undefined in read.004822C
(HW)
High-speed
DMA Ch.0
enable register
––
HS0_TF
DF–1
D0
reserved
Ch.0 trigger flag clear (writing)
Ch.0 trigger flag status (reading) 1 Clear 0
No operation
1 Set 0 Cleared
–
0
–
R/W
Undefined in read.004822E
(HW)
High-speed
DMA Ch.0
trigger flag
register
APPENDIX: I/O MAP
S1C33L03 FUNCTION PART EPSON B-APPENDIX-37
A-1
B-ap
NameAddressRegister name Bit Function Setting Init. R/W Remarks
TC1_L7
TC1_L6
TC1_L5
TC1_L4
TC1_L3
TC1_L2
TC1_L1
TC1_L0
BLKLEN17
BLKLEN16
BLKLEN15
BLKLEN14
BLKLEN13
BLKLEN12
BLKLEN11
BLKLEN10
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.1 transfer c
ounter[7:0]
(block transfer mode)
Ch.1 transfer counter[15:8]
(single/successive transfer mode)
Ch.1 block length
(block transfer mode)
Ch.1 transfer counter[7:0]
(single/successive transfer mode)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
0048230
(HW)
High-speed
DMA Ch.1
transfer
counter
register
–
–
DUALM1
D1DIR
–
TC1_H7
TC1_H6
TC1_H5
TC1_H4
TC1_H3
TC1_H2
TC1_H1
TC1_H0
DF
DE
DD–8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.1 address mode selection
D) Invalid
S) Ch.1 transfer direction control
reserved
Ch.1 transfer counter[15:8]
(block transfer mode)
Ch.1 transfer counter[23:16]
(single/successive transfer mode)
1 Dual addr 0 Single addr
1
Memory WR
0
Memory RD
0
–
0
–
X
X
X
X
X
X
X
X
R/W
–
R/W
–
R/W Undefined in read.
0048232
(HW)
High-speed
DMA Ch.1
control register
Note:
D) Dual address
mode
S) Single
address
mode
S1ADRL15
S1ADRL14
S1ADRL13
S1ADRL12
S1ADRL11
S1ADRL10
S1ADRL9
S1ADRL8
S1ADRL7
S1ADRL6
S1ADRL5
S1ADRL4
S1ADRL3
S1ADRL2
S1ADRL1
S1ADRL0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D) Ch.1 source address[15:0]
S) Ch.1 memory address[15:0] X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048234
(HW)
High-speed
DMA Ch.1
low-order
source address
set-up register
Note:
D) Dual address
mode
S) Single
address
mode
–
DATSIZE1
S1IN1
S1IN0
S1ADRH11
S1ADRH10
S1ADRH9
S1ADRH8
S1ADRH7
S1ADRH6
S1ADRH5
S1ADRH4
S1ADRH3
S1ADRH2
S1ADRH1
S1ADRH0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Ch.1 transfer data size
D) Ch.1 source address control
S) Ch.1 memory address control
D) Ch.1 source address[27:16]
S) Ch.1 memory address[27:16]
–
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
–
R/W
R/W
R/W
0048236
(HW) 1 Half word 0 Byte
High-speed
DMA Ch.1
high-order
source address
set-up register
Note:
D) Dual address
mode
S) Single
address
mode
1
1
0
0
1
0
1
0
S1IN[1:0] Inc/dec
Inc.(no init)
Inc.(init)
Dec.(no init)
Fixed
–
APPENDIX: I/O MAP
B-APPENDIX-38 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
D1ADRL15
D1ADRL14
D1ADRL13
D1ADRL12
D1ADRL11
D1ADRL10
D1ADRL9
D1ADRL8
D1ADRL7
D1ADRL6
D1ADRL5
D1ADRL4
D1ADRL3
D1ADRL2
D1ADRL1
D1ADRL0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D) Ch.1 destination address[15:0]
S) Invalid X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048238
(HW)
High-speed
DMA Ch.1
low-order
destination
address set-up
register
Note:
D) Dual address
mode
S) Single
address
mode
D1MOD1
D1MOD0
D1IN1
D1IN0
D1ADRH11
D1ADRH10
D1ADRH9
D1ADRH8
D1ADRH7
D1ADRH6
D1ADRH5
D1ADRH4
D1ADRH3
D1ADRH2
D1ADRH1
D1ADRH0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.1 transfer mode
D) Ch.1 destination address
control
S) Invalid
D) Ch.1 destination
address[27:16]
S) Invalid
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
004823A
(HW)
High-speed
DMA Ch.1
high-order
destination
address set-up
register
Note:
D) Dual address
mode
S) Single
address
mode
1
1
0
0
1
0
1
0
D1MOD[1:0] Mode
Invalid
Block
Successive
Single
1
1
0
0
1
0
1
0
D1IN[1:0] Inc/dec
Inc.(no init)
Inc.(init)
Dec.(no init)
Fixed
––
HS1_EN
DF–1
D0
reserved
Ch.1 enable 1 Enable 0 Disable
–
0
–
R/W
Undefined in read.004823C
(HW)
High-speed
DMA Ch.1
enable register
––
HS1_TF
DF–1
D0
reserved
Ch.1 trigger flag clear (writing)
Ch.1 trigger flag status (reading) 1 Clear 0
No operation
1 Set 0 Cleared
–
0
–
R/W
Undefined in read.004823E
(HW)
High-speed
DMA Ch.1
trigger flag
register
APPENDIX: I/O MAP
S1C33L03 FUNCTION PART EPSON B-APPENDIX-39
A-1
B-ap
NameAddressRegister name Bit Function Setting Init. R/W Remarks
TC2_L7
TC2_L6
TC2_L5
TC2_L4
TC2_L3
TC2_L2
TC2_L1
TC2_L0
BLKLEN27
BLKLEN26
BLKLEN25
BLKLEN24
BLKLEN23
BLKLEN22
BLKLEN21
BLKLEN20
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.2 transfer c
ounter[7:0]
(block transfer mode)
Ch.2 transfer counter[15:8]
(single/successive transfer mode)
Ch.2 block length
(block transfer mode)
Ch.2 transfer counter[7:0]
(single/successive transfer mode)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
0048240
(HW)
High-speed
DMA Ch.2
transfer
counter
register
–
–
DUALM2
D2DIR
–
TC2_H7
TC2_H6
TC2_H5
TC2_H4
TC2_H3
TC2_H2
TC2_H1
TC2_H0
DF
DE
DD–8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.2 address mode selection
D) Invalid
S) Ch.2 transfer direction control
reserved
Ch.2 transfer counter[15:8]
(block transfer mode)
Ch.2 transfer counter[23:16]
(single/successive transfer mode)
1 Dual addr 0 Single addr
1
Memory WR
0
Memory RD
0
–
0
–
X
X
X
X
X
X
X
X
R/W
–
R/W
–
R/W Undefined in read.
0048242
(HW)
High-speed
DMA Ch.2
control register
Note:
D) Dual address
mode
S) Single
address
mode
S2ADRL15
S2ADRL14
S2ADRL13
S2ADRL12
S2ADRL11
S2ADRL10
S2ADRL9
S2ADRL8
S2ADRL7
S2ADRL6
S2ADRL5
S2ADRL4
S2ADRL3
S2ADRL2
S2ADRL1
S2ADRL0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D) Ch.2 source address[15:0]
S) Ch.2 memory address[15:0] X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048244
(HW)
High-speed
DMA Ch.2
low-order
source address
set-up register
Note:
D) Dual address
mode
S) Single
address
mode
–
DATSIZE2
S2IN1
S2IN0
S2ADRH11
S2ADRH10
S2ADRH9
S2ADRH8
S2ADRH7
S2ADRH6
S2ADRH5
S2ADRH4
S2ADRH3
S2ADRH2
S2ADRH1
S2ADRH0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Ch.2 transfer data size
D) Ch.2 source address control
S) Ch.2 memory address control
D) Ch.2 source address[27:16]
S) Ch.2 memory address[27:16]
–
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
–
R/W
R/W
R/W
0048246
(HW) 1 Half word 0 Byte
High-speed
DMA Ch.2
high-order
source address
set-up register
Note:
D) Dual address
mode
S) Single
address
mode
1
1
0
0
1
0
1
0
S2IN[1:0] Inc/dec
Inc.(no init)
Inc.(init)
Dec.(no init)
Fixed
–
APPENDIX: I/O MAP
B-APPENDIX-40 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
D2ADRL15
D2ADRL14
D2ADRL13
D2ADRL12
D2ADRL11
D2ADRL10
D2ADRL9
D2ADRL8
D2ADRL7
D2ADRL6
D2ADRL5
D2ADRL4
D2ADRL3
D2ADRL2
D2ADRL1
D2ADRL0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D) Ch.2 destination address[15:0]
S) Invalid X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048248
(HW)
High-speed
DMA Ch.2
low-order
destination
address set-up
register
Note:
D) Dual address
mode
S) Single
address
mode
D2MOD1
D2MOD0
D2IN1
D2IN0
D2ADRH11
D2ADRH10
D2ADRH9
D2ADRH8
D2ADRH7
D2ADRH6
D2ADRH5
D2ADRH4
D2ADRH3
D2ADRH2
D2ADRH1
D2ADRH0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.2 transfer mode
D) Ch.2 destination address
control
S) Invalid
D) Ch.2 destination
address[27:16]
S) Invalid
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
004824A
(HW)
High-speed
DMA Ch.2
high-order
destination
address set-up
register
Note:
D) Dual address
mode
S) Single
address
mode
1
1
0
0
1
0
1
0
D2MOD[1:0] Mode
Invalid
Block
Successive
Single
1
1
0
0
1
0
1
0
D2IN[1:0] Inc/dec
Inc.(no init)
Inc.(init)
Dec.(no init)
Fixed
––
HS2_EN
DF–1
D0
reserved
Ch.2 enable 1 Enable 0 Disable
–
0
–
R/W
Undefined in read.004824C
(HW)
High-speed
DMA Ch.2
enable register
––
HS2_TF
DF–1
D0
reserved
Ch.2 trigger flag clear (writing)
Ch.2 trigger flag status (reading) 1 Clear 0
No operation
1 Set 0 Cleared
–
0
–
R/W
Undefined in read.004824E
(HW)
High-speed
DMA Ch.2
trigger flag
register
APPENDIX: I/O MAP
S1C33L03 FUNCTION PART EPSON B-APPENDIX-41
A-1
B-ap
NameAddressRegister name Bit Function Setting Init. R/W Remarks
TC3_L7
TC3_L6
TC3_L5
TC3_L4
TC3_L3
TC3_L2
TC3_L1
TC3_L0
BLKLEN37
BLKLEN36
BLKLEN35
BLKLEN34
BLKLEN33
BLKLEN32
BLKLEN31
BLKLEN30
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.3 transfer c
ounter[7:0]
(block transfer mode)
Ch.3 transfer counter[15:8]
(single/successive transfer mode)
Ch.3 block length
(block transfer mode)
Ch.3 transfer counter[7:0]
(single/successive transfer mode)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
0048250
(HW)
High-speed
DMA Ch.3
transfer
counter
register
–
–
DUALM3
D3DIR
–
TC3_H7
TC3_H6
TC3_H5
TC3_H4
TC3_H3
TC3_H2
TC3_H1
TC3_H0
DF
DE
DD–8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.3 address mode selection
D) Invalid
S) Ch.3 transfer direction control
reserved
Ch.3 transfer counter[15:8]
(block transfer mode)
Ch.3 transfer counter[23:16]
(single/successive transfer mode)
1 Dual addr 0 Single addr
1
Memory WR
0
Memory RD
0
–
0
–
X
X
X
X
X
X
X
X
R/W
–
R/W
–
R/W Undefined in read.
0048252
(HW)
High-speed
DMA Ch.3
control register
Note:
D) Dual address
mode
S) Single
address
mode
S3ADRL15
S3ADRL14
S3ADRL13
S3ADRL12
S3ADRL11
S3ADRL10
S3ADRL9
S3ADRL8
S3ADRL7
S3ADRL6
S3ADRL5
S3ADRL4
S3ADRL3
S3ADRL2
S3ADRL1
S3ADRL0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D) Ch.3 source address[15:0]
S) Ch.3 memory address[15:0] X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048254
(HW)
High-speed
DMA Ch.3
low-order
source address
set-up register
Note:
D) Dual address
mode
S) Single
address
mode
–
DATSIZE3
S3IN1
S3IN0
S3ADRH11
S3ADRH10
S3ADRH9
S3ADRH8
S3ADRH7
S3ADRH6
S3ADRH5
S3ADRH4
S3ADRH3
S3ADRH2
S3ADRH1
S3ADRH0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Ch.3 transfer data size
D) Ch.3 source address control
S) Ch.3 memory address control
D) Ch.3 source address[27:16]
S) Ch.3 memory address[27:16]
–
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
–
R/W
R/W
R/W
0048256
(HW) 1 Half word 0 Byte
High-speed
DMA Ch.3
high-order
source address
set-up register
Note:
D) Dual address
mode
S) Single
address
mode
1
1
0
0
1
0
1
0
S3IN[1:0] Inc/dec
Inc.(no init)
Inc.(init)
Dec.(no init)
Fixed
–
APPENDIX: I/O MAP
B-APPENDIX-42 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
D3ADRL15
D3ADRL14
D3ADRL13
D3ADRL12
D3ADRL11
D3ADRL10
D3ADRL9
D3ADRL8
D3ADRL7
D3ADRL6
D3ADRL5
D3ADRL4
D3ADRL3
D3ADRL2
D3ADRL1
D3ADRL0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D) Ch.3 destination address[15:0]
S) Invalid X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W0048258
(HW)
High-speed
DMA Ch.3
low-order
destination
address set-up
register
Note:
D) Dual address
mode
S) Single
address
mode
D3MOD1
D3MOD0
D3IN1
D3IN0
D3ADRH11
D3ADRH10
D3ADRH9
D3ADRH8
D3ADRH7
D3ADRH6
D3ADRH5
D3ADRH4
D3ADRH3
D3ADRH2
D3ADRH1
D3ADRH0
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Ch.3 transfer mode
D) Ch.3 destination address
control
S) Invalid
D) Ch.3 destination
address[27:16]
S) Invalid
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
004825A
(HW)
High-speed
DMA Ch.3
high-order
destination
address set-up
register
Note:
D) Dual address
mode
S) Single
address
mode
1
1
0
0
1
0
1
0
D3MOD[1:0] Mode
Invalid
Block
Successive
Single
1
1
0
0
1
0
1
0
D3IN[1:0] Inc/dec
Inc.(no init)
Inc.(init)
Dec.(no init)
Fixed
––
HS3_EN
DF–1
D0
reserved
Ch.3 enable 1 Enable 0 Disable
–
0
–
R/W
Undefined in read.004825C
(HW)
High-speed
DMA Ch.3
enable register
––
HS3_TF
DF–1
D0
reserved
Ch.3 trigger flag clear (writing)
Ch.3 trigger flag status (reading) 1 Clear 0
No operation
1 Set 0 Cleared
–
0
–
R/W
Undefined in read.004825E
(HW)
High-speed
DMA Ch.3
trigger flag
register
APPENDIX: I/O MAP
S1C33L03 FUNCTION PART EPSON B-APPENDIX-43
A-1
B-ap
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
–
SDRAR0
SDRAR1
–
SDRPC0
SDRPC1
–
D7
D6
D5–4
D3
D2
D1–0
Area 7/13 configuration
Area 8/14 configuration
reserved
#CE7/13 pin configuration
#CE8/14 pin configuration
reserved
0
0
–
0
0
–
R/W
R/W
–
R/W
R/W
–
0 when being read.
0 when being read.
039FFC0
(B) 1SDRAM 0
Not SDRAM
1SDRAM 0
Not SDRAM
1#SDCE0 0#CE7/13
1#SDCE1 0#CE8/14
SDRAM area
configuration
register
–
SDRENA
SDRINI
SDRSRF
SDRIS
SDRCLK
–
D7
D6
D5
D4
D3
D2–0
Enable SDRAM signals
Start SDRAM power up
Enable SDRAM self-refresh
Initial command sequence
Keep SDCLK during self-refresh
reserved
0
0
0
0
1
–
R/W
R/W
R/W
R/W
R/W
–
0 when being read.
0 when being read.
039FFC1
(B) 1Enabled 0Disabled
1Start 0 –
11 precharge
2 set reg.
3 refresh
01 precharge
2 refresh
3 set reg.
1Enabled 0Disabled
1Kept 0Stopped
SDRAM
control register
–
–
––
SDRCA1
SDRCA0
–
SDRRA1
SDRRA0
SDRBA
–
D7
D6–5
D4
D3–2
D1
D0
reserved
SDRAM page size
(column range)
reserved
SDRAM row addressing range
Number of SDRAM banks
reserved
–
0
0
–
0
0
0
–
–
R/W
–
R/W
R/W
–
0 when being read.
0 when being read.
0 when being read.
039FFC2
(B)
14 banks 02 banks
SDRAM
address
configuration
register
1
1
0
0
1
0
1
0
SDRRA[1:0] Addressing range
reserved
8K (SDA[12:0])
4K (SDA[11:0])
2K (SDA[10:0])
1
1
0
0
1
0
1
0
SDRCA[1:0] Page size
reserved
1K (SDA[9:0])
512 (SDA[8:0])
256 (SDA[7:0])
–
–
––
SDRCL1
SDRCL0
–
SDRBL1
SDRBL0
–
D7
D6–5
D4
D3–2
D1–0
reserved
SDRAM CAS latency
reserved
SDRAM burst length
reserved
–
1
1
–
1
1
–
–
R/W
–
R/W
–
0 when being read.
0 when being read.
0 when being read.
039FFC3
(B)
SDRAM
mode set-up
register 1 0
SDRCL[1:0] CAS latency
2 CAS latency
1
1
0
0
1
0
1
0
SDRBL[1:0] Burst length
8
4
2
1
SDRTRAS2
SDRTRAS1
SDRTRAS0
SDRTRP1
SDRTRP0
SDRTRC2
SDRTRC1
SDRTRC0
D7–5
D4–3
D2–0
SDRAM t
RAS
spec
SDRAM t
RP
spec
SDRAM t
RC
spec
0
0
0
0
0
0
0
0
R/W
R/W
R/W
039FFC4
(B)
SDRAM
timing set-up
register 1 1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
SDRTRAS[2:0]
Number of clocks
7
6
5
4
3
2
1
8
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
SDRTRC[2:0]
Number of clocks
7
6
5
4
3
2
1
8
1
1
0
0
1
0
1
0
SDRTRP[1:0]
Number of clocks
3
2
1
4
APPENDIX: I/O MAP
B-APPENDIX-44 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
SDRTRCD1
SDRTRCD0
SDRTRSC
SDRTRRD1
SDRTRRD0
–
D7–6
D5
D4–3
D2–0
SDRAM t
RCD
spec
SDRAM t
RSC
spec
SDRAM t
RRD
spec
reserved
0
0
0
0
0
–
R/W
R/W
R/W
–0 when being read.
039FFC5
(B)
SDRAM
timing set-up
register 2 1
1
0
0
1
0
1
0
SDRTRCD[1:0]
Number of clocks
3
2
1
4
1
1
0
0
1
0
1
0
SDRTRRD[1:0]
Number of clocks
3
2
1
4
–
11 clock 02 clocks
–
SDRARFC11
SDRARFC10
SDRARFC9
SDRARFC8
SDRARFC7
SDRARFC6
SDRARFC5
SDRARFC4
SDRARFC3
SDRARFC2
SDRARFC1
SDRARFC0
DF–C
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
reserved
SDRAM auto refresh count [11:0] –
1
1
1
1
1
1
1
1
1
1
1
1
–
R/W 0 when being read.039FFC6
(HW)
SDRAM
auto refresh
count register 0 to 4096
–
–
SDRSRFC3
SDRSRFC2
SDRSRFC1
SDRSRFC0
D7–4
D3
D2
D1
D0
reserved
SDRAM self refresh count [3:0] –
1
1
1
1
–
R/W 0 when being read.
This register must
not be set less than
"0x02".
039FFC8
(B)
SDRAM
self refresh
count register 2 to 15
–
–
––
SDRSZ
SDRBI
–
D7
D6
D5
D4–0
reserved
SDRAM data path bit width
SDRAM bank interleaved access
reserved
–
0
0
–
–
R/W
R/W
–
0 when being read.
0 when being read.
039FFC9
(B) 18 bits 016 bits
1Interleaved 0One bank
SDRAM
advanced
control
register
–
SDRMRS
SDRSRM
–
D7
D6
D5–0
SDRAM mode register set flag
SDRAM current refresh mode
reserved
1
1
–
R
R
–0 when being read.
039FFCA
(B) 1Not finished 0Done
1
Auto refresh
0Self refresh
SDRAM
status register
APPENDIX: I/O MAP
S1C33L03 FUNCTION PART EPSON B-APPENDIX-45
A-1
B-ap
NameAddressRegister name Bit Function Setting Init. R/W Remarks
PCODE5
PCODE4
PCODE3
PCODE2
PCODE1
PCODE0
RCODE1
RCODE0
D7
D6
D5
D4
D3
D2
D1
D0
Product code
Revision code
0
0
0
0
1
0
0
0
R
R
039FFE0
(B)
Revision code
register 0b000010
–
–
–
LDCOLOR
–
FPSMASK
LDDW1
LDDW0
D7–6
D5
D4–3
D2
D1
D0
reserved
Color/monochrome select
reserved
Mask FPSHIFT signal
LCD data width/format
–
0
–
0
0
0
–
R/W
–
R/W
R/W
0 when being read.
0 when being read.
039FFE1
(B) 1Color 0Mono
1Masked 0Output
LCDC mode
register 0
1
0
0
x
1
0
LDDW[1:0] Monochrome
reserved
8 bits
4 bits
1
1
0
0
1
0
1
0
LDDW[1:0] Color
8 bits/format 2
reserved
8 bits/format 1
4 bits
–
–
BPP1
BPP0
–
DBLANK
FRMRPT
–
INVDISP
D7
D6
D5–4
D3
D2
D1
D0
Bit-per-pixel select
(Display mode)
reserved
Blank display
Frame repeat for EL panel
reserved
Invert display
0
0
–
0
0
–
0
R/W
–
R/W
R/W
–
R/W
0 when being read.
0 when being read.
039FFE2
(B)
1Repeated 0
Not repeated
1Inverted 0Normal
1Blank 0Normal
LCDC mode
register 1 1
1
0
0
1
0
1
0
BPP[1:0] Mode
8 bpp
4 bpp
2 bpp
1 bpp
–
–
–
LCDCEN
LPWREN
–
LPSAVE1
LPSAVE0
D7–6
D5
D4
D3–2
D1
D0
reserved
LCD controller enable
LCDPWR enable
reserved
Power save mode
–
0
0
–
0
0
–
R/W
R/W
–
R/W
0 when being read.
0 when being read.
039FFE3
(B) 1Enabled 0Disabled
1Enabled 0Disabled
LCDC mode
register 2
1
1
0
0
1
0
1
0
LPSAVE[1:0] Mode
Normal operation
Doze
reserved
Power save
–
LDHSIZE5
LDHSIZE4
LDHSIZE3
LDHSIZE2
LDHSIZE1
LDHSIZE0
D7–6
D5
D4
D3
D2
D1
D0
reserved
Horizontal panel size –
0
0
0
0
0
0
–
R/W 0 when being read.039FFE4
(B)
Horizontal
panel size
register
–
H resolution (pixels) - 1
16
LDVSIZE7
LDVSIZE6
LDVSIZE5
LDVSIZE4
LDVSIZE3
LDVSIZE2
LDVSIZE1
LDVSIZE0
D7
D6
D5
D4
D3
D2
D1
D0
Vertical panel size
(low-order 8 bits) 0
0
0
0
0
0
0
0
R/W039FFE5
(B)
Vertical
panel size
register 0
V resolution (lines) - 1
–
LDVSIZE9
LDVSIZE8
D7–2
D1
D0
reserved
Vertical panel size
(high-order 2 bits)
–
0
0
–
R/W 0 when being read.039FFE6
(B)
Vertical
panel size
register 1
–
V resolution (lines) - 1
–
HNDP4
HNDP3
HNDP2
HNDP1
HNDP0
D7–5
D4
D3
D2
D1
D0
reserved
Horizontal non-display period –
0
0
0
0
0
–
R/W 0 when being read.039FFE7
(B)
Horizontal
non-display
period register
–
Non-display period (pixels) - 4
8
APPENDIX: I/O MAP
B-APPENDIX-46 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
VNDPF
–
VNDP5
VNDP4
VNDP3
VNDP2
VNDP1
VNDP0
D7
D6
D5
D4
D3
D2
D1
D0
Vertical non-display period status
reserved
Vertical non-display period
0
–
0
0
0
0
0
0
R
–
R/W 0 when being read.
039FFEA
(B)
Vertical
non-display
period register –
Non display period (lines)
1VNDP 0Display
–
MODRATE5
MODRATE4
MODRATE3
MODRATE2
MODRATE1
MODRATE0
D7–6
D5
D4
D3
D2
D1
D0
reserved
MOD rate –
0
0
0
0
0
0
–
R/W 0 when being read.039FFEB
(B)
MOD rate
register –
S1ADDR7
S1ADDR6
S1ADDR5
S1ADDR4
S1ADDR3
S1ADDR2
S1ADDR1
S1ADDR0
D7
D6
D5
D4
D3
D2
D1
D0
Screen 1 start address
(low-order 8 bits) 0
0
0
0
0
0
0
0
R/W039FFEC
(B)
Screen 1
start address
register 0
S1ADDR15
S1ADDR14
S1ADDR13
S1ADDR12
S1ADDR11
S1ADDR10
S1ADDR9
S1ADDR8
D7
D6
D5
D4
D3
D2
D1
D0
Screen 1 start address
(high-order 8 bits) 0
0
0
0
0
0
0
0
R/W039FFED
(B)
Screen 1
start address
register 1
S2ADDR7
S2ADDR6
S2ADDR5
S2ADDR4
S2ADDR3
S2ADDR2
S2ADDR1
S2ADDR0
D7
D6
D5
D4
D3
D2
D1
D0
Screen 2 start address
(low-order 8 bits) 0
0
0
0
0
0
0
0
R/W039FFEE
(B)
Screen 2
start address
register 0
S2ADDR15
S2ADDR14
S2ADDR13
S2ADDR12
S2ADDR11
S2ADDR10
S2ADDR9
S2ADDR8
D7
D6
D5
D4
D3
D2
D1
D0
Screen 2 start address
(high-order 8 bits) 0
0
0
0
0
0
0
0
R/W039FFEF
(B)
Screen 2
start address
register 1
–
S1ADDR16
D7–1
D0 reserved
Screen 1 start address (MSB)
(for portrait mode;
fix at 0 in landscape mode)
–
0–
R/W 0 when being read.039FFF0
(B)
Screen 1
start address
register 2
–
MADOFS7
MADOFS6
MADOFS5
MADOFS4
MADOFS3
MADOFS2
MADOFS1
MADOFS0
D7
D6
D5
D4
D3
D2
D1
D0
Memory address offset 0
0
0
0
0
0
0
0
R/W039FFF1
(B)
Memory
address offset
register
S1VSIZE7
S1VSIZE6
S1VSIZE5
S1VSIZE4
S1VSIZE3
S1VSIZE2
S1VSIZE1
S1VSIZE0
D7
D6
D5
D4
D3
D2
D1
D0
Screen 1 vertical size
(low-order 8 bits) 0
0
0
0
0
0
0
0
R/W039FFF2
(B)
Screen 1
vertical size
register 0
APPENDIX: I/O MAP
S1C33L03 FUNCTION PART EPSON B-APPENDIX-47
A-1
B-ap
NameAddressRegister name Bit Function Setting Init. R/W Remarks
–
S1VSIZE9
S1VSIZE8
D7–2
D1
D0
reserved
Screen 1 vertical size
(high-order 2 bits)
–
0
0
–
R/W 0 when being read.039FFF3
(B)
Screen 1
vertical size
register 1
–
–
FIFOEO3
FIFOEO2
FIFOEO1
FIFOEO0
LCLKSEL2
LCLKSEL1
LCLKSEL0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
FIFO empty offset
LCDC clock select
–
0
0
0
0
0
0
0
–
R/W
R/W
0 when being read.039FFF4
(B)
FIFO control
register –
Fix at 8 (0b1000)
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
LCLKSEL[2:0]
LCDC clock
BCU_CLK/4
BCU_CLK/3
BCU_CLK/2
BCU_CLK
reserved
Stop
Stop
Stop
–
LUTADDR3
LUTADDR2
LUTADDR1
LUTADDR0
D7–4
D3
D2
D1
D0
reserved
Look-up table address –
0
0
0
0
–
R/W 0 when being read.039FFF5
(B)
Look-up table
address
register
–
LUTDT3
LUTDT2
LUTDT1
LUTDT0
–
D7
D6
D5
D4
D3–0
Look-up table data
reserved
0
0
0
0
–
R/W
–0 when being read.
039FFF7
(B)
Look-up table
data register
–
–
GPIO2C
GPIO1C
GPIO0C
D7–3
D2
D1
D0
reserved
GPIO2 configuration
GPIO1 configuration
GPIO0 configuration
–
0
0
0
–
R/W
R/W
R/W
0 when being read.039FFF8
(B)
GPIO
configuration
register
–
1Output 0Input
1Output 0Input
1Output 0Input
–
GPO6D
GPO5D
GPO4D
GPO3D
GPIO2D
GPIO1D
GPIO0D
D7
D6
D5
D4
D3
D2
D1
D0
reserved
GPO6 data
GPO5 data
GPO4 data
GPO3 data
GPIO2 data
GPIO1 data
GPIO0 data
–
0
0
0
0
0
0
0
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 when being read.039FFF9
(B)
GPIO
status/control
register
–
1High 0Low
1High 0Low
1High 0Low
1High 0Low
1High 0Low
1High 0Low
1High 0Low
SP1A7
SP1A6
SP1A5
SP1A4
SP1A3
SP1A2
SP1A1
SP1A0
D7
D6
D5
D4
D3
D2
D1
D0
Scratch pad 0
0
0
0
0
0
0
0
R/W039FFFA
(B)
Scratch pad
register
–
PMODEN
PMODSEL
–
PMODCLK1
PMODCLK0
D7
D6
D5–2
D1
D0
Portrait mode enable
Portrait mode select
reserved
Portrait mode clock select
(LCDC clock division ratio)
Division ratio 1: Default mode
Division ratio 2: Alternate mode
P: Pixel clock, M: Memory clock
0
0
–
0
0
R/W
R/W
–
R/W 0 when being read.
039FFFB
(B) 1 Portrait 0 Landscape
1Alternate 0Default
Portrait mode
register
1
1
0
0
1
0
1
0
PMODCLK[1:0]
Division ratio 1
P: 1/8, M: 1/8
P: 1/4, M: 1/4
P: 1/2, M: 1/2
P: 1/1, M: 1/1
1
1
0
0
1
0
1
0
PMODCLK[1:0]
Division ratio 2
P: 1/8, M: 1/4
P: 1/4, M: 1/2
P: 1/2, M: 1/1
P: 1/2, M: 1/1
PMODLBC7
PMODLBC6
PMODLBC5
PMODLBC4
PMODLBC3
PMODLBC2
PMODLBC1
PMODLBC0
D7
D6
D5
D4
D3
D2
D1
D0
Line byte count 0
0
0
0
0
0
0
0
R/W039FFFC
(B)
Line byte
count register
for portrait
mode
APPENDIX: I/O MAP
B-APPENDIX-48 EPSON S1C33L03 FUNCTION PART
NameAddressRegister name Bit Function Setting Init. R/W Remarks
VRAMAR
VRAMWT2
VRAMWT1
VRAMWT0
EDMAEN
BREQEN
LCDCST
LCDCEC
D7
D6
D5
D4
D3
D2
D1
D0
VRAM area select
VRAM wait control
(number of wait cycles for SRAM)
External DMA enable
External bus-request enable
A0/BSL select
Big/little endian select
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
039FFFD
(B) 1Area 8 0Area 7
1Enabled 0Disabled
1Enabled 0Disabled
1BSL 0A0
1Big endian 0
Little endian
LCDC
system control
register 0–7
AMERICA
EPSON ELECTRONICS AMERICA, INC.
- HEADQUARTERS -
150 River Oaks Parkway
San Jose, CA 95134, U.S.A.
Phone: +1-408-922-0200 Fax: +1-408-922-0238
- SALES OFFICES -
West
1960 E. Grand Avenue
EI Segundo, CA 90245, U.S.A.
Phone: +1-310-955-5300 Fax: +1-310-955-5400
Central
101 Virginia Street, Suite 290
Crystal Lake, IL 60014, U.S.A.
Phone: +1-815-455-7630 Fax: +1-815-455-7633
Northeast
301 Edgewater Place, Suite 120
Wakefield, MA 01880, U.S.A.
Phone: +1-781-246-3600 Fax: +1-781-246-5443
Southeast
3010 Royal Blvd. South, Suite 170
Alpharetta, GA 30005, U.S.A.
Phone: +1-877-EEA-0020 Fax: +1-770-777-2637
EUROPE
EPSON EUROPE ELECTRONICS GmbH
- HEADQUARTERS -
Riesstrasse 15
80992 Munich, GERMANY
Phone: +49-(0)89-14005-0 Fax: +49-(0)89-14005-110
DÜSSELDORF BRANCH OFFICE
Altstadtstrasse 176
51379 Leverkusen, GERMANY
Phone: +49-(0)2171-5045-0 Fax: +49-(0)2171-5045-10
UK & IRELAND BRANCH OFFICE
Unit 2.4, Doncastle House, Doncastle Road
Bracknell, Berkshire RG12 8PE, ENGLAND
Phone: +44-(0)1344-381700 Fax: +44-(0)1344-381701
FRENCH BRANCH OFFICE
1 Avenue de l' Atlantique, LP 915 Les Conquerants
Z.A. de Courtaboeuf 2, F-91976 Les Ulis Cedex, FRANCE
Phone: +33-(0)1-64862350 Fax: +33-(0)1-64862355
BARCELONA BRANCH OFFICE
Barcelona Design Center
Edificio Testa, Avda. Alcalde Barrils num. 64-68
E-08190 Sant Cugat del Vallès, SPAIN
Phone: +34-93-544-2490 Fax: +34-93-544-2491
Scotland Design Center
Integration House, The Alba Campus
Livingston West Lothian, EH54 7EG, SCOTLAND
Phone: +44-1506-605040 Fax: +44-1506-605041
ASIA
EPSON (CHINA) CO., LTD.
23F, Beijing Silver Tower 2# North RD DongSanHuan
ChaoYang District, Beijing, CHINA
Phone: 64106655 Fax: 64107319
SHANGHAI BRANCH
7F, High-Tech Bldg., 900, Yishan Road
Shanghai 200233, CHINA
Phone: 86-21-5423-5577 Fax: 86-21-5423-4677
EPSON HONG KONG LTD.
20/F., Harbour Centre, 25 Harbour Road
Wanchai, Hong Kong
Phone: +852-2585-4600 Fax: +852-2827-4346
Telex: 65542 EPSCO HX
EPSON TAIWAN TECHNOLOGY & TRADING LTD.
14F, No. 7, Song Ren Road, Taipei 110
Phone: 02-8786-6688 Fax: 02-8786-6660
HSINCHU OFFICE
13F-3, No. 295, Kuang-Fu Road, Sec. 2
HsinChu 300
Phone: 03-573-9900 Fax: 03-573-9169
EPSON SINGAPORE PTE., LTD.
No. 1 Temasek Avenue, #36-00
Millenia Tower, SINGAPORE 039192
Phone: +65-6337-7911 Fax: +65-6334-2716
SEIKO EPSON CORPORATION KOREA OFFICE
50F, KLI 63 Bldg., 60 Yoido-dong
Youngdeungpo-Ku, Seoul, 150-763, KOREA
Phone: 02-784-6027 Fax: 02-767-3677
GUMI OFFICE
6F, Good Morning Securities Bldg.
56 Songjeong-Dong, Gumi-City, 730-090, KOREA
Phone: 054-454-6027 Fax: 054-454-6093
SEIKO EPSON CORPORATION
ELECTRONIC DEVICES MARKETING DIVISION
IC Marketing Department
IC Marketing & Engineering Group
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone: +81-(0)42-587-5816 Fax: +81-(0)42-587-5624
ED International Marketing Department
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone: +81-(0)42-587-5814 Fax: +81-(0)42-587-5117
International Sales Operations
In pursuit of “Saving” Technology, Epson electronic devices.
Our lineup of semiconductors, displays and quartz devices
assists in creating the products of our customers’ dreams.
Epson IS energy savings.
http://www.epsondevice.com
EPSON Electronic Devices Website
ELECTRONIC DEVICES MARKETING DIVISION
Issue April, 2003
Printed in Japan B
L
Technical Manual
S1C33L03
