1
Data sheet acquired from Harris Semiconductor
SCHS251D
Features
• Buffered Inputs
• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015
• SCR-Latchup-Resistant CMOS Process and Circuit
Design
• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
• Balanced Propagation Delays
• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
•±24mA Output Drive Current
- Fanout to 15 FAST™ ICs
- Drives 50Ω Transmission Lines
Description
The ’AC283 and ’ACT283 4-bit binary adders with fast carry
that utilize Advanced CMOS Logic technology. These
devices add two 4-bit binary numbers and generate a carry-
out bit if the sum exceeds 15.
Because of the symmetry of the add function, this device
can be used with either all active-HIGH operands (positive
logic) or with all active-LOW operands (negative logic).
When using positive logic, the carry-in input must be tied
LOW if there is no carry-in.
Pinout
CD54AC283, CD54ACT283
(CERDIP)
CD74AC283, CD74ACT283
(PDIP, SOIC)
TOP VIEW
Functional Diagram
Ordering Information
PART
NUMBER TEMP.
RANGE (oC) PACKAGE
CD54AC283F3A -55 to 125 16 Ld CERDIP
CD74AC283E 0 to 70oC, -40 to 85,
-55 to 125 16 Ld PDIP
CD74AC283M 0 to 70oC, -40 to 85,
-55 to 125 16 Ld SOIC
CD54ACT283F3A -55 to 125 16 Ld CERDIP
CD74ACT283E 0 to 70oC, -40 to 85,
-55 to 125 16 Ld PDIP
CD74ACT283M 0 to 70oC, -40 to 85,
-55 to 125 16 Ld SOIC
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local TI sales office or
customer service for ordering information.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
S1
B1
A1
S0
A0
B0
GND
CIN
VCC
A2
S2
A3
B3
S3
COUT
B2
5
6
3
2
15
11
12
14
4
9
S2
S1
A0
B0
A1
B1
B2
A3
B3
A2
7
CIN
GND = 8
VCC = 16
10
13
1
S0
S3
COUT
August 1998 - Revised May 2000
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
Copyright © 2000, Texas Instruments Incorporated
CD54/74AC283,
CD54/74ACT283
4-Bit Binary Fill Adder With Fast Carry
2
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC VCC or Ground Current, ICC or IGND (Note 3) . . . . . . . . .±100mA
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC (Note 4)
AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V
ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Slew Rate, dt/dv
AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)
AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)
ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
Thermal Impedance (Typical, Note 5) θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. For up to 4 outputs per device, add ±25mA for each additional output.
4. Unless otherwise specified, all voltages are referenced to ground.
5. The package thermal impedance is calculated in accordance with JESD 51.
DC Electrical Specifications
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC-40oC TO
85oC-55oC TO
125oC
UNITSVI(V) IO(mA) MIN MAX MIN MAX MIN MAX
AC TYPES
High Level Input Voltage VIH - - 1.5 1.2 - 1.2 - 1.2 - V
3 2.1 - 2.1 - 2.1 - V
5.5 3.85 - 3.85 - 3.85 - V
Low Level Input Voltage VIL - - 1.5 - 0.3 - 0.3 - 0.3 V
3 - 0.9 - 0.9 - 0.9 V
5.5 - 1.65 - 1.65 - 1.65 V
High Level Output Voltage VOH VIH or VIL -0.05 1.5 1.4 - 1.4 - 1.4 - V
-0.05 3 2.9 - 2.9 - 2.9 - V
-0.05 4.5 4.4 - 4.4 - 4.4 - V
-4 3 2.58 - 2.48 - 2.4 - V
-24 4.5 3.94 - 3.8 - 3.7 - V
-75
(Note 6, 7) 5.5 - - 3.85 - - - V
-50
(Note 6, 7) 5.5----3.85 - V
CD54/74AC283, CD54/74ACT283
3
Low Level Output Voltage VOL VIH or VIL 0.05 1.5 - 0.1 - 0.1 - 0.1 V
0.05 3 - 0.1 - 0.1 - 0.1 V
0.05 4.5 - 0.1 - 0.1 - 0.1 V
12 3 - 0.36 - 0.44 - 0.5 V
24 4.5 - 0.36 - 0.44 - 0.5 V
75
(Note 6, 7) 5.5 - - - 1.65 - - V
50
(Note 6, 7) 5.5-----1.65 V
Input Leakage Current IIVCC or
GND - 5.5 - ±0.1 - ±1-±1µA
Quiescent Supply Current
MSI ICC VCC or
GND 0 5.5 - 8 - 80 - 160 µA
ACT TYPES
High Level Input Voltage VIH - - 4.5 to
5.5 2-2-2-V
Low Level Input Voltage VIL - - 4.5 to
5.5 - 0.8 - 0.8 - 0.8 V
High Level Output Voltage VOH VIH or VIL -0.05 4.5 4.4 - 4.4 - 4.4 - V
-24 4.5 3.94 - 3.8 - 3.7 - V
-75
(Note 6, 7) 5.5 - - 3.85 - - - V
-50
(Note 6, 7) 5.5----3.85 - V
Low Level Output Voltage VOL VIH or VIL 0.05 4.5 - 0.1 - 0.1 - 0.1 V
24 4.5 - 0.36 - 0.44 - 0.5 V
75
(Note 6, 7) 5.5 - - - 1.65 - - V
50
(Note 6, 7) 5.5-----1.65 V
Input Leakage Current IIVCC or
GND - 5.5 - ±0.1 - ±1-±1µA
Quiescent Supply Current
MSI ICC VCC or
GND 0 5.5 - 8 - 80 - 160 µA
AdditionalSupply Currentper
Input Pin TTL Inputs High
1 Unit Load
∆ICC VCC
-2.1 - 4.5 to
5.5 - 2.4 - 2.8 - 3 mA
NOTES:
6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.
7. Test verifies a minimum 50Ω transmission-line-drive capability at 85oC, 75Ω at 125oC.
ACT Input Load Table
INPUT UNIT LOAD
A0, B0, A2, B2 1.66
A1, B1 1.9
A3, B3 1.4
CIN 1.1
NOTE: Unit load is ∆ICC limit specified in DC Electrical Specifications
Table, e.g., 2.4mA max at 25oC.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC-40oC TO
85oC-55oC TO
125oC
UNITSVI(V) IO(mA) MIN MAX MIN MAX MIN MAX
CD54/74AC283, CD54/74ACT283
4
Switching Specifications Input tr, tf = 3ns, CL= 50pF (Worst Case)
PARAMETER SYMBOL VCC (V)
-40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN TYP MAX
AC TYPES
Propagation Delay,
An or Bn to COUT
CIN to Sn
CIN to COUT
tPLH, tPHL 1.5 - - 199 - - 219 ns
3.3
(Note 9) 6.3 - 22.4 6.2 - 24.6 ns
5
(Note 10) 4.5 - 16 4.4 - 17.6 ns
Propagation Delay,
An or Bn to Sn tPLH, tPHL 1.5 - - 207 - - 228 ns
3.3 6.6 - 23.2 6.4 - 25.5 ns
5 4.7 - 16.5 4.6 - 18.2 ns
Input Capacitance CI- - -10- -10pF
Power Dissipation Capacitance CPD
(Note 11) - - 120 - - 120 - pF
ACT TYPES
Propagation Delay,
An or Bn to COUT
CIN to Sn
CIN to COUT
tPLH, tPHL 5
(Note 10) 4.5 - 16 2.7 - 17.6 ns
Propagation Delay,
An or Bn to Sn tPLH, tPHL 5 4.7 - 16.5 3.3 - 18.2 ns
Input Capacitance CI- - -10- -10pF
Power Dissipation Capacitance CPD
(Note 11) - - 120 - - 120 - pF
NOTES:
8. Limits tested 100%.
9. 3.3V Min is at 3.6V, Max is at 3V.
10. 5V Min is at 5.5V, Max is at 4.5V.
11. CPD is used to determine the dynamic power consumption per function.
AC: PD = VCC2 fi(CPD + CL)
ACT: PD = VCC2 fi(CPD + CL) + VCC ∆ICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage.
FIGURE 1. PROPAGATION DELAY TIMES
INPUT
tr≤ 3ns tf≤ 3ns INPUT LEVEL
90%
10%
GND
VS
VS
tPLH
tPHL
INVERTING
OUTPUT
DUT
OUTPUT
RL (NOTE)
OUTPUT
LOAD
500Ω
CL
50pF
NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.
FIGURE 2. PROPAGATION DELAY TIMES
AC ACT
Input Level VCC 3V
Input Switching Voltage, VS0.5 VCC 1.5V
Output Switching Voltage, VS0.5 VCC 0.5 VCC
CD54/74AC283, CD54/74ACT283
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
CD54AC283F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type Contact TI Distributor
or Sales Office
CD54ACT283F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type Contact TI Distributor
or Sales Office
CD74AC283E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Purchase Samples
CD74AC283EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Purchase Samples
CD74AC283M ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
CD74AC283M96 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
CD74AC283M96E4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
CD74AC283M96G4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
CD74AC283ME4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
CD74AC283MG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
CD74ACT283E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Contact TI Distributor
or Sales Office
CD74ACT283EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Contact TI Distributor
or Sales Office
CD74ACT283M ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
CD74ACT283ME4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
CD74ACT283MG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2010
Addendum-Page 2
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD54AC283, CD54ACT283, CD74AC283, CD74ACT283 :
•Catalog: CD74AC283, CD74ACT283
•Military: CD54AC283, CD54ACT283
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CD74AC283M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Jul-2010
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74AC283M96 SOIC D 16 2500 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Jul-2010
Pack Materials-Page 2
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