LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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LMK04000 Family
Precision Clock Conditioner with Dual PLLs and Integrated VCO
Evaluation Board Operating Instructions for rev3 PCBs
2011-08-23
LMK04000BEVAL
LMK04000BEVAL-XO
LMK04031BEVAL
LMK04031BEVAL-XO
LMK04002BEVAL
LMK04033BEVAL
National Semiconductor Corporation
Interface Division
Precision Timing Devices
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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Table of Contents
TABLE OF CONTENTS ....................................................................................................................... 2
GENERAL DESCRIPTION ................................................................................................................... 4
Evaluation Board Kit Contents ................................................................................................................................... 4
Available Evaluation Boards ...................................................................................................................................... 4
Available LMK04000 Family NSIDs ......................................................................................................................... 5
QUICK START ................................................................................................................................... 6
Default CodeLoader modes for evaluation boards ..................................................................................................... 7
USING CODELOADER TO PROGRAM THE LMK040XXB ................................................................... 8
1. Start CodeLoader 4 Application ............................................................................................................................. 8
2. Select Device .......................................................................................................................................................... 8
3. Program/Load Device ............................................................................................................................................. 9
4. Restoring a Default Mode ...................................................................................................................................... 9
5. Visual Confirmation of Frequency Lock .............................................................................................................. 10
6. Enable Fout........................................................................................................................................................... 10
7. Enable Clock Outputs ........................................................................................................................................... 11
PLL LOOP FILTERS AND LOOP PARAMETERS ................................................................................. 12
PLL 1 Loop Filter ..................................................................................................................................................... 12
122.88 MHz VCXO option ................................................................................................... 12
12.288 MHz Crystal (-XO) option ........................................................................................ 12
PLL2 Loop Filter ...................................................................................................................................................... 13
122.88 MHz VCXO (Reference Input) ................................................................................. 13
12.288 MHz Crystal (-XO) option (Reference Input) .......................................................... 13
EVALUATION BOARD INPUTS/OUTPUTS ......................................................................................... 14
RECOMMENDED TEST EQUIPMENT ................................................................................................. 17
APPENDIX A: CODELOADER USAGE .............................................................................................. 18
Port Setup Tab .......................................................................................................................................................... 18
Clock Outputs Tab .................................................................................................................................................... 19
PLL1 Tab .................................................................................................................................................................. 20
PLL2 Tab .................................................................................................................................................................. 21
Bits/Pins Tab ............................................................................................................................................................ 22
Registers Tab ............................................................................................................................................................ 24
APPENDIX B: TYPICAL PHASE NOISE PERFORMANCE PLOTS ......................................................... 25
PLL1 ......................................................................................................................................................................... 25
Crystek 122.88 MHz VCXO................................................................................................. 25
Vectron 12.288 MHz Crystal ................................................................................................ 26
PLL2 ......................................................................................................................................................................... 27
Clock Outputs ........................................................................................................................................................... 28
Clock Output Measurement Technique ................................................................................ 28
LMK040x0B Phase Noise ........................................................................................................................................ 29
LMK040x1B Phase Noise ........................................................................................................................................ 30
LMK040x2B Phase Noise ........................................................................................................................................ 31
LMK040x3B Phase Noise ........................................................................................................................................ 32
APPENDIX C: SCHEMATICS ............................................................................................................ 33
Power ........................................................................................................................................................................ 33
Main ......................................................................................................................................................................... 34
Clock Outputs ........................................................................................................................................................... 35
APPENDIX D: BOARD LAYERS STACKUP ....................................................................................... 36
APPENDIX E: BILL OF MATERIALS ................................................................................................ 37
Common Bill of Materials for Evaluation Boards .................................................................................................... 37
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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Bill of Material Custom to LMK04000BEVAL ....................................................................................................... 40
Bill of Material Custom to LMK04000BEVAL-XO ................................................................................................ 40
Bill of Material Custom to LMK04031BEVAL ....................................................................................................... 41
Bill of Material Custom to LMK04031BEVAL-XO ................................................................................................ 41
Bill of Material Custom to LMK04002BEVAL ....................................................................................................... 42
Bill of Material Custom to LMK04033BEVAL ....................................................................................................... 42
APPENDIX F: BALUN INFORMATION ............................................................................................... 43
Typical Balun Frequency Response ......................................................................................................................... 43
APPENDIX G: VCXO/CRYSTAL CHANGES...................................................................................... 44
Changing from Crystal Resonator to VCXO ............................................................................................................ 44
Changing from VCXO to Crystal Resonator ............................................................................................................ 47
APPENDIX H: LMK04000 .............................................................................................................. 50
APPENDIX I: PROPERLY CONFIGURING LPT PORT ......................................................................... 53
LPT Driver Loading ................................................................................................................................................. 53
Correct LPT Port/Address ........................................................................................................................................ 53
Correct LPT Mode .................................................................................................................................................... 54
APPENDIX J: TROUBLESHOOTING INFORMATION ........................................................................... 55
1)Confirm Communications ............................................................................................................................. 55
2)Confirm PLL1 operation/locking .................................................................................................................. 55
3)Confirm PLL2 operation/locking .................................................................................................................. 56
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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General Description
The LMK040xx Evaluation Board simplifies evaluation of the LMK040xxB Precision Clock
Conditioner with Dual PLLs and Integrated VCO. Configuring and controlling the board is
accomplished using National Semiconductor’s CodeLoader software, which can be downloaded
from: http://www.national.com/timing/software/.
The CodeLoader software will run on a Windows 2000 or Windows XP PC. The CodeLoader
software is used to program the internal registers of the LMK040xxB device through a
MICROWIRETM interface.
Evaluation Board Kit Content s
The evaluation board kit contains…
• An LMK040xx Evaluation board (one from Table 1).
• LMK04000 Family quick start guide.
o Evaluation board instructions are downloadable from the product folder on
National’s website, www.national.com/.
• CodeLoader uWire cable (LPT --> uWire).
A vailable Evaluatio n Boards
National Semiconductor has released a series of evaluation boards which allow the customer to
evaluate the different output types and VCO frequency ranges made available by the LMK04000
Family.
Note: It is possible to mount a VCXO on a –XO board or a Crystal on a non –XO board. See
Appendix G: VCXO/Crystal changes for more details.
Table 1. Avail able E val uation boards and configuration
Evaluation Board NSID VCXO Crystal (XTAL)
LMK04000BEVAL 122.88 MHz Crystek -
LMK04000BEVAL-XO - Vectron 12.288 MHz crystal
LMK04031BEVAL 122.88 MHz Crystek -
LMK04031BEVAL-XO - Vectron 12.288 MHz crystal
LMK04002BEVAL 122.88 MHz Crystek -
LMK04033BEVAL 122.88 MHz Crystek -
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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A vailable LMK04000 Family NSIDs
Please refer to the datasheet for the most up to date list of available devices in the LMK04000
Family.
Table 2. LMK040xxB Clock Output Configuration
Part Number CLKout0 CLKout1 CLKout2 CLKout3 CLKout4 VCO
Frequency
LMK04000BISQ LVPECL/
2VPECL
LVCMOS
(x2)
LVCMOS
(x2)
LVPECL/
2VPECL
LVPECL/
2VPECL
1185 to 1296
MHz
LMK04001BISQ LVPECL/
2VPECL
LVCMOS
(x2)
LVCMOS
(x2)
LVPECL/
2VPECL
LVPECL/
2VPECL
1430 to 1570
MHz
LMK04002BISQ LVPECL/
2VPECL
LVCMOS
(x2)
LVCMOS
(x2)
LVPECL/
2VPECL
LVPECL/
2VPECL
1566 to 1724
MHz
LMK04010BISQ LVPECL/
2VPECL
LVPECL/
2VPECL
LVPECL/
2VPECL
LVPECL/
2VPECL
LVPECL/
2VPECL
1185 to 1296
MHz
LMK04011BISQ LVPECL/
2VPECL
LVPECL/
2VPECL
LVPECL/
2VPECL
LVPECL/
2VPECL
LVPECL/
2VPECL
1430 to 1570
MHz
LMK04031BISQ LVDS LVPECL/
2VPECL
LVCMOS
(x2)
LVPECL/
2VPECL LVDS 1430 to 1570
MHz
LMK04033BISQ LVDS LVPECL/
2VPECL
LVCMOS
(x2)
LVPECL/
2VPECL LVDS 1840 to 2160
MHz
Note: LVPECL/2VPECL is software programmable.
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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Quick Start
Full evaluation board instructions with data are downloadable from the product folder of the
device at National Semiconductor’s website, www.national.com/.
1. Connect a voltage of 3.3 volts to either the Vcc SMA connector or the alternate connector.
2. Connect a reference clock from a signal generator or other source. Exact frequency
depends on programming. Default modes use a 122.88 MHz reference.
3. Connect the uWire header to a computer parallel port with the CodeLoader cable. A
USB communication option is available, search at www.national.com/ for:
USB2UWIRE-IFACE.
4. Program the device with CodeLoader. Ctrl-L must be pressed at least once to load all
registers once after CodeLoader is started or after restoring a Mode. CodeLoader is
available for download at www.national.com/timing/software/.
5. Measurements may be made at any clock output or Fout if enabled by programming.
Figure 1 - Quick Start Dia gr am
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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Default CodeLoader modes for evaluation boards
CodeLoader saves the state of the device when exiting the software. To ensure a common
starting point, the following modes listed in Table 3 may be restored by clicking “Mode” Æ
<Default Mode for evaluation board>.
After restoring a mode, be sure to press Ctrl-L to program the device. The default modes also
disable all outputs, so be sure to enable an output to make measurements.
Table 3 - Default Evaluation Board Modes
Evaluation Board NSID Default Mode
LMK04000BEVAL 122.88 MHz VCXO Default
LMK04000BEVAL-XO 12.288 MHz Crystal Default, or
12.288 MHz Crystal with Doubler Default
LMK04031BEVAL 122.88 MHz VCXO Default
LMK04031BEVAL-XO 12.288 MHz Crystal Default, or
12.288 MHz Crystal with Doubler Default
LMK04002BEVAL 122.88 MHz VCXO Default
LMK04033BEVAL 122.88 MHz VCXO Default
The next section outlines step-by-step procedures for using an LMK04031B evaluation board.
The process is the same for other evaluation boards except the part number is different.
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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Using CodeLoader to Program the LMK040xxB
The purpose of this section is to walk the user through using CodeLoader to make some
measurements with the LMK040xxB device. For more information on CodeLoader refer to
Appendix A: CodeLoader Usage or the CodeLoader 4 instructions located at
http://www.national.com/timing/software/.
Before proceeding, be sure to follow the Quick Start section above to ensure proper connections.
1. S tart CodeLoader 4 Application
Click “Start” Æ “Programs” Æ “CodeLoader 4” Æ “CodeLoader 4”
The CodeLoader 4 program is installed by default to the CodeLoader 4 application group.
2. Select Device
Click “Select Device” Æ “Clock Conditioners” Æ “LMK04031B”
Once started CodeLoader 4 will load the last
used device. To load a new device click
“Select Device” from the menu bar, then
select the subgroup and finally device to
load. For this example, the LMK04031B is
chosen. Selecting the device does cause the
device to be programmed.
Figure 2 – Selecting the LMK040 3 1B
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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3. Program/Load Device
Press “Ctrl – L”
Assuming the Port Settings are correct, it is
now possible to click “Keyboard Controls”
Æ “Load Device” from the menu to program
the device to the current state of the newly
loaded LMK04031B file. Ctrl-L is the
accelerator assigned to the Load Device
option and is very convenient.
Once the device has been loaded, by default CodeLoader will automatically program changed
registers, so it is not necessary to load the device again completely. It is possible to disable this
functionality by ensuring there is no checkmark by the “Mode” Æ “AutoReload with Changes.”
Since a default mode will be restored in the next step, this step isn’t really needed but included to
emphasize the importance of pressing “Ctrl-L” to load the device at least once after starting
CodeLoader, restoring a mode, or restoring a saved setup using the File menu.
See Appendix A: CodeLoader Usage or the CodeLoader 4 instructions located at
http://www.national.com/timing/software/ for more information on port setup. Appendix J:
Troubleshooting Information contains information on troubleshooting communications.
4. Restoring a Default Mode
Click “Mode” Æ “122.88 MHz VCXO Default”; then
Press “Ctrl – L”
Figure 4 – Setting the 122.88 MHz VCXO Default mode
For the purposes of this walkthrough a default mode will be loaded to ensure a common starting
point. This is important because when CodeLoader is closed, it remembers the last settings used
for a particular device. By loading the default mode a common starting point is ensured.
Loading a mode does not automatically program the device so it is necessary to press “Ctrl – L”
again to program the device.
Figure 3 - Loading the Devi ce
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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5. V isual Confirmation of Frequency Lock
After a device is selected and a default mode restored and loaded, the visual display on the board
should indicate a clock present at CLKin0 (LED D3 off) and that the PLL is locked (LED D1 on).
D1 will be on because the mode default sets PLL_MUX = PLL1/2 DLD Active High.
Figure 5 – Visual indic at ors of proper operation of eval uation board
6. Enable Fout
To measure the phase noise of the VCO,
1. Go to the Bits/Pins tab and enable the
“EN_Fout” bit.
2. Connect the Fout SMA on the left hand side of
the board to a spectrum analyzer or signal
source analyzer.
See Appendix B: Typical Phase Noise Performance
Plots for phase noise plots of the VCO.
Red LED off
LED D3 on if no signal
detected on CLKin0 port.
Green LED on
LED D1 on if locked when
PLL_MUX = PLL1/2 DLD
Active High. (mode default)
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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7. Enable Clock Output s
To measure phase noise at the clock outputs,
1. Click on the “Clock Outputs” tab,
2. Enable an output,
3. Then set the
a. CLKout MUX mode,
b. divide value, and
c. delay value.
Figure 6 - Setting Divide, Delay, CLKout _ MUX, Enabled for CLKout1 on "Clock Outpu ts" tab.
4. Connect the clock output SMAs to a spectrum analyzer or signal source analyzer.
a. For LVDS, a balun is recommended such as the ADT2-1T.
b. For LVPECL,
i. A balun can be used, or
ii. One side of the LVPECL signal can be terminated with a 50 ohm load and
the other side can be run to the test equipment single ended.
c. For LVCMOS,
i. Only one side of the LVCMOS signal can be turned
on by setting the CLKout_#a / CLKout_#b states in
the CLKout CMOS Options on the Bits/Pins tab.
ii. One side of the LVCMOS signal can be terminated
with a 50 ohm load and the other side can be run to
the test equipment single ended.
iii. A balun may be used. Ensure CLKout_#a and
CLKout_#b states are complementary, for example:
Non-inverted and Inverted.
5. The phase noise may be measured with a spectrum analyzer or signal source analyzer.
See Appendix B: Typical Phase Noise Performance Plots for phase noise plots of the clock
outputs.
National’s Clock Design Tool can be used to calculate divider values to achieve desired clock
output frequencies. See: http://www.national.com/timing/software/.
Figure 7 - Setting
LVCMOS modes.
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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PLL Loop Filters and Loop Parameters
In jitter cleaning applications that use a cascaded PLL architecture, the first PLL’s purpose is to
substitute the phase noise of a low noise oscillator (VCXO or crystal resonator) for the phase
noise of a “dirty” reference clock. The first PLL is typically configured with a narrow loop
bandwidth in order to minimize the impact of the reference clock phase noise. The reference
clock consequently serves only as a frequency reference rather than a phase reference.
The loop filters on the LMK040xx evaluation board are setup using the approach above. The
loop filter for PLL1 has been configured for a narrow loop bandwidth (< 100 Hz), while the loop
filter of PLL2 has been configured for a wide loop bandwidth (> 100 kHz). The specific loop
bandwidth values depend on the phase noise performance of the oscillator mounted on the board.
The following tables contain the parameters for PLL1 and PLL2 for each oscillator option.
National’s Clock Design Tool can be used to optimize PLL phase noise/jitter for given
specifications. See: http://www.national.com/timing/software/.
PLL 1 Loop Filter
Table 4. PLL1 Loop Filter Parameters for Crystek 122.88 MHz VCXO and 12.288 MHz Vectron Crystal
122.88 MHz VCXO option
Phase Margin 50º Kφ (Charge Pump) 100 uA
Loop Bandwidth 12 Hz Phase Detector Freq 1.024 MHz
VCO Gain 2.5 kHz/Volt
Reference Clock
Frequency 122.88 MHz Output Frequency 122.88 MHz (To PLL 2)
Loop Filter Components C1 = 100 nF C2 = 680 nF R2 = 39 kΩ
12.288 MHz Crystal (-XO) option
Phase Margin 60º Kφ (Charge Pump) 100 uA
Loop Bandwidth 8 Hz Phase Detector Freq 1.024 MHz
VCO Gain 1.5 kHz/Volt
Reference Clock
Frequency 122.88 MHz Output Frequency 12.288 MHz (To PLL 2)
Loop Filter Components C1 = 330 nF C2 = 10 uF R2 = 3.9 kΩ
Note: PLL Loop Bandwidth is a function of Kφ, Kvco, N as well as loop components. Changing
Kφ and N will change the loop bandwidth.
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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PLL2 Loop Filter
122.88 MHz VCXO (Reference Input)
LMK040x0B LMK040x1B LMK040x2B LMK040x3B Units
C1 Open
C2 12 nF
C3 0 nF
C4 0.01 nF
R2 1.8 kΩ
R3 0.6 kΩ
R4 0.2 kΩ
Charge Pump
Current, Kφ 3.2 mA
Phase Detector
Frequency 61.44 MHz
Frequency 1228.8 1474.56 1720.32 1966.08 MHz
Kvco 8 9 13 19 MHz/V
N 20 24 28 32
Phase Margin 85.5 85.5 85.0 84.0 degrees
Loop Bandwidth 366 343 424 542 kHz
12.288 MHz Crystal (-XO) option (Reference Input)
LMK040x0B LMK040x1B LMK040x2B LMK040x3B Units
C1 Open
C2 6.8 nF
C3 0 nF
C4 0.01 nF
R2 2.7 kΩ
R3 0.6 kΩ
R4 0.2 kΩ
Charge Pump
Current, Kφ 3.2 mA
Phase Detector
Frequency 12.288 MHz
Frequency 1228.8 1474.56 1720.32 1966.08 MHz
Kvco 8 9 13 19 MHz/V
N 100 120 140 160
Phase Margin 62 63 60 56 degrees
Loop Bandwidth 98 93 112 136 kHz
Note: PLL Loop Bandwidth is a function of Kφ, Kvco, N as well as loop components. Changing
Kφ and N will change the loop bandwidth.
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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Evaluation Board Inputs/Outputs
The following table contains descriptions of the various inputs and outputs for the evaluation
board.
Table 5. LMK040xx Evaluation Board I/O
Connector Name Input/Output Description
CLKout0 /
CLKout0*,
CLKout1 /
CLKout1*,
CLKout2 /
CLKout2*,
CLKout3 /
CLKout3*,
CLKout4 /
CLKout4*
Output
Populated connectors.
Differential clock output pairs. See Table 2 for format of
the output depending on part number. If an LVCMOS
output, each output can be independently configured (non-
inverted, inverted, tri-state, and LOW).
On the evaluation board, all clock outputs are AC-coupled
to allow safe testing with RF test equipment.
• All LVPECL/2VPECL clock outputs are
terminated to GND with a 120 ohm resistor, one on
each output pin of the pair.
CLKout4 is configured with an on board balun. Part
number is Mini-circuits’ ADT2-1T. According to the
ADT2-1T datasheet the 3 dB frequency range is 0.4 to 450
MHz. See Appendix F: Balun Information for more detail.
Fout Output
Populated connector.
When enabled, buffered VCO output. AC-coupled. The
default configuration on the board contains a 3-dB
attenuator on the Fout signal.
Vcc Input
Populated connector.
DC power supply for the PCB. Removing R1, R2, or R3
allow for splitting the power to various devices on the
board. For example, the VCXO is powered from the
VccAUXPlane connected via R3.
Note: The LMK04000 Family contains internal voltage
regulators for the VCO, PLL and related circuitry. The
clock outputs do not have an internal regulator. A clean
power supply is required for best performance.
VccLDO Input
Unpopulated connector.
Vcc input for LDOs on bottom of PCB. Refer to
schematics for more information.
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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Connector Name Input/Output Description
CLKin0/CLKin0*,
CLKin1/CLKin1* Input
Populated connectors.
Reference clock inputs for PLL1. The default board
configuration is setup for a single-ended reference source
at CLKin0* (CLKin0 pin is AC-coupled to ground). The
mode of the clock input buffer is programmable in
CodeLoader on the Bits/Pins tab, and may be either bi-
polar junction mode or MOS mode.
The input level for the various modes is as in the datasheet:
AC Coupled Input Clock Voltage Levels
Input Mode Min Max Units
Differential Bipolar 0.25 2.0 Vpp
Differential MOS 0.25 2.0 Vpp
Single Ended Bipolar 0.5 3.1 Vpp
Single Ended MOS 0.5 3.1 Vpp
If a DC-coupled clock is used to drive either of the inputs,
the high voltage level must be at least 2 volts and the low
voltage no greater than 0.4 volts.
By default CLKin0 is the active input in either of the auto-
switching modes (CLKin0 non-revertive, CLKin0
revertive). When loss of CLKin0 is detected, the device
automatically switches to CLKin1 if an active reference
clock is attached. See datasheet for further explanation.
LOS0, LOS1 Output
Unpopulated connectors.
Loss-of-Signal indicator (when LOS_TYPE = Active
CMOS, default) for CLKin0/0* and CLKin1/1*. The
LEDs D5 and D3 are light red when no signal is detected
according to the datasheet specification for LOS pins.
Bits/Pins, LOS_TYPE = Active CMOS for default
operation.
OSCin/OSCin* Input
Populated connectors.
By altering the PCB an external VCXO may be attached to
the OSCin/OSCin* SMA connectors. Either a differential
or single-ended device may be used. If a single-end device
is used, OSCin* should be tied to GND through a capacitor
that matches the AC-coupling capacitor value used for the
OSCin pin. See datasheet for OSCin port signal
specifications.
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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Connector Name Input/Output Description
Vtune1 Output
Unpopulated connector.
Tuning voltage output from the loop filter for PLL1. If an
external VCXO is used, this tuning voltage should be
connected to the voltage control pin of the external VCXO.
Note: Resistor R38 must be populated with a zero ohm
resistor to control an off-board VCXO.
uWire Input/Output
Populated connector.
10-pin header programming interface for the board. Of
Most important are the CLKuWire, DATAuWire, and
LEuWire programming lines from this header. Each of
these signals, GEO, and SYNC* can be monitored through
test points on the board.
LD Output
Unpopulated connector.
The LD pin is attached to a multiplexer inside the device
and may be programmed with a variety of internal signals
for monitoring internal device functions and
troubleshooting. See datasheet for further explanation.
The lock detect signal is accessible through this pin.
LD_TP Output
Test point attached to the LD pin of the device. See LD
above for more information.
GOE Input
Unpopulated connector.
Access to GOE of device.
SYNC* Input
Unpopulated connector.
Access to SYNC* of device.
PTO Output
Unpopulated connector.
Vcc SMA located close to OSCin SMAs for powering
external oscillator boards.
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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Recommended Test Equipment
Power Supply
The Power Supply should be a low noise power supply.
Phase Noise / Spectrum Analyzer
For measuring phase noise an Agilent E5052A Signal Source Analyzer is recommended. An
Agilent E4445A PSA Spectrum Analyzer with the Phase Noise option is also usable although the
architecture of the E5052A is superior for phase noise measurements. At frequencies less than
100 MHz the local oscillator noise of the E4445A is too high and measurements will reflect the
E4445A’s internal local oscillator performance, not the device under test.
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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Appendix A: CodeLoader Usage
Code Loader is used to program the evaluation board with either an LPT port using the included
CodeLoader cable or with a USB port using the optional USB <--> uWire cable available from
http://store.national.com/. The part number is USB2UWIRE-IFACE.
Port Setup Tab
Figure 8 - Port Setup tab
On the Port Setup tab, the user may select the type of communication port (USB or Parallel) that
will be used to program the device on the evaluation board. If parallel port is selected, the user
should ensure that the correct port address is entered.
The Pin Configuration field is hardware dependent and normally SHOULD NOT be changed by
the user. Figure 8 shows the default settings.
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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Clock Output s Tab
Figure 9 - Clock Outputs ta b
The clock outputs tab allows the user to Enable/Disable individual clock outputs, select the clock
mode (Bypass/Divided/Delayed/Divided & Delayed), set the clock output delay value (if delay is
enabled), and the clock output divider value (2, 4, 6, …, 510).
This tab also allows the user to select the VCO Divider value (2, 3, …, 8). Note that the total
PLL2 N divider value is composed of both the VCO Divider value and the N value shown in the
blue box in the image, and is given by: N_TOTAL = VCO Divider * N.
Clicking on the blue box that contains R, PDF and N values takes the user to the PLL2 tab where
these values may be changed.
Clicking on the components in the box containing the Internal Loop Filter values allows the user
to change these component values.
The Reference Oscillator value field may be changed in either the Clock Outputs tab or the PLL2
tab. Note this value should match the value of the on-board VCXO or Crystal. When using the
EN_PLL2_REF2X = 1, then Reference Oscillator field should be twice the VCXO or Crystal
frequency.
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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PLL1 Tab
Figure 10 - PLL1 tab.
The PLL1 tab allows the user to change:
• External VCXO (or Crystal oscillator) frequency. Note: This value must be entered in
both the PLL1 and PLL2 tabs.
• PLL1 Phase detector frequency
• PLL1 R-counter value
• PLL1 N-counter value
• CLKin (Reference) oscillator frequency
• PLL1 Phase Detector polarity (for external VCXO tuning slope, click on the polarity
value)
• PLL1 Charge pump gain (left click and right click on the charge pump current value)
• PLL1 Charge pump state (click on the charge pump state value)
Note that the value entered in the VCO frequency field on the PLL1 tab must match the
Reference Oscillator frequency entered on the PLL2 tab and the OSCin_FREQ on the Bits/Pins
tab. Updating the PLL2 tab Reference Oscillator frequency will automatically update the value
of OSCin_FREQ on the Bits/Pins tab. The only time that the Reference Oscillator frequency of
PLL2 tab will be different from the VCO frequency of PLL1 is when the EN_PLL2_REF2X
mode is enabled.
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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PLL2 Tab
Figure 11 - PLL2 tab.
The PLL2 tab allows the user to change:
• VCO frequency
• PLL2 Phase detector frequency
• PLL2 R-counter value
• PLL2 N-counter value
• The frequency of the external VCXO (or XTAL oscillator). Note: This value must be
entered in both the PLL1 and PLL2 tabs.
• PLL2 Charge pump gain
• PLL2 Charge pump state
Any changes made on this tab are reflected in the Clock Outputs tab. Note that the PLL2 Phase
Detector polarity is fixed and cannot be changed by the user. Also note that the VCO frequency
should conform to the specified frequency range for the device.
Note that the value entered in the VCO frequency field on the PLL1 tab must match the
Reference Oscillator frequency entered on the PLL2 tab and the OSCin_FREQ on the Bits/Pins
tab. Updating the PLL2 tab Reference Oscillator frequency will automatically update the value
of OSCin_FREQ on the Bits/Pins tab. The only time that the Reference Oscillator frequency of
PLL2 tab will be different from the VCO frequency of PLL1 is when the EN_PLL2_REF2X
mode is enabled.
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
22
Bit s/Pins Tab
Figure 12 - Bits/Pins tab.
The Bits/Pins tab allows the user to program bits directly. Many of which are not available on
other tabs. Refer to the datasheet for more detailed information. The bits available are:
• Common Box
o RESET - Set the reset bit. This will reset the device. In a normal application it is
not necessary to program this bit clear since it is auto-clearing. However in the
CodeLoader software, RESET must be clicked again (cleared) to not cause a reset
every time R7 is programmed.
o POWERDOWN - Place the device in powerdown mode.
o EN_Fout – Enable the Fout port.
• PLL Box
o PLL_MUX – Set the function of the LD pin.
o RC_DLD1_Start – Prevent PLL2 from locking until digital lock detect from
PLL1 is achieved.
o EN_PLL2_XTAL – Enables Crystal mode for PLL2. For use with Crystals as
opposed to a VCXO.
o EN_PLL2_REF2X – Doubles the reference frequency of PLL2. Note with this is
enabled, the PLL_R value is invalid. Program the Reference Oscillator on PLL2
Tab to be twice the VCO frequency on PLL1 tab. This adjustment must be done
manually.
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
23
• CLKin Options Box
o CLKin_SEL – Sets manual or automatic switching modes for selecting a
reference oscillator for PLL1.
o LOS_TIMEOUT – The timeout value before a loss of signal on a clock input is
registered on the LOS pins.
o LOS_TYPE – Set the type of output for the LOS pins.
o CLKin0_BUFTYPE & CLKin1_BUFTYPE – Select the input buffer used for the
respective clock input.
• PLL2_LF Box
o Set the integrated loop filter values for PLL2 including,
PLL2_R3_LF – R3 value
PLL2_R4_LF – R4 value
PLL2_C3_C4_LF – C3 and C4 value at the same time
o It is also possible to set these values by clicking on the loop filter values on the
Clock Outputs tab.
• CLKout Options Box
o EN_CLKout_Global – A global enable for clocks, if unchecked no outputs will
be observed!
o EN_CLKout0 through EN_CLKout4 – Individual clock output enables. These
can also be set on the Clock Outputs tab.
o The number of options vary depending on the option of the LMK device selected.
CLKout#_PECL_LVL – Set the level of an LVPECL output to LVPECL
or 2VPECL. The 2VPECL a higher output level than LVPECL.
• CLKout CMOS Options Box
o The presence of this box and the number of options on this tab depends upon the
option of the LMK device.
CLKout##_STATE – Set the state of the individual LVCMOS output.
• VCO Control – FC Box
o OSCin_FREQ – Must be set to the reference frequency of PLL2 in MHz, which
should normally be the VCO frequency of PLL1. NOTE: It is important to
enter the correct frequency value in this field, as it is used by the internal
state machine of the LMK040xxB to execute its calibration routine for the
internal VCO. An incorrect value may result in an unlocked condition for the
synthesizer.
Entering a reference oscillator frequency on PLL2 tab will automatically
update this register with the frequency to the nearest MHz.
• Program Pins Box
o GOE – Set high or low voltage on GOE pin. Checked is high voltage.
If GOE is low, then no clock outputs will be observed!
o SYNC* – Set high or low voltage on SYNC* pin. Checked is high voltage.
If SYNC* is low, then no clock outputs will be observed on divided clock
outputs!
o TRIGGER – Set high or low voltage on pin 10 of uWire header.
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
24
Registers Tab
The registers tab shows the value of each register. This is convenient for programming the
device to the desired settings, then recording the hex values for programming in your own
application.
By clicking in the “bit field” it is possible to manually change the value of registers by typing ‘1’
and ‘0.’
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
25
Appendix B: Typical Phase Noise Performance Plots
PLL1
The LMK040xxB’s two stage jitter cleaning process involves masking the reference noise with a
VCXO or Crystal. Therefore the phase noise performance of the VCXO or Crystal of PLL1 is a
very important contributor to the final phase noise of the system.
Crystek 122.88 MHz VCXO
The phase noise of the reference is masked by the phase noise of this VCXO by using a narrow
loop bandwidth. This VCXO sets the reference noise to PLL2. Figure 13 shows the open loop
typical phase noise performance of the CVHD-950-122.88 Crystek VCXO.
V CX O P hase Noise
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
10 100 1000 10000 100000 1000000 10000000 1E+08
Offset (Hz)
Phase Noise ( dBc/Hz)
CVHD-950-122.88
Figure 13 - CVHD-9 50-122.88 MHz VCXO Phase Noise at 122.88 MHz
Table 6 - VCXO Phase Noise
at 122.88 MHz ( dBc/Hz)
Offset Phase
Noise
10 Hz -76.6
100 Hz -108.9
1 kHz -137.4
10 kHz -153.3
100 kHz -162.0
1 MHz -165.7
10 MHz -168.1
40 MHz -168.1
Table 7 - VCXO RMS Jitter
to high offset of 20 MHz
at 122.88 MHz (rms fs)
Low
Offset Jitter
10 Hz 515.4
100 Hz 60.5
1 kHz 36.2
10 kHz 35.0
100 kHz 34.5
1 MHz 32.9
10 MHz 22.7
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
26
Vectron 12.288 MHz Crystal
The phase noise of the reference is masked by the phase noise of the crystal by using a narrow
loop bandwidth. The crystal sets the reference noise to PLL2. Figure 14 shows the typical open
loop phase noise performance of the VXB1-1127-12M288 Vectron Crystal.
Cryst al Phase Noise
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
100 1000 10000 100000 1000000 10000000
Offset (Hz)
Phase Noi se (dBc/H z)
VXB1-1127-12M288
Figure 14 - Vectron VXB1-1127-12M288 Crystal Phase Noise at 12.288 MHz
Table 8 - VCXO Phase Noise
at 12.288 MHz (dBc/Hz)
Offset Phase
Noise
100 Hz -111.6
1 kHz -143.3
10 kHz -151.6
100 kHz -152.7
1 MHz -152.8
5 MHz -153.3
Table 9 - VCXO RMS Jitter
to high offset of 20 MHz
at 12.288 MHz (rms fs)
Low
Offset Jitter
100 Hz 964.1
1 kHz 934.5
10 kHz 932.7
100 kHz 924.0
1 MHz 834.5
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
27
PLL2
The closed loop performance of the system as measured at the VCO output Fout. Fout phase
noise performance of the various LMK options is plotted in Figure 15. Table 10 and Table 11
summarize the phase noise and jitter of Fout.
LM K040x xB Fout Phase Noi se
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
10 100 1000 10000 100000 1000000 10000000 100000000
Offset (Hz)
P h ase No ise (dBc/Hz)
LMK040x0B
LMK040x1B
LMK040x2B
LMK040x3B
Figure 15 - LMK040xxB PLL2 Phase Noise (Fout)
Table 10 - LMK040x0B Phase Noise (dBc/Hz)
Offset LMK040x0B LMK040x1B LMK040x2B LMK040x3B
10 Hz -58.7 -58.3 -61.3 -61.1
100 Hz -88.0 -88.3 -85.7 -90.4
1 kHz -111.6 -110.2 -108.9 -107.5
10 kHz -118.2 -116.3 -115.7 -113.5
100 kHz -121.1 -119.5 -118.4 -117.0
1 MHz -132.0 -131.1 -128.6 -125.6
10 MHz -157.1 -155.8 -154.0 -152.7
40 MHz -165.9 -164.2 -162.3 -160.8
Table 11 - LMK040x0B RMS Jitter; Integrated to from low limit to 20 MHz (rms fs)
Low
Offset LMK040x0B LMK040x1B LMK040x2B LMK040x3B
10 Hz 580.0 506.6 443.4 356.0
100 Hz 127.2 117.5 124.5 132.8
1 kHz 114.8 111.3 114.9 128.1
10 kHz 111.7 108.0 112.0 125.0
100 kHz 97.3 92.7 99.2 112.2
1 MHz 39.7 36.2 41.6 50.9
10 MHz 6.0 5.9 6.0 5.5
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
28
Clock Output s
The LMK04000 Family features LVDS, LVPECL, 2VPECL, and LVCMOS types of outputs.
Included below are various phase noise measurements for each output.
Device LVDS LVPECL/2VPECL LVCMOS VCO Frequency
LMK040x0B
(LMK04000B) X X 1185 to 1296 MHz
LMK040x1B
(LMK04031B) X X X 1430 to 1570 MHz
LMK040x2B
(LMK04002B) X X 1566 to 1724 MHz
LMK040x3B
(LMK04033B) X X X 1840 to 2160 MHz
Note: The device in parenthesis is the device used for the measurement in these evaluation board
instructions.
Clock Output Measurement Technique
The measurement technique for each output type varies.
LVDS – measured with an ADT2-1T balun to test equipment.
LVPECL/2VPECL – Measured by terminating complementary output with 50 ohm load, then
taking output to test equipment.
LVCMOS – Measured by enabling only one side of the LVCMOS output and taking the
operating output to test equipment.
The following table lists the test conditions used for the phase noise measurements for the
VCXO option:
Table 12 . LMK040xxB test conditions
Parameter Value
PLL1 Reference clock input CLKin0* single-ended input, CLKin0 AC-coupled to GND
PLL1 Reference Clock frequency 122.88 MHz
PLL1 Phase detector frequency 1024 kHz
PLL1 Charge Pump Gain 100 uA
VCXO frequency 122.88 MHz
PLL2 phase detector frequency 61.44 MHz
PLL2 Charge Pump Gain 3200 uA
PLL2 REF2X mode Disabled
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
29
LMK040x0B Phase Noise
LMK040x0B Phase Noise
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
10 100 1000 10000 100000 1000000 1E+07 1E+08
Offset (Hz)
Phase Noi se ( dBc/Hz)
Fout
LVPECL
2VPECL
LVCMOS
LVPECL; div4
2VPECL; div4
LV CM OS; di v4
Figure 16 - LMK040x0B Phase Noise
The Fout frequency is 1228.8 MHz. The clock out frequency is 614.4 MHz, and the clock out
div 4 frequency is 153.6 MHz.
Table 13 - LMK040x0B Phase Noise (dBc/Hz)
Offset Fout LVPECL 2VPECL LVCMOS LVPECL
div4 2VPECL
div4 LVCMOS
div4
10 Hz -58.7 -67.1 -67.1 -66.3 -79.8 -81.5 -79.7
100 Hz -88.0 -95.8 -96.8 -94.8 -107.5 -109.1 -106.6
1 kHz -111.6 -117.6 -117.7 -117.9 -129.5 -130.2 -129.4
10 kHz -118.2 -123.8 -123.8 -124.2 -134.8 -135.2 -136.0
100 kHz -121.1 -127.0 -127.0 -127.3 -139.4 -139.3 -139.6
1 MHz -132.0 -137.9 -137.8 -138.1 -149.5 -149.6 -150.0
10 MHz -157.1 -153.8 -153.8 -152.8 -157.4 -158.1 -159.2
40 MHz -165.9 -154.8 -154.8 -153.6 -157.3 -158.0 -159.7
Table 14 - LMK040x0B RMS Jitter; Integrated to from low limit to 20 MHz (rms fs)
Low
Limit Fout LVPECL 2VPECL LVCMOS LVPECL
div4 2VPECL
div4 LVCMOS
div4
10 Hz 580.0 474.7 449.2 522.4 493.9 466.5 493.5
100 Hz 127.2 128.3 127.9 127.1 148.9 145.6 139.4
1 kHz 114.8 119.9 120.4 117.9 141.8 138.7 129.9
10 kHz 111.7 116.8 117.3 114.9 139.3 136.2 127.3
100 kHz 97.3 102.9 103.3 101.6 128.8 125.3 116.3
1 MHz 39.7 50.5 50.6 52.4 94.3 89.5 79.5
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
30
LMK040x1B Phase Noise
LMK040x1B Phase Noise
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
10 100 1000 10000 100000 1000000 1000000
01E+08
Offset (Hz)
Phase Noi se (dBc/Hz)
Fout
LVDS
LVPECL
2VPECL
LVCMOS
LV DS ; di v4
LVPECL; div4
2VPECL; div4
LV CMOS; di v4
Figure 17 - LMK040x1B Phase Noise
The Fout frequency is 1474.56 MHz. The clock out frequency is 737.28 MHz, and the clock out
div 4 frequency is 184.32 MHz. Note that the LVDS performance at 737.28 MHz is degraded
because it is outside of the balun’s operational bandwidth.
Table 15 - LMK040x1B Phase Noise (dBc/Hz)
Offset Fout LVDS LVPECL 2VPECL LVCMOS LVDS
div4 LVPECL
div4 2VPECL
div4 LVCMOS
div4
10 Hz -58.3 -62.0 -65.4 -66.4 -63.4 -74.8 -76.7 -73.8 -74.6
100 Hz -88.3 -96.4 -95.9 -96.0 -94.8 -106.7 -107.7 -105.3 -106.7
1 kHz -110.2 -115.3 -115.7 -115.8 -116.2 -128.3 -128.3 -128.1 -128.3
10 kHz -116.3 -118.1 -121.2 -121.3 -122.0 -132.8 -134.0 -134.3 -134.7
100 kHz -119.5 -122.0 -124.7 -124.7 -125.5 -137.7 -137.7 -137.8 -137.9
1 MHz -131.1 -133.5 -136.2 -136.2 -137.0 -148.5 -148.7 -148.7 -148.9
10 MHz -155.8 -148.2 -152.3 -152.3 -151.7 -156.9 -157.1 -157.5 -158.3
40 MHz -164.2 -149.5 -153.5 -153.6 -152.5 -157.5 -157.3 -158.0 -158.8
Table 16 - LMK040x1B RMS Jitter; Integrated to from low limit to 20 MHz (rms fs)
Low
Limit Fout LVDS LVPECL 2VPECL LVCMOS LVDS
div4 LVPECL
div4 2VPECL
div4 LVCMOS
div4
10 Hz 506.6 538.4 425.5 458.5 501.9 532.2 445.6 591.0 544.1
100 Hz 117.5 178.3 132.4 131.8 123.1 141.0 138.6 139.1 132.5
1 kHz 111.3 174.2 127.0 126.4 116.2 135.1 133.3 131.4 125.5
10 kHz 108.0 169.5 123.4 122.8 113.0 132.4 130.7 128.7 122.8
100 kHz 92.7 147.7 107.2 106.7 98.7 120.7 119.0 116.8 110.8
1 MHz 36.2 72.9 50.4 50.1 49.1 85.2 83.4 80.3 73.4
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
31
LMK040x2B Phase Noise
LMK040x2B Phase Noise
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
10 100 1000 10000 100000 1000000 1000000
01E+08
Offset (Hz)
Pha s e No ise (dBc/Hz)
Fout
LVPECL
2VPECL
LVCMOS
LV PE CL; d i v4
2V PE CL; d i v4
LV CM O S ; di v4
The Fout frequency is 1720.32 MHz. The clock out frequency is 860.16 MHz, and the clock out
div 4 frequency is 215.04 MHz.
Table 17 - LMK040x2B Phase Noise (dBc/Hz)
Offset Fout LVPECL 2VPECL LVCMOS LVPECL
div4 2VPECL
div4 LVCMOS
div4
10 Hz -61.3 -66.6 -67.3 -67.7 -80.1 -78.7 -78.9
100 Hz -85.7 -91.5 -90.4 -91.9 -103.3 -103.2 -103.8
1 kHz -108.9 -114.3 -114.2 -114.6 -126.7 -127.2 -126.5
10 kHz -115.7 -120.7 -120.7 -120.6 -133.5 -133.7 -134.1
100 kHz -118.4 -123.5 -123.5 -123.5 -136.7 -136.7 -136.8
1 MHz -128.6 -133.4 -133.4 -133.4 -146.2 -146.3 -146.5
10 MHz -154.0 -151.5 -151.5 -151.6 -156.7 -157.0 -157.7
40 MHz -162.3 -153.0 -153.2 -153.2 -157.0 -157.3 -158.2
Table 18 - LMK040x2B RMS Jitter; Integrated to from low limit to 20 MHz (rms fs)
Low
Limit Fout LVPECL 2VPECL LVCMOS LVPECL
div4 2VPECL
div4 LVCMOS
div4
10 Hz 443.4 498.1 477.3 450.5 439.3 473.4 458.5
100 Hz 124.5 143.1 140.8 140.4 141.0 140.7 136.6
1 kHz 114.9 132.7 132.1 132.0 132.3 131.1 126.6
10 kHz 112.0 129.6 129.0 129.0 130.0 128.7 124.2
100 kHz 99.2 115.7 115.2 115.2 119.7 118.3 113.7
1 MHz 41.6 54.9 54.8 54.7 79.2 77.1 71.8
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
32
LMK040x3B Phase Noise
LMK040x3B Phase Noise
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
10 100 1000 10000 100000 1000000 1E+07 1E+08
Offset (Hz)
Phase Noi se (dBc/Hz)
Fout
LVDS
LVPECL
2VPECL
LVCMOS
LV DS ; di v4
LVPECL; div4
2VPECL; div4
LV CM O S ; div4
The Fout frequency is 1966.08 MHz. The clock out frequency is 983.04 MHz, and the clock out
div 4 frequency is 245.76 MHz. Note that the LVDS performance at 737.28 MHz is degraded
because it is outside of the balun’s operational bandwidth.
Table 19 - LMK040x3B Phase Noise (dBc/Hz)
Offset Fout LVDS LVPECL 2VPECL LVCMOS LVDS
div4 LVPECL
div4 2VPECL
div4 LVCMOS
div4
10 Hz -61.1 -63.9 -66.2 -67.6 -67.0 -76.1 -75.2 -75.9 -80.1
100 Hz -90.4 -92.1 -94.6 -93.9 -94.3 -103.5 -103.7 -104.4 -106.3
1 kHz -107.5 -112.2 -112.8 -112.8 -113.6 -125.5 -125.8 -125.5 -125.4
10 kHz -113.5 -115.1 -118.1 -118.2 -119.7 -130.3 -131.4 -131.5 -132.0
100 kHz -117.0 -119.1 -121.8 -121.9 -123.0 -135.2 -135.3 -135.3 -135.3
1 MHz -125.6 -127.6 -130.4 -130.4 -131.5 -143.5 -143.6 -143.6 -143.7
10 MHz -152.7 -148.0 -150.6 -150.6 -150.0 -156.3 -156.1 -156.3 -156.8
40 MHz -160.8 -147.2 -151.9 -151.9 -151.2 -156.8 -156.4 -156.6 -157.3
Table 20 - LMK040x3B RMS Jitter; Integrated to from low limit to 20 MHz (rms fs)
Low
Limit Fout LVDS LVPECL 2VPECL LVCMOS LVDS
div4 LVPECL
div4 2VPECL
div4 LVCMOS
div4
10 Hz 356.0 531.5 367.7 339.0 367.6 471.8 499.6 464.0 338.9
100 Hz 132.8 210.0 153.3 153.4 137.4 147.1 146.5 146.2 141.5
1 kHz 128.1 205.5 149.2 149.5 132.6 140.7 140.5 140.2 137.1
10 kHz 125.0 200.9 145.8 146.1 129.6 138.1 137.9 137.6 134.4
100 kHz 112.2 181.2 131.6 131.9 117.3 127.2 127.1 126.7 123.5
1 MHz 50.9 88.9 64.4 64.5 59.5 79.6 80.6 79.7 75.8
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
33
Appendix C: Schematics
Power
C23
0.1 uF
C3
0.1 uF
C13
0.1 uF
C22
1 uF
C2
1 uF
C12
1 uF
C11
10 uF
VccPLLPlane
C205
Open
C202
Open
C203
Open
C204
Open
C210
Open
C212
Open
C217
Open
C220
Open
C200
Open
C201
Open
C208
Open
C211
Open
C213
Open
C219
Open
Fout [inc LDO]
VCO [inc LDO]
VCXO_IC
OSCin
PDCP2
PLL2
CLK0
Digital
CLKin
PDCP1
CLK1
CLK2
CLK3
CLK4
R202
Open
R206
Open
C1
10 uF
GND
C17
0.1 uF
Vcc
SMA
R1
0 ohm
Vin
1Vout 3
Vadj
2
TAB
4
U201
Open R204
Open
R209
Open
C206
Open
C209
Open
C214
Open C216
Open
C218
Open
R212
Open
LDO_Out
VccLDO
Open
R3
0 ohm
VccCLKoutPlane
VccAuxPlane
C21
10 uF
1 2
3 4
5 6
GND_TP
Open
R2
0 ohm
C10
0.1 uF
LDO Pow er Options
Power Plane for LMK Except Outputs
Power Plane for LMK CLKout Outputs
GND Head er
1 2
3 4
5 6
7 8
Vcc_TP
Open
Vcc Header
VccPLLPlane VccPLLPlan e
VccCLKoutPlaneVccCLKoutPlane
VccAuxPlane VccAuxPlane
C207
Open
Vcc Vcc
Vcc
R201
Open
R211
Open C215
Open
R213
Open
VccCLKoutPlane
VccPLLPlane
VccAuxPlane
VccCLKoutPlane
VccPLLPlane
R207
Open
R203
Open
Direct Power
R208
Open
VccAuxPlane
R210
Open
3
VIN
4VOUT 5
BYP 1
ADJ 6
SD
8
NC
2
NC
7
DAP GND
U200
Open
Power Plane for XO and VCXOs, LDOs, etc.
R205
Open
LP3878-ADJ 3.3 V com ponent v alues:
C214(C1) = 4.7 uF
R2 1 1(R3) = 51 k
C218 (C2) = 0.01 uF R213 (R2) = 1 k
C216 (C3) = 10 uF
R212 (R1) = 2.3 k
C215 (C4) = 3.9 nF
C9
10 nF
C8
0.1 uF
C7
1 uF
C16
10 nF
C15
0.1 uF
C14
1 uF
C20
10 nF
C19
0.1 uF
C18
1 uF
C6
10 nF
C5
0.1 uF
C4
1 uF
R200
Open
11
22
J1
POWER_SMALL
VIN
6
VEN
4
3
VOUT 1
NC 2
NC 5
DAP GND
U202
Open
C222
Open C223
Open
GND
V_LM317
V_LM3878-ADJ
V_LM5900
R216
Open
R215
Open
VccCLKou tPlane
R214
Open
C222 = 0.47 uF
C223 = 0.47 uF
R216 = 51 k
PTO Open
VccAuxPlane
C221
Open
Pow e r Take O ff for
external Oscillator boards
Designators greater than and equal to 200 are placed on bottom of PCB
LP3878-ADJ
LM317
LP5900SD-3.3
LP5900 Component values
LMK04000BEVAL schematic.
Refer to BOM for differences.
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
34
Main
C1_A2
Open
C2pA2
Open
C29
10 uF
Vcc PLLP lan e
VccPLLPlane
C24
100 pF
R7
270 ohm
R6
270 ohm
R5
18 ohm
R2_A2
1. 8 k
VccPLLPlan e
VccCLKoutPl an e Vc cPLLP l an e
VccPLLPlane
VccCLKoutPlan eVccCLKoutPlan eVccCLKoutPlaneVccCLKoutPlane
VccPLLPlane
VccPLLPlane
LD_TP
LOS0
Open
Fout
SMA
CLKout4_N
CLKout4_P
CLKout3_P
CLKout3_N
CLKout1_P
CLKout1_N
CLKout2_P
CLKout2_N
GND
1
Fout
2
Vcc1
3
CLKuWire
4
DATAuWi re
5
LEuWi re
6
NC
7
Vcc2
8
LDObyp1
9
LDObyp2
10
GOE
11
LD
12
Vcc313
CLKout0
14
CLKout0*
15
DLD_BYP
16
GND17
Vcc418
Vcc519
CLKin0
20
CLKin0*
21
Vcc622
CPout1
23
Vcc724
CLKin1 25
CLKin1* 26
SYNC * 27
OSCi n 28
OSCi n* 29
Vcc8 30
Vcc9 31
CPout2 32
Vcc10 33
CLKin0_LOS 34
CLKin1_LOS 35
Bias 36
Vcc11
37
CLKout1
38
CLKout1*
39
Vcc12
40
CLKout2
41
CLKout2*
42
Vcc13
43
CLKout3
44
CLKout3*
45
Vcc14
46
CLKout4
47
CLKout4*
48
LMK040xxB
DAP PAD
0
U1
LMK04000B
LOS1
Open
VccPLLPlan e
Vtune 1
NC 2
GND 3
RF
4
RF*
5
Vs
6
U4
CVHD-950-122.88
C25
1 uF
OSCin
Open
OSCin*
Open
R14
Open
R22
Open
C43
Open
C31
0.1 uF
C42
0.1 uF
R25
Open
SYNC*
OSCin VCXO
LOS Indication
C2_B2
6. 8 nF
C1_B2
Open
R2_B2
2.7 k
R10
Open
R9
0 ohm
C2pB2
Open
C2_A2
12 nF
GOE_TP
SYNC*_TP
R17
Open
R24
Open
C34
0. 1 uF
C36
0. 1 uF
C32
0. 47 uF
R2_A1
39 k
C2pA1
Open
C1_A1
100 nF
Vtune1
Vtune1
Open
R38
Open
Vtu n e_ VCXO
R54
Open
R52
Open
CLKin0*
SMA
CLKin0
Open
C54
Open
C59
0.1 uF
R53
Open
R62
51 ohm
C45
0.1 uF
R32
0 ohm
R16
100 ohm
C2_A1
680 nF
R2_B1
3.9 k
C2pB1
10 uF
C1_B1
330 nF
C2_B1
Open
R33
Open
R58
Open
Crystal Loop Filter
Y200
Open
R15
Open
R31
Open
C41
2. 0 pF
C40
2.2 nF
C33
2. 0 pF
C3_AB1
Open
R8
270 ohm
R4
270 ohm
D5
Red LED
D3
Red LED
D1
Green LED
R45
270 ohm
R13
51 ohm
R34
Open
D4
Open
VccAuxPlane
D6
Open
VccAuxPlane
D2
Open
VccAuxPlane
C53
Open
R65
0 ohm
C58
0 ohm
C35
2.2 nF
PLL2 Loop Filters
PLL1 Loop Filters
OSCin Tuneable Crystal
C62
0 ohm
R60
0 ohm
R64
Open
CLKin1*
SMA
CLKin1
SMA
C60
0.1 uF
C48
0. 1 uF
R63
Open
R50
Open
C50
Open
R57
Open
VccAuxPlane
R59
Open
C56
Open
C55
Open
Vtune 1
NC 2
GND 3
RF
4
RF*
5
Vs
6
U3
Open
R56
Open
R55
Open
R47
0 ohm
R49
Open
R48
Open
C52
Open
C51
0 ohm
C57
Open
R51
100 ohm
CLKin1 Crystal CLKin1 Impedance Matching and A ttenuation
CLKin1 XO
12
34
56
78
910
uWire
HEADER_2X5(POLARIZED)
R29
15 k
R28
27 k
R18
27 k
R12
15 k
R11
27 k
R19
15 k
R41
180 ohm
C47
1 uF
R36
180 ohm
SYNC*
C44
Open
R40
2.2 k
GOE
Open
SYNC*
Open
VccAuxPlane
R35
2.2 k
VccAuxPlane
R46
Open
C49
Open
LD
Open
R44
0 ohm
R42
Open
VccAuxPlane
CLKuWire
DATAuWire
LEuWire
uWire Voltage Translation
Analog LD
LD Indicator
CLKout0_P
CLKout0_N
CLKin0 I mpedance Matching and Attenuation
GOE Voltage Translation
LD
LD
SYNC* VoltageTranslation
Fout Balun and Impedance Matching
VccAuxPlane
C30
0.1 uF
C39
1 uF
C38
100 pF
C61
Open
R20
4. 7 k
R61
Open
C37
1 nF
R23
10 k
VCXO Loop Filter
R43
Open
D7
3. 3 V zener
D8
3. 3 V z ener
Y1
Open
C46
Open
1
3
2
D9
SMV-1249-074
R30
4.7 k
C28
33 pF
C26
33 pF
C27
33 pF
VTUNE2_TP1
VTUNE2
R21
Open
R27
Open
Vtu n e1
Vtune_VCXO
Vtu n e_ XTAL
Vtune_XTAL
R26
0 ohm
VccAuxPlane
R37
Open
R39
0 ohm
Crystal Loop Filter
VCXO Loop Filter
Designators greater than and equal to 200 are placed on bottom of PCB
LMK04000BEVAL schematic.
Refer to BOM for differences.
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
35
Clock Output s
CLKout1
SMA
CLKout1*
SMA
R93
Open
R89
Open
R90
Open
R97
Open
R98
Open
C67
0. 1 uF
C68
0. 1 uF
R92
Open
R95
Open
CLKout0
SMA
CLKout0*
SMA
R75
Open
R66
Open
R67
Open
R83
Open
R84
Open
C63
0. 1 uF
C65
0. 1 uF
R74
120 ohm
R80
120 ohm
CLKout0_N
CLKout0_P
R91
0 ohm
R96
0 ohm
R73
0 ohm
R82
0 ohm
CLKout0
CLKout1
Emitter Resistors
DC Block
Vcc Bias
Load Simulation
Notes:
1 . A st ub will be p laced ne ar a ll C LK ou t SMA co nn ect ors t o test t he eff e c t s of c ap acit ive lo ad ing.
2. CLKout0 and CLKout4 are both the same type and never CMOS.
3. CLKout1, CLKout2 and CLKout3 can be made LVPECL or CMOS via metal m ask.
VccCLKoutPlane
Emitter Resistors
Probe Tes t Point
Vcc Bias
DC Block
Vcc Bias
Load Simulation
CLKout4_N
CLKout4_P
CLKout4
Open
CLKout4*
SMA
R77
Open
R69
Open
R70
Open
R87
Open
R88
Open
C64
Open
C66
0. 1 uF
R76
120 ohm
R81
120 ohm
R85
0 ohm
R71
0 ohm
CLKout4
CLKout1_N
CLKout1_P
Emitter Resistors
DC Block
Vcc Bias
Load Simulation
Emitter Resistors
DC Block
Vcc Bias
Load Simulation
Emitter Resistors
DC Block
Vcc Bias
Load Simulation
CLKout3
SMA
CLKout3*
SMA
R108
Open
R101
Open
R102
Open
R117
Open
R118
Open
C70
0. 1 uF
C72
0. 1 uF
R107
120 ohm
R111
120 ohm
CLKout3_N
CLKout3_P
R104
0 ohm
R114
0 ohm
CLKout3
CLKout2
SMA
CLKout2*
SMA
R106
Open
R99
Open
R100
Open
R116
Open
C69
0. 1 uF
R105
Open
R109
Open
CLKout2_N
CLKout2_P
R103
0 ohm
R113
0 ohm
CLKout2
VccCLKou tPlane
VccCLKou tPlane
VccCLKoutPlan e
VccCLKoutPlan e
VccCLKoutPlane
VccCLKou tPlane
VccCLKou tPlane
VccCLKoutPlane
VccCLKoutPlane
R78
Open
R94
Open
R110
Open
R112
Open
R79
Open
C71
0. 1 uF
R115
Open
CLKout0_1_P
CLKout0_1_N
CLKout0_2_P
CLKout0_2_N
CLKout1_1_P
CLKout1_1_N
CLKout1_2_P
CLKout1_2_N
CLKout2_1_P
CLKout2_1_N
CLKout2_2_P
CLKout2_2_N
CLKout3_1_P
CLKout3_1_N
CLKout3_2_P
CLKout3_2_N
CLKout4_1_P
CLKout4_1_N
CLKout4_3_ P
CLKout4_3_ N
Output option 0 - LVPECL/2VPECL
Output option 1 - LVPECL/2VPECL
Output option 3 - LVDS
Output option 0 - LVPECL/2VPECL
Output option 1 - LVPECL/2VPECL
Output option 3 - LVDS
Output option 0 - LVCMOS
Output option 1 - LVPECL/2VPECL
Output option 3 - LVPECL/2VPECL
Output option 0 - LVCMOS
Output option 1 - LVPECL/2VPECL
Output option 3 - LVCMOS
Output option 0 - LVPECL/2VPECL
Output option 1 - LVPECL/2VPECL
Output option 3 - LVPECL/2VPECL
P1
NC 2
PD 3
S
4
SCT
5
SD
6
B1
ADT2-1T
R72
Open
R86
Open
R68
0 ohm
CLKout4_2_P
CLKout4_2_N
Designators greater than and equal to 200 are placed on bottom of PCB
LMK04000BEVAL schematic.
Refer to BOM for differences.
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
36
Appendix D: Board Layers Stackup
Layers of the 6 layer evaluation board include:
Blue is dielectrics
• Top layer for high priority high frequency signals
o 1 oz CU
• RO4003 Dielectric, 16 mils
• Ground plane
• FR4, 2.5 mils thick.
• Power plane #1 – VccCLK
• FR4, xx mils
• middle ground plane
• FR4, xx mils
• VccPLL, VccAux
• FR4, xx mils
• Bottom layer copper clad for thermal relief
Top to bottom layer order:
LMK04000.GTL (1) top copper
LMK04000.GP1 (2) gnd
LMK04000.GP2 (3) vcc
LMK04000.GP3 (4) gnd
LMK04000.G1 (5) vcc
LMK04000.GBL (6) bottom copper
RO4003 (Er = 3.38)
CONTROLLED THICKNESS of
16 mils thick
Top Copper. 1oz thick [LMK04000.GTL]
GND plane [LMK04000.GP1]
FR4 (Er = ~4.6)
CONTROLLED THICKNESS: 2.5 mils
VccCLK plane [LMK04000.GP2]
FR4
Middle Ground Plane
FR4
Bottom Copper – Thermal relief
[LMK04000.GBL]
62 mils thick total
FR4
Vcc mixed plane [LMK04000.G1]
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
37
Appendix E: Bill of Materials
Common Bill of Materials for Evaluation Boards
Part Manufacturer Part Number Qnt Identifier
Capacitors
2.0 pF Kemet C0603C209C5GAC 2 C33, C41
33 pF Kemet C0402C330J5GAC 3 C26, C27, C28
100 pF Kemet C0603C101J5GAC 2 C24, C38
1 nF Kemet C0603C102J5GAC 1 C37
2.2 nF Kemet C0603C222K5RAC 2 C35, C40
6.8 nF Kemet C0603C682K1RACTU 1 C2_B2
10 nF Kemet C0603C103K1RACTU 4 C6, C9, C16, C20
12 nF Panasonic ECH-U01123JX5 1 C2_A2
0.1 uF Kemet C0603C104J3RAC 25
C3, C5, C8, C10, C13, C15, C17, C19, C23, C30,
C34, C36, C45, C48, C59, C60, C63, C65, C66,
C67, C68, C69, C70, C71, C72
100 nF Kemet C0603C104J3RAC 1 C1_A1
330 nF Kemet C0603C334K4RACTU 1 C1_B1
0.47 uF Kemet C0603C474K8PACTU 1 C32
680 nF Kemet C0603C684K8PAC 1 C2_A1
1 uF Kemet C0603C105K8PAC 10 C2, C4, C7, C12, C14, C18, C22, C25, C39, C47
10 uF Kemet C0805C106K9PAC 5 C1, C2pB1, C11, C21, C29
(page 1/3)
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
38
Resistors
0 ohm Vishay/Dale CRCW06030000Z0EA 23
C51, C58, C62, R1, R2, R3, R26, R32, R44, R47,
R60, R65, R68, R71, R73, R82, R85, R91, R96,
R103, R104, R113, R114
18 ohm Vishay/Dale CRCW060318R0JNEA 1 R5
51 ohm Vishay/Dale CRCW060351R0JNEA 2 R13, R62
100 ohm Vishay/Dale CRCW0603100RJNEA 2 R16, R51
120 ohm Vishay/Dale CRCW0603120RJNEA 2 R107, R111
180 ohm Vishay/Dale CRCW0603180RJNEA 2 R36, R41
270 ohm Vishay/Dale CRCW0603270RJNEA 5 R4, R6, R7, R8, R45
1.8 k Vishay/Dale CRCW06031K80JNEA 1 R2_A2
2.2 k Vishay/Dale CRCW06032K20JNEA 2 R35, R40
2.7 k Vishay/Dale CRCW06032K70JNEA 1 R2_B2
3.9 k Vishay/Dale CRCW06033K90JNEA 1 R2_B1
4.7 k Vishay/Dale CRCW06034K70JNEA 2 R20, R30
10 k Vishay/Dale CRCW060310K0JNEA 1 R23
15 k Vishay/Dale CRCW060315K0JNEA 3 R12, R19, R29
27 k Vishay/Dale CRCW060327K0JNEA 3 R11, R18, R28
39 k Vishay/Dale CRCW060339K0JNEA 1 R2_A1
Other
POWER_SMALL Weidmuller 1594540000 1 J1
SMA Johnson Components 142-0701-851 14
CLKin0*, CLKin1, CLKin1*, CLKout0*, CLKout0,
CLKout1*, CLKout1, CLKout2*, CLKout2,
CLKout3*, CLKout3, CLKout4*, Fout, Vcc
SMA_FRAME Printed Circuits Corp. PCB 1 F1
Red LED Lumex SML-LX2832IC-TR 2 D3, D5
Green LED Lumex SML-LX2832GC-TR 1 D1
0.875" Standoff SPC Technology SPCS-14 4 S1, S2, S3, S4
ADT2-1T Minicircuits ADT2-1T+ 1 B1
HEADER_2X5(POLARIZED) FCI Electronics 52601-S10-8 1 uWire
3.3 V zener Comchip CZRU52C3V3 2 D7, D8
SMV-1249-074 Skyworks SMV1249-074LF 1 D9
Common Bill of Materials for Evaluation Boards (continued, 2/3)
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
39
Common Bill of Materials for Evaluation Boards (continued, 3/3)
Open
Open R 78
R14, R17, R21, R22, R24, R25, R27, R33, R34,
R38, R42, R43, R46, R48, R49, R50, R52, R53,
R54, R55, R56, R57, R58, R59, R61, R63, R64,
R66, R67, R69, R70, R72, R75, R77, R78, R79,
R83, R84, R86, R87, R88, R89, R90, R93, R94,
R97, R98, R99, R100, R101, R102, R105, R106,
R108, R109, R110, R112, R115, R116, R117, R118,
R200, R201, R202, R203, R204, R205, R206, R207,
R208, R209, R210, R211, R212, R213, R214, R215,
R216
Open C 44
C1_A2, C1_B2, C2pB2, C2pA2, C2pA1, C2_B1,
C3_AB1, C43, C44, C46, C49, C50, C52, C53, C54,
C55, C56, C57, C61, C64, C200, C201, C202,
C203, C204, C205, C206, C207, C208, C209, C210,
C211, C212, C213, C214, C215, C216, C217, C218,
C219, C220, C221, C222, C223
Open U 4 U3, U200, U201, U202
Open SMA 12
OSCin*, OSCin, LOS0, LOS1, VccLDO, LD, PTO,
GOE, SYNC*, CLKout4, Vtune1, CLKin0
Open Y 1 Y200
Open D 3 D2, D4, D6
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
40
Bill of Material Custom to LMK04000BEVAL
Part Manufacturer Part Number Qnt Identifier
Capacitors
0.1 uF Kemet C0603C104J3RAC 2 C31, C42
Resistors
0 ohm Vishay/Dale CRCW06030000Z0EA 2 R9, R39
120 ohm Vishay/Dale CRCW0603120RJNEA 4 R74, R76, R80, R81
Other
LMK04000B National Semiconductor LMK04000B 1 U1
CVHD-950-122.88 Crystek CVHD-950-122.88 1 U4
Open
Open 6 R10, R15, R31, R37, R92, R95
Open 1 Y1
Bill of Material Custom to LMK04000BEVAL-XO
Part Manufacturer Part Number Qnt Identifier
Capacitors
Resistors
0 ohm Vishay/Dale CRCW06030000Z0EA 4 R10, R15, R31, R37
120 ohm Vishay/Dale CRCW0603120RJNEA 4 R74, R76, R80, R81
Other
LMK04000B National Semiconductor LMK04000B 1 U1
12.288 MHz XTAL Vectron VXB1-1127-12M288 1 Y1
Open
Open 2 C31, C42
Open 4 R9, R39, R92, R95
Open 1 U4
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
41
Bill of Material Custom to LMK04031BEVAL
Part Manufacturer Part Number Qnt Identifier
Capacitors
0.1 uF Kemet C0603C104J3RAC 2 C31, C43
Resistors
0 ohm Vishay/Dale CRCW06030000Z0EA 2 R9, R39
120 ohm Vishay/Dale CRCW0603120RJNEA 2 R92, R95
Other
LMK04031B National Semiconductor LMK04031B 1 U1
CVHD-950-122.88 Crystek CVHD-950-122.88 1 U4
Open
Open 8
R10, R15, R31, R37, R74, R76, R80,
R81
Open 1 Y1
Bill of Material Custom to LMK04031BEVAL-XO
Part Manufacturer Part Number Qnt Identifier
Capacitors
Resistors
0 ohm Vishay/Dale CRCW06030000Z0EA 4 R10, R15, R31, R37
120 ohm Vishay/Dale CRCW0603120RJNEA 2 R92, R95
Other
LMK04031B National Semiconductor LMK04031B 1 U1
12.288 MHz XTAL Vectron VXB1-1127-12M288 1 Y1
Open
Open 2 C31, C42
Open 6 R9, R39, R74, R76, R80, R81
Open 1 U4
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
42
Bill of Material Custom to LMK04002BEVAL
Part Manufacturer Part Number Qnt Identifier
Capacitors
0.1 uF Kemet C0603C104J3RAC 2 C31, C42
Resistors
0 ohm Vishay/Dale CRCW06030000Z0EA 2 R9, R39
120 ohm Vishay/Dale CRCW0603120RJNEA 4 R74, R76, R80, R81
Other
LMK04002B National Semiconductor LMK04002B 1 U1
CVHD-950-122.88 Crystek CVHD-950-122.88 1 U4
Open
Open 6 R10, R15, R31, R37, R92, R95
Open 1 Y1
Bill of Material Custom to LMK04033BEVAL
Part Manufacturer Part Number Qnt Identifier
Capacitors
0.1 uF Kemet C0603C104J3RAC 2 C31, C42
Resistors
0 ohm Vishay/Dale CRCW06030000Z0EA 2 R9, R39
120 ohm Vishay/Dale CRCW0603120RJNEA 2 R92, R95
Other
LMK04033B National Semiconductor LMK04033B 1 U1
CVHD-950-122.88 Crystek CVHD-950-122.88 1 U4
Open
Open 8
R10, R15, R31, R37, R74, R76, R80,
R81
Open 1 Y1
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
43
Appendix F: Balun Information
Typical Balun Frequency Response
The following figure illustrates the typical frequency response of the Mini-circuit’s ADT2-1T
balun.
Figure 18 - Typical Balun Frequency Response
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
44
Appendix G: VCXO/Crystal changes
This appendix contains instructions for changing the active on-board oscillator for PLL1.
Changing from Cryst al Resonator to VCXO
If the board has been setup to use the crystal-based oscillator with PLL1, the crystal may be
disabled and the VCXO enabled as described on the following pages:
Summary
1. Connect power to VCXO
2. Disconnect Crystal RF path and connect VCXO RF path
3. Connect charge pump output from PLL1 to VCXO Loop Filter (A1) and VCXO.
4. Connect charge pump output from PLL2 to VCXO Loop filter (A2).
Procedures
1. Connect power to VCXO
a. Install a 0 ohm resistor in R26 (near the VCXO)
Figure 19
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
45
2. Disconnect Crystal RF path and connect VCXO RF path
a. Remove resistors R15 and R31.
b. Install 0.1 uF capacitors in C31 and C43.
Figure 20
3. Connect charge pump output from PLL1 to VCXO Loop Filter (A1) and VCXO.
a. Remove R37 and install a 0 ohm resistor in R39. This resistor can be “switched”
between the two footprints.
Figure 21
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
46
4. Connect charge pump output from PLL2 to VCXO Loop filter (A2).
a. Remove R10 and install a 0 ohm resistor in R9. This resistor can be “switched”
between the two footprints.
Figure 22
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
47
Changing from VCXO to Cryst al Resonator
If the board has been setup to use the VCXO for PLL1, the VCXO may be disabled and the
crystal enabled as described on the following pages:
Summary
1. Remove power from VCXO
2. Disconnect VCXO RF path and connect Crystal RF path
3. Connect charge pump output from PLL1 to Crystal Loop Filter (B1) and Crystal
4. Connect charge pump output from PLL2 to Crystal Loop filter (B2)
Procedures
1. Remove power from VCXO
a. Remove 0 ohm resistor in R26 (near the VCXO)
Figure 23
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
48
2. Disconnect VCXO RF path and connect Crystal RF path
a. Install 0 ohm resistors R15 and R31.
b. Remove 0.1 uF capacitors in C31 and C43.
Figure 24
3. Connect charge pump output from PLL1 to Crystal Loop Filter (B1) and Crystal
a. Remove R39 and install a 0 ohm resistor in R37. This resistor can be “switched”
between the two footprints.
Figure 25
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
49
4. Connect charge pump output from PLL2 to Crystal Loop filter (B2)
a. Remove R9 and install a 0 ohm resistor in R10. This resistor can be “switched”
between the two footprints.
Figure 26
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
50
Appendix H: LMK04000
The block diagram in Figure 27 illustrates the functional architecture of the LMK040xxB clock
conditioner. It features a cascaded, dual PLL arrangement, available internal loop filter
components for PLL2, internal VCO with PLL2 for frequency synthesis, and clock distribution
section with individual clock output dividers and delay adjustment blocks. The dual reference
clock input to PLL1 provides fail-safe redundancy for phase locked loop operation. The cascaded
PLL architecture allows PLL1 to be used as a jitter cleaner for an incoming reference clock that
contains excessive phase noise. This requires the user to select an external oscillator (VCXO or
crystal) that provides the desired phase noise performance at the clock output. This external
oscillator becomes the reference clock for PLL2 and along with the phase noise characteristics of
PLL2 and the internal VCO, determines the final phase noise performance at FOUT and the
output of the clock distribution section.
PLL2PLL1
R1
N1
R2
N2
VCO
CLKin0
CLKin1 VCO
DIV
CHAN
DIV
CHAN
DIV
5 Output Clock
Channels
LVPECL, LVDS,
LVCMOS
FOUT
CLKout_0
CLKout_4
uWire
Interface
DATA
CLK
LE
vcxo
Figure 27 - Functional Block Diagram of the LMK040xxB Dual PLL Precision Clock Conditioner with
External VCXO module.
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PLL1 has been designed to work with either an off-the-shelf VCXO package or with a user-
designed discrete implementation that employs a crystal resonator and associated tuning
components. The Figure 28 shows an example of a discretely implemented VCXO using a
crystal resonator.
PLL2PLL1
R1
N1
R2
N2
VCO
CLKin0
CLKin1 VCO
DIV
CHAN
DIV
CHAN
DIV
5 Output Clock
Channels
LVPECL, LVDS,
LVCMOS
FOUT
CLKout_0
CLKout_4
uWire
Interface
DATA
CLK
LE
Figure 28 - LMK040xxB wi th the XTAL Reso na t or opti on and Tuning Circuit
LMK04000 Family evaluation boards are configured with either a VCXO or Crystal (-XO) on
board. It is possible to place a VCXO on a Crystal board or a Crystal on a VCXO board by
removing and replacing certain components on the board. Instructions for modifying the board
are presented in Appendix G: VCXO/Crystal changes.
Figure 29 below shows the crystal oscillator circuit diagram.
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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CPout1
Figure 29 - Crystal Oscillator Circuit diagra m
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Appendix I: Properly Configuring LPT Port
When trying to solve any communications issue, it is convenient to program the POWERDOWN
bit to confirm high/low current draw of the evaluation board or the PLL_MUX between “Logic
Low” and “Logic High” LD output to confirm successful communications.
LPT Driver Loading
The parallel port must be configured for proper operation. To confirm that the LPT port driver is
successfully loading click “LPT/USB” Æ “Check LPT Port.” If the driver properly loads then
the following message is displayed:
Figure 30 - Successfully Opened LPT Driver
Successful loading of LPT driver does not mean LPT communications in CodeLoader are setup
properly. The proper LPT port must be selected and the LPT port must not be in an improper
mode.
The PC must be rebooted after install for LPT support to work properly.
Correct LPT Port/Address
To determine the correct LPT port in Windows, open the device manager (On Windows XP,
Start Æ Settings Æ Control Panel Æ System Æ Hardware Tab Æ Device Manager) and check
the LPT port under the Ports (COM & LPT) node of the tree. It can be helpful to confirm that
the LPT port is mapped to the expected port address, for instance to confirm that LPT1 is really
mapped to address 0x378. This can be checked by viewing the properties of the LPT1 port and
viewing resources tab to verify that the I/O Range starts at 0x378. CodeLoader expects the a
traditional port mapping: Port Address
LPT1 0x378
LPT2 0x278
LPT3 0x3BC
If a non-standard address is used, use the “Other” port address in CodeLoader and type in the
port address in hexadecimal. It is possible to change the port address in the computer’s BIOS
settings. The port address is set in CodeLoader at the Port Setup tab as shown in Figure 31.
LMK040XX-REV3 EVALUATION BOARD OPERATING INSTRUCTIONS
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Figure 31 - Selecting the LPT Port
Correct LPT Mode
If communications are not working, then it is possible the LPT port mode is set improperly. It is
recommended to use the simple, Output-only mode of the LPT port. This can be set in the BIOS
of the computer. Common terms for this desired parallel port mode are “Normal,” “Output,” or
“AT.” It is possible to enter BIOS setup during the initial boot up sequence of the computer.
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Appendix J: Troubleshooting Information
If the evaluation board is not behaving as expected, the most likely issues are…
1) Board communication issue
2) Incorrect Programming of the device
3) Setup Error
Refer to this checklist for a practical guide on identifying/exposing possible issues.
1) Confirm Communications
Refer to Appendix I: Properly Configuring LPT Port to trouble shoot this item.
Remember to load device with Ctrl-L!
2) Confirm PLL1 operation/locking
1) Program PLL_MUX = “PLL 1 R Divider /2”
2) Confirm that LD pin output is half the expected phase detector frequency of PLL1.
i. If not, examine CLKin_SEL programming.
ii. If not, examine CLKin0_BUFTYPE / CLKin1_BUFTYPE.
iii. If not, examine PLL1 register R programming.
iv. If not, examine physical CLKin input.
3) Program PLL_MUX = “PLL 1 N Divider /2”
4) Confirm that LD pin output is half the expected phase detector frequency of PLL1.
i. If not, examine PLL1 register N programming.
ii. If not, examine physical OSCin input.
Naturally, the output frequency of the above two items, PLL 1 R Divider/2 and PLL 1 N Divider
/2, on LD pin should be the same frequency.
5) Program PLL_MUX = “PLL1 DLD Active High”
6) Confirm the LD pin output is high.
i. If high, then PLL1 is locked, continue to PLL2 operation/locking.
(continued on next page)
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7) If LD pin output is low, but the frequencies are the same, it is possible that excessive
leakage on Vtune pin is causing the digital lock detect to not activate. By default
PLL2 waits for the digital lock detect to go high before allowing PLL2 and the
integrated VCO to lock. Different VCXO models have different input leakage
specifications. High leakage, low PLL1 phase detector frequencies, and low PLL1
charge pump current settings can cause the PLL1 charge pump to operate longer than
the digital lock detect timeout which allows the device to lock, but prevents the
digital lock detect from activating.
i. Redesign PLL1 loop filter with higher phase detector frequency
ii. Redesign PLL1 loop filter with higher charge pump current
iii. Isolate VCXO tuning input from PLL1 charge pump with an op amp.
iv. Program RC_DLD1_Start = 0, this will allow PLL2 to starting lock even if
the digital lock detect on PLL1 is not high.
3) Confirm PLL2 operation/locking
1) Program PLL_MUX = “PLL 2 R Divider /2”
2) Confirm that LD pin output is half the expected phase detector frequency of PLL2.
i. If not, examine PLL2 register R programming.
ii. If not, examine physical OSCin input.
3) Program PLL_MUX = “PLL 2 N Divider /2”
4) Confirm that LD pin output is half the expected phase detector frequency of PLL2.
i. If not, confirm OSCin_FREQ is programmed to OSCin frequency.
ii. If not, examine PLL2 register N programming.
Naturally, the output frequency of the above two items should be the same frequency.
5) Program PLL_MUX = “PLL2 DLD Active High”
6) Confirm the LD pin output is high.
7) Program PLL_MUX = “PLL1/2 DLD Active High”
8) Confirm the LD pin output is high.
