Enpirion(R) Power Datasheet EN6310QI 1A PowerSoC Voltage Mode Synchronous PWM Buck with Integrated Inductor Description Features The EN6310QI is a member of Altera Enpirion's high efficiency EN6300 family of PowerSoCs. It can support up to 1A of continuous output current and has an input voltage range of 2.7V to 5.5V. The EN6310QI employs Altera Enpirion's EDMOS MOSFET technology for monolithic integration and very low switching loss. The device switches at 2.2MHz in fixed PWM operation to eliminate the low frequency noise that is created by pulse frequency modulation operating modes. The MOSFET ratios are optimized to offer high conversion efficiency for lower VOUT settings. Output voltage settings are programmable via a simple resistor divider circuit. Output voltage can be programmed from as low as 0.6V to 3.3V. The device has a programmable soft-start ramp rate to accommodate sequencing and to prevent un-wanted current inrush at start up. A Power OK (POK) flag is provided to indicate a fault condition. The Altera Enpirion power solution significantly helps in system design and productivity by offering greatly simplified board design, layout and manufacturing requirements. In addition, a reduction in the number of vendors required for the complete power solution helps to enable an overall system cost savings. * Integrated inductor, MOSFET and Controller All Enpirion products are RoHS compliant and leadfree manufacturing environment compatible. * Enterprise Grade Solid State Drive (SSD) * Small 4mm x 5mm x 1.85mm QFN * High Efficiency up to 96% * Solution Footprint Less than 65mm2 * 1A Continuous Output Current * VIN Range of 2.7V to 5.5V * VOUT Range from 0.6V to 3.3V * Programmable Soft Start and Power OK Flag * Fast Transient Response and Recovery Time * Low Noise and Low Output Ripple; 4mV Typical * 2.2MHz Switching Frequency * Under Voltage Lock-out (UVLO), Short Circuit, Over Current and Thermal Protection Applications * Altera FPGAs (MAX, ARRIA, CYCLONE, STRATIX) * Low Power FPGA Applications * All SERDES and IO Supplies Requiring Low Noise * Applications Requiring High Efficiency * Noise Sensitive Wireless and RF Applications Efficiency vs. Output Current VOUT VIN VOUT PVIN 95 EN6310QI RAVIN CIN1 20 100pF ON OFF 90 COUT 47F 0805 ENABLE AVIN RA CAVIN 0.47F CA RCA VFB SS 10nF 85 80 75 70 VOUT = 2.5V 65 VOUT = 1.0V PGND PGND CSS EFFICIENCY (%) CIN2 4.7F 100 RB AGND CONDITIONS VIN = 3.3V 60 0 Figure 1. Simplified Applications Circuit 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 OUTPUT CURRENT (A) 1 Figure 2. Highest Efficiency in Smallest Solution Size www.altera.com/enpirion 09644 March 9, 2017 Rev F EN6310QI Ordering Information Part Number EN6310QI EVB-EN6310QI Package Markings N6310 N6310 T A (C) -40 to +85 Package Description 30-pin (4mm x 5mm x 1.85mm) QFN T&R QFN Evaluation Board Packing and Marking Information: www.altera.com/support/reliability/packing/rel-packing-and-marking.html Pin Assignments (Top View) Figure 3: Pin Out Diagram (Top View) NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage. NOTE B: White `dot' on top left is pin 1 indicator on top of the device package. NOTE C: The Keep Out pin is the exposed metal below the package that is not to be mechanically or electrically connected to the PCB. www.altera.com/enpirion, Page 2 09644 March 9, 2017 Rev F EN6310QI Pin Description PIN NAME 1, 2, 2430 NC(SW) 3, 4 PGND 5-12 VOUT 15 NC 13 14 16 VFB AGND CSS 17 POK 18 ENABLE 19 AVIN 20, 21 PGND 22, 23 PVIN 31 PGND Bottom Pad FUNCTION NO CONNECT. Do not connect to any signal, voltage, or ground. These pins are connected internally to the MOSFET common switch node. Power ground. The output filter capacitor ground terminal should be connected to these pins. Refer to application details for proper layout and ground routing. Regulated output. Connect output capacitors from these pins to PGND (pins 3, 4). NO CONNECT. Do not connect to any signal, voltage, or ground. These pins may be connected internally. Output feed-back node. Connect to center of VOUT resistor divider. Quiet analog ground for control circuits. Connect to system ground plane. Soft Start startup time programming pin. Connect C SS capacitor from this pin to AGND. Power OK is an open drain transistor (pulled up to AVIN or similar voltage) used for power system state indication. POK is logic high when VOUT is above 90% of VOUT nominal. Leave this pin floating if not used. Output enable; Enable = logic high, Disable = logic low. Quiet input supply for circuitry. Power ground. The input filter capacitor ground terminal should be connected to these pins. Refer to application details for proper layout and ground routing. Input supply voltage for high side MOSFET Switch. Connect input filter capacitor from this pin to PGND. Device thermal pad to be connected to the system GND plane. See Layout Recommendations section. www.altera.com/enpirion, Page 3 09644 March 9, 2017 Rev F EN6310QI Absolute Maximum Ratings CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating conditions is not implied. Stress beyond the absolute maximum ratings may impair device life. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. MIN MAX UNITS Voltages on : PVIN, AVIN, VOUT PARAMETER SYMBOL -0.3 6.6 V Voltages on: ENABLE, POK -0.3 V IN +0.3 V Voltages on: VFB, SS -0.3 2.7 V -65 150 C 150 C Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A 260 C ESD Rating (based on Human Body Model) 2000 V ESD Rating (based on CDM) 500 V Storage Temperature Range T STG Maximum Operating Junction Temperature T J-ABS Max Recommended Operating Conditions PARAMETER SYMBOL MIN MAX UNITS V IN 2.7 5.5 V Output Voltage Range V OUT 0.60 3.3 V Output Current I OUT 1 A Input Voltage Range Operating Ambient Temperature TA -40 +85 C Operating Junction Temperature TJ -40 +125 C Thermal Characteristics PARAMETER SYMBOL TYP UNITS Thermal Shutdown T SD 140 C Thermal Shutdown Hysteresis T SDH 20 C JA 60 C/W Thermal Resistance: Junction to Ambient (0 LFM) (Note 1) Thermal Resistance: Junction to Case (0 LFM) 3 C/W JC Note 1: Based on 2oz. external copper layers and proper thermal design in line with EIJ/JEDEC JESD51-7 standard for high thermal conductivity boards. www.altera.com/enpirion, Page 4 09644 March 9, 2017 Rev F EN6310QI Electrical Characteristics NOTE: V IN (PVIN and AVIN) = 5.0V, Minimum and Maximum values are over operating ambient temperature range unless otherwise noted. Typical values are at T A = 25C. PARAMETER Input Voltage Range Under Voltage Lockout VIN Rising Under Voltage Lockout VIN Falling Output Voltage Range Maximum Duty Cycle Feedback Pin Voltage Initial Accuracy SYMBOL VIN MAX 5.5 UNITS V V UVLO_F 1.9 V V OUT D MAX VFB ENABLE Pin Input Current ENABLE Lock-out ENLO Switching Frequency Soft Start Time Allowable Soft Start Capacitor Range TYP 2.3 I VFB I OUT I OCP I SD I SD I OCP EN LOW EN HIGH I ENABLE ENABLE Pin Logic Threshold MIN 2.7 UVLO_R Output Voltage DC Accuracy Feedback Pin Input Current Continuous Output Current Over Current Trip Point AVIN Shut-Down Current PVIN Shut-Down Current OCP Threshold TEST CONDITIONS VIN = AVIN = PVIN 0.6 3.3 V % 0.609 V -2.0 +2.25 % -2.0 +2.0 % -3.0 +2.0 % 85 TA = 25C, VIN = 5.0V, I LOAD = 100mA; VIN = 3.3V; 0A I OUT 1.0A; -40C T A +85C VIN = 5.0V; 0A IOUT 1.0A; -20C T A +85C VIN = 5.0V; 0A IOUT 1.0A; -40C T A +85C (Note 3) 0.591 0.60 100 5 nA A A A A A V V A 12.5 ms 1 1.2 ENABLE = Low ENABLE = Low 2.7 VIN 5.5V Pin = Low Pin = High ENABLE = High Time before enable will re-assert internally after being pulled low 1.8 175 2.2 1.2 0.0 1.8 f SW T SS CSS = 10nF (Note 2 and 3) 5.2 C SS (Note 3) 0.47 0.4 VIN 2.2 6.5 7.8 MHz ms 10 nF Note 2: Soft Start Time range does not include capacitor tolerances. Note 3: Parameter not production tested but is guaranteed by design. www.altera.com/enpirion, Page 5 09644 March 9, 2017 Rev F EN6310QI Typical Performance Curves Efficiency vs. Output Current Efficiency vs. Output Current 95 95 90 90 85 85 EFFICIENCY (%) 100 EFFICIENCY (%) 100 80 75 VOUT = 2.5V 70 VOUT = 1.8V 65 VOUT = 1.5V 60 VOUT = 1.2V 55 VOUT = 1.0V 80 75 VOUT = 3.3V 70 VOUT = 2.5V VOUT = 1.8V 65 VOUT = 1.5V 60 CONDITIONS VIN = 3.3V VOUT = 1.2V 55 50 VOUT = 1.0V CONDITIONS VIN = 5.0V 50 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 OUTPUT CURRENT (A) 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 OUTPUT CURRENT (A) 1 Output Voltage vs. Output Current Output Voltage vs. Output Current 1.220 1.030 VIN = 5V OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) VIN = 3.3V 1.020 1.010 1.000 0.990 CONDITIONS VOUT = 1.0V 0.980 VIN = 5.0V 1.200 1.190 1.180 CONDITIONS VOUT = 1.2V 1.170 0.970 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 OUTPUT CURRENT (A) 0 1 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 OUTPUT CURRENT (A) 1 Output Voltage vs. Output Current Output Voltage vs. Output Current 1.820 1.520 1.510 OUTPUT VOLTAGE (V) VIN = 3.3V OUTPUT VOLTAGE (V) VIN = 3.3V 1.210 VIN = 5.0V 1.500 1.490 1.480 CONDITIONS VOUT = 1.5V VIN = 3.3V 1.810 VIN = 5.0V 1.800 1.790 1.780 1.770 CONDITIONS VOUT = 1.8V 1.760 1.750 1.470 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 OUTPUT CURRENT (A) 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 OUTPUT CURRENT (A) 1 www.altera.com/enpirion, Page 6 09644 March 9, 2017 Rev F EN6310QI Typical Performance Curves (Continued) Output Voltage vs. Output Current Output Voltage vs. Output Current 3.320 VIN = 5.0V VIN = 3.3V 2.530 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 2.540 VIN = 5.0V 2.520 2.510 2.500 2.490 CONDITIONS VOUT = 2.5V 2.480 3.310 3.300 3.290 3.280 CONDITIONS VOUT = 3.3V 3.270 2.470 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 OUTPUT CURRENT (A) 0 1 1.020 CONDITIONS VIN = 3.3V VOUT_NOM = 1.0V 1.015 1.010 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1 Output Voltage vs. Temperature Output Voltage vs. Temperature 1.020 1.005 1.000 LOAD = 0.05A 0.995 LOAD = 0.2A 0.990 LOAD = 0.4A LOAD = 0.8A 0.985 CONDITIONS VIN = 5.0V VOUT_NOM = 1.0V 1.015 1.010 1.005 1.000 LOAD = 0.05A 0.995 LOAD = 0.2A 0.990 LOAD = 0.4A LOAD = 0.8A 0.985 LOAD = 1A 0.980 LOAD = 1A 0.980 -40 -15 10 35 60 AMBIENT TEMPERATURE (C) 85 -40 -15 10 35 60 AMBIENT TEMPERATURE (C) 85 Output Voltage vs. Temperature Output Voltage vs. Temperature 3.360 2.560 CONDITIONS VIN = 3.3V VOUT_NOM = 2.5V 2.540 2.520 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 OUTPUT CURRENT (A) 2.500 2.480 LOAD = 0.05A 2.460 LOAD = 0.2A 2.440 LOAD = 0.4A 2.420 LOAD = 0.8A CONDITIONS VIN = 5.0V VOUT_NOM = 3.3V 3.340 3.320 3.300 3.280 LOAD = 0.05A LOAD = 0.2A 3.260 LOAD = 0.4A 3.240 LOAD = 0.8A LOAD = 1A LOAD = 1A 2.400 3.220 -40 -15 10 35 60 AMBIENT TEMPERATURE (C) 85 -40 -15 10 35 60 AMBIENT TEMPERATURE (C) 85 www.altera.com/enpirion, Page 7 09644 March 9, 2017 Rev F EN6310QI Typical Performance Curves (Continued) Output Voltage vs. Input Voltage OUTPUT VOLTAGE (V) 1.820 1.815 1.810 1.805 1.800 1.795 1.790 LOAD = 0A LOAD = 0.05A LOAD = 0.25A LOAD = 0.5A LOAD = 1A 1.785 1.780 1.775 CONDITIONS VOUT_NOM = 1.8V TA = 25C 1.770 2.5 3 3.5 4 4.5 INPUT VOLTAGE (V) 5 5.5 www.altera.com/enpirion, Page 8 09644 March 9, 2017 Rev F EN6310QI Typical Performance Characteristics Output Ripple at 20MHz Bandwidth Output Ripple at 20MHz Bandwidth VOUT (AC Coupled) CONDITIONS VIN = 3.3V VOUT = 1.2V IOUT = 0A CIN = 4.7F (0603) + 100pF COUT = 47 F (0805) VOUT (AC Coupled) Output Ripple at 500MHz Bandwidth VOUT (AC Coupled) Output Ripple at 500MHz Bandwidth CONDITIONS VIN = 3.3V VOUT = 1.2V IOUT = 0A CIN = 4.7F (0603) + 100pF COUT = 47 F (0805) VOUT (AC Coupled) CONDITIONS VIN = 3.3V VOUT = 1.2V IOUT = 1A CIN = 4.7F (0603) + 100pF COUT = 47 F (0805) Output Ripple at 500MHz Bandwidth Output Ripple at 500MHz Bandwidth VOUT (AC Coupled) CONDITIONS VIN = 3.3V VOUT = 1.2V IOUT = 1A CIN = 4.7F (0603) + 100pF COUT = 47 F (0805) CONDITIONS VIN = 5V VOUT = 1.2V IOUT = 0A CIN = 4.7F (0603) + 100pF COUT = 47 F (0805) VOUT (AC Coupled) CONDITIONS VIN = 5V VOUT = 1.2V IOUT = 1A CIN = 4.7F (0603) + 100pF COUT = 47 F (0805) www.altera.com/enpirion, Page 9 09644 March 9, 2017 Rev F EN6310QI Typical Performance Characteristics (Continued) Output Ripple at 500MHz Bandwidth VOUT (AC Coupled) Output Ripple at 500MHz Bandwidth CONDITIONS VIN = 5V VOUT = 3.3V IOUT = 0A CIN = 4.7F (0603) + 100pF COUT = 47 F (0805) Load Transient from 0A to 1A Load Transient from 0A to 1A VOUT = 1.8V (AC Coupled) 50mV / DIV VOUT = 1V (AC Coupled) 50mV / DIV CONDITIONS VIN = 3.3V, VOUT = 1V CIN = 4.7F (0603) + 100pF COUT = 47F (0805) Using Datasheet Recommended Components LOAD CONDITIONS VIN = 3.3V, VOUT = 1.8V CIN = 4.7F (0603) + 100pF COUT = 47F (0805) Using Datasheet Recommended Components LOAD Load Transient from 0A to 1A Load Transient from 0A to 1A VOUT = 1.0V (AC Coupled) 50mV / DIV VOUT = 2.5V (AC Coupled) 50mV / DIV LOAD VOUT (AC Coupled) CONDITIONS VIN = 5V VOUT = 3.3V IOUT = 1A CIN = 4.7F (0603) + 100pF COUT = 47 F (0805) CONDITIONS VIN = 3.3V, VOUT = 2.5V CIN = 4.7F (0603) + 100pF COUT = 47F (0805) Using Datasheet Recommended Components LOAD CONDITIONS VIN = 5.0V, VOUT = 1.0V CIN = 4.7F (0603) + 100pF COUT = 47F (0805) Using Datasheet Recommended Components www.altera.com/enpirion, Page 10 09644 March 9, 2017 Rev F EN6310QI Typical Performance Characteristics (Continued) Load Transient from 0A to 1A Load Transient from 0A to 1A VOUT = 1.8V (AC Coupled) 50mV / DIV VOUT = 1.8V (AC Coupled) 50mV / DIV LOAD CONDITIONS VIN = 5.0V, VOUT = 1.8V CIN = 4.7F (0603) + 100pF COUT = 47F (0805) Using Datasheet Recommended Components LOAD CONDITIONS VIN = 5.0V, VOUT = 3.3V CIN = 4.7F (0603) + 100pF COUT = 47F (0805) Using Datasheet Recommended Components Enable Startup/Shutdown Waveform (0A) Enable Startup/Shutdown Waveform (1A) ENABLE ENABLE VOUT VOUT POK POK CONDITIONS VIN = 5V, VOUT = 1.8V, No Load, Css = 10nF CIN = 4.7F (0603) + 100pF, COUT = 47 F (0805) LOAD LOAD Enable Startup Waveform (0A) CONDITIONS VIN = 5V, VOUT = 1.8V, 1A Load, Css = 10nF CIN = 4.7F (0603) + 100pF, COUT = 47 F (0805) Enable Shutdown Waveform (0A) ENABLE ENABLE VOUT VOUT POK POK CONDITIONS VIN = 5V, VOUT = 1.8V, No Load, Css = 10nF CIN = 4.7F (0603) + 100pF, COUT = 47 F (0805) CONDITIONS VIN = 5V, VOUT = 1.8V, No Load, Css = 10nF CIN = 4.7F (0603) + 100pF, COUT = 47 F (0805) LOAD LOAD www.altera.com/enpirion, Page 11 09644 March 9, 2017 Rev F EN6310QI Functional Block Diagram PVIN UVLO Thermal Limit Current Limit NC(SW) P-Drive (-) PWM Comp (+) Logic VOUT N-Drive PGND PLL/Sawtooth Generator Compensation Network (-) Error Amp (+) VFB Power OK POK ENABLE Soft Start Internal Reference CSS Internal Regulator AGND AVIN Figure 4: Functional Block Diagram www.altera.com/enpirion, Page 12 09644 March 9, 2017 Rev F EN6310QI Functional Description Functional Overview Integration for Low-Noise Low-EMI The EN6310QI is a synchronous buck converter with integrated MOSFET switches and Inductor. The device can deliver up to 1A of continuous load current. The EN6310QI has a programmable soft start rise time and a power OK (POK) signal. The device operates in a fixed 2.2MHz PWM mode to eliminate noise associated with pulse frequency modulation schemes. The control topology is a low complexity type IV voltage mode providing high noise immunity and stability over the entire operating range. Output voltage is set with a simple resistor divider. The high switching frequency enables the use of small MLCC input and output filter capacitors. Figure 4 shows the EN6310QI block diagram. The EN6310QI utilizes a proprietary low loss integrated inductor. The integration of the inductor greatly simplifies the power supply design process. The inherent shielding and compact construction of the integrated inductor reduces the conducted and radiated noise that can couple into the traces of the printed circuit board. Furthermore, the package layout is optimized to reduce the electrical path length for the high di/dt input AC ripple currents that are a major source of radiated emissions from DCDC converters. Careful package and IC design minimize common mode noise that can be difficult to mitigate otherwise. The integrated inductor provides the optimal solution to the complexity, output ripple, and noise that plague low power DCDC converter design. Protection Features: The EN6310QI has the following protection features. * Over-current protection (to protect the IC from excessive load current) * Short-Circuit protection * Thermal shutdown with hysteresis * Under-voltage lockout circuit to disable the converter output when the input voltage is below a pre-defined level Additional Features: * Soft-start circuit, limiting the in-rush current when the converter is initially powered up. The soft start time is programmable with appropriate choice of soft start capacitor value Control Topology The EN6310QI utilizes an internal type IV voltage mode compensation scheme. Voltage mode control provides a high degree of noise immunity at light load currents so that low ripple and high accuracy are maintained over the entire load range. The high switching frequency allows for a very wide control loop bandwidth and hence excellent transient performance. The EN6310QI is optimized for fast transient recovery for applications with demanding transient performance. Voltage mode control enables a high degree of stability over the entire operating range. High Efficiency Technology Enable The key enabler of this revolutionary integration is Enpirion's proprietary power MOSFET technology. The advanced MOSFET switches are implemented in deep-submicron CMOS to supply very low switching loss at high switching frequencies and to allow a high level of integration. The semiconductor process allows seamless integration of all switching, control, and compensation circuitry. The EN6310QI ENABLE pin enables and disables operation of the device. A logic low will disable the converter and cause it to shut down. A logic high will enable the converter and initiate a normal soft start operation. When ENABLE is pulled low, the Power MOSFETs stop switching and the output is discharged in a controlled manner with a soft pull down MOSFET. Once the enable pin is pulled low, there is a lockout period before the device can be reenabled. The lock out period can be found in the Electrical Characteristics Table. Do not leave ENABLE pin floating or it will be in an unknown random state. The proprietary magnetics design provides highdensity/high-value magnetics in a very small footprint. Enpirion magnetics are carefully matched to the control and compensation circuitry yielding an optimal solution with assured performance over the entire operating range. The EN6310QI supports startup into a pre-biased output of up to 1.5V. The output of the EN6310QI can be pre-biased with a voltage up to 1.5V when it is first enabled. www.altera.com/enpirion, Page 13 09644 March 9, 2017 Rev F EN6310QI POK Operation The POK signal is an open drain signal (requires a pull up resistor to AVIN or similar voltage) from the converter indicating the output voltage is within the specified range. Typically, a 100k or lower resistance is used as the pull-up resistor. The POK signal will be logic high (AVIN) when the output voltage is above 90% of the programmed voltage level. If the output voltage is below this point, the POK signal will be a logic low. The POK will also be a logic low if the input voltage is in UVLO or if the ENABLE is pulled low. The POK signal can be used to sequence down-stream converters by tying to their enable pins. Programmable Soft Start Operation Soft start is externally programmable by adjusting the value of the C SS capacitor, which is placed between the respective C SS pin and AGND pin. When the enable pin is pulled high, the output will ramp up monotonically at a rate determined by the CSS capacitor. Soft start ramp time is programmable over a range of 0.5ms to 10ms. The longer ramp times allow startup into very large bulk capacitors that may be present in applications such as wireless broadband or solid state storage, without triggering an Over Current condition. The rise time is given as: T RISE [ms] = C SS [nF] 0.65 25% NOTE: Rise time does not include capacitor tolerances. If a 10nF soft-start capacitor is used, then the output voltage rise time will be around 6.5ms. The rise time is measured from when V IN V UVLOR and ENABLE pin voltage crosses its logic high threshold to when V OUT reaches its programmed value. Over Current/Short Circuit Protection The current limit and short-circuit protection is achieved by sensing the current flowing through a sense PFET. When the sensed current exceeds the current limit, both NFET and PFET switches are turned off and the output is discharged. After 1.6ms the device will be re-enabled and will then go through a normal soft-start cycle. If the over current condition persists, the device will enter a hiccup mode. Under Voltage Lockout During initial power up an under voltage lockout circuit will hold-off the switching circuitry until the input voltage reaches a sufficient level to insure proper operation. If the voltage drops below the UVLO threshold, the lockout circuitry will again disable the switching. Hysteresis is included to prevent chattering between states. Thermal Shutdown When excess power is dissipated in the EN6310QI the junction temperature will rise. Once the junction temperature exceeds the thermal shutdown temperature the thermal shutdown circuit turns off the converter output voltage thus allowing the device to cool. When the junction temperature decreases to a safe operating level, the part will go through the normal startup process. The thermal shutdown temperature and hysteresis values can be found in the electrical characteristics table. www.altera.com/enpirion, Page 14 09644 March 9, 2017 Rev F EN6310QI Application Information VOUT Output Voltage Programming VOUT The EN6310QI output voltage is programmed using a simple resistor divider network (R A and R B ). The feedback voltage at VFB is nominally 0.6V. R A is fixed at 200k and R B can be calculated based on Figure 5. The values recommended for C OUT , C A , and R CA make up the external compensation of the EN6310QI. It will vary with each VIN and VOUT combination to optimize on performance. Please see Table 1 for a list of recommended R A , C A , R CA , and C OUT values for each solution. Since VFB is a sensitive node, do not touch the VFB node while the device is in operation as doing so may introduce parasitic capacitance into the control loop that causes the device to behave abnormally and damage may occur. The output voltage is set by the following formula: = 1 + Rearranging to solve for R B : Where: = - R A = 200k VREF = 0.60V COUT RCA VFB = 0.6V PGND RB = EN6310QI 120 - 0.6 VOUT - VFB CIN = 4.7F/0603 + 100pF CAVIN = 20 + 0.47F COUT = 47F/0805 or 2x22F/0603 R A = 200k, R CA = 1k, R B = 0.6R A /(V OUT - 0.6) V IN (V) 5.5 V OUT (V) Ca (pF) 15 V IN (V) 5.5 5 3.3 15 5 4.5 15 4.5 5.5 15 3.3 33 15 2.7 39 15 5.5 39 3.3 15 5 39 5.5 15 4.5 5 15 3.3 47 15 2.7 47 3.3 22 5.5 39 2.7 22 5 39 5.5 22 4.5 5 22 3.3 56 22 2.7 56 4.5 R A is chosen as 200k to provide constant loop gain. The output voltage can be programmed over the range of 0.6V to 3.3V. VFB x RA Figure 5. External Compensation 4.5 = CA VFB 5 Then R B is given as: RA 4.5 2.5 1.8 1.5 3.3 27 2.7 33 V OUT (V) Ca (pF) 27 27 1.2 1 0.6 33 39 47 Table 1. Compensation values. For output voltages in between, use the values from the higher output voltage www.altera.com/enpirion, Page 15 09644 March 9, 2017 Rev F EN6310QI Input Filter Capacitor Output Filter Capacitor The EN6310QI requires at least a 4.7F/0603 and a 100pF input capacitor near the PVIN pins. Low-cost, low-ESR ceramic capacitors should be used as input capacitors for this converter. The dielectric must be X5R or X7R rated. Y5V or equivalent dielectric formulations must not be used as these lose too much capacitance with frequency, temperature and bias voltage. In some applications, lower value capacitors are needed in parallel with the larger capacitors in order to provide high frequency decoupling. Table 2 contains a list of recommended input capacitors. The EN6310QI requires at least a 47F/0805 or two 22F/0603 output filter capacitors. Low ESR ceramic capacitors are required with X5R or X7R rated dielectric formulation. Y5V or equivalent dielectric formulations must not be used as these lose too much capacitance with frequency, temperature and bias voltage. Table 3 contains a list of recommended output capacitors. Description 4.7F, 10V, X5R, 10%, 0603 4.7F, 10V, X5R, 10%, 0603 MFG P/N Murata GRM185R61A475KE11# Taiyo Yuden LMK107BJ475KA-T Table 2. Recommended Input Capacitors Description 47F, 6.3V, X5R, 20%, 0805 47F, 6.3V, X5R, 20%, 0805 22F, 10V, X5R, 20%, 0603 22F, 10V, X5R, 20%, 0603 MFG P/N Murata GRM21BR60J476ME15# Taiyo Yuden JMK212BBJ476MG-T Murata GRM188R60J226MEA0# Taiyo Yuden JMK107BBJ226MA-T Table 3. Recommended Output Capacitors www.altera.com/enpirion, Page 16 09644 March 9, 2017 Rev F EN6310QI Thermal Considerations Thermal considerations are important power supply design facts that cannot be avoided in the real world. Whenever there are power losses in a system, the heat that is generated by the power dissipation needs to be accounted for. The Enpirion PowerSoC helps alleviate some of those concerns. The Enpirion EN6310QI DC-DC converter is packaged in a 4x5x1.85mm 30-pin QFN package. The QFN package is constructed with copper lead frames that have exposed thermal pads. The exposed thermal pad on the package should be soldered directly on to a copper ground pad on the printed circuit board (PCB) to act as a heat sink. The recommended maximum junction temperature for continuous operation is 125C. Continuous operation above 125C may reduce long-term reliability. The device has a thermal overload protection circuit designed to turn off the device at an approximate junction temperature value of 140C. The following example and calculations illustrate the thermal performance of the EN6310QI. = P OUT / P IN = 91% = 0.91 P IN = P OUT / P IN 3.3W / 0.91 3.63W The power dissipation (P D ) is the power loss in the system and can be calculated by subtracting the output power from the input power. P D = P IN - P OUT 3.63W - 3.3W 0.33W With the power dissipation known, the temperature rise in the device may be estimated based on the theta JA value ( JA ). The JA parameter estimates how much the temperature will rise in the device for every watt of power dissipation. The EN6310QI has a JA value of 60 C/W without airflow. Determine the change in temperature (T) based on P D and JA . T = P D x JA T 0.33W x 60C/W 19.8C 20C V IN = 5V The junction temperature (T J ) of the device is approximately the ambient temperature (T A ) plus the change in temperature. We assume the initial ambient temperature to be 25C. V OUT = 3.3V T J = T A + T I OUT = 1A T J 25C + 20C 45C First calculate the output power. The maximum operating junction temperature (T JMAX ) of the device is 125C, so the device can operate at a higher ambient temperature. The maximum ambient temperature (T AMAX ) allowed can be calculated. Example: P OUT = 3.3V x 1A = 3.3W Next, determine the input power based on the efficiency () shown in Figure 6. T AMAX = T JMAX - P D x JA Efficiency vs. Output Current 100 125C - 20C 105C 95 The maximum ambient temperature the device can reach is 105C given the input and output conditions. Note that the efficiency will be slightly lower at higher temperatures and this calculation is an estimate. EFFICIENCY (%) 90 85 80 75 70 65 60 VOUT = 3.3V 55 CONDITIONS VIN = 5.0V 50 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 OUTPUT CURRENT (A) 1 Figure 6. Efficiency vs. Output Current For V IN = 5V, V OUT = 3.3V at 1A, 91% www.altera.com/enpirion, Page 17 09644 March 9, 2017 Rev F EN6310QI Engineering Schematic VOUT VIN VOUT PVIN CIN2 4.7F CIN1 100pF EN6310QI RAVIN 20 ON OFF COUT 47F 0805 ENABLE AVIN RA CAVIN 0.47F CA RCA VFB SS PGND PGND CSS 10nF AGND RB Figure 7. Typical Engineering Schematic www.altera.com/enpirion, Page 18 09644 March 9, 2017 Rev F EN6310QI Layout Recommendation Figure 8. Evaluation Board Layout Recommendations Recommendation 1: Input and output filter capacitors should be placed on the same side of the PCB, and as close to the EN6310QI package as possible. They should be connected to the device with very short and wide traces. Do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. The +V and GND traces between the capacitors and the EN6310QI should be as close to each other as possible so that the gap between the two nodes is minimized, even under the capacitors. www.altera.com/enpirion, Page 19 09644 March 9, 2017 Rev F EN6310QI Recommendation 2: The system ground plane should be the first layer immediately below the surface layer. This ground plane should be continuous and un-interrupted below the converter and the input/output capacitors. Please see the Gerber files on EN6310QI's product page at www.altera.com/enpirion. Recommendation 3: The large thermal pad underneath the component must be connected to the system ground plane through as many vias as possible. The drill diameter of the vias should be 0.33mm, and the vias must have at least 1 oz. copper plating on the inside wall, making the finished hole size around 0.20-0.26mm. Do not use thermal reliefs or spokes to connect the vias to the ground plane. This connection provides the path for heat dissipation from the converter. See Figure 8. Recommendation 4: Multiple small vias (the same size as the thermal vias discussed in recommendation 3 should be used to connect ground terminal of the input capacitor and output capacitors to the system ground plane. It is preferred to put these vias under the capacitors along the edge of the GND copper closest to the +V copper. Please see Figure 8. These vias connect the input/output filter capacitors to the GND plane, and help reduce parasitic inductances in the input and output current loops. If the vias cannot be placed under C IN and C OUT , then put them just outside the capacitors along the GND slit separating the two components. Do not use thermal reliefs or spokes to connect these vias to the ground plane. Recommendation 5: AVIN is the power supply for the internal small-signal control circuits. It should be connected to the input voltage at a quiet point. A good location is to place the AVIN connection on the source side of the input capacitor, away from the PVIN pins. Recommendation 6: The layer 1 metal under the device must not be more than shown in Figure 8. See the section regarding exposed metal on bottom of package. As with any switchmode DC/DC converter, try not to run sensitive signal or control lines underneath the converter package on other layers. Recommendation 7: The V OUT sense point should be just after the last output filter capacitor. Keep the sense trace as short as possible in order to avoid noise coupling into the control loop. Recommendation 8: Keep R A , C A , and R B close to the VFB pin (see Figures 6 and 7). The VFB pin is a high-impedance, sensitive node. Keep the trace to this pin as short as possible. Whenever possible, connect R B directly to the AGND pin instead of going through the GND plane. www.altera.com/enpirion, Page 20 09644 March 9, 2017 Rev F EN6310QI Recommended PCB Footprint Figure 9. EN6310QI PCB Footprint (Top View) Note: Don't use the layer underneath the device keep out area as it contains the exposed metal below the package that is not to be mechanically or electrically connected to the PCB. www.altera.com/enpirion, Page 21 09644 March 9, 2017 Rev F EN6310QI Package and Mechanical Figure 10. EN6310QI Package Dimensions (Bottom View) Packing and Marking Information: www.altera.com/support/reliability/packing/rel-packing-and-marking.html www.altera.com/enpirion, Page 22 09644 March 9, 2017 Rev F EN6310QI Revision History Rev Date A B C March 2014 March 2015 June 2015 D Feb 2016 E June 2016 F Feb 2017 Change(s) * * * * * * * * * * * * Introductory production datasheet Pin 12 changed to VOUT instead of NC Updated the pre-bias section adding the capability of pre-biasing to voltage up to 1.5V Changed Feedback Pin Voltage Initial Accuracy on Electrical Characteristics Table Corrected thermal hysteresis value in thermal shutdown section Added section on "Design considerations for lead-frame based modules" i.e. keepout area Modified PCB Footprint and package drawings Formatting changes Added EMI scan data Clarified location of Gerber files in layout recommendation section Updating the device package drawings with the keep-out area drawing. Drawing the Keep-out Pins in figure 3. Contact Information Altera Corporation 101 Innovation Drive San Jose, CA 95134 Phone: 408-544-7000 www.altera.com (c) 2014 Altera Corporation--Confidential. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. www.altera.com/enpirion, Page 23 09644 March 9, 2017 Rev F