Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LMP2021, LMP2022 SNOSAY9G - SEPTEMBER 2008 - REVISED FEBRUARY 2016 LMP202x Zero-Drift, Low-Noise, EMI-Hardened Amplifiers 1 Features 3 Description The LMP2021 and LMP2022 are single and dual precision operational amplifiers offering ultra low input offset voltage, near zero input offset voltage drift, very low input voltage noise and very high open loop gain. They are part of the LMPTM precision family and are ideal for instrumentation and sensor interfaces. (Typical Values, TA = 25C, VS = 5 V) 1 * * * * * * * * * * * * * * * Input Offset Voltage (Typical) -0.4 V Input Offset Voltage (Max) 5 V Input Offset Voltage Drift (Typical) -0.004 V/C Input Offset Voltage Drift (Max) 0.02 V/C Input Voltage Noise, AV = 1000 11 nV/Hz Open Loop Gain 160 dB CMRR 139 dB PSRR 130 dB Supply Voltage Range 2.2 V to 5.5 V Supply Current (per Amplifier) 1.1 mA Input Bias Current 25 pA GBW 5 MHz Slew Rate 2.6 V/s Operating Temperature Range -40C to 125C 5-Pin SOT-23, 8-Pin VSSOP and 8-Pin SOIC Packages The LMP202x has only 0.004 V/C of input offset voltage drift, and 0.4 V of input offset voltage. These attributes provide great precision in high accuracy applications. The proprietary continuous auto zero correction circuitry ensures impressive CMRR and PSRR, removes the 1/f noise component, and eliminates the need for calibration in many circuits. With only 260 nVPP (0.1 Hz to 10 Hz) of input voltage noise and no 1/f noise component, the LMP202x are suitable for low frequency applications such as industrial precision weigh scales. The extremely high open loop gain of 160 dB drastically reduces gain error in high gain applications. With ultra precision DC specifications and very low noise, the LMP202x are ideal for position sensors, bridge sensors, pressure sensors, medical equipment and other high accuracy applications with very low error budgets. 2 Applications * * * * Precision Instrumentation Amplifiers Battery Powered Instrumentation Thermocouple Amplifiers Bridge Amplifiers The LMP2021 is offered in 5-Pin SOT-23 and 8-Pin SOIC packages. The LMP2022 is offered in 8-Pin VSSOP and 8-Pin SOIC packages. Device Information(1) PART NUMBER LMP2021 LMP2022 PACKAGE BODY SIZE (NOM) SOIC (8) 4.90 mm x 3.91 mm SOT-23 (5) 2.90 mm x 1.60 mm SOIC (8) 4.90 mm x 3.91 mm VSSOP (8) 3.00 mm x 3.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Bridge Amplifier VA VA = 5V + 1/2 LMP2022 EMI R1 - 0.1 PF R4 1 k: 200: 5.1 k: 0.1% VA R2 R3 ADC161S626 - + VA - 0.1 PF 5.1 k: 0.1% 1/2 LMP2022 + 1 + LMP2021 280: VA 470 pF 180: VR = 1/2 VA 200: 1 k: The LMP202x support systems with up to 24 bits of accuracy. An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMP2021, LMP2022 SNOSAY9G - SEPTEMBER 2008 - REVISED FEBRUARY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions SC-70 and VSSOP references from LMP2021 pinout descriptions............................................................ Specifications......................................................... 1 1 1 2 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 5 7 9 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics: 2.5 V ................................ Electrical Characteristics: 5 V ................................... Typical Characteristics .............................................. 3 4 Detailed Description ............................................ 15 7.1 Overview ................................................................. 15 7.2 Functional Block Diagram ....................................... 15 7.3 Feature Description................................................. 15 7.4 Device Functional Modes........................................ 15 8 Application and Implementation ........................ 17 8.1 Application Information............................................ 17 8.2 Typical Application .................................................. 23 9 Power Supply Recommendations...................... 24 10 Layout................................................................... 24 10.1 Layout Guidelines ................................................. 24 10.2 Layout Example .................................................... 25 11 Device and Documentation Support ................. 26 11.1 11.2 11.3 11.4 11.5 11.6 Device Support .................................................... Documentation Support ........................................ Related Links ........................................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 26 26 26 26 26 26 12 Mechanical, Packaging, and Orderable Information ........................................................... 27 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (December 2014) to Revision G Page * Deleted SC-70 and VSSOP references from LMP2021 pinout descriptions ......................................................................... 3 * Deleted DCK and DGK packages and corrected SOT-23 pin function table for LMP2021 .................................................. 3 Changes from Revision E (March 2013) to Revision F * Page Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 Changes from Revision D (March 2013) to Revision E * 2 Page Changed layout of National Data Sheet to TI format ........................................................................................................... 23 Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP2021 LMP2022 LMP2021, LMP2022 www.ti.com SNOSAY9G - SEPTEMBER 2008 - REVISED FEBRUARY 2016 5 Pin Configuration and Functions N/C + V -IN - V - +IN 3 4 -IN V - 8 2 - 2 + +IN 1 3 + 4 7 + -IN A OUT +IN A V 6 5 OUT A N/C N/C V - 1 8 A 2 3 7 B + 5 1 D and DGK Packages: LMP2022 8 Pin VSSOP or SOIC TOP VIEW + OUT D Package: LMP2021 8 Pin SOIC TOP VIEW 4 6 - DVB Package: LMP2021 5 Pin SOT-23 TOP VIEW 5 + V OUT B -IN B +IN B Pin Functions: LMP2021 PIN LMP2021 NAME I/O DBV D OUT 1 6 +IN 3 -IN 4 V- DESCRIPTION I Output 3 I Non-Inverting Input 2 O Inverting Input 2 4 P Negative Supply V+ 5 7 P Positive Supply N/C - 1 - No Internal Connection N/C - 5 - No Internal Connection N/C - 8 - No Internal Connection Pin Functions: LMP2022 PIN LMP2022 I/O DESCRIPTION NAME D, DGK +IN A 3 I Non-Inverting input, channel A +IN B 5 I Non-Inverting input, channel B -IN A 2 I Inverting input, channel A -IN B 6 I Inverting input, channel B OUT A 1 O Output, channel A OUT B 7 O Output, channel B V+ 8 P Positive (highest) power supply V- 4 P Negative (lowest) power supply Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP2021 LMP2022 Submit Documentation Feedback 3 LMP2021, LMP2022 SNOSAY9G - SEPTEMBER 2008 - REVISED FEBRUARY 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings (1) (2) VIN Differential MIN MAX -VS VS 6.0 V V+ + 0.3 V- - 0.3 V Supply Voltage (VS = V+ - V-) All Other Pins + - (3) Output Short-Circuit Duration to V or V Junction Temperature (4) Soldering Information Infrared or Convection (20 sec) Tstg Storage temperature range (1) (2) (3) (4) Wave Soldering Lead Temperature (10 sec) -65 UNIT 5 seconds 150 C 235 C 260 C 150 C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics Tables. If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. Package power dissipation should be observed. The maximum power dissipation is a function of TJ(MAX), JA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ JA. All numbers apply for packages soldered directly onto a PC board. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) 2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) 1000 Machine model 200 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Temperature Range -40 125 C Supply Voltage (VS = V+ - V-) 2.2 5.5 V 6.4 Thermal Information THERMAL METRIC (1) RJA (1) 4 Junction-to-ambient thermal resistance LMP2021, LMP2022 LMP2021 LMP2022 D DBV DGK 8 PINS 5 PINS 8 PINS 106 164 217 UNIT C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP2021 LMP2022 LMP2021, LMP2022 www.ti.com SNOSAY9G - SEPTEMBER 2008 - REVISED FEBRUARY 2016 6.5 Electrical Characteristics: 2.5 V (1) Unless otherwise specified, all limits are ensured for TA = 25C, V+ = 2.5 V, V- = 0 V, VCM = V+/2, RL >10 k to V+/2. PARAMETER VOS TEST CONDITIONS Input Offset Voltage -40C TJ 125C MIN (2) TYP (3) -5 -0.9 -10 MAX (2) 5 Input Offset Voltage Drift (4) -0.02 0.001 0.02 IB Input Bias Current -100 23 100 IOS Input Offset Current CMRR CMVR EMIRR Common Mode Rejection Ratio Input Common-Mode Voltage Range AVOL VOUT Large Signal CMRR 105 dB -0.2 1.7 0 1.5 40 VRF-PEAK = 100 mVP (-20 dBVP) f = 900 MHz 48 VRF-PEAK = 100 mVP (-20 dBVP) f = 1800 MHz 67 VRF-PEAK = 100 mVP (-20 dBVP) f = 2400 MHz 79 2.5 V V+ 5.5 V, VCM = 0 115 2.5 V V+ 5.5 V, VCM = 0 , -40C TJ 125C 112 2.2 V V+ 5.5 V, VCM = 0 110 130 RL = 10 k to V /2, VOUT = 0.5 V to 2 V 124 150 RL = 10 k to V+/2, VOUT = 0.5 V to 2 V, -40C TJ 125C 119 RL = 2 k to V+/2, VOUT = 0.5 V to 2 V 120 RL = 2 k to V+/2, VOUT = 0.5 V to 2 V, -40C TJ 125C 115 + 30 mV from either 45 rail 55 RL = 10 k to V /2 58 75 RL = 2 k to V+/2, -40C TJ 125C (5) 85 115 RL = 2 k to V+/2 (4) 50 70 62 RL = 10 k to V+/2, -40C TJ 125C (2) (3) dB 150 RL = 2 k to V+/2, -40C TJ 125C (1) dB dB 38 RL = 2 k to V+/2 Linear Output Current V 130 RL = 10 k to V /2, -40C TJ 125C IOUT pA dB + Output Swing Low pA 141 VRF-PEAK = 100 mVP (-20 dBVP) f = 400 MHz RL = 10 k to V+/2 Output Swing High 250 102 + Large Signal Voltage Gain 200 105 Electro-Magnetic Interference Rejection Ratio (5) Power Supply Rejection Ratio 57 -250 -0.2 V VCM 1.7 V, 0 V VCM 1.5 V, -40C TJ 125C Large Signal CMRR 102 dB, -40C TJ 125C V/C 300 -0.2 V VCM 1.7 V, 0 V VCM 1.5 V IN+ and IN- PSRR -300 -200 -40C TJ 125C V 10 TCVOS -40C TJ 125C UNIT 95 Sourcing, VOUT = 2 V 30 50 Sinking, VOUT = 0.5 V 30 50 mA Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. All limits are specified by testing, statistical analysis or design. Typical values represent the most likely parametric norm at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Offset voltage temperature drift is determined by dividing the change in VOS at the temperature extremes by the total temperature change. The EMI Rejection Ratio is defined as EMIRR = 20Log ( VRF-PEAK/VOS). Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP2021 LMP2022 Submit Documentation Feedback 5 LMP2021, LMP2022 SNOSAY9G - SEPTEMBER 2008 - REVISED FEBRUARY 2016 www.ti.com Electrical Characteristics: 2.5 V(1) (continued) Unless otherwise specified, all limits are ensured for TA = 25C, V+ = 2.5 V, V- = 0 V, VCM = V+/2, RL >10 k to V+/2. PARAMETER IS Supply Current MIN (2) TEST CONDITIONS Per Amplifier TYP (3) MAX (2) 0.95 1.10 Per Amplifier, -40C TJ 125C SR Slew Rate (6) AV = +1, CL = 20 pF, RL = 10 k VO = 2 VPP GBW Gain Bandwidth Product GM Gain Margin M CIN en V/s CL = 20 pF, RL = 10 k 5 MHz CL = 20 pF, RL = 10 k 10 dB Phase Margin CL = 20 pF, RL = 10 k 60 deg Input Capacitance Common Mode 12 Differential Mode 12 Input-Referred Voltage Noise Density f = 0.1 kHz or 10 kHz, AV = 1000 11 f = 0.1 kHz or 10 kHz, AV = 100 15 Input-Referred Voltage Noise 0.1 Hz to 10 Hz 260 0.01 Hz to 10 Hz 330 350 fA/Hz 50 s 150 dB Input-Referred Current Noise f = 1 kHz tr Recovery time to 0.1%, RL = 10 k, AV = -50, VOUT = 1.25 VPP Step, Duration = 50 s CT Cross Talk LMP2022, f = 1 kHz 6 mA 2.5 In (6) 1.37 UNIT pF nV/Hz nVPP The number specified is the average of rising and falling slew rates and is measured at 90% to 10%. Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP2021 LMP2022 LMP2021, LMP2022 www.ti.com SNOSAY9G - SEPTEMBER 2008 - REVISED FEBRUARY 2016 6.6 Electrical Characteristics: 5 V (1) Unless otherwise specified, all limits are ensured for TA = 25C, V+ = 5 V, V- = 0 V, VCM = V+/2, RL > 10 k to V+/2. PARAMETER VOS TEST CONDITIONS Input Offset Voltage -40C TJ 125C MIN (2) TYP (3) -5 -0.4 -10 MAX (2) UNIT 5 V 10 TCVOS Input Offset Voltage Drift (4) -0.02 -0.004 0.02 V/C IB Input Bias Current -100 25 100 pA IOS Input Offset Current -40C TJ 125C -200 -40C TJ 125C CMRR CMVR EMIRR Common Mode Rejection Ratio Input Common-Mode Voltage Range AVOL VOUT 250 115 Large Signal CMRR 120 dB -0.2 4.2 0 4.0 dB 58 VRF-PEAK = 100 mVP (-20 dBVP) f = 900 MHz 64 VRF-PEAK = 100 mVP (-20 dBVP) f = 1800 MHz 72 VRF-PEAK = 100 mVP (-20 dBVP) f = 2400 MHz 82 2.5 V V+ 5.5 V, VCM = 0 115 2.5 V V+ 5.5 V, VCM = 0, -40C TJ 125C 112 2.2 V V+ 5.5 V, VCM = 0 110 130 RL = 10 k to V /2, VOUT = 0.5 V to 4.5 V 125 160 RL = 10 k to V+/2, VOUT = 0.5 V to 4.5 V, -40C TJ 125C 120 RL = 2 k to V+/2, VOUT = 0.5 V to 4.5 V 123 RL = 2 k to V+/2, VOUT = 0.5 V to 4.5 V, -40C TJ 125C 118 RL = 10 k to V+/2 RL = 10 k to V /2 65 RL = 2 k to V+/2 103 RL = 2 k to V+/2, -40C TJ 125C (4) (5) 160 mV from either 80 rail 105 204 + RL = 10 k to V+/2, -40C TJ 125C (2) (3) 135 170 120 RL = 2 k to V+/2, -40C TJ 125C (1) dB 160 83 RL = 2 k to V+/2 Linear Output Current dB dB RL = 10 k to V /2, -40C TJ 125C IOUT V 130 + Output Swing Low pA 139 VRF-PEAK = 100 mVP (-20 dBVP) f = 400 MHz + Output Swing High 200 120 Electro-Magnetic Interference Rejection Ratio (5) Large Signal Voltage Gain -250 -0.2 V VCM 4.2 V, 0 V VCM 4.0 V, -40C TJ 125C Large Signal CMRR 115 dB, -40C TJ 125C Power Supply Rejection Ratio 300 48 -0.2 V VCM 4.2 V, 0 V VCM 4.0 V IN+ and IN- PSRR -300 125 158 Sourcing, VOUT = 4.5 V 30 50 Sinking, VOUT = 0.5 V 30 50 mA Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. All limits are specified by testing, statistical analysis or design. Typical values represent the most likely parametric norm at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Offset voltage temperature drift is determined by dividing the change in VOS at the temperature extremes by the total temperature change. The EMI Rejection Ratio is defined as EMIRR = 20Log ( VRF-PEAK/VOS). Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP2021 LMP2022 Submit Documentation Feedback 7 LMP2021, LMP2022 SNOSAY9G - SEPTEMBER 2008 - REVISED FEBRUARY 2016 www.ti.com Electrical Characteristics: 5 V(1) (continued) Unless otherwise specified, all limits are ensured for TA = 25C, V+ = 5 V, V- = 0 V, VCM = V+/2, RL > 10 k to V+/2. PARAMETER IS Supply Current MIN (2) TEST CONDITIONS Per Amplifier TYP (3) MAX (2) 1.1 1.25 Per Amplifier, -40C TJ 125C SR Slew Rate (6) AV = +1, CL = 20 pF, RL = 10 k VO = 2 VPP GBW Gain Bandwidth Product GM Gain Margin M CIN en V/s CL = 20 pF, RL = 10 k 5 MHz CL = 20 pF, RL = 10 k 10 dB Phase Margin CL = 20 pF, RL = 10 k 60 deg Input Capacitance Common Mode 12 Differential Mode 12 Input-Referred Voltage Noise Density f = 0.1 kHz or 10 kHz, AV= 1000 11 f = 0.1 kHz or 10 kHz, AV= 100 15 Input-Referred Voltage Noise 0.1 Hz to 10 Hz Noise 260 0.01 Hz to 10 Hz Noise 330 350 fA/Hz 50 s 150 dB Input-Referred Current Noise f = 1 kHz tr Input Overload Recovery time to 0.1%, RL = 10 k, AV = -50, VOUT = 2.5 VPP Step, Duration = 50 s CT Cross Talk LMP2022, f = 1 kHz 8 mA 2.6 In (6) 1.57 UNIT pF nV/Hz nVPP The number specified is the average of rising and falling slew rates and is measured at 90% to 10%. Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP2021 LMP2022 LMP2021, LMP2022 www.ti.com SNOSAY9G - SEPTEMBER 2008 - REVISED FEBRUARY 2016 6.7 Typical Characteristics Unless otherwise noted: TA = 25C, RL > 10 k, VS= V+ - V-, VS= 5 V, VCM = VS/2. 16 TA = 25C 12 VCM = VS/2 10 8 6 4 PERCENTAGE (%) PERCENTAGE (%) 14 UNITS TESTED > 1700 VS = 2.5V 14 2 UNITS TESTED > 1700 12 -40C d TA d 125C VS = 2.5V 10 VCM = VS/2 8 6 4 2 0 -5 -4 -3 -2 -1 0 1 2 3 4 0 -20 5 -10 VOS (PV) Figure 1. Offset Voltage Distribution 16 UNITS TESTED = 6200 VS = 5V 16 10 VCM = VS/2 10 8 6 PERCENTAGE (%) VCM = VS/2 12 UNITS TESTED = 6200 VS = 5V 14 TA = 25C 14 12 -40C d TA d 125C 10 8 6 4 4 2 2 0 -5 -4 -3 -2 -1 0 1 2 3 4 0 -20 5 -10 0 10 20 TCVOS (nV/C) VOS (PV) Figure 4. TCVOS Distribution Figure 3. Offset Voltage Distribution 140 10 VS = 2.5V, 5V VCM = VS/2 120 5 100 -PSRR PSRR (dB) OFFSET VOLTAGE (PV) 20 Figure 2. TCVOS Distribution 18 PERCENTAGE (%) 0 TCVOS (nV/C) -40C 0 25C 85C 80 60 +PSRR 40 -5 125C 20 -10 2 2.5 3 3.5 4 4.5 5 5.5 0 10 100 1k 10k 100k 1M FREQUENCY (Hz) SUPPLY VOLTAGE (V) Figure 5. Offset Voltage vs. Supply Voltage Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP2021 LMP2022 Figure 6. PSRR vs. Frequency Submit Documentation Feedback 9 LMP2021, LMP2022 SNOSAY9G - SEPTEMBER 2008 - REVISED FEBRUARY 2016 www.ti.com Typical Characteristics (continued) Unless otherwise noted: TA = 25C, RL > 10 k, VS= V+ - V-, VS= 5 V, VCM = VS/2. Figure 7. Input Bias Current vs. VCM Figure 8. Input Bias Current vs. VCM 10 10 OFFSET VOLTAGE (PV) 5 -40C 25C 0 85C -5 125C -10 -0.2 0.2 0.6 1 1.4 -40C 85C -5 125C 1.4 0.6 2.2 3.8 3 4.6 COMMON MODE VOLTAGE (V) Figure 9. Offset Voltage vs. VCM Figure 10. Offset Voltage vs. VCM 125C 1.25 85C 25C 1 -40C 0.75 2 2.5 3 3.5 4 4.5 5 5.5 100 GAIN = 1000 VS = 5V 10 VS = 2.5V 1 10 SUPPLY VOLTAGE (V) Submit Documentation Feedback 100 1k 10k 100k FREQUENCY (Hz) Figure 11. Supply Current vs. Supply Voltage (Per Amplifier) 10 25C 0 COMMON MODE VOLTAGE (V) 1.5 SUPPLY CURRENT (mA) 5 -10 -0.2 1.8 INPUT VOLTAGE NOISE DENSITY (nV/ Hz) OFFSET VOLTAGE (PV) VS = 2.5V Figure 12. Input Voltage Noise vs. Frequency Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP2021 LMP2022 LMP2021, LMP2022 www.ti.com SNOSAY9G - SEPTEMBER 2008 - REVISED FEBRUARY 2016 Typical Characteristics (continued) Unless otherwise noted: TA = 25C, RL > 10 k, VS= V+ - V-, VS= 5 V, VCM = VS/2. 120 100 150 100 150 PHASE 60 30 20 120 80 GAIN (dB) 90 60 40 180 90 60 40 PHASE 30 20 VS = 2.5V VS = 5V 0 RL = 2 k:, 10 k:, 10 M: CL = 20 pF, 50 pF, 100 pF -20 100k 10k 100 1k 0 RL = 2 k:, 10 k:, 10 M: CL = 20 pF, 50 pF, 100 pF -20 100k 10k 100 1k 0 -30 10M 1M FREQUENCY (Hz) 120 180 160 150 140 -30 10M 20 VS = 5V RL = 10 k: EMIRR (dB) 60 GAIN PHASE () 90 40 120 120 PHASE 60 100 80 VS = 5V 60 30 40 VS = 2.5V 0 0 CL = 20 pF TA = -40C, 25C, 85C, 125C -20 100k 10k 100 1k 1M 20 -30 10M 0 10 100 FREQUENCY (Hz) 1000 10000 FREQUENCY (MHz) Figure 15. Open Loop Frequency Response Over Temperature Figure 16. EMIRR vs. Frequency 140 120 VS = 5V VS = 2.5V 120 100 fRF = 2400 MHz 40 20 60 -10 0 fRF = 400 MHz fRF = 900 MHz 20 fRF = 900 MHz -20 fRF = 1800 MHz 80 40 fRF = 400 MHz -30 EMIRR (dB) fRF = 1800 MHz 60 0 -40 fRF = 2400 MHz 100 80 EMIRR (dB) 1M Figure 14. Open Loop Frequency Response 100 80 0 FREQUENCY (Hz) Figure 13. Open Loop Frequency Response GAIN (dB) 60 PHASE () 120 PHASE () GAIN (dB) 120 GAIN GAIN 80 180 10 20 30 0 -40 -30 -20 -10 0 10 20 30 RF INPUT SIGNAL PEAK (dBm) RF INPUT SIGNAL PEAK (dBm) Figure 17. EMIRR vs. Input Power Figure 18. EMIRR vs. Input Power Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP2021 LMP2022 Submit Documentation Feedback 11 LMP2021, LMP2022 SNOSAY9G - SEPTEMBER 2008 - REVISED FEBRUARY 2016 www.ti.com Typical Characteristics (continued) Unless otherwise noted: TA = 25C, RL > 10 k, VS= V+ - V-, VS= 5 V, VCM = VS/2. Figure 19. Time Domain Input Voltage Noise 160 VS = 2.5V 3 VS = 2.5V, 5V VIN = 1 VPP AV = +1 f = 10 kHz VCM = VS/2 140 2.8 SLEW RATE (V/Ps) VS = 5V 120 CMRR (dB) Figure 20. Time Domain Input Voltage Noise 100 80 RL = 10 k: CL = 20 pF FALLING EDGE 2.6 2.4 RISING EDGE 2.2 60 40 10 100 1k 10k 2 100k 2 2.5 FREQUENCY (Hz) 3 3.5 4 4.5 5 5.5 SUPPLY VOLTAGE (V) Figure 21. CMRR vs. Frequency Figure 22. Slew Rate vs. Supply Voltage 160 200 RL = 2 k: RL = 2 k: 125C 125C VOUT from RAIL (mV) VOUT from RAIL (mV) 160 85C 120 25C 80 -40C 120 85C 25C 80 -40C 40 40 0 0 2 2.5 3 3.5 4 4.5 5 5.5 2 SUPPLY VOLTAGE (V) Submit Documentation Feedback 3 3.5 4 4.5 5 5.5 SUPPLY VOLTAGE (V) Figure 23. Output Swing High vs. Supply Voltage 12 2.5 Figure 24. Output Swing Low vs. Supply Voltage Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP2021 LMP2022 LMP2021, LMP2022 www.ti.com SNOSAY9G - SEPTEMBER 2008 - REVISED FEBRUARY 2016 Typical Characteristics (continued) Unless otherwise noted: TA = 25C, RL > 10 k, VS= V+ - V-, VS= 5 V, VCM = VS/2. 120 200 RL = 10 k: RL = 10 k: 100 VOUT from RAIL (mV) VOUT from RAIL (mV) 160 125C 120 85C 80 25C 40 -40C 125C 80 40 -40C 20 0 2.5 3 3.5 4 4.5 5 25C 60 0 2 85C 5.5 2 3 3.5 4 4.5 5 5.5 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 25. Output Swing High vs. Supply Voltage Figure 26. Output Swing Low vs. Supply Voltage 50 mV/DIV INPUT VS = 5V 50 mV/DIV INPUT 2.5 AV = -50 V/V RL = 10 k: VS = 5V AV = -50 V/V RL = 10 k: | | 1 V/DIV OUTPUT 1 V/DIV OUTPUT 2 Ps/DIV 10 Ps/DIV Figure 27. Overload Recovery Time Figure 28. Overload Recovery Time 20 mV/DIV 200 mV/DIV | | VS = 2.5V AV = +1 VIN = 1 VPP f = 10 kHz VS = 2.5V AV = +1 VIN = 100 mVPP f = 10 kHz RL = 10 k: RL = 10 k: CL = 20 pF CL = 20 pF 10 Ps/DIV 10 Ps/DIV Figure 29. Large Signal Step Response Figure 30. Small Signal Step Response Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP2021 LMP2022 Submit Documentation Feedback 13 LMP2021, LMP2022 SNOSAY9G - SEPTEMBER 2008 - REVISED FEBRUARY 2016 www.ti.com Typical Characteristics (continued) 20 mV/DIV 500 mV/DIV Unless otherwise noted: TA = 25C, RL > 10 k, VS= V+ - V-, VS= 5 V, VCM = VS/2. VS = 5V AV = +1 VS = 5V AV = +1 VIN = 2 VPP f = 10 kHz VIN = 100 mVPP f = 10 kHz RL = 10 k: RL = 10 k: CL = 20 pF CL = 20 pF 10 Ps/DIV 10 Ps/DIV Figure 31. Large Signal Step Response Figure 32. Small Signal Step Response 200 + VS = 2.5V, 5V + VOUT from RAIL (V) (V ) -0.2 + (V ) -0.4 + (V ) -0.6 0.4 | 125C 85C 25C -40C | 0.2 0 0 5 10 15 20 25 30 35 40 CROSSTALK REJECTION RATIO (dB) V VS = 2.5V 180 Channel A to B 160 140 120 14 Submit Documentation Feedback Channel B to A 80 60 10 100 1k 10k 100k 1M FREQUENCY (Hz) OUTPUT CURRENT (mA) Figure 33. Output Voltage vs. Output Current VS = 5V 100 Figure 34. Cross Talk Rejection Ratio vs. Frequency (LMP2022) Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP2021 LMP2022 LMP2021, LMP2022 www.ti.com SNOSAY9G - SEPTEMBER 2008 - REVISED FEBRUARY 2016 7 Detailed Description 7.1 Overview The LMP202x are single and dual precision operational amplifiers with ultra low offset voltage, ultra low offset voltage drift, and very low input voltage noise with no 1/f and extended supply voltage range. The LMP202x offer on chip EMI suppression circuitry which greatly enhances the performance of these precision amplifiers in the presence of radio frequency signals and other high frequency disturbances. The LMP202x utilize proprietary auto zero techniques to measure and continuously correct the input offset error voltage. The LMP202x have a DC input offset voltage with a maximum value of 5 V and an input offset voltage drift maximum value of 0.02 V/C. The input voltage noise of the LMP202x is less than 11 nV/Hz at a voltage gain of 1000 V/V and has no flicker noise component. This makes the LMP202x ideal for high accuracy, low frequency applications where lots of amplification is needed and the input signal has a very small amplitude. The proprietary input offset correction circuitry enables the LMP202x to have superior CMRR and PSRR performances. The combination of an open loop voltage gain of 160 dB, CMRR of 142 dB, PSRR of 130 dB, along with the ultra low input offset voltage of only -0.4 V, input offset voltage drift of only -0.004 V/C, and input voltage noise of only 260 nVPP at 0.1 Hz to 10 Hz make the LMP202x great choices for high gain transducer amplifiers, ADC buffer amplifiers, DAC I-V conversion, and other applications requiring precision and long-term stability. Other features are rail-to-rail output, low supply current of 1.1 mA per amplifier, and a gainbandwidth product of 5 MHz. The LMP202x have an extended supply voltage range of 2.2 V to 5.5 V, making them ideal for battery operated portable applications. The LMP2021 is offered in 5-pin SOT-23 and 8-pin SOIC packages. The LMP2022 is offered in 8-pin VSSOP and 8-Pin SOIC packages. 7.2 Functional Block Diagram 7.3 Feature Description The amplifier's differential inputs consist of a non-inverting input (+IN) and an inverting input (-IN). The amplifier amplifies only the difference in voltage between the two inputs, which is called the differential input voltage. The output voltage of the op-amp Vout is given by Equation 1: VOUT = AOL (IN+ - IN-) (1) where AOL is the open-loop gain of the amplifier, typically around 100dB (100,000x, or 10uV per Volt). 7.4 Device Functional Modes 7.4.1 EMI Suppression The near-ubiquity of cellular, Bluetooth, and Wi-Fi signals and the rapid rise of sensing systems incorporating wireless radios make electromagnetic interference (EMI) an evermore important design consideration for precision signal paths. Though RF signals lie outside the op amp band, RF carrier switching can modulate the DC offset of the op amp. Also some common RF modulation schemes can induce down-converted components. The added DC offset and the induced signals are amplified with the signal of interest and thus corrupt the measurement. The LMP202x use on chip filters to reject these unwanted RF signals at the inputs and power supply pins; thereby preserving the integrity of the precision signal path. Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP2021 LMP2022 Submit Documentation Feedback 15 LMP2021, LMP2022 SNOSAY9G - SEPTEMBER 2008 - REVISED FEBRUARY 2016 www.ti.com Device Functional Modes (continued) Twisted pair cabling and the active front-end's common-mode rejection provide immunity against low frequency noise (i.e. 60 Hz or 50 Hz mains) but are ineffective against RF interference. Figure 46 displays this. Even a few centimeters of PCB trace and wiring for sensors located close to the amplifier can pick up significant 1 GHz RF. The integrated EMI filters of LMP202x reduce or eliminate external shielding and filtering requirements, thereby increasing system robustness. A larger EMIRR means more rejection of the RF interference. For more information on EMIRR, please refer to AN-1698 (Literature Number SNOA497). 7.4.2 Input Voltage Noise The input voltage noise density of the LMP202x has no 1/f corner, and its value depends on the feedback network used. This feature of the LMP202x differentiates this family from other products currently available from other vendors. In particular, the input voltage noise density decreases as the closed loop voltage gain of the LMP202x increases. The input voltage noise of the LMP202x is less than 11 nV/Hz when the closed loop voltage gain of the op amp is 1000. Higher voltage gains are required for smaller input signals. When the input signal is smaller, a lower input voltage noise is quite advantageous and increases the signal to noise ratio. INPUT VOLTAGE NOISE DENSITY (nV/ Hz) Figure 35 shows the input voltage noise of the LMP202x as the closed loop gain increases. 24 VS = 5V f = 100 Hz 20 16 12 8 4 0 1 10 100 1000 CLOSED LOOP GAIN (V/V) Figure 35. Input Voltage Noise Density decreases with Gain INPUT VOLTAGE NOISE DENSITY (nV/ Hz) Figure 36 shows the input voltage noise density does not have the 1/f component. 100 GAIN = 100 GAIN = 10 GAIN = 51 10 GAIN = 250 GAIN = 1000 GAIN = 500 1 10 100 1k 10k FREQUENCY (Hz) Figure 36. Input Voltage Noise Density with no 1/f With smaller and smaller input signals and high precision applications with lower error budget, the reduced input voltage noise and no 1/f noise allow more flexibility in circuit design. 16 Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP2021 LMP2022 LMP2021, LMP2022 www.ti.com SNOSAY9G - SEPTEMBER 2008 - REVISED FEBRUARY 2016 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information 8.1.1 Achieving Lower Noise With Filtering The low input voltage noise of the LMP202x, and no 1/f noise make these suitable for many applications with noise sensitive designs. Simple filtering can be done on the LMP202x to remove high frequency noise. Figure 37 shows a simple circuit that achieves this. In Figure 37 CF and the corner frequency of the filter resulting from CF and RF will reduce the total noise. RIN//RF IN + - CF RF RIN Figure 37. Noise Reducing Filter for Lower Gains In order to achieve lower noise floors for even more noise stringent applications, a simple filter can be added to the op amp's output after the amplification stage. Figure 38 shows the schematic of a simple circuit which achieves this objective. Low noise amplifiers such as the LMV771 can be used to create a single pole low pass filter on the output of the LMP202x. The noise performance of the filtering amplifier, LMV771 in this circuit, will not be dominant as the input signal on LMP202x has already been significantly gained up and as a result the effect of the input voltage noise of the LMV771 is effectively not noticeable. CFILT RIN/RF RFILT IN + RFILT LMP2021/ LMP2022 - RF LMV771 + OUT RIN Figure 38. Enhanced Filter to Further Reduce Noise at Higher Gains Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP2021 LMP2022 Submit Documentation Feedback 17 LMP2021, LMP2022 SNOSAY9G - SEPTEMBER 2008 - REVISED FEBRUARY 2016 www.ti.com Application Information (continued) Using the circuit in Figure 38 has the advantage of removing the non-linear filter bandwidth dependency which is seen when the circuit in Figure 37 is used. The difference in noise performance of the circuits in Figure 37 and Figure 38 becomes apparent only at higher gains. At voltage gains of 10 V/V or less, there is no difference between the noise performance of the two circuits. 10 RMS NOISE (PV) AV = 40 dB 1 2-Stage Filter AV = 60 dB 0.1 0.01 10 100 1k 10k 3 dB FILTER BANDWIDTH (Hz) Figure 39. RMS Input Referred Noise vs. Frequency Figure 39 shows the total input referred noise vs. 3 dB corner of both filters of Figure 37 and Figure 38 at gains of 100V/V and 1000V/V. For these measurements and using Figure 37's circuit, RF = 49.7 k and RIN = 497. Value of CF has been changed to achieve the desired 3 dB filter corner frequency. In the case of Figure 38's circuit, RF = 49.7 k and RIN = 497, RFILT = 49.7 k, and CFILT has been changed to achieve the desired 3 dB filter corner frequency. Figure 39 compares the RMS noise of these two circuits. As Figure 39 shows, the RMS noise measured the circuit in Figure 38 has lower values and also depicts a more linear shape. 8.1.2 Input Bias Current The bias current of the LMP202x behaves differently than a conventional amplifier due to the dynamic transient currents created on the input of an auto-zero circuit. The input bias current is affected by the charge and discharge current of the input auto-zero circuit. This effectivly creates a repetitive impulse current noise of 100's of pA. For this reason, the LMP202x is not recommeded for source impedances of 1 M or greater. The amount of current sunk or sourced from that stage is dependent on the combination of input impedance (resistance and capacitance), as well as the balance and matching of these impedances across the two inputs. This current, integrated by the input capacitence, causes a shift in the apparent "bias current". Because of this, there is an apparent "bias current vs. input impedance" interaction. In the LMP202x for an input resistive impedance of 1 G, the shift in input bias current can be up to 40 pA. This input bias shift is caused by varying the input's capacitive impedance. Since the input bias current is dependent on the input impedance, it is difficult to estimate what the actual bias current is without knowing the end circuit and associated capacitive strays. Figure 40 shows the input bias current of the LMP202x and that of another commercially available amplifier from a competitor. As it can be seen, the shift in LMP202x bias current is much lower than that of other chopper style or auto zero amplifiers available from other vendors. 18 Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP2021 LMP2022 LMP2021, LMP2022 www.ti.com SNOSAY9G - SEPTEMBER 2008 - REVISED FEBRUARY 2016 Application Information (continued) LMP2021/LMP2022 CG = 0, 1, 3, 5, 8, 10, 20, 50, 75, 100, 200, 500, 1000 pF VS = 5V, VCM = VS/2, RG = 1 G: 150 IBIAS (pA) Competitor A 175 CG = 1000 pF 150 125 125 100 100 75 50 75 CG = 1000 pF CG = 20 pF CG = 20 pF 50 25 25 0 0 IBIAS (pA) 175 -25 -25 -50 0 -50 CG = 0 pF CG = 0 pF -75 10 20 30 40 50 60 70 80 90 100 10 20 30 40 50 60 70 80 -75 90 100 TIME (s) TIME (s) Figure 40. Input Bias Current of LMP202x is lower than Competitor A 8.1.3 Lowering the Input Bias Current As mentioned in the Input Bias Current section, the input bias current of an auto zero amplifier such as the LMP202x varies with input impedance and feedback impedance. Once the value of a certain input resistance, i.e. sensor resistance, is known, it is possible to optimize the input bias current for this fixed input resistance by choosing the capacitance value that minimizes that current. Figure 41 shows the input bias current vs. input impedance of the LMP202x. The value of RG or input resistance in this test is 1 G. When this value of input resistance is used, and when a parallel capacitance of 22 pF is placed on the circuit, the resulting input bias current is nearly 0 pA. Figure 41 can be used to extrapolate capacitor values for other sensor resistances. For this purpose, the total impedance seen by the input of the LMP202x needs to be calculated based on Figure 41. By knowing the value of RG, one can calculate the corresponding CG which minimizes the non-inverting input bias current, positive bias current, value. POSITIVE BIAS CURRENT (pA) 30 18 6 -6 + RG -18 CG -30 1 10 100 1000 INPUT CAPACITANCE (pF) Figure 41. Input Bias Current vs. CG with RG = 1 G In a typical I-V converter, the output voltage will be the sum of DC offset plus bias current and the applied signal through the feedback resistor. In a conventional input stage, the inverting input's capacitance has very little effect on the circuit. This effect is generally on settling time and the dielectric soakage time and can be ignored. In auto zero amplifiers, the input capacitance effect will add another term to the output. This additional term means that the baseline reading on the output will be dependent on the input capacitance. The term input capacitance for this purpose includes circuit strays and any input cable capacitances. There is a slight variation in the capacitive Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP2021 LMP2022 Submit Documentation Feedback 19 LMP2021, LMP2022 SNOSAY9G - SEPTEMBER 2008 - REVISED FEBRUARY 2016 www.ti.com Application Information (continued) offset as the duty cycle and amplitude of the pulses vary from part to part, depending on the correction at the time. The lowest input current will be obtained when the impedances, both resistive and capacitive, are matched between the inputs. By balancing the input capacitances, the effect can be minimized. A simple way to balance the input impedance is adding a capacitance in parallel to the feedback resistance. The addition of this feedback capacitance reduces the bias current and increases the stability of the operational amplifier. Figure 42 shows the input bias current of the LMP202x when RF is set to 1 G. As it can be seen from Figure 42, choosing the optimum value of CF will help reducing the input bias current. NEGATIVE BIAS CURRENT (pA) 156 130 104 78 CF 52 RF + 26 0 1 10 100 1000 FEEDBACK CAPACITANCE (pF) Figure 42. Input Bias Current vs. CF with RF = 1 G The effect of bias current on a circuit can be estimated with the following: AV*IBIAS+*ZS - IBIAS-*ZF (2) Where AV is the closed loop gain of the system and IBIAS+ and IBIAS- denote the positive and negative bias current, respectively. It is common to show the average of these bias currents in product datasheets. If IBIAS+ and IBIAS- are not individually specified, use the IBIAS value provided in datasheet graphs or tables for this calculation. For the application circuit shown in Figure 46, the LMP2022 amplifiers each have a gain of 18. With a sensor impedance of 500 for the bridge, and using the above equation, the total error due to the bias current on the outputs of the LMP2022 amplifier will be less than 200 nV. 8.1.4 Sensor Impedance The sensor resistance, or the resistance connected to the inputs of the LMP202x, contributes to the total impedance seen by the auto correcting input stage. RIN VIN + VIN_DIFF FEEDBACK NETWORK 20 Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP2021 LMP2022 LMP2021, LMP2022 www.ti.com SNOSAY9G - SEPTEMBER 2008 - REVISED FEBRUARY 2016 Application Information (continued) RON_SWITCH RIN VIN VOUT INPUT SWITCHES + VIN_DIFF COUT Figure 43. Auto Correcting Input Stage Model As shown in Figure 43, the sum of RIN and RON-SWITCH will form a low pass filter with COUT during correction cycles. As RIN increases, the time constant of this filter increases, resulting in a slower output signal which could have the effect of reducing the open loop gain, AVOL, of the LMP202x. In order to prevent this reduction in AVOL in presence of high impedance sensors or other high resistances connected to the input of the LMP202x, a capacitor can be placed in parallel to this input resistance. This is shown in Figure 44. CIN RIN VIN + VIN_DIFF FEEDBACK NETWORK CIN RON_SWITCH RIN VIN VOUT INPUT SWITCHES + VIN_DIFF COUT Figure 44. Sensor Impedance with Parallel Capacitance CIN in Figure 44 adds a zero to the low pass filter and hence eliminating the reduction in AVOL of the LMP202x. An alternative circuit to achieve this is shown in Figure 45. RIN VIN + CIN VIN_DIFF FEEDBACK NETWORK Figure 45. Alternative Sensor Impedance Circuit Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP2021 LMP2022 Submit Documentation Feedback 21 LMP2021, LMP2022 SNOSAY9G - SEPTEMBER 2008 - REVISED FEBRUARY 2016 www.ti.com Application Information (continued) 8.1.5 Transient Response to Fast Inputs On chip continuous auto zero correction circuitry eliminates the 1/f noise and significantly reduces the offset voltage and offset voltage drift; all of which are very low frequency events. For slow changing sensor signals this correction is transparent. For excitations which may otherwise cause the output to swing faster than 40 mV/s, there are additional considerations which can be viewed two perspectives: for sine waves and for steps. For sinusoidal inputs, when the output is swinging rail-to-rail on 2.5-V supplies, the auto zero circuitry will introduce distortions above 2.55 kHz. For smaller output swings, higher frequencies can be amplified without the auto zero slew limitation as shown in table below. Signals above 20 kHz, are not affected, though normally, closed loop bandwidth should be kept below 20 kHz so as to avoid aliasing from the auto zero circuit. VOUT-PEAK (V) fMAX-SINE WAVE 0.32 20 1 6.3 2.5 2.5 (kHz) For step-like inputs, such as those arising from disturbances to a sensing system, the auto zero slew rate limitation manifests itself as an extended ramping and settling time, lasting ~100 s. 8.1.6 Digital Acquisition Systems High resolution ADC's with 16-bits to 24-bits of resolution can be limited by the noise of the amplifier driving them. The circuit configuration, the value of the resistors used and the source impedance seen by the amplifier can affect the noise of the amplifier. The total noise at the output of the amplifier can be dominated by one of several sources of noises such as: white noise or broad band noise, 1/f noise, thermal noise, and current noise. In low frequency applications such as medical instrumentation, the source impedance is generally low enough that the current noise coupled into it does not impact the total noise significantly. However, as the 1/f or flicker noise is paramount to many application, the use of an auto correcting stabilized amplifier like the LMP202x reduces the total noise. Table 1 summarizes the input and output referred RMS noise values for the LMP202x compared to that of Competitor A. As described in previous sections, the outstanding noise performance of the LMP202x can be even further improved by adding a simple low pass filter following the amplification stage. The use of an additional filter, as shown in Figure 38 benefits applications with higher gain. For this reason, at a gain of 10, only the results of circuit in Figure 37 are shown. The RMS input noise of the LMP202x are compared with Competitor A's input noise performance. Competitor A's RMS input noise behaves the same with or without an additional filter. Table 1. RMS Input Noise Performance Amplifier Gain (V/V) 10 100 1000 (1) 22 RMS Input Noise (nV) System Bandwidth Requirement (Hz) LMP202x Competitor A Figure 37 Circuit Figure 38 Circuit Figure 37, Figure 38 Circuit 229 See (1) 300 1000 763 (1) 100 229 196 300 1000 763 621 1030 10 71 46 95 100 158 146 300 1000 608 462 1030 100 See 1030 No significant difference in Noise measurements at AV = 10V/V Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP2021 LMP2022 LMP2021, LMP2022 www.ti.com SNOSAY9G - SEPTEMBER 2008 - REVISED FEBRUARY 2016 8.2 Typical Application Figure 46 shows the Bridge Sensor Interface for these devices. VA VA = 5V + 1/2 LMP2022 EMI R1 - 0.1 PF R4 1 k: 200: 5.1 k: 0.1% VA VA 470 pF 180: R2 + LMP2021 280: ADC161S626 - + R3 VA - 0.1 PF 5.1 k: 0.1% 1/2 LMP2022 + VR = 1/2 VA 200: 1 k: Figure 46. LMP202x Used With ADC161S626 8.2.1 Design Requirements Bridge sensors are used in a variety of applications such as pressure sensors and weigh scales. Bridge sensors typically have a very small differential output signal. This very small differential signal needs to be accurately amplified before it can be fed into an ADC. As discussed in the previous sections, the accuracy of the op amp used as the ADC driver is essential to maintaining total system accuracy. The high DC performance of the LMP202x make these amplifiers ideal choices for use with a bridge sensor. The LMP202x have very low input offset voltage and very low input offset voltage drift. The open loop gain of the LMP202x is 160 dB. The circuit in Figure 46 shows a signal path solution for a typical bridge sensor using the LMP202x. Bridge sensors are created by replacing at least one of the resistors in a typical bridge with a sensor whose resistance varies in response to an external stimulus. For this example, the expected bridge output signal will be in the range of 12 mV. This signal must be accurately amplified by the amplifier to best match the dynamic input range of the ADC. This is done by using one LMP2022 and one LMP2021 in front of the ADC161S626. The on chip EMI rejection filters available on the LMP202x help remove the EMI interference introduced to the signal and hence improve the overall system performance. 8.2.2 Detailed Design Procedure The amplification of this 12 mV signal is achieved in 2 stages and through a three op-amp instrumentation amplifier. The dual LMP2022 in Figure 46 amplifies each side of the differential output of the bridge sensor by a gain of 18.2. Using the LMP2022 with a gain of 18.2 reduces the input referred voltage noise of the op amps and the system as a result. Also, this gain allows direct filtering of the signal on the LMP2022 without compromising noise performance. The differential output of the two amplifiers in the LMP2022 are then fed into a LMP2021 configured as a difference amplifier. This stage has a gain of 5, with a total system having a gain of (18.2 * 2 +1 ) * 5 = 187. The LMP2021 has an outstanding CMRR value of 139. This impressive CMRR improves system performance by removing the common mode signal introduced by the bridge. With an overall gain of 187, the 12 mV differential input signal is gained up to 2.24V (0.26 V to 4.74V single ended). This utilizes the amplifiers output swing as well as the ADC's input dynamic range, and allows for some overload range. Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP2021 LMP2022 Submit Documentation Feedback 23 LMP2021, LMP2022 SNOSAY9G - SEPTEMBER 2008 - REVISED FEBRUARY 2016 www.ti.com Typical Application (continued) Bridge sensor measurements are usually done up to 10s of Hz. Placing a 300 Hz filter on the LMP2022 helps removing the higher frequency noise from this circuit. This filter is created by placing two capacitors in the feedback path of the LMP2022 amplifiers. This amplified signal is then fed into the ADC161S626. The ADC161S626 is a 16-bit, 50 kSPS to 250 kSPS 5V ADC. In order to utilize the maximum number of bits of the ADC161S626 in this configuration, a 2.5V reference voltage is used. This 2.5V reference is also used to power the bridge sensor and the inverting input of the ADC. Using the same voltage source for these three points helps reducing the total system error by eliminating error due to source variations. With this system, the output signal of the bridge sensor which can be up to 13.3 mV and is accurately scaled to the full scale range of the ADC and then digitized for further processing. The LMP202x introduced minimal error to the system and improved the signal quality by removing common mode signals and high frequency noise. 8.2.3 Application Curve 5.0 4.5 4.0 VOUT (V) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -12 -10 -8 -6 -4 -2 0 2 4 6 8 DIFFERENTIAL INPUT (mV) 10 12 C001 Figure 47. Single Ended Output Results for Bridge Circuit 9 Power Supply Recommendations The LMP202x is specified for operation from 2.2 V to 5.5 V (1.1 V to 2.75 V) over a -40C to +125C temperature range. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in the Typical Characteristics. CAUTION Supply voltages larger than 6 V can permanently damage the device. 10 Layout 10.1 Layout Guidelines For best operational performance of the device, use good printed circuit board (PCB) layout practices, including: * Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. * Connect low-ESR, 0.1-F ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single supply applications. * Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective 24 Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP2021 LMP2022 LMP2021, LMP2022 www.ti.com SNOSAY9G - SEPTEMBER 2008 - REVISED FEBRUARY 2016 Layout Guidelines (continued) * * * * methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds paying attention to the flow of the ground current. For more detailed information refer to SLOA089, Circuit Board Layout Techniques. In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed to in parallel with the noisy trace. Place the external components as close to the device as possible. As shown in Typical Characteristics, keeping RF and RG close to the inverting input minimizes parasitic capacitance. Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit. Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials. 10.2 Layout Example + VIN VOUT RG RF (Schematic Representation) Run the input traces as far away from the supply lines as possible Place components close to device and to each other to reduce parasitic errors VS+ RF N/C N/C GND IN V+ VIN +IN OUTPUT V N/C RG Use low-ESR, ceramic bypass capacitor GND GND Use low-ESR, ceramic bypass capacitor VOUT VS Ground (GND) plane on another layer Figure 48. Operational Amplifier Board Layout for Noninverting Configuration Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP2021 LMP2022 Submit Documentation Feedback 25 LMP2021, LMP2022 SNOSAY9G - SEPTEMBER 2008 - REVISED FEBRUARY 2016 www.ti.com 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support LMP2021/22 PSPICE Model, SNOM100 TINA-TI SPICE-Based Analog Simulation Program, http://www.ti.com/tool/tina-ti TI Filterpro Software, http://www.ti.com/tool/filterpro DIP Adapter Evaluation Module, http://www.ti.com/tool/dip-adapter-evm TI Universal Operational Amplifier Evaluation Module, http://www.ti.com/tool/opampevm Manual for LMH730268 Evaluation board 551012922-001 11.2 Documentation Support 11.2.1 Related Documentation SBOA015 (AB-028) -- Feedback Plots Define Op Amp AC Performance. SLOA089 -- Circuit Board Layout Techniques. SLOD006 -- Op Amps for Everyone. SNOA497 -- AN-1698 A Specification for EMI Hardened Operational Amplifiers. SBOA128 -- EMI Rejection Ratio of Operational Amplifiers. TIPD128 -- Capacitive Load Drive Solution using an Isolation Resistor. SBOA092 --- Handbook of Operational Amplifier Applications. 11.3 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 2. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY LMP2021 Click here Click here Click here Click here Click here LMP2022 Click here Click here Click here Click here Click here 11.4 Trademarks LMP is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.6 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 26 Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP2021 LMP2022 LMP2021, LMP2022 www.ti.com SNOSAY9G - SEPTEMBER 2008 - REVISED FEBRUARY 2016 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: LMP2021 LMP2022 Submit Documentation Feedback 27 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) LMP2021MA/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMP20 21MA LMP2021MAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMP20 21MA LMP2021MF/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 AF5A LMP2021MFE/NOPB ACTIVE SOT-23 DBV 5 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 AF5A LMP2021MFX/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 AF5A LMP2022MA/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMP20 22MA LMP2022MAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMP20 22MA LMP2022MM/NOPB ACTIVE VSSOP DGK 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 AV5A LMP2022MME/NOPB ACTIVE VSSOP DGK 8 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 AV5A LMP2022MMX/NOPB ACTIVE VSSOP DGK 8 3500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 AV5A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 10-Dec-2020 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 13-Aug-2020 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMP2021MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMP2021MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMP2021MFE/NOPB SOT-23 DBV 5 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMP2021MFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMP2022MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMP2022MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMP2022MME/NOPB VSSOP DGK 8 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMP2022MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 13-Aug-2020 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMP2021MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMP2021MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LMP2021MFE/NOPB SOT-23 DBV 5 250 210.0 185.0 35.0 LMP2021MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LMP2022MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMP2022MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LMP2022MME/NOPB VSSOP DGK 8 250 210.0 185.0 35.0 LMP2022MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 0.1 C B A 5 2X 0.95 1.9 1.45 0.90 3.05 2.75 1.9 2 4 0.5 5X 0.3 0.2 3 (1.1) C A B 0.15 TYP 0.00 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] A .004 [0.1] C PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .150 [3.81] .189-.197 [4.81-5.00] NOTE 3 4X (0 -15 ) 4 5 B 8X .012-.020 [0.31-0.51] .010 [0.25] C A B .150-.157 [3.81-3.98] NOTE 4 .069 MAX [1.75] .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 [0.11-0.25] 0 -8 .016-.050 [0.41-1.27] DETAIL A (.041) [1.04] TYPICAL 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X METAL SOLDER MASK OPENING EXPOSED METAL .0028 MAX [0.07] ALL AROUND SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL .0028 MIN [0.07] ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. 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