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Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. "Standard": 8. 9. 10. 11. 12. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. DATA SHEET MOS INTEGRATED CIRCUIT PD431000A-X 1M-BIT CMOS STATIC RAM 128K-WORD BY 8-BIT EXTENDED TEMPERATURE OPERATION Description The PD431000A-X is a high speed, low power, and 1,048,576 bits (131,072 words by 8 bits) CMOS static RAM. The PD431000A-X has two chip enable pins (/CE1, CE2) to extend the capacity. And battery backup is available. In addition to this, A and B versions are low voltage operations. The PD431000A-X is packed in 32-pin PLASTIC SOP, 32-pin PLASTIC TSOP (I) (8 x 13.4 mm) and (8 x 20 mm). Features * 131,072 words by 8 bits organization * Fast access time: 70, 85, 100, 120, 150 ns (MAX.) * Low voltage operation (A version: VCC = 3.0 to 5.5 V, B version: VCC = 2.7 to 5.5 V) * Operating ambient temperature: TA = -25 to +85 C * Low VCC data retention: 2.0 V (MIN.) * Output Enable input for easy application * Two Chip Enable inputs: /CE1, CE2 Part number Access time ns (MAX.) PD431000A-xxX 70, 85 PD431000A-AxxX Note2 PD431000A-BxxX Note2 Supply current voltage temperature At operating At standby At data retention V C mA (MAX.) A (MAX.) A (MAX.) Note1 4.5 to 5.5 -25 to +85 70 50 2.5 , 100 3.0 to 5.5 35 Note3 , 100, 120, 150 2.7 to 5.5 30 Note4 70 70 Operating supply Operating ambient 26 Note5 22 Note6 Notes 1. TA 40 C 2. VCC = 4.5 to 5.5 V 3. 70 mA (VCC > 3.6 V) 4. 70 mA (VCC > 3.3 V) 5. 50 A (VCC > 3.6 V) 6. 50 A (VCC > 3.3 V) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. M10430EJBV0DS00 (11th edition) Date Published November 2008 Printed in Japan 1995 PD431000A-X Ordering Information Part number Package Access time ns (MAX.) PD431000AGW-70X 32-pin PLASTIC SOP 70 Operating supply Operating ambient voltage temperature V C 4.5 to 5.5 -25 to +85 Remark - (13.34 mm (525)) PD431000AGZ-70X-KJH 32-pin PLASTIC TSOP (I) PD431000AGZ-85X-KJH (8 x 20) (Normal bent) 85 PD431000AGZ-A10X-KJH 100 3.0 to 5.5 A version PD431000AGZ-B10X-KJH 100 2.7 to 5.5 B version PD431000AGZ-B12X-KJH 120 PD431000AGZ-B15X-KJH 150 2.7 to 5.5 B version 4.5 to 5.5 - PD431000AGU-B10X-9JH 32-pin PLASTIC TSOP (I) 100 PD431000AGU-B12X-9JH (8 x 13.4) (Normal bent) 120 PD431000AGU-B15X-9JH PD431000AGW-70X-A 150 32-pin PLASTIC SOP 70 (13.34 mm (525)) PD431000AGZ-70X-KJH-A 32-pin PLASTIC TSOP (I) PD431000AGZ-85X-KJH-A (8 x 20) (Normal bent) 85 PD431000AGZ-A10X-KJH-A 100 3.0 to 5.5 A version PD431000AGZ-B10X-KJH-A 100 2.7 to 5.5 B version PD431000AGZ-B12X-KJH-A 120 PD431000AGZ-B15X-KJH-A 150 2.7 to 5.5 B version PD431000AGU-B10X-9JH-A 32-pin PLASTIC TSOP (I) 100 PD431000AGU-B12X-9JH-A (8 x 13.4) (Normal bent) 120 PD431000AGU-B15X-9JH-A Remark 2 150 Products with -A at the end of the part number are lead-free products. Data Sheet M10430EJBV0DS PD431000A-X Pin Configurations (Marking Side) /xxx indicates active low signal. 32-pin PLASTIC SOP (13.34 mm (525)) [PD431000AGW-xxX] [PD431000AGW-xxX-A] NC 1 32 VCC A16 2 31 A15 A14 3 30 CE2 A12 4 29 /WE A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 /OE A2 10 23 A10 A1 11 22 /CE1 A0 12 21 I/O8 I/O1 13 20 I/O7 I/O2 14 19 I/O6 I/O3 15 18 I/O5 GND 16 17 I/O4 A0 - A16 : Address inputs I/O1 - I/O8 : Data inputs / outputs /CE1, CE2 : Chip Enable 1, 2 /WE : Write Enable /OE : Output Enable VCC : Power supply GND : Ground NC : No connection Remark Refer to Package Drawings for the 1-pin index mark Data Sheet M10430EJBV0DS 3 PD431000A-X 32-pin PLASTIC TSOP (I) (8x20) (Normal bent) [PD431000AGZ-xxX-KJH] [PD431000AGZ-AxxX-KJH] [PD431000AGZ-BxxX-KJH] [PD431000AGZ-xxX-KJH-A] [PD431000AGZ-AxxX-KJH-A] [PD431000AGZ-BxxX-KJH-A] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A11 A9 A8 A13 /WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A0 - A16 : Address inputs /OE : Output Enable I/O1 - I/O8 : Data inputs / outputs VCC : Power supply /CE1, CE2 : Chip Enable 1, 2 GND : Ground /WE NC : No connection : Write Enable Remark Refer to Package Drawings for the 1-pin index mark. 4 Data Sheet M10430EJBV0DS /OE A10 /CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 A3 PD431000A-X 32-pin PLASTIC TSOP (I) (8x13.4) (Normal bent) [PD431000AGU-BxxX-9JH] [PD431000AGU-BxxX-9JH-A] A11 A9 A8 A13 /WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A0 - A16 : Address inputs I/O1 - I/O8 : Data inputs / outputs /CE1, CE2 : Chip Enable 1, 2 /WE : Write Enable /OE : Output Enable VCC : Power supply GND : Ground NC : No connection /OE A10 /CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 A3 Remark Refer to Package Drawings for the 1-pin index mark. Data Sheet M10430EJBV0DS 5 PD431000A-X Block Diagram VCC GND A0 Address buffer A16 Row decoder I/O1 Memory cell array 1,048,576 bits Input data controller I/O8 Sense amplifier / Switching circuit Column decoder Output data controller Address buffer /CE1 CE2 /OE /WE Truth Table /CE1 CE2 /OE /WE Mode I/O Supply current H x x x Not selected High impedance ISB x L x x L H H H Output disable L H L H Read DOUT L H x L Write DIN Remark x : VIH or VIL 6 Data Sheet M10430EJBV0DS ICCA PD431000A-X Electrical Specifications Absolute Maximum Ratings Parameter Symbol Supply voltage Condition Rating VCC -0.5 -0.5 Note Note Unit to +7.0 V to VCC + 0.5 V Input / Output voltage VT Operating ambient temperature TA -25 to +85 C Storage temperature Tstg -55 to +125 C Note -3.0 V (MIN.) (Pulse width: 30 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol Condition PD431000A-xxX PD431000A-AxxX PD431000A-BxxX MIN. MAX. MIN. MAX. MIN. MAX. Unit Supply voltage VCC 4.5 5.5 3.0 5.5 2.7 5.5 V High level input voltage VIH 2.4 VCC+0.5 2.4 VCC+0.5 2.4 VCC+0.5 V +0.5 V +85 C Low level input voltage VIL Operating ambient temperature TA -0.3 Note -25 +0.6 +85 -0.3 Note -25 +0.5 -0.3 +85 Note -25 Note -3.0 V (MIN.) (Pulse width: 30 ns) Capacitance (TA = 25 C, f = 1 MHz) Parameter Symbol Test conditions MIN. TYP. MAX. Unit Input capacitance CIN VIN = 0 V 6 pF Input / Output capacitance CI/O VI/O = 0 V 10 pF Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These parameters are not 100% tested. Data Sheet M10430EJBV0DS 7 PD431000A-X DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) Parameter Symbol Input leakage PD431000A-xxX Test condition PD431000A-AxxX PD431000A-BxxX MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. Unit ILI VIN = 0 V to VCC -1.0 +1.0 -1.0 +1.0 -1.0 +1.0 A ILO VI/O = 0 V to VCC, -1.0 +1.0 -1.0 +1.0 -1.0 +1.0 A mA current I/O leakage current /CE1 = VIH or CE2 = VIL or /WE = VIL or /OE = VIH Operating ICCA1 supply current ICCA2 ICCA3 /CE1 = VIL, CE2 = VIH, II/O = 0 mA VCC 3.6 V Minimum cycle time VCC 3.3 V 40 70 40 70 40 70 - - 15 35 - - - - 15 30 15 15 15 /CE1 = VIL, CE2 = VIH, II/O = 0 mA, VCC 3.6 V - 10 - Cycle time = VCC 3.3 V - - 8 10 10 10 /CE1 0.2 V, CE2 VCC - 0.2 V, Cycle time = 1 s, II/O = 0 mA, Standby ISB VIL 0.2 V, VCC 3.6 V - 8 - VIH VCC - 0.2 V VCC 3.3 V - - 7 3 3 3 VCC 3.6 V - 2 - VCC 3.3 V - - 2 /CE1 = VIH or CE2 = VIL supply current ISB1 /CE1 VCC - 0.2 V, CE2 VCC - 0.2 V ISB2 High level VOH output voltage Low level 50 - 50 - 50 VCC 3.6 V - - 0.5 26 - - VCC 3.3 V - - - - 0.5 22 1 50 - 50 - 50 VCC 3.6 V - - 0.5 26 - - VCC 3.3 V - - - - 0.5 22 CE2 0.2 V IOH = -1.0 mA, VCC 4.5 V IOH = -0.5 mA VOL output voltage 1 2.4 2.4 2.4 - 2.4 2.4 IOL = 2.1 mA, VCC 4.5 V IOL = 1.0 mA 0.4 0.4 - 0.4 0.4 VI/O : Input / Output voltage 2. These DC characteristics are in common regardless product classification. 8 Data Sheet M10430EJBV0DS A V 0.4 Remarks 1. VIN : Input voltage mA V PD431000A-X AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions [PD431000A-70X, PD431000A-85X] Input Waveform (Rise and Fall Time 5 ns) 2.4 V 1.5 V Test points 1.5 V 1.5 V Test points 1.5 V 0.6 V Output Waveform Output Load AC characteristics should be measured with the following output load conditions. Figure 1 Figure 2 (tAA, tCO1, tCO2, tOE, tOH) (tLZ1, tLZ2, tOLZ, tHZ1, tHZ2, tOHZ, tWHZ, tOW ) +5 V +5 V 1.8 k 1.8 k I/O (Output) I/O (Output) 990 990 100 pF CL 5 pF CL Remark CL includes capacitance of the probe and jig, and stray capacitance. [PD431000A-A10X, PD431000A-B10X, PD431000A-B12X, PD431000A-B15X] Input Waveform (Rise and Fall Time 5 ns) 2.4 V 1.5 V Test points 1.5 V 1.5 V Test points 1.5 V 0.5 V Output Waveform Output Load AC characteristics should be measured with the following output load conditions. Part number Output load condition tAA, tCO1, tCO2, tOE, tOH tLZ1, tLZ2, tOLZ, tHZ1, tHZ2, tOHZ, tWHZ, tOW PD431000A-A10X, PD431000A-B10X, PD431000A-B12X 1TTL + 50 pF 1TTL + 5 pF PD431000A-B15X 1TTL + 100 pF 1TTL + 5 pF Data Sheet M10430EJBV0DS 9 PD431000A-X Read Cycle (1/2) Parameter VCC 4.5 V Symbol PD431000A-70X VCC 3.0 V PD431000A-85X Unit Condition PD431000A-A10X PD431000A-AxxX PD431000A-BxxX MIN. MAX. 70 MIN. MAX. 85 MIN. MAX. Read cycle time tRC 100 ns Address access time tAA 70 85 100 ns /CE1 access time tCO1 70 85 100 ns CE2 access time tCO2 70 85 100 ns /OE to output valid tOE 35 45 50 ns Output hold from address change tOH 10 10 10 ns /CE1 to output in low impedance tLZ1 10 10 10 ns CE2 to output in low impedance tLZ2 10 10 10 ns /OE to output in low impedance tOLZ 5 5 5 ns /CE1 to output in high impedance tHZ1 25 30 35 ns CE2 to output in high impedance tHZ2 25 30 35 ns /OE to output in high impedance tOHZ 25 30 35 ns Note Note See the output load. Remark These AC characteristics are in common regardless of package types. Read Cycle (2/2) Parameter VCC 2.7 V Symbol Unit Condition PD431000A-B10X PD431000A-B12X PD431000A-B15X MIN. MAX. 100 MIN. MAX. 120 MIN. MAX. Read cycle time tRC 150 Address access time tAA 100 120 150 ns /CE1 access time tCO1 100 120 150 ns CE2 access time tCO2 100 120 150 ns /OE to output valid tOE 50 60 70 ns Output hold from address change tOH 10 10 10 ns /CE1 to output in low impedance tLZ1 10 10 10 ns CE2 to output in low impedance tLZ2 10 10 10 ns /OE to output in low impedance tOLZ 5 5 5 ns /CE1 to output in high impedance tHZ1 35 40 50 ns CE2 to output in high impedance tHZ2 35 40 50 ns /OE to output in high impedance tOHZ 35 40 50 ns Note See the output load. Remark These AC characteristics are in common regardless of package types. 10 Data Sheet M10430EJBV0DS ns Note PD431000A-X Read Cycle Timing Chart tRC Address (Input) tAA tOH /CE1 (Input) tHZ1 tCO1 tLZ1 CE2 (Input) tCO2 tHZ2 tLZ2 /OE (Input) tOE tOHZ tOLZ I/O (Output) High impedance Data out Remark In read cycle, /WE should be fixed to high level. Data Sheet M10430EJBV0DS 11 PD431000A-X Write Cycle (1/2) Parameter VCC 4.5 V Symbol PD431000A-70X VCC 3.0 V PD431000A-85X Unit Condition PD431000A-A10X PD431000A-AxxX PD431000A-BxxX MIN. MAX. MIN. MAX. MIN. MAX. Write cycle time tWC 70 85 100 ns /CE1 to end of write tCW1 55 70 80 ns CE2 to end of write tCW2 55 70 80 ns Address valid to end of write tAW 55 70 80 ns Address setup time tAS 0 0 0 ns Write pulse width tWP 50 60 60 ns Write recovery time tWR 5 5 0 ns Data valid to end of write tDW 35 35 60 ns Data hold time tDH 0 0 0 ns /WE to output in high impedance tWHZ Output active from end of write tOW 25 5 30 5 35 5 ns Note ns Note See the output load. Remark These AC characteristics are in common regardless of package types. Write Cycle (2/2) Parameter VCC 2.7 Symbol Unit Condition PD431000A-B10X PD431000A-B12X PD431000A-B15X MIN. MAX. MIN. MAX. MIN. MAX. Write cycle time tWC 100 120 150 ns /CE1 to end of write tCW1 80 100 120 ns CE2 to end of write tCW2 80 100 120 ns Address valid to end of write tAW 80 100 120 ns Address setup time tAS 0 0 0 ns Write pulse width tWP 60 85 100 ns Write recovery time tWR 0 0 0 ns Data valid to end of write tDW 60 60 80 ns Data hold time tDH 0 0 0 ns /WE to output in high impedance tWHZ Output active from end of write tOW 35 5 40 5 Note See the output load. Remark These AC characteristics are in common regardless of package types. 12 Data Sheet M10430EJBV0DS 50 5 ns ns Note PD431000A-X Write Cycle Timing Chart 1 (/WE Controlled) tWC Address (Input) tCW1 /CE1 (Input) tCW2 CE2 (Input) tAW tAS tWP tWR /WE (Input) tOW tWHZ I/O (Input / Output) Indefinite data out tDW High impedance tDH Data in High impedance Indefinite data out Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remarks 1. Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2. 2. If /CE1 changes to low level at the same time or after the change of /WE to low level, or if CE2 changes to high level at the same time or after the change of /WE to low level, the I/O pins will remain high impedance state. 3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance. Data Sheet M10430EJBV0DS 13 PD431000A-X Write Cycle Timing Chart 2 (/CE1 Controlled) tWC Address (Input) tAS tCW1 /CE1 (Input) tCW2 CE2 (Input) tAW tWP tWR /WE (Input) tDW tDH High impedance High Data in I/O (Input) impedance Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remark Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2. Write Cycle Timing Chart 3 (CE2 Controlled) tWC Address (Input) tCW1 /CE1 (Input) tAS tCW2 CE2 (Input) tAW tWP tWR /WE (Input) tDW High impedance I/O (Input) Data in tDH High impedance Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remark 14 Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2. Data Sheet M10430EJBV0DS PD431000A-X Low VCC Data Retention Characteristics (TA = -25 to +85 C) Parameter Symbol PD431000A-xxX Test Condition Unit PD431000A-AxxX PD431000A-BxxX MIN. Data retention supply voltage Data retention supply current MAX. VCCDR1 /CE1 VCC - 0.2 V, CE2 VCC - 0.2 V 2.0 5.5 VCCDR2 CE2 0.2 V 2.0 5.5 ICCDR1 VCC = 3.0 V, /CE1 VCC - 0.2 V, CE2 VCC - 0.2 V ICCDR2 Chip deselection TYP. 0.5 VCC = 3.0 V, CE2 0.2 V 0.5 20 Note 20 Note V A tCDR 0 ns tR 5 ms to data retention mode Operation recovery time Note 2.5 A (TA 40 C) Data Sheet M10430EJBV0DS 15 PD431000A-X Data Retention Timing Chart (1) /CE1 Controlled tCDR Data retention mode tR VCC 4.5 V Note /CE1 VIH (MIN.) VCCDR (MIN.) /CE1 VCC - 0.2 V VIL (MAX.) GND Note A version : 3.0 V, B version : 2.7 V Remark On the data retention mode by controlling /CE1, the input level of CE2 must be CE2 VCC - 0.2 V or CE2 0.2 V. The other pins (Address, I/O, /WE, /OE) can be in high impedance state. (2) CE2 Controlled tCDR Data retention mode tR VCC 4.5 V Note VIH (MIN.) VCCDR (MIN.) CE2 VIL (MAX.) CE2 0.2 V GND Note A version : 3.0 V, B version : 2.7 V Remark On the data retention mode by controlling CE2, the other pins (/CE1, Address, I/O, /WE, /OE) can be in high impedance state. 16 Data Sheet M10430EJBV0DS PD431000A-X Package Drawings 32-PIN PLASTIC SOP (13.34 mm (525)) 32 17 detail of lead end P 1 16 A H F I G J S N B S C D M L K M E NOTE Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition. ITEM A MILLIMETERS 20.61 MAX. B 0.78 MAX. C 1.27 (T.P.) D 0.40+0.10 -0.05 E 0.150.05 F G H 2.95 MAX. 2.7 14.10.3 I 11.3 J 1.40.2 K 0.20 +0.10 -0.05 L M N P 0.80.2 0.12 0.10 3 +7 -3 P32GW-50-525A-1 Data Sheet M10430EJBV0DS 17 PD431000A-X 32-PIN PLASTIC TSOP(I) (8x20) detail of lead end 1 32 F G R Q 16 L 17 S E P I J A S B C D K N M M S NOTES ITEM MILLIMETERS 1. Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. A 8.00.1 B 0.45 MAX. 2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.) C 0.5 (T.P.) D 0.220.05 E 0.10.05 F 1.2 MAX. G 0.970.08 I 18.40.1 J 0.80.2 K 0.1450.05 L 0.5 M 0.10 N 0.10 P 20.00.2 Q 3+5 -3 R S 0.25 0.600.15 S32GZ-50-KJH1-2 18 Data Sheet M10430EJBV0DS PD431000A-X 32-PIN PLASTIC TSOP(I) (8x13.4) detail of lead end 1 32 S T R L 16 17 U Q P I J A G S H K B C N S NOTES D M M ITEM 1. Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.) MILLIMETERS A 8.00.1 B 0.45 MAX. C D 0.5 (T.P.) 0.220.05 G 1.00.05 H 12.40.2 I 11.80.1 J 0.80.2 K 0.145 +0.025 -0.015 L 0.5 M 0.08 N 0.08 P 13.40.2 Q 0.10.05 R 3 +5 -3 S 1.2 MAX. T 0.25 U 0.60.15 P32GU-50-9JH-2 Data Sheet M10430EJBV0DS 19 PD431000A-X Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the PD431000A-X. Types of Surface Mount Device PD431000AGW-xxX : 32-pin PLASTIC SOP (13.34 mm (525)) PD431000AGZ-xxX-KJH : 32-pin PLASTIC TSOP (I) (8x20) (Normal bent) PD431000AGZ-AxxX-KJH : 32-pin PLASTIC TSOP (I) (8x20) (Normal bent) PD431000AGZ-BxxX-KJH : 32-pin PLASTIC TSOP (I) (8x20) (Normal bent) PD431000AGU-BxxX-9JH : 32-pin PLASTIC TSOP (I) (8x13.4) (Normal bent) PD431000AGW-xxX-A : 32-pin PLASTIC SOP (13.34 mm (525)) PD431000AGZ-xxX-KJH-A : 32-pin PLASTIC TSOP (I) (8x20) (Normal bent) PD431000AGZ-AxxX-KJH-A : 32-pin PLASTIC TSOP (I) (8x20) (Normal bent) PD431000AGZ-BxxX-KJH-A : 32-pin PLASTIC TSOP (I) (8x20) (Normal bent) PD431000AGU-BxxX-9JH-A : 32-pin PLASTIC TSOP (I) (8x13.4) (Normal bent) 20 Data Sheet M10430EJBV0DS PD431000A-X Revision History Edition/ Date 11th edition/ Page Type of This Previous edition edition through through Description revision Modification Ordering Information revised. Nov. 2008 Data Sheet M10430EJBV0DS 21 PD431000A-X [MEMO] 22 Data Sheet M10430EJBV0DS PD431000A-X NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Data Sheet M10430EJBV0DS 23 PD431000A-X * The information in this document is current as of November, 2008. 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