May 2002 AS7C1025A AS7C31025A (R) 5V/3.3V 128K X 8 CMOS SRAM (Revolutionary pinout) Features * * * * * AS7C1025A (5V version) AS7C31025A (3.3V version) Industrial and commercial temperatures Organization: 131,072 x 8 bits High speed - 10/12/15/20 ns address access time - 5, 6, 7, 8 ns output enable access time * Low power consumption: ACTIVE - 853 mW (AS7C1025A) / max @ 10 ns (5V) - 522 mW (AS7C31025A) / max @ 10 ns (3.3V) * Low power consumption: STANDBY - 55 mW (AS7C1025A) / max CMOS (5V) - 36 mW (AS7C31025A) / max CMOS (3.3V) * * * * * Latest 6T 0.25u CMOS technology Easy memory expansion with CE, OE inputs Center power and ground TTL/LVTTL-compatible, three-state I/O JEDEC-standard packages - 32-pin, 300 mil SOJ - 32-pin, 400 mil SOJ - 32-pin, TSOP 2 * ESD protection 2000 volts * Latch-up current 200 mA Pin arrangement Logic block diagram VCC GND I/O7 A0 A1 A2 A3 CE I/O0 I/O1 VCC GND I/O2 I/O3 WE A4 A5 A6 A7 I/O0 Control circuit WE OE CE A9 A10 A11 A12 A13 A14 A15 A16 Column decoder 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE I/O7 I/O6 GND VCC I/O5 I/O4 A12 A11 A10 A9 A8 32-pin SOJ (300 mil) 32-pin SOJ (400 mil) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AS7C1025A AS7C31025A 512x256x8 Array (1,048,576) Sense amp A0 A1 A2 A3 A4 A5 A6 A7 A8 Row decoder Input buffer 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AS7C1025A AS7C31025A 32-pin TSOP 2 A0 A1 A2 A3 CE I/O0 I/O1 VCC GND I/O2 I/O3 WE A4 A5 A6 A7 A16 A15 A14 A13 OE I/O7 I/O6 GND VCC I/O5 I/O4 A12 A11 A10 A9 A8 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Selection guide -10 -12 -15 -20 Unit Maximum address access time 10 12 15 20 ns Maximum output enable access time 5 6 7 8 ns AS7C1025A 155 150 145 140 mA AS7C31025A 145 140 135 130 mA AS7C1025A 10 10 10 10 mA AS7C31025A 5 5 5 5 mA Maximum operating current Maximum CMOS standby current 9/26/02; v.0.9.8 Alliance Semiconductor P. 1 of 8 Copyright (c) Alliance Semiconductor. All rights reserved. AS7C1025A AS7C31025A (R) Functional description The AS7C1025A and AS7C31025A are high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as 131,072 x 8 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal for high-performance applications. The chip enable input CE permits easy memory and expansion with multiple-bank memory systems. When CE is high the devices enter standby mode. The standard AS7C1025A is guaranteed not to exceed 55 mW power consumption in standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled withRXWSXWHQDEOH OE RUZULWHHQDEOH (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chips drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply (AS7C1025A) or 3.3V supply (AS7C31025A). The AS7C1025A and AS7C31025A are packaged in common industry standard packages. Absolute maximum ratings Parameter Device Symbol Min Max Unit AS7C1025A Vt1 -0.50 +7.0 V AS7C31025A Vt1 -0.50 +5.0 V Voltage on any pin relative to GND Vt2 -0.50 VCC + 0.5 V Power dissipation PD - 1.0 Voltage on VCC relative to GND Storage temperature (plastic) Tstg -65 W +150 o C Ambient temperature with VCC applied Tbias -55 +125 oC DC current into outputs (low) IOUT - 20 mA NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE WE OE Data Mode H X X High Z Standby (ISB, ISB1) L H H High Z Output disable (ICC) L H L DOUT Read (ICC) L L X DIN Write (ICC) Key: X = Don't Care, L = Low, H = High 9/26/02; v.0.9.8 Alliance Semiconductor P. 2 of 8 AS7C1025A AS7C31025A (R) Recommended operating conditions Parameter Supply voltage Input voltage Device Symbol Min Nominal Max Unit AS7C1025A VCC 4.5 5.0 5.5 V AS7C31025A VCC 3.0 3.3 3.6 V AS7C1025A VIH 2.2 - VCC + 0.5 V AS7C31025A VIH 2.0 - VCC + 0.5 V -0.5 - 0.8 V Both Ambient operating temperature VIL commercial TA 0 - 70 oC industrial TA -40 - 85 o C VIL min. = -3.0V for pulse width less than tRC/2. DC operating characteristics (over the operating range) -10 Parameter Sym Test conditions Device -12 Min Max Min -15 -20 Max Min Max Min Max Unit Input leakage current | ILI | VCC = Max, VIN = GND to VCC Both - 1 - 1 - 1 - 1 A Output leakage current | ILO | VCC = Max, CE = VIH, Vout = GND to VCC Both - 1 - 1 - 1 - 1 A AS7C1025A - 155 - 150 - 145 - 140 AS7C31025A - 145 - 140 - 135 - 130 AS7C1025A - 30 - 25 - 20 - 20 AS7C31025A - 30 - 25 - 20 - 20 AS7C1025A - AS7C31025A - 10 5 - .04 Operating power supply current Standby power supply current Output voltage ICC CE = VIL, f = fMax, IOUT = 0 mA ISB CE = VIH, f = fMax, fOUT = 0 ISB1 CE VCC-0.2V, VIN 0.2V or VIN VCC -0.2V, f = 0, fOUT = 0 VOL IOL = 8 mA, VCC = Min VOH IOH = -4 mA, VCC = Min Both 2.4 10 5 10 5 mA mA 10 5 mA - 0.4 - 0.4 - 0.4 V 2.4 - 2.4 - 2.4 - V Capacitance (f = 1 MHz, Ta = 25 oC, VCC = NOMINAL) Parameter Symbol Signals Test conditions Max Unit Input capacitance CIN A, CE, WE, OE VIN = 0V 5 pF I/O capacitance CI/O I/O VIN = VOUT = 0V 7 pF 9/26/02; v.0.9.8 Alliance Semiconductor P. 3 of 8 AS7C1025A AS7C31025A (R) Read cycle (over the operating range) -10 Parameter Symbol -12 Min Max Min -15 -20 Max Min Max Min Max Unit Notes Read cycle time tRC 10 - 12 - 15 - 20 - ns Address access time tAA - 10 - 12 - 15 - 20 ns 3 Chip enable (CE) access time tACE - 10 - 12 - 15 - 20 ns 3 Output enable (OE) access time tOE - 5 - 6 - 7 - 8 ns Output hold from address change tOH 2 - 3 - 3 - 3 - ns 5 CE/RZWo output in low Z tCLZ 0 - 0 - 0 - 0 - ns 4, 5 CE Low to output in high Z tCHZ - 3 - 3 - 4 - 5 ns 4, 5 OE Low to output in low Z tOLZ 0 - 0 - 0 - 0 - ns 4, 5 OE High to output in high Z tOHZ - 3 - 3 - 4 - 5 ns 4, 5 Power up time tPU 0 - 0 - 0 - 0 - ns 4, 5 Power down time tPD - 10 - 12 - 15 - 20 ns 4, 5 Key to switching waveforms Rising input Falling input Undefined/don't care Read waveform 1 (address controlled) tRC Address tAA tOH DOUT Data valid Read waveform 2 (CE and OE controlled) tRC1 CE tOE OE tACE DOUT Data valid tCLZ Supply current 9/26/02; v.0.9.8 tOHZ tCHZ tOLZ tPU tPD 50% Alliance Semiconductor ICC ISB 50% P. 4 of 8 AS7C1025A AS7C31025A (R) Write cycle (over the operating range) -10 Parameter -12 Symbol Min Max Min Write cycle time tWC 10 - Chip enable (CE) to write end tCW 8 Address setup to write end tAW Address setup time -15 -20 Max Min Max Min Max Unit Notes 12 - 15 - 20 - ns - 10 - 12 - 12 - ns 8 - 9 - 10 - 12 - ns tAS 0 - 0 - 0 - 0 - ns Write pulse width tWP 7 - 8 - 9 - 12 - ns Write recovery time tWR 0 - 0 - 0 - 0 - ns Address hold from end of write tAH 0 - 0 - 0 - 0 - ns Data valid to write end tDW 5 - 6 - 8 - 10 - ns Data hold time tDH 0 - 0 - 0 - 0 - ns 4, 5 Write enable to output in high Z tWZ - 6 - 6 - 6 - 8 ns 4, 5 Output active from write end tOW 1 - 1 - 1 - 2 - ns 4, 5 Write waveform 1 (WE controlled) tAW tWC tWR tAH Address tWP WE tAS tDW DIN tDH Data valid tWZ tOW DOUT 9/26/02; v.0.9.8 Alliance Semiconductor P. 5 of 8 AS7C1025A AS7C31025A (R) Write waveform 2 (CE controlled) tWC tAW tAH tWR Address tAS tCW CE tWP WE tWZ tDW DIN tDH Data valid DOUT AC test conditions - - - - Output load: see Figure B or Figure C. Input pulse level: GND to 3.0V. See Figure A. Input rise and fall times: 2 ns. See Figure A. Input and output timing reference levels: 1.5V. Thevenin equivalent: 168 DOUT +1.728V (5V and 3.3V) +5V +3.3V 480 +3.0V GND 90% 10% 90% 2 ns 10% Figure A: Input pulse DOUT 255 C(14) GND Figure B: 5V Output load 320 DOUT 255 C(14) GND Figure C: 3.3V Output load Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions, Figures A, B, and C. tCLZ and tCHZ are specified with CL = 5pF, as in Figure C. Transition is measured 500mV from steady-state voltage. This parameter is guaranteed, but not 100% tested. WE is High for read cycle. CE and OE are Low for read cycle. Address valid prior to or coincident with CE transition Low. All read cycle timings are referenced from the last valid address to the first transitioning address. CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle. All write cycle timings are referenced from the last valid address to the first transitioning address. NA. C=30pF, except all high Z and low Z parameters, where C=5pF. 9/26/02; v.0.9.8 Alliance Semiconductor P. 6 of 8 AS7C1025A AS7C31025A (R) Package dimensions 32-pin TSOP 2 (mm) 32-pin TSOP 2 N Symbol Min Max A - 1.2 A1 0.05 0.15 b 0.3 0.52 C 0.12 0.21 D 20.82 21.08 E1 10.03 10.29 E 11.56 11.96 N/2+1 E E1 1 N/2 D e Seating plane A 1.27 BSC L ZD 0.40 ZD 0.95 REF. c 0.60 0 5 A1 b L c 32-pin SOJ 300 mil 32-pin SOJ 300 mil/400 mil D e E1 E2 B Pin 1 A A1 c b A2 Seating Plane 32-pin SOJ 400 mil Symbol Min Max Min Max A - 0.145 - 0.145 A1 0.025 - 0.025 - A2 0.086 0.105 0.086 0.115 B 0.026 0.032 0.026 0.032 b 0.014 0.020 0.015 0.020 c 0.006 0.013 0.007 0.013 D 0.820 0.830 0.820 0.830 E 0.250 0.275 0.360 0.380 E1 0.292 0.305 0.395 0.405 E2 0.330 0.340 0.435 0.445 e 0.050 BSC 0.050 BSC E 9/26/02; v.0.9.8 Alliance Semiconductor P. 7 of 8 AS7C1025A AS7C31025A (R) Ordering codes Package \ Access time Volt. Temperature Commercial 5V Industrial TSOP 2 3.3V 5V 3.3V 3.3V 20 ns AS7C1025A-10HFC AS7C1025A-12HFC AS7C1025A-15HFC AS7C1025A-20HFC AS7C1025A-10TI AS7C1025A-12HFI AS7C1025A-15HFI AS7C1025A-20HFI AS7C31025A-12HFC AS7C31025A-15HFC AS7C31025A-20HFC Industrial AS7C31025A-10HFI AS7C31025A-12HFI AS7C31025A-15HFI AS7C31025A-20HFI Commercial AS7C1025A-10TJC AS7C1025A-12TJC AS7C1025A-15TJC AS7C1025A-20TJC AS7C1025A-10TJI AS7C1025A-12TJI AS7C1025A-15TJI AS7C1025A-20TJI Commercial AS7C31025A-10TJC AS7C31025A-12TJC AS7C31025A-15TJC AS7C31025A-20TJC Industrial AS7C31025A-10TJI AS7C31025A-12TJI AS7C31025A-15TJI AS7C31025A-20TJI AS7C1025A-10JC AS7C1025A-12JC AS7C1025A-15JC AS7C1025A-20JC Industrial 400-mil SOJ 15 ns AS7C31025A-10HFC Commercial 5V 12 ns Commercial Industrial 300-mil SOJ 10 ns AS7C1025A-10JI AS7C1025A-12JI AS7C1025A-15JI AS7C1025A-20JI Commercial AS7C31025A-10JC AS7C31025A-12JC AS7C31025A-15JC AS7C31025A-20JC Industrial AS7C31025A-10JI AS7C31025A-12JI AS7C31025A-15JI AS7C31025A-20JI Part numbering system AS7C X SRAM prefix Voltage: Blank=5V CMOS 3=3.3V CMOS 9/26/02; v.0.9.8 1025 Device number -XX X X Access time Package: HF = TSOP 2 / 32 Pin TJ = SOJ 300 mil J = SOJ 400 mil Temperature range C = Commercial, 0C to 70C I = Industrial, -40C to 85C Alliance Semiconductor P. 8 of 8 (c) Copyright A lliance Sem iconductor Corporation. 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