May 2002
Copyright © Alliance Semiconductor. All rights reserved.
®
AS7C1025A
AS7C31025A
5V/3.3V 128K X 8 CMOS SRAM (Revolutionary pinout)
9/26/02; v.0.9.8 Alliance Semiconductor P. 1 of 8
Features
• AS7C1025A (5V version)
• AS7C31025A (3.3V version)
• Industrial and commercial temperatures
• Organization: 131,072 x 8 bits
• High speed
- 10/12/15/20 ns address access time
- 5, 6, 7, 8 ns output enable access time
• Low power consumption: ACTIVE
- 853 mW (AS7C1025A) / max @ 10 ns (5V)
- 522 mW (AS7C31025A) / max @ 10 ns (3.3V)
• Low power consumption: STANDBY
- 55 mW (AS7C1025A) / max CMOS (5V)
- 36 mW (AS7C31025A) / max CMOS (3.3V)
• Latest 6T 0.25u CMOS technology
• Easy memory expansion with CE, OE inputs
• Center power and ground
• TTL/LVTTL-compatible, three-state I/O
• JEDEC-standard packages
- 32-pin, 300 mil SOJ
- 32-pin, 400 mil SOJ
- 32-pin, TSOP 2
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Logic block diagram
512
×
256
×
8
Array
(1,048,576)
Sense amp
Input buffer
A10
A11
A12
A13
A14
A15
A16
I/O0
I/O7
OE
CE
WE
Column decoder
Ro w deco der
Control
circuit
A9
A0
A1
A2
A3
A4
A5
A6
A7
V
CC
GND
A8
Pin arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A15
A14
A13
OE
I/O7
I/O6
GND
VCC
I/O5
I/O4
A12
A11
A10
A9
A8
A0
A1
A2
A3
CE
I/O0
I/O1
VCC
GND
I/O2
I/O3
WE
A4
A5
A6
A7
AS7C1025A
AS7C31025A
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A0
A1
A2
A3
CE
I/O0
I/O1
VCC
GND
I/O2
I/O3
WE
A16
A15
A14
A13
OE
I/O7
I/O6
GND
VCC
I/O5
I/O4
A9
A8
A4
A5
A6
A7
A12
A11
A10
32-pin TSOP 2
AS7C1025A
AS7C31025A
Selection guide
-10 -12 -15 -20 Unit
Maximum address access time 10 12 15 20 ns
Maximum output enable access time 5 6 7 8 ns
Maximum
operating current AS7C1025A 155 150 145 140 mA
AS7C31025A 145 140 135 130 mA
Maximum CMOS
standby current AS7C1025A 10 10 10 10 mA
AS7C31025A 5 5 5 5 mA
AS7C1025A
AS7C31025A
9/26/02; v.0.9.8 Alliance Semiconductor P. 2 of 8
®
Functional description
The AS7C1025A and AS7C31025A are high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as
131,072 x 8 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal for
high-performance applications. The chip enable input CE permits easy memory and expansion with multiple-bank memory systems.
When
CE
is high the devices enter standb y mode. The standard AS7C1025A is guaranteed not to exceed 55 mW pow er consumption in standby
mode.
A write cycle is accomplished by asserting write enable (
WE
) and ch ip enable (
CE
). Data on the input pins I/O0-I/O7 is written on the r isin g
edge of
WE
(write cycle 1) or
CE
(write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been
disabled withRXWSXWHQDEOH
OE
RUZULWHHQDEOH (
WE
).
A read cycle is accomplished by asserting output enable (
OE
) and chip enable (
CE
), with write enable (
WE
) high. The chips drive I/O pins
with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output
drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply (AS7C1025A) or 3.3V supply (AS7C31025A). The
AS7C1025A and AS7C31025A are packaged in common industry standard packages.
NOTE: Stresses greater than those listed unde r Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional oper-
ation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Key: X = Don’t Care, L = Low, H = High
Absolute maximum ratings
Parameter Device Symbol Min Max Unit
Voltage on VCC relativ e to GND AS7C1025A Vt1 –0.50 +7.0 V
AS7C31025A Vt1 –0.50 +5.0 V
Voltage on any pin rela tive to GND Vt2 –0.50 VCC + 0.5 V
Power dissipation PD–1.0W
Storage temperature (plastic) Tstg –65 +150 oC
Ambient temperature with VCC applied Tbias –55 +125 oC
DC cur rent int o outpu t s (l ow) IOUT –20mA
Truth table
CE WE OE
Data Mode
H X X High Z Standby (ISB, ISB1)
L H H High Z Output disable (ICC)
LHL D
OUT Read (ICC)
LLX D
IN Write (ICC)
AS7C1025A
AS7C31025A
9/26/02; v.0.9.8 Alliance Semiconductor P. 3 of 8
®
†VIL min. = –3.0V for pulse width less than tRC/2.
Recommended operating conditions
Parameter Device Symbol Min Nominal Max Unit
Supply voltage AS7C1025A VCC 4.5 5.0 5.5 V
AS7C31025A VCC 3.0 3.3 3.6 V
Input voltage AS7C1025A VIH 2.2 – VCC + 0.5 V
AS7C31025A VIH 2.0 – VCC + 0.5 V
Both VIL†–0.5 – 0.8 V
Ambient operating temperature commercial TA0–70
oC
industrial TA–40 – 85 oC
DC operating characteristics (over the operating range)
Parameter Sym Test conditions Device
-10 -12 -15 -20
UnitMin Max Min Max Min Max Min Max
Input
leakage
current | ILI | VCC = Max, VIN = GND to VCC Both – 1 – 1 – 1 – 1 µA
Output
leakage
current | ILO | VCC = Max, CE = VIH, Vout = GND
to VCC Both – 1 – 1 – 1 – 1 µA
Operating
power
supply
current
ICC CE = VIL, f = fMax, IOUT = 0 mA
AS7C1025A – 155 – 150 – 145 – 140
mA
AS7C31025A – 145 – 140 – 135 – 130
Standby
power
supply
current
ISB CE = VIH, f = fMax, fOUT = 0 AS7C1025A – 30 – 25 – 20 – 20 mA
AS7C31025A – 30 – 25 – 20 – 20
ISB1 CE ≥ VCC–0.2V, VIN ≤ 0.2V or VIN
≥ VCC –0.2V, f = 0, fOUT = 0 AS7C1025A – 10 10 10 10 mA
AS7C31025A – 5555
Output
voltage VOL IOL = 8 mA, VCC = Min Both – .04 – 0.4 – 0.4 – 0.4 V
VOH IOH = –4 mA, VCC = Min 2.4 2.4 – 2.4 – 2.4 – V
Capacitance (f = 1 MHz, Ta = 25 oC, VCC = NOMINAL)
Parameter Symbol Signals Test conditions Max Unit
Input capacitance CIN A, CE, WE, OE VIN = 0V 5 pF
I/O capacitance CI/O I/O VIN = VOUT = 0V 7 pF
AS7C1025A
AS7C31025A
9/26/02; v.0.9.8 Alliance Semiconductor P. 4 of 8
®
Key to switching waveforms
Read waveform 1 (address controlled)
Read waveform 2 (CE and OE controlled)
Read cycle (over the operating range)
Parameter Symbol
-10 -12 -15 -20
Unit NotesMin Max Min Max Min Max Min Max
Read cycle time tRC 10 – 12 – 15 – 20 – ns
Address access time tAA – 10 – 12 – 15 – 20 ns 3
Chip enable (CE) access time tACE – 10 – 12 – 15 – 20 ns 3
Output enable (OE) access time tOE –5–6–7– 8 ns
Output hold from address change tOH 2 – 3 – 3 – 3 – ns 5
CE/RZWo output in low Z tCLZ 0 – 0 – 0 – 0 – ns 4, 5
CE Lo w to output in high Z tCHZ – 3 – 3 – 4 – 5 ns 4, 5
OE Low to output in low Z tOLZ 0 – 0 – 0 – 0 – ns 4, 5
OE High to output in high Z tOHZ – 3 – 3 – 4 – 5 ns 4, 5
Power up time tPU 0 – 0 – 0 – 0 – ns 4, 5
Power down time tPD – 10 – 12 – 15 – 20 ns 4, 5
Undefined/don’t careFalling inputRising input
Address
D
OUT
Data valid
t
OH
t
AA
t
RC
current
Supply
OE
D
OUT
t
OE
t
OLZ
t
ACE
t
CHZ
t
CLZ
t
PU
t
PD
I
CC
I
SB
50% 50%
Data valid
t
RC1
CE
t
OHZ
AS7C1025A
AS7C31025A
9/26/02; v.0.9.8 Alliance Semiconductor P. 5 of 8
®
Write waveform 1 (WE controlled)
Write cycle (over the operating range)
Parameter Symbol
-10 -12 -15 -20
Unit NotesMin Max Min Max Min Max Min Max
Write cycle time tWC 10 – 12 – 15 – 20 – ns
Chip enable (CE) to write end tCW 8 – 10 – 12 – 12 – ns
Address setup to write end tAW 8–9–10–12– ns
Address setup time tAS 0–0–0–0 – ns
Write pulse width tWP 7–8–9–12– ns
Write recovery time tWR 0–0–0–0– ns
Address hold from end of write tAH 0–0–0–0 – ns
Data v alid to write end tDW 5–6–8–10– ns
Data hold time tDH 0 – 0 – 0 – 0 – ns 4, 5
Write enab le to output in high Z tWZ – 6 – 6 – 6 – 8 ns 4, 5
Output activ e from write end tOW 1 – 1 – 1 – 2 – ns 4, 5
t
AW
t
AH
t
WC
Address
WE
D
OUT
t
DH
t
OW
t
DW
t
WZ
t
WP
t
AS
Data valid
D
IN
t
WR
AS7C1025A
AS7C31025A
9/26/02; v.0.9.8 Alliance Semiconductor P. 6 of 8
®
Write waveform 2 (CE controlled)
AC test conditions
Notes
1During V
CC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
2 This parameter is sampled, but not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A, B, and C.
4t
CLZ and tCHZ are specified with CL = 5pF, as in Figure C. Transition is measured ±500mV from steady-st ate voltage.
5 This parameter is guaranteed, but not 100% tested.
6WE
is High for read cycle.
7CE
and OE are Low for read cycle.
8 Address valid prior to or coincident with CE transition Low.
9 All read cycle timings are re ferenced from the last valid address to the first transitioning address.
10 CE or WE must be High during address transitions. Eit her CE or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 NA.
13 C=30pF, except all high Z and low Z parameters, where C=5pF.
t
AW
Address
CE
WE
D
OUT
t
CW
t
WP
t
DW
t
DH
t
AH
t
WZ
t
WC
t
AS
Data valid
D
IN
t
WR
255
Ω
– Output load: see Figure B or Figure C.
– Input pulse level: GND to 3.0V. See Figure A.
– Input rise and fall times: 2 ns. See Figure A.
– Input and output timing reference levels: 1.5V.
C(14)
320
Ω
D
OUT
GND
+3.3V
168
Ω
Thevenin equivalent:
D
OUT
+1.728V (5V and 3.3V)
Figure C: 3.3V Output load
255
Ω
C(14)
480
Ω
D
OUT
GND
+5V
Figure B: 5V Output load
10%
90%
10%
90%
GND
+3.0V
Figure A: Input pulse
2 ns
AS7C1025A
AS7C31025A
9/26/02; v.0.9.8 Alliance Semiconductor P. 7 of 8
®
Package dimensions
Symbol
32-pin TSOP 2 (mm)
Min Max
A–1.2
A1 0.05 0.15
b0.3 0.52
C0.12 0.21
D20.82 21.08
E1 10.03 10.29
E11.56 11.96
e1.27 BSC
L0.40 0.60
ZD 0.95 REF.
α0° 5°
32-pin TSOP 2
NN/2+1
1N/2
D
E1 E
L
α
c
ZD
cbA1
ASeating plane
eD
E1
Pin 1
b
B
A1
A2 c
E
Seating
Plane
E2
A
32-pin SOJ
300 mil/400 mil
Symbol
32-pin SOJ
300 mil 32-pin SOJ
400 mil
Min Max Min Max
A-0.145-0.145
A1 0.025 - 0.025 -
A2 0.086 0.105 0.086 0.115
B0.026 0.032 0.026 0.032
b0.014 0.020 0.015 0.020
c0.006 0.013 0.007 0.013
D0.820 0.830 0.820 0.830
E0.250 0.275 0.360 0.380
E1 0.292 0.305 0.395 0.405
E2 0.330 0.340 0.435 0.445
e0.050 BSC 0.050 BSC
AS7C1025A
AS7C31025A
© C o py rig h t A llia nc e S e m ico n du c tor C or po ra tion . All r ig hts r ese rv ed . O u r th re e-p o int lo g o, o u r n ame an d I nte lliw a tt are tra de m arks or registered trademarks of Alliance. All other brand and
p
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res po n sibilit y f or an y e rro rs tha t m a y a pp e ar in th is do c umen t. T h e d ata co nta in ed he rein re p rese n ts A llia nc e’s b est d ata an d /or estimates at th e time o f issuance. Alliance reserves the right to
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again st all cla im s arising fro m such use.
9/26/02; v.0.9.8 Alliance Semiconductor P. 8 of 8
®
Ordering codes
Package \
Access time Volt. Temperature 10 ns 12 ns 15 ns 20 ns
TSOP 2 5V Commercial AS7C1025A-10HFC AS7C1025A-12HFC AS7C1025A-15HFC AS7C1025A-20HFC
Industrial AS7C1025A-10TI AS7C1025A-12HFI AS7C1025A-15HFI AS7C1025A-20HFI
3.3V Commercial AS7C31025A-10HFC AS7C31025A-12HFC AS7C31025A-15HFC AS7C31025A-20HFC
Industrial AS7C31025A-10HFI AS7C31025A-12HFI AS7C31025A-15HFI AS7C31025A-20HFI
300-mil SOJ 5V Commercial AS7C1025A-10TJC AS7C1025A-12TJC AS7C1025A-15TJC AS7C1025A-20TJC
Industrial AS7C1025A-10TJI AS7C1025A-12TJI AS7C1025A-15TJI AS7C1025A-20TJI
3.3V Commercial AS7C31025A-10TJC AS7C31025A-12TJC AS7C31025A-15TJC AS7C31025A-20TJC
Industrial AS7C31025A-10TJI AS7C31025A-12TJI AS7C31025A-15TJI AS7C31025A-20TJI
400-mil SOJ 5V Commercial AS7C1025A-10JC AS7C1025A-12JC AS7C1025A-15JC AS7C1025A-20JC
Industrial AS7C1025A-10JI AS7C1025A-12JI AS7C1025A-15JI AS7C1025A-20JI
3.3V Commercial AS7C31025A-10JC AS7C31025A-12JC AS7C31025A-15JC AS7C31025A-20JC
Industrial AS7C31025A-10JI AS7C31025A-12JI AS7C31025A-15JI AS7C31025A-20JI
Part numbering system
AS7C X1025 –XX X X
SRAM
prefix
Voltage:
Blank=5V CMOS
3=3.3V CMOS Device number Access time
Package:
HF = TSOP 2 / 32 Pin
TJ = SOJ 300 mil
J = SOJ 400 mil
Temperature range
C = Commercial, 0°C to 70°C
I = Industrial, -40°C to 85°C