a DSP Microcomputer ADSP-2188M System Interface Flexible I/O Structure Allows 2.75 V or 3.3 V Operation; All Inputs Tolerate up to 3.6 V Regardless of Mode 16-Bit Internal DMA Port for High-Speed Access to On-Chip Memory (Mode Selectable) 4 MByte Memory Interface for Storage of Data Tables and Program Overlays (Mode Selectable) 8-Bit DMA to Byte Memory for Transparent Program and Data Memory Transfers (Mode Selectable) I/O Memory Interface with 2048 Locations Supports Parallel Peripherals (Mode Selectable) Programmable Memory Strobe and Separate I/O Memory Space Permits "Glueless" System Design Programmable Wait State Generation Two Double-Buffered Serial Ports with Companding Hardware and Automatic Data Buffering Automatic Booting of On-Chip Program Memory from Byte-Wide External Memory, e.g., EPROM, or through Internal DMA Port Six External Interrupts 13 Programmable Flag Pins Provide Flexible System Signaling UART Emulation through Software SPORT Reconfiguration ICE-PortTM Emulator Interface Supports Debugging in Final Systems FEATURES Performance 13.3 ns Instruction Cycle Time @ 2.75 V (Internal), 75 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions Power-Down Mode Featuring Low CMOS Standby Power Dissipation with 200 CLKIN Cycle Recovery from Power-Down Condition Low Power Dissipation in Idle Mode Integration ADSP-2100 Family Code Compatible (Easy to Use Algebraic Syntax), with Instruction Set Extensions 256K Bytes of On-Chip RAM, Configured as 48K Words Program Memory RAM 56K Words Data Memory RAM Dual-Purpose Program Memory for Both Instruction and Data Storage Independent ALU, Multiplier/Accumulator, and Barrel Shifter Computational Units Two Independent Data Address Generators Powerful Program Sequencer Provides Zero Overhead Looping Conditional Instruction Execution Programmable 16-Bit Interval Timer with Prescaler 100-Lead LQFP and 144-Ball Mini-BGA FUNCTIONAL BLOCK DIAGRAM POWER-DOWN CONTROL FULL MEMORY MODE MEMORY DATA ADDRESS GENERATORS DAG1 DAG2 PROGRAM SEQUENCER PROGRAM MEMORY 48K 24 BIT DATA MEMORY 56K 16 BIT PROGRAMMABLE I/O AND FLAGS EXTERNAL DATA BUS PROGRAM MEMORY ADDRESS DATA MEMORY ADDRESS BYTE DMA CONTROLLER PROGRAM MEMORY DATA OR DATA MEMORY DATA ARITHMETIC UNITS ALU MAC SHIFTER EXTERNAL ADDRESS BUS EXTERNAL DATA BUS SERIAL PORTS SPORT0 ADSP-2100 BASE ARCHITECTURE SPORT1 TIMER INTERNAL DMA PORT HOST MODE ICE-Port is a trademark of Analog Devices, Inc. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000 ADSP-2188M TABLE OF CONTENTS RECOMMENDED OPERATING CONDITIONS . . . . . ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . GENERAL NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIMING NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MEMORY TIMING SPECIFICATIONS . . . . . . . . . . . . FREQUENCY DEPENDENCY FOR TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . ENVIRONMENTAL CONDITIONS . . . . . . . . . . . . . . . POWER DISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . . Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . . . . . Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Disable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Enable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Signals and Reset . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Request-Bus Grant . . . . . . . . . . . . . . . . . . . . . . . . . Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDMA Address Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . IDMA Write, Short Write Cycle . . . . . . . . . . . . . . . . . . IDMA Write, Long Write Cycle . . . . . . . . . . . . . . . . . . . IDMA Read, Long Read Cycle . . . . . . . . . . . . . . . . . . . IDMA Read, Short Read Cycle . . . . . . . . . . . . . . . . . . . IDMA Read, Short Read Cycle in Short Read Only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100-LEAD LQFP PIN CONFIGURATION . . . . . . . . . . LQFP Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144-Ball Mini-BGA Package Pinout . . . . . . . . . . . . . . . . . Mini-BGA Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . OUTLINE DIMENSIONS 100-Lead Metric Thin Plastic Quad Flatpack (LQFP) (ST-100) . . . . . . . . . . . . . . . . . . . . . . . . . . . OUTLINE DIMENSIONS 144-Ball Mini-BGA (CA-144) . . . . . . . . . . . . . . . . . . . . ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 3 DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . 3 Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . 4 Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Common-Mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Memory Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Full Memory Mode Pins (Mode C = 0) . . . . . . . . . . . . . . 7 Host Mode Pins (Mode C = 1) . . . . . . . . . . . . . . . . . . . . 7 Terminating Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 LOW POWER OPERATION . . . . . . . . . . . . . . . . . . . . . . . 9 Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Slow Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SYSTEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 MODES OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . 11 Setting Memory Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Passive Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Active Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 IACK Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 MEMORY ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . 12 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Memory Mapped Registers (New to the ADSP-2188M) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 I/O Space (Full Memory Mode) . . . . . . . . . . . . . . . . . . . 14 Composite Memory Select (CMS) . . . . . . . . . . . . . . . . . 14 Byte Memory Select (BMS) . . . . . . . . . . . . . . . . . . . . . . 14 Byte Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Byte Memory DMA (BDMA, Full Memory Mode) . . . . 14 Internal Memory DMA Port (IDMA Port; Host Memory Mode) . . . . . . . . . . . . . . 15 Bootstrap Loading (Booting) . . . . . . . . . . . . . . . . . . . . . 16 IDMA Port Booting . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Bus Request and Bus Grant . . . . . . . . . . . . . . . . . . . . . . 16 Flag I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Instruction Set Description . . . . . . . . . . . . . . . . . . . . . . 17 DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM . . . 17 Target Board Connector for EZ-ICE Probe . . . . . . . . . . 18 Target Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . 18 PM, DM, BM, IOM, AND CM . . . . . . . . . . . . . . . . . . . . 18 Target System Interface Signals . . . . . . . . . . . . . . . . . . . 18 19 19 20 20 20 20 20 21 21 21 21 22 23 23 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 40 40 Tables Table I. Interrupt Priority and Interrupt Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table II. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . 11 Table III. PMOVLAY Bits . . . . . . . . . . . . . . . . . . . . . . . . 12 Table IV. DMOVLAY Bits . . . . . . . . . . . . . . . . . . . . . . . . 13 Table V. Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table VI. Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . 14 -2- REV. 0 ADSP-2188M GENERAL DESCRIPTION The ADSP-2188M is a single-chip microcomputer optimized for digital signal processing (DSP) and other high-speed numeric processing applications. The ADSP-2188M combines the ADSP-2100 family base architecture (three computational units, data address generators, and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities, and on-chip program and data memory. The ADSP-2188M integrates 256K bytes of on-chip memory configured as 48K words (24-bit) of program RAM, and 56K words (16-bit) of data RAM. Power-down circuitry is also provided to meet the low power needs of battery-operated portable equipment. The ADSP-2188M is available in a 100-lead LQFP package and 144 Ball Mini-BGA. In addition, the ADSP-2188M supports new instructions, which include bit manipulations--bit set, bit clear, bit toggle, bit test-- new ALU constants, new multiplication instruction (x squared), biased rounding, result-free ALU operations, I/O memory transfers, and global interrupt masking, for increased flexibility. Fabricated in a high-speed, low-power, CMOS process, the ADSP-2188M operates with a 13.3 ns instruction cycle time. Every instruction can execute in a single processor cycle. The ADSP-2188M's flexible architecture and comprehensive instruction set allow the processor to perform multiple operations in parallel. In one processor cycle, the ADSP-2188M can: * * * * * Generate the next program address Fetch the next instruction Perform one or two data moves Update one or two data address pointers Perform a computational operation This takes place while the processor continues to: * * * * Receive and transmit data through the two serial ports Receive and/or transmit data through the internal DMA port Receive and/or transmit data through the byte DMA port Decrement timer DEVELOPMENT SYSTEM The ADSP-2100 Family Development Software, a complete set of tools for software and hardware system development, supports the ADSP-2188M. The System Builder provides a high-level method for defining the architecture of systems under development. The Assembler has an algebraic syntax that is easy to program and debug. The Linker combines object files into an executable file. The Simulator provides an interactive instructionlevel simulation with a reconfigurable user interface to display different portions of the hardware environment. The EZ-KIT Lite is a hardware/software kit offering a complete evaluation environment for the ADSP-218x family: an ADSP2189M-based evaluation board with PC monitor software plus assembler, linker, simulator, and PROM splitter software. The ADSP-2189M EZ-KIT Lite is a low cost, easy to use hardware platform on which you can quickly get started with your DSP software design. The EZ-KIT Lite includes the following features: * * * * * * The ADSP-218x EZ-ICE(R) Emulator aids in the hardware debugging of an ADSP-2188M system. The ADSP-2188M integrates on-chip emulation support with a 14-pin ICE-Port interface. This interface provides a simpler target board connection that requires fewer mechanical clearance considerations than other ADSP-2100 Family EZ-ICEs. The ADSP-2188M device need not be removed from the target system when using the EZ-ICE, nor are any adapters needed. Due to the small footprint of the EZ-ICE connector, emulation can be supported in final board designs. The EZ-ICE performs a full range of functions, including: * * * * * * * * In-target operation Up to 20 breakpoints Single-step or full-speed operation Registers and memory values can be examined and altered PC upload and download functions Instruction-level emulation of program booting and execution Complete assembly and disassembly of instructions C source-level debugging See Designing An EZ-ICE-Compatible Target System in the ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections) as well as the Designing an EZ-ICE-Compatible System section of this data sheet for the exact specifications of the EZ-ICE target board connector. Additional Information This data sheet provides a general overview of ADSP-2188M functionality. For additional information on the architecture and instruction set of the processor, refer to the ADSP-2100 Family User's Manual. For more information about the development tools, refer to the ADSP-2100 Family Development Tools data sheet. EZ-ICE is a registered trademark of Analog Devices, Inc. REV. 0 75 MHz ADSP-2189M Full 16-Bit Stereo Audio I/O with AD73322 Codec RS-232 Interface EZ-ICE Connector for Emulator Control DSP Demo Programs Evaluation Suite of VisualDSP -3- ADSP-2188M POWER-DOWN CONTROL FULL MEMORY MODE MEMORY DATA ADDRESS GENERATORS DAG1 DAG2 PROGRAM SEQUENCER PROGRAM MEMORY 48K 24 BIT DATA MEMORY 56K 16 BIT PROGRAMMABLE I/O AND FLAGS EXTERNAL DATA BUS PROGRAM MEMORY ADDRESS BYTE DMA CONTROLLER DATA MEMORY ADDRESS PROGRAM MEMORY DATA OR DATA MEMORY DATA ARITHMETIC UNITS ALU MAC SHIFTER EXTERNAL DATA BUS SERIAL PORTS SPORT0 EXTERNAL ADDRESS BUS TIMER SPORT1 ADSP-2100 BASE ARCHITECTURE INTERNAL DMA PORT HOST MODE Figure 1. Functional Block Diagram (indirect addressing), it is post-modified by the value of one of four possible modify registers. A length value may be associated with each pointer to implement automatic modulo addressing for circular buffers. ARCHITECTURE OVERVIEW The ADSP-2188M instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. Every instruction can be executed in a single processor cycle. The ADSP-2188M assembly language uses an algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development. Efficient data transfer is achieved with the use of five internal buses: * * * * * Figure 1 is an overall block diagram of the ADSP-2188M. The processor contains three independent computational units: the ALU, the multiplier/accumulator (MAC), and the shifter. The computational units process 16-bit data directly and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations; division primitives are also supported. The MAC performs single-cycle multiply, multiply/add, and multiply/subtract operations with 40 bits of accumulation. The shifter performs logical and arithmetic shifts, normalization, denormalization, and derive exponent operations. Program Memory Address (PMA) Bus Program Memory Data (PMD) Bus Data Memory Address (DMA) Bus Data Memory Data (DMD) Bus Result (R) Bus The two address buses (PMA and DMA) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (PMD and DMD) share a single external data bus. Byte memory space and I/O memory space also share the external buses. Program memory can store both instructions and data, permitting the ADSP-2188M to fetch two operands in a single cycle, one from program memory and one from data memory. The ADSP-2188M can fetch an operand from program memory and the next instruction in the same cycle. The shifter can be used to efficiently implement numeric format control, including multiword and block floating-point representations. The internal result (R) bus connects the computational units so that the output of any unit may be the input of any unit on the next cycle. In lieu of the address and data bus for external memory connection, the ADSP-2188M may be configured for 16-bit Internal DMA port (IDMA port) connection to external systems. The IDMA port is made up of 16 data/address pins and five control pins. The IDMA port provides transparent, direct access to the DSPs on-chip program and data RAM. A powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these computational units. The sequencer supports conditional jumps, subroutine calls, and returns in a single cycle. With internal loop counters and loop stacks, the ADSP-2188M executes looped code with zero overhead; no explicit jump instructions are required to maintain loops. An interface to low-cost byte-wide memory is provided by the Byte DMA port (BDMA port). The BDMA port is bidirectional and can directly address up to four megabytes of external RAM or ROM for off-chip storage of program overlays or data tables. Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches (from data memory and program memory). Each DAG maintains and updates four address pointers. Whenever the pointer is used to access data The byte memory and I/O memory space interface supports slow memories and I/O memory-mapped peripherals with programmable wait state generation. External devices can gain control of -4- REV. 0 ADSP-2188M external buses with bus request/grant signals (BR, BGH, and BG). One execution mode (Go Mode) allows the ADSP-2188M to continue running from on-chip memory. Normal execution mode requires the processor to halt while buses are granted. The ADSP-2188M can respond to eleven interrupts. There can be up to six external interrupts (one edge-sensitive, two levelsensitive, and three configurable) and seven internal interrupts generated by the timer, the serial ports (SPORTs), the Byte DMA port, and the power-down circuitry. There is also a master RESET signal. The two serial ports provide a complete synchronous serial interface with optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of operation. Each port can generate an internal programmable serial clock or accept an external serial clock. The ADSP-2188M provides up to 13 general-purpose flag pins. The data input and output pins on SPORT1 can be alternatively configured as an input flag and an output flag. In addition, eight flags are programmable as inputs or outputs, and three flags are always outputs. A programmable interval timer generates periodic interrupts. A 16-bit count register (TCOUNT) decrements every n processor cycle, where n is a scaling value stored in an 8-bit register (TSCALE). When the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (TPERIOD). Serial Ports The ADSP-2188M incorporates two complete synchronous serial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication. Here is a brief list of the capabilities of the ADSP-2188M SPORTs. For additional information on Serial Ports, refer to the ADSP-2100 Family User's Manual. * SPORTs can use an external serial clock or generate their own serial clock internally. * SPORTs have independent framing for the receive and transmit sections. Sections run in a frameless mode or with frame synchronization signals internally or externally generated. Frame sync signals are active high or inverted, with either of two pulsewidths and timings. * SPORTs support serial data word lengths from 3 to 16 bits and provide optional A-law and -law companding according to CCITT recommendation G.711. * SPORT receive and transmit sections can generate unique interrupts on completing a data word transfer. * SPORTs can receive and transmit an entire circular buffer of data with only one overhead cycle per data word. An interrupt is generated after a data buffer transfer. * SPORT0 has a multichannel interface to selectively receive and transmit a 24 or 32 word, time- division multiplexed, serial bitstream. * SPORT1 can be configured to have two external interrupts (IRQ0 and IRQ1) and the FI and FO signals. The internally generated serial clock may still be used in this configuration. PIN DESCRIPTIONS The ADSP-2188M is available in a 100-lead LQFP package and a 144-Ball Mini-BGA package. In order to maintain maximum functionality and reduce package size and pin count, some serial port, programmable flag, interrupt and external bus pins have dual, multiplexed functionality. The external bus pins are configured during RESET only, while serial port pins are software configurable during program execution. Flag and interrupt functionality is retained concurrently on multiplexed pins. In cases where pin functionality is reconfigurable, the default state is shown in plain text; alternate functionality is shown in italics. * SPORTs are bidirectional and have a separate, doublebuffered transmit and receive section. REV. 0 -5- ADSP-2188M Common-Mode Pins Pin Name # of Pins I/O Function RESET BR BG BGH DMS PMS IOMS BMS CMS RD WR 1 1 1 1 1 1 1 1 1 1 1 I I O O O O O O O O O Processor Reset Input Bus Request Input Bus Grant Output Bus Grant Hung Output Data Memory Select Output Program Memory Select Output Memory Select Output Byte Memory Select Output Combined Memory Select Output Memory Read Enable Output Memory Write Enable Output IRQ2 PF7 1 I I/O Edge- or Level-Sensitive Interrupt Request1 Programmable I/O Pin IRQL1 PF6 1 I I/O Level-Sensitive Interrupt Requests1 Programmable I/O Pin IRQL0 PF5 1 I I/O Level-Sensitive Interrupt Requests1 Programmable I/O Pin IRQE PF4 1 I I/O Edge-Sensitive Interrupt Requests1 Programmable I/O Pin Mode D PF3 1 I I/O Mode Select Input--Checked Only During RESET Programmable I/O Pin During Normal Operation Mode C PF2 1 I I/O Mode Select Input--Checked Only During RESET Programmable I/O Pin During Normal Operation Mode B PF1 1 I I/O Mode Select Input--Checked Only During RESET Programmable I/O Pin During Normal Operation Mode A PF0 1 I I/O Mode Select Input--Checked Only During RESET Programmable I/O Pin During Normal Operation CLKIN, XTAL CLKOUT SPORT0 SPORT1 IRQ1:0, FI, FO PWD PWDACK FL0, FL1, FL2 VDDINT VDDEXT GND VDDINT VDDEXT GND EZ-Port 2 1 5 5 I O I/O I/O 1 1 3 2 4 10 4 7 20 9 I O O I I I I I I I/O Clock or Quartz Crystal Input Processor Clock Output Serial Port I/O Pins Serial Port I/O Pins Edge- or Level-Sensitive Interrupts, FI, FO2 Power-Down Control Input Power-Down Control Output Output Flags Internal VDD (2.75 V) Power (LQFP) External VDD (2.75 V or 3.3 V) Power (LQFP) Ground (LQFP) Internal VDD (2.75 V) Power (Mini-BGA) External VDD (2.75 V or 3.3 V) Power (Mini-BGA) Ground (Mini-BGA) For Emulation Use NOTES 1 Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, then the DSP will vector to the appropriate interrupt vector address when the pin is asserted, either by external devices, or set as a programmable flag. 2 SPORT configuration determined by the DSP System Control Register. Software configurable. -6- REV. 0 ADSP-2188M Memory Interface Pins The ADSP-2188M processor can be used in one of two modes: Full Memory Mode, which allows BDMA operation with full external overlay memory and I/O capability, or Host Mode, which allows IDMA operation with limited external addressing capabilities. The operating mode is determined by the state of the Mode C pin during RESET and cannot be changed while the processor is running. The following tables list the active signals at specific pins of the DSP during either of the two operating modes (Full Memory or Host). A signal in one table shares a pin with a signal from the other table, with the active signal determined by the mode set. For the shared pins and their alternate signals (e.g., A4/IAD3), refer to the package pinout tables. Full Memory Mode Pins (Mode C = 0) Pin Name # of Pins I/O Function A13:0 D23:0 14 24 O I/O Address Output Pins for Program, Data, Byte, and I/O Spaces Data I/O Pins for Program, Data, Byte, and I/O Spaces (8 MSBs are also used as Byte Memory Addresses.) Host Mode Pins (Mode C = 1) Pin Name # of Pins I/O Function IAD15:0 A0 D23:8 IWR 16 1 16 1 1 1 1 1 I/O O I/O I I I I O IDMA Port Address/Data Bus Address Pin for External I/O, Program, Data, or Byte Access1 Data I/O Pins for Program, Data, Byte, and I/O Spaces IDMA Write Enable IDMA Read Enable IDMA Address Latch Pin IDMA Select IDMA Port Acknowledge Configurable in Mode D; Open Drain IRD IAL IS IACK NOTE 1 In Host Mode, external peripheral addresses can be decoded using the A0, CMS, PMS, DMS, and IOMS signals. REV. 0 -7- ADSP-2188M Terminating Unused Pins The following table shows the recommendations for terminating unused pins. Pin Terminations Pin Name XTAL CLKOUT A13:1 or IAD 12:0 A0 D23:8 D7 or IWR D6 or IRD D5 or IAL D4 or IS D3 or IACK D2:0 or IAD15:13 PMS DMS BMS IOMS CMS RD WR BR BG BGH IRQ2/PF7 IRQL1/PF6 IRQL0/PF5 IRQE/PF4 SCLK0 RFS0 DR0 TFS0 DT0 SCLK1 RFS1/IRQ0 DR1/FI TFS1/IRQ1 DT1/FO EE EBR EBG ERESET EMS EINT ECLK ELIN ELOUT I/O 3-State (Z) Reset State I O O (Z) I/O (Z) O (Z) I/O (Z) I/O (Z) I I/O (Z) I I/O (Z) I I/O (Z) I I/O (Z) I O Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z I Hi-Z I Hi-Z I Hi-Z I Hi-Z I/O (Z) I/O (Z) O (Z) O (Z) O (Z) O (Z) O (Z) O (Z) O (Z) I O (Z) O I/O (Z) I/O (Z) I/O (Z) I/O (Z) I/O I/O I I/O O I/O I/O I I/O O I I O I O I I I O Hi-Z Hi-Z O O O O O O O I O O I I I I I I I I O I I I I O I I O I O I I I O Hi-Z* Caused By BR, EBR IS BR, EBR BR, EBR BR, EBR BR, EBR BR, EBR BR, EBR BR, EBR BR, EBR IS BR, EBR BR, EBR BR, EBR BR, EBR BR, EBR BR, EBR BR, EBR EE Unused Configuration Float Float Float Float Float Float Float High (Inactive) Float High (Inactive) Float Low (Inactive) Float High (Inactive) Float Float Float Float Float Float Float Float Float Float Float High (Inactive) Float Float Input = High (Inactive) or Program as Output, Set to 1, Let Float Input = High (Inactive) or Program as Output, Set to 1, Let Float Input = High (Inactive) or Program as Output, Set to 1, Let Float Input = High (Inactive) or Program as Output, Set to 1, Let Float Input = High or Low, Output = Float High or Low High or Low High or Low Float Input = High or Low, Output = Float High or Low High or Low High or Low Float Float Float Float Float Float Float Float Float Float NOTES *Hi-Z = High Impedance. 1. If the CLKOUT pin is not used, turn it OFF, using CLKODIS in SPORT0 autobuffer control register. 2. If the Interrupt/Programmable Flag pins are not used, there are two options: Option 1: When these pins are configured as INPUTS at reset and function as interrupts and input flag pins, pull the pins High (inactive). Option 2: Program the unused pins as OUTPUTS, set them to 1, prior to enabling interrupts, and let pins float. 3. All bidirectional pins have three-stated outputs. When the pin is configured as an output, the output is Hi-Z (high impedance) when inactive. 4. CLKIN, RESET, and PF3:0/MODE D:A are not included in the table because these pins must be used. -8- REV. 0 ADSP-2188M Interrupts LOW POWER OPERATION The interrupt controller allows the processor to respond to the 11 possible interrupts and reset with minimum overhead. The ADSP-2188M provides four dedicated external interrupt input pins: IRQ2, IRQL0, IRQL1, and IRQE (shared with the PF7:4 pins). In addition, SPORT1 may be reconfigured for IRQ0, IRQ1, FI and FO, for a total of six external interrupts. The ADSP-2188M also supports internal interrupts from the timer, the byte DMA port, the two serial ports, software, and the powerdown control circuit. The interrupt levels are internally prioritized and individually maskable (except power- down and reset). The IRQ2, IRQ0, and IRQ1 input pins can be programmed to be either level- or edge-sensitive. IRQL0 and IRQL1 are levelsensitive and IRQE is edge-sensitive. The priorities and vector addresses of all interrupts are shown in Table I. The ADSP-2188M has three low power modes that significantly reduce the power dissipation when the device operates under standby conditions. These modes are: Table I. Interrupt Priority and Interrupt Vector Addresses * Power-Down * Idle * Slow Idle The CLKOUT pin may also be disabled to reduce external power dissipation. Power-Down The ADSP-2188M processor has a low power feature that lets the processor enter a very low-power dormant state through hardware or software control. Following is a brief list of powerdown features. Refer to the ADSP-2100 Family User's Manual, "System Interface" chapter, for detailed information about the power-down feature. Source Of Interrupt Interrupt Vector Address (Hex) * Quick recovery from power-down. The processor begins executing instructions in as few as 200 CLKIN cycles. Reset (or Power-Up with PUCR = 1) Power-Down (Nonmaskable) IRQ2 IRQL1 IRQL0 SPORT0 Transmit SPORT0 Receive IRQE BDMA Interrupt SPORT1 Transmit or IRQ1 SPORT1 Receive or IRQ0 Timer 0000 (Highest Priority) 002C 0004 0008 000C 0010 0014 0018 001C 0020 0024 0028 (Lowest Priority) * Support for an externally generated TTL or CMOS processor clock. The external clock can continue running during powerdown without affecting the lowest power rating and 200 CLKIN cycle recovery. Interrupt routines can either be nested with higher priority interrupts taking precedence or processed sequentially. Interrupts can be masked or unmasked with the IMASK register. Individual interrupt requests are logically ANDed with the bits in IMASK; the highest priority unmasked interrupt is then selected. The power-down interrupt is nonmaskable. The ADSP-2188M masks all interrupts for one instruction cycle following the execution of an instruction that modifies the IMASK register. This does not affect serial port autobuffering or DMA transfers. The interrupt control register, ICNTL, controls interrupt nesting and defines the IRQ0, IRQ1, and IRQ2 external interrupts to be either edge- or level-sensitive. The IRQE pin is an external edge sensitive interrupt and can be forced and cleared. The IRQL0 and IRQL1 pins are external level sensitive interrupts. * Support for crystal operation includes disabling the oscillator to save power (the processor automatically waits approximately 4096 CLKIN cycles for the crystal oscillator to start or stabilize), and letting the oscillator run to allow 200 CLKIN cycle start-up. * Power-down is initiated by either the power-down pin (PWD) or the software power-down force bit. Interrupt support allows an unlimited number of instructions to be executed before optionally powering down. The power-down interrupt also can be used as a nonmaskable, edge-sensitive interrupt. * Context clear/save control allows the processor to continue where it left off or start with a clean context when leaving the power-down state. * The RESET pin also can be used to terminate power-down. * Power-down acknowledge pin indicates when the processor has entered power-down. Idle When the ADSP-2188M is in the Idle Mode, the processor waits indefinitely in a low-power state until an interrupt occurs. When an unmasked interrupt occurs, it is serviced; execution then continues with the instruction following the IDLE instruction. In Idle mode IDMA, BDMA and autobuffer cycle steals still occur. The IFC register is a write-only register used to force and clear interrupts. On-chip stacks preserve the processor status and are automatically maintained during interrupt handling. The stacks are twelve levels deep to allow interrupt, loop, and subroutine nesting. The following instructions allow global enable or disable servicing of the interrupts (including power down), regardless of the state of IMASK. Disabling the interrupts does not affect serial port autobuffering or DMA. Slow Idle ENA INTS; DIS INTS; IDLE (n); When the processor is reset, interrupt servicing is enabled. REV. 0 The IDLE instruction is enhanced on the ADSP-2188M to let the processor's internal clock signal be slowed, further reducing power consumption. The reduced clock frequency, a programmable fraction of the normal clock rate, is specified by a selectable divisor given in the IDLE instruction. The format of the instruction is: where n = 16, 32, 64, or 128. This instruction keeps the processor fully functional, but operating at the slower clock rate. While it is in this state, the processor's other internal clock signals, such -9- ADSP-2188M FULL MEMORY MODE HOST MEMORY MODE ADSP-2188M 1/2x CLOCK OR CRYSTAL ADSP-2188M CLKIN XTAL 14 SERIAL DEVICE SERIAL DEVICE D23-16 IRQ2/PF7 IRQE/PF4 DATA23-0 IRQL0/PF5 BMS IRQL1/PF6 WR MODE D/PF3 RD MODE C/PF2 MODE A/PF0 MODE B/PF1 IOMS SPORT1 SCLK1 RFS1 OR IRQ0 TFS1 OR IRQ1 DT1 OR FO PMS DR1 OR FI DMS CMS SPORT0 SCLK0 RFS0 TFS0 DT0 DR0 A13-0 ADDR13-0 FL0-2 24 CLKIN 1/2x CLOCK OR CRYSTAL XTAL A0-A21 BYTE MEMORY D15-8 DATA IRQ2/PF7 IRQE/PF4 DATA23-8 IRQL0/PF5 IRQL1/PF6 BMS MODE D/PF3 WR MODE C/PF2 RD MODE A/PF0 MODE B/PF1 CS A10-0 ADDR D23-8 DATA I/O SPACE (PERIPHERALS) 2048 LOCATIONS CS A13-0 ADDR D23-0 DATA 1 A0 FL0-2 SPORT1 SCLK1 RFS1 OR IRQ0 TFS1 OR IRQ1 DT1 OR FO DR1 OR FI SERIAL DEVICE OVERLAY MEMORY TWO 8K PM SEGMENTS TWO 8K DM SEGMENTS SPORT0 SCLK0 RFS0 TFS0 DT0 DR0 SERIAL DEVICE BR BG BGH PWD PWDACK SYSTEM INTERFACE OR CONTROLLER 16 16 IOMS PMS DMS CMS BR BG BGH PWD IDMA PORT PWDACK IRD/D6 IWR/D7 IS/D4 IAL/D5 IACK/D3 IAD15-0 Figure 2. Basic System Interface as SCLK, CLKOUT, and timer clock, are reduced by the same ratio. The default form of the instruction, when no clock divisor is given, is the standard IDLE instruction. When the IDLE (n) instruction is used, it effectively slows down the processor's internal clock and thus its response time to incoming interrupts. The one-cycle response time of the standard idle state is increased by n, the clock divisor. When an enabled interrupt is received, the ADSP-2188M will remain in the idle state for up to a maximum of n processor cycles (n = 16, 32, 64, or 128) before resuming normal operation. When the IDLE (n) instruction is used in systems that have an externally generated serial clock (SCLK), the serial clock rate may be faster than the processor's reduced internal clock rate. Under these conditions, interrupts must not be generated at a faster than can be serviced, due to the additional time the processor takes to come out of the idle state (a maximum of n processor cycles). The CLKIN input cannot be halted, changed during operation, nor operated below the specified frequency during normal operation. The only exception is while the processor is in the power-down state. For additional information, refer to Chapter 9, ADSP-2100 Family User's Manual, for detailed information on this power-down feature. If an external clock is used, it should be a TTL-compatible signal running at half the instruction rate. The signal is connected to the processor's CLKIN input. When an external clock is used, the XTAL input must be left unconnected. The ADSP-2188M uses an input clock with a frequency equal to half the instruction rate; a 37.50 MHz input clock yields a 13 ns processor cycle (which is equivalent to 75 MHz). Normally, instructions are executed in a single processor cycle. All device timing is relative to the internal instruction clock rate, which is indicated by the CLKOUT signal when enabled. SYSTEM INTERFACE Figure 2 shows typical basic system configurations with the ADSP-2188M, two serial devices, a byte-wide EPROM, and optional external program and data overlay memories (modeselectable). Programmable wait state generation allows the processor to connect easily to slow peripheral devices. The ADSP-2188M also provides four external interrupts and two serial ports or six external interrupts and one serial port. Host Memory Mode allows access to the full external data bus, but limits addressing to a single address bit (A0). Through the use of external hardware, additional system peripherals can be added in this mode to generate and latch address signals. Because the ADSP-2188M includes an on-chip oscillator circuit, an external crystal may be used. The crystal should be connected across the CLKIN and XTAL pins, with two capacitors connected as shown in Figure 3. Capacitor values are dependent on crystal type and should be specified by the crystal manufacturer. A parallel-resonant, fundamental frequency, microprocessorgrade crystal should be used. A clock output (CLKOUT) signal is generated by the processor at the processor's cycle rate. This can be enabled and disabled by the CLKODIS bit in the SPORT0 Autobuffer Control Register. Clock Signals CLKIN XTAL CLKOUT DSP The ADSP-2188M can be clocked by either a crystal or a TTL-compatible clock signal. Figure 3. External Crystal Connections -10- REV. 0 ADSP-2188M RESET The RESET signal initiates a master reset of the ADSP-2188M. The RESET signal must be asserted during the power-up sequence to assure proper initialization. RESET during initial power-up must be held long enough to allow the internal clock to stabilize. If RESET is activated any time after power-up, the clock continues to run and does not require stabilization time. The power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid VDD is applied to the processor, and for the internal phase-locked loop (PLL) to lock onto the specific crystal frequency. A minimum of 2000 CLKIN cycles ensures that the PLL has locked but does not include the crystal oscillator start-up time. During this power-up sequence the RESET signal should be held low. On any subsequent resets, the RESET signal must meet the minimum pulsewidth specification, tRSP. The RESET input contains some hysteresis; however, if an RC circuit is used to generate the RESET signal, the use of an external Schmidt trigger is recommended. The master reset sets all internal stack pointers to the empty stack condition, masks all interrupts, and clears the MSTAT register. When RESET is released, if there is no pending bus request and the chip is configured for booting, the boot-loading sequence is performed. The first instruction is fetched from on-chip program memory location 0x0000 once boot loading completes. Power Supplies The ADSP-2188M has separate power supply connections for the internal (VDDINT) and external (VDDEXT) power supplies. The internal supply must meet the 2.75 V requirement. The external supply can be connected to either a 2.75 V or 3.3 V supply. All external supply pins must be connected to the same supply. All input and I/O pins can tolerate input voltages up to 3.6 V, regardless of the external supply voltage. This feature provides maximum flexibility in mixing 2.75 V and 3.3 V components. MODES OF OPERATION Setting Memory Mode Memory Mode selection for the ADSP-2188M is made during chip reset through the use of the Mode C pin. This pin is multiplexed with the DSP's PF2 pin, so care must be taken in how the mode selection is made. The two methods for selecting the value of Mode C are active and passive. Passive Configuration Passive Configuration involves the use a pull-up or pull-down resistor connected to the Mode C pin. To minimize power consumption, or if the PF2 pin is to be used as an output in the DSP application, a weak pull-up or pull-down, on the order of 10 k, can be used. This value should be sufficient to pull the pin to the desired level and still allow the pin to operate as a programmable flag output without undue strain on the processor's output driver. For minimum power consumption during power-down, reconfigure PF2 to be an input, as the pull-up or pull-down will hold the pin in a known state, and will not switch. Active Configuration Active Configuration involves the use of a three-statable external driver connected to the Mode C pin. A driver's output enable should be connected to the DSP's RESET signal such that it only drives the PF2 pin when RESET is active (low). When RESET is deasserted, the driver should three-state, thus allowing full use of the PF2 pin as either an input or output. To minimize power consumption during power-down, configure the programmable flag as an output when connected to a threestated buffer. This ensures that the pin will be held at a constant level, and will not oscillate should the three-state driver's level hover around the logic switching point. Table II. Modes of Operation MODE D MODE C MODE B MODE A Booting Method X 0 0 0 BDMA feature is used to load the first 32 program memory words from the byte memory space. Program execution is held off until all 32 words have been loaded. Chip is configured in Full Memory Mode.1 X 0 1 0 No automatic boot operations occur. Program execution starts at external memory location 0. Chip is configured in Full Memory Mode. BDMA can still be used, but the processor does not automatically use or wait for these operations. 0 1 0 0 BDMA feature is used to load the first 32 program memory words from the byte memory space. Program execution is held off until all 32 words have been loaded. Chip is configured in Host Mode. IACK has active pull-down. (REQUIRES ADDITIONAL HARDWARE). 0 1 0 1 IDMA feature is used to load any internal memory as desired. Program execution is held off until internal program memory location 0 is written to. Chip is configured in Host Mode. IACK has active pull-down.1 1 1 0 0 BDMA feature is used to load the first 32 program memory words from the byte memory space. Program execution is held off until all 32 words have been loaded. Chip is configured in Host Mode; IACK requires external pull down. (REQUIRES ADDITIONAL HARDWARE) 1 1 0 1 IDMA feature is used to load any internal memory as desired. Program execution is held off until internal program memory location 0 is written to. Chip is configured in Host Mode. IACK requires external pull-down.1 NOTE 1 Considered as standard operating settings. Using these configurations allows for easier design and better memory management. REV. 0 -11- ADSP-2188M IACK Configuration Program Memory Mode D = 0 and in host mode: IACK is an active, driven signal and cannot be "wire OR'd." Program Memory (Full Memory Mode) is a 24-bit-wide space for storing both instruction opcodes and data. The ADSP2188M has 48K words of Program Memory RAM on chip, and the capability of accessing up to two 8K external memory overlay spaces using the external data bus. Mode D = 1 and in host mode: IACK is an open drain and requires an external pull-down, but multiple IACK pins can be "wire OR'd" together. Program Memory (Host Mode) allows access to all internal memory. External overlay access is limited by a single external address line (A0). External program execution is not available in host mode due to a restricted data bus that is 16 bits wide only. MEMORY ARCHITECTURE The ADSP-2188M provides a variety of memory and peripheral interface options. The key functional groups are Program Memory, Data Memory, Byte Memory, and I/O. Refer to the following figures and tables for PM and DM memory allocations in the ADSP-2188M. PM (MODE B = 1)1 PM MODE B = 0 ALWAYS ACCESSIBLE AT ADDRESS 0x0000 - 0x1FFF RESERVED 0x2000 - 0x3FFF ACCESSIBLE WHEN PMOVLAY = 0 0x2000 - 0x3FFF ACCESSIBLE WHEN PMOVLAY = 0 RESERVED 0x2000 - 0x3FFF ACCESSIBLE WHEN PMOVLAY = 4 INTERNAL MEMORY 0x2000 - 0x3FFF INTERNAL MEMORY ACCESSIBLE WHEN PMOVLAY = 5 RESERVED ACCESSIBLE WHEN PMOVLAY = 6 ACCESSIBLE WHEN PMOVLAY = 7 PROGRAM MEMORY MODE B = 0 8K INTERNAL PMOVLAY = 0, 4, 5, 6, 7 OR 8K EXTERNAL PMOVLAY = 1, 2 0x0000 - 0x1FFF2 0x2000 - 0x3FFF RESERVED 0x2000 - 0x3FFF2 ACCESSIBLE WHEN PMOVLAY = 1 EXTERNAL MEMORY RESERVED 0x2000 - 0x3FFF ACCESSIBLE WHEN PMOVLAY = 0 0x2000 - 0x3FFF2 EXTERNAL MEMORY 0x0000 - 0x1FFF2 RESERVED NOTES 1WHEN MODE B = 1, PMOVLAY MUST BE SET TO 0 2SEE TABLE III FOR PMOVLAY BITS ACCESSIBLE WHEN PMOVLAY = 2 PROGRAM MEMORY MODE B = 1 ADDRESS 0x3FFF ADDRESS 0x3FFF 8K INTERNAL PMOVLAY = 0 0x2000 0x2000 0x1FFF 0x1FFF 8K INTERNAL 8K INTERNAL 0x0000 0x0000 Figure 4. Program Memory Table III. PMOVLAY Bits PMOVLAY Memory A13 A12:0 0, 4, 5, 6, 7 1 2 Internal External Overlay 1 External Overlay 2 Not Applicable 0 1 Not Applicable 13 LSBs of Address Between 0x2000 and 0x3FFF 13 LSBs of Address Between 0x2000 and 0x3FFF -12- REV. 0 ADSP-2188M DATA MEMORY DATA MEMORY ALWAYS ACCESSIBLE AT ADDRESS 0x2000 - 0x3FFF 0x3FFF 32 MEMORY MAPPED REGISTERS 0x3FE0 0x3FDF INTERNAL 8160 WORDS 0x0000 - 0x1FFF 0x2000 0x0000 - 0x1FFF ACCESSIBLE WHEN DMOVLAY = 0 0x0000 - 0x1FFF ACCESSIBLE WHEN DMOVLAY = 5 0x1FFF 8K INTERNAL DMOVLAY = 0, 4, 5, 6, 7, 8 OR 8K EXTERNAL DMOVLAY = 1, 2 0x0000 - 0x1FFF ACCESSIBLE WHEN DMOVLAY = 4 0x0000 0x0000 - 0x1FFF ACCESSIBLE WHEN DMOVLAY = 6 INTERNAL MEMORY ADDRESS 0x0000 - 0x1FFF ACCESSIBLE WHEN DMOVLAY = 7 0x0000 -0x1FFF ACCESSIBLE WHEN DMOVLAY = 8 0x0000 -0x1FFF ACCESSIBLE WHEN DMOVLAY = 1 EXTERNAL MEMORY ACCESSIBLE WHEN DMOVLAY = 2 Figure 5. Data Memory Map Table IV. DMOVLAY Bits DMOVLAY Memory A13 A12:0 0, 4, 5, 6, 7, 8 1 2 Internal External Overlay 1 External Overlay 2 Not Applicable 0 1 Not Applicable 13 LSBs of Address Between 0x2000 and 0x3FFF 13 LSBs of Address Between 0x2000 and 0x3FFF Data Memory Data Memory (Full Memory Mode) is a 16-bit-wide space used for the storage of data variables and for memory-mapped control registers. The ADSP-2188M has 56K words on Data Memory RAM on-chip. Part of this space is used by 32 memorymapped registers. Support also exists for up to two 8K external memory overlay spaces through the external data bus. All internal accesses complete in one cycle. Accesses to external memory are timed using the wait states specified by the DWAIT register and the wait state mode bit. PROGRAMMABLE FLAG AND COMPOSITE SELECT CONTROL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 BMWAIT 0 PFTYPE 0 = INPUT 1 = OUTPUT CMSSEL 0 = DISABLE CMS 1 = ENABLE CMS (WHERE BIT: 11-IOM, 10-BM, 9-DM, 8-PM) Figure 7. Programmable Flag and Composite Control Register Data Memory (Host Mode) allows access to all internal memory. External overlay access is limited by a single external address line (A0). SYSTEM CONTROL Memory Mapped Registers (New to the ADSP-2188M) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 The ADSP-2188M has three memory mapped registers that differ from other ADSP-21xx Family DSPs. The slight modifications to these registers (Wait State Control, Programmable Flag and Composite Select Control, and System Control) provide the ADSP-2188M's wait state and BMS control features. Default bit values at reset are shown; if no value is shown, the bit is undefined at reset. Reserved bits are shown on a grey field. These bits should always be written with zeros. 0 0 0 0 0 0 0 0 1 1 1 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DWAIT 1 1 IOWAIT3 IOWAIT2 IOWAIT1 0 0 0 0 RESERVED SET TO 0 1 RESERVED, ALWAYS SET TO 0 SPORT0 ENABLE 0 = DISABLE 1 = ENABLE SPORT1 ENABLE 0 = DISABLE 1 = ENABLE DM(0x3FFF) PWAIT PROGRAM MEMORY WAIT STATES DISABLE BMS 0 = ENABLE BMS 1 = DISABLE BMS, EXCEPT WHEN MEMORY STROBES ARE THREE-STATED SPORT1 CONFIGURE 0 = FI, FO, IRQ0, IRQ1, SCLK 1 = SPORT1 WAITSTATE CONTROL 15 14 13 12 11 10 DM(0x3FE6) DM(0x3FFE) NOTE: RESERVED BITS ARE SHOWN ON A GRAY FIELD. THESE BITS SHOULD ALWAYS BE WRITTEN WITH ZEROS. IOWAIT0 Figure 8. System Control Register WAIT STATE MODE SELECT 0 = NORMAL MODE (PWAIT, DWAIT, IOWAIT0-3 = N WAIT STATES, RANGING FROM 0 TO 7) 1 = 2N + 1 MODE (PWAIT, DWAIT, IOWAIT0-3 = 2N + 1 WAIT STATES, RANGING FROM 0 TO 15) Figure 6. Wait State Control Register REV. 0 -13- ADSP-2188M I/O Space (Full Memory Mode) The ADSP-2188M supports an additional external memory space called I/O space. This space is designed to support simple connections to peripherals (such as data converters and external registers) or to bus interface ASIC data registers. I/O space supports 2048 locations of 16-bit wide data. The lower eleven bits of the external address bus are used; the upper three bits are undefined. Two instructions were added to the core ADSP-2100 Family instruction set to read from and write to I/O memory space. The I/O space also has four dedicated three-bit wait state registers, IOWAIT0-3, which in combination with the wait state mode bit, specify up to 15 wait states to be automatically generated for each of four regions. The wait states act on address ranges as shown in Table V. The byte memory space on the ADSP-2188M supports read and write operations as well as four different data formats. The byte memory uses data bits 15:8 for data. The byte memory uses data bits 23:16 and address bits 13:0 to create a 22-bit address. This allows up to a 4 meg x 8 (32 megabit) ROM or RAM to be used without glue logic. All byte memory accesses are timed by the BMWAIT register and the wait state mode bit. Byte Memory DMA (BDMA, Full Memory Mode) The byte memory DMA controller allows loading and storing of program instructions and data using the byte memory space. The BDMA circuit is able to access the byte memory space while the processor is operating normally and steals only one DSP cycle per 8-, 16- or 24-bit word transferred. BDMA CONTROL Table V. Wait States Address Range Wait State Register 0x000-0x1FF 0x200-0x3FF 0x400-0x5FF 0x600-0x7FF IOWAIT0 and Wait State Mode Select Bit IOWAIT1 and Wait State Mode Select Bit IOWAIT2 and Wait State Mode Select Bit IOWAIT3 and Wait State Mode Select Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 BMPAGE DM (0x3FE3) BTYPE BDIR 0 = LOAD FROM BM 1 = STORE TO BM BCR 0 = RUN DURING BDMA 1 = HALT DURING BDMA BDMA OVERLAY BITS Figure 9. BDMA Control Register Composite Memory Select (CMS) The ADSP-2188M has a programmable memory select signal that is useful for generating memory select signals for memories mapped to more than one space. The CMS signal is generated to have the same timing as each of the individual memory select signals (PMS, DMS, BMS, IOMS) but can combine their functionality. The BDMA circuit supports four different data formats that are selected by the BTYPE register field. The appropriate number of 8-bit accesses are done from the byte memory space to build the word size selected. Table VI shows the data formats supported by the BDMA circuit. Table VI. Data Formats Each bit in the CMSSEL register, when set, causes the CMS signal to be asserted when the selected memory select is asserted. For example, to use a 32K word memory to act as both program and data memory, set the PMS and DMS bits in the CMSSEL register and use the CMS pin to drive the chip select of the memory, and use either DMS or PMS as the additional address bit. The CMS pin functions like the other memory select signals with the same timing and bus request logic. A 1 in the enable bit causes the assertion of the CMS signal at the same time as the selected memory select signal. All enable bits default to 1 at reset, except the BMS bit. Byte Memory Select (BMS) The ADSP-2188M's BMS disable feature combined with the CMS pin allows use of multiple memories in the byte memory space. For example, an EPROM could be attached to the BMS select, and an SRAM could be connected to CMS. Because at reset BMS is enabled, the EPROM would be used for booting. After booting, software could disable BMS and set the CMS signal to respond to BMS, enabling the SRAM. BTYPE Internal Memory Space Word Size Alignment 00 01 10 11 Program Memory Data Memory Data Memory Data Memory 24 16 8 8 Full Word Full Word MSBs LSBs Unused bits in the 8-bit data memory formats are filled with 0s. The BIAD register field is used to specify the starting address for the on-chip memory involved with the transfer. The 14-bit BEAD register specifies the starting address for the external byte memory space. The 8-bit BMPAGE register specifies the starting page for the external byte memory space. The BDIR register field selects the direction of the transfer. Finally, the 14-bit BWCOUNT register specifies the number of DSP words to transfer and initiates the BDMA circuit transfers. BDMA accesses can cross page boundaries during sequential addressing. A BDMA interrupt is generated on the completion of the number of transfers specified by the BWCOUNT register. Byte Memory The byte memory space is a bidirectional, 8-bit-wide, external memory space used to store programs and data. Byte memory is accessed using the BDMA feature. The byte memory space consists of 256 pages, each of which is 16K x 8. The BWCOUNT register is updated after each transfer so it can be used to check the status of the transfers. When it reaches zero, the transfers have finished and a BDMA interrupt is generated. The BMPAGE and BEAD registers must not be accessed by the DSP during BDMA operations. The source or destination of a BDMA transfer will always be on-chip program or data memory. -14- REV. 0 ADSP-2188M When the BWCOUNT register is written with a nonzero value the BDMA circuit starts executing byte memory accesses with wait states set by BMWAIT. These accesses continue until the count reaches zero. When enough accesses have occurred to create a destination word, it is transferred to or from on-chip memory. The transfer takes one DSP cycle. DSP accesses to external memory have priority over BDMA byte memory accesses. The BDMA Context Reset bit (BCR) controls whether the processor is held off while the BDMA accesses are occurring. Setting the BCR bit to 0 allows the processor to continue operations. Setting the BCR bit to 1 causes the processor to stop execution while the BDMA accesses are occurring, to clear the context of the processor, and start execution at address 0 when the BDMA accesses have completed. The BDMA overlay bits specify the OVLAY memory blocks to be accessed for internal memory. The BMWAIT field, which has 4 bits on ADSP-2188M, allows selection up to 15 wait states for BDMA transfers. Internal Memory DMA Port (IDMA Port; Host Memory Mode) The IDMA Port provides an efficient means of communication between a host system and the ADSP-2188M. The port is used to access the on-chip program memory and data memory of the DSP with only one DSP cycle per word overhead. The IDMA port cannot, however, be used to write to the DSP's memorymapped control registers. A typical IDMA transfer process is described as follows: 1. Host starts IDMA transfer 2. Host checks IACK control line to see if the DSP is busy 3. Host uses IS and IAL control lines to latch either the DMA starting address (IDMAA) or the PM/DM OVLAY selection into the DSP's IDMA control registers. If Bit 15 = 1, the value of bits 7:0 represent the IDMA overlay: bits 14:8 must be set to 0. If Bit 15 = 0, the value of Bits 13:0 represent the starting address of internal memory to be accessed and Bit 14 reflects PM or DM for access. IDMA Port access occurs in two phases. The first is the IDMA Address Latch cycle. When the acknowledge is asserted, a 14-bit address and 1-bit destination type can be driven onto the bus by an external device. The address specifies an on-chip memory location, the destination type specifies whether it is a DM or PM access. The falling edge of the IDMA address latch signal (IAL) or the missing edge of the IDMA select signal (IS) latches this value into the IDMAA register. Once the address is stored, data can be read from, or written to, the ADSP-2188M's on-chip memory. Asserting the select line (IS) and the appropriate read or write line (IRD and IWR respectively) signals the ADSP-2188M that a particular transaction is required. In either case, there is a one-processor-cycle delay for synchronization. The memory access consumes one additional processor cycle. Once an access has occurred, the latched address is automatically incremented, and another access can occur. Through the IDMAA register, the DSP can also specify the starting address and data format for DMA operation. Asserting the IDMA port select (IS) and address latch enable (IAL) directs the ADSP-2188M to write the address onto the IAD0-14 bus into the IDMA Control Register. If Bit 15 is set to 0, IDMA latches the address. If Bit 15 is set to 1, IDMA latches into the OVLAY register. This register, shown below, is memory mapped at address DM (0x3FE0). Note that the latched address (IDMAA) cannot be read back by the host. When Bit 14 in 0x3FE7 is set to 1, timing in Figure 31 applies for short reads. When Bit 14 in 0x3FE7 is set to zero, short reads use the timing shown in Figure 32. Refer to the following figures for more information on IDMA and DMA memory maps. IDMA OVERLAY 15 14 13 12 11 10 0 0 4. Host uses IS and IRD (or IWR) to read (or write) DSP internal memory (PM or DM). 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 RESERVED SET TO 0 IDDMOVLAY RESERVED SET TO 0 SHORT READ ONLY 0 = ENABLE 1 = DISABLE DM (0x3FE7) IDPMOVLAY IDMA CONTROL (U = UNDEFINED AT RESET) 5. Host checks IACK line to see if the DSP has completed the previous IDMA operation. 15 14 13 12 11 10 0 6. Host ends IDMA transfer. U U U U U 9 8 7 6 5 4 3 2 1 0 U U U U U U U U U U DM (0x3FE0) IDMAA ADDRESS The IDMA port has a 16-bit multiplexed address and data bus and supports 24-bit program memory. The IDMA port is completely asynchronous and can be written while the ADSP-2188M is operating at full speed. RESERVED SET TO 0 IDMAD DESTINATION MEMORY TYPE 0 = PM 1 = DM NOTE: RESERVED BITS ARE SHOWN ON A GRAY FIELD. THESE BITS SHOULD ALWAYS BE WRITTEN WITH ZEROS. Figure 10. IDMA Control/OVLAY Registers The DSP memory address is latched and then automatically incremented after each IDMA transaction. An external device can therefore access a block of sequentially addressed memory by specifying only the starting address of the block. This increases throughput as the address does not have to be sent for each memory access. REV. 0 0 -15- ADSP-2188M DMA PROGRAM MEMORY OVLAY DMA DATA MEMORY OVLAY ALWAYS ACCESSIBLE AT ADDRESS 0x0000 - 0x1FFF ALWAYS ACCESSIBLE AT ADDRESS 0x2000 - 0x3FFF 0x2000 - 0x3FFF 0x0000 - 0x1FFF 0x2000 - 0x3FFF ACCESSIBLE WHEN PMOVLAY = 0 0x2000 - 0x3FFF ACCESSIBLE WHEN PMOVLAY = 4 ACCESSIBLE WHEN PMOVLAY = 5 ACCESSIBLE WHEN PMOVLAY = 6 0x0000 - 0x1FFF ACCESSIBLE WHEN DMOVLAY = 0 0x0000 - 0x1FFF ACCESSIBLE WHEN DMOVLAY = 4 0x2000 - 0x3FFF ACCESSIBLE WHEN DMOVLAY = 5 0x2000 - 0x3FFF 0x0000 - 0x1FFF ACCESSIBLE WHEN DMOVLAY = 6 ACCESSIBLE WHEN PMOVLAY = 7 0x0000 - 0x1FFF ACCESSIBLE WHEN DMOVLAY = 7 0x0000 - 0x1FFF ACCESSIBLE WHEN DMOVLAY = 8 NOTE: IDMA AND BDMA HAVE SEPARATE DMA CONTROL REGISTERS. Figure 11. Direct Memory Access--PM and DM Memory Maps Bootstrap Loading (Booting) Bus Request and Bus Grant The ADSP-2188M has two mechanisms to allow automatic loading of the internal program memory after reset. The method for booting is controlled by the Mode A, B, and C configuration bits. The ADSP-2188M can relinquish control of the data and address buses to an external device. When the external device requires access to memory, it asserts the bus request (BR) signal. If the ADSP-2188M is not performing an external memory access, it responds to the active BR input in the following processor cycle by: When the MODE pins specify BDMA booting, the ADSP-2188M initiates a BDMA boot sequence when reset is released. The BDMA interface is set up during reset to the following defaults when BDMA booting is specified: the BDIR, BMPAGE, BIAD, and BEAD registers are set to 0, the BTYPE register is set to 0 to specify program memory 24-bit words, and the BWCOUNT register is set to 32. This causes 32 words of on-chip program memory to be loaded from byte memory. These 32 words are used to set up the BDMA to load in the remaining program code. The BCR bit is also set to 1, which causes program execution to be held off until all 32 words are loaded into on-chip program memory. Execution then begins at address 0. * Asserting the bus grant (BG) signal, and * Halting program execution. If Go Mode is enabled, the ADSP-2188M will not halt program execution until it encounters an instruction that requires an external memory access. The ADSP-2100 Family development software (Revision 5.02 and later) fully supports the BDMA booting feature and can generate byte memory space compatible boot code. The IDLE instruction can also be used to allow the processor to hold off execution while booting continues through the BDMA interface. For BDMA accesses while in Host Mode, the addresses to boot memory must be constructed externally to the ADSP-2188M. The only memory address bit provided by the processor is A0. IDMA Port Booting The ADSP-2188M can also boot programs through its Internal DMA port. If Mode C = 1, Mode B = 0, and Mode A = 1, the ADSP-2188M boots from the IDMA port. IDMA feature can load as much on-chip memory as desired. Program execution is held off until on-chip program memory location 0 is written to. * Three-stating the data and address buses and the PMS, DMS, BMS, CMS, IOMS, RD, WR output drivers, If the ADSP-2188M is performing an external memory access when the external device asserts the BR signal, it will not threestate the memory interfaces nor assert the BG signal until the processor cycle after the access completes. The instruction does not need to be completed when the bus is granted. If a single instruction requires two external memory accesses, the bus will be granted between the two accesses. When the BR signal is released, the processor releases the BG signal, re-enables the output drivers, and continues program execution from the point at which it stopped. The bus request feature operates at all times, including when the processor is booting and when RESET is active. The BGH pin is asserted when the ADSP-2188M requires the external bus for a memory or BDMA access, but is stopped. The other device can release the bus by deasserting bus request. Once the bus is released, the ADSP-2188M deasserts BG and BGH and executes the external memory access. Flag I/O Pins The ADSP-2188M has eight general purpose programmable input/output flag pins. They are controlled by two memory mapped registers. The PFTYPE register determines the direction, 1 = output and 0 = input. The PFDATA register is used to read and write the values on the pins. Data being read from a pin configured as an input is synchronized to the ADSP-2188M's clock. Bits that are programmed as outputs will read the value being output. The PF pins default to input during reset. -16- REV. 0 ADSP-2188M In addition to the programmable flags, the ADSP-2188M has five fixed-mode flags, FI, FO, FL0, FL1, and FL2. FL0-FL2 are dedicated output flags. FI and FO are available as an alternate configuration of SPORT1. ERESET RESET ADSP-2188M Note: Pins PF0, PF1, PF2, and PF3 are also used for device configuration during reset. 1k MODE A/PFO Instruction Set Description The ADSP-2188M assembly language instruction set has an algebraic syntax that was designed for ease of coding and readability. The assembly language, which takes full advantage of the processor's unique architecture, offers the following benefits: * The algebraic syntax eliminates the need to remember cryptic assembler mnemonics. For example, a typical arithmetic add instruction, such as AR = AX0 + AY0, resembles a simple equation. * Every instruction assembles into a single, 24-bit word that can execute in a single instruction cycle. * The syntax is a superset ADSP-2100 Family assembly language and is completely source and object code compatible with other family members. Programs may need to be relocated to utilize on-chip memory and conform to the ADSP-2188M's interrupt vector and reset vector map. * Sixteen condition codes are available. For conditional jump, call, return, or arithmetic instructions, the condition can be checked and the operation executed in the same instruction cycle. * Multifunction instructions allow parallel execution of an arithmetic instruction with up to two fetches or one write to processor memory space during a single instruction cycle. DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM The ADSP-2188M has on-chip emulation support and an ICE-Port, a special set of pins that interface to the EZ-ICE. These features allow in-circuit emulation without replacing the target system processor by using only a 14-pin connection from the target system to the EZ-ICE. Target systems must have a 14-pin connector to accept the EZ-ICE's in-circuit probe, a 14-pin plug. PROGRAMMABLE I/O Figure 12. Mode A Pin/EZ-ICE Circuit See the ADSP-2100 Family EZ-Tools data sheet for complete information on ICE products. The ICE-Port interface consists of the following ADSP-2188M pins: EBR, EINT, EE, EBG, ECLK, ERESET, ELIN, EMS, and ELOUT These ADSP-2188M pins must be connected only to the EZ-ICE connector in the target system. These pins have no function except during emulation, and do not require pull-up or pull-down resistors. The traces for these signals between the ADSP-2188M and the connector must be kept as short as possible, no longer than 3 inches. The following pins are also used by the EZ-ICE: BR, BG, RESET, and GND. The EZ-ICE uses the EE (emulator enable) signal to take control of the ADSP-2185M in the target system. This causes the processor to use its ERESET, EBR, and EBG pins instead of the RESET, BR, and BG pins. The BG output is three-stated. These signals do not need to be jumper-isolated in your system. The EZ-ICE connects to your target system via a ribbon cable and a 14-pin female plug. The female plug is plugged onto the 14-pin connector (a pin strip header) on the target board. Target Board Connector for EZ-ICE Probe The EZ-ICE connector (a standard pin strip header) is shown in Figure 13. You must add this connector to your target board design if you intend to use the EZ-ICE. Be sure to allow enough room in your system to fit the EZ-ICE probe onto the 14-pin connector. Issuing the chip reset command during emulation causes the DSP to perform a full chip reset, including a reset of its memory mode. Therefore, it is vital that the mode pins are set correctly PRIOR to issuing a chip reset command from the emulator user interface. If a passive method of maintaining mode information is being used (as discussed in Setting Memory Modes), it does not matter that the mode information is latched by an emulator reset. However, if the RESET pin is being used as a method of setting the value of the mode pins, the effects of an emulator reset must be taken into consideration. 2 3 4 5 6 7 8 9 10 11 12 13 14 BG BR EBG EBR KEY (NO PIN) EINT ELIN ELOUT ECLK EMS EE One method of ensuring that the values located on the mode pins are those desired is to construct a circuit like the one shown in Figure 12. This circuit forces the value located on the Mode A pin to logic high; regardless of whether it is latched via the RESET or ERESET pin. REV. 0 1 GND RESET ERESET TOP VIEW Figure 13. Target Board Connector for EZ-ICE -17- ADSP-2188M The 14-pin, 2-row pin strip header is keyed at the Pin 7 location--you must remove Pin 7 from the header. The pins must be 0.025 inch square and at least 0.20 inch in length. Pin spacing should be 0.1 x 0.1 inches. The pin strip header must have at least 0.15 inch clearance on all sides to accept the EZ- ICE probe plug. Pin strip headers are available from vendors such as 3M, McKenzie, and Samtec. Restriction: All memory strobe signals on the ADSP-2188M (RD, WR, PMS, DMS, BMS, CMS, and IOMS) used in your target system must have 10 k pull-up resistors connected when the EZ-ICE is being used. The pull-up resistors are necessary because there are no internal pull-ups to guarantee their state during prolonged three-state conditions resulting from typical EZ-ICE debugging sessions. These resistors may be removed at your option when the EZ-ICE is not being used. Target Memory Interface Target System Interface Signals For your target system to be compatible with the EZ-ICE emulator, it must comply with the memory interface guidelines listed below. When the EZ-ICE board is installed, the performance on some system signals change. Design your system to be compatible with the following system interface signal changes introduced by the EZ-ICE board: PM, DM, BM, IOM, AND CM * EZ-ICE emulation introduces an 8 ns propagation delay between your target circuitry and the DSP on the RESET signal. Design your Program Memory (PM), Data Memory (DM), Byte Memory (BM), I/O Memory (IOM), and Composite Memory (CM) external interfaces to comply with worst case device timing requirements and switching characteristics as specified in this data sheet. The performance of the EZ- ICE may approach published worst case specification for some memory access timing requirements and switching characteristics. Note: If your target does not meet the worst-case chip specification for memory access parameters, you may not be able to emulate your circuitry at the desired CLKIN frequency. Depending on the severity of the specification violation, you may have trouble manufacturing your system as DSP components statistically vary in switching characteristic and timing requirements within published limits. * EZ-ICE emulation introduces an 8 ns propagation delay between your target circuitry and the DSP on the BR signal. * EZ-ICE emulation ignores RESET and BR when singlestepping. * EZ-ICE emulation ignores RESET and BR when in Emulator Space (DSP halted). * EZ-ICE emulation ignores the state of target BR in certain modes. As a result, the target system may take control of the DSP's external memory bus only if bus grant (BG) is asserted by the EZ- ICE board's DSP. -18- REV. 0 ADSP-2188M SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS K Grade B Grade Parameter Min Max Min Max Unit VDDINT VDDEXT VINPUT1 TAMB 2.61 2.61 VIL = -0.3 0 2.89 3.6 VIH = +3.6 +70 2.25 2.25 VIL = -0.3 -40 2.75 3.6 VIH = +3.6 +85 V V V C NOTES 1 The ADSP-2188M is 3.3 V tolerant (always accepts up to 3.6 V max V IH), but voltage compliance (on outputs, V OH) depends on the input VDDEXT; because VOH (max) VDDEXT (max). This applies to bidirectional pins (D0-D23, RFS0, RFS1, SCLK0, SCLK1, TFS 0, TFS1, A1-A13, PF0-PF7) and input only pins (CLKIN, RESET, BR, DR0, DR1, PWD). Specifications subject to change without notice. ELECTRICAL CHARACTERISTICS Parameter VIH VIH VIL VOH Hi-Level Input Voltage1, 2 Hi-Level CLKIN Voltage Lo-Level Input Voltage1, 3 Hi-Level Output Voltage1, 4, 5 VOL IIH IIL IOZH IOZL IDD IDD IDD IDD IDD Lo-Level Output Voltage1, 4, 5 Hi-Level Input Current3 Lo-Level Input Current3 Three-State Leakage Current7 Three-State Leakage Current7 Supply Current (Idle)9 Supply Current (Idle)9 Supply Current (Dynamic)10 Supply Current (Dynamic)10 Supply Current (Power-Down)12 CI CO Input Pin Capacitance3, 6 Output Pin Capacitance6, 7, 12, 13 Test Conditions Min @ VDDINT = max @ VDDINT = max @ VDDINT = min @ VDDEXT = min, IOH = -0.5 mA @ VDDEXT = 3.0 V, IOH = -0.5 mA @ VDDEXT = min, IOH = -100 A6 @ VDDEXT = min, IOL = 2 mA @ VDDINT = max, VIN = 3.6 V @ VDDINT = max, VIN = 0 V @ VDDEXT = max, VIN = 3.6 V8 @ VDDEXT = max, VIN = 0 V8 @ VDDINT = 2.75, tCK = 15 ns @ VDDINT = 2.75, tCK = 13.3 ns @ VDDINT = 2.75, tCK = 15 ns11, TAMB = 25C @ VDDINT = 2.75, tCK = 13.3 ns11, TAMB = 25C @ VDDINT = 2.75, TAMB = 25C in Lowest Power Mode @ VIN = 2.75 V, fIN = 1.0 MHz, TAMB = 25C @ VIN = 2.75 V, fIN = 1.0 MHz, TAMB = 25C 1.5 2.0 K/B Grades Typ Max Unit 0.4 10 10 10 10 V V V V V V V A A A A mA mA mA mA A 8 8 pF pF 0.7 2.0 2.4 VDDEXT - 0.3 9 10 44 42 100 NOTES 1 Bidirectional pins: D0-D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1-A13, PF0-PF7. 2 Input only pins: RESET, BR, DR0, DR1, PWD. 3 Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD. 4 Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2-0, BGH. 5 Although specified for TTL outputs, all ADSP-2188M outputs are CMOS-compatible and will drive to V DDEXT and GND, assuming no dc loads. 6 Guaranteed but not tested. 7 Three-statable pins: A0-A13, D0-D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0-PF7. 8 0 V on BR. 9 Idle refers to ADSP-2188M state of operation during execution of IDLE instruction. Deasserted pins are driven to either V DD or GND. 10 IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (Types 1, 4, 5, 12, 13, 14), 30% are Type 2 and Type 6, and 20% are idle instructions. 11 VIN = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section. 12 See Chapter 9 of the ADSP-2100 Family User's Manual for details. 13 Output pin capacitance is the capacitive load for any three-stated output pin. Specifications subject to change without notice. REV. 0 -19- ADSP-2188M ABSOLUTE MAXIMUM RATINGS 1 Parameter Internal Supply Voltage (VDDINT) External Supply Voltage (VDDEXT) Input Voltage2 Output Voltage Swing3 Operating Temperature Range Storage Temperature Range Lead Temperature (5 sec) LQFP Value Min Max -0.3 V -0.3 V -0.5 V -0.5 V -40C -65C +3.0 V +4.0 V +4.0 V VDDEXT + 0.5 V +85C +150C NOTES 1 Stresses greater than those listed may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Applies to Bidirectional pins (D0-D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1-A13, PF0-PF7) and Input only pins (CLKIN, RESET, BR, DR0, DR1, PWD). 3 Applies to Output pins (BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2-0, BGH). 280C ESD SENSITIVITY ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-2188M features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. TIMING SPECIFICATIONS Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, you cannot meaningfully add up parameters to derive longer times. Switching characteristics specify how the processor changes its signals. You have no control over this timing--circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics tell you what the processor will do in a given circumstance. You can also use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. Timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices. ESD SENSITIVE DEVICE MEMORY TIMING SPECIFICATIONS GENERAL NOTES TIMING NOTES WARNING! The table below shows common memory device specifications and the corresponding ADSP-2188M timing parameters, for your convenience. Memory Device Specification Timing Parameter Parameter Definition1 Address Setup to Write Start Address Setup to Write End Address Hold Time tASW Data Setup Time tDW tAW tWRA Data Hold Time tDH OE to Data Valid tRDD Address Access Time tAA A0-A13, xMS Setup before WR Low A0-A13, xMS Setup before WR Deasserted A0-A13, xMS Hold before WR Low Data Setup before WR High Data Hold after WR High RD Low to Data Valid A0-A13, xMS to Data Valid NOTE 1 xMS = PMS, DMS, BMS, CMS or IOMS. -20- REV. 0 ADSP-2188M * Each address and data pin has a 10 pF total load at the pin. FREQUENCY DEPENDENCY FOR TIMING SPECIFICATIONS tCK is defined as 0.5 tCKI. The ADSP-2188M uses an input clock with a frequency equal to half the instruction rate. For example, a 37.50 MHz input clock (which is equivalent to 26.6 ns) yields a 13.3 ns processor cycle (equivalent to 75 MHz). tCK values within the range of 0.5 tCKI period should be substituted for all relevant timing parameters to obtain the specification value. * The application operates at VDDEXT = 3.3 V and tCK = 30 ns. Total Power Dissipation = PINT + (C x VDDEXT2 x f ) PINT = internal power dissipation from Power vs. Frequency graph (Figure 15). (C x VDDEXT2 x f ) is calculated for each output: Example: tCKH = 0.5 tCK - 2 ns = 0.5 (15 ns) - 2 ns = 5.5 ns ENVIRONMENTAL CONDITIONS Rating Description Symbol Thermal Resistance CA (Case-to-Ambient) Thermal Resistance JA (Junction-to-Ambient) Thermal Resistance JC (Junction-to-Case) 1 LQFP Mini-BGA 48C/W 63.3C/W 50C/W 70.7C/W 2C/W 7.4C/W NOTE 1 Where the Ambient Temperature Rating (T AMB) is: TAMB = TCASE - (PD x CA) TCASE = Case Temperature in C PD = Power Dissipation in W Parameters # of Pins C pF VDDEXT2 f V MHz PD mW Address Data Output, WR RD CLKOUT, DMS 7 9 1 2 10 10 10 10 3.32 3.32 3.32 3.32 12.7 16.3 1.8 7.2 38.0 Total power dissipation for this example is PINT + 38.0 mW. Output Drive Currents Figure 14 shows typical I-V characteristics for the output drivers on the ADSP-2188M. The curves represent the current drive capability of the output drivers as a function of output voltage. 80 60 VDDEXT = 3.6V @ -40C SOURCE CURRENT - mA POWER DISSIPATION To determine total power dissipation in a specific application, the following equation should be applied for each output: C x VDD 2 x f C = load capacitance, f = output switching frequency. Example: In an application where external data memory is used and no other outputs are active, power dissipation is calculated as follows: 40 VOH VDDEXT = 3.3V @ +25C 20 VDDEXT = 2.5V @ +85C 0 -20 VDDEXT = 3.6V @ -40C VOL -40 VDDEXT = 2.5V @ +85C VDDEXT = 3.3V @ +25C -60 Assumptions: -80 * External data memory is accessed every cycle with 50% of the address pins switching. 0 0.5 1.0 1.5 2.0 2.5 SOURCE VOLTAGE - V 3.0 3.5 4.0 Figure 14. Typical Output Driver Characteristics * External data memory writes occur every other cycle with 50% of the data pins switching. REV. 0 16.67 16.67 16.67 33.3 -21- ADSP-2188M Capacitive Loading Figure 16 and Figure 17 show the capacitive loading characteristics of the ADSP-2188M. 145mW VD T DIN V DD INT V DDIN 55 T 129mW .9V =2 = 30 5V 2.7 T = 85C VDD = 0V TO 2.0V 111mW 25 RISE TIME (0.4V-2.4V) - ns POWER (PINT) - mW POWER, INTERNAL1, 2, 3 150 145 140 135 130 125 120 115 110 105 100 101mW 95 90 85 88mW 80 75 78mW 70 45 50 6V = 2. 60 65 1/tCK - MHz 70 75 POWER, IDLE1, 2, 4 45 10 0 0 50 100 36mW 35 V DDINT 30 V DDINT 28mW 25 V DDINT = 2.9V 32mW V = 2.75 28mW 15 55 60 65 1/tCK - MHz 70 75 POWER, IDLE n MODES 2 40 35 32mW 30 25 IDLE 18mW 300 14 12 10 8 6 4 2 NOMINAL -2 -4 24mW 20 19mW 250 16 20mW 50 200 18 = 2.6V 24mW 20 150 CL - pF Figure 16. Typical Output Rise Time vs. Load Capacitance (at Maximum Ambient Operating Temperature) VALID OUTPUT DELAY OR HOLD - ns POWER (PIDLE) - mW 15 5 40 POWER (PIDLEn) - mW 20 -6 IDLE (16) IDLE (128) 21mW 0 50 100 150 200 250 CL - pF Figure 17. Typical Output Valid Delay or Hold vs. Load Capacitance, CL (at Maximum Ambient Operating Temperature) 19mW 15 10 50 75 55 60 65 70 1/tCK - MHz NOTES: VALID FOR ALL TEMPERATURE GRADES. 1 POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS. 2 TYPICAL POWER DISSIPATION AT 2.75V V DDINT AND 25C, EXCEPT WHERE SPECIFIED. 3I DD MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1, 4, 5, 12, 13, 14), 30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS. 4 IDLE REFERS TO STATE OF OPERATION DURING EXECUTION OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER VDD OR GND. Figure 15. Power vs. Frequency -22- REV. 0 ADSP-2188M TEST CONDITIONS Output Disable Time Output Enable Time Output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state. The output disable time (tDIS) is the difference of tMEASURED and tDECAY, as shown in the Output Enable/Disable diagram. The time is the interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0.5 V from the measured output high or low voltage. The decay time, tDECAY, is dependent on the capacitive load, CL, and the current load, iL, on the output pin. It can be approximated by the following equation: t DECAY = Output pins are considered to be enabled when they have made a transition from a high-impedance state to when they start driving. The output enable time (tENA) is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown Figure 19. If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. REFERENCE SIGNAL tMEASURED tENA VOH (MEASURED) C L x 0.5V iL tDIS VOH (MEASURED) VOH (MEASURED) - 0.5V 2.0V VOL (MEASURED) +0.5V 1.0V OUTPUT from which VOL (MEASURED) VOL (MEASURED) tDECAY tDIS = tMEASURED - tDECAY INPUT OUTPUT OUTPUT STARTS DRIVING OUTPUT STOPS DRIVING is calculated. If multiple pins (such as the data bus) are disabled, the measurement value is that of the last pin to stop driving. HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V. Figure 19. Output Enable/Disable 1.5V IOL 2.0V 1.5V 0.8V Figure 18. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable) TO OUTPUT PIN 1.5V 50pF IOH Figure 20. Equivalent Loading for AC Measurements (Including All Fixtures) REV. 0 -23- ADSP-2188M Parameter Min Max Unit Timing Requirements: CLKIN Period tCKI tCKIL CLKIN Width Low tCKIH CLKIN Width High 26.6 8 8 80 ns ns ns Switching Characteristics: tCKL CLKOUT Width Low tCKH CLKOUT Width High tCKOH CLKIN High to CLKOUT High 0.5tCK - 2 0.5tCK - 2 0 Control Signals Timing Requirements: tRSP RESET Width Low tMS Mode Setup before RESET High tMH Mode Hold after RESET High 5tCK1 2 5 Clock Signals and Reset 13 ns ns ns ns ns ns NOTE 1 Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal oscillator start-up time). tCKI tCKIH CLKIN tCKIL tCKOH tCKH CLKOUT tCKL PF(3:0)* tMS tMH RESET tRSP *PF3 IS MODE D, PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A Figure 21. Clock Signals -24- REV. 0 ADSP-2188M Parameter Min Max Unit Interrupts and Flags Timing Requirements: IRQx, FI, or PFx Setup before CLKOUT Low1, 2, 3, 4 tIFS tIFH IRQx, FI, or PFx Hold after CLKOUT High1, 2, 3, 4 0.25tCK + 10 0.25tCK Switching Characteristics: tFOH Flag Output Hold after CLKOUT Low5 tFOD Flag Output Delay from CLKOUT Low5 ns ns 0.5tCK - 5 0.5tCK + 4 ns ns NOTES 1 If IRQx and FI inputs meet t IFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on the following cycle. (Refer to "Interrupt Controller Operation" in the Program Control chapter of the ADSP-2100 Family User's Manual for further information on interrupt servicing.) 2 Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced. 3 IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQLE. 4 PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7. 5 Flag Outputs = PFx, FL0, FL1, FL2, FO. tFOD CLKOUT tFOH FLAG OUTPUTS tIFH IRQx FI PFx tIFS Figure 22. Interrupts and Flags REV. 0 -25- ADSP-2188M Parameter Min Max Unit Bus Request-Bus Grant Timing Requirements: BR Hold after CLKOUT High1 tBH tBS BR Setup before CLKOUT Low1 0.25tCK + 2 0.25tCK + 10 Switching Characteristics: tSD CLKOUT High to xMS, RD, WR Disable xMS, RD, WR Disable to BG Low tSDB tSE BG High to xMS, RD, WR Enable tSEC xMS, RD, WR Enable to CLKOUT High xMS, RD, WR Disable to BGH Low2 tSDBH tSEH BGH High to xMS, RD, WR Enable2 0 0 0.25tCK - 3 0 0 ns ns 0.25tCK + 8 ns ns ns ns ns ns NOTES xMS = PMS, DMS, CMS, IOMS, BMS. 1 BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on the following cycle. Refer to the ADSP-2100 Family User's Manual for BR/BG cycle relationships. 2 BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue. tBH CLKOUT BR tBS CLKOUT PMS, DMS BMS, RD WR BG BGH tSD tSEC tSDB tSE tSDBH tSEH Figure 23. Bus Request-Bus Grant -26- REV. 0 ADSP-2188M Parameter Min Max Unit 0.5tCK - 5 + w 0.75tCK - 6 + w ns ns ns Memory Read Timing Requirements: RD Low to Data Valid tRDD tAA A0-A13, xMS to Data Valid tRDH Data Hold from RD High 0 Switching Characteristics: tRP RD Pulsewidth tCRD CLKOUT High to RD Low tASR A0-A13, xMS Setup before RD Low A0-A13, xMS Hold after RD Deasserted tRDA tRWR RD High to RD or WR Low 0.5tCK - 3 + w 0.25tCK - 2 0.25tCK - 3 0.25tCK - 3 0.5tCK - 3 NOTES w = wait states x t CK. xMS = PMS, DMS, CMS, IOMS, BMS. CLKOUT A0-A13 DMS, PMS, BMS, IOMS, CMS tRDA RD tASR tRP tCRD tRWR D0-D23 tAA tRDD WR Figure 24. Memory Read REV. 0 -27- tRDH 0.25tCK + 4 ns ns ns ns ns ADSP-2188M Parameter Min Max Unit Memory Write Switching Characteristics: Data Setup before WR High tDW Data Hold after WR High tDH WR Pulsewidth tWP WR Low to Data Enabled tWDE A0-A13, xMS Setup before WR Low tASW Data Disable before WR or RD Low tDDR CLKOUT High to WR Low tCWR A0-A13, xMS, Setup before WR Deasserted tAW A0-A13, xMS Hold after WR Deasserted tWRA tWWR WR High to RD or WR Low 0.5tCK - 4 + w 0.25tCK - 1 0.5tCK - 3 + w 0 0.25tCK - 3 0.25tCK - 3 0.25tCK - 2 0.75tCK - 5 + w 0.25tCK - 1 0.5tCK - 3 0.25 tCK + 4 ns ns ns ns ns ns ns ns ns ns NOTES w = wait states x tCK. xMS = PMS, DMS, CMS, IOMS, BMS. CLKOUT A0-A13 DMS, PMS, BMS, CMS, IOMS tWRA WR tASW tWWR tWP tAW tDH tCWR tDDR D0-D23 tWDE tDW RD Figure 25. Memory Write -28- REV. 0 ADSP-2188M Serial Ports Parameter Min Max Unit Serial Ports Timing Requirements: tSCK SCLK Period tSCS DR/TFS/RFS Setup before SCLK Low DR/TFS/RFS Hold after SCLK Low tSCH tSCP SCLKIN Width 26.6 4 7 12 Switching Characteristics: tCC CLKOUT High to SCLKOUT SCLK High to DT Enable tSCDE tSCDV SCLK High to DT Valid tRH TFS/RFSOUT Hold after SCLK High TFS/RFSOUT Delay from SCLK High tRD tSCDH DT Hold after SCLK High tTDE TFS (Alt) to DT Enable TFS (Alt) to DT Valid tTDV tSCDD SCLK High to DT Disable tRDV RFS (Multichannel, Frame Delay Zero) to DT Valid CLKOUT tCC 0.25tCK 0 12 12 0 0 12 12 12 tCC tSCK tSCP tSCS tSCP tSCH DR TFSIN RFSIN tRD tRH RFSOUT TFSOUT tSCDD tSCDV tSCDH tSCDE DT tTDE tTDV TFSOUT ALTERNATE FRAME MODE tRDV RFSOUT TFSIN tTDE tTDV ALTERNATE FRAME MODE RFSIN MULTICHANNEL MODE, FRAME DELAY 0 (MFD = 0) tRDV Figure 26. Serial Ports REV. 0 0.25tCK + 6 0 SCLK MULTICHANNEL MODE, FRAME DELAY 0 (MFD = 0) ns ns ns ns -29- ns ns ns ns ns ns ns ns ns ns ADSP-2188M Parameter Min Max Unit IDMA Address Latch Timing Requirements: Duration of Address Latch1, 2 tIALP tIASU IAD15-0 Address Setup before Address Latch End2 tIAH IAD15-0 Address Hold after Address Latch End2 IACK Low before Start of Address Latch2, 3 tIKA tIALS Start of Write or Read after Address Latch End2, 3 tIALD Address Latch Start after Address Latch End1, 2 10 5 3 0 3 2 ns ns ns ns ns ns NOTES 1 Start of Address Latch = IS Low and IAL High. 2 End of Address Latch = IS High or IAL Low. 3 Start of Write or Read = IS Low and IWR Low or IRD Low. IACK tIKA tIALD IAL tIALP tIALP IS IAD15-0 tIASU tIAH tIASU tIAH tIALS IRD OR IWR Figure 27. IDMA Address Latch -30- REV. 0 ADSP-2188M Parameter Min Max Unit IDMA Write, Short Write Cycle Timing Requirements: IACK Low before Start of Write1 tIKW Duration of Write1, 2 tIWP tIDSU IAD15-0 Data Setup before End of Write2, 3, 4 IAD15-0 Data Hold after End of Write2, 3, 4 tIDH 0 10 3 2 Switching Characteristic: tIKHW Start of Write to IACK High 10 NOTES 1 Start of Write = IS Low and IWR Low. 2 End of Write = IS High or IWR High. 3 If Write Pulse ends before IACK Low, use specifications t IDSU, tIDH. 4 If Write Pulse ends after IACK Low, use specifications t IKSU, tIKH. tIKW IACK tIKHW IS tIWP IWR tIDSU IAD15-0 tIDH DATA Figure 28. IDMA Write, Short Write Cycle REV. 0 ns ns ns ns -31- ns ADSP-2188M Parameter Min Max Unit IDMA Write, Long Write Cycle Timing Requirements: IACK Low before Start of Write1 tIKW IAD15-0 Data Setup before End of Write2, 3, 4 tIKSU IAD15-0 Data Hold after End of Write2, 3, 4 tIKH 0 0.5tCK + 5 0 Switching Characteristics: tIKLW Start of Write to IACK Low4 tIKHW Start of Write to IACK High ns ns ns 1.5tCK 10 ns ns NOTES 1 Start of Write = IS Low and IWR Low. 2 If Write Pulse ends before IACK Low, use specifications t IDSU, tIDH. 3 If Write Pulse ends after IACK Low, use specifications t IKSU, tIKH. 4 This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User's Manual. tIKW IACK tIKHW tIKLW IS IWR tIKSU tIKH DATA IAD15-0 Figure 29. IDMA Write, Long Write Cycle -32- REV. 0 ADSP-2188M Parameter Min Max Unit IDMA Read, Long Read Cycle Timing Requirements: IACK Low before Start of Read1 tIKR tIRK End of read after IACK Low2 0 2 Switching Characteristics: tIKHR IACK High after Start of Read1 IAD15-0 Data Setup before IACK Low tIKDS tIKDH IAD15-0 Data Hold after End of Read2 tIKDD IAD15-0 Data Disabled after End of Read2 IAD15-0 Previous Data Enabled after Start of Read tIRDE tIRDV IAD15-0 Previous Data Valid after Start of Read tIRDH1 IAD15-0 Previous Data Hold after Start of Read (DM/PM1)3 tIRDH2 IAD15-0 Previous Data Hold after Start of Read (PM2)4 ns ns 10 0.5tCK - 2 0 10 0 11 2tCK - 5 tCK - 5 NOTES 1 Start of Read = IS Low and IRD Low. 2 End of Read = IS High or IRD High. 3 DM read or first half of PM read. 4 Second half of PM read. IACK tIKHR tIKR IS tIRK IRD tIKDH tIKDS tIRDE PREVIOUS DATA IAD15-0 READ DATA tIRDV tIKDD tIRDH1 or tIRDH2 Figure 30. IDMA Read, Long Read Cycle REV. 0 -33- ns ns ns ns ns ns ns ns ADSP-2188M Parameter Min Max Unit 0 10 10 2tCK - 5 tCK - 5 ns ns ns IDMA Read, Short Read Cycle1, 2 Timing Requirements: tIKR IACK Low before Start of Read3 Duration of Read (DM/PM1)4 tIRP1 Duration of Read (PM2)5 tIRP2 Switching Characteristics: tIKHR IACK High after Start of Read3 tIKDH IAD15-0 Data Hold after End of Read6 IAD15-0 Data Disabled after End of Read6 tIKDD tIRDE IAD15-0 Previous Data Enabled after Start of Read tIRDV IAD15-0 Previous Data Valid after Start of Read 10 0 10 0 10 ns ns ns ns ns NOTES 1 Short Read Only must be disabled in the IDMA Overlay memory mapped register. 2 Consider using the Short Read Only mode, instead, because Short Read mode is not applicable at high clock frequencies. 3 Start of Read = IS Low and IRD Low. 4 DM Read or first half of PM Read. 5 Second half of PM Read. 6 End of Read = IS High or IRD High. IACK tIKR tIKHR IS tIRP IRD tIKDH tIRDE PREVIOUS DATA IAD15-0 tIRDV tIKDD Figure 31. IDMA Read, Short Read Cycle -34- REV. 0 ADSP-2188M Parameter Min IDMA Read, Short Read Cycle in Short Read Only Mode Max Unit 1 Timing Requirements: tIKR IACK Low before Start of Read2 Duration of Read3 tIRP 0 10 Switching Characteristics: tIKHR IACK High after Start of Read2 tIKDH IAD15-0 Previous Data Hold after End of Read3 IAD15-0 Previous Data Disabled after End of Read3 tIKDD tIRDE IAD15-0 Previous Data Enabled after Start of Read tIRDV IAD15-0 Previous Data Valid after Start of Read ns ns 10 0 10 0 10 ns ns ns ns ns NOTES 1 Short Read Only is enabled by setting Bit 14 of the IDMA Overlay Register to 1 (0x3FE7). Short Read Only can be enabled by the processor core writing to the register or by an external host writing to the register. Disabled by default. 2 Start of Read = IS Low and IRD Low. Previous data remains until end of read. 3 End of Read = IS High or IRD High. IACK tIKR tIKHR IS tIRP IRD tIKDH tIRDE PREVIOUS DATA IAD15-0 tIRDV tIKDD Figure 32. IDMA Read, Short Read Only Cycle REV. 0 -35- ADSP-2188M A4/IAD3 A5/IAD4 1 2 78 D18 77 D17 76 D16 80 GND 79 D19 82 D21 81 D20 84 D23 83 D22 86 FL1 85 FL2 87 FL0 89 PF2 [MODE C] 88 PF3 [MODE D] 91 PWD 90 VDDEXT 92 GND 94 PF0 [MODE A] 93 PF1 [MODE B] 95 BGH 96 PWDACK 98 A1/IAD0 97 A0 100 A3/IAD2 99 A2/IAD1 100-LEAD LQFP PIN CONFIGURATION 75 D15 74 D14 PIN 1 IDENTIFIER GND 3 A6/IAD5 4 73 D13 72 D12 A7/IAD6 5 71 GND A8/IAD7 6 A9/IAD8 7 70 D11 69 D10 A10/IAD9 8 68 D9 67 VDDEXT A11/IAD10 9 A12/IAD11 10 66 GND A13/IAD12 11 GND 12 65 D8 64 D7/IWR ADSP-2188M CLKIN 13 63 D6/IRD TOP VIEW (Not to Scale) XTAL 14 VDDEXT 15 62 D5/IAL 61 D4/IS CLKOUT 16 GND 17 VDDINT 18 60 GND 59 VDD INT 58 D3/IACK WR 19 RD 20 57 D2/IAD15 BMS 21 DMS 22 55 D0/IAD13 54 BG PMS 23 53 EBG 52 BR 56 D1/IAD14 IOMS 24 CMS 25 -36- EINT 50 ELIN 49 ELOUT 48 EMS 45 EE 46 ECLK 47 RESET 44 ERESET 43 GND 41 SCLK1 42 DR1/FI 40 RFS1/IRQ0 39 DT1/FO 37 TFS1/IRQ1 38 DR0 34 SCLK0 35 VDDEXT 36 RFS0 33 TFS0 32 IRQ2+PF7 30 DT0 31 GND 28 IRQL1+PF6 29 IRQE+PF4 26 IRQL0+PF5 27 51 EBR REV. 0 ADSP-2188M The LQFP package pinout is shown in the table below. Pin names in bold text replace the plain text named functions when Mode C = 1. A + sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET. The multiplexed pins DT1/FO, TFS1/IRQ1, RFS1/IRQ0, and DR1/FI, are mode selectable by setting Bit 10 (SPORT1 configure) of the System Control Register. If Bit 10 = 1, these pins have serial port functionality. If Bit 10 = 0, these pins are the external interrupt and flag pins. This bit is set to 1 by default upon reset. LQFP Package Pinout Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 A4/IAD3 A5/IAD4 GND A6/IAD5 A7/IAD6 A8/IAD7 A9/IAD8 A10/IAD9 A11/IAD10 A12/IAD11 A13/IAD12 GND CLKIN XTAL VDDEXT CLKOUT GND VDDINT WR RD BMS DMS PMS IOMS CMS 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 IRQE + PF4 IRQL0 + PF5 GND IRQL1 + PF6 IRQ2 + PF7 DT0 TFS0 RFS0 DR0 SCLK0 VDDEXT DT1/FO TFS1/IRQ1 RFS1/IRQ0 DR1/FI GND SCLK1 ERESET RESET EMS EE ECLK ELOUT ELIN EINT 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 EBR BR EBG BG D0/IAD13 D1/IAD14 D2/IAD15 D3/IACK VDDINT GND D4/IS D5/IAL D6/IRD D7/IWR D8 GND VDDEXT D9 D10 D11 GND D12 D13 D14 D15 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 D16 D17 D18 D19 GND D20 D21 D22 D23 FL2 FL1 FL0 PF3 [MODE D] PF2 [MODE C] VDDEXT PWD GND PF1 [MODE B] PF0 [MODE A] BGH PWDACK A0 A1/IAD0 A2/IAD1 A3/IAD2 REV. 0 -37- ADSP-2188M 144-Ball Mini-BGA Package Pinout (Bottom View) 12 11 10 9 8 7 6 5 4 3 2 1 GND GND D22 NC NC NC GND NC A0 GND A1/IAD0 A2/IAD1 A D16 D17 D18 D20 D23 VDDEXT GND NC NC GND A3/IAD2 A4/IAD3 B D14 NC D15 D19 D21 VDDEXT PWD A7/IAD6 A5/IAD4 RD A6/IAD5 PWDACK C GND NC D12 D13 NC PF2 [MODE C] PF1 [MODE B] A9/IAD8 BGH NC WR NC D D10 GND VDDEXT GND GND PF3 [MODE D] FL2 PF0 [MODE A] FL0 A8/IAD7 VDDEXT VDDEXT E D9 NC D8 D11 D7/IWR NC NC FL1 A11/IAD10 A12/IAD11 NC A13/IAD12 F D4/IS NC NC D5/IAL D6/IRD NC NC NC A10/IAD9 GND NC XTAL G GND NC GND D3/IACK D2/IAD15 TFS0 DT0 VDDINT GND GND GND CLKIN H VDDINT VDDINT D1/IAD14 BG RFS1/IRQ0 D0/IAD13 SCLK0 VDDEXT VDDEXT NC VDDINT CLKOUT J EBG BR EBR ERESET SCLK1 TFS1/IRQ1 RFS0 DMS BMS NC NC NC K EINT ELOUT ELIN RESET GND DR0 PMS GND IOMS IRQL1 + PF6 NC IRQE + PF4 L ECLK EE EMS NC GND DR1/FI DT1/FO GND CMS NC IRQ2 + PF7 IRQL0 + PF5 M -38- REV. 0 ADSP-2188M The Mini-BGA package pinout is shown in the table below. Pin names in bold text replace the plain text named functions when Mode C = 1. A + sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET. The multiplexed pins DT1/FO, TFS1/IRQ1, RFS1/IRQ0, and DR1/FI, are mode selectable by setting Bit 10 (SPORT1 configure) of the System Control Register. If Bit 10 = 1, these pins have serial port functionality. If Bit 10 = 0, these pins are the external interrupt and flag pins. This bit is set to 1 by default upon reset. Mini-BGA Package Pinout Ball # Pin Name Ball # Pin Name Ball # Pin Name Ball # Pin Name A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A2/IAD1 A1/IAD0 GND A0 NC GND NC NC NC D22 GND GND D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 NC WR NC BGH A9/IAD8 PF1 [MODE B] PF2 [MODE C] NC D13 D12 NC GND G01 G02 G03 G04 G05 G06 G07 G08 G09 G10 G11 G12 XTAL NC GND A10/IAD9 NC NC NC D6/IRD D5/IAL NC NC D4/IS K01 K02 K03 K04 K05 K06 K07 K08 K09 K10 K11 K12 NC NC NC BMS DMS RFS0 TFS1/IRQ1 SCLK1 ERESET EBR BR EBG B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 A4/IAD3 A3/IAD2 GND NC NC GND VDDEXT D23 D20 D18 D17 D16 E01 E02 E03 E04 E05 E06 E07 E08 E09 E10 E11 E12 VDDEXT VDDEXT A8/IAD7 FL0 PF0 [MODE A] FL2 PF3 [MODE D] GND GND VDDEXT GND D10 H01 H02 H03 H04 H05 H06 H07 H08 H09 H10 H11 H12 CLKIN GND GND GND VDDINT DT0 TFS0 D2/IAD15 D3/IACK GND NC GND L01 L02 L03 L04 L05 L06 L07 L08 L09 L10 L11 L12 IRQE + PF4 NC IRQL1 + PF6 IOMS GND PMS DR0 GND RESET ELIN ELOUT EINT C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 PWDACK A6/IAD5 RD A5/IAD4 A7/IAD6 PWD VDDEXT D21 D19 D15 NC D14 F01 F02 F03 F04 F05 F06 F07 F08 F09 F10 F11 F12 A13/IAD12 NC A12/IAD11 A11/IAD10 FL1 NC NC D7/IWR D11 D8 NC D9 J01 J02 J03 J04 J05 J06 J07 J08 J09 J10 J11 J12 CLKOUT VDDINT NC VDDEXT VDDEXT SCLK0 D0/IAD13 RFS1/IRQ0 BG D1/IAD14 VDDINT VDDINT M01 M02 M03 M04 M05 M06 M07 M08 M09 M10 M11 M12 IRQL0 + PF5 IRQL2 + PF7 NC CMS GND DT1/FO DR1/FI GND NC EMS EE ECLK REV. 0 -39- ADSP-2188M OUTLINE DIMENSIONS Dimensions shown in millimeters. 100-Lead Metric Thin Plastic Quad Flatpack (LQFP) (ST-100) 12 TYP 100 1 10.10 10.00 SQ 9.90 10.10 10.00 SQ 9.90 76 75 SEATING PLANE 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M 8.80 BSC TOP VIEW 0.80 BSC C01629-2.5-9/00 (rev. 0) 16.20 16.00 TYP SQ 15.80 14.05 14.00 TYP SQ 13.95 12.00 BSC 1.60 MAX 0.75 0.60 TYP 0.50 144-Ball Mini-BGA (CA-144) TOP VIEW (PINS DOWN) 0.80 BSC 8.80 BSC 1.40 MAX DETAIL A DETAIL A 0.08 MAX LEAD COPLANARITY 0 - 7 6 4 0.15 0.05 25 26 51 50 0.50 BSC LEAD PITCH NOTES: 1. THE ACTUAL POSITION OF THE BALL 0.40 POPULATION IS WITHIN 0.150 OF ITS 0.25 IDEAL POSITION RELATIVE TO THE PACKAGE EDGES. 2. THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.08 OF ITS IDEAL POSITION RELATIVE TO THE BALL POPULATION. 0.27 0.22 TYP 0.17 LEAD WIDTH NOTE: THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 FROM ITS IDEAL POSITION WHEN MEASURED IN THE LATERAL DIRECTION. 1.00 0.85 0.55 0.12 SEATING MAX PLANE 0.50 0.45 BALL DIAMETER ORDERING GUIDE Part Number Ambient Temperature Range Instruction Rate Package Description* Package Option ADSP-2188MKST-300 ADSP-2188MBST-266 ADSP-2188MKCA-300 ADSP-2188MBCA-266 0C to 70C -40C to +85C 0C to 70C -40C to +85C 75 66 75 66 100-Lead LQFP 100-Lead LQFP 144-Ball Mini-BGA 144-Ball Mini-BGA ST-100 ST-100 CA-144 CA-144 PRINTED IN U.S.A. *In 1998, JEDEC reevaluated the specifications for the TQFP package designation, assigning it to packages 1.0 mm thick. Previously labeled TQFP packages (1.6 mm thick) are now designated as LQFP. -40- REV. 0