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Document Number: 002-15469 Rev. *E Revised July 12, 2016
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53CS20732-DS105-R
5300 California Avenue • Irvine, CA 92617 • Phone: 949-926-5000 • Fax: 949-926-5203 February 16, 2016
Data Sheet
BCM20732
Single-Chip Bluetooth Low-Energy Only SoC
GENERAL DESCRIPTION
APPLICATIONS
The Broadcom® BCM20732 is a Bluetooth Low-
Energy (BLE)-only SoC. The BCM20732 radio has
been designed to provide low power, low cost, and
robust communications for applications operating in
the globally available 2.4 GHz unlicensed Industrial,
Scientific, and Medical (ISM) band.
The single-chip BLE SoC is a monolithic component
implemented in a standard digital CMOS process and
requires minimal external components to make a fully
compliant Bluetooth device. The BCM20732 is
available in a 32-pin, 5 mm × 5 mm 32-QFN package.
FEATURES
• Bluetooth Low-Energy (BLE)-compliant
• Infrared modulator
• IR learning
• Supports Adaptive Frequency Hopping
• Excellent receiver sensitivity
• 10-bit auxiliary ADC with nine analog channels
• On-chip support for serial peripheral interface
(master and slave modes)
• Broadcom Serial Control (BSC) interface
(compatible with NXP I2C slaves)
• Programmable output power control
• Integrated ARM Cortex-M3 based
microprocessor core
• On-chip power-on reset (POR)
• Support for EEPROM and serial flash interfaces
• Integrated Low DropOut (LDO) regulator
• On-chip, software controlled power management
unit
• 32-pin 32-QFN (5 mm × 5 mm) package
• RoHS compliant
The following profiles are supported in ROM:
• Battery status
• Blood pressure monitor
•Find me
• Heart rate monitor
•Proximity
• Thermometer
• Weight scale
•Time
Additional profiles that can be supported from RAM
include:
• Blood glucose monitor
• Temperature alarm
• Location
Full qualification and use of these profiles may require
firmware updates from Broadcom. Some profiles are
under development/approval at Bluetooth SIG and
conformity with the final approved version is pending.
Contact your supplier for updates and the latest list of
profiles.
Revision HistoryBCM20732 Data Sheet
Broadcom®
February 16, 2016 • 53CS20732-DS105-R Page 2
BROADCOM CONFIDENTIAL
Figure 1: Functional Block Diagram
Processing
Unit
(ARM -CM3)
System Bus
Bluetooth
Baseband
Core
2.4 GHz
Radio
RF Control
and Data
T/R
Switch
RF I/O
GPIO
Control/
Status
Registers
Frequency
Synthesizer
24 MHz
Ref Xtal
PMU
I/O Ring Bus
I/O Ring
Control
Registers
Peripheral
Interface
Block
1.2V VDD_CORE
Domain
VDD_IO
Domain
WAKE
1.2V
LDO
1.425V to 3.6V
1.62V to 3.6V
1.2V
VDD_CORE
320K
ROM 60K
RAM
BSC/SPI
Master
Interface
(BSC is I
2
C-
compaƟble)
SDA/
MOSI
SCL/
SCK
High Current
Driver Controls
14 GPIOs
32 kHz
LPCLK
9 ADC
Inputs
24
MHz
hclk
(24 MHz to 1 MHz)
AutoCal
MISO
1.2V VDD_RF
Domain PWM
WDT
128 kHz
LPO
÷4
32 kHz
LPCLK
128 kHz
LPCLK
32 kHzyƚĂů;ŽƉƟŽŶĂůͿ
Power
1.62V to 3.6V
VDD_IO
1.2V
POR
1.2V
Test
UART
IR
I/O
IR
Mod.
and
Learning
SPI
M/S
3.6V
MIA POR
28 ADC
Inputs
CT ɇѐ
ADC
VSS,
VDDO,
VDDC
Periph
UART
UART_RXD
UART_TXD Tx
Rx
RTS_N
CTS_N
Muxed on GPIO
Volt. Trans
Revision HistoryBCM20732 Data Sheet
Broadcom®
February 16, 2016 • 53CS20732-DS105-R Page 3
BROADCOM CONFIDENTIAL
Revision History
Revision Date Change Description
53CS20732-DS105-R 02/16/16 Added:
•“ESD Test Models” on page 38
53CS20732-DS104-R 04/21/15 Updated:
• Table 15: “Receiver RF Specifications,” on page 33
53CS20732-DS103-R 11/24/14 Updated:
• Table 5: “Reference Crystal Electrical Specifications,” on page 20
53CS20732-DS102-R 06/05/14 Updated:
• “UART Interface” on page 19.
53CS20732-DS101-R 3/27/2014 Updated:
• Figure 14: “32-Pin 5x5 mm QFN Package,” on page 38
53CS20732-DS100-R 3/14/2014 Initial release
Broadcom®, the pulse logo, Connecting everything®, and the Connecting everything logo are among the
trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries and/or the
EU. Any other trademarks or trade names mentioned are the property of their respective owners.
This data sheet (including, without limitation, the Broadcom component(s) identified herein) is not designed,
intended, or certified for use in any military, nuclear, medical, mass transportation, aviation, navigations,
pollution control, hazardous substances management, or other high-risk application. BROADCOM PROVIDES
THIS DATA SHEET “AS-IS,” WITHOUT WARRANTY OF ANY KIND. BROADCOM DISCLAIMS ALL
WARRANTIES, EXPRESSED AND IMPLIED, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-
INFRINGEMENT.
Broadcom Corporation
5300 California Avenue
Irvine, CA 92617
© 2016 by Broadcom Corporation
All rights reserved
Printed in the U.S.A.
Table of ContentsBCM20732 Data Sheet
Broadcom®
February 16, 2016 • 53CS20732-DS105-R Page 5
BROADCOM CONFIDENTIAL
Table of Contents
About This Document .................................................................................................................................. 9
Purpose and Audience............................................................................................................................ 9
Acronyms and Abbreviations................................................................................................................... 9
Section 1: Functional Description ................................................................................... 10
Bluetooth Baseband Core ......................................................................................................................... 10
Frequency Hopping Generator.............................................................................................................. 10
E0 Encryption ........................................................................................................................................ 10
Link Control Layer ................................................................................................................................. 10
Adaptive Frequency Hopping................................................................................................................ 10
Bluetooth Low Energy Profiles .............................................................................................................. 11
Test Mode Support................................................................................................................................ 11
Infrared Modulator...................................................................................................................................... 11
Infrared Learning........................................................................................................................................ 12
ADC Port...................................................................................................................................................... 13
Serial Peripheral Interface ......................................................................................................................... 14
Microprocessor Unit................................................................................................................................... 15
EEPROM Interface................................................................................................................................ 15
Serial Flash Interface ............................................................................................................................ 15
Internal Reset........................................................................................................................................ 16
External Reset....................................................................................................................................... 16
Integrated Radio Transceiver .................................................................................................................... 17
Transmitter Path.................................................................................................................................... 17
Digital Modulator ............................................................................................................................ 17
Power Amplifier .............................................................................................................................. 17
Receiver Path........................................................................................................................................ 17
Digital Demodulator and Bit Synchronizer ..................................................................................... 17
Receiver Signal Strength Indicator................................................................................................. 17
Local Oscillator...................................................................................................................................... 17
Calibration ............................................................................................................................................. 18
Internal LDO Regulator ......................................................................................................................... 18
Peripheral Transport Unit .......................................................................................................................... 18
Broadcom Serial Communications Interface ......................................................................................... 18
UART Interface...................................................................................................................................... 19
Clock Frequencies...................................................................................................................................... 19
Crystal Oscillator ................................................................................................................................... 19
Peripheral Block ............................................................................................................................. 20
32 kHz Crystal Oscillator................................................................................................................ 20
Table of ContentsBCM20732 Data Sheet
Broadcom®
February 16, 2016 • 53CS20732-DS105-R Page 6
BROADCOM CONFIDENTIAL
GPIO Port .................................................................................................................................................... 21
PWM............................................................................................................................................................. 22
Power Management Unit............................................................................................................................ 23
RF Power Management ........................................................................................................................ 23
Host Controller Power Management ..................................................................................................... 23
BBC Power Management...................................................................................................................... 23
Section 2: Pin Assignments ............................................................................................. 24
Pin Descriptions ......................................................................................................................................... 24
Ball Maps..................................................................................................................................................... 29
Section 3: Specifications .................................................................................................. 30
Electrical Characteristics........................................................................................................................... 30
RF Specifications ....................................................................................................................................... 33
Timing and AC Characteristics ................................................................................................................. 35
UART Timing......................................................................................................................................... 35
SPI Timing............................................................................................................................................. 36
BSC Interface Timing ............................................................................................................................ 37
ESD Test Models ........................................................................................................................................ 38
Human-Body Model (HBM) – ANSI/ESDA/JEDEC JS-001-2012.......................................................... 38
Machine Model (MM) – JEDEC JESD22-A115C .................................................................................. 38
Charged-Device Model (CDM) - JEDEC JESD22-C101E..................................................................... 39
Results Summary .................................................................................................................................. 39
Section 4: Mechanical Information .................................................................................. 40
Tape Reel and Packaging Specifications.............................................................................................. 42
Section 5: Ordering Information ...................................................................................... 43
Appendix A: Acronyms and Abbreviations .................................................................... 44
List of FiguresBCM20732 Data Sheet
Broadcom®
February 16, 2016 • 53CS20732-DS105-R Page 7
BROADCOM CONFIDENTIAL
List of Figures
Figure 1: Functional Block Diagram................................................................................................................... 2
Figure 2: Infrared TX ........................................................................................................................................ 12
Figure 3: Infrared RX ....................................................................................................................................... 12
Figure 4: Internal Reset Timing........................................................................................................................ 16
Figure 5: External Reset Timing ...................................................................................................................... 16
Figure 6: Recommended Oscillator Configuration—12 pF Load Crystal ........................................................ 19
Figure 7: 32 kHz Oscillator Block Diagram ...................................................................................................... 20
Figure 8: PWM Channel Block Diagram .......................................................................................................... 22
Figure 9: 32-pin QFN Ball Map ........................................................................................................................ 29
Figure 10: UART Timing .................................................................................................................................. 35
Figure 11: SPI Timing – Mode 0 and 2 ............................................................................................................ 36
Figure 12: SPI Timing – Mode 1 and 3 ............................................................................................................ 37
Figure 13: BSC Interface Timing Diagram ....................................................................................................... 38
Figure 14: 32-Pin 5x5 mm QFN Package ........................................................................................................ 40
Figure 15: Pin 1 Orientation ............................................................................................................................. 42
List of TablesBCM20732 Data Sheet
BROADCOM CONFIDENTIAL
Broadcom®
February 16, 2016 • 53CS20732-DS105-R Page 8
List of Tables
Table 1: ADC Modes........................................................................................................................................ 13
Table 2: BCM20732 First SPI Set (Master Mode) ........................................................................................... 14
Table 3: BCM20732 Second SPI Set (Master Mode) ...................................................................................... 14
Table 4: BCM20732 Second SPI Set (Slave Mode) ........................................................................................ 14
Table 5: Reference Crystal Electrical Specifications ....................................................................................... 20
Table 6: XTAL Oscillator Characteristics ......................................................................................................... 21
Table 7: Pin Descriptions ................................................................................................................................. 24
Table 8: GPIO Pin Descriptions ....................................................................................................................... 26
Table 9: Maximum Electrical Rating ................................................................................................................ 30
Table 10: Power Supply................................................................................................................................... 30
Table 11: LDO Regulator Electrical Specifications .......................................................................................... 31
Table 12: ADC Specifications .......................................................................................................................... 31
Table 13: Digital Levels.................................................................................................................................... 32
Table 14: Current Consumption ...................................................................................................................... 32
Table 15: Receiver RF Specifications.............................................................................................................. 33
Table 16: Transmitter RF Specifications.......................................................................................................... 34
Table 17: UART Timing Specifications ............................................................................................................ 35
Table 18: SPI Interface Timing Specifications ................................................................................................. 36
Table 19: BSC Interface Timing Specifications................................................................................................ 37
Table 20: 32-pin 5x5 mm QFN Package Dimensions (Footprint: 0.80) ........................................................... 41
Table 21: BCM20732 5 × 5 × 1 mm QFN, 32-Pin Tape Reel Specifications ................................................... 42
Table 22: Ordering Information ........................................................................................................................ 43
About This Document
Broadcom®
February 16, 2016 • 53CS20732-DS105-R Page 9
BCM20732 Data Sheet
BROADCOM CONFIDENTIAL
About This Document
Purpose and Audience
This data sheet provides a description of the major blocks, interfaces, pin assignments, and specifications of the
BCM20732 single-chip Bluetooth low energy (BLE) SoC. This is a required document for designers responsible
for adding the BCM20732 BLE SoC to wireless input device applications including heart-rate monitors, blood-
pressure monitors, proximity sensors, temperature sensors, and battery monitors.
Acronyms and Abbreviations
In most cases, acronyms and abbreviations are defined on first use. Acronyms and abbreviations in this
document are also defined in Appendix A: “Acronyms and Abbreviations,” on page 44.
For a comprehensive list of acronyms and other terms used in Broadcom documents, go to
http://www.broadcom.com/press/glossary.php.
Technical Support
Broadcom provides customer access to a wide range of information, including technical documentation,
schematic diagrams, product bill of materials, PCB layout information, and software updates through its
customer support portal (https://support.broadcom.com). For a CSP account, contact your Sales or Engineering
support representative.
In addition, Broadcom provides other product support through its Downloads & Support site
(http://www.broadcom.com/support/).
Functional DescriptionBCM20732 Data Sheet
BROADCOM CONFIDENTIAL
Broadcom®
February 16, 2016 • 53CS20732-DS105-R Page 10
Section 1: Functional Description
Bluetooth Baseband Core
The Bluetooth Baseband Core (BBC) implements all of the time-critical functions required for high performance
Bluetooth operation. The BBC manages the buffering, segmentation, and data routing for all connections. It also
buffers data that passes through it, handles data flow control, schedules ACL TX/RX transactions, monitors
Bluetooth slot usage, optimally segments and packages data into baseband packets, manages connection
status indicators, and composes and decodes HCI packets. In addition to these functions, it independently
handles HCI event types and HCI command types.
The following transmit and receive functions are also implemented in the BBC hardware to increase TX/RX data
reliability and security before sending over the air:
• Receive Functions: symbol timing recovery, data deframing, forward error correction (FEC), header error
control (HEC), cyclic redundancy check (CRC), data decryption, and data dewhitening.
• Transmit Functions: data framing, FEC generation, HEC generation, CRC generation, link key generation,
data encryption, and data whitening.
Frequency Hopping Generator
The frequency hopping sequence generator selects the correct hopping channel number depending on the link
controller state, Bluetooth clock, and device address.
E0 Encryption
The encryption key and the encryption engine are implemented using dedicated hardware to reduce software
complexity and provide minimal processor intervention.
Link Control Layer
The link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the
link control unit (LCU). This layer consists of the Command Controller, which takes software commands, and
other controllers that are activated or configured by the Command Controller to perform the link control tasks.
Each task performs a different Bluetooth link controller state. STANDBY and CONNECTION are the two major
states. In addition, there are five substates: page, page scan, inquiry, and inquiry scan.
Adaptive Frequency Hopping
The BCM20732 gathers link quality statistics on a channel-by-channel basis to facilitate channel assessment
and channel map selection. The link quality is determined by using both RF and baseband signal processing to
provide a more accurate frequency hop map.
Infrared ModulatorBCM20732 Data Sheet
BROADCOM CONFIDENTIAL
Broadcom®
February 16, 2016 • 53CS20732-DS105-R Page 11
Bluetooth Low Energy Profiles
The BCM20732 supports Bluetooth low-energy, including the following profiles that are supported1 in ROM:
• Battery status
• Blood pressure monitor
•Find me
• Heart rate monitor
•Proximity
• Thermometer
• Weight scale
•Time
The following additional profiles can be supported1 from RAM:
• Blood glucose monitor
• Temperature alarm
• Location
• Custom profile
Test Mode Support
The BCM20732 fully supports Bluetooth Test mode, as described in the Bluetooth low energy specification.
Infrared Modulator
The BCM20732 includes hardware support for infrared TX. The hardware can transmit both modulated and
unmodulated waveforms. For modulated waveforms, hardware inserts the desired carrier frequency into all IR
transmissions. IR TX can be sourced from firmware-supplied descriptors, a programmable bit, or the peripheral
UART transmitter.
If descriptors are used, they include IR on/off state and the duration between 1 and 32,767 µsec. The
BCM20732 IR TX firmware driver inserts this information in a hardware FIFO and makes sure that all descriptors
are played out without a glitch due to underrun (see Figure 2 on page 12).
1. Full qualification and use of these profiles may require firmware updates from Broadcom. Some of these
profiles are under development/approval at the Bluetooth SIG and conformity with the final approved version is
pending. Contact your supplier for updates and the latest list of profiles.
Infrared LearningBCM20732 Data Sheet
BROADCOM CONFIDENTIAL
Broadcom®
February 16, 2016 • 53CS20732-DS105-R Page 12
Figure 2: Infrared TX
Infrared Learning
The BCM20732 includes hardware support for infrared learning. The hardware can detect both modulated and
unmodulated signals. For modulated signals, the BCM20732 can detect carrier frequencies between 10 kHz–
500 kHz and the duration that the signal is present or absent. The BCM20732 firmware driver supports further
analysis and compression of learned signal. The learned signal can then be played back through the BCM20732
IR TX subsystem (see Figure 3).
Figure 3: Infrared RX
ADC PortBCM20732 Data Sheet
BROADCOM CONFIDENTIAL
Broadcom®
February 16, 2016 • 53CS20732-DS105-R Page 13
ADC Port
The BCM20732 contains a 16-bit ADC (effective number of bits is 10).
Additionally:
• There are nine analog input channels in the 32-pin package
• The following GPIOs can be used as ADC inputs:
–P0
–P1
– P8/P33 (select only one)
–P11
–P12
– P13/P28 (select only one)
– P14/P38 (select only one)
–P15
–P32
• The conversion time is 10 s.
• There is a built-in reference with supply- or bandgap-based reference modes.
• The maximum conversion rate is 187 kHz.
• There is a rail-to-rail input swing.
The ADC consists of an analog ADC core that performs the actual analog-to-digital conversion and digital
hardware that processes the output of the ADC core into valid ADC output samples. Directed by the firmware,
the digital hardware also controls the input multiplexers that select the ADC input signal Vinp and the ADC
reference signals Vref.
The ADC input range is selectable by firmware control:
• When an input range of 0–3.6V is used, the input impedance is 3 M.
• When an input range of 0–2.4V is used, the input impedance is 1.84 M.
• When an input range of 0–1.2V is used, the input impedance is 680 k.
ADC modes are defined in Ta b l e 1.
Table 1: ADC Modes
Mode ENOB (Typical) Maximum Sampling Rate (kHz) Latencya (μs)
a. Settling time after switching channels.
0 13 5.859 171
112.6 11.7 85
212 46.875 21
3 11.5 93.75 11
410 187 5
Serial Peripheral InterfaceBCM20732 Data Sheet
BROADCOM CONFIDENTIAL
Broadcom®
February 16, 2016 • 53CS20732-DS105-R Page 14
Serial Peripheral Interface
The BCM20732 has two independent SPI interfaces. One is a master-only interface and the other can be either
a master or a slave. Each interface has a 16-byte transmit buffer and a 16-byte receive buffer. To support more
flexibility for user applications, the BCM20732 has optional I/O ports that can be configured individually and
separately for each functional pin as shown in Table 2, Ta b le 3, and Ta b le 4. The BCM20732 acts as a SPI
master device that supports 1.8V or 3.3V SPI slaves. The BCM20732 can also act as an SPI slave device that
supports a 1.8V or 3.3V SPI master.
Table 2: BCM20732 First SPI Set (Master Mode)
Pin Name SPI_CLK SPI_MOSI SPI_MISO SPI_CSa
a. Any GPIO can be used as SPI_CS when SPI is in master mode.
Configured Pin Name SCL SDA P24 –
––P26–
––P32–
Table 3: BCM20732 Second SPI Set (Master Mode)
Pin Name SPI_CLK SPI_MOSI SPI_MISO SPI_CSa
a. Any GPIO can be used as SPI_CS when SPI is in master mode.
Configured Pin Name P3 P0 P1 –
–P4P25–
P24 P27 – –
Table 4: BCM20732 Second SPI Set (Slave Mode)
Pin Name SPI_CLK SPI_MOSI SPI_MISO SPI_CS
Configured Pin Name P3 P0 P1 P2
–P27––
P24 P33 P25 P26
–––P32
Microprocessor UnitBCM20732 Data Sheet
BROADCOM CONFIDENTIAL
Broadcom®
February 16, 2016 • 53CS20732-DS105-R Page 15
Microprocessor Unit
The BCM20732 microprocessor unit (µPU) executes software from the link control (LC) layer up to the
application layer components. The microprocessor is based on an ARM Cortex-M3, 32-bit RISC processor with
embedded ICE-RT debug and JTAG interface units. The µPU has 320 KB of ROM for program storage and boot-
up, 60 KB of RAM for scratch-pad data, and patch RAM code. The SoC has a total storage of 380 KB, including
RAM and ROM.
The internal boot ROM provides power-on reset flexibility, which enables the same device to be used in different
HID applications with an external serial EEPROM or with an external serial flash memory. At power-up, the
lowest layer of the protocol stack is executed from the internal ROM memory.
External patches may be applied to the ROM-based firmware to provide flexibility for bug fixes and feature
additions. The device can also support the integration of user applications.
EEPROM Interface
The BCM20732 provides a Broadcom Serial Control (BSC) master interface. BSC is programmed by the CPU
to generate four types of bus transfers: read-only, write-only, combined read/write, and combined write/read.
BSC supports both low-speed and fast mode devices. BSC is compatible with an NXP I2C slave device, except
that master arbitration (multiple I2C masters contending for the bus) is not supported.
The EEPROM can contain customer application configuration information including application code,
configuration data, patches, pairing information, BD_ADDR, baud rate, SDP service record, and file system
information used for code.
Native support for the Microchip 24LC128, Microchip 24AA128, and the STMicroelectronics M24128-BR is
included.
Serial Flash Interface
The BCM20732 includes an SPI master controller that can be used to access serial flash memory. The SPI
master contains an AHB slave interface, transmit and receive FIFOs, and the SPI core PHY logic.
Devices natively supported include the following:
• Atmel AT25BCM512B
• MXIC MX25V512ZUI-20G
Microprocessor UnitBCM20732 Data Sheet
BROADCOM CONFIDENTIAL
Broadcom®
February 16, 2016 • 53CS20732-DS105-R Page 16
Internal Reset
Figure 4: Internal Reset Timing
External Reset
The BCM20732 has an integrated power-on reset circuit that completely resets all circuits to a known power-on
state. An external active low reset signal, RESET_N, can be used to put the BCM20732 in the reset state. The
RESET_N pin has an internal pull-up resistor and, in most applications, it does not require that anything be
connected to it. RESET_N should only be released after the VDDO supply voltage level has been stabilized.
Figure 5: External Reset Timing
VDDO
VDDO POR
VDDC
VDDO POR threshold
VDDO POR delay
~ 2 ms
VDDC POR
VDDC POR threshold
VDDC POR delay
~ 2 ms
Baseband Reset
Crystal
warm-up
delay:
~ 5 ms
Crystal Enable
Start reading EEPROM and
firmware boot
RESET_N
Pulse width
>20 µs
Crystal Enable
Baseband Reset
Start reading EEPROM and
firmware boot
Crystal
warm-up
delay:
~ 5 ms
Integrated Radio TransceiverBCM20732 Data Sheet
BROADCOM CONFIDENTIAL
Broadcom®
February 16, 2016 • 53CS20732-DS105-R Page 17
Integrated Radio Transceiver
The BCM20732 has an integrated radio transceiver that is optimized for 2.4 GHz Bluetooth wireless systems. It
has been designed to provide low power, low cost, and robust communications for applications operating in the
globally available 2.4 GHz unlicensed ISM band. It is fully compliant with Bluetooth Radio Specification 4.0 and
meets or exceeds the requirements to provide the highest communication link quality of service.
Transmitter Path
The BCM20732 features a fully integrated transmitter. The baseband transmit data is GFSK modulated in the
2.4 GHz ISM band.
Digital Modulator
The digital modulator performs the data modulation and filtering required for the GFSK signal. The fully digital
modulator minimizes any frequency drift or anomalies in the modulation characteristics of the transmitted signal.
Power Amplifier
The BCM20732 has an integrated power amplifier (PA) that can transmit up to +4 dBm for class 2 operation.
Receiver Path
The receiver path uses a low IF scheme to downconvert the received signal for demodulation in the digital
demodulator and bit synchronizer. The receiver path provides a high degree of linearity, an extended dynamic
range, and high-order, on-chip channel filtering to ensure reliable operation in the noisy 2.4 GHz ISM band. The
front-end topology, which has built-in out-of-band attenuation, enables the BCM20732 to be used in most
applications without off-chip filtering.
Digital Demodulator and Bit Synchronizer
The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency
tracking and bit synchronization algorithm.
Receiver Signal Strength Indicator
The radio portion of the BCM20732 provides a receiver signal strength indicator (RSSI) to the baseband. This
enables the controller to take part in a Bluetooth power-controlled link by providing a metric of its own receiver
signal strength to determine whether the transmitter should increase or decrease its output power.
Local Oscillator
The local oscillator (LO) provides fast frequency hopping (1600 hops/second) across the 79 maximum available
channels. The BCM20732 uses an internal loop filter.
Peripheral Transport UnitBCM20732 Data Sheet
BROADCOM CONFIDENTIAL
Broadcom®
February 16, 2016 • 53CS20732-DS105-R Page 18
Calibration
The BCM20732 radio transceiver features a self-contained automated calibration scheme. No user interaction
is required during normal operation or during manufacturing to provide optimal performance. Calibration
compensates for filter, matching network, and amplifier gain and phase characteristics to yield radio
performance within 2% of what is optimal. Calibration takes process and temperature variations into account,
and it takes place transparently during normal operation and hop setting times.
Internal LDO Regulator
The BCM20732 has an integrated 1.2V LDO regulator that provides power to the digital and RF circuits. The
1.2V LDO regulator operates from a 1.425V to 3.63V input supply with a 30 mA maximum load current.
Peripheral Transport Unit
Broadcom Serial Communications Interface
The BCM20732 provides a 2-pin master BSC interface, which can be used to retrieve configuration information
from an external EEPROM or to communicate with peripherals such as track-ball or touch-pad modules, and
motion tracking ICs used in mouse devices. The BSC interface is compatible with I2C slave devices. The BSC
does not support multimaster capability or flexible wait-state insertion by either master or slave devices.
The following transfer clock rates are supported by the BSC:
• 100 kHz
• 400 kHz
• 800 kHz (not a standard I2C-compatible speed.)
• 1 MHz (Compatibility with high-speed I2C-compatible devices is not guaranteed.)
The following transfer types are supported by the BSC:
• Read (Up to 16 bytes can be read.)
• Write (Up to 16 bytes can be written.)
• Read-then-Write (Up to 16 bytes can be read and up to 16 bytes can be written.)
• Write-then-Read (Up to 16 bytes can be written and up to 16 bytes can be read.)
Hardware controls the transfers, requiring minimal firmware setup and supervision.
The clock pin (SCL) and data pin (SDA) are both open-drain I/O pins. Pull-up resistors external to the
BCM20732 are required on both the SCL and SDA pins for proper operation.
Note: Always place the decoupling capacitors near the pins as closely together as possible.
Clock FrequenciesBCM20732 Data Sheet
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UART Interface
The UART is a standard 2-wire interface (RX and TX) and has adjustable baud rates from 9600 bps to
115.2 Kbaud. The baud rate can be selected via a vendor-specific UART HCI command. The interface supports
the Bluetooth 3.0 UART HCI (H4) specification. The default baud rate for H4 is 115.2 Kbaud.
Both high and low baud rates can be supported by running the UART clock at 24 MHz.
The BCM20732 UART operates correctly with the host UART as long as the combined baud rate error of the
two devices is within ±5 percent
Clock Frequencies
The BCM20732 is set with a crystal frequency of 24 MHz.
Crystal Oscillator
The crystal oscillator requires a crystal with an accuracy of ±20 ppm as defined by the Bluetooth specification.
Two external load capacitors in the range of 5 pF to 30 pF (see Figure 6) are required to work with the crystal
oscillator. The selection of the load capacitors is crystal-dependent.
Figure 6: Recommended Oscillator Configuration—12 pF Load Crystal
22 pF
20 pF
Crystal
XIN
XOUT
Clock FrequenciesBCM20732 Data Sheet
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February 16, 2016 • 53CS20732-DS105-R Page 20
Table 5 shows the recommended crystal specifications.
Peripheral Block
The BCM20732 peripheral blocks all run from a single 128 kHz low-power RC oscillator. The oscillator can be
turned on at the request of any of the peripherals. If the peripheral is not enabled, it shall not assert its clock
request line.
The keyboard scanner is a special case, in that it may drop its clock request line even when enabled, and then
reassert the clock request line if a keypress is detected.
32 kHz Crystal Oscillator
Figure 7 shows the 32 kHz crystal (XTAL) oscillator with external components and Table 6 on page 21 lists the
oscillator’s characteristics. It is a standard Pierce oscillator using a comparator with hysteresis on the output to
create a single-ended digital output. The hysteresis was added to eliminate any chatter when the input is around
the threshold of the comparator and is ~100 mV. This circuit can be operated with a 32 kHz or 32.768 kHz crystal
oscillator or be driven with a clock input at similar frequency. The default component values are: R1 = 10 M,
C1 = C2 = ~10 pF. The values of C1 and C2 are used to fine-tune the oscillator.
Figure 7: 32 kHz Oscillator Block Diagram
Table 5: Reference Crystal Electrical Specifications
Parameter Conditions Minimum Typical Maximum Unit
Nominal frequency – – 24.000 – MHz
Oscillation mode – Fundamental –
Frequency tolerance @25°C – ±10 – ppm
Tolerance stability over temp @0°C to +70°C – ±10 – ppm
Equivalent series resistance – – – 60
Load capacitance – – 12 – pF
Operating temperature range – 0 – +70 °C
Storage temperature range – –40 – +125 °C
Drive level – – – 200 W
Aging – – – ±10 ppm/year
Shunt capacitance – – – 2 pF
C2
C1
R1 32.768 kHz
XTAL
GPIO PortBCM20732 Data Sheet
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GPIO Port
The BCM20732 has 14 general-purpose I/Os (GPIOs) in the 32-pin package. All GPIOs support programmable
pull-up and pull-down resistors, and all support a 2 mA drive strength except P26, P27, and P28, which provide
a 16 mA drive strength at 3.3V supply.
The following GPIOs are available:
•P0–P4
• P8/P33 (Dual bonded, only one of two is available.)
• P11/P27 (Dual bonded, only one of two is available.)
• P12/P26 (Dual bonded, only one of two is available.)
• P13/P28 (Dual bonded, only one of two is available.)
• P14/P38 (Dual bonded, only one of two is available.)
•P15
•P24
•P25
•P32
For a description of all GPIOs, see Table 8: “GPIO Pin Descriptions,” on page 26.
Table 6: XTAL Oscillator Characteristics
Parameter Symbol Conditions Minimum Typical Maximum Unit
Output
frequency
Foscout ––32.768–kHz
Frequency
tolerance
– Crystal dependent – 100 – ppm
Start-up time Tstartup –––500ms
XTAL drive level Pdrv For crystal
selection
0.5 – – W
XTAL series
resistance
Rseries For crystal
selection
–– 70k
XTAL shunt
capacitance
Cshunt For crystal
selection
–– 1.3pF
PWMBCM20732 Data Sheet
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February 16, 2016 • 53CS20732-DS105-R Page 22
PWM
The BCM20732 has four internal PWM channels. The PWM module is described as follows:
•PWM0–3
• The following GPIOs can be mapped as PWMs:
•P26
•P27
• P14/P28 (Dual bonded, only one of two is available.)
•P13
• Each of the PWM channels, PWM0–3, contains the following registers:
– 10-bit initial value register (read/write)
– 10-bit toggle register (read/write)
– 10-bit PWM counter value register (read)
• The PWM configuration register is shared among PWM0–3 (read/write). The 12-bit register is used:
– To configure each PWM channel.
– To select the clock of each PWM channel.
– To change the phase of each PWM channel.
Figure 8 shows the structure of one PWM channel.
Figure 8: PWM Channel Block Diagram
pwm_cfg_adr register pwm#_init_val_adr register pwm#_togg_val_adr register
pwm#_cntr_adr
enable
cntr value is CM3 readable
clk_sel
o_flip
10'H000
10'H3FF
10
10 10
Example: PWM cntr w/ pwm#_init_val = 0 (dashed line)
PWM cntr w/ pwm#_init_val = x (solid line)
10'Hx
pwm_out
pwm_togg_val_adr
pwm_out
Power Management UnitBCM20732 Data Sheet
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February 16, 2016 • 53CS20732-DS105-R Page 23
Power Management Unit
The power management unit (PMU) provides power management features that can be invoked by software
through power management registers or packet-handling in the baseband core.
RF Power Management
The BBC generates power-down control signals for the transmit path, receive path, PLL, and power amplifier to
the 2.4 GHz transceiver, which then processes the power-down functions accordingly.
Host Controller Power Management
Power is automatically managed by the firmware based on input device activity. As a power-saving task, the
firmware controls the disabling of the on-chip regulator when in deep sleep mode.
BBC Power Management
There are several low-power operations for the BBC:
• Physical layer packet handling turns RF on and off dynamically within packet TX and RX.
• Bluetooth-specified low-power connection mode. While in these low-power connection modes, the
BCM20732 runs on the low power oscillator (LPO) and wakes up after a predefined time period.
The BCM20732 automatically adjusts its power dissipation based on user activity. The following power modes
are supported:
• Active mode
• Idle mode
• Sleep mode
• HIDOFF (Deep Sleep) mode
The BCM20732 transitions to the next lower state after a programmable period of user inactivity. Busy mode is
immediately entered when user activity resumes.
In HIDOFF (Deep Sleep) mode, the BCM20732 baseband and core are powered off by disabling power to
LDOOUT. The VDDO domain remains powered up and will turn the remainder of the chip on when it detects
user events. This mode minimizes chip power consumption and is intended for long periods of inactivity.
Pin AssignmentsBCM20732 Data Sheet
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February 16, 2016 • 53CS20732-DS105-R Page 24
Section 2: Pin Assignments
Pin Descriptions
Table 7: Pin Descriptions
Pin Number Pin Name I/O Power Domain Description
Radio I/O
6 RF I/O VDD_RF RF antenna port
RF Power Supplies
4 VDDIF I VDD_RF IFPLL power supply
5 VDDFE I VDD_RF RF front-end supply
7 VDDVCO I VDD_RF VCO, LOGEN supply
8 VDDPLL I VDD_RF RFPLL and crystal oscillator supply
Power Supplies
11 VDDC I VDDC Baseband core supply
28 VDDO I VDDO I/O pad and core supply
14 VDDM I VDDM I/O pad supply
Clock Generator and Crystal Interface
9 XTALI I VDD_RF Crystal oscillator input. See page 19 for options.
10 XTALO O VDD_RF Crystal oscillator output.
1 XTALI32K I VDDO LPO input is used. Alternative Function:
•P11
•P27
32 XTALO32K O VDDO LPO output. Alternative Function:
•P12
•P26
Core
18 RESET_N I/O PU VDDO Active-low system reset with open-drain output &
internal pull-up resistor
17 TMC I VDDO Test mode control
High: test mode
Connect to GND if not used.
UART
12 UART_RXD I VDDM UART serial input – Serial data input for the HCI
UART interface. Leave unconnected if not used.
Alternative function:
•GPIO3
Pin DescriptionsBCM20732 Data Sheet
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February 16, 2016 • 53CS20732-DS105-R Page 25
13 UART_TXD O, PU VDDM UART serial output – Serial data output for the
HCI UART interface. Leave unconnected if not
used.
Alternative Function:
•GPIO2
BSC
15 SDA I/O, PU VDDM Data signal for an external I2C device.
Alternative function:
• SPI_1: MOSI (master only)
•GPIO0
•CTS
16 SCL I/O, PU VDDM Clock signal for an external I2C device.
Alternative function:
• SPI_1: SPI_CLK (master only)
•GPIO1
•RTS
LDO Regulator Power Supplies
2 LDOIN I N/A Battery input supply for the LDO
3 LDOOUT O N/A LDO output
Table 7: Pin Descriptions (Cont.)
Pin Number Pin Name I/O Power Domain Description
Pin DescriptionsBCM20732 Data Sheet
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February 16, 2016 • 53CS20732-DS105-R Page 26
Table 8: GPIO Pin Descriptionsa
Pin Number Pin Name
Default
Direction
After
POR
State
Power
Domain Alternate Function Description
19 P0 Input Input
floating
VDDO • GPIO: P0
• A/D converter input
• Peripheral UART: puart_tx
• SPI_2: MOSI (master and slave)
• IR_RX
• 60Hz_main
• Not available during TMC=1
20 P1 Input Input
floating
VDDO • GPIO: P1
• A/D converter input
• Peripheral UART: puart_rts
• SPI_2: MISO (master and slave)
•IR_TX
21 P3 Input Input
floating
VDDO • GPIO: P3
• Peripheral UART: puart_cts
• SPI_2: SPI_CLK (master and slave)
22 P2 Input Input
floating
VDDO • GPIO: P2
• Peripheral UART: puart_rx
• SPI_2: SPI_CS (slave only)
• SPI_2: SPI_MOSI (master only)
23 P4 Input Input
floating
VDDO • GPIO: P4
• Peripheral UART: puart_rx
• SPI_2: MOSI (master and slave)
•IR_TX
24 P8 Input Input
floating
VDDO • GPIO: P8
• A/D converter input
• External T/R switch control: ~tx_pd
P33 Input Input
floating
VDDO • GPIO: P33
• A/D converter input
• SPI_2: MOSI (slave only)
• Auxiliary clock output: ACLK1
• Peripheral UART: puart_rx
1 P11 Input Input
floating
VDDO • GPIO: P11
• A/D converter input
• XTALI32K
P27
PWM1
Input Input
floating
VDDO • GPIO: P27
• SPI_2: MOSI (master and slave)
Current: 16 mA
Pin DescriptionsBCM20732 Data Sheet
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February 16, 2016 • 53CS20732-DS105-R Page 27
32 P12 Input Input
floating
VDDO • GPIO: P12
• A/D converter input
• XTALO32K
P26
PWM0
Input Input
floating
VDDO • GPIO: P26
• SPI_2: SPI_CS (slave only)
• SPI_1: MISO (master only)
Current: 16 mA
29 P13
PWM3
Input Input
floating
VDDO • GPIO: P13
• A/D converter input
P28
PWM2
Input Input
floating
VDDO • GPIO: P28
• A/D converter input
•LED1
•IR_TX
Current: 16 mA
30 P14
PWM2
Input Input
floating
VDDO • GPIO: P14
• A/D converter input
P38 Input Input
floating
VDDO • GPIO: P38
• A/D converter input
• SPI_2: MOSI (master and slave)
•IR_TX
31 P15 Input Input
floating
VDDO • GPIO: P15
• A/D converter input
• IR_RX
• 60 Hz_main
27 P24 Input Input
floating
VDDO • GPIO: P24
• SPI_2: SPI_CLK (master and slave)
• SPI_1: MISO (master only)
• Peripheral UART: puart_tx
26 P25 Input Input
floating
VDDO • GPIO: P25
• SPI_2: MISO (master and slave)
• Peripheral UART: puart_rx
Table 8: GPIO Pin Descriptionsa (Cont.)
Pin Number Pin Name
Default
Direction
After
POR
State
Power
Domain Alternate Function Description
Pin DescriptionsBCM20732 Data Sheet
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February 16, 2016 • 53CS20732-DS105-R Page 28
25 P32 Input Input
floating
VDDO • GPIO: P32
• A/D converter input
• SPI_2: SPI_CS (slave only)
• SPI_1: MISO (master only)
• Auxiliary clock output: ACLK0
• Peripheral UART: puart_tx
a. During power-on reset, all inputs are disabled.
Table 8: GPIO Pin Descriptionsa (Cont.)
Pin Number Pin Name
Default
Direction
After
POR
State
Power
Domain Alternate Function Description
Ball MapsBCM20732 Data Sheet
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February 16, 2016 • 53CS20732-DS105-R Page 29
Ball Maps
Figure 9: 32-pin QFN Ball Map
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
17
18
19
20
21
22
23
24
25 26 27 28 29 30 31 32
P11/P27/XIN32
LDO_IN
LDO_OUT
VDDIF
VDDFE
RF
VDDVCO
VDDPLL
XTALI
XTALO
VDDC
UART_RXD
UART_TXD
VDDM
SDA
SCL
TMC
RST_N
P0
P1
P3
P2
P4
P8/P33
P32
P25
P24
VDDO
P13/P28
P14/P38
P15
P12/P26/XO32
SpecificationsBCM20732 Data Sheet
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February 16, 2016 • 53CS20732-DS105-R Page 30
Section 3: Specifications
Electrical Characteristics
Ta b l e 9 shows the maximum electrical rating for voltages referenced to VDD pin.
Ta b l e 10 shows the power supply characteristics for the range TJ = 0 to 125°C.
Table 9: Maximum Electrical Rating
Rating Symbol Value Unit
DC supply voltage for RF domain – 1.4 V
DC supply voltage for core domain – 1.4 V
DC supply voltage for VDDM domain (UART/I2C) –3.8 V
DC supply voltage for VDDO domain – 3.8 V
DC supply voltage for VR3V – 3.8 V
DC supply voltage for VDDFE – 1.4 V
Voltage on input or output pin – VSS – 0.3 to VDD + 0.3 V
Operating ambient temperature range Topr –30 to +85 °C
Storage temperature range Tstg –40 to +125 °C
Table 10: Power Supply
Parameter Minimuma
a. Overall performance degrades beyond minimum and maximum supply voltages.
Typical MaximumaUnit
DC supply voltage for RF 1.14 1.2 1.26 V
DC supply voltage for Core 1.14 1.2 1.26 V
DC supply voltage for VDDM (UART/I2C) 1.62 – 3.63 V
DC supply voltage for VDDO 1.62 – 3.63 V
DC supply voltage for LDOIN 1.425 – 3.63 V
DC supply voltage for VDDFE 1.14 1.2b
b. 1.2V for Class 2 output with internal VREG.
1.26 V
Electrical CharacteristicsBCM20732 Data Sheet
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February 16, 2016 • 53CS20732-DS105-R Page 31
Table 11 shows the digital level characteristics for (VSS = 0V).
Ta b l e 12 shows the specifications for the ADC characteristics.
Table 11: LDO Regulator Electrical Specifications
Parameter Conditions Min. Typ. Max. Unit
Input voltage range – 1.425 – 3.63 V
Default output voltage – – 1.2 – V
Output voltage Range 0.8 – 1.4 V
Step size – 40 or 80 – mV
Accuracy at any step –5 – +5 %
Load current – – – 30 mA
Line regulation Vin from 1.425 to 3.63V, Iload = 30 mA –0.2 – 0.2 %VO/V
Load regulation Iload from 1 µA to 30 mA, Vin = 3.3V,
Bonding R = 0.3
–0.10.2%V
O/mA
Quiescent current No load @Vin = 3.3V
*Current limit enabled
–6–µA
Power-down current Vin = 3.3V, worst@70°C – 5 200 nA
Table 12: ADC Specifications
Parameter Symbol Conditions Min. Typ. Max. Unit
Number of Input channels – – – 9 – –
Channel switching rate fch – – – 133.33 kch/s
Input signal range Vinp –0–3.63V
Reference settling time – Changing refsel 7.5 – – s
Input resistance Rinp Effective, single ended – 500 – k
Input capacitance Cinp –––5pF
Conversion rate fC– 5.859 – 187 kHz
Conversion time TC– 5.35 – 170.7 s
Resolution R – – 16 – bits
Effective number of bits – In specified performance range – See Table 1
on page 13
––
Absolute voltage
measurement error
– Using on-chip ADC firmware driver – ±2 – %
Current I Iavdd1p2 + Iavdd3p3 –– 1 mA
Power P – – 1.5 – mW
Leakage current Ileakage T = 25°C – – 100 nA
Power-up time Tpowerup – – – 200 µs
Integral nonlinearity3INL In guaranteed performance range –1 – 1 LSBa
a. LSBs are expressed at the 10-bit level.
Differential nonlinearityaDNL In guaranteed performance range –1 – 1 LSBa
Electrical CharacteristicsBCM20732 Data Sheet
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February 16, 2016 • 53CS20732-DS105-R Page 32
Table 13 shows the specifications for the digital voltage levels.
Table 14 shows the specifications for current consumption.
Table 13: Digital Levelsa
a. This table is also applicable to VDDMEM domain.
Characteristics Symbol Min Typ Max Unit
Input low voltage VIL ––0.4V
Input high voltage VIH 0.75 ×
VDDO
––V
Input low voltage (VDDO = 1.62V) VIL ––0.4V
Input high voltage (VDDO = 1.62V) VIH 1.2 – – V
Output low voltageb
b. At the specified drive current for the pad.
VOL ––0.4V
Output high voltagebVOH VDDO – 0.4 – – V
Input capacitance (VDDMEM domain) CIN –0.12–pF
Table 14: Current Consumption a
a. Currents measured between power terminals (Vdd) using 90% efficient DC-DC converter at 3V.
Operational Mode Conditions Min Typ Max Unit
Receive Receiver and baseband are both operating, 100% ON. – 9.8 – mA
Transmit Transmitter and baseband are both operating, 100% ON. – 9.1 – mA
Sleep Internal LPO is in use. – 12.0 – A
– – 0.65 –
RF SpecificationsBCM20732 Data Sheet
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February 16, 2016 • 53CS20732-DS105-R Page 33
RF Specifications
Table 15: Receiver RF Specifications
Parameter Mode and Conditions Min Typ Max Unit
Receiver Sectiona
a. 30.8% PER.
Frequency range – 2402 – 2480 MHz
RX sensitivity (standard) 0.1%BER, 1Mbps, dirty transmitter
OFF
––93–dBm
RX sensitivity (low current) – –90 – dBm
Input IP3 – –16 – – dBm
Maximum input – –10 – – dBm
Interference Performancea,b
b. Desired signal is 3 dB above the reference sensitivity level (defined as –70 dBm).
C/I cochannel 0.1%BER – – 21 dB
C/I 1 MHz adjacent channel 0.1%BER – – 15 dB
C/I 2 MHz adjacent channel 0.1%BER – – –17 dB
C/I 3 MHz adjacent channel 0.1%BER – – –27 dB
C/I image channel 0.1%BER – – –9.0 dB
C/I 1 MHz adjacent to image
channel
0.1%BER – – –15 dB
Out-of-Band Blocking Performance (CW)a,b
30 MHz to 2000 MHz 0.1%BERc
c. Measurement resolution is 10 MHz.
– –30.0 – dBm
2003 MHz to 2399 MHz 0.1%BERd
d. Measurement resolution is 3 MHz.
––35–dBm
2484 MHz to 2997 MHz 0.1%BERd––35–dBm
3000 MHz to 12.75 GHz 0.1%BERe
e. Measurement resolution is 25 MHz.
– –30.0 – dBm
Spurious Emissions
30 MHz to 1 GHz – – – –57.0 dBm
1 GHz to 12.75 GHz – – – –55.0 dBm
RF SpecificationsBCM20732 Data Sheet
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February 16, 2016 • 53CS20732-DS105-R Page 34
Table 16: Transmitter RF Specifications
Parameter Minimum Typical Maximum Unit
Transmitter Section
Frequency range 2402 – 2480 MHz
Output power adjustment range –20 – 4 dBm
Default output power – 4.0 – dBm
Output power variation – 2.0 – dB
Adjacent Channel Power
|M – N| = 2 – – –20 dBm
|M – N| 3– – –30dBm
Out-of-Band Spurious Emission
30 MHz to 1 GHz – – –36.0 dBm
1 GHz to 12.75 GHz – – –30.0 dBm
1.8 GHz to 1.9 GHz – – –47.0 dBm
5.15 GHz to 5.3 GHz – – –47.0 dBm
LO Performance
Initial carrier frequency tolerance – – ±150 kHz
Frequency Drift
Frequency drift – – ±50 kHz
Drift rate – – 20 kHz/50 µs
Frequency Deviation
Average deviation in payload
(sequence used is 00001111)
225 – 275 kHz
Maximum deviation in payload
(sequence used is 10101010)
185 – – kHz
Channel spacing – 2 – MHz
Timing and AC CharacteristicsBCM20732 Data Sheet
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February 16, 2016 • 53CS20732-DS105-R Page 35
Timing and AC Characteristics
In this section, use the numbers listed in the Reference column of each table to interpret the following timing
diagrams.
UART Timing
Figure 10: UART Timing
Table 17: UART Timing Specifications
Reference Characteristics Min Max Unit
1 Delay time, UART_CTS_N low to UART_TXD valid – 24 Baud out cycles
2 Setup time, UART_CTS_N high before midpoint of stop bit – 10 ns
3 Delay time, midpoint of stop bit to UART_RTS_N high – 2 Baud out cycles
Timing and AC CharacteristicsBCM20732 Data Sheet
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February 16, 2016 • 53CS20732-DS105-R Page 36
SPI Timing
The SPI interface supports clock speeds up to 12 MHz with VDDIO 2.2V. The supported clock speed is 6 MHz
when 2.2V > VDDIO 1.62V.
Figure 11 and Figure 12 on page 37 show the timing requirements when operating in SPI Mode 0 and 2, and
SPI Mode 1 and 3, respectively.
Figure 11: SPI Timing – Mode 0 and 2
Table 18: SPI Interface Timing Specifications
Reference Characteristics Min Typ Max
1 Time from CSN asserted to first clock edge 1 SCK 100
2 Master setup time – ½ SCK –
3 Master hold time ½ SCK – –
4 Slave setup time – ½ SCK –
5 Slave hold time ½ SCK – –
6 Time from last clock edge to CSN deasserted 1 SCK 10 SCK 100
Timing and AC CharacteristicsBCM20732 Data Sheet
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February 16, 2016 • 53CS20732-DS105-R Page 37
Figure 12: SPI Timing – Mode 1 and 3
BSC Interface Timing
Table 19: BSC Interface Timing Specifications
Reference Characteristics Min Max Unit
1 Clock frequency – 100 kHz
400
800
1000
2 START condition setup time 650 – ns
3 START condition hold time 280 – ns
4 Clock low time 650 – ns
5 Clock high time 280 – ns
6 Data input hold timea
a. As a transmitter, 300 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid
unintended generation of START or STOP conditions.
0 – ns
7 Data input setup time 100 – ns
8 STOP condition setup time 280 – ns
9 Output valid from clock – 400 ns
10 Bus free timeb
b. Time that the cbus must be free before a new transaction can start.
650 – ns
3
SPI_CSN
SPI_CLK
(Mode 1)
SPI_MOSI -Invalid bit
SPI_MISO Not Driven Invalid bit
First bit
First bit
Last bit
Last bit
1
2
6
-
Not Driven
SPI_CLK
(Mode 3)
54
ESD Test ModelsBCM20732 Data Sheet
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February 16, 2016 • 53CS20732-DS105-R Page 38
Figure 13: BSC Interface Timing Diagram
ESD Test Models
ESD can have serious detrimental effects on all semiconductor ICs and the system that contains them.
Standards are developed to enhance the quality and reliability of ICs by ensuring all devices employed have
undergone proper ESD design and testing, thereby minimizing the detrimental effects of ESD. Three major test
methods are widely used in the industry today to describe uniform methods for assessing ESD immunity at
Component level, Human Body Model (HBM), Machine Model (MM), and Charged Device Model (CDM). The
following standards were used to test this device:
Human-Body Model (HBM) – ANSI/ESDA/JEDEC JS-001-2012
The HBM has been developed to simulate the action of a human body discharging an accumulated static charge
through a device to ground, and employs a series RC network consisting of a 100 pF capacitor and a 1500
(Ohm) resistor. Both positive and negative polarities are used for this test. Although, a 100 ms delay is allowable
per specification, the minimum delay used for testing was set to 300 ms between each pulse.
Machine Model (MM) – JEDEC JESD22-A115C
The MM has been developed to simulate the rapid discharge from a charged conductive object, such as a
metallic tool or fixture. The most common application would be rapid discharge from charged board assembly
or the charged cables of automated testers. This model consists of a 200 pF capacitor discharged directly into
a component with no series resistor (0). One positive and one negative polarity pulses are applied. The
minimum delay between pulses is 500 ms.
ESD Test ModelsBCM20732 Data Sheet
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February 16, 2016 • 53CS20732-DS105-R Page 39
Charged-Device Model (CDM) - JEDEC JESD22-C101E
CDM simulates charging/discharging events that occur in production equipment and processes. The potential
for a CDM ESD events occurs when there is metal-to-metal contact in manufacturing. CDM addresses the
possibility that a charge may reside on the lead frame or package (e.g., from shipping) and discharge through
a pin that subsequently is grounded, causing damage to sensitive devices in the path. Discharge current is
limited only by the parasitic impedance and capacitance of the device. CDM testing consists of charging
package to a specified voltage, then discharging the voltage through relevant package leads. One positive and
one negative polarity pulse is applied. The minimum delay between pulses is 200 ms.
Results Summary
ESD Test Voltage Level Results:
• HBM +/– 2KV PASS
• CDM +/– 500V PASS
• MM +/– 150V PASS
Mechanical InformationBCM20732 Data Sheet
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February 16, 2016 • 53CS20732-DS105-R Page 40
Section 4: Mechanical Information
Figure 14: 32-Pin 5x5 mm QFN Package
Mechanical InformationBCM20732 Data Sheet
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February 16, 2016 • 53CS20732-DS105-R Page 41
Ta b l e 20 provides dimensions and additional details on the 32-pin 5x5 mm QFN package.
Table 20: 32-pin 5x5 mm QFN Package Dimensions (Footprint: 0.80)
S/N SYM Dimension Comments/Specifications
1 A 0.900 ±0.100 Overall Height
General tolerance: Distance: ±0.100
Angle:
2 A1 0.020 ±TBD Standoff
Matte finish on package body surface, except ejection
and pin 1 marking.
Ra 0.3 ~ 1.2 m
3 D 5.000 ±0.100 Package Length
Frame base metal thickness 0.203 base
4 E 5.000 ±0.100 Package Width
All molded body sharp corner radii; unless otherwise
specified.
R0.200 (maximum)
5 L 0.400 ±0.075 Foot Length
Drawing does not include plastic or metal protrusion of
cutting burr.
6 T 0.203 Ref. Frame Thickness
Compliant to JEDEC standard: MO-220.
7 b 0.250 ±0.050 Lead Width
8 e 0.500 Base Lead Pitch
Mechanical InformationBCM20732 Data Sheet
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February 16, 2016 • 53CS20732-DS105-R Page 42
Tape Reel and Packaging Specifications
The top left corner of the BCM20732 package is situated near the sprocket holes, as shown in Figure 15.
Figure 15: Pin 1 Orientation
Table 21: BCM20732 5 × 5 × 1 mm QFN, 32-Pin Tape Reel Specifications
Parameter Value
Quantity per reel 2500 pieces
Reel diameter 13 inches
Hub diameter 7 inches
Tape width 12 mm
Tape pitch 8 mm
Pin 1: Top left corner of package toward sprocket holes
Ordering InformationBCM20732 Data Sheet
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Section 5: Ordering Information
Table 22: Ordering Information
Part Number Package Ambient Operating Temperature
BCM20732A1KML2G 32-pin QFN –30°C to +85°C
Acronyms and AbbreviationsBCM20732 Data Sheet
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Appendix A: Acronyms and Abbreviations
The following list of acronyms and abbreviations may appear in this document.
Term Description
ADC analog-to-digital converter
AFH adaptive frequency hopping
AHB advanced high-performance bus
APB advanced peripheral bus
APU audio processing unit
ARM7TDMI-S Acorn RISC Machine 7 Thumb instruction, Debugger, Multiplier, Ice, Synthesizable
BSC Broadcom Serial Control
BTC Bluetooth controller
COEX coexistence
DFU device firmware update
DMA direct memory access
EBI external bus interface
HCI Host Control Interface
HV high voltage
IDC initial digital calibration
IF intermediate frequency
IRQ interrupt request
JTAG Joint Test Action Group
LCU link control unit
LDO low drop-out
LHL lean high land
LPO low power oscillator
LV LogicVision
MIA multiple interface agent
PCM pulse code modulation
PLL phase locked loop
PMU power management unit
POR power-on reset
PWM pulse width modulation
QD quadrature decoder
RAM random access memory
RF radio frequency
ROM read-only memory
RX/TX receive, transmit
SPI serial peripheral interface
Acronyms and AbbreviationsBCM20732 Data Sheet
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February 16, 2016 • 53CS20732-DS105-R Page 45
SW software
UART universal asynchronous receiver/transmitter
UPI µ-processor interface
WD watchdog
Term Description
Phone: 949-926-5000
Fax: 949-926-5203
E-mail: info@broadcom.com
Web: www.broadcom.com
Broadcom Corporation
5300 California Avenue
Irvine, CA 92617
© 2016 by BROADCOM CORPORATION. All rights reserved.
53CS20732-DS105-R February 16, 2016
Broadcom® Corporation reserves the right to make changes without further notice to any products or
data herein to improve reliability, function, or design.
Information furnished by Broadcom Corporation is believed to be accurate and reliable. However,
Broadcom Corporation does not assume any liability arising out of the application or use of this
information, nor the application or use of any product or circuit described herein, neither does it
convey any license under its patent rights nor the rights of others.
BCM20732 Data Sheet
®