APPLICATION NOTE TV EAST/WEST CORRECTION CIRCUITS SUMMARY Page I GENERAL PRINCIPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 I.1 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 I.2 DIODE MODULATOR PRINCIPLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 I.3 PULSE-WIDTH MODULATOR PRINCIPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 I.4 GENERAL CONSIDERATIONS TO GENERATE THE CORRECTION PARABOLA . . . 7 I.5 I.5.1 I.5.2 I.5.3 I.6 ADJUSTMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Horizontal size adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin cushion correction adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trapezium correction adjustment (keystone correction) . . . . . . . . . . . . . . . . . . . . . . . . . PRODUCTS PRESENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 9 9 11 11 II TEA2031A GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 II.1 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 II.2 II.2.1 II.2.1.a II.2.1.b II.2.1.c II.3 II.3.1 II.3.2 II.4 II.4.1 II.4.1.a II.4.1.b II.4.1.c II.4.1.d II.4.2 II.5 II.5.1 II.5.2 II.6 PARABOLA GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplier stage operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation without keystone correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation with keystone correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example of applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LINE SAWTOOTH GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Role of resistors R7, R8, RT1 and D2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Role of diode D1 and capacitor C3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OUTPUT STAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation of the output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output in the low stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output in the high stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output with commutation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conclusion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation in association with the diode modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SELECTION OF THE VALUES OF CAPACITORS C2 AND C3. . . . . . . . . . . . . . . . . . . Selection of C3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Selection of C2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . APPLICATION EXAMPLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 13 13 13 15 15 15 16 17 17 18 18 19 19 20 20 21 21 III TDA4950 - TDA8145 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 III.1 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 III.2 III.3 DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . APPLICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 24 AN393/1193 1/32 TV EAST/WEST CORRECTION CIRCUITS SUMMARY (continued) Page IV TDA8146 GENERAL DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 IV.1 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 IV.2 INPUT AMPLIFIER AND RECTIFIER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 IV.3 VERTICAL CLAMPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 IV.4 REFERENCE AND STARTING CIRCUIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 IV.5 PARABOLA GENERATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 IV.6 PULSE-WIDTH MODULATOR AND OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 IV.7 APPLICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V TDA8147 GENERAL DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 V.1 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 V.2 INPUT AMPLIFIER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 V.3 VOLTAGE REFERENCE AND STARTING CIRCUIT. . . . . . . . . . . . . . . . . . . . . . . . . . . 31 V.4 PWM MODULATOR AND OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 V.5 APPLICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 I - TV EAST/WEST CORRECTION GENERAL PRINCIPLES I.1 - INTRODUCTION Figure 1 : All color picture tubes which are used in the present TV-sets have a magnetic deflection system. Using a homogenous magnetic field, we have generally a pillow-distortion of a rectangular picture on the screen. This is mainly due to the tangens relation between the deflection angle and the beam position on the screen Using a well dimensioned and optimized inhomogenous magnetic deflection field, this distortion can be eliminated completely for picture tubes with a deflection angle of 90o. In the same way the pillowdistortion of 110o deflection tubes can be eliminated in the vertical direction (North-South direction). But until now the distortion in the horizontal direction (East-West direction) can not eliminated with special designed deflection yokes. A distortion remains in Figure 1. In order to compensate this effect, the horizontal deflection current in the yoke must be modulated. This means a large amplitude of the deflection current in the middle of the screen and a small amplitude on the top and the bottom of the screen. The general behaviour of the deflection currents is illustrated in Figure 2. In this picture TV and TH are the time periods for the vertical and the horizontal deflection. Note that the envelope of the horizontal yoke current must be a parabola with the same phase as the vertical saw-tooth current. This means an East/West correction can be reached by modulating the horizontal yoke current with a parabola. There are different possibilities to modulate the yoke current. The most convenient modulator is the so-called Diode Modulator described in the next chapter. 2/32 AN393-01.EPS Test Grid on a 110o Color Tube TV EAST/WEST CORRECTION CIRCUITS Figure 2 : Horizontal and Vertical Yoke Current (TH = 64s, TV = 20ms) I YOKE horizontal t TH I YOKE vertical AN393-02.EPS t TV I.2 - DIODE MODULATOR PRINCIPLE For the sake of simplicity, the electronic switches (diodes and transistors) are drawn as simple switches S1 and S2. The deflection time TH of 64s can be divided in two parts : the scan time TS at which the electronic switches S1 and S2 are closed and the flyback time TF (S1 and S2 opened). The total time period is the Let us consider the basic circuit of the horizontal deflection unit as shown in Figure 3. Figure 3 : Basic Circuit of the Horizontal Deflection Power Stage including Modulator TH = TF + TS LTR VLTR VLY LY CY S1 LM CM S2 We assume now that the line transformer LTR have a neglectable high inductance and the time behaviour is mainly determined by LY, LM, CY, CM. Small modifications are necessary to consider also the electrical characteristics of LTR, but they should not be discussed here. During the scan time the inductors LY and LM are directly connected to the voltage sources V0 and VM : I LY Line transformer VLM I LM VLY = V0 - VM VLM = VM VM LY : line yoke LM : modulator coil VM : modulator voltage V0 : supply voltage S1 and S2 : electronic switches S1 and S2 closed (scan time) (1.2) (1.3) Neglecting any power consumption in possible series resistors, the current in the two inductors increases linear in time : AN393-03.EPS V0 (1.1) t (V0 - VM) LY t VM iLM = LM iLY = (1.4) (1.5) 3/32 TV EAST/WEST CORRECTION CIRCUITS Since the current iLY and iLM must be zero-symmetrical (average value = 0), the peak value of iLY and iLM is obtained after half of the scan time TS/2 ^iLY = TS (V0 - VM) (1.6) ^iLM = TS VM 2 LM (1.7) 2 LY (1.8) LY CY = LM CM = L C (1.8) Under this condition, both capacitors CY and CM have its peak voltage at the half of the flyback time TF/2. The energy in the inductors stored at the end of the scan period 1 L (iL)2 is then 2 (1.9) 1 C (VC)2 2 (1.10) Under this condition, we obtain the general equation for the peak voltage in the middle of the flyback Figure 4 : (1.11) V0 - VM TS ^ ^ + (V0 - VM) VLY = VCY = - LY CY 2 TS = (V0 - VM) (1 - ) 2 L C (1.12) in the same way (1.7 and 1.11) we obtain ^ ^ VLM = VCM = VM (1 - TS 2 L C ) (1.13) The resulting peak voltage during the flyback time at the line transformer is then TS ^ ^ ^ VLTR = - VLY - VLM = V0 ( - 1) 2 L C (1.14) Please note that in this circuit, the horizontal flyback voltage VLTR (1.14) is independent from the modulation voltage VM, though the yoke current ILY can be changed via the modulator voltage VM (see 1.6) completely transformed into the capacitor EC = ^ VC = - ^iL CL + Vinit This voltage is the addition of the initial voltage and the voltage increase due to the energy transfer. With (1.6) and (1.11) we get After this time, S1 and S2 are opened and the energy in the inductors LY and LM changes to the capacitors CY and CM. We assume now the same resonance frequency for both LC parts EL = period An overview of the currents and voltages is given in Figure 4. Currents and Voltages of the Basic Circuit ILY VM t TS VM VLY TF t VM VLTR TS 2 - 1) LC t - V0 4/32 independent from V M AN393-04.EPS V0 ( TV EAST/WEST CORRECTION CIRCUITS For a practical application, a large capacitor CS can be inserted in series to the yoke to get an S-correction of the deflection current ILY. Simultaneously, the voltage VM can be grouded to have a simpler handling of the modulator driver. The switch S1 is a standard high voltage power transistor (e.g. BU508A or S2000AFI), the switch S2 can be replaced by 2 diodes as shown in Figure 5. Normally, the current IM into the modulator voltage source is positive and VM must only be realized as a variable resistor (e.g. transistor TM). Many manufacturers use this simple diode modulator with such active load. A disadvantage of this application is the power consumption in the power transistor TM (~2W). Under ideal conditions, VM Figure 5 : should have no power consumption (average iM = 0), but in practice the coils and the line transformer are not free from parasitic resistors. Furthermore a reasonably large power is used from the various loads on the line transformer. An improvement from the power consumption point of view is the use of a switched power stage VM. For this purpose, an additional inductance LS (5...20mH) is used and connected as shown in Figure 6. Point A is biased from a pulse-width modulated rectangular wave. The frequency is arbitrary, for a simple pulse-width modulator, The horizontal line frequency is used normally. Standard Diode Modulator with Class-A Modulator Driver Line transformer CS V0 LY CY LM CM e.g. BU508A or S2000AFI AN393-05.EPS IM VM TM Standard Diode Modulator with Class D Modulator Driver (pulse-width modulator) Line transformer CS V0 LY CY LM CM LS IS VA AN393-06.EPS Figure 6 : t A 5/32 TV EAST/WEST CORRECTION CIRCUITS I.3 - PULSE-WIDTH MODULATOR PRINCIPLE The pulse-width modulator for driving the diode modulator contains mainly one power comparator with the external circuitry shown in Figure 7. The working frequency is determined by the linear saw-tooth voltage biasing the positive comparator input. It is generated by the flyback pulses of the line transformer. The current sink on the positive input discharges the capacitor CS during the scan time TS and yields the negative slope of the sawtooth voltage. The negative input is biased from a parabola voltage, its generation is discussed later. To improve the performance of this pulse-width modulator, a feedback path RK is provided compensating variations in the power supply VCC of the comparator. The capacitor CK together with Rin and RK serves as a low-pass filter to suppress the line frequency coming from the comparator output. If the current IS in the inductor LS (see Figures 6 and 7) is only positive, the output stage can have a simple darlington transistor and a diode as seen Figure 7 : in Figure 8. If the darlington stage is switched on, the current IS is flowing through TA and TB into ground. Otherwise, the diode D is conducting and IS flows into the supply voltage. The power, consumed normally in LM (see Figure 5) is then redelivered into this supply voltage. A greater flexibility in the design of the diode modulator can be reached, if the current IS is allowed to have negative values. For this case, the comparator power stage must be realized as push-pull stage (see Figure 9). Due to the voltage drop across the transistors and diodes, the transition from positive values IS and negative values IS yields a voltage step on the output as illustrated in Figure 10. In this case the steps in the output voltage produce an additional undesired modulation of the yoke current. Then you can see some irregularities in the vertical lines of the test grid on the screen. With the aid of a reasonable large fedback factor (small RK, small CS, large parabola amplitude) this effect becomes neglectable. Pulse-width Modulator Vpar VCC t I YOKE vertical to diode modulator LS RK IS t VOUT Rin CK CS 6/32 + t VOUT flyback pulses from the line transformer AN393-07.EPS Vpar TV EAST/WEST CORRECTION CIRCUITS Figure 8 : Comparator Output Stage, only positive modulator current IS is allowed Figure 9 : Comparator Output Push-pull Stage, negative and positive modulator current IS allowed VCC D VCC IS LS to diode modulator + OUT TA + IS LS AN393-09.EPS AN393-08.EPS TB Figure 10 : Voltage on the comparator output by zero crossing of IS VOUT VCC t AN393-10.EPS IS t I.4 - GENERAL CONSIDERATIONS TO GENERATE THE CORRECTION PARABOLA The correction parabola which drives the pulsewidth modulator (Figure 7) must have the same frequency and phase as the vertical deflection current in the yoke. Therefore, the parabola can be generated directly from the vertical saw-tooth signal which drives the deflection output stage. Principally there are two different kinds for generating the parabola: a) integrator-network (linear) b) functional-network (non linear) Let us consider first the integration method : The vertical saw-tooth signal can be described with the following simple equation, valid for one period Ssaw-tooth (t) = A t TV 0 < t < TV (1.15) where A is the amplitude, TV the time period and t the time. Integrating this signal we get t t t A 0 Ssaw-tooth (t) dt = 0 A TV dt = 2 TV t 2 (1.16) Since the relation between the current and the voltage on a capacitor is given by VC (t) = iC (t) dt (1.17) the parabola can be obtained directly from the coupling capacitor CY in the vertical output stage as illustrated in Figure 11. Due to the aging and the temperature dependence of this (electrolytic) capacitor CY, some manufacturers prefer to generate the parabola from the voltage drop across RY (VRY) with the aid of a separate integrator. 7/32 TV EAST/WEST CORRECTION CIRCUITS Figure 11 : Vertical Output Stage and Corresponding Voltages VC i Yoke Vertical Yoke DC - feedback CY VC VRY RY VRY AN393-11.EPS AC - feedback TV Due to the small amount of active and passive components, this integration method is the usual method to realize the East/West correction circuit with discrete elements. The functional network realization requires a quite larger amount of active components and is therefore especially suited for integrated circuits. The input signal for this kind of parabola generation is also the vertical saw-tooth signal corresponding to (1.15). With the aid of a functional (square) network, the square of this signal can be formed according to the following equation : Sparabola = k (Ssaw-tooth - S0)2 t = k (A - A0)2 TV (1.18) and is illustrated in Figure 12. Thereby, k is the gain and A0 is a DC-level which allows to adjust the symmetry of the parabola ("trapezoidal" or "keystone" correction). Comparing the two methods, the following properties are evident : - the parabola amplitude using the integration method is frequency dependent : assuming a constant amplitude of the saw-tooth signal, the amplitude of the parabola is linear in the time period TV (see 1.16) . This means different adjustments between 50 and 60Hz TV-sets. The funct i ona l (sq uar e) met h od g ives a frequency-independent amplitude of the parabola, if a constant saw-tooth signal is provided. - during the flyback time of the saw-tooth signal, the functional network produces a second (parasitic) parabola as shown in Figure 12 Figure 12 : Generation of the Parabola with Functional Network S saw-tooth A0 t t 8/32 AN393-12.EPS Sparabola TV EAST/WEST CORRECTION CIRCUITS I.5 - ADJUSTMENTS I.5.1 - Horizontal size adjustment Adjustment of horizontal amplitude is made by modifying the mean cyclic ratio (duty factor) of the output pulses. When this mean cyclic ratio is minimum, the picture width is maximum, because the output is more frequently in the low state, and therefore the highest current is drawn from the diode modulator and the deflection current is maximum. To change the mean cyclic ratio of the pulse train (in addition to the change due to the parabolic shape of the signal) it is necessary to change the continuous level of the sawtooth pulse train (see Figure 14). The rise of the continous level of the parabola is due to the increase of the cyclic ratio, as we have seen above. The value of pincushion correction is not modified since the parabola peak-to-peak amplitude is kept the same. Only the mean cyclic ratio varies, i.e. also the horizontal scan width. I.5.2 - Pincushion correction adjustment Pincushion correction is made by varying the peakto-peak amplitude of the parabola. The greater this amplitude,the greater the variation of the output signal cyclic ratio is between the ends and the top of the parabola, and therefore the more important is the parabolic modulation of the current drawn from the diode modulator (see Figure 15). Figure 13 : Modified parabola : constant during the flyback time i Yoke t Vpar t 9/32 AN393-13.EPS Although this parasitic parabola is present during the vertical flyback time (dark screen) this small parabola (like a spike) produces a damped oscillation of the diode modulator. The result is a damped sinusoidal vertical line on the top of the screen, if a test-grid is on the screen (the vertical lines are similar to a crutch-stick). The maximum amplitude of this oscillation is present on the left and right top of the screen. Though its amplitude is normally only about 3mm, this effect must be suppressed. This can be reached by two different methods : - the linear saw-tooth voltage generating the parabola must have an extremely small flyback time. Then the very small parasitic parabola is integrated in the capacitor CK of the comparator and has no effect (see Figure 7). The saw-tooth voltage coming from the vertical oscillator fulfills this requirement wherefore the deflection yoke-current has a too large flyback time. - another possibility is to hold the parabola signal constant during the flyback time as illustrated in Figure 13. This behaviour can be reached by providing a parabola output limitation and then overmodulating the functional network during the flyback time. Overcoming the problems of the parasitic parabola, the functional method should be preferred due to the independence of the frequency (50/60Hz compatibility). The nonlinearity which forms the parabola can be realized in two different ways : - use of an analog multiplier - forming a nonlinear network by piece wise linearization. TV EAST/WEST CORRECTION CIRCUITS Figure 14 : Horizontal Size Adjustment Line sawtooth signal and vertical parabola t PWM output signal t Deflection current Broad picture AN393-14.EPS t Narrow picture Figure 15 : Pincushion Correction Adjustment Line sawtooth signal and vertical parabola t PWM output signal t Deflection current Slight pincushion correction 10/32 Pronounced pincushion correction AN393-15.EPS t TV EAST/WEST CORRECTION CIRCUITS I.5.3 - Trapezium correction adjustment (keystone correction) Trapezium correction is made by modifying the symmetry of the left and right sides of the parabola (Figure 16). Figure 16 : Keystone Correction Line sawtooth signal and vertical parabola t PWM output signal t Deflection current t Bottom of picture Picture broad at top and narrow at bottom Top of picture Bottom of picture AN393-16.EPS Top of picture Picture narrow at top and broad at bottom I.6 - PRODUCTS PRESENTATION All the East/West correction devices are with class D diode modulator driver. Concerning the frame parabola generation, TDA4950, TDA8145 and TDA8146 use a non-linear network whereas TEA2031A uses an analog multiplier. TDA4950 and TDA8145 generate a parabola with a fixed shape; this shape is different between the two devices and makes the TDA4950 intended for standard CRT and TDA8145 for square tubes. These two devices have a parasitic parabola suppression (during vertical flyback time) by current limitation. TDA8146 has a programmable parabola shape generation by segments which makes it suitable for different CRTs. It has also a parasitic parabola suppression by pulse during vertical flyback. All the devices can support a keystone correction adjustment (parabola symmetry) and have 50/60Hz capability. Some others adjustments are possible (picture width...). Finally, another available device the TDA8147 has been designed for use in the East/West pincushion correction by driving a diode modulator but since this device has not the parabola generator and is drived by a PWM, it is very useful in digital TV-sets. A detailed description about all the devices is done in the next chapters. 11/32 TV EAST/WEST CORRECTION CIRCUITS multiplier and applied on its -input (Pin 7). An output stage that can absorb or deliver current and comprises a diode connected to the DC voltage supply in order to limit the voltage applied on the output terminal during line flyback. This stage enables the diode modulator of the line scan circuit to be driven directly with a maximum current of 0.5A. This maximum current that the output can absorb is not limited by the size of the transistors but by the maximum power dissipated by the package (Minidip). II - TEA2031A GENERAL DESCRIPTION II.1 - INTRODUCTION The TEA2031A circuit comprises (see Figure 17) : an analog multiplier that uses a frame sawtooth signal applied on Pin 1 so that the current on Pin 7 has a parabolic modulation. This multiplier operates in current differential mode and uses a reference DC voltage, selected according to the continuous level of the sawtooth voltage, and applied on Pin 2. The level of this DC voltage also serves to correct trapezium distortion. - a reference voltage available on Pin 3 that can be used (via a voltage divider) to provide input 2 of the multiplier with a reference voltage. - a current generator, producing a line frequency sawtooth signal by integrating the line flyback signal and generating current available on Pin 8. - a comparator controlling the output stage by using the line sawtooth signal applied on its +input (Pin 8) and the parabolic signal generated by the II.2 - PARABOLA GENERATION Using a fixed continuous current and a vertical sawtooth current, the multiplier generates an output current on Pin 7 with parabolic modulation. II.2.1 - Multiplier stage operation The multiplier inputs (Pins 1 and 2) operate in current differential mode (Figure 18). Figure 17 : Block Diagram 8 7 6 VCC 50A 5 Comparator 120A K . (I 1 - I 2) 2 MULTIPLIER I1 I2 1 12/32 2 6.3V 3 4 TEA2031A AN393-17.EPS VREF TV EAST/WEST CORRECTION CIRCUITS Figure 18 : Multiplier Stage VCC TEA2031A I 7DC 0V I7 7 0A 2 K (L1 - L2) I2 1 R1 R5 V REF = 6.5V VREF I1 V7 I3 2 R2 3 R3 V1 AN393-18.EPS VDC 0V The output current is given by : i7 = i7DC - k (i1 - i2)2 i7DC and k depend on the current reference on Pin 3. Remarks : As we can see, the two inputs can be inverted and the slope of the sawtooth has no influence on the parabola shape. II.2.1.a - Operation without keystone correction In order to eliminate supply and thermal drift influences, R1 is taken equal to R2. In this case, V1DC = V2DC (Figure 19). II.2.1.b - Operation with keystone correction In order to correct keystone correction, V2 voltage becomes adjustable. In this case, the parabola shape presents a dissymmetry (Figure 20). II.2.1.c - Example of applications 1. Sawtooth coming from the horizontal:vertical processor (e.g. TDA8185, TEA2028B, ...) In this case, V1DC = 2.5V (Figure 21). For practical reason, the DC voltage comes from internal voltage reference.Impedance value seen between Pin 3 and ground must be 22k for best conditions of operation (to have the good internal current reference). 2. Sawtooth coming from the vertical output stage (Figure 22) 1 In this caseV1DC = 0V and R1 = R2 + RT2 2 13/32 TV EAST/WEST CORRECTION CIRCUITS Figure 19 : Operation without Keystone Correction Figure 20 : Operation with Keystone Correction V1 V1 4V 4V 3V 2.5V 2V 3V 2.5V 2V V2 1V 1V t 0 10ms t 20ms 0 V7 10ms 20ms V7 V7H V7H V2 = V1 DC = 2.5V V7A V2 = 3V V7L1 V7L2 t 0 10ms AN393-19.EPS V2 V7L V7B V1 DC V2 = 2V t 0 10ms AN393-20.EPS V2 Figure 21 : Sawtooth coming from H/V Processor TEA2031A 1 2 39k 3 39k + 3.8V 4 10k I 3 Reference + 2.5V 3V 2V 4.7k AN393-21.EPS Typical Frame Saw-tooth Keystone Adjustment 3.9k + 1.2V 0V Figure 22 : Sawtooth coming from Vertical Output Stage TEA2031A Vertical Yoke 2 I1 3 I2 R1 R2 R T2 14/32 4 I3 R3 22k AN393-22.EPS 1 0V TV EAST/WEST CORRECTION CIRCUITS supply. II.3 - LINE SAWTOOTH GENERATION The line sawtooth signal is applied as a reference at the +input terminal of the comparator. It is obtained by integrating the line flyback and the constant current discharge of capacitor C3 in Pin 8 (Figure 23). II.3.2 - Role of diode D1 and capacitor C3 During line flyback, diode D1 rapidly charges capacitor C3 at the potential available on the slide contact of RT1. Then during line scanning, D1 is blocked and C3 is discharged at constant current (about 50A) through Pin 8. The peak-to-peak amplitude of the line frequency sawtooth signal obtained in this way depends directly on the value of capacitor C3 since it is defined by the discharge current of the capacitor and the line period (Figure 24). This amplitude can be calculated using the following equation : dt i8 V8 (peak-to-peak) = C3 where Dt = duration of line and i8 = current in Pin 8. The continuous level of this sawtooth signal is set by adjusting potentiometer RT1 (Figure 25). II.3.1 - Role of resistors R7, R8, RT1 and D2 By means of the voltage divider bridge comprising resistors R7, RT1 and R8, a signal that is the image of the line flyback signal applied on R7, is obtained on the slide contact of potentiometer RT1. The peak amplitude of this signal depends on the nominal voltage of the Zener diode D2 and on the adjustment of RT1. The role of Zener diode D2 is to maintain a constant amplitude of the signal on the slide contact of RT1 whatever the variations in amplitude of the line flyback signal. This diode D2 can be also replaced by a single diode connected to a regulated 12V or 15V power Figure 23 : Line Sawtooth Generation Line Flyback (16kHz) R7 Parabola (50Hz) Line Sawtooth D2 I8 RT1 I7 D1 8 7 C3 Output AN393-23.EPS R8 TEA2031A 15/32 TV EAST/WEST CORRECTION CIRCUITS Figure 24 : Peak-to-peak Amplitude of Sawtooth Signal versus Two Different Values of C3 (with RT1 = constant) C3 = 10nF C3 = 3.3nF Line Flyback Voltage on RT1 Slide Contact Sawtooth Signal on C3 Same Peak Level 250mV 0.8V 0V t Line Flyback Voltage on R7 t AN393-24.EPS 0V Figure 25 : Continuous Level of Swatooth Signal for Two Different Adjustments of RT1 11s 53s Voltage on RT1 Slide Contact 0V II.4 - OUTPUT STAGE The output stage is controlled by the comparator fed by signals applied on its inputs, i.e. the sawtooth signal at line frequency on +input (Pin 8) and the parabola at vertical frequency on -input (Pin 7) (see Figure 26). The comparison between the 50Hz parabola and the sawtooth signal at line frequency (16kHz) pro- 16/32 Continuous Level t duces pulses at line frequency with a duty cycle that is modulated at vertical frequency. This allows, by means of the diode modulator, the modulation of the line scanning current during each field period in order to carry out the pincushion correction (or East/West correction) (see Figure 27). The role of the filter C2 and RT3 + R6 is to suppress the line frequency of the feedback output signal. AN393-25.EPS Sawtooth Wave on C3 TV EAST/WEST CORRECTION CIRCUITS Figure 26 : Output Stage R5 RT3 I R5 I5 C2 I C2 V CC R6 I7 8 I8 7 6 5 I7 AN393-26.EPS I8 TEA2031A Figure 27 : PWM Output Signal (with adaptation of time scales) Input Pin 7 Input Pin 8 64s 20ms Continuous Level 0V t 0V AN393-27.EPS Output Pin 5 t II.4.1 - Operation of the Output Stage RT3 value is minimum. The operation of the output stage can be considered as 3 separate cases according to the 3 possible states of output Pin 5. II.4.1.a - Output in the low state (Figure 28) In this case resistances R6 and RT3 are connected to the ground, therefore they are in parallel with R5, according to the following diagram. The continuous level and the peak-to-peak amplitude of the parabola are at their minimum when the It is possible to calculate the voltage for a given point of the parabola (Pin 7) using the following equation : V7b = i7 R5 (R6 + RT3) R5 + R6 + RT3 The capacitance of C2 is neglected as this capacitor is equivalent to an open-circuit at vertical frequency. 17/32 TV EAST/WEST CORRECTION CIRCUITS Figure 28 : Output in Low State R6 RT3 R5 0V C2 V CC Output Low State 0V V7 I7 8 7 6 5 V8 < V 7 0V Saturated AN393-28.EPS t TEA2031A nected and constitutes a filter with R6 and RT3. The preceding signal is filtered and is transformed into the signal shown in Figure 31. The 16kHz line frequency component has disappeared in the signal and only the 50Hz parabola remains, but slightly modulated at line frequency by the C2 charge when the output is in the high state, and by the C2 discharge when the output is in the low state; this gives a tiny triangular modulation signal. II.4.1.b - Output in the high state In this case, resistances R6, RT3 and R5 form a voltage divider bridge which returns on Pin 7 and capacitor C2 part of the continuous voltage available on the output terminal that is added to the parabola voltage. The equivalent circuit diagram is the following : see Figure 29. It is possible to calculate the voltage for a given point of the parabola (Pin 7) with the following equation : V7h = i7 So the continuous level of the parabola depends only on the cyclic ratio of the output pulse train. This level can be calculated by means of the following equation : Vmean = M V7h + (1 - M) V7b R5 (R6 + RT3) R5 + V5 R5 + R6 + RT3 R5 + R6 + RT3 II.4.1.c - Output with commutation In this case and if capacitor C2 is eliminated, Figure 30 gives the signal obtained on Pin 7. It corresponds exactly to the levels and amplitudes of the parabolas for output in the high state and the low state, linked by 16kHz commutations. In normal circuit configuration, capacitor C2 is con- where M : output pulse cyclic ratio V7h : mean level on Pin 7, output blocked in the high state V7l : mean level on Pin 7, output blocked in the low state Figure 29 : Output in High State R5 R6 High State Output RT3 C2 I5 V CC V7 I7 V8 < V 7 7 6 5 VCC - 1 V D Continuous level is maximum when RT3 is minimum 0V TEA2031A 18/32 t AN393-29.EPS 8 TV EAST/WEST CORRECTION CIRCUITS Figure 30 : Output with Commutation (without C2) V7 Parabola level for high state output 16kHz commutations 20ms 0V AN393-32.EPS Parabola level for low state output t Figure 31 : Output with Commutation (with C2) V7 0V We see that, when the cyclic ratio increases, the continuous level of the parabola also increases and approaches its maximum level when the output is in the high state. Conversely, when the cyclic ratio decreases, the continuous level of the parabola also decreases since it approaches its minimum continuous level when the output is in the low state. II.4.1.d - Conclusion For a given parabolic current i7, the parabola peakto-peak amplitude depends only on resistance values R5,R6 and RT3. Therefore by adjusting RT3, it is possible to obtain a more or less pronounced parabola and so adjust the importance of pincushion correction. AN393-31.EPS Mean continuous level as a function of the cyclic ratio of the output pulses t The continuous level of the parabola depends principally on the mean cyclic ratio at the output, and much less on the adjustment of RT3. II.4.2 - Operation in association with the diode modulator (see Figure 32) In the majority of cases, the system operates by drawing more or less high current from the modulator through the connecting inductor. The current through terminal Pin 5 of TEA2031A is entering into the circuit. It flows, either to the ground when the output is in the low state, or to VCC through the internal diode when the output is in the high state and the output voltage tends to exceed VCC. The circuit can also produce current. 19/32 TV EAST/WEST CORRECTION CIRCUITS Figure 32 : Operation with Diode Modulator HT Line Flyback VCC EHT LS LY 8 7 6 5 VCC comp LM TEA2031A 2 3 4 AN393-32.EPS 1 Figure 33 : Output Oscillagrams II.5 - SELECTION OF THE VALUES OF CAPACITORS C2 AND C3 Correct operation of TEA2031A depends partly on the choice of these values for two reasons : - for a given amplitude of the parabola, the importance of final pincushion correction at the output of TEA2031A is determined by defining, by means of C3, the amplitude of the line sawtooth wave. - the absence of oscillation at circuit output is controlled through adjustment of the value of C2 as described below. Voltage at Pin 7 0V t Current in connecting inductor LS 0A 20/32 t t Line deflection current AN393-33.EPS 0A II.5.1 - Selection of C3 As seen before (chapter II.3.2), the value of C3 and only this value (in the limits of the available voltage on the slider of RT1) can fix the value for the amplitude of the line sawtooth wave. Now this amplitude must be greater than the parabola am- TV EAST/WEST CORRECTION CIRCUITS plitude (Pin 7) but not so far in order to have a correction amplitude sufficient but permitting also an horizontal amplitude adjustment : - if the line sawtooth wave and the parabola have the same amplitude, the pincushion correction is maximum but the horizontal amplitude adjustment range is non-exutent - if the line sawtooth amplitude is much greater than the parabola's one, we will have a large range for the horizontal amplitude adjustment, but it will be to the detriment of the pincushion correction amplitude. Once the desired line sawtooth amplitude has been fixed, we can calculate the value of C3 with the following formula Dt i8 C3 = V8 where Dt : line scan duration (around 53s) i8 : Pin 8 current (around 50A) V8 : line sawtooth peak-to-peak amplitude (Pin 8) II.5.2 - Selection of C2 The selection of C2 is related to the values of R5, R6 and RT3. The value of C2 must be large enough to avoid any risk of oscillations at output for the entire range of adjustment of potentiometers RT1 and RT3. The value of C2 must be small enough not to influence the shape of the vertical frequency parabola. II.6 - APPLICATION EXAMPLE A typical application diagram is given in Figure 34. Figure 34 : Typical Application V CC 24V Line Flyback C1 10F R7 2.2k D2 BZX 46C15 RT1 2.2k R5 100k RT3 D1 1N4148 R8 470 C2 22nF 1M R6 33k C3 1.8nF 8 7 6 L1 6.3mH Output (to diode modulator) 5 TEA2031A 3.8V 2.5V 4.2V Typical frame sawtooth 2 R1 39k 3 R2 39k 4 R3 10k RT2 4.7k R4 3.9k AN393-34.EPS 1 21/32 TV EAST/WEST CORRECTION CIRCUITS III - TDA4950 - TDA8145 GENERAL DESCRIPTION III.1 - INTRODUCTION The TDA4950 and TDA8145 consist mainly of 5 parts as seen in the simplified circuit diagram (Figure 35). 1. Full-wave rectifier for the input current IIN. 2. Current limiter in order to limit the rectified current IIN to the maximum value of 40A (with this functional block a suppression of the parasitic parabola is possible, see chapter I.4). 3. Parabola network producing the current IA = k(IIN)2 (k = constant). 4. Comparator and output stage working as a pulse-width modulator for driving the diode modulator. 5. Voltage reference and current reference which produces the reference current IREF via external resistor RI between Pin 3 and Ground. 4 Z1 D3 D2 R8 R12 R11 AN393-35.EPS Q7 I IN 2 1 Full-wave rectifier Q8 VCC - 6 VBE I C6 I C9 Q6 IE5 IE6 OP1 Q5 I C5 VCC - 3 VB E I S = I IN Q2 Q3 Q1 Q9 I lim Q4 IE Q10 R9 R10 I ET24 Q11 IA Parabola network R13 7 IZ 5 IZ IC IZ OP2 3 IZ R7 R6 Q12 R5 Q21 R2 Q13 V REF IO 8 7 Current limiter 22/32 Current reference 3 Q22 OP3 Q20 Q19 R3 Q17 Q15 Q14 Comparator and output stage I REF D4 5 Q16 D1 6 Figure 35 : Simplified Circuit Diagram for TDA4950 - TDA8145 TV EAST/WEST CORRECTION CIRCUITS III.2 - DESCRIPTION Let us consider the blocks in detail : The input amplifier OP1 drives the transistor Q5 or Q6. They offer two different signal paths, depending on the sign of the input current IIN. Assuming that IIN is negative, the feedback loop is closed via the transistor Q5 and the output current IC5 is given by 5 5 = - IIN IC5 = IE5 1 + 5 1 + 5 where 5 is the current gain of the transistor Q5. 5 can be assumed to be more than 100, so the mismatching between IC5 and IIN is less than 1%. For a positive current IIN the output voltage of OP1 decreases : Q5 is switched off the current IIN is the emitter current IE13 of Q6. Its collector current IC6 is given by 6 IC6 = IIN 1 + 6 Since the maximum input current is 40A, the current gain of this PNP transistor is still high enough to give a reasonable small error. This current biases the current mirror Q8 and Q9. A good matching between the current IC8 and IC9 must be provided. Thus the current IS is given by 5 - IIN IIN < 0 1 + 5 IS = 6 + IIN IIN > 0 1 + 6 Neglecting the base current of Q6 and Q5, IS is nearly the absolute value of IIN. Note that for both signal paths, the OP1 has a feedback factor of 1. This means OP1 must be frequency compensated for unity gain. The transistors Q3 and Q4 work as a normal current mirror if the current IS plus IE is smaller than the current Ilim : 2 IS < Ilim In this case the excess current is shunted via the PNP transistor Q1. If the current IS becomes higher IS > Ilim/2 the transistor Q1 switches off and Q2 picks up the current IS from the rectifier which exceeds the maximum value of Ilim/2. Using the proposed reference resistor RI between Pin 3 and Ground (11k) the current IE can be described with IIN IIN < 40A IE = 40A IIN > 40A The parabola network produces an output current IA which is approximately a parabola : IA = k IE2 The parabolic behaviour IA is obtained via piecewise linear approximation. For this purpose the identical resistors RZ are connected with the four emitters. The four different biasing currents iZ, 3iZ, 5iZ, 7iZ yield four different threshold voltages, so the four emitter currents of Q11 are switched stepwise. A schematic illustration of the single emitter currents IEQ11 (1...4) of Q11 as a function of the current IE is given in Figure 36. Figure 36 : Transfer Characteristic of the Parabola Network I A (mA) I EQ11 (mA) I EQ11 (1) I EQ11 (2) I EQ11 (3) AN393-36.EPS I EQ11 (4) I E (A) 23/32 TV EAST/WEST CORRECTION CIRCUITS The transistor Q13 and the resistor R5 acts as a current source biasing the current mirror Q14, Q15. The transistor Q16 is switched on. If the output of OP2 becomes low, Q12 and Q21 are switched off. In this case the current in Q14 and Q15 dissappears and Q16 is switched off. Synchronously the darlington stage Q19 and Q20 is saturated. In order to achieve a fast commutation from Q16 to Q19/Q20 an active discharging of Q16 is provided with the aid of the transistor Q17. During a normal operation range if the output current iOUT is positive, only the Darlington stage (Q19, Q20) and the diode D1 are necessary to drive the external inductor. With the aid of Q16 and the intrinsic substrate diode D4 the output current iOUT can become negative, too; so that the modulation range of the diode modulator becomes larger. The Zener diode Z1 serves as the voltage reference. With the aid of the diodes D2 and D3, a good temperature compensation can be achieved. Using an external resistor of RI = 11k between Pin 3 and Ground we get an accurate and temperature independent current reference to bias the internal current sources. Due to the exponential character of the emitter current as a function of the base emitter voltage, the output current IA is smoothed. For designing the values of RZ and iZ of this parabola network we must take a compromise between the smoothing effect and the temperature dependence. Small values of RZ and iZ yield small threshold voltages for the 4 emitters of Q11. This means a good smoothing of the edges, but a worse temperature dependence. Large values of RZ and iZ yield the opposite result. Practical experiences show that a value of 0.5V for the 4th emitter (R13 7iZ) for IIN= 0 gives an acceptable cmpromise. Due to different values of resistor RZ, the TDA8145 is adapted to flat square tubes (see Figure 37 for the two different shapes of the parabola). Figure 37 : Parabola Shapes for TDA4950 and TDA8145 VPAR (V) TDA4950 TDA8145 t (ms) 0.5 2ms The parabolic output current IA produces a corresponding voltage drop across an external resistor between Pin 7 and Ground (18k). The additional constant current source I0 shifts the D.C. voltage level to achieve an appropriate operating point of the comparator. Its non-inverting input is connected with a horizontal saw-tooth voltage. For this purpose an external capacitor is connected with Pin 8 and Ground which is discharged with the internal current source IC. It will be charged with the positive flyback pulses produced in the line transformer during the flyback time. Due to the linear saw-tooth voltage on Pin 8 this comparator works as a pulse-width modulator. The output of this comparator controls the output stage. If the output of the comparator OP2 is high, Q21 and Q12 are saturated. Therefore, the Darlington output transistor Q19, Q20 is switched off. 24/32 AN393-37.EPS III.3 - APPLICATION A standard application diagram is given in Figure 38. Pin 2 is biased from a linear saw-tooth voltage, the resistor RIN produces the input saw-tooth current. The non-inverting input (Pin 1) is connected with an adjustable voltage (keystone correction). With the aid of this trimmer, the symmetry of the parabola can be adjusted in order to correct a trapezoidal error in the colour picture tube. A further adjustment trimmer is responsible for the picture width and influences only the DC-level of the comparator input (Pin 8). (Since the discharging current sink on Pin 8 is constant, the amplitude of the horizontal saw-tooth voltage (VPP) remains constant). The thrid trimmer is in the feedback path and is responsible for the parabola correction factor. With the aid of this trimmer the distortion on the screen can be changed from pillow-distortion up to an over-correction (tun-distorsion). For some applications the keystone adjustment trimmer is not necessary (small trapezoidal error of the picture tube). In this case, a symmetric parabola should be produced. TV EAST/WEST CORRECTION CIRCUITS Figure 38 : Standard Application Diagram of TDA4950 and TDA8145 East-West amplitude V CC 26V Diode 10mH modulator 100F 47k 4.7k 6 5 47nF V CC 12k 18k I REF 3 7 Picture width 2VPP 100k Keystone correction V REF 1k 8 1 1N4148 V CC - 4V V fr ib ua t 4.7nF ic ib ic ib 4 from line transformer 2 Rin Vl t This can easily be obtained by AC-coupling the input (Pin 2) as seen in Figure 39. Figure 39 : AC-coupled Vertical Saw-tooth Voltage, no Keystone (trapezoidal) Correction 3 CIN RIN 2 In order to avoid any distorsion, the time constant CIN RIN should be at least 10 times larger than the time period (CIN RIN > 10 20ms). On the other AN393-39.EPS 1 hand a too large time constant yields an undesired bouncing effect in the East/West correction. The DC voltage on Pin 1 is arbitrary. For the sake of simplicity, connect Pin 1 with Pin 3. Another possible application with parasitic parabola suppression is given in Figure 40. The input current into Pin 2 is generated via the voltage drop on RM. Due to the common mode rejection of the input operational amplifier, the voltage change during the vertical scan time (sawtooth voltage) has nearly no effect. During the flyback time, a positive pulse (> VCC) is present on Pin 1 and Pin 2. With this flyback pulse the current limitation in the parabola generation circuit is activated and limits the parabola amplitude. Since the flyback time is relatively long, this limitation is necessary to suppress the parasitic parabola (see chapter I.4). 25/32 AN393-38.EPS 40A ua TV EAST/WEST CORRECTION CIRCUITS Figure 40 : Application of TDA4950 and TDA8145 with Parasitic Parabola Suppression V CC 6 5 V CC RI I REF 3 7 Deflection unit RM V REF 8 1 V CC - 4V 40A ic ib ua RIN ib ic ua 4 ib AN393-40.EPS Yoke 2 IV - TDA8146 GENERAL DESCRIPTION IV.1 - INTRODUCTION - programmable parabolic current generator - parasitic parabola suppression during vertical flyback - output sink current up to 800mA and source current up to 100mA - vertical current sense inputs ground compatible The TDA8146 was designed for TV and monitor sets with various types of picture tubes, where a programmable parabola is mandatory. The complete block diagram is shown in Figure 41. The following features confer to this IC an all-purpose suitability : Figure 41 : Block Diagram V P4 PS PAR VS 4 14 13 12 8 TEA8146 I 7 OUT 60A I REF 22V 1.2V 26/32 1.2V 8.2V 3 2 1 11 10 9 6 IGND IV VGL C PW Z GND 5 I REF AN393-41.EPS REF TV EAST/WEST CORRECTION CIRCUITS VIN Thus, IR = R2 If VIN is a symmetrical saw-tooth with GND as the average value and 1.6 Vpeak-to-peak, the rectified peak current will be : IV.2 - INPUT AMPLIFIER AND RECTIFIER The input circuitry (Figure 42) is designed for a common mode range up to 12V. The voltage drop on R1 gives on IGND (Pin 3) : VR1 = R1 IREF IRP = The operational amplifier OP regulates the current through R2, thus : IR2 = (VR1 - VIN) / R2 = (R1 IREF - VIN) / R2 0.8 1010-3 = 80A IV.3 - VERTICAL CLAMPING To avoid the parasitic parabola during the vertical flyback time a vertical clamp circuit was used. The vertical clamping principle is presented in Figure 43. The rectified sawtooth current I R Flows through D2 to the output. When V goes over VS, Q1 switches off and Q2 on. IREF flows now through D1 to the output and IR through Q2 to the ground. IRC = IREF is now the clamped value of the output current. For VIN > 0, we note the output current of the input amplifier IN : IN = IREF - IR2 = IREF - (R1 IREF - VIN) / R2 For VIN < 0, we note the output current of the input amplifier IP : IP = IR2 - IREF = (R1 IREF - VIN) /R2 - IREF The rectifier is formed by Q2, Q3 and Q4. For VIN > 0, IN flows through Q2 to the rectifier output, thus IR = IN. For VIN < 0, IP flows through Q3 from VS into the output of the input amplifier. Q4 reflects the IP current, thus the rectifier output currrent will be IR = IPM = IP. If the sign convention of IR is considered, we have : IV.4 - REFERENCE AND STARTING CIRCUIT Figure 44 presents the complete voltage and current reference circuitry. 8.2V The reference current is IREF = = 82A 100k To guarantee the start of the device, it is necessary to choose the value of the resistor R5 in order to have a minimum current of 56A. (R1 IREF - VIN) R1 VIN IR = - IREF = IREF - 1 + R R2 R2 In our case, R1 = R2 = 10k and IREF = 120A Figure 42 : Input and Rectifier Principle Diagram VIN Input Amplifier I REF Rectifier I REF VS Q3 VS Q4 0 IN t VIR IP I P IN VIP I PM OP Q2 Q1 IR IS IR I RP R1 2 IV R2 0 t AN393-42.EPS IGND 3 VIN 27/32 TV EAST/WEST CORRECTION CIRCUITS Figure 43 : Vertical Clamping Principle Diagram Rectified Sawtooth Current I RC I REF IR VS I REF 0 D1 Vertical Flyback OP Q1 t D2 Rectified and Clamped Sawtooth Current I RC INV VV VS Q2 VV 0 As it can be seen in Figure 46 the parabola can be corrected in the following limits : VC5/VC = K5 = 1.07 with Pin 5 to GND VC4/VC = K4 = 1.17 with Pins 4 and 5 to GND An application specific correction can be thus obtained for various picture tube types. Figure 44 : Reference and Starting Circuit I REF OP T1 D1 IV.6 - PULSE-WIDTH MODULATOR AND OUTPUT D2 D3 5 R5 100k IV.5 - PARABOLA GENERATOR Figure 45 presents the simplified circuit diagram of the parabola generator. The parabolic behaviour of the parabola output current is obtained via piecewise linear approximation. Two external pins permit an external adjustment of the parabola shape (these pins can be connected to ground or to resistors). The parabolic output current on Pin 12 Produces a corresponding voltage drop across an external resistor between Pin 12 and ground. 28/32 AN393-44.EPS Current Reference t The simplified diagram of the pulse-width modulator and output is presented in Figure 47. The non-inverting input of the comparator (Pin 11) is connected to a horizontal saw-tooth voltage. An external capacitor connected on Pin 11 is charged during the flyback time and then discharged by the internal current source generating the saw-tooth voltage. Due to the linear saw-tooth voltage on Pin 11, the comparator works as a pulse-width modulator. The output of this comparator controls the output stage. If the output of the comparator is high, Q67 and Q64 are saturated. The Darlington output configuration Q65/Q66 is switched off. Q62 acts together with R53 as a current source, biasing the current mirror Q58/Q59. The transistor Q60 is switched on. If the output of the comparator becomes low, Q64 and Q67 are switched off. The current through D58/Q59 disappears and Q60 is switched off. Synchronously the Darlington stage Q65/Q66 is saturated. In order to achieve a fast commutation, an active discharging of the Q60 base charge is provided with the aid of Q63. AN393-43.EPS V TV EAST/WEST CORRECTION CIRCUITS Figure 45 : Parabola Generation Parabolic Output Current PAR 12 I2 I1 I3 I4 I5 Constant Current Sources I E5 720mV I E4 I GL 560mV I E3 Rectified Input Current 2k I E2 I E1 2k 400mV 240mV 80mV 3k 3k 3k 1k P4 14 1k 1k VCC 1k P5 13 VCC * S4 * S5 AN393-45.EPS 0 Note : * It is possible to replace the switches S4 and S5 by this configuration in order to have a continuous shape variations. Figure 46 : Parabola Correction V PAR VPAR0 VA 9.6V 9V VC VD VC5 VF 8V 7V during flyback AN393-46.EPS VC4 V SE -0.8V -0.6V -0.3V 0 +0.8V 29/32 TV EAST/WEST CORRECTION CIRCUITS Figure 47 : Pulse-width Modulator and Output C PAR 11 12 8 VS 7 OUT D58 Q59 V REF Q62 Q60 R52 Q63 R53 Q64 Q65 Q66 AN393-47.EPS Q67 IV.7 - APPLICATION An application diagram is presented in Figure 48. The internal Zener configuration on Pin 9 can be useful in certain application. Figure 48 : Application Diagram P4 V GL 1 14 2 13 10k RS 3.3M Vertical Yoke P5 10k 100nF T D A 8 1 4 6 330k 3 4 Vertical Flyback Vertical Deflection 100k 5 12 3.3nF 11 10 2.2k * 9 6 3.3k * V CC 8 7 220F 1nF 47k 4.7k 15mH +27V To diode modulator 30/32 * Note : depending on flyback voltage AN393-48.EPS V CC Horizontal Flyback TV EAST/WEST CORRECTION CIRCUITS V - TDA8147 GENERAL DESCRIPTION V.1 - INTRODUCTION The TDA8147 was designed as an interface IC between the digital circuitry and the diode modulator in digital chassis. The complete block diagram is shown in Figure 49. Figure 49 : TDA8147 Block Diagram 100nF +24V 39k AMP VS PAR 6 3 2 47k TDA8147 PW modulated Parabola 0.2 - 5V IN Av = 4.5 10mH OUT 7 to diode modulator 1 100k 1nF 17.5k R2 H 60A 5 5k H 9..16 R1 4 SGND C GND AN393-49.EPS 8 Pinning for 8 + 8 DIL package V.2 - INPUT AMPLIFIER The pulse-width modulator of the TDA8147 is working with input voltages from 1V to 23V. To have the same range for the parabola voltage an input amplifier is necessary. Digital TV sets deliver an analog parabola or a PWM-signal with small amplitude (2V to 3V). An additional signal ground (SGND Pin) separates the digital ground from the deflection circuit ground. The internal feedback loop of the amplifier gives a 17.5 voltage gain AV = + 1 = 4.5 (see Figure 50) 5 V.3 - VOLTAGE REFERENCE AND STARTING CIRCUIT V.5 - APPLICATION A Standard application diagram is given in Figure 51. Since all the adjustment of the parabola are made by the digital processor, only the feedback loop of the PWM modulator must be carefully designed. The TDA8147 is well-suited for new TV concepts with 32kHz line frequency. Figure 50 : Input Amplifier AMP 6 IN 7 The voltage reference and starting circuit have the same configuration as for the TDA8146 (see paragraph IV.4). 17.5k 5k The PWM modulator (Figure 51) has the same configuration as for the TDA8146. So see paragraph IV.6 for explanation. AN393-50.EPS V.4 - PWM MODULATOR AND OUTPUT 8 SGND 31/32 TV EAST/WEST CORRECTION CIRCUITS Figure 51 : Application Diagram 100nF +24V 39k AMP VS PAR 6 3 2 47k W TDA8147 PW modulated Parabola 0.2 - 5V IN Av = 4.5 10mH OUT 7 to diode modulator 1 100k 1nF 50VPP 6.8k 17.5k 60A H H 5k 5 2.2k 9..16 4 SGND C GND 1k 4.7nF Pinning for 8 + 8 DIL package Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1994 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 32/32 AN393-51.EPS 8