ADS808Y/2KG4 - Texas Instruments High-Performance Analog

ADS808

12-Bit

Pipelined

ADC Core

Reference and

Mode Select

Reference Ladder

and Driver

Timing Circuitry

Error

Correction

Logic

3-State

Outputs

T&H D0

D11

•

+VS

ADS808 CLK

CLK

SEL2 REFBVREF

REFT

VDRV

IN1Vp-p

1Vp-p

(+2.5V)

SEL1

OVR

12-Bit, 70MHz Sampling

ANALOG-TO-DIGITAL CONVERTER

FEATURES

●DYNAMIC RANGE:

SNR: 64dB at 10MHz fIN

SFDR: 68dB at 10MHz fIN

●PREMIUM TRACK-AND-HOLD:

Low Jitter: 0.25ps rms

Differential or Single-Ended Inputs

Selectable Full-Scale Input Range

●FLEXIBLE CLOCKING:

Differential or Single-Ended

Accepts Sine or Square Wave Clocking

Down to 0.5Vp-p

Variable Threshold Level

DESCRIPTION

The ADS808 is a high-dynamic range, 12-bit, 70MHz,

pipelined Analog-to-Digital Converter (ADC). It includes a

high-bandwidth linear track-and-hold that has a low jitter of

only 0.25ps rms, leading to excellent SNR performance. The

clock input can accept a low-level differential sine wave or

square wave signal down to 0.5Vp-p, further improving the

SNR performance. It also accepts a single-ended clock

signal and has flexible threshold levels.

The ADS808 has a 2Vp-p differential input range (1Vp-p • 2

inputs) for optimum signal-to-noise ratio. The differential

operation gives the lowest even-order harmonic compo-

nents. A lower input voltage of 1.5Vp-p or 1Vp-p can also be

selected using the internal references, further optimizing

SFDR. Alternatively, a single-ended input range can be used

by tying the

input to the common-mode voltage, if desired.

The ADS808 also provides an over-range flag that indicates

when the input signal has exceeded the converter’s full-scale

range. This flag can also be used to reduce the gain of the

front-end signal conditioning circuitry. It also employs digital

error-correction techniques to provide excellent differential

linearity for demanding imaging applications. The ADS808 is

available in a small TQFP-48 PowerPAD™ thermally en-

hanced package.

APPLICATIONS

●BASESTATION WIDEBAND RADIOS:

CDMA, GSM, TDMA, 3G, AMPS, and NMT

●TEST INSTRUMENTATION

●CCD IMAGING

ADS808

SBAS179C – DECEMBER 2000 – REVISED SEPTEMBER 2002

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a registered trademark of Texas Instruments.

ADS808

2SBAS179C

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ELECTRICAL CHARACTERISTICS

At TA = full specified temperature range, differential input range = 1V to 2V, sampling rate = 70MHz, VS = +5V, and internal reference, unless otherwise noted.

SPECIFIED

PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT

PRODUCT PACKAGE-LEAD DESIGNATOR(1) RANGE MARKING NUMBER MEDIA, QUANTITY

ADS808Y TQFP-48 PHP –40°C to +85°C ADS808Y ADS808Y/250 Tape and Reel, 250

"" " " "ADS808Y/2K Tape and Reel, 2000

NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.

PACKAGE/ORDERING INFORMATION

+VS.......................................................................................................+6V

Analog Input .......................................................... (–0.3V) to (+VS + 0.3V)

Logic Input ............................................................ (–0.3V) to (+VS + 0.3V)

Case Temperature ......................................................................... +100°C

Junction Temperature .................................................................... +150°C

Storage Temperature..................................................................... +150°C

NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”

may cause permanent damage to the device. Exposure to absolute maximum

conditions for extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas

Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper han-

dling and installation procedures can cause damage.

ESD damage can range from subtle performance degrada-

tion to complete device failure. Precision integrated circuits

may be more susceptible to damage because very small

parametric changes could cause the device not to meet its

published specifications.

ADS808Y

PARAMETER CONDITIONS MIN TYP MAX UNITS

RESOLUTION 12 Tested Bits

SPECIFIED TEMPERATURE RANGE Ambient Air –40 to +85 °C

ANALOG INPUT

Standard Differential Input Range (1Vp-p • 2, +10dBm) 1 2 V

Single-Ended Input Voltage 1Vp-p 2 3 V

Common-Mode Voltage 2.5 V

Optional Input Ranges Selectable

1Vp-p or 1.5Vp-p

Analog Input Bias Current 1µA

Track-Mode Input Bandwidth –3dBFS 1 GHz

Input Impedance Static, No Clock 1.25 || 9 MΩ || pF

CONVERSION CHARACTERISTICS

Sample Rate 1M 70M Samples/s

Data Latency 5 Clk Cyc

DYNAMIC CHARACTERISTICS

Differential Linearity Error (largest code error)

f = 1MHz ±0.7 +1.7/–1.0 LSB

No Missing Codes Tested

Integral Nonlinearity Error, f = 1MHz ±4.0 ±7.0 LSBs

Spurious-Free Dynamic Range(1)

f = 1MHz 72 dBFS(2)

f = 10MHz 65 68 dBFS

2-Tone Intermodulation Distortion

fIN = 19.4MHz and 20.4MHz (–7dB each tone) –77 dBFS

Signal-to-Noise Ratio (SNR)

f = 1MHz 64.5 dBFS

f = 10MHz 64 dBFS

Signal-to-(Noise + Distortion) (SINAD)

f = 2.2MHz 64 dBFS

f = 10MHz 63 dBFS

Output Noise Input AC-Grounded 0.3 LSBs rms

Aperture Delay Time 3ns

Aperture Jitter 0.25 ps rms

Over-Voltage Recovery Time 2ns

Full-Scale Step Acquisition Time 5ns

DIGITAL INPUTS

Logic Family +3V/+5V Logic Compatible CMOS

Convert Command Start Conversion Rising Edge of Convert Clock

High-Level Input Current (VIN = 5V)(3) 100 µA

Low-Level Input Current (VIN = 0V) ±10 µA

High-Level Input Voltage +2.0 V

Low-Level Input Voltage +1.0 V

Input Capacitance 5pF

ADS808 3

SBAS179C www.ti.com

ELECTRICAL CHARACTERISTICS (Cont.)

At TA = full specified temperature range, differential input range = 1V to 2V, sampling rate = 70MHz, VS = +5V, and internal reference, unless otherwise noted.

ADS808Y

PARAMETER CONDITIONS MIN TYP MAX UNITS

+3V/+5V Compatible CMOS

Straight Offset Binary

DIGITAL OUTPUTS

Logic Family

Logic Coding

Low Output Voltage (IOL = 50µA to 1.6mA) VDRV = 3V +0.2 V

High Output Voltage, (IOH = 50µA to 0.5mA) +2.5 V

Low Output Voltage, (IOL = 50µA to 1.6mA) VDRV = 5V +0.2 V

High Output Voltage, (IOH = 50µA to 1.6mA) +2.5 V

3-State Enable Time

= LOW 20 40 ns

3-State Disable Time

= HIGH 2 10 ns

Output Capacitance 5pF

ACCURACY (Internal Reference, = 2V, Unless Otherwise Noted)

Zero Error (Midscale) at 25°C 0.5 %FS

Zero Error Drift (Midscale) 12 ppm/°C

Gain Error(4) at 25°C±1.5 %FS

Gain Error Drift(4) 38 ppm/°C

Gain Error(5) at 25°C±0.75 %FS

Gain Error Drift(5) 20 ppm/°C

Power-Supply Rejection of Gain ∆VS = ±5% 68 dB

Internal REF Tolerance (VREFP – VREFN) Deviation from Ideal ±10 ±40 mV

Reference Input Resistance 660 Ω

POWER-SUPPLY REQUIREMENTS

Supply Voltage: +VSOperating +4.75 +5.0 +5.25 V

Supply Current: +ISOperating 142 mA

Output Driver Supply Current (VDRV) 10 mA

Power Dissipation: VDRV = 5V Internal Reference 740 mW

VDRV = 3V Internal Reference 720 770 mW

VDRV = 5V External Reference 720 mW

VDRV = 3V External Reference 700 mW

Power Down Operating 20 mW

Thermal Resistance,

TQFP-48 28.8 °C/W

NOTES: (1) Spurious-Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to Full-Scale. (3) A 50kΩ pull-down

resistor is inserted internally. (4) Includes internal reference. (5) Excludes internal reference.

ADS808

4SBAS179C

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26 VDRV Output Bit Driver Voltage Supply

27 GND Ground

28 I

Output Enable: HI = High Impedance;

LO or Floating: Normal Operation

29 I PD Power Down: HI = Power Down; LO = Normal

30 I BTC HI = Binary Two’s Complement;

LO = Straight Binary

31 GND Ground

32 SEL2 Reference Select 2: See Table on Page 5.

33 SEL1 Reference Select 1: See Table on Page 5.

34 VREF Internal Reference Voltage

35 GND Ground

36 GND Ground

37 GND Ground

38 GND Ground

39 REFB Bottom Reference Voltage Bypass

40 CM Common-Mode Voltage (mid-scale)

41 REFT Top Reference Voltage Bypass

42 GND Ground

43 GND Ground

44 I

Complementary Analog Input

45 GND Ground

46 I IN Analog Input

47 +VSSupply Voltage

48 +VSSupply Voltage

1 BYP Bypass Point

2+V

SSupply Voltage

3+V

SSupply Voltage

4+V

SSupply Voltage

5 GND Ground

6 I CLK Clock Input

7I CLK Complementary Clock Input

8 GND Ground

9 GND Ground

10 O OVR Over-Range Indicator

11 O DV Data Valid Pulse: HI = Data Valid

12 NC No Connection

13 NC No Connection

14 O D11 Data Bit 11, (MSB)

15 O D10 Data Bit 10

16 O D9 Data Bit 9

17 O D8 Data Bit 8

18 O D7 Data Bit 7

19 O D6 Data Bit 6

20 O D5 Data Bit 5

21 O D4 Data Bit 4

22 O D3 Data Bit 3

23 O D2 Data Bit 2

24 O D1 Data Bit 1

25 O D0 Data Bit 0, (LSB)

GND

REF

SEL1

SEL2

GND

BTC

GND

VDRV

D0 (LSB)

GND

REFT

REFB

GND

D11 (MSB)

D10

BYP

GND

CLK

GND

OVR

48 47 46 45 44 43 42 41 40 39 38

13 14 15 16 17 18 19 20 21 22 23

ADS808Y

PIN I/O DESIGNATOR DESCRIPTION PIN I/O DESIGNATOR DESCRIPTION

PIN DESCRIPTIONS

PIN DIAGRAM

Top View TQFP

ADS808 5

SBAS179C www.ti.com

DESIRED INTERNAL

FULL-SCALE RANGE SEL1 SEL2 VREF

1Vp-p VREF GND 0.5V

1.5Vp-p GND +VS0.75V

2Vp-p GND GND 1.0V

REFERENCE AND FULL-SCALE RANGE SELECT

NOTE: For external reference operation, tie VREF to +VS and apply REFT and REFB externally. Internal voltage buffer of CM is powered up. The full-scale input range

is equal to 2x the reference value (REFT – REFB).

TIMING DIAGRAM

SYMBOL DESCRIPTION MIN(1) TYP MAX(1) UNITS

tCONV Convert Clock Period 14.3 1µsns

tHClock Pulse HIGH 7 t CONV/2 ns

tLClock Pulse LOW 7 t CONV/2 ns

tAAperture Delay 4.6 6.1 ns

tDV Data Valid Pulse Delay(2) 11.5 14 ns

t1Data Hold Time, CL = 0pF 4 5 ns

t2New Data Delay Time, CL = 15pF max 9 11 ns

NOTES: (1) Timing values based on simulation at room temperature. Min/Max values provided for

design estimation only. (2) Measured from the 50% point of the clock to the time when signals are

within valid logic levels.

tCONV tH

N – 5N – 4N – 3N – 2N – 1 N N + 1

Data Bits Out

Data Valid Pulse

Clock

N + 1 N + 2

N + 3 N + 4 N + 5

N + 6

N + 7

Analog In

tDV

5 Clock Cycles

ADS808

6SBAS179C

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TYPICAL CHARACTERISTICS

At TA = full specified temperature range, differential input range = 1V to 2V, sampling rate = 70MHz, and internal reference, unless otherwise noted.

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

SPECTRAL PERFORMANCE

(Differential, 2Vp-p)

Frequency (MHz)

0 5 10 15 20 25 30 35

Amplitude (dBFS)

= 1MHz (–1.0dBFS)

SFDR = 71.40dBFS

SNR = 64.41dBFS

SINAD = 63.33dBFS

DYNAMIC PERFORMANCE

vs SAMPLING FREQUENCY

Sampling Frequency (MHz)

30 35 40 45 5550 60 65 70 75 80

SFDR, SNR, and SINAD (dBFS)

= 1MHz

SNR

SINAD

SFDR

DYNAMIC PERFORMANCE

vs SAMPLING FREQUENCY

(2Vp-p, Differential)

Sample Frequency (MHz)

30 35 40 45 5550 60 65 70 75 80

SFDR, SNR, and SINAD (dBFS)

= 10MHz

SNR

SINAD

SFDR

DYNAMIC PERFORMANCE

vs SAMPLING FREQUENCY

(2Vp-p, Differential)

Sample Frequency (MHz)

40 45 50 6055 65 70 75 80

SFDR, SNR, and SINAD (dBFS)

= 20MHz

SNR

SINAD

SFDR

760

740

720

700

680

660

640

620

600

580

560

540

520

500

TOTAL POWER vs SAMPLING FREQUENCY

Sampling Frequency (MHz)

30 35 40 5045 55 60 7065 8075

Power (mW)

fIN = 10MHz

fIN = 1MHz

DYNAMIC PERFORMANCE vs INPUT FREQUENCY

Input Frequency (MHz)

1 6 11 16 21 3126

SFDR, SNR, and SINAD (dBFS)

SNR

SINAD

SFDR

ADS808 7

SBAS179C www.ti.com

TYPICAL CHARACTERISTICS (Cont.)

At TA = full specified temperature range, differential input range = 1V to 2V, sampling rate = 70MHz, and internal reference, unless otherwise noted.

300k

250k

200k

150k

100k

50k

OUTPUT NOISE HISTOGRAM

(2Vp-p, Grounded Input)

Code

N – 1 N N + 1 N + 2

Counts

N – 2

0.8

0.6

0.4

0.3

–0.2

–0.4

–0.6

–0.8

–1

DIFFERENTIAL LINEARITY ERROR

Code

0 1024 2048 3072 4096

DLE (LSB)

–1

–2

–3

INTEGRAL LINEARITY ERROR

Code

0 1024 2048 3072 4096

ILE (LSB)

ADS808

8SBAS179C

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APPLICATION INFORMATION

THEORY OF OPERATION

The ADS808 is a high-speed, high-performance, CMOS

ADC built with a fully differential, 9-stage pipeline architec-

ture. Each stage contains a low-resolution quantizer and

digital error-correction logic, ensuring excellent differential

linearity and no missing codes at the 12-bit level. The

conversion process is initiated by a rising edge of the

external convert clock. Once the signal is captured by the

input track-and-hold amplifier, the bits are sequentially en-

coded starting with the MSB. This process results in a data

latency of five clock cycles, after which the output data is

available as a 12-bit parallel word either coded in a straight

binary or binary two’s complement format.

The analog input of the ADS808 consists of a differential

track-and-hold circuit, as shown in Figure 1. The differential

topology produces a high level of AC-performance at high

sampling rates. It also results in a very high usable input

bandwidth that is especially important for IF, or undersampling

applications. Both inputs (IN,

) require external biasing up

to a common-mode voltage that is typically at the mid-supply

level (+VS/2). This is because the on-resistance of the CMOS

switches is lowest at this voltage, minimizing the effects of

the signal dependent nonlinearity of RON. The track-and-hold

circuit can also convert a single-ended input signal into a fully

differential signal for the quantizer. For ease of use, the

ADS808 incorporates a selectable voltage reference, a ver-

satile clock input, and a logic output driver designed to

interface to 3V or 5V logic.

particularly suited for communication systems that digitize

wideband signals. Features on the ADS808, like the input

range selector or the option of an external reference, provide

the needed flexibility to accommodate a wide range of

applications. In any case, the analog interface/driver require-

ments should be carefully examined before selecting the

appropriate circuit configuration. The circuit definition should

include considerations on the input frequency spectrum and

amplitude, single-ended versus differential driver configura-

tion, as well as the available power supplies.

Differential versus Single-Ended

The ADS808 input structure allows it to be driven either

single-ended or differentially. Differential operation of the

ADS808 requires an input signal that consists of an in-phase

and a 180° out-of-phase component simultaneously applied

to the inputs (IN,

). Differential signals offer a number of

advantages that in many applications will be instrumental in

achieving the best harmonic performance of the ADS808:

•The signal amplitude is half of that required for the single-

ended operation and is, therefore, less demanding to

achieve while maintaining good linearity performance from

the signal source.

•The reduced signal swing allows for more headroom of

the interface circuitry and, therefore, a wider selection of

the best suitable driver amplifier.

•Even-order harmonics are minimized.

•Improves the noise immunity based on the converter’s

common-mode input rejection.

For the single-ended mode, the signal is applied to one of the

inputs while the other input is biased with a DC voltage to the

required common-mode level. Both inputs are identical in

terms of their impedance and performance except that apply-

ing the signal to the complementary input (

) instead of the

IN-input will invert the orientation of the input signal relative

to the output code. For example, if the input driver operates

in inverting mode using

as the signal input, it will restore

the phase of the signal to its original orientation. Time-

domain applications may benefit from a single-ended inter-

face configuration and a reduced circuit complexity. Driving

the ADS808 with a single-ended signal will result in a trade-

off of the excellent distortion performance, while maintaining

a good signal-to-noise ratio (SNR). The trade-off of the

differential input configuration over the single-ended is its

increase in circuit complexity. In either case, the selection of

the driver amplifier should be such that the amplifier’s perfor-

mance will not degrade the A/D converter’s performance.

Input Full-Scale Range versus Performance

Employing dual-supply amplifiers and AC-coupling will usually

yield the best results. DC-coupling and/or single-supply ampli-

fiers impose additional design constrains due to their head-

room requirements, especially when selecting the 2Vp-p input

range. The full-scale input range of the ADS808 is defined

either by the settings of the reference select pins (SEL1,

SEL2) or by an external reference voltage (see Table I).

T&H

CIN

Tracking Phase: S1, S2, S3, S4Closed; S5, S6 Open

Hold Phase: S1, S2, S3, S4Open; S5, S6 Closed

ADS808

FIGURE 1. Simplified Circuit of Input Track-and-Hold Amplifier.

DRIVING THE ANALOG INPUTS

Types of Applications

The analog input of the ADS808 can be configured in various

ways and driven with different circuits, depending on the

application and the desired level of performance. Offering a

high dynamic range at high input frequencies, the ADS808 is

ADS808 9

SBAS179C www.ti.com

By choosing between the three different signal input ranges,

trade-offs can be made between noise and distortion perfor-

mance. In order to maximize the SNR, which is important for

time-domain applications, the 2Vp-p range may be se-

lected. This range may also be used with low-level (–6dBFS

to –40dBFS) to high-frequency inputs (multi-tone). The

1.5Vp-p range may be considered for achieving a combina-

tion of both low noise and distortion performance. Here the

SNR number is typically 3dB down compared to the 2Vp-p

range, while an improvement in the distortion performance

of the driver amplifier may be realized due to the reduced

output power level required. The third option, 1Vp-p FSR,

may be considered mainly for applications requiring DC-

coupling and/or single-supply operation of the driver and the

converter.

Input Biasing (VCM)

The ADS808 operates from a single +5V supply, and re-

quires each of the analog inputs to be externally biased to a

common-mode voltage of typically +2.5V. This allows a

symmetrical signal swing while maintaining sufficient head-

room to either supply rail. Communication systems are usu-

ally AC-coupled in-between signal processing stages, mak-

ing it convenient to set individual common-mode voltages

and allow optimizing the DC operating point for each stage.

Other applications (e.g., imaging) process only unipolar or

DC-restored signals. In this case, the common-mode voltage

may be shifted such that the full-input range of the converter

is utilized.

It should be noted that the CM pin is internally buffered.

However, it is recommended to keep the loading of this pin

to a minimum to avoid an increase in the converter’s

nonlinearity. Additionally, the DC voltage at the CM pin is not

exactly +2.5V, but is subject to the tolerance of the top and

bottom references, as well as the resistor ladder.

Input Impedance

The input of the ADS808 is of a capacitive nature and the

driving source needs to provide the slew current to charge or

discharge the input sampling capacitor while the track-and-

hold amplifier is in track mode (see Figure 1). This effectively

results in a dynamic input impedance that is a function of the

sampling frequency. Figure 2 depicts the differential input

impedance of the ADS808 as a function of the input fre-

quency.

For applications that use op amps to drive the ADC, it is

recommended to add a series resistor between the amplifier

output and the converter inputs. This will isolate the converter’s

capacitive input from the driving source and avoid gain

peaking, or instability. Furthermore, it will create a 1st-order,

low-pass filter in conjunction with the specified input capaci-

tance of the ADS808. Its cutoff frequency can be adjusted

even further by adding an external shunt capacitor from each

signal input to ground. However, the optimum values of this

RC network depend on a variety of factors, including the

ADS808’s sampling rate, the selected op amp, the interface

configuration, and the particular application (time domain

versus frequency domain). Generally, increasing the size of

the series resistor and/or capacitor will improve the signal-to-

noise ratio, however, depending on the signal source, large

resistor values may reduce the harmonic distortion perfor-

mance. In any case, the use of the RC network is optional but

optimizing the values to adapt to the specific application is

encouraged.

INPUT DRIVER CONFIGURATIONS

The following section provides some principal circuit sugges-

tions on how to interface the analog input signal to the

ADS808. A first example of a typical analog interface circuit

is shown in Figure 3. Here it is assumed that the input signal

is already available in differential form (e.g., coming from a

preceding mixer stage). The differential driver performs an

impedance transformation as well as amplifying the signal to

match the selected full-scale input range of the ADS808 (for

example, 2Vp-p). The common-mode voltage (VCM) for the

converter input is established by connecting the inputs to the

midpoints of the resistor divider. The input signal is AC-

coupled through capacitors CIN to the inputs of the converter

that are set to a VCM of approximately +2.5VDC.

FIGURE 2. Differential Input Impedance versus Input

Frequency.

Differential

Driver ADS808

0.1µF

REFT

REFB

1kΩ

= +2.5V

NOTE: Reference bypassing omitted for clarity.

FIGURE 3. AC Coupling Allows for Easy DC Biasing of the

ADS808 Inputs While the Input Signal is Applied

by the Differential Input Driver.

1000

100

0.1

0.01 0.1 1 10 100 1000

ADS808 INPUT IMPEDANCE vs INPUT FREQUENCY

fIN (MHz)

ZIN (kΩ)

ADS808

10 SBAS179C

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Some differential driver circuits may allow setting an appropri-

ate common-mode voltage directly at the driver input. This will

simplify the interface to the ADS808 and eliminate the external

biasing resistors and the coupling capacitors. Texas Instru-

ments offers a line of fully differential high-speed amplifiers

(refer to our web site at www.ti.com). The THS4150, for

example, may be used for input frequencies from DC to

approximately 10MHz, for which the part maintains good

distortion performance, providing a 2Vp-p (max) output swing

on ±5V supplies. Combining a differential driver circuit with a

step-up transformer can lead to significant improvement of the

distortion performance (see Figure 6).

Transformer Coupled Interface Circuits

If the application allows for AC-coupling, but requires a signal

conversion from a single-ended source to drive the ADS808

differentially, using a transformer offers a number of advan-

tages. As a passive component, it does not add to the total

noise; plus by using a step-up transformer, further signal

amplification can be realized. As a result, the signal swing

out of the amplifier driving the transformer can be reduced,

leading to more headroom for the amplifier and improved

distortion performance.

One possible interface solution that uses a transformer is

given in Figure 4. The input signal is assumed to be an

Intermediate Frequency (IF) and bandpass filtered prior to

the IF amplifier. Dedicated IF amplifiers, for example the

RF2312 or MAR-6, are fixed-gain broadband amplifiers and

feature a very high bandwidth, a low-noise figure, and a high

intercept point at the expense of high quiescent currents of

50-120mA. The IF amplifier may be AC-coupled or directly

connected to the primary side of the transformer.

A variety of miniature RF transformers are readily available

from different manufacturers, i.e., Mini-Circuits, Coilcraft, or

Trak. When choosing a selection, it is important to carefully

examine the application requirements and determine the

correct model, the desired impedance ratio, and frequency

characteristics. Furthermore, the appropriate model must

support the targeted distortion level and should not exhibit

any core saturation at full-scale voltage levels. Since the

transformer does not appreciably load the ladder, its center

tap can be directly tied to the CM pin of the converter, as

shown in Figure 4. The value of termination resistor (RT)

should be chosen to satisfy the termination requirements of

the source impedance (RS). It can be calculated using the

equation RT = n2 • RS to ensure proper impedance matching.

Transformer Coupled, Single-Ended to

Differential Configuration

For applications in which the input frequency is limited to

about 40MHz (e.g., baseband), the wideband, current-feed-

back, operational amplifier OPA685 may be used. As shown

in Figure 5, the OPA685 is configured for the noninverting

mode, amplifies the single-ended input signal, and drives the

primary of an RF transformer. To maintain the very low

distortion performance of the OPA685, it may be advanta-

geous to reduce the full-scale input range (FSR) of the

ADS808 from 2Vp-p to 1.5Vp-p or 1Vp-p (refer to the “Ref-

erence” section for details on selecting the converter’s full-

scale range).

The circuit also shows the use of an additional RC low-pass

filter placed in series with each converter input. This optional

filter can be used to set a defined corner frequency and

FIGURE 4. Driving the ADS808 with a Low Distortion RF Amplifier and a Transformer Suited for IF Sampling Applications.

4.7µF0.1µF

0.1µF1:n

XFMR

Amp

Optional

Bandpass

Filter

(IF)

ADS808

+5V

–V

+2.5V

RIN

RIN CIN

CIN

2.2µF0.1µF

0.1µF1:n

XFMR

OPA685

VIN

ADS808

+5V–V+V

VCM +2.5V

FIGURE 5. Converting a Single-Ended Input Signal into a Differential Signal Using a RF Transformer.

ADS808 11

SBAS179C www.ti.com

attenuate some of the wideband noise. The actual compo-

nent values would need to be tuned for the individual appli-

cation requirements. As a guideline, resistor values are

typically in the range of 10Ω to 100Ω, capacitors in the range

of 10pF to 200pF. In any case, the RIN and CIN values should

have a low tolerance. This will ensure that the ADS808 sees

closely matched source impedances.

AC-Coupled, Differential Interface with Gain

The interface circuit example presented in Figure 6 employs

two OPA685s, (current-feedback op amps), optimized for

gains of 8V/V or higher. The input transformer (T1) converts

the single-ended input signal to a differential signal required

at the amplifier’s inverting inputs, that are tuned to provide a

50Ω impedance match to an assumed 50Ω source. To

achieve the 50Ω input match at the primary of the 1:2

transformer, the secondary input must see a 200Ω load

impedance. Both amplifiers are configured for the inverting

mode resulting in close gain and phase matching of the

differential signal. This technique, along with a highly sym-

metrical layout, is instrumental in achieving a substantial

reduction of the 2nd-harmonic, while retaining excellent 3rd-

order performance. A common-mode voltage (VCM) is ap-

plied to the noninverting inputs of the OPA685. Additional

series of 43.2Ω resistors isolate the output of the op amps

from the capacitive load presented by the 22pF capacitors

and the input capacitance of the ADS808. This 43.2Ω/22pF

combination sets a pole at approximately 167MHz and rolls

off some of the wideband noise.

REFERENCE

REFERENCE OPERATION

Integrated into the ADS808 is a bandgap reference circuit

including some logic that provides a +0.5V, +0.75V, or +1V

reference output by selecting the corresponding pin-strap

configuration. Table I gives a complete overview of the

possible reference options and pin configurations.

+5V

–5V

OPA685

22pF

+5V

–5V

600Ω

OPA685

1:2

50Ω Source

Noise

Figure

11.8dB

600Ω

100Ω

43.2Ω

Power-supply decoupling

not shown.

43.2Ω

A/D Converter Input

= 12V/V (21.6dB)

DIS

FIGURE 6. Wideband Differential A/D Converter Driver.

DESIRED FULL-SCALE RANGE, CONNECT SEL1 CONNECT SEL2 VOLTAGE AT VREF VOLTAGE AT REFT VOLTAGE AT REFB

FSR (Differential) (Pin 33) (Pin 32) (Pin 34) (Pin 41) (Pin 39)

2Vp-p (+10dBm) GND GND +1.0V +3V +2V

1.5Vp-p (+7.5dBm) GND +VS+0.75V +2.875V +2.125V

1Vp-p VREF GND +0.5V +2.75V +2.25V

External Reference ——> +3.5V +2.75V to +4.5V +0.5V to +2.25V

TABLE I. Reference Pin Configurations and Corresponding Voltage on the Reference Pins.

ADS808

12 SBAS179C

www.ti.com

Figure 7 shows the basic model of the internal reference

circuit. The functional blocks are a 1V bandgap voltage

reference, a selectable gain amplifier, the drivers for the top

and bottom reference (REFT, REFB), and the resistive refer-

ence ladder. The ladder resistance measures approximately

660Ω between the REFT and REFB pin. The ladder is split

into two equal segments, establishing a common-mode volt-

age at the ladder midpoint, labeled “CM”. The ADS808

requires solid bypassing for all reference pins to keep the

effect of clock feedthrough to a minimum and to achieve the

specified level of performance. Figure 7 also demonstrates

the recommended decoupling scheme. All 0.1µF capacitors

should be located as close to the pins as possible.

When operating the ADS808 from the internal reference, the

effective full-scale input span for each of the inputs, IN and

, is determined by the voltages at REFT and REFB pins,

given as:

Input Span (differential) = 2x (REFT – REFB), in Vp-p = 2 • V

REF

The top and bottom reference outputs may be used to

provide up to 1mA (sink or source) of current to external

circuits. Degradation of the differential linearity (DNL) and,

consequently, of the dynamic performance of the ADS808

may occur if this limit is exceeded.

Using External References

For even more design flexibility, the ADS808 can be oper-

ated with an external reference.

The utilization of an external reference voltage may be

considered for applications requiring higher accuracy, im-

proved temperature stability, or a continuous adjustment of

the converter’s full-scale range. Especially in multichannel

applications, the use of a common external reference offers

the benefit of improving the gain matching between convert-

ers. Selection between internal or external reference opera-

tion is controlled through the VREF pin. The internal reference

will become disabled if the voltage applied to the VREF pin

exceeds +3.5VDC. Once selected, the ADS808 requires two

reference voltages—a top-reference voltage applied to the

REFT pin and a bottom-reference voltage applied to the

REFB pin (see Table I). As illustrated in Figure 8, a micropower

reference (REF1004) and a dual, single-supply amplifier may

be used to generate a precision external reference. Note that

the function of the range select pins, SEL1 and SEL2, are

disabled while the converter is in external mode.

Range Select

and

Gain Amplifier

Top

Reference

Driver

Bottom

Reference

Driver

+1VDC

Bandgap

Reference

ADS808

REFT

REFB

0.1µF

1µF

0.1µF

ByP

SEL1 SEL2 PD

VREF

330Ω

FIGURE 7. Internal Reference Circuit of the ADS808 and Recommended Bypass Scheme.

+2.2µF

0.1µF

+2.2µF 0.1µF

10µF

REFT

REFB

ADS808

1/2

OPA2234

1/2

OPA2234

4.7kΩ

+5V +5V

REF1004

+2.5V

FIGURE 8. Example for an External Reference Circuit Using a Dual, Single-Supply Op Amp.

ADS808 13

SBAS179C www.ti.com

CLK

ADS808

0.1µF1:1

Square Wave

Clock Source

FIGURE 11. Connecting a Ground Referenced Square Wave

Clock Source to the ADS808 Using a RF Trans-

former.

DIGITAL INPUTS AND OUTPUTS

CLOCK INPUT

Unlike most A/D converters, the ADS808 contains an internal

clock conditioning circuitry. This enables the converter to

adapt to a variety of application requirements and different

clock sources. Some interface examples are given in the

following section. With no input signal connected to either

clock pin, the threshold level is set to about +1.6V by the

on-chip resistive voltage divider, as shown in Figure 9. The

parallel combination of R1 || R2 and R3 || R4 sets the input

impedance of the clock inputs (CLK, CLK) to approximately

2.7kΩ single-ended, or 5.4kΩ differentially. The associated

ground-referenced input capacitance is approximately 5pF

for each input. If a logic voltage other than the nominal +1.6V

is desired, the clock inputs can be externally driven to

establish an alternate threshold voltage.

8.5kΩ

ADS808

8.5kΩ

+5V

4kΩ

CLK

4kΩ

Applying a single-ended clock signal will provide satisfactory

results in many applications. However, unbalanced high-

speed logic signals often introduce a high amount of distur-

bances, such as ringing or ground bouncing. Also, a high

amplitude may cause the clock signal to have unsymmetrical

rise and fall times, potentially effecting the converter’s distor-

tion performance. Proper termination practice and a clean

PCB layout will help to keep those effects to a minimum.

To take full advantage of the excellent distortion performance

of the ADS808, it is recommended to drive the clock inputs

differentially. A low-level, differential clock improves the digi-

tal feedthrough immunity and minimizes the effect of modu-

lation between the signal and the clock. Figure 11 illustrates

a simple method of converting a square wave clock from

single-ended to differential using a RF transformer. Small

surface-mount transformers are readily available from sev-

eral manufacturers (e.g.: model ADT1-1 by Mini-Circuits). A

capacitor in series with the primary side may be inserted to

block any DC voltage present in the signal. Since the clock

inputs are self-biased, the secondary side connects directly

to the two clock inputs of the converter.

CLK

ADS808

47nF

TTL/CMOS

Clock Source

(3V/5V)

FIGURE 9. The Differential Clock Inputs are Internally Biased.

FIGURE 10. Single-Ended TTL/CMOS Clock Source.

The ADS808 can be interfaced to standard TTL or CMOS

logic and accepts 3V or 5V compliant logic levels. In this case,

the clock signal should be applied to the CLK input, while the

complementary clock input (

CLK

) should be bypassed to

ground by a low-inductance ceramic chip capacitor, as shown

in Figure 10. Depending on the quality of the signal, inserting

a series damping resistor may be beneficial to reduce ringing.

When digitizing at high sampling rates (f

> 50MHz), the clock

should have a 50% duty cycle (t

= t

) to maintain a good

distortion performance.

The clock inputs of the ADS808 can be connected in a

number of ways. However, the best performance is obtained

when the clock input pins are driven differentially. When

operating in this mode, the clock inputs accommodate signal

swings ranging from 2.5Vp-p down to 0.5Vp-p, differentially.

This allows direct interfacing of clock sources, such as

voltage-controlled crystal oscillators (VCXO) to the ADS808.

The advantage here is the elimination of external logic

usually necessary to convert the clock signal into a suitable

logic (TTL or CMOS) signal, that otherwise would create an

additional source of jitter. In any case, a very low-jitter clock

is fundamental to preserving the excellent AC performance

of the ADS808. The converter itself is specified for a very low

0.25ps (rms) jitter, characterizing the outstanding capability

of the internal clock and track-and-hold circuitry. Generally,

as the input frequency increases, the clock jitter becomes

more dominant in maintaining a good SNR. This is particu-

larly critical in IF sampling applications where the sampling

frequency is lower than the input frequency (or

ADS808

14 SBAS179C

www.ti.com

undersampling). The following equation can be used to

calculate the achievable SNR for a given input frequency and

clock jitter (tJA in ps rms):

SNR ft

IN JA

(

)

20 1

log π

Depending on the nature of the clock source’s output imped-

ance, an impedance matching might become necessary. For

this, a termination resistor (RT) may be installed, as shown in

Figure 12. To calculate the correct value for this resistor,

consider the impedance ratio of the selected transformer and

the differential clock input impedance of the ADS808, which

is approximately 5.4kΩ.

It is not recommended to employ any type of differential TTL

logic that suffers from mismatch in delay time and slew-rate

leading to performance degradation. Alternatively, a low jitter

ECL or PECL clock may be AC-coupled directly to the clock

inputs using small (0.1µF) capacitors.

CLK

ADS808

1:1

RF Sine

Source

Output Enable (

)

The digital outputs of the ADS808 can be set to high

impedance (tri-state), exercising the output enable pin (

For normal operation, this pin must be at a logic LOW

potential, while a logic HIGH voltage disables the outputs.

Even though this function effects the output driver stage, the

threshold voltages for the

pin do not depend on the

output driver supply (VDRV), but are fixed (see the Digital

Inputs of the Electrical Characteristics table). Operating the

function dynamically (i.e., high speed multiplexing) should

be avoided, as it will corrupt the conversion process.

Power Down (PD)

A power-down of the ADS808 is initiated by taking the PD pin

HIGH. This shuts down portions within the converter and

reduces the power dissipation to about 20mW. The remain-

ing active blocks include the internal reference, ensuring a

fast reactivation time. During power-down, data in the con-

verter pipeline will be lost and new valid data will be subject

to the specified pipeline delay. In case the PD pin is not used,

it should be tied to ground or a logic LOW level.

Over-Range Indicator (OVR)

If the analog input voltage exceeds the full-scale range set by

the reference voltages, an over-range condition exists. The

ADS808 incorporates a function, that monitors the input volt-

age and detects any such out-of-range condition. The current

state can be read at the over-range indicator pin (OVR).

FIGURE 12. Applying a Sinusoidal Clock to the ADS808.

MINIMUM SAMPLING RATE

The pipeline architecture of the ADS808 uses the switched

capacitor technique in its internal track-and-hold stages. With

each clock cycle charges representing the captured signal

level are moved within the ADC pipeline core. The high

sampling speed necessitates the use of very small capacitor

values. In order to hold the droop errors LOW, the capacitors

require a minimum “refresh rate”. Therefore, the sampling

clock on the ADS808 should not drop below the specified

minimum of 1MHz.

DATA OUTPUT FORMAT (BTC)

The ADS808 makes two data output formats available, either

the “Straight Offset Binary” code (SOB) or the “Binary Two’s

Complement” code (BTC). The selection of the output coding

is controlled through the BTC pin. Applying a logic HIGH will

enable the BTC coding, while a logic LOW will enable the

SOB code. The BTC output format is widely used to interface

to microprocessors and such. The two code structures are

identical with the exception that the MSB is inverted for the

BTC format, as shown in Tables II and III.

SINGLE-ENDED BINARY TWO’S

INPUT (IN) STRAIGHT OFFSET COMPLEMENT

(IN Biased to VCM) BINARY (SOB) (BTC)

+FS – 1LSB 1111 1111 1111 0111 1111 1111

(

= CMV + FSR / 2)

+1/2 FS 1100 0000 0000 0100 0000 0000

Bipolar Zero 1000 0000 0000 0000 0000 0000

(IN = CMV)

–1/2 FS 0100 0000 0000 1100 0000 0000

–FS 0000 0000 0000 1000 0000 0000

(IN = CMV – FSR /2)

TABLE II. Coding Table for Single-Ended Input Configuration

with IN Tied to the Common-Mode Voltage (CMV).

STRAIGHT OFFSET BINARY TWO’S

BINARY COMPLEMENT

DIFFERENTIAL INPUT (SOB) (BTC)

+FS – 1LSB 1111 1111 1111 0111 1111 1111

(IN = +3V,

= +2V)

+1/2 FS 1100 0000 0000 0100 0000 0000

Bipolar Zero 1000 0000 0000 0000 0000 0000

(IN =

= CMV)

–1/2 FS 0100 0000 0000 1100 0000 0000

–FS 0000 0000 0000 1000 0000 0000

(IN = +2V,

= +3V)

TABLE III. Coding Table for Differential Input Configuration

and 2Vp-p Full-Scale Input Range.

ADS808 15

SBAS179C www.ti.com

FIGURE 13. Recommended Supply Decoupling Scheme.

This output is LOW when the input voltage is within the

defined input range. It will change to HIGH if the applied

signal exceeds the full-scale range. It should be noted that the

OVR output is updated along with the data output, corre-

sponding to the particular sampled analog input voltage.

Therefore, the OVR data is subject to the same pipeline delay

as the digital data (5 clock cycles).

Output Loading

It is recommended to keep the capacitive loading on the data

output lines as low as possible, preferably below 15pF.

Higher capacitive loading will cause larger dynamic currents

to flow as the digital outputs are changing. For example, with

a typical output slew-rate of 0.8V/ns and a total capacitive

loading of 10pF (including 4pF output capacitance, 5pF input

capacitance of external logic buffer, and 1pF pc-board

parasitics), a bit transition can cause a dynamic current of

10pF • 0.8V/1ns = 8mA. Those high current surges can feed

back to the analog portion of the ADS808 and adversely

affect the performance. External buffers, or latches, close to

the converter’s output pins may be used to minimize the

capacitive loading. They also provide the added benefit of

isolating the ADS808 from any digital activities on the bus

from coupling back high-frequency noise.

POWER SUPPLIES

When defining the power supplies for the ADS808, is it highly

recommended to consider linear supplies instead of switch-

ing types. Even with good filtering, switching supplies may

radiate noise that could interfere with any high-frequency

input signal and cause unwanted modulation products. At its

full conversion rate of 70MHz, the ADS808 requires typically

170mA of supply current on the +5V supply (+VS). Note that

this supply voltage should stay within a 5% tolerance. The

ADS808 does not require separate analog and digital sup-

plies, but only one single +5V supply to be connected to all

its +VS pins. This is with the exception of the output driver

supply pin, denoted VDRV (see the following section).

Digital Output Driver Supply (VDRV)

A dedicated supply pin, denoted VDRV, provides power to

the logic output drivers of the ADS808, and may be operated

with a supply voltage in the range of +3.0V to +5.0V. This can

simplify interfacing to various logic families, in particular low-

voltage CMOS. It is recommended to operate the ADS808

with a +3.0V supply voltage on VDRV. This will lower the

power dissipation in the output stages due to the lower output

swing and reduce current glitches on the supply line that may

affect the AC performance of the converter. The analog

supply (+VS) and driver supply (VDRV) may be tied together,

with a ferrite bead or inductor between the supply pins. Each

of the these supply pins must be bypassed separately with at

least one 0.1µF ceramic chip capacitor, forming a pi-filter.

The recommended operation for the ADS808 is +5V for the

+VS pins and +3.0V on the output driver pin (VDRV).

LAYOUT AND DECOUPLING CONSIDERATIONS

Proper grounding and bypassing, short lead length, and the

use of ground planes are particularly important for high-

frequency designs. Achieving optimum performance with a

fast sampling converter, like the ADS808, requires careful

attention to the pc-board layout to minimize the effect of

board parasitics and optimize component placement.

A multilayer board usually ensures best results and allows

convenient component placement.

The ADS808 should be treated as an analog component with

the +VS pins connected to clean analog supplies. This will

ensure the most consistent results, since digital supplies

often carry a high level of switching noise that could couple

into the converter and degrade the performance. As men-

tioned previously, the driver supply pins (VDRV) should also

be connected to a low-noise supply. Supplies of adjacent

digital circuits may carry substantial current transients. The

supply voltage must be thoroughly filtered before connecting

to the VDRV supply of the converter. All ground connections

on the ADS808 are internally bonded to the metal flag

(bottom of package) that forms a large ground plane. All

ground pins should directly connect to an analog ground

plane that covers the pc-board area under the converter.

Due to its high sampling frequency, the ADS808 generates

high-frequency current transients and noise (clock

feedthrough) that are fed back into the supply and reference

lines. If not sufficiently bypassed, this will add noise to the

conversion process. Figure 13 shows the recommended

supply decoupling scheme for the ADS808. All +VS pins may

be connected together and bypassed with a combination of

10nF to 0.1µF ceramic chip capacitors (0805, low ESR) and

a 10µF tantalum tank capacitor. A similar approach may be

used on the driver supply pins, VDRV. In order to minimize

the lead and trace inductance, the capacitors should be

located as close to the supply pins as possible. Where

double-sided component mounting is allowed, they are best

placed directly under the package. In addition, larger bipolar

decoupling capacitors (2.2µF to 10µF), effective at lower

frequencies, should also be used on the main supply pins.

They can be placed on the pc-board in proximity (< 0.5") of

the ADC.

2, 47, 48 35, 36, 37, 38

42, 43, 45

GND

ADS808

0.1µF

0.01µF 0.01µF 0.01µF

3, 4

5, 8, 31

GND

0.1µF

VDRV

9, 27

GND

0.1µF

+3V, +5V

+5V

ADS808

16 SBAS179C

www.ti.com

If the analog inputs to the ADS808 are driven differentially, it

is especially important to optimize towards a highly symmetri-

cal layout. Small trace length differences may create phase

shifts compromising a good distortion performance. For this

reason, the use of two single op amps (rather than one dual

amplifier) enables a more symmetrical layout and a better

match of parasitic capacitances. The pin orientation of the

ADS808 package follows a “flow-through” design with the

analog inputs located on one side of the package while the

digital outputs are located on the opposite side of the quad-

flat package. This provides a good physical isolation be-

tween the analog and digital connections. While designing

the layout, it is important to keep the analog signal traces

separated from any digital lines to prevent noise coupling

onto the analog portion.

Also, try to match trace length for the differential clock signal

(if used) to avoid mismatches in propagation delays. Single-

ended clock lines must be short and should not cross any

other signal traces.

Short-circuit traces on the digital outputs will minimize ca-

pacitive loading. Trace length should be kept short to the

receiving gate (< 2") with only one CMOS gate connected to

one digital output. If possible, the digital data outputs should

be buffered (with a 74LCX571, for example). Dynamic perfor-

mance may also be improved with the insertion of series

resistors at each data output line. This sets a defined time

constant and reduces the slew rate that would otherwise

flow, due to the fast edge rate. The resistor value may be

chosen to result in a time constant of 15% to 25% of the used

data rate.

LAYOUT OF PCB WITH

PowerPAD THERMALLY

ENHANCED PACKAGES

The ADS808 is housed in a 48-lead PowerPAD thermally

enhanced package. To make optimum use of the thermal

efficiencies designed into the PowerPAD package, the PCB

must be designed with this technology in mind. Please refer

to SLMA004 PowerPAD brief “PowerPAD Made Easy” on

our web site at www.ti.com, which addresses the specific

considerations required when integrating a PowerPAD pack-

age into the PCB design. For more detailed information,

including thermal modeling and repair procedures, please

see SLMA002 technical brief “PowerPAD Thermally En-

hanced Package” (www.ti.com).

PACKAGE OPTION ADDENDUM

www.ti.com 21-May-2010

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

ADS808Y/250 ACTIVE HTQFP PHP 48 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

ADS808Y/250G4 ACTIVE HTQFP PHP 48 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm) W

(mm) Pin1

Quadrant

ADS808Y/250 HTQFP PHP 48 250 177.8 16.4 9.6 9.6 1.5 12.0 16.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 20-Sep-2008

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

ADS808Y/250 HTQFP PHP 48 250 190.5 212.7 31.8

PACKAGE MATERIALS INFORMATION

www.ti.com 20-Sep-2008

Pack Materials-Page 2

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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products Applications

Audio www.ti.com/audio Communications and Telecom www.ti.com/communications

Amplifiers amplifier.ti.com Computers and Peripherals www.ti.com/computers

Data Converters dataconverter.ti.com Consumer Electronics www.ti.com/consumer-apps

DLP® Products www.dlp.com Energy and Lighting www.ti.com/energy

DSP dsp.ti.com Industrial www.ti.com/industrial

Clocks and Timers www.ti.com/clocks Medical www.ti.com/medical

Interface interface.ti.com Security www.ti.com/security

Logic logic.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense

Power Mgmt power.ti.com Transportation and www.ti.com/automotive

Automotive

Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video

RFID www.ti-rfid.com Wireless www.ti.com/wireless-apps

RF/IF and ZigBee® Solutions www.ti.com/lprfTI E2E Community Home Page e2e.ti.com

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265