General Description
The DS1089L is a clock generator that produces a
spread spectrum (dithered) square-wave output of fre-
quencies from 130kHz to 66.6MHz. The DS1089L is
shipped from the factory programmed at a specific fre-
quency. The DS1089L is pin-for-pin compatible with the
DS1087L, however, the DS1089L dithers at equal per-
centages above and below the center frequency. The
user still has access to the internal frequency divider,
selectable ±1%, ±2%, ±4%, or ±8% dithered output,
dithering rate, and programmable output power-
down/disable mode through an I2C-compatible pro-
gramming interface. All the device settings are stored
in nonvolatile (NV) EEPROM allowing it to operate in
stand-alone applications. The DS1089L also has
power-down and output-enable control pins for power-
sensitive applications.
Applications
Automotive Infotainment
Printers
Copiers
Computer Peripherals
POS Terminals
Cable Modems
Features
♦Factory-Programmed Square-Wave Generator
from 33.3MHz to 66.6MHz
♦Center Frequency Remains Constant Independent
of Dither Percentage
♦No External Timing Components Required
♦EMI Reduction
♦Variable Dither Frequency
♦User Programmable Down to 130kHz with Divider
(Dependent on Master Oscillator Frequency)
♦±1%, ±2%, ±4%, or ±8% Selectable Dithered
Output
♦Glitchless Output-Enable Control
♦I2C-Compatible Serial Interface
♦Nonvolatile Settings
♦Power-Down Mode
♦Programmable Output Power-Down/Disable Mode
DS1089L
3.3V Center Spread-Spectrum EconOscillator™
______________________________________________ Maxim Integrated Products 1
Rev 2; 5/06
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
*See Standard Frequency Options Table.
Ordering Information
Pin Configuration and Typical Operating Circuits appear at end of data sheet.
PART TEMP RANGE PIN-PACKAGE
DS1089LU-yxx* -40°C to +85°C
8 µSOP (118 mil)
Add “/T” for Tape and Reel.
Custom frequencies available, contact factory.
Standard Frequency Options
PART FREQUENCY (MHz) SPREAD (±%) DITHER FREQUENCY
DS1089LU-21G 14.7456 1 fMOSC / 4096
DS1089LU-4CL 18.432 2 fMOSC / 4096
DS1089LU-22F 24.576 1 fMOSC / 2048
DS1089LU-23C 33.3 1 fMOSC / 4096
DS1089LU-450 50.0 2 fMOSC / 4096
DS1089LU-866 66.6 4 fMOSC / 4096
DS1089LU-yxx Fixed up to 66.6 1, 2, 4, or 8 fMOSC / 2048 or 4096 or 8192
EconOscillator is a trademark of Dallas Semiconductor Corp.
DS1089L
3.3V Center Spread-Spectrum EconOscillator™
2 _____________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage on VCC Relative to Ground.......................-0.5V to +6.0V
Voltage on SPRD, PDN, OE, SDA,
SCL Relative to Ground* ........................-0.5V to (VCC + 0.5V)
Operating Temperature Range ...........................-40°C to +85°C
Programming Temperature Range.........................0°C to +70°C
Storage Temperature Range.............................-55°C to +125°C
Soldering Temperature...................See IPC/JEDEC J-STD-020A
PARAMETER
SYMBOL
CONDITION
MIN TYP MAX
UNITS
Supply Voltage VCC (Note 1) 2.7 3.3 3.6 V
High-Level Input Voltage
(SDA, SCL, SPRD, PDN, OE) VIH 0.7 x VCC VCC +
0.3 V
Low-Level Input Voltage
(SDA, SCL, SPRD, PDN, OE) VIL
-0.3
0.3 x
VCC
V
*This voltage must not exceed 6.0V.
RECOMMENDED OPERATING CONDITIONS
(TA= -40°C to +85°C)
PARAMETER
SYMBOL
CONDITION
MIN TYP MAX
UNITS
High-Level Output Voltage (OUT)
VOH IOH = -4mA, VCC = min 2.4 V
Low-Level Output Voltage (OUT)
VOL IOL = 4mA 0.4 V
VOL1 3mA sink current 0.4
Low-Level Output Voltage (SDA)
VOL2 6mA sink current 0.6 V
High-Level Input Current IIH VIH = VCC 1µA
Low-Level Input Current IIL VIL = 0V -1 µA
Supply Current (Active) ICC CL = 15pF, fOUT = fMOSCmax 12 mA
Standby Current (Power-Down) ICCQ Power-down mode 10 µA
DC ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +3.6V, TA= -40°C to +85°C)
DS1089L
3.3V Center Spread-Spectrum EconOscillator™
_____________________________________________________________________ 3
PARAMETER
SYMBOL
CONDITION
MIN TYP MAX
Internal Master Oscillator
Frequency fMOSC
33.3 66.6
Master Oscillator Frequency
Tolerance VCC = 3.3V,
TA = +25°C (Notes 2, 10)
-0. 5 +0. 5
%
Voltage Frequency
Variation TA = +25°C (Note 3)
-0.75 +0.75
%
TA = 0°C to +85°C
-0.75 +0.75
Temperature Frequency Variation
(Note 4) VCC = 3.3V,
fOUT = fMOSCmax TA = -40°C to 0°C
-2.00 +0.75
%
J3 = J2 = GND ±1
J3 = GND, J2 = VCC ±2
J3 = VCC, J2 = GND ±4
Dither Frequency Range
(Note 5)
J3 = J2 = VCC ±8
%
J1 = GND, J0 = VCC fMOSC / 2048
J1 = VCC, J0 = GND fMOSC / 4096
Dither Frequency
(Note 5) fMOD J1 = J0 = VCC fMOSC / 8192 Hz
MASTER OSCILLATOR CHARACTERISTICS
(VCC = +2.7V to +3.6V, TA= -40°C to +85°C)
PARAMETER
SYMBOL
CONDITION
MIN TYP MAX
UNITS
Frequency Stable After
PRESCALER Change 1
Period
Power-Up Time tPOR +
tSTAB (Note 6) 40 200 µs
Enable of OUT After Exiting
Power-Down Mode tSTAB (Note 6) 512 clock
cycles
OUT Disabled After Entering
Power-Down Mode tPDN 7µs
Load Capacitance CL15 50 pF
Output Duty Cycle (fOUT) 50 %
AC ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +3.6V, TA= -40°C to +85°C)
∆f
fMOSC
MOSC
∆f
fMOSC
∆f
fMOSC
DS1089L
3.3V Center Spread-Spectrum EconOscillator™
4 _____________________________________________________________________
Note 1: All voltages are referenced to ground.
Note 2: This is the absolute accuracy of the master oscillator frequency at the default settings with spread disabled.
Note 3: This is the change that is observed in master oscillator frequency with changes in voltage at TA= +25°C.
Note 4: This is the change that is observed in master oscillator frequency with changes in temperature at VCC = 3.3V.
Note 5: The dither deviation of the master oscillator frequency is biderectional and results in an output frequency centered at the
undithered frequency.
Note 6: This indicates the time elapsed between power-up and the output becoming active. An on-chip delay is intentionally intro-
duced to allow the oscillator to stabilize. tSTAB is equivalent to 512 master clock cycles and will depend on the programmed
master oscillator frequency.
Note 7: Timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C standard-mode timing.
Note 8: CB—total capacitance of one bus line in picofarads.
Note 9: EEPROM write time applies to all the EEPROM memory and SRAM shadowed EEPROM memory when WC = 0.
The EEPROM write time begins after a stop condition occurs.
Note 10:Typical frequency shift due to aging is ±0.25%. Aging stressing includes Level 1 moisture reflow conditioning (24hr) +125°C
bake, 168hr +85°C/85°RH moisture soak, and three solder reflow passes +260 +0/-5°C peak) followed by 408hr max VCC
biased 125°C HTOL, 500 temperature cycles at -55°C to +125°C, 96hr +130°C/85%RH/3,6V HAST and 168hr +121°C/2 ATM
Steam/Unbiased Autoclave.
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
SCL Clock Frequency fSCL (Note 7) 0 400 kHz
Bus Free Time Between Stop and
Start Conditions tBUF 1.3 µs
Hold Time (Repeated) Start
Condition
tHD:STA
0.6 µs
Low Period of SCL tLOW 1.3 µs
High Period of SCL tHIGH 0.6 µs
Data Hold Time
tHD:DAT
0 0.9 µs
Data Setup Time
tSU:DAT 100
ns
Start Setup Time tSU:STA 0.6 µs
SDA and SCL Rise Time tR(Note 8) 20 + 0.1CB300 ns
SDA and SCL Fall Time tF(Note 8) 20 + 0.1CB300 ns
Stop Setup Time
tSU:STO
0.6 µs
SDA and SCL Capacitive
Loading CB(Note 8) 400 pF
EEPROM Write Time tWR (Note 9) 10 20 ms
AC ELECTRICAL CHARACTERISTICS—I2C INTERFACE
(VCC = +2.7V to +3.6V, TA= -40°C to +85°C, unless otherwise noted. Timing referenced to VIL(MAX) and VIH(MIN).)
PARAMETER
SYMBOL
CONDITION
MIN TYP MAX
UNITS
Writes +70°C
10,000
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = +2.7V to +3.6V)
DS1089L
3.3V Center Spread-Spectrum EconOscillator™
_____________________________________________________________________ 5
0
2
6
4
8
10
ACTIVE SUPPLY CURRENT
vs. SUPPLY VOLTAGE
DS 1089L toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
2.7 3.0 3.3 3.6
66MHz
50MHz 130kHz
33MHz
TA = +25°C,
OUTPUT
UNLOADED
0
3
2
1
4
5
6
7
8
9
10
-40 10-15 35 60 85
ACTIVE SUPPLY CURRENT
vs. TEMPERATURE
DS 1089L toc02
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
66MHz
50MHz 130kHz
33MHz
TA = +25°C,
OUTPUT
UNLOADED
0
1 100010010
SUPPLY CURRENT
vs. PRESCALER
10
4
2
8
6
DS 1089L toc03
PRESCALE DIVIDER (DECIMAL)
SUPPLY CURRENT (mA)
3.6V
3.3V
2.7V
TA = +25°C,
fMOSC = 50MHz,
OUTPUT UNLOADED
0
1
3
2
4
5
-40 10-15 35 60 85
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
DS 1089L toc04
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
VCC = 3.3V,
PDN = GND
-0.50
-0.25
0
0.25
0.50
2.7 3.0 3.3 3.6
FREQUENCY % CHANGE
vs. SUPPLY VOLTAGE
DS 1089L toc05
SUPPLY VOLTAGE (V)
FREQUENCY CHANGE (%)
66MHz
50MHz
130kHz
33MHz
TA = +25°C
-0.8
-0.6
-0.2
-0.4
0
0.2
-40 10-15 35 60 85
FREQUENCY % CHANGE
vs. TEMPERATURE
DS 1089L toc06
TEMPERATURE (°C)
FREQUENCY CHANGE (%)
66MHz
50MHz
130kHz
33MHz
VCC = 3.3V
Typical Operating Characteristics
(VCC = 3.3V, TA= +25°C, unless otherwise noted.)
Pin Description
PIN
NAME
FUNCTION
1 OUT Oscillator Output
2
SPRD
Dither Enable. When the pin is high, the dither is enabled. When the pin is low, the dither is disabled.
3V
CC Power Supply
4
GND
Ground
5OE
Output Enable. When the pin is high, the output buffer is enabled. When the pin is low, the output is disabled
but the internal master oscillator is still on.
6PDN
Power-Down. When the pin is high, the master oscillator is enabled. When the pin is low, the master oscillator
and the output buffer are disabled (power-down mode).
7 SDA I2C Serial Data. This pin is for serial data transfer to and from the device.
8 SCL I2C Serial Clock. This pin is used to clock data into and out of the device.
DS1089L
3.3V Center Spread-Spectrum EconOscillator™
6 _____________________________________________________________________
48
50
54
52
56
58
-40 10-15 35 60 85
DUTY CYCLE vs. TEMPERATURE
DS 1089L toc08
TEMPERATURE (°C)
DUTY CYCLE (%)
66MHz 50MHz
130kHz
33MHz
VCC = 3.3V
48
50
54
52
56
58
DUTY CYCLE
vs. SUPPLY VOLTAGE
DS 1089L toc07
SUPPLY VOLTAGE (V)
DUTY CYCLE (%)
2.7 3.0 3.3 3.6
66MHz
50MHz
130kHz
33MHz
TA = +25°C
-90
-70
-80
-40
-50
-60
-10
-20
-30
0
44 4846 50 52 54 56
SPECTRUM COMPARISON
(120kHz BW, SAMPLE DETECT)
DS 1089L toc09
FREQUENCY (MHz)
POWER SPECTRUM (dBm)
NO SPREAD
±1%
±2%
±4% ±8%
fMOSC = 50MHz,
DITHER RATE = fMOSC / 4096
Typical Operating Characteristics (continued)
(VCC = 3.3V, TA= +25°C, unless otherwise noted.)
DS1089L
3.3V Center Spread-Spectrum EconOscillator™
_____________________________________________________________________ 7
Block Diagram
FACTORY-
PROGRAMMED
MASTER
OSCILLATOR
33.3MHz TO
66.6MHz
PRESCALER
DIVIDE BY 1, 2, 4,
8, 16, 32, 64,
128, OR 256
TRIANGLE-
WAVE
GENERATOR
I2C SERIAL
INTERFACE
PRESCALER
ADDR
P0P1P2P3X
LO/
HIZ
J0J1
A0A1A2WCXOEJ2
J3
VCC
VCC
SCL
SDA
DITHER RATE
DITHER %
EEPROM
WRITE EE
COMMAND
OUT
I2C
ADDRESS
BITS
PRESCALER SETTING
EEPROM
WRITE
CONTROL
CONTROL REGISTERS
fMOD
fOSC
fMOSC
fMOSC
fOUT
SYNCED
OUTPUT
BUFFER
OUTPUT CONFIGURATION
OUTPUT CONTROL
OE
PDN
GND
SPRD
S/W GATED OUTPUT
H/W GATED OUTPUT
DS1089L
Detailed Description
Master Oscillator
The internal master oscillator is capable of generating a
square wave with a 33.3MHz to 66.6MHz frequency
range. The master oscillator frequency (fMOSC) is factory
programmed, and is specified in the Ordering Information.
Prescaler
The user can program the prescaler divider to produce
an output frequency (fOUT) as low as 130kHz using bits
P0, P1, P2, and P3 in the PRESCALER register. The
output frequency can be calculated using Equation 1.
Any value programmed greater than 28will be decod-
ed as 28. See Table 1 for prescaler divider settings.
Equation 1
where x = P3, P2, P1, P0
Output Frequency Hz f f
OSC MOSC
x
() =2
BITS P3, P2,
P1, P0 2x =f
OUT = fOSC
0000 1 fMOSC
0001 2 fMOSC / 2
0010 4 fMOSC / 4
0011 8 fMOSC / 8
0100 16 fMOSC / 16
0101 32 fMOSC / 32
0110 64 fMOSC / 64
0111 128 fMOSC / 128
1000 256 fMOSC / 256
1111 256 fMOSC / 256
Table 1. Prescaler Divider Settings
DS1089L
3.3V Center Spread-Spectrum EconOscillator™
8 _____________________________________________________________________
Output Control
Two user control signals control the output. The output
enable pin (OE) gates the output buffer and the power-
down pin (PDN) disables the master oscillator and
turns off the output for power-sensitive applications.
(Note: the power-down command must persist for at
least two output frequency cycles plus 10µs for
deglitching purposes.) On power-up, the output is dis-
abled until power is stable and the master oscillator has
generated 512 clock cycles.
Additionally, the OE input is OR’ed with the OE bit in the
ADDR register, allowing for either hardware or software
gating of the output waveform (see the Block Diagram).
Both controls feature a synchronous enable, which
ensures that there are no output glitches when the out-
put is enabled. The synchronous enable also ensures a
constant time interval (for a given frequency setting)
from an enable signal to the first output transition.
Dither Generator
The DS1089L has the ability to reduce radiated emis-
sion peaks. The output frequency can be dithered by
±1%, ±2%, ±4%, or ±8% symmetrically around the pro-
grammed center frequency. Although the output fre-
quency changes when the dither is enabled, the duty
cycle does not change.
The dither rate (fMOD) is controlled by the J0 and J1
bits in the PRESCALER register and is enabled with the
SPRD pin. The maximum spectral attenuation occurs
when the prescaler is set to 1. The spectral attenuation
is reduced by 2.7dB for every factor of 2 that is used in
the prescaler. This happens because the prescaler’s
divider function tends to average the dither in creating
the lower frequency. However, the most stringent spec-
tral emission limits are imposed on the higher frequen-
cies where the prescaler is set to a low divider ratio.
A triangle-wave generator injects an offset element into
the master oscillator to dither its output. The dither rate
can be calculated based on the master oscillator fre-
quency (see Equation 2).
Equation 2
where fMOD = dither frequency, fMOSC = master oscilla-
tor frequency, and n= divider setting (see Table 2).
Dither Percentage Settings
The dither amplitude (measured in percentage of the
master oscillator center frequency) is set using the J2
and J3 bits in the ADDR register. This circuit uses a
sense current from the master oscillator bias circuit to
adjust the amplitude of the triangle-wave signal to a
voltage level that modulates the master oscillator to a
percentage of its factory-programmed center frequen-
cy. This percentage is set in the application to be ±1%,
±2%, ±4%, or ±8% (see Table 3).
The location of bits P3, P2, P1, P0, J1, and J0 in the
PRESCALER register and bits J3 and J2 in the ADDR
register are shown in the Register Summary section.
ff
MOD MOSC
=n
Table 2. Dither Frequency Settings
BITS J1, J0 DITHER FREQUENCY
00 No dither
01 fMOSC / 2048
10 fMOSC / 4096
11 fMOSC / 8192
Table 3. Dither Percentage Settings
BITS J3, J2 DITHER AMOUNT
00 ±1%
01 ±2%
10 ±4%
11 ±8%
When dither is enabled (by selecting a dither frequency
setting greater than 0 with SPRD high), the master
oscillator frequency is dithered around the center fre-
quency by the selected percentage from the pro-
grammed fMOSC (see Figure 2). For example, if fMOSC
is programmed to 40MHz (factory setting) and the
dither amount is programmed to ±1%, the frequency of
fMOSC will dither between 39.6MHz and 40.4MHz at a
modulation frequency determined by the selected
dither frequency. Continuing with the same example, if
J1 = 0 and J0 = 1, selecting fMOSC / 2048, then the
dither frequency would be 19.531kHz.
Register Summary
The DS1089L registers are used to change the dither
amount, output frequency, and slave address. A bit
summary of the registers is shown in Table 4. Once pro-
grammed into EEPROM, the settings only need to be
reprogrammed if it is desired to reconfigure the device.
PRESCALER Register
Bits 7 to 6: Dither Frequency. The J1 and J0 bits
control the dither frequency applied to the
output. See Table 2 for divider settings. If
either of bits J1 or J0 is high and SPRD is
high, dither is enabled.
Bit 5: Output Low or Hi-Z. The LO/HIZ bit
determines the state of the output during
power-down. While the output is deacti-
vated, if the LO/HIZ bit is set to 0, the out-
put will be high impedance (high-Z). If the
LO/HIZ bit is set to 1, the output will be
driven low.
Bit 4: Reserved.
Bits 3 to 0: Prescaler Divider. The prescaler bits (bits
P3 to P0) divide the master oscillator fre-
quency by 2xwhere x can be from 0 to 8.
Any prescaler bit value entered that is
greater than 8 will decode as 8. See Table
1 for prescaler settings.
ADDR Register
Bits 7 to 6: Dither Percentage. The J3 and J2 bits
control the selected dither amplitude (%).
When both J3 and J2 are set to 0, the
default dither rate is ±1%.
Bit 5: Output Enable. The OE bit and the OE
pin state determine if the output is on
when the device is active (PDN = VIH). If
(OE = 0 OR OE is high) AND the PDN pin
is high, the output will be driven.
Bit 4: Reserved.
Bit 3: Write Control. The WC bit determines if
the EEPROM is to be written after register
contents have been changed. If WC = 0
(default), EEPROM is written automatically
after a write. If WC = 1, the EEPROM is
only written when the WRITE EE command
is issued. See the WRITE EE Command
section for more information.
Bits 2 to 0: Address. The A0, A1, A2 bits determine
the lower nibble of the I2C slave address.
DS1089L
3.3V Center Spread-Spectrum EconOscillator™
_____________________________________________________________________ 9
IF DITHER AMOUNT = 0%
(+1, 2, 4,
OR 8% OF fMOSC)
PROGRAMMED
fMOSC
(-1, 2, 4,
OR 8% OF fMOSC)
DITHER
AMOUNT
(2, 4, 8,
OR 16%)
TIME
1
fMOD
fMOSC
Figure 2. Output Frequency vs. Dither Rate
Table 4. Register Summary
REGISTER
ADDR
BIT7
BINARY
BIT0
DEFAULT ACCESS
PRESCALER 02h
J1 J0 LO/
HIZ
X
P3 P2 P1 P0
xx00xxxxb R/W
ADDR 0Dh
J3 J2 OE
X
WC A2 A1 A0
xx100000b R/W
WRITE EE 3Fh No Data ——
X = “don’t care”
x = values depend on custom settings
DS1089L
WRITE EE Command
The WRITE EE command is useful in closed-loop appli-
cations where the registers are frequently written. In
applications where the register contents are frequently
written, the WC bit should be set to 1 to prevent wear-
ing out the EEPROM. Regardless of the value of the WC
bit, the value of the ADDR register is always written
immediately to EEPROM. When the WRITE EE com-
mand has been received, the contents of the registers
are written into the EEPROM, thus locking in the regis-
ter settings.
3.3V Center Spread-Spectrum EconOscillator™
10 ____________________________________________________________________
STOP
CONDITION
OR REPEATED
START
CONDITION
REPEATED IF MORE BYTES
ARE TRANSFERRED
ACK
START
CONDITION
ACK
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
SLAVE ADDRESS
MSB
SCL
SDA
R/W
DIRECTION
BIT
12 678 9 12 893–7
Figure 3. I2C Data Transfer Protocol
101
1R/W
A0
A1
A2
MSB LSB
DEVICE
IDENTIFIER
DEVICE
ADDRESS
READ/WRITE BIT
Figure 4. Slave Address Byte
I2C Serial Port Operation
DS1089L
3.3V Center Spread-Spectrum EconOscillator™
____________________________________________________________________ 11
SDA
SCL
tHD:STA
tLOW
tHIGH
tRtF
tBUF
tHD:DAT
tSU:DAT REPEATED
START
tSU:STA
tHD:STA
tSU:STO
tSP
STOP START
Figure 5. I2C AC Characteristics
SLAVE
ACK
10 1
1R/WA0*A1* SLAVE
ACK
A2*
MSB LSB
DEVICE IDENTIFIER DEVICE
ADDRESS
READ/
WRITE
MSB LSB
COMMAND/REGISTER ADDRESS
SLAVE
ACK
MSB LSB
b7 b6 b5 b4 b3 b2 b1 b0 SLAVE
ACK STOP
*THE ADDRESS DETERMINED BY A0, A1, AND A2 MUST
MATCH THE ADDRESS SET IN THE ADDR REGISTER.
DATA
TYPICAL I
2
C WRITE TRANSACTION
EXAMPLE I
2
C TRANSACTIONS (WHEN A0, A1, AND A2 ARE ZERO)
A) SINGLE BYTE WRITE
-WRITE PRESCALER
REGISTER TO 128
B) SINGLE BYTE READ
-READ PRESCALER
REGISTER
START
START
START
B0h
B0h
SLAVE
ACK
SLAVE
ACK
02h
02h
SLAVE
ACK
SLAVE
ACK
DATA
SLAVE
ACK STOP
10110000
10110000
b7 b6 b5 b4 b3 b2 b1 b0
00000010 10000000
10000000
00000010 REPEATED
START
DATA
MASTER
NACK STOP
SLAVE
ACK
10110001
B1h
Figure 6. I2C Transactions
Applications Information
Power-Supply Decoupling
To achieve the best results when using the DS1089L,
decouple the power supply with 0.01µF and 0.1µF
high-quality, ceramic, surface-mount capacitors.
Surface-mount components minimize lead inductance,
which improves performance, and ceramic capacitors
tend to have adequate high-frequency response for
decoupling applications. These capacitors should be
placed as close to the VCC and GND pins as possible.
Stand-Alone Mode
SCL and SDA cannot be left floating even in stand-
alone mode. If the DS1089L will never need to be pro-
grammed in-circuit, including during production
testing, SDA and SCL can be connected high.
DS1089L
3.3V Center Spread-Spectrum EconOscillator™
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
is a registered trademark of Dallas Semiconductor Corporation.
Package Information
For the latest package outline information, go to
www.maxim-ic.com/DallasPackInfo.
Chip Topology
TRANSISTOR COUNT: 5985
SUBSTRATE CONNECTED TO GROUND
PDN
OEGND
1
2
8
7
SCL
SDA
SPRD
VCC
OUT
µSOP (118 mils)
TOP VIEW
3
4
6
5
DS1089L
Pin Configuration
OUT
SPRD
GND OE
PDN
SDA
SCL
VCC
VCC
VCC
VCC
4.7kΩ4.7kΩ
2-WIRE
INTERFACE
DITHERED 130kHz
TO 66.6MHz OUTPUT
DECOUPLING CAPACITORS
(0.1µF and 0.01µF)
*SDA AND SCL CAN BE CONNECTED DIRECTLY HIGH IF THE DS1089L NEVER
NEEDS TO BE PROGRAMMED IN-CIRCUIT, INCLUDING DURING PRODUCTION TESTING.
DS1089L
OUT
N.C.
SPRD
GND OE
PDN
SDA*
SCL*
VCC
VCC
VCC
DITHERED 130kHz
TO 66.6MHz OUTPUT
XTL2/OSC2
XTL1/OSC1
MICROPROCESSOR
DECOUPLING CAPACITORS
(0.1µF and 0.01µF)
DS1089L
Typical Operating Circuits
PROCESSOR-CONTROLLED MODE STAND-ALONE MODE