CY22381
CY223811
Three-PLL General Purpose FLASH
Programmable Clock Generator
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-07012 Rev. *I Revised May 17, 2011
Features
■Three integrated phase-locked loops
■Ultra-wide divide counters (eight-bit Q, eleven-bit P, and
seven-bit post divide)
■Improved linear crystal load capacitors
■Flash programmability
■Field programmability
■Low-jitter, high-accuracy outputs
■Power-management options (Shutdown, OE, Suspend)
■Configurable crystal drive strength
■Frequency select option through external LVTTL Input
■3.3 V operation
■8-pin small outline integrated circuit (SOIC) package
(CY22381)
■8-pin SOIC package with NiPdAu lead finish (CY223811)
■CyClocks RT™ support
Functional Description
The CY22381 is the next-generation programmable Flash
programmable clock for use in networking, telecommunication,
datacom, and other general-purpose applications. The CY22381
offers up to three configurable outputs in a 8-pin SOIC, running
off a 3.3 V power supply. The on-chip reference oscillator is
designed to run off an 8–30-MHz crystal, or a 1–166-MHz
external clock signal. The CY22381 has a three PLLs driving 3
programmable output clocks. The output clocks are derived from
the PLL or the reference frequency (REF). Output post dividers
are available for either. The CY223811 is the CY22381 with
NiPdAu lead finish.
XTALIN
XTALOUT
FS/SUSPEND
SHUTDOWN/OE
CONFIGURATION
FLASH
OSC.
PLL1
11-BIT P
8-BIT Q
PLL2
11-BIT P
8-BIT Q
PLL3
11-BIT P
8-BIT Q
4 × 3
Switch
Crosspoint
Divider
7-BIT
Divider
7-BIT
Divider
7-BIT
CLKA
CLKB
CLKC
Logic Block Diagram
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CY22381
CY223811
Document #: 38-07012 Rev. *I Page 2 of 11
Contents
Features ............................................................................. 1
Functional Description .....................................................1
Logic Block Diagram ........................................................1
Pinouts ..............................................................................3
Pin Definitions .................................................................. 3
Operation ........................................................................... 3
Configurable PLLs ....................................................... 3
General-Purpose Input ................................................ 3
Crystal Input ................................................................ 3
Crystal Drive Level and Power .................................... 4
Output Configuration ...................................................4
Power-Saving Features ............................................... 4
Improving Jitter ............................................................4
CyClocks RT Software ..................................................... 4
Maximum Ratings .............................................................5
Operating Conditions ....................................................... 5
Recommended Crystal Specifications ........................... 5
Electrical Characteristics ................................................. 5
Switching Characteristics ................................................ 6
Switching Waveforms ...................................................... 6
Possible Configurations ............................................... 8
Ordering Information ........................................................ 8
Package Drawing and Dimensions ................................ 9
Acronyms .......................................................................... 9
Document Conventions ................................................... 9
Units of Measure ......................................................... 9
Document History Page ................................................. 10
Sales, Solutions, and Legal Information ...................... 11
Worldwide Sales and Design Support ....................... 11
Products .................................................................... 11
PSoC Solutions ......................................................... 11
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CY22381
CY223811
Document #: 38-07012 Rev. *I Page 3 of 11
Pinouts
Figure 1. CY22381, CY223811- 8-pin SOIC
Operation
The CY22381 is an upgrade to the existing CY2081. The new
device has a wider frequency range, greater flexibility, improved
performance, and incorporates many features that reduce PLL
sensitivity to external system issues.
The device has three PLLs that allow each output to operate at
an independent frequencies. These three PLLs are completely
programmable.
The CY223811 is the CY22381 with NiPdAu lead finish.
Configurable PLLs
PLL1 generates a frequency that is equal to the reference
divided by an eight-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL1 is sent
to the crosspoint switch. The frequency of PLL1 can optionally
be changed by using the external CMOS general purpose input.
See the following section on “General-Purpose Input” for more
detail.
PLL2 generates a frequency that is equal to the reference
divided by an eight-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL2 is sent
to the crosspoint switch.
PLL3 generates a frequency that is equal to the reference
divided by an eight-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL3 is sent
to the cross-point switch.
General-Purpose Input
The CY22381 features an output control pin (pin 8) that can be
programmed to control one of four features.
When programmed as a frequency select (FS), the input can
select between two arbitrarily programmed frequency settings.
The frequency select can change the following; the frequency of
PLL1, the output divider of CLKB, and the output divider of
CLKA. Any divider change as a result of switching the FS input
is guaranteed to be glitch free.
The general-purpose input can simultaneously control the
Suspend feature, turning off a set of PLLs and outputs
determined during programming.
When programmed as an output enable (OE) the input forces all
outputs to be placed in a three-state condition when LOW.
When programmed as a Shutdown, the input forces a full chip
shutdown mode when LOW.
Crystal Input
The input crystal oscillator is an important feature of this device
because of its flexibility and performance features.
The oscillator inverter has programmable drive strength. This
allows for maximum compatibility with crystals from various
manufacturers, processes, performances, and qualities.
The input load capacitors are placed on-die to reduce external
component cost. These capacitors are true parallel-plate
capacitors for ultra-linear performance. These were chosen to
reduce the frequency shift that occurs when non-linear load
capacitance interacts with load, bias, supply, and temperature
changes. Non-linear (FET gate) crystal load capacitors must not
be used for MPEG, communications, or other applications that
are sensitive to absolute frequency requirements
The value of the load capacitors is determined by six bits in a
programmable register. The load capacitance can be set with a
resolution of 0.375pF for a total crystal load range of 6pF to 30pF.
For driven clock inputs the input load capacitors may be
completely bypassed. This enables the clock chip to accept
driven frequency inputs up to 166 MHz. If the application requires
a driven input, then XTALOUT must be left floating.
Pin Definitions
Name Pin Number Description
CLKC 1 Configurable clock output C
GND 2 Ground
XTALIN 3 Reference crystal input or external reference clock input
XTALOUT 4 Reference crystal feedback (float if XTALIN is driven by external reference clock)
CLKB 5 Configurable clock output B
CLKA 6 Configurable clock output A
VDD 7 Power supply
FS/SUSPEND/
OE/SHUTDOWN
8 General Purpose Input. Can be Frequency Control, Suspend mode control, Output Enable,
or full-chip shutdown.
1
2
3
45
6
7
8
CLKC
GND
XTALIN
XTALOUT
FS/SUSPEND/OE/SHUTDOWN
VDD
CLKA
CLKB
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CY22381
CY223811
Document #: 38-07012 Rev. *I Page 4 of 11
Crystal Drive Level and Power
Crystals are specified to accept a maximum drive level.
Generally, larger crystals can accept more power. The drive level
specification in the table below is a general upper bound for the
power driven by the oscillator circuit in the CY22381.
For a given voltage swing, power dissipation in the crystal is
proportional to ESR and proportional to the square of the crystal
frequency. (Note that actual ESR is sometimes much less than
the value specified by the crystal manufacturer.) Power is also
almost proportional to the square of CL.
Power can be reduced to less than the DL specification in the
table below by selecting a reduced frequency crystal with low CL
and low R1 (ESR).
Output Configuration
Under normal operation there are four internal frequency
sources that may be routed through a programmable crosspoint
switch to any of the three outputs through programmable
seven-bit output dividers. The four sources are: reference, PLL1,
PLL2, and PLL3. The following is a description of each output.
CLKA’s output originates from the crosspoint switch and goes
through a programmable seven-bit post divider. The seven-bit
post divider derives its value from one of two programmable
registers controlled by FS.
CLKB’s output originates from the crosspoint switch and goes
through a programmable seven-bit post divider. The seven-bit
post divider derives its value from one of two programmable
registers controlled by FS.
CLKC’s output originates from the crosspoint switch and goes
through a programmable seven-bit post divider. The seven-bit
post divider derives its value from one programmable register.
The Clock outputs have been designed to drive a single point
load with a total lumped load capacitance of 15pF. While driving
multiple loads is possible with the proper termination, it is
generally not recommended.
Power-Saving Features
When configured as OE, the general-purpose input three-states
all outputs when pulled LOW. When configured as Shutdown, a
LOW on this pin three-states all outputs and shuts off the PLLs,
counters, the reference oscillator, and all other active
components. The resulting current on the VDD pins is less than
5A (typical). After leaving shutdown mode, the PLLs has to
relock.
When configured as SUSPEND, the general-purpose input can
be configured to shut down a customizable set of outputs and/or
PLLs, when LOW. All PLLs and any of the outputs can be shut
off in nearly any combination. The only limitation is that if a PLL
is shut off, all outputs derived from it must also be shut off.
Suspending a PLL shuts off all associated logic, while
suspending an output forces a three-state condition.
Improving Jitter
Jitter optimization control is useful in mitigating problems related
to similar clocks switching at the same moment and causing
excess jitter. If one PLL is driving more than one output, the
negative phase of the PLL can be selected for one of the outputs.
This prevents the output edges from aligning, allowing superior
jitter performance.
CyClocks RT Software
CyClocks RT is our second-generation application that allows
users to configure this device. The easy-to-use interface offers
complete control of the many features of this family including
input frequency, PLL and output frequencies, and different
functional options. Data sheet frequency range limitations are
checked and performance tuning is automatically applied. You
can download a free copy of CyClocks RT on Cypress’s web site
at http://www.cypress.com.
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CY22381
CY223811
Document #: 38-07012 Rev. *I Page 5 of 11
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Supply voltage ..............................................–0.5 V to +7.0 V
DC input voltage .............................–0.5 V to + (VDD + 0.5 V)
Storage temperature..................................... –65 °C +125 °C
Junction temperature.................................................. 125 °C
Data retention at Tj = 125 °C.................................> 10 years
Maximumrprogamming cycles..........................................100
Package power dissipation....................................... 250 mW
Static discharge voltage
(per MIL-STD-883, Method 3015) ........................... 2000V
Latch up (per JEDEC 17) ....................................
±2 00 m A
Operating Conditions
Parameter Description Min Typ Max Unit
VDD Supply voltage 3.135 3.3 3.465 V
TACommercial operating temperature, ambient 0 – +70 °C
Industrial operating temperature, ambient –40 – +85 °C
CLOAD_OUT Max. load capacitance – – 15 pF
fREF External reference crystal 8 – 30 MHz
External reference clock[2], cCommercial 1–166MHz
External reference clock[2], industrial 1–150MHz
tPU Power up time for all VDD's to reach minimum specified voltage (power
ramps must be monotonic)
0.05 – 500 ms
Recommended Crystal Specifications
Parameter Description Description Min Typ. Max Unit
FNOM Nominal crystal frequency Parallel resonance, fundamental mode 8 – 30 MHz
CLNOM Nominal load capacitance 8 – 20 pF
R1Equivalent series resistance
(ESR)
Fundamental mode – – 50
DL Crystal drive level No external series resistor assumed – 0.5 2 mW
Notes
1. Unless otherwise noted, Electrical and Switching Characteristics are guaranteed across these operating conditions.
2. External input reference clock must have a duty cycle between 40% and 60%, measured at VDD/2.
3. Guaranteed by design, not 100% tested.
Electrical Characteristics
Parameter Description Conditions[1] Min Typ Max Unit
IOH Output high current[3] VOH = VDD – 0.5, VDD = 3.3 V 12 24 – mA
IOL Output low current[3] VOL = 0.5 V, VDD = 3.3 V 12 24 – mA
CXTAL_MIN Crystal load capacitance[3] Capload at minimum setting – 6 – pF
CXTAL_MAX Crystal load capacitance[3] Capload at maximum setting – 30 – pF
CIN Input pin capacitance[3] Except crystal pins – 7 – pF
VIH HIGH-level input voltage CMOS levels,% of VDD 70% – – VDD
VIL LOW-level input voltage CMOS levels,% of VDD ––30%V
DD
IIH Input HIGH current VIN = VDD – 0.3 V – <1 10 A
IIL Input LOW current VIN = +0.3 V – <1 10 A
IOZ Output leakage current Three-state outputs – – 10 A
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CY22381
CY223811
Document #: 38-07012 Rev. *I Page 6 of 11
IDD Total power supply current 3.3 V Power supply; 3 outputs at 50 MHz – 35 – mA
3.3 V Power supply; 3 outputs at 166 MHz – 70 – mA
IDDS Total power supply current in
shutdown mode
Shutdown active – 5 20 A
Switching Characteristics
Parameter Name Description Min Typ. Max Unit
1/t1Output frequency[3, 5] Clock output limit,commercial – – 200 MHz
Clock output limit, industrial – – 166 MHz
t2Output duty cycle[3, 6] Duty cycle for outputs, defined as t2t1,
Fout < 100 MHz, divider >= 2, measured
at VDD/2
45% 50% 55%
Duty cycle for outputs, defined as t2t1,
Fout > 100 MHz or divider = 1, measured
at VDD/2
40% 50% 60%
t3Rising edge slew rate[3] Output clock rise time, 20% to 80% of VDD 0.75 1.4 – V/ns
t4Falling edge slew rate[3] Output clock fall time, 20% to 80% of VDD 0.75 1.4 – V/ns
t5Output three-state timing[3] Time for output to enter or leave
three-state mode after SHUTDOWN/OE
switches
– 150 300 ns
t6Clock jitter[3, 7] Peak-to-peak period jitter, CLK outputs
measured at VDD/2
–200 – ps
t7Lock time[3] PLL Lock Time from Power up – 1.0 3 ms
Switching Waveforms
Electrical Characteristics
Parameter Description Conditions[1] Min Typ Max Unit
Notes
4. Guaranteed by design, not 100% tested.
5. Guaranteed to meet 20% – 80% output thresholds and duty cycle specifications.
6. Reference Output duty cycle depends on XTALIN duty cycle.
7. Jitter varies significantly with configuration. Reference Output jitter depends on XTALIN jitter and edge rate.
t1
OUTPUT
t2
t3t4
Figure 2. All Outputs, Duty Cycle and Rise and Fall Time
t5
OE
ALL
OUTPUTS
t5
THREE-STATE
Figure 3. Output Three-State Timing
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CY22381
CY223811
Document #: 38-07012 Rev. *I Page 8 of 11
Some product offerings are factory programmed customer specific devices with customized part numbers. The Possible Configura
tions table shows the available device types, but not complete part numbers. Contact your local Cypress FAE or Sales Representative
for more information.
Possible Configurations
Ordering Code Definitions
Ordering Information
Ordering Code Package Type Operating Range Operating Voltage
Pb-Free
CY223811FXI 8-SOIC with NiPdAu lead frame Industrial (TA=–40 °C to 85 °C) 3.3 V
CY22381FXC[10] 8-SOIC Commercial (TA=0 °C to 70 °C) 3.3 V
CY22381FXCT 8-SOIC – Tape and Reel Commercial (TA=0 °C to 70 °C) 3.3 V
CY22381FXI 8-SOIC Industrial (TA=–40 °C to 85 °C) 3.3 V
CY22381FXIT 8-SOIC – Tape and Reel Industrial (TA=–40 °C to 85 °C) 3.3 V
Programmer
CY3672-USB Programmer
CY3699 CY22381F Adapter for CY3672-USB
Ordering Code Package Type Operating Range Operating Voltage
CY22381SI-xxxT[8, 9] 8-SOIC – Tape and Reel Industrial (TA=–40°C to 85°C) 3.3 V
Pb-Free
CY22381SXC-xxx[8] 8-SOIC Commercial (TA=0 °C to 70 °C) 3.3 V
CY22381SXC-xxxT[8] 8-SOIC – Tape and Reel Commercial (TA=0 °C to 70 °C) 3.3 V
CY22381SXI-xxx[8] 8-SOIC Industrial (TA=–40 °C to 85 °C) 3.3 V
CY22381SXI-xxxT[8] 8-SOIC – Tape and Reel Industrial (TA=–40 °C to 85 °C) 3.3 V
Notes
8. The CY22381SI-xxx, CY22381SXC-xxx and CY22381SXI-xxx are factory programmed configurations. Factory programming is available for high-volume design
opportunities of 100Ku/year or more in production. For more details, contact your local Cypress FAE or Cypress Sales Representative.
9. Not recommended for new designs.
10. The CY22381FSZC and CY22381FXC are identical. For new designs, use CY22381FXC.
T = tape and reel, blank = tube
Configuration specific identifier (factory programmed)
Temperature Range: C = Commercial, I = Industrial
Package:
S = SOIC, leaded
SX = SOIC, Pb-free
X = SOIC, Pb-free
F = field programmable, blank = factory programmed
Lead finish:1 = NiPdAu, blank = unspecified
Part Identifier
Company Code: CY = Cypress Semiconductor
22381CY SX C (-xxx)
(1) (F) (T)
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CY22381
CY223811
Document #: 38-07012 Rev. *I Page 9 of 11
Package Drawing and Dimensions
Acronyms Document Conventions
Units of Measure
51-85066-*D
Figure 6. 8-Pin (150-mil) SOIC
Acronym Description
CMOS complementary metal oxide semiconductor
ESR equivalent series resistance
FET field effect transistor
MPEG motion picture experts group
OE output enable
PLL phase-locked loop
SOIC small outline integrated circuit
Symbol Unit of Measure
C degree Celcius
µA micro Amperes
mA milli Amperes
ms milli seconds
mW milli Watts
MHz Mega Hertz
Amicro Amps
F micro Farads
ns nano seconds
pF pico Farad
ps pico seconds
VVolts
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CY22381
CY223811
Document #: 38-07012 Rev. *I Page 10 of 11
Document History Page
Document Title: CY22381, CY223811 Three-PLL General Purpose Flash Programmable Clock Generator
Document Number: 38-07012
Revision ECN Orig. of
Change
Submission
Date Description of Change
** 106737 TLG 07/03/01 New data sheet
*A 108514 JWK 08/23/01 Updated based on characterization results. Removed “Preliminary” heading
Removed soldering temperature rating. Split crystal load into two typical specs
representing digital settings range. Changed t5 max to 300 ns
Changed t6 typical to 200 ps. Changed t7 typical to 1.0 ms
*B 110053 CKN 12/10/01 Changed from preliminary to final
*C 121863 RBI 12/14/02 Added power up requirements to Operating Conditions information
*D 279431 RGL See ECN Added lead-free devices
*E 2584052 AESA 10/10/08 Updated template. Added Note 8 and 9. Added part number CY22381FC,
CY22381FCT, CY3672-USB, CY3699, CY22381FSZC in ordering information
table. Removed part number CY22381FI, CY22381FIT, CY22381SC-xxx,
CY22381SC-xxxT, CY22381SI-xxx, and CY22381SI-xxxT in Ordering
Information table. Added CY223811FXI (NiPdAu lead finish). Changed
Lead-Free to Pb-Free.
*F 2620588 KVM/AESA 12/11/08 Add CY223811 to the document title
Distinguish between CY22381 and CY223811 in page 1 Features section
Add part number CY22381SI-xxxT in Ordering Information table.
*G 2897317 KVM 03/22/10 Removed obsolete parts from Ordering Information table and moved ‘xx’ parts
to Possible Configurations table
Updated package diagram
*H 3065190 KVM/BASH 01/17/11 Add crystal parameter table, ordering code definition, acronym and units tables.
Crystal Drive Level and Power. Remove FTG from CY3672.
Removed Benefits section and replaced with Functional Description section.
*I 3259420 BASH 05/17/2011 Updated as per template
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Document #: 38-07012 Rev. *I Revised May 17, 2011 Page 11 of 11
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY22381
CY223811
© Cypress Semiconductor Corporation, 2010-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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