eGaN® FET DATASHEET
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2012 | | PAGE 1
EPC2012
EPC2012 – Enhancement Mode Power Transistor
VDSS , 200 V
RDS(ON) , 100 mW
ID , 3 A
Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment leverag-
ing the infrastructure that has been developed over the last 55 years. GaN’s exceptionally high elec-
tron mobility and low temperature coecient allows very low R
DS(ON)
, while its lateral device structure
and majority carrier diode provide exceptionally low Q
G
and zero Q
RR
. The end result is a device that
can handle tasks where very high switching frequency, and low on-time are benecial as well as
those where on-state losses dominate.
EPC2012 eGaN® FETs are supplied only in
passivated die form with solder bars
Applications
• HighSpeedDC-DCconversion
• ClassDAudio
• HardSwitchedandHighFrequencyCircuits
Benets
• UltraHighEciency
• UltraLowRDS(on)
• UltralowQG
• Ultrasmallfootprint
EFFICIENT POWER CONVERSION
Maximum Ratings
VDS Drain-to-Source Voltage 200 V
ID
Continuous (TA =25˚C, θJA = 70)3
A
Pulsed (25˚C, Tpulse = 300 µs) 15
VGS
Gate-to-Source Voltage6
V
Gate-to-Source Voltage-5
TJOperating Temperature -40 to 125 ˚C
TSTG Storage Temperature -40 to 150
PARAMETER TEST CONDITIONS MINTYP MAX UNIT
Static Characteristics (T
J
= 25˚C unless otherwise stated)
BV
DSS
Drain-to-Source VoltageV
GS
= 0 V, I
D
= 60 µA 200 V
I
DSS
Drain Source LeakageV
DS
= 160 V, V
GS
= 0 V1050µA
I
GSS
Gate-Source Forward LeakageV
GS
= 5 V 0.2 1 mA
Gate-Source Reverse LeakageV
GS
= -5 V 0.1 0.5
V
GS(TH)
Gate Threshold VoltageV
DS
= V
GS
, I
D
= 1 mA 0.7 1.4 2.5 V
R
DS(ON)
Drain-Source On ResistanceV
GS
= 5 V, I
D
= 3 A70 100 mΩ
Source-Drain Characteristics (T
J
= 25˚C unless otherwise stated)
V
SD
Source-Drain Forward Voltage I
S
= 0.5 A, V
GS
= 0 V, T = 25˚C 1.9 V
I
S
= 0.5 A, V
GS
= 0 V, T = 125˚C2
Dynamic Characteristics (T
J
= 25˚C unless otherwise stated)
C
ISS
Input Capacitance
V
DS
= 100 V, V
GS
= 0 V
V
DS
= 100 V, V
GS
= 0 V
128 145
pFC
OSS
Output Capacitance 73 95
C
RSS
Reverse Transfer Capacitance 3.3 4.4
Q
G
Total Gate Charge (V
GS
= 5 V)
V
DS
= 100 V, I
D
= 3 A
1.5
nC
Q
GD
Gate to Drain Charge 0.57
Q
GS
Gate to Source Charge 0.33
Q
OSS
Output Charge11
1.8
0.75
0.41
14
Q
RR
Source-Drain Recovery Charge0
PARAMETER TEST CONDITIONS MINTYP MAX UNIT
All measurements were done with substrate shorted to source.
All measurements were done with substrate shorted to source.
NEW PRODUCT
HAL
Thermal Characteristics
R
θ
JC
Thermal Resistance, Junction to Case 7.6 ˚C/W
R
θ
JB
Thermal Resistance, Junction to Board 36 ˚C/W
R
θ
JA
Thermal Resistance, Junction to Ambient (Note 1) 85 ˚C/W
TYP
Note 1: R
θ
JA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
eGaN® FET DATASHEET
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2012 | | PAGE 2
EPC2012
ID – Drain Current (A)
VDS – Drain to Source Voltage (V)
15
10
5
00 0.5 1 1.5 2
VGS = 5
VGS = 4
VGS = 3
VGS = 2
ID – Drain Current (A)
VGS – Gate to Source Voltage (V)
15
10
5
0
00.5 1.5 12 2.5 3 3.5
44
.5
25˚C
125˚C
VD = 3 V
RDS(ON) – Drain to Source Resistance (mΩ)
VGS – Gate to Source Voltage (V)
200
150
100
50
02.5 23 3.5 4 4.5 5 5.5
ID = 3 A
ID = 6 A
ID = 10 A
ID = 15 A
RDS(ON) – Drain to Source Resistance (mΩ)
VGS – Gate to Source Voltage (V)
250
200
100
50
150
0
2 2.5 3 3.5 4 4.5 5 5.5
ID = 3 A
25˚C
125˚C
Figure 1: Typical Output Characteristics Figure 2: Transfer Characteristics
Figure 3: RDS(ON) vs. VGS for Various Drain Currents Figure 4: RDS(ON) vs. VGS for Various Temperatures
PARAMETER TEST CONDITIONS MINTYP MAX UNIT
Static Characteristics (T
J
= 25˚C unless otherwise stated)
BV
DSS
Drain-to-Source VoltageV
GS
= 0 V, I
D
= 60 µA 200 V
I
DSS
Drain Source LeakageV
DS
= 160 V, V
GS
= 0 V1050µA
I
GSS
Gate-Source Forward LeakageV
GS
= 5 V 0.2 1 mA
Gate-Source Reverse LeakageV
GS
= -5 V 0.1 0.5
V
GS(TH)
Gate Threshold VoltageV
DS
= V
GS
, I
D
= 1 mA 0.7 1.4 2.5 V
R
DS(ON)
Drain-Source On ResistanceV
GS
= 5 V, I
D
= 3 A70 100 mΩ
Source-Drain Characteristics (T
J
= 25˚C unless otherwise stated)
V
SD
Source-Drain Forward Voltage I
S
= 0.5 A, V
GS
= 0 V, T = 25˚C 1.9 V
I
S
= 0.5 A, V
GS
= 0 V, T = 125˚C2
Dynamic Characteristics (T
J
= 25˚C unless otherwise stated)
C
ISS
Input Capacitance
V
DS
= 100 V, V
GS
= 0 V
V
DS
= 100 V, V
GS
= 0 V
128 145
pFC
OSS
Output Capacitance 73 95
C
RSS
Reverse Transfer Capacitance 3.3 4.4
Q
G
Total Gate Charge (V
GS
= 5 V)
V
DS
= 100 V, I
D
= 3 A
1.5
nC
Q
GD
Gate to Drain Charge 0.57
Q
GS
Gate to Source Charge 0.33
Q
OSS
Output Charge11
1.8
0.75
0.41
14
Q
RR
Source-Drain Recovery Charge0
PARAMETER TEST CONDITIONS MINTYP MAX UNIT
All measurements were done with substrate shorted to source.
All measurements were done with substrate shorted to source.
eGaN® FET DATASHEET
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2012 | | PAGE 3
EPC2012
ISD – Source to Drain Current (A)
VSD – Source to Drain Voltage (V)
15
10
5
00 0.5 1 1.5 2 2.5 3 4 4.53.5
25˚C
125˚C
Normalized On-State Resistance – RDS(ON)
TJ – Junction Temperature ( ˚C )
1.6
1.8
1.4
1.2
1
0.8
-20 0 20 40 60 80 100 120 140
ID = 3 A
VGS = 5 V
IG – Gate Current (A)
VGS – Gate-to-Source Voltage (V)
.025
.02
.015
.01
.005
00 1 2 3 4 5 6
25˚C
125˚C
Normalized Threshold Voltage (V)
1
1.2
1.4
1.6
0.8
0.6
0.4
0.2
-20 0 20 40 60 80 100 120 140
ID = 1 mA
Figure 7: Reverse Drain-Source Characteristics Figure 8: Normalized On Resistance vs. Temperature
Figure 10: Gate CurrentFigure 9: Normalized Threshold Voltage vs. Temperature
TJ – Junction Temperature ( ˚C )
VG – Gate Voltage (V)
C – Capacitance (nF)
VDS – Drain to Source Voltage (V)
0.05
0.1
0.15
0.2
0.25
00 50 100 150 200
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
QG – Gate Charge (nC)
5
4
3
2
1
00 0.51 1.
52
ID = 3 A
VD = 100 V
Figure 5: Capacitance Figure 6: Gate Charge
All measurements were done with substrate shortened to source.
eGaN® FET DATASHEET
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2012 | | PAGE 4
EPC2012
Figure 11: Transient Thermal Response Curves
Figure 12: Safe Operating Area
Duty Factors:
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJB x RθJB + TB
PDM
t1
t2
0.5
0.2
0.1
0.05
0.02
0.01
Single Pulse
1
0.1
0.01
0.001
0.0001
10-5 10-4 10-3 10-2 10-1 110 100
Normalized Maximum Transient Thermal Impedance
tp, Rectangular Pulse Duration, seconds
Z
θJB
, Normalized Thermal Impedance
Normalized Maximum Transient Thermal Impedance
tp, Rectangular Pulse Duration, seconds
Duty Factors:
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJC x RθJC + TC
PDM
t1
t2
0.5
0.2
0.1
0.05
0.02
0.01
Single Pulse
1
0.1
0.01
0.001
ZθJC, Normalized Thermal Impedance
10-5
10-6 10-4 10-3 10-2 10-1 1
0.01
0.1
1
10
100
0.1 1 10 100 1000
ID- Drain Current (A)
VDS - Drain-Source Voltage (V)
limited by RDS(ON)
TJ = Max Rated, TC = +25°C, Single Pulse
10 µs
100 µs
1 ms
10 ms
100 ms/DC
eGaN® FET DATASHEET
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2012 | | PAGE 5
EPC2012
DIE OUTLINE
Solder Bar View
Side View
B
c
d
X2
1
34
2
d
eg g
f
x2
A
815 Max
100 +/- 20
SEATING PLANE
(685)
DIM MIN Nominal MAX
A1.681 1.711 1.741
B0.889 0.919 0.949
c0.660 0.663 0.666
d0.251 0.254 0.257
e0.230 0.245 0.260
f0.251 0.254 0.257
g0.600 0.600 0.600
MILLIMETERS
a
d e f g
c
b
EPC2012 (note 1)
Dimension (mm) target min max
a 8.00 7.90 8.30
b 1.75 1.65 1.85
c (note 2) 3.50 3.45 3.55
d 4.00 3.90 4.10
e 4.00 3.90 4.10
f (note 2) 2.00 1.95 2.05
g 1.5 1.5 1.6
TAPE AND REEL CONFIGURATION
4mm pitch, 8mm wide tape on 7” reel
Note 1: MSL1 (moisture sensitivity level 1) classied according to IPC/JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket,
not the pocket hole.
Die
orientation
dot
Gate
solder bar is
under this
corner
Die is placed into pocket
solder bar side down
(face side down)
7” reel
Loaded Tape Feed Direction
2012
YYYY
ZZZZ
Die orientation dot
Gate Pad solder bar
is under this corner
Part
Number
Laser Markings
Part #
Marking Line 1
Lot_Date Code
Marking line 2
Lot_Date Code
Marking Line 3
EPC2012 2012 YYYY ZZZZ
DIE MARKINGS
eGaN® FET DATASHEET
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2012 | | PAGE 6
EPC2012
RECOMMENDED
LAND PATTERN
(units in µm)
Pad no. 1 is Gate
Pad no. 2 is Substrate
Pad no. 3 is Drain
Padno.4isSource
The land pattern is solder mask dened
Information subject to
change without notice.
Revised October, 2012
600
409
600
919
1711
234
X2
234
643
234
1
1
34 34
2
2
600
409
600
919
1711
234
X2
234
643
234
1
1
34 34
2
2
Ecient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any productor circuit
described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Ecient Power Conversion Corporation.