LTC1864/LTC1865
1
18645fb
TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
µPower, 16-Bit, 250ksps
1- and 2-Channel
ADCs in MSOP
The LTC
®
1864/LTC1865 are 16-bit A/D converters that
are offered in MSOP and SO-8 packages and operate
on a single 5V supply. At 250ksps, the supply current is
only 850μA. The supply current drops at lower speeds
because the LTC1864/LTC1865 automatically power down
between conversions. These 16-bit switched capacitor
successive approximation ADCs include sample-and-
holds. The LTC1864 has a differential analog input with an
adjustable reference pin. The LTC1865 offers a software-
selectable 2-channel MUX and an adjustable reference pin
on the MSOP version.
The 3-wire, serial I/O, small MSOP or SO-8 package and
extremely high sample rate-to-power ratio make these
ADCs ideal choices for compact, low power, high speed
systems.
These ADCs can be used in ratiometric applications or with
external references. The high impedance analog inputs
and the ability to operate with reduced spans down to
1V full scale, allow direct connection to signal sources
in many applications, eliminating the need for external
gain stages.
Single 5V Supply, 250ksps, 16-Bit Sampling ADC
n 16-Bit 250ksps ADCs in MSOP Package
n Single 5V Supply
n
Low Supply Current: 850μA (Typ)
n
Auto Shutdown Reduces Supply Current
to 2μA at 1ksps
n
True Differential Inputs
n
1-Channel (LTC1864) or 2-Channel (LTC1865)
Versions
n
SPI/MICROWIRE™ Compatible Serial I/O
n
16-Bit Upgrade to 12-Bit LTC1286/LTC1298
n Pin Compatible with 12-Bit LTC1860/LTC1861
n Guaranteed Operation to +125°C (MSOP Package)
n High Speed Data Acquisition
n
Portable or Compact Instrumentation
n
Low Power Battery-Operated Instrumentation
n Isolated and/or Remote Data Acquisition
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
Supply Current vs Sampling Frequency
1
2
3
4
8
7
6
5
VREF
IN+
IN–
GND
VCC
SCK
SDO
CONV
LTC1864
18645 TA01
ANALOG INPUT
0V TO 5V
5V
1μF
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
SAMPLING FREQUENCY (kHz)
0.01
SUPPLY CURRENT (μA)
1000
100
10
1
0.1
0.01 100
18645 TA02
0.1 110 1000
LTC1864/LTC1865
2
18645fb
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC) .................................................7V
Ground Voltage Difference
AGND, DGND LTC1865 MSOP Package ............ ±0.3V
Analog Input ................ (GND – 0.3V) to (VCC + 0.3V)
Digital Input ................................ (GND – 0.3V) to 7V
Digital Output .............. (GND – 0.3V) to (VCC + 0.3V)
Power Dissipation .............................................. 400mW
(Notes 1, 2)
1
2
3
4
VREF
IN+
IN¯
GND
8
7
6
5
VCC
SCK
SDO
CONV
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 210°C/W
1
2
3
4
5
CONV
CH0
CH1
AGND
DGND
10
9
8
7
6
VREF
VCC
SCK
SDO
SDI
TOP VIEW
MS PACKAGE
10-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 210°C/W
1
2
3
4
8
7
6
5
TOP VIEW
S8 PACKAGE
8-LEAD PLASTIC SO
VREF
IN+
IN–
GND
VCC
SCK
SDO
CONV
TJMAX = 150°C, θJA = 175°C/W
1
2
3
4
8
7
6
5
TOP VIEW
S8 PACKAGE
8-LEAD PLASTIC SO
CONV
CH0
CH1
GND
VCC
SCK
SDO
SDI
TJMAX = 150°C, θJA = 175°C/W
PIN CONFIGURATION
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC1864CMS8#PBF LTC1864CMS8#TRPBF LTHQ 8-Lead Plastic MSOP 0°C to 70°C
LTC1864IMS8#PBF LTC1864IMS8#TRPBF LTHQ 8-Lead Plastic MSOP –40°C to 85°C
LTC1864HMS8#PBF LTC1864HMS8#TRPBF LTHQ 8-Lead Plastic MSOP –40°C to 125°C
LTC1864ACMS8#PBF LTC1864ACMS8#TRPBF LTHQ 8-Lead Plastic MSOP 0°C to 70°C
LTC1864AIMS8#PBF LTC1864AIMS8#TRPBF LTHQ 8-Lead Plastic MSOP –40°C to 85°C
LTC1864AHMS8#PBF LTC1864AHMS8#TRPBF LTHQ 8-Lead Plastic MSOP –40°C to 125°C
LTC1864CS8#PBF LTC1864CS8#TRPBF 1864 8-Lead Plastic SO 0°C to 70°C
LTC1864IS8#PBF LTC1864IS8#TRPBF 1864I 8-Lead Plastic SO –40°C to 85°C
LTC1864ACS8#PBF LTC1864ACS8#TRPBF 1864A 8-Lead Plastic SO 0°C to 70°C
LTC1684AIS8#PBF LTC1684AIS8#TRPBF 1864AI 8-Lead Plastic SO –40°C to 85°C
LTC1865CMS#PBF LTC1865CMS#TRPBF LTHS 10-Lead Plastic MSOP 0°C to 70°C
LTC1865IMS#PBF LTC1865IMS#TRPBF LTHS 10-Lead Plastic MSOP –40°C to 85°C
Operating Temperature Range
LTC1864C/LTC1865C/
LTC1864AC/LTC1865AC ...........................0°C to 70°C
LTC1864I/LTC1865I/
LTC1864AI/LTC1865AI ...................... –40°C to 85°C
LTC1864H/LTC1865H
LTC1864AH/LTC1865AH ................. –40°C to 125°C
Storage Temperature Range ...................–65°C to 150°C
Lead Temperature (Soldering, 10 sec) ..................300°C
LTC1864 LTC1865
LTC1864 LTC1865
LTC1864/LTC1865
3
18645fb
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC1865HMS#PBF LTC1865HMS#TRPBF LTHS 10-Lead Plastic MSOP –40°C to 125°C
LTC1865ACMS#PBF LTC1865ACMS#TRPBF LTHS 10-Lead Plastic MSOP 0°C to 70°C
LTC1865AIMS#PBF LTC1865AIMS#TRPBF LTHS 10-Lead Plastic MSOP –40°C to 85°C
LTC1865AHMS#PBF LTC1865AHMS#TRPBF LTHS 10-Lead Plastic MSOP –40°C to 125°C
LTC1865CS8#PBF LTC1865CS8#TRPBF 1865 8-Lead Plastic SO 0°C to 70°C
LTC1865IS8#PBF LTC1865IS8#TRPBF 1865I 8-Lead Plastic SO –40°C to 85°C
LTC1865ACS8#PBF LTC1865ACS8#TRPBF 1865A 8-Lead Plastic SO 0°C to 70°C
LTC1865AIS8#PBF LTC1865AIS8#TRPBF 1865AI 8-Lead Plastic SO –40°C to 85°C
LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC1864CMS8 LTC1864CMS8#TR LTHQ 8-Lead Plastic MSOP 0°C to 70°C
LTC1864IMS8 LTC1864IMS8#TR LTHQ 8-Lead Plastic MSOP –40°C to 85°C
LTC1864HMS8 LTC1864HMS8#TR LTHQ 8-Lead Plastic MSOP –40°C to 125°C
LTC1864ACMS8 LTC1864ACMS8#TR LTHQ 8-Lead Plastic MSOP 0°C to 70°C
LTC1864AIMS8 LTC1864AIMS8#TR LTHQ 8-Lead Plastic MSOP –40°C to 85°C
LTC1864AHMS8 LTC1864AHMS8#TR LTHQ 8-Lead Plastic MSOP –40°C to 125°C
LTC1864CS8 LTC1864CS8#TR 1864 8-Lead Plastic SO 0°C to 70°C
LTC1864IS8 LTC1864IS8#TR 1864I 8-Lead Plastic SO –40°C to 85°C
LTC1864ACS8 LTC1864ACS8#TR 1864A 8-Lead Plastic SO 0°C to 70°C
LTC1684AIS8 LTC1684AIS8#TR 1864AI 8-Lead Plastic SO –40°C to 85°C
LTC1865CMS LTC1865CMS#TR LTHS 10-Lead Plastic MSOP 0°C to 70°C
LTC1865IMS LTC1865IMS#TR LTHS 10-Lead Plastic MSOP –40°C to 85°C
LTC1865HMS LTC1865HMS#TR LTHS 10-Lead Plastic MSOP –40°C to 125°C
LTC1865ACMS LTC1865ACMS#TR LTHS 10-Lead Plastic MSOP 0°C to 70°C
LTC1865AIMS LTC1865AIMS#TR LTHS 10-Lead Plastic MSOP –40°C to 85°C
LTC1865AHMS LTC1865AHMS#TR LTHS 10-Lead Plastic MSOP –40°C to 125°C
LTC1865CS8 LTC1865CS8#TR 1865 8-Lead Plastic SO 0°C to 70°C
LTC1865IS8 LTC1865IS8#TR 1865I 8-Lead Plastic SO –40°C to 85°C
LTC1865ACS8 LTC1865ACS8#TR 1865A 8-Lead Plastic SO 0°C to 70°C
LTC1865AIS8 LTC1865AIS8#TR 1865AI 8-Lead Plastic SO –40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
LTC1864/LTC1865
4
18645fb
CONVERTER AND MULTIPILEXER CHARACTERISTICS
LTC1864/LTC1865
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SNR Signal-to-Noise Ratio 87 dB
S/(N + D) Signal-to-Noise Plus Distortion Ratio 10kHz Input Signal
100kHz Input Signal
83
76
dB
dB
THD Total Harmonic Distortion Up to 5th Harmonic 10kHz Input Signal
100kHz Input Signal
88
77
dB
dB
Full Power Bandwidth 20 MHz
Full Linear Bandwidth S/(N+D) ≥ 75dB 125 kHz
The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C.
VCC = 5V, VREF = 5V, fSCK = fSCK(MAX) as defi ned in Recommended Operating Conditions, unless otherwise noted.
PARAMETER CONDITIONS
LTC1864/LTC1865 LTC1864A/LTC1865A
UNITSMIN TYP MAX MIN TYP MAX
Resolution l16 16 Bits
No Missing Codes Resolution l14 15 Bits
INL (Note 3)
H-Grade (Note 3)
l
l
±8
±8.5
±6
±6.5
LSB
LSB
Transition Noise 1.1 1.1 LSBRMS
Gain Error l±20 ±20 mV
Offset Error LTC1864 SO-8 and MSOP, LTC1865 MSOP
LTC1865 SO-8
l
l
±2
±3
±5
±7
±2
±3
±5
±7
mV
mV
Input Differential Voltage Range VIN = IN+ – IN–l0V
REF 0V
REF V
Absolute Input Range IN+ Input
IN– Input
–0.05
–0.05
VCC + 0.05
VCC/2
–0.05
–0.05
VCC + 0.05
VCC/2
V
V
VREF Input Range LTC1864 SO-8 and MSOP,
LTC1865 MSOP
1V
CC 1V
CC V
Analog Input Leakage Current (Note 4) l±1 ±1 μA
CIN Input Capacitance In Sample Mode
During Conversion
12
5
12
5
pF
pF
DYNAMIC ACCURACY
TA = 25°C. VCC = 5V, VREF = 5V, fSAMPLE = 250kHz, unless otherwise noted.
LTC1864/LTC1865
5
18645fb
LTC1864/LTC1865
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage VCC = 5.25V l2.4 V
VIL Low Level Input Voltage VCC = 4.75V l0.8 V
IIH High Level Input Current VIN = VCC l2.5 μA
IIL Low Level Input Current VIN = 0V l–2.5 μA
VOH High Level Output Voltage VCC = 4.75V, IO = 10μA
VCC = 4.75V, IO = 360μA
l
l
4.5
2.4
4.74
4.72
V
V
VOL Low Level Output Voltage VCC = 4.75V, IO = 1.6mA ●0.4 V
IOZ Hi-Z Output Leakage CONV = VCC ●±3 μA
ISOURCE Output Source Current VOUT = 0V –25 mA
ISINK Output Sink Current VOUT = VCC 20 mA
IREF Reference Current (LTC1864 SO-8 and MSOP,
LTC1865 MSOP)
CONV = VCC
fSMPL = fSMPL(MAX)
●
●
0.001
0.05
3
0.1
μA
mA
ICC Supply Current CONV = VCC After Conversion
CONV = VCC After Conversion, H-Grade
fSMPL = fSMPL(MAX)
●
●
●
0.001
0.001
0.85
3
5
1.3
μA
μA
mA
PDPower Dissipation fSMPL = fSMPL(MAX) 4.25 mW
DIGITAL AND DC ELECTRICAL CHARACTERISTICS
The ● denotes specifi cations which apply
over the full operating temperature range, otherwise specifi cations are TA = 25°C. VCC = 5V, VREF = 5V, unless otherwise noted.
LTC1864/LTC1865
6
18645fb
RECOMMENDED OPERATING CONDITIONS
The ● denotes specifi cations which apply over the
full operating temperature range, otherwise specifi cations are TA = 25°C.
LTC1864/LTC1865
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC Supply Voltage 4.75 5.25 V
fSCK Clock Frequency
H-Grade
●
●
20
16.7
MHz
MHz
tCYC Total Cycle Time 16 • SCK + tCONV μs
tSMPL Analog Input Sampling Time LTC1864 (Note 5)
LTC1865 (Note 5)
16
14
SCK
SCK
tsuCONV Setup Time CONV↓ Before First SCK↑
(See Figure 1) H-Grade
60
65
30
30
ns
ns
thDI Hold Time SDI After SCK↑LTC1865 15 ns
tsuDI Setup Time SSDI Stable Before SCK↑LTC1865 15 ns
tWHCLK SCK High Time fSCK = fSCK(MAX) 40% 1/fSCK
tWLCLK SCK Low Time fSCK = fSCK(MAX) 40% 1/fSCK
tWHCONV CONV High Time Between Data Transfer
Cycles
(Note 5) tCONV μs
tWLCONV CONV Low Time During Data Transfer (Note 5) 16 SCK
thCONV Hold Time CONV Low After Last SCK↑13 ns
LTC1864/LTC1865
7
18645fb
TIMING CHARACTERISTICS
The ● denotes specifi cations which apply over the full operating temperature
range, otherwise specifi cations are TA = 25°C. VCC = 5V, VREF = 5V, fSCK = fSCK(MAX) as defi ned in Recommended Operating Conditions,
unless otherwise noted.
LTC1864/LTC1865
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tCONV Conversion Time (See Figure 1)
H-Grade
●
●
2.75
2.75
3.2
3.3
μs
μs
fSMPL(MAX) Maximum Sampling Frequency
H-Grade
●
●
250
234
kHz
kHz
tdDO Delay Time, SCK↓ to SDO Data Valid CLOAD = 20pF
CLOAD = 20pF
CLOAD = 20pF, H-Grade
●
●
15 20
25
30
ns
ns
ns
tdis Delay Time, CONV↑ to SDO Hi-Z
H-Grade
●
●
30
30
60
65
ns
ns
ten Delay Time, CONV↓ to SDO Enabled CLOAD = 20pF
CLOAD = 20pF, H-Grade
●
●
30
30
60
65
ns
ns
thDO Time Output Data Remains Valid After SCK↓CLOAD = 20pF ●510 ns
trSDO Rise Time CLOAD = 20pF 8 ns
tfSDO Fall Time CLOAD = 20pF 4 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: Integral nonlinearity is defi ned as deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 4: Channel leakage current is measured while the part is in sample
mode.
Note 5: Guaranteed by design, not subject to test.
LTC1864/LTC1865
8
18645fb
TYPICAL PERFORMANCE CHARACTERISTICS
Reference Current vs
Sampling Rate
Reference Current vs
Temperature
Reference Current vs
Reference Voltage
Typical INL Curve Typical DNL Curve
Analog Input Leakage Current vs
Temperature
Supply Current vs Sampling
Frequency Supply Current vs Temperature Sleep Current vs Temperature
SAMPLING FREQUENCY (kHz)
0.01
SUPPLY CURRENT (μA)
1000
100
10
1
0.1
0.01 100
18645 G01
0.1 1.0 10 1000
VCC = 5V
TA = 25°C
CONV LOW = 800ns
TEMPERATURE (°C)
–50
SUPPLY CURRENT (μA)
1000
800
600
400
200
0050 75
18645 G02
–25 25 100 125
VCC = 5V
VREF = 5V
fSAMPLE = 250kHz
CONV HIGH = 3.2μS
TEMPERATURE (°C)
–50
SLEEP CURRENT (nA)
1000
900
800
700
600
500
400
300
200
100
0050 75
18645 G03
–25 25 100 125
CONV = VCC = 5V
SAMPLE RATE (kHz)
0
REFERENCE CURRENT (μA)
60
50
40
30
20
10
050 100 150 200
18645 G04
250
VCC = 5V
TA = 25°C
VREF = 5V
CONV LOW = 800ns
TEMPERATURE (°C)
–50
REFERENCE CURRENT (μA)
55
54
53
52
51
50
49
48
47
46
45 050 75
18645 G05
–25 25 100 125
VCC = 5V
VREF = 5V
fS = 250kHz
VREF (V)
0
REFERENCE CURRENT (μA)
60
50
40
30
20
10
01234
18645 G06
5
VCC = 5V
TA = 25°C
fS = 250kHz
CODE
0
INL ERROR (LSBs)
65536
18645 G07
32768
4
2
0
–2
–4 16384 49152
VCC = 5V
TA = 25°C
VREF = 5V
CODE
0 65536
18645 G08
3276816384 49152
DNL ERROR (LSBs)
2
1
0
–1
–2
VCC = 5V
TA = 25°C
VREF = 5V
TEMPERATURE (°C)
–50
ANALOG INPUT LEAKAGE (nA)
100
18645 G09
050
100
75
50
25
0–25 25 75 125
VCC = 5V
VREF = 5V
CONV = 0V
LTC1864/LTC1865
9
18645fb
TYPICAL PERFORMANCE CHARACTERISTICS
Change in Gain Error vs
Temperature
Histogram of 4096 Conversions of
a DC Input Voltage 4096 Point FFT Nonaveraged
SINAD vs Frequency THD vs Frequency SFDR vs Frequency
Change in Offset Error vs
Reference Voltage Change in Offset vs Temperature
Change in Gain Error vs
Reference Voltage
REFERENCE VOLTAGE (V)
0
CHANGE IN OFFSET ERROR (LSB)
75
50
25
0
–25 4
18645 G10
1235
VCC = 5V
TA = 25°C
TEMPERATURE (°C)
–50
CHANGE IN OFFSET (LSB)
5
4
3
2
1
0
–1
–2
–3
–4
–5 050 75
18645 G11
–25 25 100 125
VCC = 5V
VREF = 5V
REFERENCE VOLTAGE(V)
0
CHANGE IN GAIN ERROR (LSB)
20
15
10
5
0
–5
–10
–15
–20 245
18645 G12
13
VCC = 5V
TA = 25°C
TEMPERATURE (°C)
–50
CHANGE IN GAIN ERROR (LSB)
5
4
3
2
1
0
–1
–2
–3
–4
–5 050 75
18645 G13
–25 25 100 125
VCC = 5V
VREF = 5V
FREQUENCY
1800
1600
1400
1200
1000
800
600
400
200
0
CODE
18645 G14
–4 –3 –2 –1 012345
00 1200
1534
127
516
1178
729
VCC = 5V
TA = 25°C
VREF = 5V
FREQUENCY (kHz)
AMPLITUDE (dB)
0
–20
–40
–60
–80
–100
–120
–140
18645 G15
020 40 60 80 100 120
fS = 203.125kHz
fIN = 99.72763kHz
VCC = 5V
VREF = 5V
TA = 25°C
FIN (kHz)
1
SINAD (dB)
100
90
80
70
60
50
40
30
20
10
010 100 1000
18645 G16
VCC = 5V
VREF = 5V
TA = 25°C
VIN = 0dB
SNR
SINAD
FIN (kHz)
1
THD (dB)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100 10 100 1000
18645 G17
VCC = 5V
VREF = 5V
TA = 25°C
VIN = 0dB
FIN (kHz)
1
SFDR (dB)
100
90
80
70
60
50
40
30
20
10
010 100 1000
18645 G18
VCC = 5V
VREF = 5V
TA = 25°C
VIN = 0dB
LTC1864/LTC1865
10
18645fb
PIN FUNCTIONS
VREF (Pin 1): Reference Input. The reference input defi nes
the span of the A/D converter and must be kept free of
noise with respect to GND.
IN+, IN– (Pins 2, 3): Analog Inputs. These inputs must
be free of noise with respect to GND.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
CONV (Pin 5): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is
left high after the A/D conversion is fi nished, the part
powers down. A logic low on this input enables the SDO
pin, allowing the data to be shifted out.
SDO (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this pin.
SCK (Pin 7): Shift Clock Input. This clock synchronizes
the serial data transfer.
VCC (Pin 8):
Positive Supply. This supply must be kept
free of noise and ripple by bypassing directly to the
analog ground plane.
CONV (Pin 1): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is
left high after the A/D conversion is fi nished, the part
powers down. A logic low on this input enables the SDO
pin, allowing the data to be shifted out.
CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must
be free of noise with respect to AGND.
AGND (Pin 4): Analog Ground. AGND should be tied directly
to an analog ground plane.
DGND (Pin 5): Digital Ground. DGND should be tied directly
to an analog ground plane.
SDI (Pin 6):
Digital Data Input. The A/D confi guration
word is shifted into this input.
SDO (Pin 7): Digital Data Output. The A/D conversion
result is shifted out of this output.
SCK (Pin 8): Shift Clock Input. This clock synchronizes
the serial data transfer.
VCC (Pin 9):
Positive Supply. This supply must be kept
free of noise and ripple by bypassing directly to the
analog ground plane.
VREF (Pin 10): Reference Input. The reference input defi nes
the span of the A/D converter and must be kept free of
noise with respect to AGND.
LTC1864
LTC1865 (MSOP Package)
LTC1865 (SO-8 Package)
CONV (Pin 1): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is
left high after the A/D conversion is fi nished, the part
powers down. A logic low on this input enables the SDO
pin, allowing the data to be shifted out.
CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must
be free of noise with respect to GND.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
SDI (Pin 5):
Digital Data Input. The A/D confi guration
word is shifted into this input.
SDO (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
SCK (Pin 7): Shift Clock Input. This clock synchronizes
the serial data transfer.
VCC (Pin 8):
Positive Supply. This supply must be kept
free of noise and ripple by bypassing directly to the analog
ground plane. VREF is tied internally to this pin.
LTC1864/LTC1865
11
18645fb
FUNCTIONAL BLOCK DIAGRAM
18645 BD
16-BIT
SAMPLING
ADC
BIAS AND
SHUTDOWN
CONVERT
CLK
SERIAL
PORT
16 BITS
IN+
(CH0)
IN–
(CH1)
VCC
VREF
SDO
GND
CONV (SDI) SCK
PIN NAMES IN
PARENTHESES
REFER TO LTC1865
DATA OUT
DATA IN
+
–
LTC1864/LTC1865
12
18645fb
Load Circuit for tdDO, tr, tf, tdis and ten Voltage Waveforms for SDO Rise and Fall Times, tr, tf
Voltage Waveforms for ten Voltage Waveforms for tdis
Voltage Waveforms for SDO Delay Times,tdDO and thDO
SDO 3k
20pF
TEST POINT
VCC tdis WAVEFORM 2, ten
tdis WAVEFORM 1
18645 TC01
18645 TC03
CONV
SDO
ten
SCK
SDO
VIL
tdDO
thDO
VOH
VOL
18645 TC02
SDO
trtf18645 TC04
VOH
VOL
SDO
WAVEFORM 1
(SEE NOTE 1)
VIH
tdis
90%
10%
SDO
WAVEFORM 2
(SEE NOTE 2)
CONV
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL
18645 TC05
TEST CIRCUITS
LTC1864/LTC1865
13
18645fb
LTC1864 OPERATION
Operating Sequence
The LTC1864 conversion cycle begins with the rising edge
of CONV. After a period equal to tCONV
, the conversion is
fi nished. If CONV is left high after this time, the LTC1864
goes into sleep mode drawing only leakage current. On the
falling edge of CONV, the LTC1864 goes into sample mode
and SDO is enabled. SCK synchronizes the data transfer
with each bit being transmitted from SDO on the falling
SCK edge. The receiving system should capture the data
from SDO on the rising edge of SCK. After completing the
data transfer, if further SCK clocks are applied with CONV
low, SDO will output zeros indefi nitely. See Figure 1.
Analog Inputs
The LTC1864 has a unipolar differential analog input. The
converter will measure the voltage between the “IN+”
and “IN–” inputs. A zero code will occur when IN+ minus
IN– equals zero. Full scale occurs when IN+ minus IN–
equals VREF minus 1LSB. See Figure 2. Both the “IN+” and
“IN–” inputs are sampled at the same time, so common
mode noise on the inputs is rejected by the ADC. If “IN–”
is grounded and VREF is tied to VCC, a rail-to-rail input
span will result on “IN+” as shown in Figure 3.
Reference Input
The voltage on the reference input of the LTC1864 defi nes
the full-scale range of the A/D converter. The LTC1864 can
operate with reference voltages from VCC to 1V.
APPLICATIONS INFORMATION
Figure 1. LTC1864 Operating Sequence
Figure 2. LTC1864 Transfer Curve Figure 3. LTC1864 with Rail-to-Rail Input Span
CONV
tCONV
SCK
SDO
16151413121110987654321
B15 B14 B12 B10 B8 B6 B4 B2 B0* Hi-Z
18645 F01
Hi-Z B13 B11 B9 B7 B5 B3 B1
SLEEP MODE tSMPL
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE
APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
tsuCONV
0V
1LSB
VREF – 2LSB
VREF – 1LSB
VREF
VIN*
*VIN = IN+ – IN–
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
•
•
•
18645 F02
1
2
3
4
8
7
6
5
VREF
IN+
IN–
GND
VCC
SCK
SDO
CONV
LTC1864
18645 F03
VIN = 0V TO VCC
VCC
1μF
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
LTC1864/LTC1865
14
18645fb
APPLICATIONS INFORMATION
LTC1865 OPERATION
Operating Sequence
The LTC1865 conversion cycle begins with the rising edge
of CONV. After a period equal to tCONV
, the conversion is
fi nished. If CONV is left high after this time, the LTC1865
goes into sleep mode drawing only leakage current. The
LTC1865’s 2-bit data word is clocked into the SDI input
on the rising edge of SCK after CONV goes low. Additional
inputs on the SDI pin are then ignored until the next CONV
cycle. The shift clock (SCK) synchronizes the data transfer
with each bit being transmitted on the falling SCK edge and
captured on the rising SCK edge in both transmitting and
receiving systems. The data is transmitted and received
simultaneously (full duplex). After completing the data
transfer, if further SCK clocks are applied with CONV low,
SDO will output zeros indefi nitely. See Figure 4.
Analog Inputs
The two bits of the input word (SDI) assign the MUX
confi guration for the next requested conversion. For a
given channel selection, the converter will measure the
voltage between the two channels indicated by the “+”
and “–” signs in the selected row of the following table. In
single-ended mode, all input channels are measured
with respect to GND. A zero code will occur when the
“+” input minus the “–” input equals zero. Full scale oc-
curs when the “+” input minus the “–” input equals VREF
minus 1LSB. See Figure 5. Both the “+” and “–” inputs
are sampled at the same time so common mode noise
is rejected. The input span in the SO-8 package is fi xed
at VREF = VCC. If the “–” input in differential mode is
grounded, a rail-to-rail input span will result on the “+”
input.
Reference Input
The reference input of the LTC1865 SO-8 package is
internally tied to VCC. The span of the A/D converter is
therefore equal to VCC. The voltage on the reference
input of the LTC1865 MSOP package defi nes the span
of the A/D converter. The LTC1865 MSOP package can
operate with reference voltages from 1V to VCC.
Figure 4. LTC1865 Operating Sequence
MUX ADDRESS
Table 1. Multiplexer Channel Selection
SGL/DIFF
1
1
0
0
ODD/SIGN
0
1
0
1
CHANNEL #
0
+
+
–
1
+
–
+
GND
–
–
18645 TBL1
SINGLE-ENDED
MUX MODE
DIFFERENTIAL
MUX MODE
CONV
SDI
SCK
16151413121110987654321
SDO B15 B14 B12 B10 B8 B6 B4 B2 B0* Hi-Z
B13 B11 B9 B7 B5 B3 B1
S/D O/S DON’T CAREDON’T CARE
tCONV
18645 F04
SLEEP MODE
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE
APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
Hi-Z
tSMPL
LTC1864/LTC1865
15
18645fb
APPLICATIONS INFORMATION
GENERAL ANALOG CONSIDERATIONS
Grounding
The LTC1864/LTC1865 should be used with an analog
ground plane and single point grounding techniques. Do not
use wire wrapping techniques to breadboard and evaluate
the device. To achieve the optimum performance, use a
printed circuit board. The ground pins (AGND and DGND
for the LTC1865 MSOP package and GND for the LTC1864
and LTC1865 SO-8 package) should be tied directly to the
analog ground plane with minimum lead length.
Bypassing
For good performance, the VCC and VREF pins must be free
of noise and ripple. Any changes in the VCC/VREF voltage
with respect to ground during the conversion cycle can
induce errors or noise in the output code. Bypass the VCC
and VREF pins directly to the analog ground plane with
a minimum of 1μF tantalum. Keep the bypass capacitor
leads as short as possible.
Analog Inputs
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1864/LTC1865
have capacitive switching input current spikes. These cur-
rent spikes settle quickly and do not cause a problem if
source resistances are less than 200Ω or high speed op
amps are used (e.g., the LT
®
1211, LT1469, LT1807, LT1810,
LT1630, LT1226 or LT1215). But if large source resistances
are used, or if slow settling op amps drive the inputs, take
care to ensure the transients caused by the current spikes
settle completely before the conversion begins.
Figure 5. LTC1865 Transfer Curve
0V
1LSB
VCC – 2LSB
VCC – 1LSB
VCC
VIN*
*VIN = (SELECTED “+” CHANNEL) –
(SELECTED “–” CHANNEL)
REFER TO TABLE 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
•
•
•
18645 F05
LTC1864/LTC1865
16
18645fb
APPLICATIONS INFORMATION
LTC1864 Evaluation Circuit Schematic
U12B
74AC109
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
–
+
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
JP8
246
135
JP9
246
135
2
3
4
1
5
6
7
8
10
9
8
5VDIG
5VDIG
5VDIG
5VDIG
5VDIG
15V
–15V
5VDIG
5VDIG
5VAN
5VDIG
5VDIG
5VDIG
C16
0.1μF
C23
0.1μF
C5
0.1μF
C6
0.1μF
C24
0.1μF
C18
0.1μF
C17
0.1μF
5VDIG
5VDIG 5VDIG
C13
0.1μF
C26
10μF
6.3V
1206
C14
0.1μF
U12A
74AC109
U10
LTC1799
RESET
CLK
P0
P1
P2
P3
ENP
GND
VCC
RCO
Q0
Q1
Q2
Q3
ENT
LO
U6
74HC163AD
J
K
CLK
CLR
PRE
Q
Q
GND
VCC
1
2
3
5
4
V+
GND
SET DIV
14
13
12
15
11
J
K
CLK
CLR
PRE
Q
Q
GND
VCC
16 16
U9B
74AC00
U9A
74AC00
U13B
74AC32
RESET
CLK
P0
P1
P2
P3
ENP
GND
VCC
RCO
Q0
Q1
Q2
Q3
ENT
LO
U7
74HC163AD
R10
20k
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
J4
3201S40G1
QB
QC
QD
QE
QF
QG
QH
GND
VCC
QA
A
OENB
LCLK
SCLK
RESET
SQH
RN1
330
QB
QC
QD
QE
QF
QG
QH
GND
VCC
QA
A
OENB
LCLK
SCLK
RESET
SQH
R7
51Ω
0PT
R9
51Ω
R8
51Ω
0PT
C9
180pF
C10
680pF
OPT
C8
1000pF
OPT
C12
1000pF
OPT
C7
390pF
C11
390pF
C27
0.1μF
C1
0.1μF
C4
0.1μF
C21
47pF
C22
47pF
C25
0.1μF
5VDIG C15
0.1μF
5VDIG
C19
0.1μF
C2
1μF
10V
0805
C3
10μF
6.3V
1206
JP3
JP2
JP1
R1
510Ω
R3
2Ω
R2
510Ω
VIN VOUT
GND U1
LT1021-5
VIN VOUT
GND
R4
2Ω
15V
15V
IN+IN+
AGND
IN–IN–
VREF
IN+
IN–
GND
VCC
SCK
SDO
CONV
U8A
74AC14
U8B
74AC14
U8E
74AC14
U8D
74AC14 U8F
74AC14
OUT
15V 5VAN
U4
74HC595ADT
U5
74HC595ADT
U9C
74AC00
U9D
74AC00
U13A
74AC32
U13D
74AC32
U13C
74AC32
ANALOG GROUND PLANE
CLK
JP6
JP7
JP4
J1
J2
E1
E8
E9
U2
OPT
U3
LTC1864CMS8
1
2
3
4
8
7
6
5
R6
402Ω
1%
R5
402Ω, 1%
1
2
3
4
8
7
6
5
2
21
21
2
1
2
1
21
3
3
2
1
21
4
61
2
3
JP5
CONV
DGND
DGND
DOUT
CLKOUT
CLKIN
ENABLE
DATA
U8C
74AC14
E2
E3
E7
E6
E4
E5
J3
NOTES: UNLESS OTHERWISE SPECIFIED
INSTALL SHUNTS ON JP1, JP3-JP7 PIN 1 AND PIN2;
ON JP8 AND JP9 PIN 2 AND PIN 4, PIN 3 AND PIN 5.
18645 AI1
R12
10k
LTC1864/LTC1865
17
18645fb
APPLICATIONS INFORMATION
Component Side Silk Screen for LTC1864 Evaluation Circuit
Component Side Showing Traces
(Note Sider Traces on Analog Side)
Bottom Side Showing Traces
(Note Almost No Analog Traces on Board Bottom)
Ground Layer with Separate Analog and Digital Grounds Supply Layer with 5V Digital Supply and
Analog Ground Repeated
LTC1864/LTC1865
18
18645fb
APPLICATIONS INFORMATION
Figure 6. LTC1864 Manchester Transmitter
U12B
74AC109
U11
LT1121CST-5
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
2
3
4
1
5
6
7
8
10
9
8
5VDIG
5VDIG
5VDIG
5VDIG 5VDIG
5VAN
5VDIG
5VDIG
C16
0.1μF
C23
0.1μF
C24
0.1μF
C18
0.1μF
C17
0.1μF
5VDIG
C26
10μF
6.3V
1206
U12A
74AC109
U10
LTC1799
RESET
CLK
P0
P1
P2
P3
ENP
GND
VCC
RCO
Q0
Q1
Q2
Q3
ENT
LO
U6
74HC163AD
J
K
CLK
CLR
PRE
Q
Q
GND
VCC
1
2
3
5
4
V+
GND
SET DIV
14
13
12
15
11
J
K
CLK
CLR
PRE
Q
Q
GND
VCC
16 16
U9B
74AC00
U9A
74AC00
U13B
74AC32
RESET
CLK
P0
P1
P2
P3
ENP
GND
VCC
RCO
Q0
Q1
Q2
Q3
ENT
LO
U7
74HC163AD
100k
RN1
330
C4
0.1μF
C3
10μF
6.3V
1206
VIN VOUT
GND
R4
2Ω
VREF
IN+
IN–
GND
VCC
SCK
SDO
CONV
OUT
15V
15V
5VAN
U13C
74AC32
ANALOG GROUND PLANE
CLK
U3
LTC1864CMS8
1
2
3
4
8
7
6
5
1
2
3
4
PRE
D
CLK
CLR
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
18645 AI2
RO
RE
DE
DI
VCC
B
A
GND
1V to 5V REFERENCE
0V to VREF INPUT
Q
v
v
v
Q
PRE
D
CLK
CLR
Q
v
Q
5VDIG
5VDIG 5VDIG
5VDIG
5V
1
5
2
3
4
500Ω
MC74VHC1G66
120Ω
4 CONDUCTOR
TELEPHONE WIRES
TO RECEIVER
LTC1485
74AC74
74AC74
74AC86
LTC1864/LTC1865
19
18645fb
APPLICATIONS INFORMATION
Figure 7. LTC1864 Manchester Receiver
1
2
3
4
8
7
6
5
4
2
3
1
10
12
11
13
5
6
4
2
3
1
5
6
4
2
3
1
5
6
9
8
10
12
11
13
9
8
18645 AI3
RO
RE
DE
DI
VCC
B
A
GND
PRE
D
CLK
CLR
Q
v
Q
4 CONDUCTOR
TELEPHONE WIRES
TO TRANSMITTER
U1
LTC1485
PRE
D
CLK
CLR
Q
v
Q
IC1A
74AC74
VCC
PRE
D
CLK
CLR
Q
v
Q
IC1B
74AC74
IC3B
74AC74
VCC
VCC
VCC
VCC
VCC
VCC
VCC
CLK
CLK
DATA
DATA
PRE
D
CLK
CLR
Q
v
Q
IC2A
74AC74
CLK
PRE
D
CLK
CLR
Q
v
Q
IC2B
74AC74 IC4B
74AC08
CLK
PRE
D
CLK
CLR
Q
v
Q
IC3A
74AC74
CLK
DATA IN
15V SUPPLY TO
TRANSMITTER
RECEIVE CLOCK AT
8 X TRANSMIT
CLOCK FREQUENCY SER
SCK
SCL
RCK
8
15
1
2
3
4
5
6
7
9
QA
QB
QC
QD
QE
QF
QG
QH
QHIN
D15
D14
D13
D12
D11
D10
D9
D8
14
11
10
12
13
STROBE
STROBE
v
IC8
74AC595
VCC
SER
SCK
SCL
RCK
8
15
1
2
3
4
5
6
7
9
QA
QB
QC
QD
QE
QF
QG
QH
QHIN
D7
D6
D5
D4
D3
D2
D1
D0
14
11
10
12
13
v
IC9
74AC595
10
12
11
13
9
8
CLK
PRE
J
CLK
K
CLR
Q
v
Q
IC7B
74AC109
11
14
12
13
15
10
9
DATA
OPTIONAL SERIAL TO
PARALLEL CONVERTER
R1
120Ω
IC5C
74AC86
IC4D
74AC08 IC4C
74AC08
IC6D
74AC32
IC6C
74LS32D
IC4A
74AC08
LTC1864/LTC1865
20
18645fb
APPLICATIONS INFORMATION
Transmit LTC1864 Data Over Modular Telephone Wire
Using Simple Transmitter/Receiver
Figure 6 shows a simple Manchester encoder and dif-
ferential transmitter suitable for use with the LTC1864.
This circuit allows transmission of data over inexpensive
telephone wire. This is useful for measuring a remote
sensor, particularly when the cost of preserving the analog
signal over a long distance is high.
Manchester encoding is a clock signal that is modulated
by exclusive ORing with the data signal. The resulting
signal contains both clock and data information and has
an average duty cycle of 50%, that also allows transformer
coupling. In practice, generating a Manchester encoded
signal with an XOR gate will often produce glitches due
to the skew between data and clock transitions. The D
fl ip-fl ops in this encoder retime the clock and data such
that the respective edges are closely aligned, effectively
suppressing glitches. The retimed data and clock are then
XORed to produce the Manchester encoded data, which
is interfaced to telephone wire with an LTC1485 RS485
transceiver.
In order to synchronize to incoming data, the receiver
needs a sequence to indicate the start of a data word. The
transmitter schematic shows logic that will produce 31
zeros, a start bit, followed by the 16 data bits (one sample
every 48 clock cycles) at a clock frequency of 1MHz set by
the LTC1799 oscillator. Sending at least 18 zeros before
each start bit ensures that if synchronization is lost, the
receiver can resynchronize to a start bit under all condi-
tions. The serial to parallel converter shown in Figure 7
requires 18 zeros to avoid triggering on data bits.
The Manchester receiver shown in Figure 7 was adopted
from Xilinx application note 17-30 and would typically be
implemented in an FPGA. The decoder clock frequency is
nominally 8 times the transmit clock frequency and is very
tolerant of frequency errors. The outputs of the decoder
are data and a strobe that indicates a valid data bit. The
data can be deserialized using shift registers as shown.
The start bit resets the J-K/fl ip-fl op on its way into the
fi rst shift register. When it appears at the QHIN output of
the second shift register, it sets the fl ip-fl op that loads the
parallel data into the output register.
With AC family CMOS logic at 5V the receiver clock fre-
quency is limited to 20MHz; the corresponding transmitter
clock frequency is 2.5MHz. If the receiver is implemented
in an FPGA that can be clocked at 160MHz, the LTC1864
can be clocked at its rated clock frequency of 20MHz.
LTC1864/LTC1865
21
18645fb
PACKAGE DESCRIPTION
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
MSOP (MS8) 1001
0.53 ± 0.015
(.021 ± .006)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.18
(.077)
0.254
(.010)
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
0.13 ± 0.05
(.005 ± .002)
0.86
(.034)
REF
0.65
(.0256)
BCS
0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
12
34
4.88 ± 0.1
(.192 ± .004)
8765
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
3.00 ± 0.102
(.118 ± .004)
NOTE 4
0.52
(.206)
REF
5.23
(.206)
MIN
3.2 – 3.45
(.126 – .136)
0.889 ± 0.127
(.035 ± .005)
RECOMMENDED SOLDER PAD LAYOUT
0.42 ± 0.04
(.0165 ± .0015)
TYP
0.65
(.0256)
BSC
LTC1864/LTC1865
22
18645fb
PACKAGE DESCRIPTION
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
MSOP (MS) 1001
0.53 ± 0.01
(.021 ± .006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 – 0.27
(.007 – .011)
0.13 ± 0.05
(.005 ± .002)
0.86
(.034)
REF
0.50
(.0197)
TYP
12345
4.88 ± 0.10
(.192 ± .004)
0.497 ± 0.076
(.0196 ± .003)
REF
8910 76
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
3.00 ± 0.102
(.118 ± .004)
NOTE 4
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010) 0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.23
(.206)
MIN
3.2 – 3.45
(.126 – .136)
0.889 ± 0.127
(.035 ± .005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 ± 0.038
(.0120 ± .0015)
TYP
0.50
(.0197)
BSC
LTC1864/LTC1865
23
18645fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
0.016 – 0.050
(0.406 – 1.270)
0.010 – 0.020
(0.254 – 0.508)× 45°
0°– 8° TYP
0.008 – 0.010
(0.203 – 0.254)
SO8 1298
0.053 – 0.069
(1.346 – 1.752)
0.014 – 0.019
(0.355 – 0.483)
TYP
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
BSC
1234
0.150 – 0.157**
(3.810 – 3.988)
8765
0.189 – 0.197*
(4.801 – 5.004)
0.228 – 0.244
(5.791 – 6.197)
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
*
**
LTC1864/LTC1865
24
18645fb
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2007
LT 1207 REV B • PRINTED IN USA
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER SAMPLE RATE POWER DISSIPATION DESCRIPTION
14-Bit Serial I/O ADCs
LTC1417 400ksps 20mW 16-Pin SSOP, Unipolar or Bipolar, Reference, 5V or ±5V
LTC1418 200ksps 15mW Serial/Parallel I/O, Internal Reference, 5V or ±5V
16-Bit Serial I/O ADCs
LTC1609 200ksps 65mW Confi gurable Bipolar or Unipolar Input Ranges, 5V
References
LT1460 Micropower Precision Series Reference Bandgap, 130μA Supply Current, 10ppm/°C, Available in SOT-23
LT1790 Micropower Low Dropout Reference 60μA Supply Current, 10ppm/°C, SOT-23
Op Amps
LT1468/LT1469 Single/Dual 90MHz, 16-Bit Accurate Op Amps 22V/μs Slew Rate, 75μV/125μV Offset
LT1806/LT1807 Single/Dual 325MHz Low Noise Op Amps 140V/μs Slew Rate, 3.5nV/√Hz Noise, –80dBc Distortion
LT1809/LT1810 Single/Dual 180MHz Low Distortion Op Amps 350V/μs Slew Rate, –90dBc Distortion at 5MHz
Sample Two Channels Simultaneously with a Single Input ADC 4096 Point FFT of Output
–
+
–
+
0.1μF
0.1μF
0.1μF
0.1μF
1μF
1μF
0.1μF1μF
100Ω
100Ω
28.7k
10k
4.096V
REF
5V
5V
5k
5k
10k
20k
100pF
100pF
5pF
1/2
LT1492
1/2
LT1492
f1
(0V TO 0.66V)
f2
(0V TO 2V) 8
4
2
81
7
6
5
4
3
4.096V
REF
LTC1864
IN+
IN–
VCC
GND
CONV
SDO
SCK
REF
18645 TA03a
0
10
20
30
40
50
60
70
80
90
100
110
120
130 0 5 10 15 20 25 30 35 40 45 50
FREQUENCY (kHz)
AMPLITUDE (dB)
18645 TA03b
f1 = 7.507324kHz AT 530mVP-P
f2 = 45.007324kHz AT 1.7VP-P
fS = 100kHz
