©2004 Integrated Device Technology, Inc.
JULY 2004
DSC 3199/8
1
Functional Block Diagram
Features
◆◆
◆◆
◆True Dual-Ported memory cells which allow simultaneous
access of the same memory location
◆◆
◆◆
◆High-speed access
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 20/25ns (max.)
◆◆
◆◆
◆Low-power operation
– IDT7027S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7027L
Active: 750mW (typ.)
Standby: 1mW (typ.)
◆◆
◆◆
◆Separate upper-byte and lower-byte control for bus
matching capability.
◆◆
◆◆
◆Dual chip enables allow for depth expansion without
external logic
HIGH-SPEED
32K x 16 DUAL-PORT
STATIC RAM
IDT7027S/L
◆◆
◆◆
◆IDT7027 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
◆◆
◆◆
◆M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
◆◆
◆◆
◆Busy and Interrupt Flags
◆◆
◆◆
◆On-chip port arbitration logic
◆◆
◆◆
◆Full on-chip hardware support of semaphore signaling
between ports
◆◆
◆◆
◆Fully asynchronous operation from either port
◆◆
◆◆
◆TTL-compatible, single 5V (±10%) power supply
◆◆
◆◆
◆Available in 100-pin Thin Quad Flatpack (TQFP) and 108-pin
Ceramic Pin Grid Array (PGA)
◆◆
◆◆
◆Industrial temperature range (–40°C to +85°C) is available
for selected speeds
NOTES:
1. BUSY is an input as a Slave (M/S=VIL) and an output as a Master (M/S=VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
I/O
Control
Address
Decoder
32Kx16
MEMORY
ARRAY
7027
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
0L
OE
L
R/W
L
A
14L
A
0L
A
14L
A
0L
SEM
L
INT
L
(2)
BUSY
L
LB
L
CE
0L
OE
L
UB
L
I/O
Control
Address
Decoder
CE
0R
OE
R
R/W
R
A
14R
A
0R
A
14R
A
0R
SEM
R
INT
R
(2)
BUSY
R
(1,2)
LB
R
R/
W
R
OE
R
UB
R
M/S
(2)
CE
1L
CE
0R
CE
1R
3199 drw 01
I/O
CE
1R
CE
1L
8-15L
I/O
I/O
0-7R
I/O
8-15R
0-7L
R/
W
L
.
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
2
Description
The IDT7027 is a high-speed 32K x 16 Dual-Port Static RAM,
designed to be used as a stand-alone 512K-bit Dual-Port RAM or as a
combination MASTER/SLAVE Dual-Port RAM for 32-bit-or-more word
systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-
bit or wider memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
The device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (CE0 and CE1) permits the on-chip
circuitry of each port to enter a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 750mW of power. The IDT7027 is
packaged in a 100-pin Thin Quad Flatpack (TQFP) and a 108-pin ceramic
Pin Grid Array (PGA).
Military grade product is manufactured in compliance with the
latest revision of MIL-PRF-38535 QML, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.
Pin Configurations(1,2,3)
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
INDEX
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
IDT7027PF
PN100-1(4)
100-Pin TQFP
Top View(5)
GND
OE
R
R/W
R
SEM
R
CE
1R
CE
0R
NC
NC
GND
A
12R
A
13R
A
11R
A
10R
A
9R
A
14R
NC
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
I/O
15R
GND
UB
R
LB
R
3199 drw 02
I/O
15L
GND
OE
L
R/W
L
SEM
L
CE
1L
CE
0L
Vcc
NC
A
14L
A
13L
NC
NC
A
12L
A
11L
A
10L
A
9L
I/O
10L
I/O
11L
I/O
12L
I/O
13L
I/O
14L
UB
L
LB
L
GND
I/O
5R
I/O
4R
I/O
3R
I/O
2R
I/O
0R
I/O
0L
GND
I/O
2L
I/O
4L
I/O
5L
I/O
6L
I/O
7
L
I/O
3L
I/O
1R
I/O
7R
NC
I/O
8R
I/O
9R
I/O
8L
I/O
9L
I/O
6R
A
7R
A
8L
A
7L
A
6R
A
5R
A
4R
A
3R
A
2R
A
1R
A
0R
INT
R
BUSY
R
M/S
BUSY
L
INT
L
NC
A
0L
A
2L
A
3L
A
5L
A
6L
A
1L
A
4L
A
8R
GND
Vcc
I/O1
L
Vcc
GND
.
07/23/04
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
3
Pin Configurations(1,2,3) (con't.)
Pin Names
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.21 in x 1.21 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
Left Port Right Port Names
CE
0L
, CE
1L
CE
0R
, CE
1R
Chip Enab les
R/W
L
R/W
R
Read/Write Enab le
OE
L
OE
R
Output Enable
A
0L
- A
14L
A
0R
- A
14R
Address
I/O
0L
- I/ O
15L
I/O
0R
- I/O
15R
Data Inp u t/ Out p ut
SEM
L
SEM
R
Semaphore Enable
UB
L
UB
R
Upper Byte Select
LB
L
LB
R
Lo we r By te Se le c t
INT
L
INT
R
Inte rrupt Flag
BUSY
L
BUSY
R
Busy Flag
M/SMaster or Slave Select
V
CC
Power
GND Ground
3199 tbl 01
3199 d r w 0 3
80 77 74 72 69 68 65 63 60
83 78 76 73 70 67 64 61 5984 56
8687
8890
9192
9495
9796
10099
103101
105104
2
1
5
4
7
8
10
12
13
17
16
21
19
25
22
28
24
32
31 34
35 37
39 40
44 43
48 46
52 49
55 51
IDT7027G
G108-1
(4)
108-Pin PGA
Top View
(5)
ABCDEFGHJ KLM
81 57 54
53
82 79 75 71 66 62 58 50
33
36
38
41
42
45
47
369111415182023
29 30
26 27
85
89
93
98
102
106
107
108
12
11
10
09
08
07
06
05
04
03
02
01
INDEX
GND
OE
R
R/W
R
SEM
R
CE
1R
CE
0R
NC
NC
GND
A
12R
A
13R
A
11R
A
10R
A
9R
GND
OE
L
R/W
L
SEM
L
CE
1L
CE
0L
Vcc
NC
A
14L
A
13L
NC
NCA
12L
A
11L
A
10L
A
9L
I/O
6R
I/O
5R
I/O
4R
I/O
3R
I/O
2R
I/O
0R
GND
Vcc
I/O
0L
I/O
1L
GNDI/O
2L
I/O
4L
I/O
5L
I/O
6L
I/O
7
L
I/O
3L
I/O
1R
I/O
7R
NC
I/O
8R
I/O
9R
I/O
8L
I/O
9L
VccA
6R
A
5R
A
4R
A
3R
A
2R
A
1R
A
0R
INT
R
BUSY
R
M/S
BUSY
L
INT
L
NC
A
0L
GND
A
2L
A
3L
A
5L
A
6L
A
1L
A
4L
A
8R
A
7R
A
8L
A
7L
A
14R
NC
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
I/O
15R
I/O
10L
I/O
11L
I/O
12L
I/O
13L
I/O
14L
GND
UB
R
LB
R
UB
L
LB
L
GND
NC
NC
NC
NC
NCNC
NC
NC
I/O
15L
.
07/23/04
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
4
NOTES:
1. Chip Enable references are shown above with the actual CE0 and CE1 levels, CE is a reference only.
2. Port "A" and "B" references are located where CE is used.
3 . "H" = VIH and "L" = VIL.
Truth Table I – Chip Enable
Truth Table II – Non-Contention Read/Write Control
NOTES:
1. A0L — A14L ≠ A0R — A14R.
2. Refer to Chip Enable Truth Table.
Truth Table III – Semaphore Read/Write Control
NOTES:
1. There are eight semaphore flags written to via I/O0 and read from all the I/Os (I/O0 __I/O15). These eight semaphore flags are addressed by A0-A2.
2. Refer to Chip Enable Truth Table.
CE CE
0
CE
1
Mode
LV
IL
V
IH
Po rt Se le c te d (TTL Ac tiv e )
< 0.2V >V
CC
- 0.2V Po rt Se le cte d (CMOS A ctiv e )
H
V
IH
X Po rt De s e le c te d (TTL Inac tiv e )
XV
IL
Po rt De s e le c te d (TTL Inac tiv e )
>V
CC
- 0. 2V X Po rt De s e le c te d (CMOS Inac tiv e )
X<
0.2V Po rt Dese lec te d (CMOS Inactive)
3199 tbl 02
Inputs
(1)
Outputs
Mode
CE
(2)
R/WOE UB LB SEM I/O
8-15
I/O
0-7
H X X X X H Hig h-Z Hig h-Z De s e le c te d : P owe r-Do wn
X X X H H H Hi gh-Z Hi g h-Z B o th B yte s De s e le cte d
LLXLHHDATA
IN
High-Z Write to Upper Byte Only
L L X H L H High-Z DATA
IN
Write to Lo we r By te Onl y
LLXLLHDATA
IN
DATA
IN
Write to B o th B yte s
LHLLHHDATA
OUT
High-Z Read Upper Byte Only
LHLHLHHigh-ZDATA
OUT
Read Lo we r B yte Only
LHLLLHDATA
OUT
DATA
OUT
Read Both Bytes
X X H X X X High-Z High-Z Outputs Disabled
3199 tbl 03
Inputs
(1)
Outputs
Mode
CE
(2)
R/WOE UB LB SEM I/O
8-15
I/O
0-7
HHLXXLDATA
OUT
DATA
OUT
Read Data in Semaphore Flag
XHLHHLDATA
OUT
DATA
OUT
Read Data in Semaphore Flag
H↑XXXLDATA
IN
DATA
IN
Wri te I/ O
0
into Semaphore Flag
X↑XHHLDATA
IN
DATA
IN
Wri te I/ O
0
into Semaphore Flag
LXXLXL
______ ______
Not Allo wed
LXXXLL
______ ______
Not Allo wed
3199 tbl 04
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
5
Capacitance(1)
(TA = +25°C, f = 1.0mhz) TQFP ONLY
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
NOTE:
1. At Vcc < 2.0V, input leakages are undefined.
Recommended DC Operating
Conditions
Maximum Operating
Temperature and Supply Voltage(1)
Absolute Maximum Ratings(1,3)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. COUT also references CI/O.
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
Symbol Rating Commercial
& Industrial Military Unit
V
TERM
(2)
Ter mi n al V olt a ge
with Respect
to G ND
-0.5 to +7.0 -0.5 to +7.0 V
T
BIAS
Temperature
Und er Bias -55 to +125 -65 to +135
o
C
T
STG
Storage
Temperature -65 to +150 -65 to +150
o
C
I
OUT
DC Outp ut
Current 50 50 mA
3199 tbl 05
Grade Ambient
Temperature GND Vcc
Military -55
O
C to + 125
O
C0V 5.0V
+
10%
Commercial 0
O
C to + 70
O
C0V5.0V
+
10%
Industrial -40
O
C to + 85
O
C0V 5.0V
+
10%
3199 t b l 06
Symbol Parameter Conditions Max. Unit
C
IN
In p ut Ca p aci tance V
IN
= 0V 9 pF
C
OUT
(2)
Output
Capacitance V
OUT
= 0V 10 p F
3199 tbl 08
Symbol Parameter Min. Typ. Max. Unit
V
CC
Supply Voltage 4.5 5.0 5.5 V
GND Ground 0 0 0 V
V
IH
Inp ut Hig h Vo ltag e 2. 2
____
6.0
(2)
V
V
IL
Inp ut Lo w Vo ltag e -0. 5
(1)
____
0.8 V
3199 tbl 07
Symbol Parameter Test Condi tions
7027S 7027L
UnitMin. Max. Min. Max.
|I
LI
| Inp ut Leakage Current
(1)
V
CC
= 5.5V, V
IN
= 0V to V
CC
___
10
___
5µA
|I
LO
| Outp ut Le akag e Curre nt CE = V
IH
, V
OUT
= 0V to V
CC
___
10
___
5µA
V
OL
Output Low Vo ltage I
OL
= 4mA
___
0.4
___
0.4 V
V
OH
Output High Voltage I
OH
= -4mA 2.4
___
2.4
___
V
3199 t bl 09
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
6
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,6) (VCC = 5.0V ± 10%)
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
2. VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions” of input
levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6. Refer to Chip Enable Truth Table.
7027X15
Co m 'l O nl y 7027X20
Com'l
& I nd
7027X25
Com'l
& I nd
Sym bol Parameter Test Conditio n Version Typ.
(2)
Max. Typ.
(2)
Max. Typ.
(2)
Max. Unit
I
CC
Dynami c O perating
Current
(B o th Ports A c tive)
CE = V
IL
, Outputs Disable d
SEM = V
IH
f = f
MAX
(3)
COM'L S
L205
200 365
325 190
180 325
285 180
170 305
265 mA
IND S
L
___
___
___
___
___
180
___
335 170
___
345
___
I
SB1
S tandb y Current
(B o th Ports - TTL Le v e l
Inputs)
CE
L
= CE
R
= V
IH
SEM
R
= SEM
L
= V
IH
f = f
MAX
(3)
COM'L S
L65
65 110
90 50
50 90
70 40
40 85
60 mA
IND S
L
___
___
___
___
___
50
___
85 40
___
100
___
I
SB2
S tandb y Current
(O ne P o rt - TTL Le v e l
Inputs)
CE
"A"
= V
IL
and CE
"B"
= V
IH
(5)
Active Port Outputs Disab led,
f=f
MAX
(3)
SEM
R
= SEM
L
= V
IH
COM'L S
L130
130 245
215 115
115 215
185 105
105 200
170 mA
IND S
L
___
___
___
___
___
115
___
220 105
___
230
___
I
SB3
Full Stand by Current
(B o th Ports - A ll CMOS
Level Inp uts )
Both Ports CE
L
and
CE
R
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V o r
V
IN
< 0.2V, f = 0
(4)
SEM
R
= SEM
L
> V
CC
- 0.2V
COM'L S
L1.0
0.2 15
51.0
0.2 15
51.0
0.2 15
5mA
IND S
L
___
___
___
___
___
0.2
___
10 1.0
___
30
___
I
SB4
Full Stand by Current
(O ne P o rt - Al l CM OS
Level Inp uts )
CE
"A"
< 0.2V a nd
CE
"B"
> V
CC
- 0. 2V
(5)
SEM
R
= SEM
L
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V o r V
IN
< 0.2V
Active Port Outputs Disab led
f = f
MAX
(3)
COM'L S
L120
120 220
190 110
110 190
160 100
100 170
145 mA
IND S
L
___
___
___
___
___
110
___
195 100
___
200
___
3199 tb l 10a
7027X35
Com 'l On ly 7027X55
Com'l Only
Symbol Parameter Test Condition Version Typ.
(2)
Max. Typ.
(2)
Max. Unit
I
CC
Dynamic Ope rating Current
(B o th P o rts A c tiv e ) CE = V
IL
, Outputs Disabled
SEM = V
IH
f = f
MAX
(3)
COM'L S
L160
160 295
255 150
150 270
230 mA
IND S
L
___
___
___
___
___
___
___
___
I
SB1
Standby Current
(Both Ports - TTL Level
Inputs)
CE
L
= CE
R
= V
IH
SEM
R
= SEM
L
= V
IH
COM'L S
L30
30 85
60 20
20 85
60 mA
IND S
L
___
___
___
___
___
___
___
___
I
SB2
Standby Current
(On e P o rt - TTL Le v e l
Inp uts )
CE
"A"
= V
IL
and CE
"B"
= V
IH
(5)
Active Port Outputs Disab led,
f=f
MAX
(3)
SEM
R
= SEM
L
= V
IH
COM'L S
L95
95 185
155 85
85 165
135 mA
IND S
L
___
___
___
___
___
___
___
___
I
SB3
Full Standby Current
(Bo th Ports - All CMOS
Lev e l Inp uts )
Both Ports CE
L
and
CE
R
> V
CC
- 0. 2V
V
IN
> V
CC
- 0. 2V o r
V
IN
< 0. 2V , f = 0
(4)
SEM
R
= SEM
L
> V
CC
- 0. 2V
COM'L S
L1.0
0.2 15
51.0
0.2 15
5mA
IND S
L
___
___
___
___
___
___
___
___
I
SB4
Full Standby Current
(One Port - A ll CMOS
Lev e l Inp uts )
CE
"A"
< 0. 2V and
CE
"B"
> V
CC
- 0. 2V
(5)
SEM
R
= SEM
L
> V
CC
- 0. 2V
V
IN
> V
CC
- 0. 2V or V
IN
< 0.2V
Active Port Outputs Disab led
f = f
MAX
(3)
COM'L S
L90
90 160
135 80
80 135
110 mA
IND S
L
___
___
___
___
___
___
___
___
3199 tb l 1 0b
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
7
AC Test Conditions
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Ranges(4)
NOTES:.
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE= VIH and SEM = VIL.
4. 'X' in part numbers indicates power rating (S or L).
5. Refer to Chip Enable Truth Table.
Figure 1. AC Output Test Load Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
*Including scope and jig.
d Inp ut Pulse Le ve ls
In p u t R i se/F al l Ti m es
Input Timi ng Re fe re nce Le ve ls
Outp ut Refe re nce Le v els
Outp ut Lo ad
GND to 3.0V
5ns Max.
1.5V
1.5V
Fig ures 1 and 2
31 9 9 tb l 11
3199 drw 04
893Ω
30pF
347Ω
5V
DATA
OUT
BUSY
INT
893Ω
5pF*
347Ω
5V
DATA
OUT
7027X15
Com'l Only 7027X20
Com'l
& Ind
7027X25
Com ' l
& I nd
7027X35
Com ' l Onl y 7027X55
Com ' l Onl y
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.Min.Max.Min.Max.
READ CYCLE
t
RC
Re ad Cy c le Ti m e 15
____
20
____
25
____
35
____
55
____
ns
t
AA
Address Access Time
____
15
____
20
____
25
____
35
____
55 ns
t
ACE
Chip Enable Access Time
(4)
____
15
____
20
____
25
____
35
____
55 ns
t
AOE
Output Enab le A cc e ss Tim e
____
10
____
12
____
13
____
20
____
30 ns
t
OH
Outp ut Ho ld fro m Ad d re ss Chang e 3
____
3
____
3
____
3
____
3
____
ns
t
LZ
Outp ut Lo w-Z Time
(1,2)
3
____
3
____
3
____
3
____
3
____
ns
t
HZ
Output Hig h-Z Time
(1,2)
____
10
____
12
____
15
____
15
____
25 ns
t
PU
Chi p E nab l e to P o we r Up Ti me
(2)
0
____
0
____
0
____
0
____
0
____
ns
t
PD
C hi p Dis ab l e to P o we r Do wn Tim e
(2)
____
15
____
20
____
25
____
35
____
50 ns
t
SOP
Semaphore Flag Up date Pulse (OE or SEM)10
____
10
____
12
____
15
____
15
____
ns
t
SAA
Semaphore Address Access Time
____
15
____
20
____
25
____
35
____
55 ns
3199 tbl 12
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
8
Waveform of Read Cycles(5)
Timing of Power-Up Power-Down
NOTES:
1. Timing depends on which signal is asserted last, CE, OE, LB, or UB.
2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
6. Refer to Chip Enable Truth Table.
t
RC
R/W
CE
ADDR
t
AA
OE
UB,LB
3199 drw 05
(4)
t
ACE
(4)
t
AOE
(4)
t
ABE
(4)
(1)
t
LZ
t
OH
(2)
t
HZ
(3,4)
t
BDD
DATA
OUT
BUSY
OUT
VALID DATA
(4)
(6)
CE
3199 drw 06
t
PU
I
CC
I
SB
t
PD
50% 50%
(6)
.
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
9
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3 . To access RAM CE= VIL and SEM = V IH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. Refer to Chip Enable
Truth Table.
4 . The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although t DH and tOW values will vary over voltage
and temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part numbers indicates power rating (S or L).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(5)
Symbol Parameter
7027X15
Com'l Only 7027X20
Com'l
& I nd
7027X25
Com'l
& I nd
7027X35
Com'l Only 7027X55
Com'l Only
UnitMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
WR IT E C YC LE
t
WC
Write Cycle Time 15
____
20
____
25
____
35
____
55
____
ns
t
EW
Chip Enable to End-of-Write
(3)
12
____
15
____
20
____
30
____
45
____
ns
t
AW
Address Valid to End-of-Write 12
____
15
____
20
____
30
____
45
____
ns
t
AS
Address Set-up Time
(3)
0
____
0
____
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 12
____
15
____
20
____
25
____
40
____
ns
t
WR
Wri te Re c o v e ry Time 0
____
0
____
0
____
0
____
0
____
ns
t
DW
Data Val i d to En d -o f-Wri te 10
____
15
____
15
____
15
____
30
____
ns
t
HZ
Output Hig h-Z Tim e
(1,2)
____
10
____
12
____
15
____
15
____
25 ns
t
DH
Data Ho l d Tim e
(5)
0
____
0
____
0
____
0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1,2)
____
10
____
12
____
15
____
15
____
25 ns
t
OW
Ou tp ut A c tiv e fro m E nd - o f-Wri te
(1,2,5)
0
____
0
____
0
____
0
____
0
____
ns
t
SWRD
SE M Fl ag Write to Re ad Time 5
____
5
____
5
____
5
____
5
____
ns
t
SPS
SE M Fl ag Co nte ntio n Wi nd o w 5
____
5
____
5
____
5
____
5
____
ns
3199 tb l 13
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
10
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
NOTES:
1. R/W or CE or UB and LB = VIH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7 . This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure
2).
8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified tWP.
9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
10. Refer to Chip Enable Truth Table.
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5)
R/W
t
WC
t
HZ
t
AW
t
WR
t
AS
t
WP
DATA
OUT
(2)
t
WZ
t
DW
t
DH
t
OW
OE
ADDRESS
DATA
IN
(6)
(4) (4)
(7)
UB or LB
3199 drw 07
(9)
CE or SEM
(9,10)
(7)
(3)
3199 drw 08
t
WC
t
AS
t
WR
t
DW
t
DH
ADDRESS
DATA
IN
R/W
t
AW
t
EW
UB or LB
(3)
(2)
(6)
CE or SEM
(9,10)
(9)
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
11
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
Timing Waveform of Semaphore Write Contention(1,3,4)
NOTES:
1. CE = VIH or UB and LB = VIH for the duration of the above timing (both write and read cycle), refer to Chip Enable Truth Table.
2. "DATAOUT VALID" represents all I/O's (I/O0-I/O15) equal to the semaphore value.
NOTES:
1. DOR = D OL = VIL, CER = CEL = VIH, or both UB & LB = VIH (refer to Chip Enable Truth Table).
2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied, there is no guarantee which side will be granted the semaphore flag.
SEM
3199 drw 09
t
AW
t
EW
t
SOP
I/O
0
VALID ADDRESS
t
SAA
R/W
t
WR
t
OH
t
ACE
VALID ADDRESS
DATA
IN
VALID DATA
OUT
t
DW
t
WP
t
DH
t
AS
t
SWRD
t
AOE
Read CycleWrite Cycle
A
0
-A
2
OE
VALID
(2)
SEM
"A"
3199 drw 10
t
SPS
MATCH
R/W
"A"
MATCH
A
0"A"
-A
2"A"
SIDE "A"
(2)
SEM
"B"
R/W
"B"
A
0"B"
-A
2"B"
SIDE
(2)
"B"
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
12
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6)
7027X15
Com'l Only 7027X20
Com'l
& I nd
7027X25
Com'l
& I nd
7027X35
Com'l Only 7027X55
Com'l Onl y
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
BUSY TIMING (M/S=V
IH
)
t
BAA
BUSY Access Time from Address Match ____ 15 ____ 20 ____ 20 ____ 20 ____ 45 ns
t
BDA
BUSY Disable Time from Address Not Matched ____ 15 ____ 20 ____ 20 ____ 20 ____ 40 ns
t
BAC
BUSY Access Time from Chip E nable Lo w ____ 15 ____ 20 ____ 20 ____ 20 ____ 40 ns
t
BDC
BUSY Access Time from Chip Enable High ____ 15 ____ 17 ____ 17 ____ 20 ____ 35 ns
t
APS
A rb i tra tio n Priori ty Se t-up Ti me
(2)
5____ 5____ 5____ 5____ 5____ ns
t
BDD
BUSY Disable to Valid Data
(3)
____ 15 ____ 20 ____ 25 ____ 35 ____ 55 ns
t
WH
Write Ho ld A fte r BUSY
(5)
12 ____ 15 ____ 17 ____ 25 ____ 25 ____ ns
BUSY TIMING (M/S=V
IL
)
t
WB
BUSY Inp ut to Write
(4)
0____ 0____ 0____ 0____ 0____ ns
t
WH
Write Ho ld A fte r BUSY
(5)
12 ____ 15 ____ 17 ____ 25 ____ 25 ____ ns
PORT-TO-PORT DELAY T IMI NG
t
WDD
Write Pulse to Data Delay
(1)
____ 30 ____ 45 ____ 50 ____ 60 ____ 80 ns
t
DDD
Write Data Valid to Read Data Delay
(1)
____ 25 ____ 30 ____ 35 ____ 45 ____ 65 ns
3199 tbl 14
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
13
Timing Waveform of Write with Port-to-Port Read and BUSY
(M/S = VIH)(2,4,5)
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the "Slave" version.
Timing Waveform of Write with BUSY (M/S = VIL)
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).
2. CEL = CER = VIL (refer to Chip Enable Truth Table).
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
3199 drw 11
t
DW
t
APS
ADDR
"A"
t
WC
DATA
OUT "B"
MATCH
t
WP
R/W
"A"
DATA
IN "A"
ADDR
"B"
t
DH
VALID
(1)
MATCH
BUSY
"B"
t
BDA
VALID
t
BDD
t
DDD
(3)
t
WDD
t
BAA
3199 drw 12
R/W
"A"
BUSY
"B"
t
WP
t
WB
R/W
"B"
t
WH
(2)
(3)
(1)
.
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
14
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing (M/S = VIH)(1)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
3. Refer to Chip Enable Truth Table.
Waveform of BUSY Arbitration Controlled by CE Timing (M/S = VIH)(1,3)
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1)
3199 drw 13
ADDR
"A"
and
"B"
ADDRESSES MATCH
CE
"A"
CE
"B"
BUSY
"B"
t
APS
t
BAC
t
BDC
(2)
3199 drw 14
ADDR
"A"
ADDRESS "N"
ADDR
"B"
BUSY
"B"
t
APS
t
BAA
t
BDA
(2)
MATCHING ADDRESS "N"
7027X15
Com'l Only 7027X20
Com'l
& In d
7027X25
Com'l
& I nd
7027X35
Com'l Only 7027X55
Com'l Only
Symbol Parameter Min.Max.Min.Max.Min.Max.Min.Max.Min.Max.Unit
I NTERRUPT TI MI NG
t
AS
Ad dress Set-up Time 0
____
0
____
0
____
0
____
0
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
0
____
0
____
ns
t
INS
Inte rrup t Se t Ti me
____
15
____
20
____
20
____
25
____
40 ns
t
INR
Inte rrup t Re s e t Time
____
15
____
20
____
20
____
25
____
40 ns
3199 tbl 15
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
15
Waveform of Interrupt Timing(1,5)
Truth Table IV — Interrupt Flag(1,4)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. See the Interrupt Truth Table IV.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
5. Refer to Chip Enable Truth Table.
NOTES:
1. Assumes BUSYL = BUSYR =VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. Refer to Chip Enable Truth Table.
3199 drw 15
ADDR
"A"
INTERRUPT SET ADDRESS
CE
"A"
R/W
"A"
t
AS
t
WC
t
WR
(3) (4)
t
INS
(3)
INT
"B"
(2)
3199 drw 16
ADDR
"B"
INTERRUPT CLEAR ADDRESS
CE
"B"
OE
"B"
t
AS
t
RC
(3)
t
INR
(3)
INT
"B"
(2)
Left P or t Ri ght P ort
FunctionR/W
L
CE
L
OE
L
A
14L
-A
0L
INT
L
R/W
R
CE
R
OE
R
A
14R
-A
0R
INT
R
LLX7FFFXXXX X L
(2) S e t R ig h t INT
R
Flag
XXX X XXLL7FFFH
(3) Res e t Ri g ht INT
R
Fl ag
XXX X L
(3) L L X 7 FFE X Se t Le ft INT
L
Flag
XLL7FFEH
(2) XXXXXReset Left INT
L
Flag
3199 tb l 16
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
16
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT7027 are
push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2 . "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3 . Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of the actual logic level on the pin. Writes to the right port are internally
ignored when BUSYR outputs are driving LOW regardless of the actual logic level on the pin.
4. Refer to Chip Enable Truth Table.
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7027.
2. There are eight semaphore flags written to via I/O0 and read from all the I/O's (I/O0-I/O15). These eight semaphores are addressed by A0-A2.
3. CE = VIH, SEM = VIL, to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
Functional Description
The IDT7027 provides two ports with separate control, address and
I/O pins that permit independent access for reads or writes to any location
in memory. The IDT7027 has an automatic power down feature controlled
by CE0 and CE1. The CE0 and CE1 control the on-chip power down
circuitry that permits the respective port to go into a standby mode when
not selected (CE = VIH). When a port is enabled, access to the entire
memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
(INTL) is asserted when the right port writes to memory location 7FFE
(HEX), where a write is defined as CER = R/WR = V IL per Truth Table
IV. The left port clears the interrupt through access of address location
7FFE when CEL= OEL= VIL, R/W is a "don't care". Likewise, the right port
interrupt flag (INTR) is asserted when the left port writes to memory location
7FFF (HEX) and to clear the interrupt flag (INTR), the right port must read
the memory location 7FFF. The message (16 bits) at 7FFE or 7FFF is
user-defined since it is an addressable SRAM location. If the interrupt
function is not used, address locations 7FFE and 7FFF are not used as
mail-boxes by ignoring the interrupt, but as part of the random access
memory. Refer to Truth Table IV for the interrupt operation.
Truth Table VI — Example of Semaphore Procurement Sequence(1,2,3)
Truth Table V —
Address Bus Arbitration(4)
Inputs Outputs
Function
CE
L
CE
R
A
OL
-A
14L
A
OR
-A
14R
BUSY
L
(1)
BUSY
R
(1)
X X NO MATCH H H Normal
H X MATCH H H Normal
X H MATCH H H Normal
LL MATCH (2) (2) Write
Inhi b it
(3)
31 99 tbl 17
Functions D
0
- D
15
Left D
0
- D
15
Right Status
No Action 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token
Left Po rt Writes "0" to Se map ho re 1 0 No chang e . Le ft p ort has no write acce s s to se map ho re
Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free
Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token
Right Port Writes "1" to Semaphore 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free
3199 tbl 18
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
17
Busy Logic
Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is “Busy”.
The BUSY pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a BUSY indication, the write signal is gated internally
to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of busy logic is not
desirable, the BUSY logic can be disabled by placing the part in slave mode
with the M/S pin. Once in slave mode the BUSY pin operates solely as a
write inhibit input pin. Normal operation can be programmed by tying the
BUSY pins HIGH. If desired, unintended write operations can be pre-
vented to a port by tying the BUSY pin for that port LOW.
The BUSY outputs on the IDT7027 RAM in master mode, are push-
pull type outputs and do not require pull up resistors to operate. If these
RAMs are being expanded in depth, then the BUSY indication for the
resulting array requires the use of an external AND gate.
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT7027 RAMs.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an IDT7027 RAM array in width while using BUSY
logic, one master part is used to decide which side of the RAM array
will receive a BUSY indication, and to output that indication. Any number
of slaves to be addressed in the same address range as the master, use
the BUSY signal as a write inhibit signal. Thus on the IDT7027 RAM the
BUSY pin is an output if the part is used as a Master (M/S pin = VIH), and
the BUSY pin is an input if the part used as a Slave (M/S pin = VIL) as shown
in Figure 3.
If two or more master parts were used when expanding in width, a split
decision could result with one master indicating BUSY on one side of the
array and another master indicating BUSY on one other side of the array.
This would inhibit the write operations from one port for part of a word and
inhibit the write operations from the other port for the other part of the word.
The BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enough for a BUSY flag to be output from the master before the actual write
pulse can be initiated with either the R/W signal or the byte enables. Failure
to observe this timing can result in a glitched internal write inhibit signal and
corrupted data in the slave.
Semaphores
The IDT7027 is a fast Dual-Port 32K x 16 CMOS Static RAM with an
additional 8 address locations dedicated to binary semaphore flags. These
flags allow either processor on the left or right side of the Dual-Port SRAM
to claim a privilege over the other processor for functions defined by the
system designer’s software. As an example, the semaphore can be used
by one processor to inhibit the other from accessing a portion of the Dual-
Port SRAM or any other shared resource.
The Dual-Port SRAM features a fast access time, and both ports are
completely independent of each other. This means that the activity on the
left port in no way slows the access time of the right port. Both ports are
identical in function to standard CMOS Static RAM and can be read from,
or written to, at the same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphore location. Semaphores are protected against such ambiguous
situations and may be used by the system program to avoid any conflicts
in the non-semaphore portion of the Dual-Port SRAM. These devices
have an automatic power-down feature controlled by CE the Dual-Port
SRAM enable, and SEM, the semaphore enable. The CE and SEM pins
control on-chip power down circuitry that permits the respective port to go
into standby mode when not selected. This is the condition which is shown
in Truth Table II where CE and SEM = VIH.
Systems which can best use the IDT7027 contain multiple processors
or controllers and are typically very high-speed systems which are
software controlled or software intensive. These systems can benefit
from a performance increase offered by the IDT7027's hardware
semaphores, which provide a lockout mechanism without requiring
complex programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in varying
configurations. The IDT7027 does not use its semaphore flags to control
any resources through hardware, thus allowing the system designer total
flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred in
either processor. This can prove to be a major advantage in very high-
speed systems.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are independent
of the Dual-Port SRAM. These latches can be used to pass a flag, or token,
from one port to the other to indicate that a shared resource is in use. The
semaphores provide a hardware assist for a use assignment method
called “Token Passing Allocation.” In this method, the state of a semaphore
latch is used as a token indicating that shared resource is in use. If the left
processor wants to use this resource, it requests the token by setting the
latch. This processor then verifies its success in setting the latch by reading
it. If it was successful, it proceeds to assume control over the shared
resource. If it was not successful in setting the latch, it determines that the
right side processor has set the latch first, has the token and is using the
shared resource. The left processor can then either repeatedly request
that semaphore’s status or remove its request for that semaphore to
3199 drw 17
MASTER
Dual Port RAM
BUSY
R
CE
0
MASTER
Dual Port RAM
BUSY
R
SLAVE
Dual Port RAM
BUSY
R
SLAVE
Dual Port RAM
BUSY
R
CE
1
CE
1
CE
0
A
15
BUSY
L
BUSY
L
BUSY
L
BUSY
L
BUSY
L
BUSY
R
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
18
D
3199 drw 18
0DQ
WRITE
D
0
D
Q
WRITE
SEMAPHORE
REQUEST FLIP FLOP SEMAPHORE
REQUEST FLIP FLOP
LPORT RPORT
SEMAPHORE
READ
SEMAPHORE
READ
.
perform another task and occasionally attempt again to gain control of the
token via the set and test sequence. Once the right side has relinquished
the token, the left side should succeed in gaining control.
The semaphore flags are active low. A token is requested by writing
a zero into a semaphore latch and is released when the same side writes
a one to that latch.
The eight semaphore flags reside within the IDT7027 in a separate
memory space from the Dual-Port SRAM. This address space is accessed
by placing a low input on the SEM pin (which acts as a chip select for the
semaphore flags) and using the other control pins (Address, OE, and
R/W) as they would be used in accessing a standard Static RAM. Each
of the flags has a unique address which can be accessed by either side
through address pins A0 – A2. When accessing the semaphores, none of
the other address pins has any effect.
When writing to a semaphore, only data pin D0 is used. If a LOW level
is written into an unused semaphore location, that flag will be set to a zero
on that side and a one on the other side (see Truth Table VI). That
semaphore can now only be modified by the side showing the zero. When
a one is written into the same location from the same side, the flag will be
set to a one for both sides (unless a semaphore request from the other side
is pending) and then can be written to by both sides. The fact that the side
which is able to write a zero into a semaphore subsequently locks out writes
from the other side is what makes semaphore flags useful in interprocessor
communications. (A thorough discussion on the use of this feature follows
shortly.) A zero written into the same location from the other side will be
stored in the semaphore request latch for that side until the semaphore is
freed by the first side.
When a semaphore flag is read, its value is spread into all data bits so
that a flag that is a one reads as a one in all data bits and a flag containing
a zero reads as all zeros. The read value is latched into one side’s output
register when that side's semaphore select (SEM) and output enable (OE)
signals go active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the other side.
Because of this latch, a repeated read of a semaphore in a test loop must
cause either signal (SEM or OE) to go inactive or the output will never
change.
A sequence WRITE/READ must be used by the semaphore in order
to guarantee that no system level contention will occur. A processor
requests access to shared resources by attempting to write a zero into a
semaphore location. If the semaphore is already in use, the semaphore
request latch will contain a zero, yet the semaphore flag will appear as one,
a fact which the processor will verify by the subsequent read (see Truth
Table VI). As an example, assume a processor writes a zero to the left port
at a free semaphore location. On a subsequent read, the processor will
verify that it has written successfully to that location and will assume control
over the resource in question. Meanwhile, if a processor on the right side
attempts to write a zero to the same semaphore flag it will fail, as will be
verified by the fact that a one will be read from that semaphore on the right
side during subsequent read. Had a sequence of READ/WRITE been
used instead, system contention problems could have occurred during the
gap between the read and write cycles.
It is important to note that a failed semaphore request must be followed
by either repeated reads or by writing a one into the same location. The
reason for this is easily understood by looking at the simple logic diagram
of the semaphore flag in Figure 4. Two semaphore request latches feed
into a semaphore flag. Whichever latch is first to present a zero to the
Figure 4. IDT7027 Semaphore Logic
semaphore flag will force its side of the semaphore flag LOW and the other
side HIGH. This condition will continue until a one is written to the same
semaphore request latch. Should the other side’s semaphore request latch
have been written to a zero in the meantime, the semaphore flag will flip
over to the other side as soon as a one is written into the first side’s request
latch. The second side’s flag will now stay LOW until its semaphore request
latch is written to a one. From this it is easy to understand that, if a semaphore
is requested and the processor which requested it no longer needs the
resource, the entire system can hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timing is when both sides request a
single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem. If simulta-
neous requests are made, the logic guarantees that only one side receives
the token. If one side is earlier than the other in making the request, the
first side to make the request will receive the token. If both requests
arrive at the same time, the assignment will be arbitrarily made to one port
or the other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is secure.
As with any powerful programming technique, if semaphores are misused
or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be handled
via the initialization program at power-up. Since any semaphore request
flag which contains a zero must be reset to a one, all semaphores on both
sides should have a one written into them at initialization from both sides
to assure that they will be free when needed.
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
19
Ordering Information
NOTE:
1. Contact your local sales office for industrial temp range for other speeds, packages and powers.
A
Power
999
Speed
A
Package
A
Process/
Temperature
Range
Blank
I
(1)
B
Commercial (0°C to +70°C)
Industrial (-40°C to + 85°C)
Military (-55°C to +125°C)
Compliant to MIL-PRF-38535 QML
PF
G
100-pin TQFP (PN100-1)
108-pin PGA (G108-1)
20
25
35
55
S
L
Standard Power
Low Power
XXXXX
Device
Type
512K (32K x 16) Dual-Port RAM7027
IDT
3199 drw 19
Commercial & Industrial
Commercial & Industrial
Commercial Only
Commercial Only
Speed in nanoseconds
.
15 Commercial Only
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794
San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
1/15/99: Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Pages 2 and 3 Added additional notes to pin configurations
5/19/99: Pages 4 and 16 Fixed typographical errors
6/3/99: Changed drawing format
Page 1 Corrected DSC number
11/10/99: Replaced IDT logo
5/22/00: Page 5 Increased storage temperature parameter
Clarified TA parameter
Page 6 DC Electrical parameters–changed wording from "open" to "disabled"
Changed ±200mV to 0mV in notes
7/23/04 Page 2 & 3 Added date revision for pin configurations
Page 5 Updated Capacitance table
Page 6 Added 15ns commercial speed grade to the DC Electrical Characteristics
Added 20ns Industrial temp for low power to DC Electrical Characteristics
Removed military temp range for 25/35/55ns from DC Electrical Characteristics
Page 7, 9, 12 & 14 Added 15ns commercial speed grade to AC Electrical Characteristics
Added 20ns Industrial temp for low power to AC Electrical Characteristics for Read, Write, Busy and Interrupt
Removed military temp range for 25/35/55ns from AC Electrical Characteristics
Page 19 Added Commercial speed grade for 15ns and Industrial temp to 20ns in ordering information
Page 1 & 19 Replaced old TM logo with new TM logo
