SA57
SA57U 1
P r o d u c t I n n o v a t i o n F r o m
DESCRIPTION
The SA57 is a fully integrated switching amplier de-
signed primarily to drive DC brush motors. Two inde-
pendent half bridges provide over 15 amperes peak
output current under microcontroller or DSC control.
Thermal and short circuit monitoring is provided, which
generates fault signals for the microcontroller to take
appropriate action. A block diagram is provided in Fig-
ure 1.
Additionally, cycle-by-cycle current limit offers user
programmable hardware protection independent of the
microcontroller. Output current is measured using an
innovative low loss technique. The SA57 is built using
a multi-technology process allowing CMOS logic con-
trol and complementary DMOS output power devices
on the same IC. Use of P-channel high side FETs en-
ables 60V operation without bootstrap or charge pump
circuitry.
The Power Quad surface mount package balances ex-
cellent thermal performance with the advantages of a
low prole surface mount package.
FEATURES
♦ Low cost intelligent switching amplier
♦ Directly connects to most embedded Micro-
controllers and Digital Signal Controllers
♦ Integrated gate driver logic with dead-time
generation and shoot-through prevention
♦ Wide power supply range (8.5V to 60V)
♦ Over 15A peak output current per phase
♦ 5A continuous output current per phase
8A continuous for A-Grade (SA57A)
♦ Independent current sensing for each output
♦ User programmable cycle-by-cycle current
limit protection
♦ Over-current and over-temperature warning
signals
APPLICATIONS
♦ Bidirectional DC brush motors
♦ 2 unidirectional DC brush motors
♦ 2 independent solenoid actuators
♦ Stepper motors
Switching Amplifier
SA57
P r o d u c t I n n o v a t i o n F r o m
FIGURE 1. BLOCK DIAGRAM
Copyright © Cirrus Logic, Inc. 2008
(All Rights Reserved)
http://www.cirrus.com
OCT 2008
SA57 Switching Amplifier
V s 1
P G N D 1
Gate
Control
PWM
Signals
O ut 1
O ut 2
P G N D 2
T E M P
GND
V s 2
VS+
ILIM/D IS 1
S C
D IS 2
S G N D
P h as e 1
P h as e 2
Control
Logic
VDD
I1' I2'
I1'
I2'
Fault
Logic
I1
I2
1t
1b
2t
2b
VDD VDD
SA57
2 SA57U
P r o d u c t I n n o v a t i o n F r o m
1. CHARACTERISTICS AND SPECIFICATIONS
NOTES:
1. (All Min/Max characteristics and specications are guaranteed over the Specied Operating Condi-
tions. Typical performance characteristics and specications are derived from measurements taken
at typical supply voltages and TC = 25°C).
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Min Max Units
SUPPLY VOLTAGE VS60 V
SUPPLY VOLTAGE VDD 5.5 V
LOGIC INPUT VOLTAGE (-0.5) (VDD+0.5) V
OUTPUT CURRENT, peak, 10ms2IOUT 17 A
POWER DISSIPATION, avg, 25ºC2PD100 W
TEMPERATURE, junction3TJ150 °C
TEMPERATURE RANGE, storage TSTG −55 125 °C
OPERATING TEMPERATURE, case TA−40 125 °C
2. Long term operation at elevated temperature will result in reduced product life. De-rate internal power
dissipation to achieve high MTBF.
3. Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any
set of conditions, do not exceed the specied current rating or a junction temperature of 150°C.
Parameter Test Conditions2SA57 SA57A Units
Min Typ Max Min Typ Max
LOGIC
INPUT LOW 1 * V
INPUT HIGH 1.8 * V
OUTPUT LOW 0.3 * V
OUTPUT HIGH 3.7 * V
OUTPUT CURRENT
(SC, Temp, ILIM/DIS1) 50 * mA
POWER SUPPLY
VSUVLO 50 60 55 V
VS UNDERVOLTAGE
LOCKOUT, (UVLO) 9 * * V
VDD 4.5 5.5 * * V
SUPPLY CURRENT, VS
20 kHz (One phase
switching at 50% duty
cycle) , VS=50V, VDD=5V
25 30 * * mA
SUPPLY CURRENT, VDD
20 kHz (One phase
switching at 50% duty
cycle) , VS=50V, VDD=5V
5 6 * * mA
SPECIFICATIONS
* The specication of SA57A is identical to the specication for SA57 in applicable column to the left.
SA57
SA57U 3
P r o d u c t I n n o v a t i o n F r o m
Parameter Test Conditions2SA57 SA57A Units
Min Typ Max Min Typ Max
CURRENT LIMIT
CURRENT LIMIT
THRESHOLD (Vth)3.95 * V
Vth HYSTERESIS 100 * mV
OUTPUT
CURRENT, CONTINUOUS 25ºC Case Temperature 58A
RISING DELAY, TD (RISE) See Figure 10 270 * ns
FALLING DELAY, TD (FALL) See Figure 10 270 * ns
DISABLE DELAY, TD (DIS) See Figure 10 200 * ns
ENABLE DELAY, TD (DIS)See Figure 10 200 * ns
RISE TIME, T (RISE) See Figure 11 50 * ns
FALL TIME, T (FALL) See Figure 11 50 * ns
ON RESISTANCE
SOURCING (P-CHANNEL) 5A Load 300 750 300 600 mΩ
ON RESISTANCE
SINKING (N-CHANNEL) 5A Load 250 750 250 600 mΩ
THERMAL
THERMAL WARNING 135 * ºC
THERMAL WARNING
HYSTERESIS 40 *ºC
RESISTANCE, junction to
case Full temperature range 1.25 1.5 * * ºC/W
TEMPERATURE RANGE,
case Meets Specications -25 85 -40 125 ºC
FIGURE 2. 64-PIN QFP, PACKAGE STYLE HQ
SPECIFICATIONS, continued
SA57
4 SA57U
P r o d u c t I n n o v a t i o n F r o m
DIODE FORWARD VOLTAGE - TOP FET
(P-Channel)
0
1
2
3
4
5
FORWARD VOLTAGE (V)
CURRENT (A)
0.5 1.51.31.10.90.7
DIODE FORWARD VOLTAGE - BOTTOM FET
(N-Channel)
0
1
2
3
4
5
FORWARD VOLTAGE (V)
CURRENT (A)
0.5 1.51.31.10.90.7
ON RESISTANCE - TOP FET
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
IOUT,(A)
RDS(on),(Ω)
VS=11
VS=13
VS=15
VS>17
100 987654321
(P-Channel)
ON RESISTANCE - BOTTOM FET
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
10
IOUT,(A)
RDS(on),(Ω)
VS=11
VS=13
VS=15
VS=17
VS>22
0 987654321
(N-Channel)
POWER DERATING
0
20
40
60
80
100
120
CASE TEMPERATURE, TC
POWER DISSIPATION, PD
SA57
SA57A
-40 12080400
VDD SUPPLY CURRENT
4.5
4.6
4.7
4.8
4.9
5
0 50 100 150 200 250 300
FREQUENCY (kHz)
VDD SUPPLY CURRENT (mA)
ONE PHASE SWITCHING @
50% DUTY CYCLE; VS=50V
VDD SUPPLY CURRENT
4
4.5
5
5.5
6
6.5
7
7.5
8
10 20 30 40 50 60
VS SUPPLY VOLTAGE (V)
VDD SUPPLY CURRENT (mA)
ONE PHASE SWITCHING
FREQUENCY = 20kHz
50% DUTY CYCLE
25°C
125°C
CURRENT SENSE
0.1
1
10
0.01 0.1 1 10
SENSE CURRENT (mA)
LOAD CURRENT (A)
VS SUPPLY CURRENT
20
40
60
80
100
120
140
160
180
0 50 100 150 200 250 300
FREQUENCY (kHz)
V
S
SUPPLY CURRENT (mA)
ONE PHASE SWITCHING @
50% DUTY CYCLE; VS=50V
0
V
S
SUPPLY CURRENT
0
5
10
15
20
25
V
S
SUPPLY VOLTAGE (V)
V
S
SUPPLY CURRENT (mA)
125°C
25°C
ONE PHASE SWITCHING
FREQUENCY = 20kHz
50% DUTY CYCLE
10 20 30 40 50 60
SA57
SA57U 5
P r o d u c t I n n o v a t i o n F r o m
FIGURE 3. EXTERNAL CONNECTIONS
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
OUT 2
OUT 2
NC
VS 2
VS 2
VS 2
VS 2
NC
NC
NC
NC
NC
PGND 1
PGND 1
PGND 1
PGND 1
NC
OUT 1
OUT 1
OUT 1
I2
NC
SC
NC
SGND
NC
ILIM/DIS1
NC
SGND
NC
SGND
NC
SGND
NC
1b
NC
1t
NC
VDD
NC
OUT 2
NC
PGND 2
PGND 2
PGND 2
HS
HS
NC
2b
NC
2t
NC
NC
VS 1
VS 1
VS 1
NC
HS
HS
TEMP
NC
DIS2
NC
I1
TABLE 1. PIN DESCRIPTIONS
Pin # Pin Name Signal Type
29,30,31 VS (phase 1) Power High Voltage Supply (8.5-60V) supplies phase 1 only
51,52,53 OUT 2 Power Output Half Bridge 2 Power Output
55,56,57 PGND (phase 2) Power High Current GND Return Path for Power Output 2
3 SC Logic Output Indication of a short of an output to supply, GND or another phase
61 2b Logic Input Logic high commands 2 phase lower FET to turn on
63 2t Logic Input Logic high commands 2 phase upper FET to turn on
1I2 Analog Output Phase 2 current sense output
7 ILIM/DIS1 Logic Input/Output
As an output, logic high indicates cycle-by-cycle current limit, and
logic low indicates normal operation. As an input, logic high places
all outputs in a high impedance state and logic low disables the
cycle-by-cycle current limit function.
SA57
6 SA57U
P r o d u c t I n n o v a t i o n F r o m
TABLE 1. PIN DESCRIPTIONS
Pin # Pin Name Signal Type
5,9,11,13 SGND Power Analog and digital GND – internally connected to PGND
15 1b Logic Input Logic high commands 1 phase lower FET to turn on
17 1t Logic Input Logic high commands 1 phase upper FET to turn on
19 VDD Power Logic Supply (5V)
21 I1 Analog Output Phase 1 current sense output
23 DIS2 Logic Input Logic high places all outputs in a high impedance state
25 TEMP Logic Output Thermal indication of die temperature above 135ºC
46,47,48,49 VS (phase 2) Power High Voltage Supply phase 2
33,34,35 OUT 1 Power Output Half Bridge 1 Power Output
37,38,39,40 PGND (phase 1) Power High Current GND Return Path for Power Outputs 1&2
26,27,58,59 HS Mechanical Pins connected to the package heat slug
2,4,6,8,10,
12,14,16,18,
20,22,24,28,
32,36,41,42,
43,44,45,50,
54,60,62,64
NC --- Do Not Connect
1.2 Pin Descriptions
S: Supply voltage for the output transistors. These pins require decoupling (1μF capacitor with good high frequency
characteristics is recommended) to the PGND pins. The decoupling capacitor should be located as close to the VS
and PGND pins as possible. Additional capacitance will be required at the VS pins to handle load current peaks and
potential motor regeneration. Refer to the applications section of this datasheet for additional discussion regarding
bypass capacitor selection. Note that Vs pins 29-31 carry only the phase 1 supply current. Pins 46-49 carry supply
current for phase2. Phase 1 may be operated at a different supply voltage from phase 2. Only the B & C supply pins
(46-49) are monitored for undervoltage conditions.
OUT 1, OUT 2: These pins are the power output connections to the load. NOTE: When driving an inductive load, it
is recommended that two Schottky diodes with good switching characteristics (fast tRR specs) be connected to each
pin so that they are in parallel with the parasitic back-body diodes of the output FETs. (See Section 2.6)
PGND: Power Ground. This is the ground return connection for the output FETs. Return current from the load ows
through these pins. PGND is internally connected to SGND through a resistance of a few ohms. See section 2.1 of
this datasheet for more details.
SC: Short Circuit output. If a condition is detected on any output which is not in accordance with the input com-
mands, this indicates a short circuit condition and the SC pin goes high. The SC signal is blanked for approximately
200ns during switching transitions but in high current applications, short glitches may appear on the SC pin. A high
state on the SC output will not automatically disable the device. The SC pin includes an internal 12kΩ series resis-
tor.
1b, 2b: These Schmitt triggered logic level inputs are responsible for turning the associated bottom, or lower N-
channel output FETs on and off. Logic high turns the bottom N-channel FET on, and a logic low turns the low side
N-channel FET off. If 1b or 2b is high at the same time that a corresponding 1t or 2t input is high, protection circuitry
will turn off both FETs in order to prevent shoot-through current on that output phase. Protection circuitry also in-
SA57
SA57U 7
P r o d u c t I n n o v a t i o n F r o m
cludes a dead-time generator, which inserts dead time in the outputs in the case of simultaneous switching of the
top and bottom input signals.
1t, 2t: These Schmitt triggered logic level inputs are responsible for turning the associated top side, or upper P-
channel FET outputs on and off. Logic high turns the top P-channel FET on, and a logic low turns the top P-channel
FET off.
I1, I2: Current sense pins. The SA57 supplies a positive current to these pins which is proportional to the current
owing through the top side P-channel FET for that phase. Commutating currents owing through the back-body
diode of the P-channel FET or through external Schottky diodes are not registered on the current sense pins. Nor do
currents owing through the low side N-channel FET, in either direction, register at the current sense pins. A resistor
connected from a current sense pin to SGND creates a voltage signal representation of the phase current that can
be monitored with ADC inputs of a processor or external circuitry.
The current sense pins are also internally compared with the current limit threshold voltage reference, Vth. If the
voltage on any current sense pin exceeds Vth, the cycle by cycle current limit circuit engages. Details of this func-
tionality are described in the applications section of this datasheet.
ILIM/DIS1: This pin is directly connected to the disable circuitry of the SA57. Pulling this pin to logic high places OUT
1 and OUT 2 in a high impedance state. This pin is also connected internally to the output of the current limit latch
through a 12kΩ resistor and can be monitored to observe the function of the cycle-by-cycle current limit feature.
Pulling this pin to a logic low effectively disables the cycle-by-cycle current limit feature.
SGND: This is the ground return connection for the VDD logic power supply pin. All internal analog and logic circuitry
is referenced to this pin. PGND is internally connected to GND through a resistance of a few ohms,. However, it is
highly recommended to connect the GND pin to the PGND pins externally as close to the device as possible. Failure
do to this may result in oscillations on the output pins during rising or falling edges.
DD: This is the connection for the 5V power supply, and provides power for the logic and analog circuitry in the
SA57. This pin requires decoupling (at least 0.1µF capacitor with good high frequency characteristics is recom-
mended) to the SGND pin.
DIS2: The DIS2 pin is a Schmitt triggered logic level input that places OUT 1 and OUT 2 in a high impedance state
when pulled high. DIS2 has an internal 12kΩ pull-down resistor and may therefore be left unconnected.
TEMP: This logic level output goes high when the die temperature of the SA57 reaches approximately 135ºC. This
pin WILL NOT automatically disable the device. The TEMP pin includes a 12kΩ series resistor.
HS: These pins are internally connected to the thermal slug on the reverse of the package. They should be con-
nected to GND. Neither the heat slug nor these pins should be used to carry high current.
NC: These “no-connect” pins should be left unconnected.
SA57
8 SA57U
P r o d u c t I n n o v a t i o n F r o m
2. SA57 OPERATION
The SA57 is designed primarily to drive DC brush motors. However, it can be used for any application requiring two
high current outputs. The signal set of the SA57 is designed specically to interface with a DSP or microcontroller. A
typical system block diagram is shown in the gure below. Over-temperature, Short-Circuit and Current Limit fault
signals provide important feedback to the system controller which can safely disable the output drivers in the pres-
ence of a fault condition. High side current monitors for both phases provide performance information which can
be used to regulate or limit torque.
FIGURE 4. SYSTEM DIAGRAM
SA57 Switching Amplifier
DC BRUSH
MOTOR
Vs 1
PGND 1
Current
monitor
Signals
1
2
OUT 1
OUT 2
PGND 2
GND
Vs 2
Vs +
GND
SGND
Gate
Control
Control
Logic
Fault
Logic
T E M P
I
LIM
/D IS 1
S C
I1
I2
V
DD
PWM
Signals
D IS 2
S G N D
1t
1b
2t
2b
M icrocontroller
or DSC
SA57
SA57U 9
P r o d u c t I n n o v a t i o n F r o m
SGND
Gate
Control
Vs
OUT 1
PGND
1t
1b
SC
TEMP
SC
Logic
Temp
Sense
Ref
I1
DIS2
ILIM/DIS1
UVLO
I1'
+
_
Lim 2
+
_
Vdd
Lim 1
Current
Sense
12k
12k
12k
12k
Vth
The block diagram in Figure 5 illustrates the features of the input and output structures of the SA57. For simplicity,
a single phase is shown.
FIGURE 5. INPUT AND OUTPUT STRUCTURES FOR A SINGLE PHASE
TABLE 2. TRUTH TABLE
1t, 2t
1b, 2b
I1, I2
ILIM/DIS1
DIS2
OUT 1
OUT 2
Comments
0 0 X X X High-Z Top and Bottom output FETs for that phase are turned off.
0 1 <Vth 0 0 PGND Bottom output FET for that phase is turned on.
1 0 <Vth 0 0 VS Top output FET for that phase is turned on.
1 1 X X X High-Z Both output FETs for that phase are turned off.
X X >Vth 1 X High-Z Voltage on I1 or I2 has exceeded Vth, which causes ILIM/DIS1 to go high.
This internally disables Top and Bottom output FETs for ALL phases.
X X X X 1 High-Z DIS2 pin pulled high, which disables all outputs.
X X X Pulled
High X High-Z Pulling the ILIM/DIS1 pin high externally acts as a second disable input,
which disables ALL output FETs.
X X X Pulled
Low 0
Determined
by PWM
inputs
Pulling the DIS2 pin low externally disables the cycle-by-cycle current limit
function. The state of the outputs is strictly a function of the PWM inputs.
X X X X X High-Z If VS is below the UVLO threshold all output FETs will be disabled.
SA57
10 SA57U
P r o d u c t I n n o v a t i o n F r o m
2.1 LAYOUT CONSIDERATIONS
Output traces carry signals with very high dV/dt and dI/dt. Proper routing and adequate power supply bypassing
ensures normal operation. Poor routing and bypassing can cause erratic and low efciency operation as well as
ringing at the outputs.
The VS supply should be bypassed with a surface mount ceramic capacitor mounted as close as possible to the VS
pins. Total inductance of the routing from the capacitor to the VS and GND pins must be kept to a minimum to pre-
vent noise from contaminating the logic control signals. A low ESR capacitor of at least 25μF per ampere of output
current should be placed near the SA57 as well. Capacitor types rated for switching applications are the only types
that should be considered.
The bypassing requirements of the VDD supply are less stringent, but still necessary. A 0.1μF to 0.47μF surface
mount ceramic capacitor (X7R or NPO) connected directly to the VDD pin is sufcient.
SGND and PGND pins are connected internally. However, these pins must be connected externally in such a way
that there is no motor current owing in the logic and signal ground traces as parasitic resistances in the small
signal routing can develop sufcient voltage drops to erroneously trigger input transitions. Alternatively, a ground
plane may be separated into power and logic sections connected by a pair of back to back Schottky diodes. This
isolates noise between signal and power ground traces and prevents high currents from passing between the plane
sections.
Unused area on the top and bottom PCB planes should be lled with solid or hatched copper to minimize inductive
coupling between signals. The copper ll may be left unconnected, although a ground plane is recommended.
2.2 FAULT INDICATIONS
In the case of either an over-temperature or short circuit fault, the SA57 will take no action to disable the outputs.
Instead, the SC and TEMP signals are provided to an external controller, where a determination can be made re-
garding the appropriate course of action. In most cases, the SC pin would be connected to a FAULT input on the
processor, which would immediately disable its PWM outputs. The TEMP fault does not require such an immediate
response, and would typically be connected to a GPIO, or Keyboard Interrupt pin of the processor. In this case,
the processor would recognize the condition as an external interrupt, which could be processed in software via an
Interrupt Service Routine. The processor could optionally bring all inputs low, or assert a high level to either of the
disable inputs on the SA57.
Figure 6 shows an external SR ip-op which pro-
vides a hard wired shutdown of all outputs in re-
sponse to a fault indication. An SC or TEMP fault sets
the latch, pulling the disable pin high. The processor
clears the latched condition with a GPIO. This circuit
can be used in safety critical applications to remove
software from the fault-shutdown loop, or simply to
reduce processor overhead.
In applications which may not have available GPIO,
the TEMP pin may be externally connected to the
adjacent DIS1 pin. If the device temperature reach-
es ~135ºC all outputs will be disabled, de-energizing
the motor. The SA57 will re-energize the motor when the device temperature falls below approximately 95ºC. The
TEMP pin hysteresis is wide to reduce the likelihood of thermal oscillations which can greatly reduce the life of the
device.
The undervoltage lockout condition results in the SA57 unilaterally disabling all output FETs until VS is above the
UVLO threshold indicated in the spec table. There is no external signal indicating that an undervoltage lockout con-
dition is in progress. The SA57 has two VS connections: one for phase 1 and another for phase 2. The supply volt-
FIGURE 6. EXTERNAL FAULT LATCH CIRCUIT
SA57
PROCESSOR
INTERRUPT
GPIO
PWM
SC
DIS2 TEMP
LATCHED FAULT
FAULT RESET
SA57
SA57U 11
P r o d u c t I n n o v a t i o n F r o m
ages on these pins need not be the same, but the
UVLO will engage if either is below the threshold.
Hysteresis on the UVLO circuit prevents oscilla-
tions with typical power supply variations.
2.4 CURRENT SENSE
External power shunt resistors are not required
with the SA57. Forward current in each top, P-
channel output FET is measured and mirrored to
the respective current sense output pin, I1 and
I2. By connecting a resistor between each cur-
rent sense pin and a reference, such as ground,
a voltage develops across the resistor that is pro-
portional to the output current for that phase. An
ADC can monitor the voltages on these resistors
for protection or for closed loop torque control
in some application congurations. The current
sense pins source current from the VDD supply.
Headroom required for the current sense circuit is
approximately 0.5V. The nominal scale factor for
each proportional output current is shown in the typical performance plot on page 4 of this datasheet.
2.5 CYCLE-BY-CYCLE CURRENT LIMIT
In applications where the current in the motor is not directly controlled, both the average current rating of the motor
and the inrush current must be considered when selecting a proper amplier. For example, a 1A continuous motor
might require a drive amplier that can deliver well over 10A peak in order to survive the inrush condition at start-
up.
Because the output current of each upper output FET is measured, the SA57 is able to provide a very robust current
limit scheme. This enables the SA57 to safely and easily drive virtually any DC brush motor through a start-up inrush
condition. With limited current, the starting torque and acceleration are also limited. The plot in Figure 7 shows
starting current and back EMF with and without current limit enabled.
If the voltage of any of the two current sense pins exceeds the current limit threshold voltage (Vth), all outputs are
disabled. After all current sense pins fall below the Vth threshold voltage AND the offending phase’s top side input
goes low, the output stage will return to an active state on the rising edge of ANY top side input command signal
(1t or 2t). With most commutation schemes, the current limit will reset each PWM cycle. This scheme regulates the
peak current in each phase during each PWM cycle as illustrated in the timing diagram below. The ratio of average
to peak current depends on the inductance of the motor winding, the back EMF developed in the motor, and the
width of the pulse.
Figure 8 illustrates the current limit trigger and reset sequence. Current limit engages and ILIM/DIS1 goes high when
any current sense pin exceeds Vth. Notice that the moment at which the current sense signal exceeds the Vth
threshold is asynchronous with respect to the input PWM signal. The difference between the PWM period and the
motor winding L/R time constant will often result in an audible beat frequency sometimes called a sub-cycle oscilla-
tion. This oscillation can be seen on the ILIM/DIS1 pin waveform in Figure 8.
Input signals commanding 0% or 100% duty cycle may be incompatible with the current limit feature due to the
absence of rising edges of 1t and 2t. At high RPM, this may result in poor performance. At low RPM, the motor may
stall if the current limit trips and the motor current reaches zero without a commutation edge which will typically reset
the current limit latch.
TIME
NON-LIMITED BACK EMF
LIMITED BACK EMF
LIMITED MOTOR CURRENT
NON-LIMITED MOTOR CURRENT
SA57
12 SA57U
P r o d u c t I n n o v a t i o n F r o m
The current limit feature may be disabled
by tying the ILIM/DIS1 pin to GND. The
current sense pins will continue to provide
top FET output current information.
Typically, the current sense pins source
current into grounded resistors which pro-
vide voltages to the current limit compara-
tors. If instead the current limit resistors are
connected to a voltage output DAC, the
current limit can be controlled dynamically
from the system controller. This technique
essentially reduces the current limit thresh-
old voltage to (Vth-VDAC). During expect-
ed conditions of high torque demand, such
as start-up or reversal, the DAC can adjust
the current limit dynamically to allow pe-
riods of high current. In normal operation
when low current is expected, the DAC
output voltage can increase, reducing the
current limit setting to provide more con-
servative fault protection.
2.6 EXTERNAL FLYBACK DIODES
External y-back diodes will offer superior reverse recovery characteristics
and lower forward voltage drop than the internal back-body diodes. In high
current applications, external yback diodes can reduce power dissipation
and heating during commutation of the motor current. Reverse recovery
time and capacitance are the most important parameters to consider when
selecting these diodes. Ultra-fast rectiers offer better reverse recovery
time and Schottky diodes typically have low capacitance. Individual appli-
cation requirements will be the guide when determining the need for these
diodes and for selecting the component which is most suitable.
It INPUT
OUT 1
I1
Vth
ILIM/DIS1
FIGURE 9. SCHOTTKY DIODES
OUT 1
OUT 2
VSVS
SA57
SA57
SA57U 13
P r o d u c t I n n o v a t i o n F r o m
FIGURE 10. TIMING DIAGRAMS
3. POWER DISSIPATION
The thermally enhanced package of the SA57 al-
lows several options for managing the power dis-
sipated in the two output stages. Power dissipation
in traditional PWM applications is a combination
of output power dissipation and switching losses.
Output power dissipation depends on the quadrant
of operation and whether external yback diodes
are used to carry the reverse or commutating cur-
rents. Switching losses are dependent on the fre-
quency of the PWM cycle as described in the typi-
cal performance graphs.
The size and orientation of the heatsink must be
selected to manage the average power dissipation
of the SA57. Applications vary widely and various
thermal techniques are available to match the re-
quired performance. The patent pending mounting
technique shown in Figure 12, with the SA57 in-
verted and suspended through a cutout in the PCB
is adequate for power dissipation up to 17W with
the HS33, a 1.5 inch long aluminum extrusion with
four ns. In free air, mounting the PCB perpendicular to the ground, such that the heated air ows upward along the
channels of the ns can provide a total ΘJA of less than 14 ºC/W (9W max average PD). Mounting the PCB parallel
to the ground impedes the ow of heated air and provides a ΘJA of 16.66 ºC/W (7.5W max average PD). In applica-
tions in which higher power dissipation is expected or lower junction or case temperatures are required, a larger
heatsink or circulated air can signicantly improve the performance.
4. ORDERING AND PRODUCT STATUS INFORMATION
MODEL TEMPERATURE PACKAGE PRODUCTION STATUS
SA57-IHZ -25 to 85ºC 64 pin Power QFP (HQ package drawing) Samples Available
SA57A-FHZ -40 to +125ºC 64 pin Power QFP (HQ package drawing) Samples Available
TOP INPUT
BOTTOM INPUT
DELAY TIMING
OUTPUT
DISABLE
td(fall) td(dis)td(rise) td(dis)
td(dis)
td(dis)
TOP INPUT
BOTTOM INPUT
OUTPUT
t(fall)
t(rise)
20%
80%
FIGURE 11. OUTPUT RESPONSE
SA57
14 SA57U
P r o d u c t I n n o v a t i o n F r o m
FIGURE 12. HEATSINK TECHNIQUE
PATENT PENDING
CONTACTING CIRRUS LOGIC SUPPORT
For all Apex Precision Power product questions and inquiries, call toll free 800-546-2739 in North America.
For inquiries via email, please contact tucson.support@cirrus.com.
International customers can also request support by contacting their local Cirrus Logic Sales Representative.
To nd the one nearest to you, go to www.cirrus.com
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