TPS51427 www.ti.com................................................................................................................................................ SLUS819B - APRIL 2008 - REVISED SEPTEMBER 2008 DUAL D-CAPTM SYNCHRONOUS STEP-DOWN CONTROLLER FOR NOTEBOOK POWER RAILS FEATURES 1 DESCRIPTION * Fixed-Frequency Emulated On-Time Control; Frequency Selectable from Three Options * D-CAPTM Mode Enables Fast Transient Response Less than 100 ns * Advanced Ramp Compensation Allows Low Output Ripple with Minimal Jitter * Selectable PWM-Only/OOATM/Auto-Skip Modes * Wide Input Voltage Range: 5.5 V to 28 V * Dual Fixed or Adjustable SMPS: - 0.7 V to 5.9 V (Channel1) - 0.5 V to 2.5 V (Channel2) * Fixed 3.3-V/5-V, or Adjustable Output 0.7-V to 4.5-V LDO; Capable of Sourcing 100 mA * Fixed 3.3-VREF Output Capable of Sourcing 10 mA * Temperature Compensated Low-Side RDS(on) Current Sensing * Adaptive Gate Drivers with Integrated Boost Switch * Bootstrap Charge Auto Refresh * Integrated Soft Start, Tracking Soft Stop * Independent PGOOD and EN for Each Channel 23 The TPS51427 is a dual synchronous step-down controller designed for notebook and mobile communications applications. This device is part of a low-cost suite of notebook power bus regulators that enables system designs with low external component counts. The TPS51427 includes two pulse-width-modulation (PWM) controllers, SMPS1 and SMPS2. The output of SMPS1 can be adjusted from 0.7 V to 5.9 V, while the output of SMPS2 can be adjusted from 0.5 V to 2.5 V. This device also features a low-dropout (LDO) regulator that provides a 5-V/3.3-V output, or adjustable from 0.7-V to 4.5-V output via LDOREFIN. The fixed-frequency emulated adaptive on-time control supports seamless operation between PWM mode under heavy load conditions and reduced frequency operation at light loads for high-efficiency down to the milliampere range. An integrated boost switch enhances the high-side MOSFET to further improve efficiency. The main control loop is the D-CAPTM mode that is optimized for low equivalent series resistance (ESR) output capacitors such as POSCAP or SP-CAP. Advanced ramp compensation minimizes jitter without degrading line and load regulation. RDS(on) current sensing methods offers maximum cost saving. The TPS51427 supports supply input voltages that range from 5.5 V to 28 V. It is available in the 32-pin, 5-mm x 5-mm QFN package (Green, RoHscompliant, and Pb-free). The device is specified from -40C to +85C. APPLICATIONS * * * Notebook I/O and System Bus Rails Graphics Application PDAs and Mobile Communication Devices TPS51427 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. D-CAP, OOA are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2008, Texas Instruments Incorporated TPS51427 SLUS819B - APRIL 2008 - REVISED SEPTEMBER 2008................................................................................................................................................ www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) ORDERABLE PART NO. TA PACKAGE -40C to +85C Plastic Quad Flatpack (32-pin QFN) (1) (2) TRANSPORT MEDIA TPS51427RHBT TPS51427RHBR Tape and Reel QUANTITY ECO STATUS (2) 250 Green (RoHs and No Sb/Br) 3000 For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Eco-Status information: Additional details including specific material content can be accessed at www.ti.com/leadfree GREEN: Ti defines Green to mean Lead (Pb)-Free and in addition, uses less package materials that do not contain halogens, including bromine (Br), or antimony (Sb) above 0.1% of total product weight. N/A: Not yet available Lead (Pb)-Free; for estimated conversion dates, go to www.ti.com/leadfree. Pb-FREE: Ti defines Lead (Pb)-Free to mean RoHS compatible, including a lead concentration that does not exceed 0.1% of total product weight, and, if designed to be soldered, suitable for use in specified lead-free soldering processes. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range; all voltages are with respect to GND (unless otherwise noted). PARAMETER 5V voltage range Input voltage range (2) VALUE V5DRV, V5FILT -0.3 to 7 VIN, ENLDO -0.3 to 30 VBST1, VBST2 -0.3 to 37 VBST1, VBST2 (w.r.t. LLx) -0.3 to 7 EN1, EN2, VOUT1, VOUT2, VFB1, REFIN2, TRIP1, TRIP2, SKIPSEL, TONSEL, VSW, LDOREFIN -0.3 to 7 TRIP1, TRIP2 Output voltage range (2) -2 to 37 DRVH1, DRVH2 (w.r.t. LLx) -0.3 to 7 LL1, LL2 -2 to 30 (1) (2) V -0.3 to 7 PGND TJ V -0.3 to (V5FILT + 0.3) DRVH1, DRVH2 DRVL1, DRVL2, VREF2, PGOOD1, PGOOD2, LDO, VREF3 Tstg UNIT -0.3 to 0.3 Storage temperature range -55 to +150 Junction temperature range +150 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted. DISSIPATION RATINGS (1) (1) 2 PACKAGE TA < +25C POWER RATING DERATING FACTOR ABOVE TA = +25C TA = +85C POWER RATING 32Ld 5 x 5 QFN 2.320 W 23.2 mW/C 0.93 W Dissipation ratings are calculated based on the usage of nine standard thermal vias and thermal pad soldered on the PCB. If thermal pad is not soldered to the PCB, the junction-to-ambient thermal resistance is 88.6C/W. Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51427 TPS51427 www.ti.com................................................................................................................................................ SLUS819B - APRIL 2008 - REVISED SEPTEMBER 2008 RECOMMENDED OPERATING CONDITIONS Over operating free-air temperature range (unless otherwise noted). MIN TYP MAX Supply input voltage range V5DRV, V5FILT 4.5 5.5 Input voltage range VBST1, VBST2 -0.1 34 VBST1, VBST2 (with regard to LLx) -0.1 5.5 EN1, EN2, VOUT1, VFB1, REFIN2, TRIP1, TRIP2, SKIPSEL, TONSEL, ENLDO,VSW, LDOREFIN -0.1 5.5 VOUT2 -0.1 3.7 DRVH1, DRVH2 -0.8 34 DRVH1, DRVH2 (w.r.t. LLx) -0.1 5.5 LL1, LL2 -0.8 28 DRVL1, DRVL2, VREF2, PGOOD1, PGOOD2, LDO, VREF3 -0.1 5.5 PGND -0.1 0.1 -40 +85 Output voltage range Operating free-air temperature, TA Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51427 UNIT V V C 3 TPS51427 SLUS819B - APRIL 2008 - REVISED SEPTEMBER 2008................................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS Over recommended free-air temperature range, VV5DRV = 5 V, VVIN = 12 V (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SUPPLIES VIN Input Voltage Range LDO in regulation 5.5 VIN Operating Supply Current LDO switched over to VSW, 4.5-V to 5.5-V SMPS VIN Standby Current 5.5 V VVIN 28 V, TA = +25C, no load, EN_LDO = 5 V, EN1 = EN2 = VSW = 0 V VIN Shutdown Current 5.5 V VVIN 28 V, TA = +25C, no load, EN_LDO = EN1 = EN2 = VSW = 0 V Quiescent Power Consumption TA = +25C, no load, EN_LDO = EN1 = EN2 = REFIN2 = 5 V, VFB1 = SKIPSEL = 0 V, VOUT1 = VSW = 5.3 V, VOUT2 = 3.5 V 28 V 5 10 A 115 150 A 12 20 A 5 7 mW PWM CONTROLLERS VOUT1 Output Voltage Accuracy 5-V Preset output: 5.5 V VVIN 28 V, VFB1 = 0 V, SKIPSEL = 5 V 4.975 (-1.5%) 5.05 5.125 (+1.5%) 1.5-V Preset output: 5.5 V VVIN 28 V, VFB1 = 5V, SKIPSEL = 5V 1.482 (-1.2%) 1.50 1.518 (+1.2%) 0.693 (-1%) 0.70 0.707 (+1%) Adjustable feedback output, 5.5 V VVIN 28 V, SKIPSEL = 5 V VOUT1 Voltage Adjust Range VFB1 Threshold Voltage VFB1 Input Current VOUT2 Output Voltage Accuracy 0.707 5-V Preset output 1.5-V Preset output DC Load Regulation V 0.20 3.285 (-1.4%) 3.33 3.375 (+1.4%) 1.05-V Preset output: REFIN2 = 3.3 V, 5.5 V VVIN 28 V, SKIPSEL= 5 V 1.038 (-1.2%) 1.05 1.062 (+1.2%) 0.99 (-1%) 1.00 1.01 (+1%) 2.50 V -0.2 0.2 A 1.05-V Preset output 3.00 3.45 3.3-V Preset output 3.90 Either SMPS, SKIPSEL = 5 V, 0 A to 5 A (1) -0.10% Either SMPS, SKIPSEL = 2 V, 0 A to 5 A (1) -2.20% Either SMPS, SKIPSEL = GND, 0 A to 5 A (1) -0.50% (1) Channel1 On-Time TONSEL = 0 V, 2 V, or OPEN (400 kHz), VOUT1 = 5.05 V 0.005 1052 1209 TONSEL = 5 V (200 kHz), VOUT1 = 5.05 V 1895 2105 2315 TONSEL = 0 V (500 kHz), VOUT2 = 3.33 V 475 555 635 TONSEL = 2 V, OPEN, or 5 V (300 kHz), VOUT2 = 3.33 V 833 925 1017 300 400 500 Soft Start Ramp Time Zero to full limit 1.8 VOUT1, VOUT2 Discharge On Resistance EN1 = EN2 = 0 V, VOUT1 = VOUT2 = 0.5 V 17 OOA Operating Frequency SKIPSEL = 2 V or OPEN 22 30 V %/V 895 Minimum Off-Time 4 V 0.50 Either SMPS, 5.5 V < VIN < 28 V (1) A 0.5 V VVREFIN2 2.5 V Line Regulation Channel2 On-Time V -0.20 REFIN2 Voltage Adjust Range REFIN2 Threshold Voltage V 0.20 3.3-V Preset output: REFIN2 = 5 V, 5.5 V VVIN 28 V, SKIPSEL = 5 V Tracking output: REFIN2 = 1.0 V, 5.5 V VVIN 28 V, SKIPSEL = 5 V REFIN2 Input Current 5.900 3.90 VFB1 = 0.8 V V ns ns ns ms 35 kHz Ensured by design. Not production tested. Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51427 TPS51427 www.ti.com................................................................................................................................................ SLUS819B - APRIL 2008 - REVISED SEPTEMBER 2008 ELECTRICAL CHARACTERISTICS (continued) Over recommended free-air temperature range, VV5DRV = 5 V, VVIN = 12 V (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX LDOREFIN = VSW = 0 V, 0 < ILDO < 10 0mA, 6 V< VIN< 28 V 4.94 (-1.7%) 5.025 5.11 (+1.7%) LDOREFIN = 5 V, VSW = 0 V, 0 < ILDO < 100 mA, 5.5 V < VIN < 28 V 3.28 (-1.5%) 3.33 3.38 (+1.5%) LDOREFIN = 0.5 V, VSW = 0 V, 0 < ILDO < 50 mA, 5.5V < VIN < 28 V 0.98 (-2%) 1.00 1.02 (+2%) UNIT LINEAR REGULATOR (LDO) LDO Output Voltage V LDOREFIN Input Range VLDO = 2 x VLDOREFIN 0.35 2.25 V LDOREFIN Leakage Current VLDOREFIN = 0 V or 5 V -0.5 0.5 A LDOREFIN Threshold Voltage Fixed LDO = 5 V 0.15 Fixed LDO = 3.3 V 3.90 LDO Output Current VSW = GND , VIN = 5.5 V to 28 V LDO Output Current During Switchover to 5 V VSW = 5 V , VIN = 5.5 V to 28 V, LDOREFIN = 0 V LDO Output Current During Switchover to 3.3 V VSW = 3.3 V , VIN = 5.5 V to 28 V, LDOREFIN = 5 V LDO Short-Circuit Current VSW = LDO = 0 V LDO 5-V Switchover Threshold Rising edge of VSW, LDOREFIN = 0 V 100 mA 340 500 mA 330 500 mA mA 140 180 220 4.63 (92.6%) 4.78 (95.6%) 4.93 (98.6%) V 3.25 (98.5%) V 1.5 Hysteresis LDO 3.3-V Switchover Threshold 0.20 Rising edge of VSW, LDOREFIN = 5 V 3.05 (92.5%) Hysteresis 3.15 (95.5%) 0.150 LDO Switchover Switch On Resistance LDO to VSW, VSW = 5 V, ILDO = 100 mA LDO Switchover Delay Turning on LDO Undervoltage Lockout Threshold Falling edge of V5FILT 3.80 3.93 4.10 Rising edge of V5FILT 4.20 4.37 4.50 VIN POR Threshold Thermal-Shutdown Threshold V 0.7 3.96 Falling edge of VIN 1.8 Rising edge of VIN 2.1 Hysteresis = +10C (2) ms V V +140 C 3.3V ALWAYS-ON LINEAR REGULATOR (VREF3) No external load, VVSW > 4.5 V 3.250 (-1.5%) 3.300 3.350 (+1.5%) No external load, VVSW < 4.0 V 3.220 (-2.4%) 3.300 3.380 (+2.4%) VREF3 Output Voltage VREF3 Load Regulation 0 mA < ILOAD < 10 mA VREF3 Current Limit VREF3 = GND VREF3 Undervoltage Lockout Threshold Falling edge of VREF3 2.96 Hysteresis 0.17 (2) 15 V 60 mV 20 mA V Ensured by design. Not production tested. Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51427 5 TPS51427 SLUS819B - APRIL 2008 - REVISED SEPTEMBER 2008................................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS (continued) Over recommended free-air temperature range, VV5DRV = 5 V, VVIN = 12 V (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX 1.98 (-1%) 2.00 2.02 (+1%) 1.975 (-1.25%) 2.00 2.025 (+1.25%) 1.700 1.825 UNIT REFERENCE (REF) |IVREF2| = 0 A VREF2 Output Voltage |IVREF2| < 50 A VREF2 Sink Current VREF2 in regulation VREF2 Undervoltage Lockout Threshold Falling edge of VREF2 A 50 1.575 Hysteresis V 0.1 V OUT1 FAULT DETECTION Overvoltage Trip Threshold VFB1 with respect to nominal regulation point Overvoltage Fault Propagation Delay VFB1 delay with 50-mV overdrive Undervoltage Trip Threshold VFB1 with respect to nominal output voltage Undervoltage Fault Propagation Delay Undervoltage Fault Enable Delay From ENx signal PGOOD1 Lower Trip Threshold VFB1 with respect to nominal output, falling edge, typical hysteresis = 5% PGOOD1 Low Propagation Delay Falling edge, 50-mV overdrive PGOOD1 High Propagation Delay Rising edge, 50-mV overdrive PGOOD1 Output Low Voltage PGOOD1 Low impedance, ISINK = 4 mA Out-Of-Bound Threshold VFB1 with respect to nominal output voltage PGOOD1 Leakage Current PGOOD1 High impedance, forced to 5.5 V +12.5% +15% +17.5% s 10 -35% -30% -25% 0.8 1 1.2 ms 10 20 30 ms -12.5% -10% -7.5% 0.8 1.0 1.2 ms 0.4 0.8 V 1 A s 10 +5% OUT2 FAULT DETECTION Overvoltage Trip Threshold REFIN2 with respect to nominal regulation point Overvoltage Fault Propagation Delay REFIN2 delay with 50-mV overdrive Undervoltage Trip Threshold REFIN2 with respect to nominal output voltage Undervoltage Fault Propagation Delay Undervoltage Fault Enable Delay From ENx signal PGOOD2 Lower Trip Threshold REFIN2 with respect to nominal output, falling edge, typical hysteresis = 5% Out-Of-Bound Threshold REFIN2 with respect to nominal output voltage PGOOD2 Low Propagation Delay Falling edge, 50-mV overdrive PGOOD2 High Propagation Delay Rising edge, 50-mV overdrive PGOOD2 Output Low Voltage PGOOD2 Low impedance, ISINK = 4 mA PGOOD2 Leakage Current PGOOD2 High impedance, forced to 5.5 V 6 Submit Documentation Feedback +12.5% +15.0% +17.5% s 10 -35% -30% -25% 0.8 1 1.2 ms 10 20 30 ms -12.5% -10% -7.5% +5% s 10 0.8 1.0 1.2 ms 0.4 0.8 V 1 A Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51427 TPS51427 www.ti.com................................................................................................................................................ SLUS819B - APRIL 2008 - REVISED SEPTEMBER 2008 ELECTRICAL CHARACTERISTICS (continued) Over recommended free-air temperature range, VV5DRV = 5 V, VVIN = 12 V (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CURRENT LIMIT TRIPx Adjustment Range 0.2 4.75 (-5%) TRIPx Source Current 0.2 V < VTRIPx < 2 V, TA = +25C TRIPx Current Temperature Coefficient on the basis of TA = +25C (3) 5 2.0 V 5.25 (+5%) A 2900 ppm/C GND - LLx, VTRIPx = 0.2 V 13 (-35%) 20 27 (+35%) GND - LLx, VTRIPx = 0.5 V 42.5 (-15%) 50 57.5 (+15%) GND - LLx, VTRIPx = 1 V 93 (-7%) 100 107 (+7%) GND - LLx, VTRIPx = 2 V 190 (-5%) 200 210 (+5%) Current-Limit Threshold (Positive, Default) VTRIPx = 5.0 V, GND - LLx (no temperature compensation) 93 (-7%) 100 107 (+7%) Fixed 100-mV OCL TRIPx Threshold Voltage High threshold 3.0 3.2 3.3 V Hysteresis 40 70 100 mV 0 3.5 mV Source, VBSTx-DRVHx = 0.1 V 1.0 3.6 Sink, DRVHx-LLx = 0.1 V 0.8 2.6 Source, V5DRV-DRVLx = 0.1 V 1.2 4.0 Sink, DRVLx-PGND = 0.1 V 0.6 1.5 Current-Limit Threshold (Positive, Adjustable) Current Limit Threshold (Negative) With respect to valley current limit threshold, SKIPSEL = 5 V Zero-Crossing Current Limit Threshold SKIPSEL = 0 V, 2 V, or OPEN, GND - LLx mV mV -100% -3.5 GATE DRIVERS DRVHx Gate-Driver On-Resistance DRVLx Gate-Driver On-Resistance DRVHx Gate-Driver Source Current VBSTx-LLx = 5 V, DRVHx = 2.0 V (3) 1.8 A (3) 1.6 A DRVHx Gate-Driver Sink Current VBSTx-LLx = 5 V, DRVHx = 2.0 V DRVLx Gate-Driver Source Current V5DRV-PGND = 5 V, DRVLx = 2.0 V (3) 1.4 A (3) 2.6 A DRVLx Gate-Driver Sink Current Dead Time V5DRV-PGND = 5 V, DRVLx = 2.0 V DRVHx low (DRVHx = 1 V) to DRVLx high (DRVLx = 4 V), LLx = -0.05 V 20 30 50 ns DRVLx low (DRVLx = 1 V) to DRVHx high (DRVHx = 4 V), LLx = -0.05 V 25 40 60 ns Internal BST_ Switch On-Resistance IVBSTx = 10 mA, V5DRV = 5 V, TA = +25C VBSTx Leakage Current VVBSTx = 35 V, LLx = 28 V (3) 10 0.01 2.0 A Ensured by design. Not production tested. Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51427 7 TPS51427 SLUS819B - APRIL 2008 - REVISED SEPTEMBER 2008................................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS (continued) Over recommended free-air temperature range, VV5DRV = 5 V, VVIN = 12 V (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 2.25 V INPUTS AND OUTPUTS TONSEL Input Logic Levels High level 2.9 Float level 1.85 Low level 0.45 High threshold (PWM Only) SKIPSEL Input Logic Levels Float level (OOA) 2.9 1.85 2.25 Low level (Auto Skip) SKIPSEL, TONSEL Input Current EN1, EN2 Input Logic Levels SKIPSEL = TONSEL = 0 V 2.5 SMPS On level 2.9 Delay start level 1.85 4.0 SMPS Off level EN1, EN2 Leakage Current EN_LDO Input Logic Levels EN_LDO Input Current 8 V 0.45 5.5 A 2.25 V 0.45 EN1 = EN2 = 0 V Rising edge -0.1 1.3 Hysteresis 0.1 1.65 1.9 0.6 EN_LDO = 0 V 0.7 1.0 1.3 EN_LDO = 30 V -0.1 0 0.1 Submit Documentation Feedback A V A Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51427 TPS51427 www.ti.com................................................................................................................................................ SLUS819B - APRIL 2008 - REVISED SEPTEMBER 2008 DEVICE INFORMATION TERMINAL FUNCTIONS TERMINAL NAME NO. DRVH1 15 DRVH2 26 DRVL1 18 DRVL2 23 EN1 14 EN2 27 EN_LDO I/O DESCRIPTION O High-side N-Channel FET driver outputs. LL referenced floating drivers. The gate drive voltage is defined by the voltage across VBST to LL node bootstrap capacitor. O Synchronous low-side MOSFET driver outputs. Ground referenced drivers. The gate drive voltage is defined by V5DRV voltage. I Channel enable pins. If EN1 is connected to VREF2, Channel1 starts after Channel2 reaches regulation (delay start). If EN2 is connected to VREF2, Channel2 starts after Chanel1 reaches regulation. 4 I LDO Enable Input. The LDO is enabled if EN_LDO is within logic high level and disabled if EN_LDO is less than the logic low level. GND 21 I Analog ground for both channels and LDO. LL1 16 LL2 25 I/O Phase node connections for high-side drivers. These connections also serve as inputs to current comparators for RDS(on) sensing and input voltage monitor for on-time control circuitry. LDO 7 O Linear regulator output. The LDO regulator can provide a total of 100-mA external loads. The LDO regulates at 5 V If LDOREFIN is connected to GND. When the LDO is set at 5 V and VSW is within a 5-V switchover threshold, the internal regulator shuts down and the LDO output pin connects to VSW through a 0.7- switch. The LDO regulates at 3.3 V if LDOREFIN is connected to V5FILT. When the LDO is set at 3.3 V and VSW is within a 3.3-V switchover threshold, the internal regulator shuts down and the LDO output pin connects to VSW through a 0.7- switch. Bypass the LDO output with a minimum of 4.7-F ceramic capacitance. LDOREFIN 8 I LDO Reference Input. Connect LDOREFIN to GND for fixed 5-V operation. Connect LDOREFIN to V5FILT for fixed 3.3-V operation. LDOREFIN can be used to program LDO output voltage from 0.7 V to 4.5 V. LDO output is twice the voltage of LDOREFIN. There is no switchover in adjustable mode. PGND 22 I Ground pin for drivers and LS synchronous FET source terminals. This pin is also the input to zero crossing comparator and overcurrent comparator. PGOOD1 13 O Channel1/Channel2 power-good open-drain output. PGOOD1/PGOOD2 is low when the Channel1/Channel2 output voltage is 10% less than the normal regulation point, at onset of OVP events, or during soft start. PGOOD1/PGOOD2 is high impedance when the output is in regulation and the soft-start circuit has terminated. PGOOD1/PGOOD2 is low in shutdown. Output voltage control for Channel2. Connect REFIN2 to V5FILT for fixed 3.3-V operation. Connect REFIN2 to VREF3 for fixed 1.05-V operation. REFIN2 can be used to program Channel2 output voltage from 0.5 V to 2.5 V. PGOOD2 28 REFIN2 32 I NC 20 - SKIPSEL 29 I Low-noise mode control. Connect SKIPSEL to GND for Auto Skip mode operation or to V5FILT for PWM mode (fixed frequency). Connect to VREF2 or leave floating for OOATM mode operation. TONSEL 2 I Frequency select input. Connect to GND for 400-kHz/500-kHz operation. Connect to VREF2 (or leave open) for 400-kHz/300-kHz operation. Connect to V5FILT for 200-kHz/300-kHz operation (5-V/3.3-V SMPS switching frequencies, respectively). TRIP1 12 TRIP2 31 I Overcurrent trip point set input. Sourcing current is 5 A at RT with 2900 ppm/C temperature coefficient. V5DRV 19 I Supply voltage for the low-side MOSFET driver DRVL1/DRVL2. Connect a 5-V power source to the V5DRV pin (bypass with 4.7-F MLCC capacitor to PGND if necessary). V5FILT 3 I 5-V analog supply input. VFB1 11 I Channel1 feedback input. Connect VFB1 to GND for fixed 5-V operation. Connect VFB1 to V5FILT for fixed 1.5-V operation. Connect VFB1 to a resistive voltage divider from OUT1 to GND to adjust the output from 0.7 V to 5.9 V. VBST1 17 VBST2 24 I Supply input for high-side MOSFET driver (bootstrap terminal). Connect a capacitor from this pin to the respective LL terminals. VIN 6 I Power supply input. VIN supplies power to the linear regulators. The linear regulators are powered by Channel1 if VOUT1 is set greater than 5 V and VSW is tied to VOUT1. VOUT1 10 VOUT2 30 O Output connections to SMPS. These terminals serve two functions: on-time adjustment and output discharge. VREF2 1 O 2-V reference output. Bypass to GND with a 0.1-F capacitor. VREF2 can source up to 50 A for external loads. VREF3 5 O 3.3-V reference output. VREF3 can source up to 10 mA for external loads. Bypass to GND with a 1-F capacitor. VSW 9 I VSW is the switchover source voltage for the LDO when LDOREFIN is connected to GND or V5FILT. Connect VSW to 5 V if LDOREFIN is tied GND. Connect VSW to 3.3 V if LDOREFIN is tied to V5FILT. Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51427 9 TPS51427 SLUS819B - APRIL 2008 - REVISED SEPTEMBER 2008................................................................................................................................................ www.ti.com QFN-32, 5-mm x 5-mm (TOP VIEW) LL2 DVRH2 EN2 PGOOD2 SKIPSEL VOUT2 TRIP2 REFIN2 RHB PACKAGE (TOP VIEW) 32 31 30 29 28 27 26 25 24 VREF2 1 TONSEL 2 23 DRVL2 V5FILT 3 22 PGND EN_LDO 4 21 GND VREF3 5 20 NC VIN 6 19 V5DRV LDO 7 18 DRVL1 LDOREFIN 8 17 10 11 12 13 14 15 16 VBST1 LL1 DRVH1 EN1 PGOOD1 TRIP1 VFB1 VSW 9 VOUT1 TPS51427 VBST2 NC = No connection. 10 Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51427 TPS51427 www.ti.com................................................................................................................................................ SLUS819B - APRIL 2008 - REVISED SEPTEMBER 2008 FUNCTIONAL BLOCK DIAGRAMS 140C /125C Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51427 11 TPS51427 SLUS819B - APRIL 2008 - REVISED SEPTEMBER 2008................................................................................................................................................ www.ti.com DETAILED DESCRIPTION BASIC PWM OPERATION The main control loop of the TPS51427 is designed as an adaptive on-time pulse width modulation (PWM) controller. It supports a proprietary D-CAPTM mode that uses internal compensation circuitry and is suitable for a minimal external component count configuration when an appropriate amount of ESR at the output capacitor(s) is allowed. D-CAP mode can also enable stable operation when using capacitors with low ESR, such as specialty polymer capacitors. The basic operation of D-CAP mode can be described in this way: At the beginning of each cycle, the synchronous high-side MOSFET turns on or goes to an ON state. This MOSFET turns off, or returns to an OFF state, after an internal one-shot timer expires. The one-shot timer is determined by VIN and VOUT and keeps the frequency fairly constant over the input voltage range under steady-state conditions; it is an adaptive on-time control or fixed-frequency emulated on-time control. The MOSFET turns on again when the following two conditions occur: * Feedback information, monitored at the VFB1/VOUT2 voltage, indicates insufficient output voltage; and * the inductor current information indicates that current is below the overcurrent limit. Operating in this manner, the controller regulates the output voltage. The synchronous low-side or the rectifying MOSFET is turned on each OFF state to keep the conduction loss minimum. LIGHT LOAD CONDITIONS The TPS51427 supports three selectable operating modes: PWM-only, Out-Of-Audio (OOATM), and Auto-Skip. If the SKIPSEL pin is connected to GND, Auto-Skip mode is selected. This mode enables a seamless transition to the reduced frequency operation under light load conditions so that high efficiency is maintained over a wide range of load current. This frequency reduction is achieved smoothly and without an increase in VOUT ripple or load regulation. Auto-Skip operation can be described in this way: As the output current decreases from a heavy load condition, the inductor current is also reduced. Eventually, the inductor current reaches the point that its valley equals zero current; that is, the boundary between continuous conduction and discontinuous conduction modes. The rectifying MOSFET turns off when this zero inductor current is detected. Because the output voltage remains higher than the reference voltage at this point, both high-side and low-side MOSFETs are turned off and wait for the next cycle. As the load current decreases further, the converter runs in discontinuous conduction mode and takes longer to discharge the output capacitor below the reference voltage. Note that the ON time remains the same as that in the heavy load condition. On the other hand, when the output current increases from a light load to a heavy load, the switching frequency increases to the preset value as the inductor current reaches the continuous conduction limit. The transition load point to the light load operation IOUT(LL) (that is, the threshold between continuous conduction and discontinuous conduction mode) can be calculated as shown in Equation 1: ae 1 IOUT(LL) = c 2 L f SW e o ae (VVIN - VVOUT ) VVOUT / cc VVIN o e o / / o (1) Where fSW is the PWM switching frequency. Switching frequency versus output current under a light load condition is a function of L, fSW, VIN, and VOUT, but decreases at a near-proportional rate to the output current from the IOUT(LL) threshold. For example, the frequency is approximately 60 kHz at IOUT(LL)/5 if the PWM switching frequency is 300 kHz. PWM-only mode is selected if the SKIPSEL pin is connected to 5 V. The rectifying MOSFET does not turn off when the inductor current reaches zero. The converter runs in forced continuous conduction mode over the entire load range. System designers may want to use this mode to avoid certain frequencies under light load conditions but do so at the cost of lower efficiency. However, keep in mind that the output has the capability to both source and sink current in this mode. If the output terminal is connected to a voltage source that is higher than the regulator target value, the converter sinks current from the output and boosts the charge into the input capacitors. This operation may cause an unexpected high voltage at VIN and may damage the power FETs. If SKIPSEL pin is connected to VREF2 or left floating, OOA mode operation is selected. 12 Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51427 TPS51427 www.ti.com................................................................................................................................................ SLUS819B - APRIL 2008 - REVISED SEPTEMBER 2008 Table 1. SKIPSEL Operating Modes SKIPSEL GND FLOAT/VREF2 V5IN Operating Mode Auto Skip OOATM PWM Only OUT-OF-AUDIO (OOATM) OPERATION If out-of-audio (OOA) operation is enabled, the switching frequency of the channel remains higher than the audible frequency under any load condition, at a minimum of 22 kHz to minimize the audible noise in the system. The TPS51427 automatically reduces switching frequencies under light load conditions. The OOA control circuit monitors the switching period and forces the high-side MOSFET to turn on if the switching frequency goes below the 22-kHz threshold. The high-side MOSFET turns on even if the output voltage is higher than the target value; therefore, the output voltage tends to be higher when operating in OOA mode. The OOA control circuit detects the overvoltage condition and prevents the voltage from rising by re-modulating the device on time. The overvoltage condition is detected by the VFB1/VOUT2 voltages. The inductor current ripple (peak-to-peak) should be less than two-thirds of the OCL setting for the OOA circuit to work properly at a 0-A load. To keep the OOA mode loop stable, the output voltage ripple cannot be too large. If OOA mode operation is desired, the recommended output ripple voltage cannot be more than 1% of the target dc voltage. RAMP COMPENSATION The TPS51427 employs an advanced ramp compensation technique in D-CAP mode to optimize jitter performance. An internal ramp signal is added to the reference voltage to virtually increase the slope of the VFB1/VOUT2 down ramp, which the PWM comparator uses to determine the turn-on timing. LOW-SIDE DRIVER The low-side driver is designed to drive high-current, low RDS(on), N-channel MOSFET(s). The drive capability is represented by its internal resistance: 1.2 for V5DRV to DRVLx and 0.6 for DRVLx to PGND. A dead time to prevent shoot-through is generated internally between the two transistors, with the top MOSFET off and bottom MOSFET on, and then with the bottom MOSFET off and the top MOSFET on. A 5-V bias voltage is delivered from the V5DRV supply. The instantaneous drive current is supplied by an input capacitor connected between V5DRV and GND. The average drive current is equal to the gate charge at VGS = 5 V times the switching frequency. HIGH-SIDE DRIVER The high-side driver is also designed to drive high-current, low RDS(on), N-channel MOSFET(s). When configured as a floating driver, a 5-V bias voltage is delivered from the V5DRV supply. The average drive current is also calculated by the gate charge at VGS = 5 V times the switching frequency. The instantaneous drive current is supplied by the floating capacitor between the VBSTx and LLx pins. The drive capability is represented by its internal resistance: 1.0 for VBSTx to DRVHx and 0.8 for DRVHx to LLx. BOOSTRAP CHARGE AUTO REFRESH Boost undervoltage protection is activated during the device ON time when the voltage difference between DRVH and LL becomes less than 1.8 V. Upon detection of the undervoltage condition, the high-side gate driver immediately turns off and the low-side gate driver turns on after the deadtime expires for the minimum off time in an attempt to recharge the boost capacitor. PWM FREQUENCY AND ADAPTIVE ON-TIME CONTROL The TPS51427 employs an adaptive on-time control scheme and does not have a dedicated onboard oscillator. However, the device runs with pseudo-constant frequency by feed-forwarding the input voltage and output voltage into the on-time one-shot timer. The frequencies are set by the TONSEL terminal connection as Table 2 shows. The on-time is controlled: it is inversely proportional to the input voltage and proportional to the output voltage, so that the duty ratio maintains technically as VOUT/VIN with the same cycle time. Although the TPS51427 does not use VIN directly, the input voltage is monitored at the LLx pin during the ON state. Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51427 13 TPS51427 SLUS819B - APRIL 2008 - REVISED SEPTEMBER 2008................................................................................................................................................ www.ti.com Table 2. TONSEL Terminal Connection Options TONSEL GND VREF2 or Float V5FILT Channel1 Frequency 400 kHz 400 kHz 200 kHz Channel2 Frequency 500 kHz 300 kHz 300 kHz ENABLE AND SOFT START TPS51427 has an internal digital soft-start timer that begins to ramp up to the maximum allowed current limit during device startup. The soft-start ramp occurs in five steps of positive current limit; step sizes are 20%, 40%, 60%, 80%, and 100%. Smooth control of the output voltage during device startup is maintained. In addition, if tracking discharge is required, the ENx pin can be used to control the output voltage discharge smoothly. At the beginning of the soft-start period, the rectifying MOSFET maintains an off state until the top MOSFET turns on at least once. This architecture prevents a high negative current from flowing back from the output capacitor in the event of an output capacitor pre-charged condition. If EN1 is connected to VREF2, Channel1 starts up after the Channel2 reaches regulation (delay start). If EN2 is connected to VREF2, Channel2 starts up after the Channel1 reaches regulation (delay start). When both ENx are low and ENLDO is low, the TPS51427 enters a shutdown state and consumes less than 15 A. POWER-GOOD AND OUT-OF-BOUND OPERATION The TPS51427 has a power-good output (PGOODx) for each switching channel. The power-good function activates after the soft start finishes. If the output voltage reaches within 95% of the target value, internal comparators detect a power-good state and the power-good signal goes high after a 1-ms internal delay. If the output voltage falls below 90% of the target value, the power-good signal goes low after a 10-s internal delay. When the output voltage exceeds +5% above of the target value while SKIPSEL is selected as auto-skip or OOA skip-mode, the out-of-bound operation starts. During the out-of-bound condition, the controller operates in forced PWM-only mode. Turning on the low-side MOSFET beyond the zero inductor current quickly discharges the output capacitor. During this operation, the cycle-by-cycle negative overcurrent limit is also valid. Once the output voltage becomes back within regulation range, the controller resumes to auto-skip or OOA skip mode." OUTPUT SHUTDOWN AND DISCHARGE CONTROL The TPS51427 discharges the output when ENx is low, or when the controller is shut down by the circuit protection functions (OVP, UVP, UVLO, and thermal shutdown). The TPS51427 discharges the outputs using an internal, 17- MOSFET that is connected to VOUTx and PGND. The external low-side MOSFET does not turn on during the output discharge operation to avoid the possibility of causing a negative voltage at the output. The output discharge time constant is a function of the output capacitance and the resistance of the internal discharge MOSFET. This discharge ensures that on device restart, the regulated voltage always starts from 0 V. If an SMPS restarts before the discharge completes, the discharge action is terminated and switching resumes after the reference level (ramped up by an internal digital-to-analog converter, or DAC) returns to the remaining output voltage. When shutdown mode activates, the 3.3-V VREF3 remains on. 2-V REFERENCE (VREF2) The 2-V reference is useful for generating auxiliary voltages. The tolerance for this reference voltage is 1.25% over a 50-A load and -40C to +85C ambient temperature range. This reference is enabled when ENLDO goes high, and shuts down after both switching channels are turned off and ENLDO is shut down. If this output is forcibly tied to ground, both SMPSs are turned off without a latch. Bypass the VREF2 pin to GND with a minimum 0.1-F ceramic capacitor. 3-V REFERENCE (VREF3) The 3.3-V reference (VREF3) is accurate to 1.5% over temperature, making VREF3 useful as a precision system reference for the real-time clock (RTC) circuit in many notebook applications. VREF3 can supply up to 10 mA for external loads. Bypass VREF3 to GND with a 1-F capacitor. VREF3 is activated when VIN rises above 2.1 V, and remains on even when the SMPS and LDO are both shut down. VREF3 is deactivated if VIN falls below 1.8 V. In thermal shutdown conditions, VREF3 remains activate. 14 Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51427 TPS51427 www.ti.com................................................................................................................................................ SLUS819B - APRIL 2008 - REVISED SEPTEMBER 2008 LDO When the LDOREFIN pin is connected to GND, the TPS51427 internal linear regulator produces a fixed 5-V LDO output; when LDOREFIN is connected to V5FILT, the linear regulator produces a fixed 3.3-V LDO output. The LDO regulator can supply up to 100 mA for external loads. Bypass the LDO with a minimum 4.7-F ceramic capacitor. When the LDO is fixed at 5 V, and VSW voltage is equal to or greater than 4.7 V, the 5 V LDO switches off after a 3.8-ms delay, and the 5V rail is bootstrapped to the VSW output, thereby improving the efficiency of the converter. A glitch-free switchover is also accomplished. The switchover impedance from the VSW pin to the LDO pin is typically 0.7 . In the same way, when the LDO is fixed at 3.3-V and the VSW voltage is equal to or greater than 3.15 V, the 3.3-V LDO switches off after a delay of 4 ms, and the 3.3-V rail is bootstrapped to the VSW output. In adjustable mode, the LDO output can be set from 0.7 V to 4.5 V. The LDO output voltage is equal to two times the LDOREFIN voltage. There is no switchover action in adjustable mode. For the 5-V LDO output, a 4.7-F ceramic capacitor (minimum) is required from the LDO to GND. For the 3.3-V LDO output, a 10-F ceramic capacitor (minimum) is required from the LDO to GND. If a lower voltage LDO output is desired, scale the output capacitance of the LDO according to Equation 2. CLDO(min ) = 5V 4.7 mF V LDO (2) For example, if VLDO = 1 V, CLDO(min) = 23.5 F. Use the standard capacitance value to choose 27 F for the 1-V LDO output. CURRENT SENSING AND OVERCURRENT PROTECTION In order to provide the most cost-effective solution, the TPS51427 supports low-side MOSFET RDS(on) sensing for overcurrent protection. In any setting, the output signal of the current amplifier becomes 100 mV at the overcurrent limit (OCL) set point. This configuration means that the current sensing amplifier normalizes the current information signal based on the OCL setting. The TPS51427 supports cycle-by-cycle OCL control. The controller does not allow the next ON cycle while the current level is above the trip threshold. The overcurrent trip threshold voltage is determined by the TRIPx pin as Table 3 shows. The TRIPx terminal sources 5-A current with a 2900ppm/C temperature slope, with respect to its +25C value, to compensate the temperature dependency of the MOS RDS(on). The trip level is set to the voltage across RTRIPx when TRIPx is between 200 mV and 2 V at room temperature. When the TRIPx pin is tied to 5 V directly, the controller defaults to 100 mV fixed OCL setting. With this option, temperature compensation is not obtained. Table 3. Overcurrent Trip Threshold Voltage TRIPx 0.2 V to 2 V 5V OCL threshold in RDS(on) sensing 20 mV to 200 mV 100 mV Temperature Coefficient (ppm/C) 2900 None The overcurrent condition is detected during the OFF state; therefore, ITRIP sets the valley level of the inductor current. Thus, the load current at overcurrent threshold, IOCP, can be calculated in Equation 3. aeI IOCP = ITRIP + c RIPPLE 2 e 1 o ae / = ITRIP + c f 2 L e o o ae (VVIN - VVOUT ) VVOUT / cc VVIN o e o / / o (3) Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51427 15 TPS51427 SLUS819B - APRIL 2008 - REVISED SEPTEMBER 2008................................................................................................................................................ www.ti.com In an overcurrent condition, the current to the load exceeds the current to the output capacitor. As a result, the output voltage tends to drop, and ends up crossing the undervoltage protection threshold, and the device shuts down. The TPS51427 also supports a cycle-by-cycle negative overcurrent limit in PWM-only mode. The negative overcurrent limit is set to be negative, but at the same absolute value as the positive overcurrent limit. If the output voltage continues to rise, the bottom MOSFET is always on; the inductor current reduces and reverse direction after it reaches zero. When there is too much negative current in the inductor, the bottom MOSFET turns off and a new on-time period is initiated; that is, the top MOSEFET turns on to allow current to flow into VIN. After the on-time expires, the bottom MOSFET turns on again. This protection ensures a maximum allowable discharge capability when the output voltage continues to rise, effectively reducing the possibility of the overvoltage protection (OVP) circuitry. OVERVOLTAGE/UNDERVOLTAGE PROTECTION The TPS51427 monitors the feedback voltage for Channel1 and output voltage for Channel2 to detect both overand undervoltage conditions. When the output voltage becomes 15% higher than the target value, the OVP comparator output goes high after a 10-s propagation delay; the circuit then latches the top MOSFET driver off and the bottom MOSFET driver on, until the negative OCL limit is reached. At that time, the bottom MOSFET turns off and the top MOSFET turns on for the minimum on-time. Once the minimum on-time expires, the bottom MOSFET turns on again. This process repeats until the valley current of the inductor is above the negative overcurrent limit. Once the inductor valley current is greater than the OCL, the bottom MOSFET remains on until it is reset. Upon OVP activation, both PGOODx outputs are pulled low. When the voltage becomes lower than 70% of the target voltage, the undervoltage protection (UVP) comparator output goes high and an internal UVP delay counter begins counting. After 1 ms, the TPS51427 latches both top and bottom MOSFETs off and shuts off the other channel as well. This function is enabled after the device soft start completes. UNDERVOLTATGE LOCKOUT (UVLO) PROTECTION The TPS51427 has V5FILT undervoltage lockout (UVLO) protection. When the V5FILT voltage is lower than the UVLO threshold voltage, the TPS51427 shuts off. This feature is a non-latched protection circuit. THERMAL SHUTDOWN The TPS51427 monitors the temperature of the die itself. If the temperature exceeds the threshold value (typically +140C), the TPS51427 shuts down. This feature is a non-latched protection circuit. 16 Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51427 TPS51427 www.ti.com................................................................................................................................................ SLUS819B - APRIL 2008 - REVISED SEPTEMBER 2008 TYPICAL CHARACTERISTICS SYSTEM DUAL RAILS EFFICIENCY vs OUTPUT CURRENT 100 100 80 80 h - Efficiency - % h - Efficiency - % EFFICIENCY vs OUTPUT CURRENT 60 40 60 40 VIN (V) 20 0 0.001 CH1 Auto-Skip Mode VTONSEL = V5FILT 0.01 VIN (V) 8 12 20 0.1 1 20 CH2 Auto-Skip Mode VTONSEL = V5FILT 0 0.001 10 0.01 8 12 20 0.1 1 IOUT - Output Current - A IOUT - Output Current - A Figure 1. 5-V Efficiency in Auto-Skip Mode Figure 2. 3.3-V Efficiency in Auto-Skip Mode EFFICIENCY vs OUTPUT CURRENT 10 EFFICIENCY vs OUTPUT CURRENT 100 100 VIN (V) 80 h - Efficiency - % h - Efficiency - % 80 60 40 20 0 0.001 8 12 20 60 40 VIN (V) CH1 OOA Mode VTONSEL = V5FILT 8 12 20 0.01 0.1 1 IOUT - Output Current - A CH2 OOA Mode VTONSEL = V5FILT 20 10 0 0.001 0.01 0.1 1 10 IOUT - Output Current - A Figure 3. 5-V Efficiency in OOA Mode Figure 4. 3.3-V Efficiency in OOA Mode Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51427 17 TPS51427 SLUS819B - APRIL 2008 - REVISED SEPTEMBER 2008................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) EFFICIENCY vs OUTPUT CURRENT EFFICIENCY vs OUTPUT CURRENT 100 100 CH1 PWM Mode VTONSEL = V5FILT 80 h - Efficiency - % h - Efficiency - % 80 60 40 VIN (V) 20 0.01 0.1 1 IOUT - Output Current - A 60 40 VIN (V) 20 8 12 20 0 0.001 CH2 PWM Mode VTONSEL = V5FILT 8 12 20 0 0.001 10 Figure 5. 5-V Efficiency in PWM Mode 3.42 5.13 3.40 5.12 3.38 VOUT - Output Voltage - V VOUT - Output Voltage - V OUTPUT VOLTAGE vs INPUT VOLTAGE OOA, 0 A 5.11 Auto-skip, 0A 5.10 5.09 PWM Only, 0 A 5.08 5.07 OOA, 8 A 5.06 5.05 Auto-skip, 0A OOA, 0 A 3.36 3.34 OOA, 8 A Auto-skip, 8 A 3.32 PWM Only, 8 A 3.30 Mode, IOUT (A) 3.28 Auto-skip, 8 A Auto-skip, 0A OOA, 8 A OOA, 0 A PWM Only, 8A PWM Only, 0A 3.26 3.24 OOA, 8 A Auto-skip, 8 A 5.04 3.22 PWM Only, 8 A 3.20 5.03 5 10 15 20 25 5 10 15 20 25 VIN - Input Voltage - V VIN - Input Voltage - V Figure 7. 5-V Line Regulation 18 10 Figure 6. 3.3-V Efficiency in PWM Mode OUTPUT VOLTAGE vs INPUT VOLTAGE 5.14 0.01 0.1 1 IOUT - Output Current - A Submit Documentation Feedback Figure 8. 3.3-V Line Regulation Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51427 TPS51427 www.ti.com................................................................................................................................................ SLUS819B - APRIL 2008 - REVISED SEPTEMBER 2008 TYPICAL CHARACTERISTICS (continued) OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs OUTPUT CURRENT 5.18 3.42 CH1 VIN = 12 V VTONSEL = V5FILT OOA 5.16 5.12 Auto-Skip 5.10 5.08 5.06 5.04 5.02 5.00 4.98 0.001 0.01 Auto-Skip 3.36 3.34 3.32 PWM Only 3.30 3.28 PWM Only Mode OOA Auto-Skip PWM Only CH2 VIN = 12 V VTONSEL = V5FILT 3.38 VOUT - Output Voltage - V VOUT - Output Voltage - V 5.14 OOA 3.40 Mode OOA Auto-Skip PWM Only 3.26 0.1 1 3.24 0.001 10 IOUT - Output Current - mA 0.01 0.1 1 10 IOUT - Output Current - mA Figure 9. 5-V Load Regulation Figure 10. 3.3-V Load Regulation LOW VOLTAGE DUAL RAILS EFFICIENCY vs OUTPUT CURRENT 100 100 90 90 80 80 70 70 h - Efficiency - % h - Efficiency - % EFFICIENCY vs OUTPUT CURRENT 60 50 40 10 0 0.001 50 40 30 30 20 60 VIN (V) CH1 Auto-Skip Mode VTONSEL = GND VIN (V) 20 8 12 20 0.01 0.1 1 IOUT - Output Current - A 10 10 Figure 11. 1.5-V Efficiency in Auto-Skip mode CH2 Auto-Skip Mode VTONSEL = GND 0 0.001 8 12 20 0.01 0.1 1 IOUT - Output Current - A 10 Figure 12. 1.05-V Efficiency in Auto-Skip Mode Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51427 19 TPS51427 SLUS819B - APRIL 2008 - REVISED SEPTEMBER 2008................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) EFFICIENCY vs OUTPUT CURRENT EFFICIENCY vs OUTPUT CURRENT 100 100 90 80 CH1 OOA Mode VTONSEL = GND 80 h - Efficiency - % h - Efficiency - % 70 60 50 40 60 40 30 VIN (V) 20 8 12 20 10 0 0.001 VIN (V) 0.01 0.1 1 IOUT - Output Current - A 20 CH2 Auto-Skip Mode VTONSEL = GND 0 0.001 10 0.01 0.1 1 IOUT - Output Current - A Figure 13. 1.5-V Efficiency in OOA mode EFFICIENCY vs OUTPUT CURRENT 100 CH1 PWM Mode VTONSEL = GND 80 h - Efficiency - % h - Efficiency - % 100 60 40 VIN (V) 20 0 0.001 0.01 0.1 1 IOUT - Output Current - A CH2 PWM Mode VTONSEL = GND 60 40 VIN (V) 20 8 12 20 10 Figure 15. 1.5-V Efficiency in PWM mode 20 10 Figure 14. 1.05-V Efficiency in OOA mode EFFICIENCY vs OUTPUT CURRENT 80 8 12 20 8 12 20 0 0.001 0.01 0.1 1 IOUT - Output Current - A 10 Figure 16. 1.05-V Efficiency in PWM mode Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51427 TPS51427 www.ti.com................................................................................................................................................ SLUS819B - APRIL 2008 - REVISED SEPTEMBER 2008 TYPICAL CHARACTERISTICS (continued) OUTPUT VOLTAGE vs INPUT VOLTAGE 1.530 OUTPUT VOLTAGE vs INPUT VOLTAGE 1.080 OOA, 0 A 1.075 PWM Only, 0 A VOUT - Output Voltage - V VOUT - Output Voltage - V 1.525 1.520 Auto-skip, 0A 1.515 1.510 Mode, IOUT (A) Auto-skip, 8 A Auto-skip, 0A OOA, 8 A OOA, 0 A PWM Only, 8A PWM Only, 0A 1.505 OOA, 8 A Auto-skip, 8 A PWM Only, 8 A 1.500 1.070 1.065 Mode, IOUT (A) 1.060 Auto-skip, 10 A Auto-skip, 0A OOA, 10 A OOA, 0 A PWM Only, 10A PWM Only, 0A 1.055 1.495 1.050 5 10 15 20 25 5 10 VIN - Input Voltage - V OUTPUT VOLTAGE vs OUTPUT CURRENT 1.076 1.530 OOA CH1 VIN = 12 V VTONSEL = GND 1.072 Auto-Skip 1.515 1.500 0.001 PWM Only Mode OOA Auto-Skip PWM Only 0.01 CH2 VIN = 12 V VTONSEL = GND 1.074 VOUT - Output Voltage - V VOUT - Output Voltage - V 1.525 1.505 25 Figure 18. 1.05-V Line Regulation OUTPUT VOLTAGE vs OUTPUT CURRENT 1.510 20 VIN - Input Voltage - V Figure 17. 1.5-V Line Regulation 1.520 15 1.070 PWM Only 1.066 1.064 1.062 1.060 Auto-Skip 1.058 Mode OOA Auto-Skip PWM Only 1.056 0.1 1 10 OOA 1.068 1.054 0.001 0.01 0.1 1 10 IOUT - Output Current - mA IOUT - Output Current - A Figure 19. 1.5-V Load Regulation Figure 20. 1.05-V Load Regulation Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51427 21 TPS51427 SLUS819B - APRIL 2008 - REVISED SEPTEMBER 2008................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs OUTPUT CURRENT 4.0 5.5 VIN = 12 V VIN = 6 V VOUT - Output Voltage - V VOUT - Output Voltage - V 5.0 VIN = 6 V 4.5 VIN = 25 V 4.0 VIN (V) 3.5 3.5 3.0 VIN = 25 V 2.5 VIN = 12 V VIN (V) 6 12 25 6 12 25 3.0 2.0 0 50 100 200 150 0 50 IOUT - Output Current - mA Figure 21. 5-V LDO Load Regulation OUTPUT VOLTAGE vs OUTPUT CURRENT 2.000 3.310 VIN (V) VIN (V) 1.999 6 12 25 1.998 VIN = 6 V 1.997 1.996 VIN = 12 V 1.995 1.994 VIN = 6 V 3.305 VVREF - Voltage Reference - V VVREF - Voltage Reference - V 200 150 Figure 22. 3.3-V LDO Load Regulation OUTPUT VOLTAGE vs OUTPUT CURRENT VIN = 25 V 1.993 6 12 25 3.300 3.295 VIN = 12 V 3.290 VIN = 25 V 3.285 3.280 3.275 1.992 1.991 3.270 0 50 100 150 0 1 IOUT - Output Current - mA Figure 23. 2-V Reference Load Regulation 22 100 IOUT - Output Current - mA 2 3 4 5 6 7 8 9 10 IOUT - Output Current - mA Figure 24. 3.3-V Reference Load Regulation Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51427 TPS51427 www.ti.com................................................................................................................................................ SLUS819B - APRIL 2008 - REVISED SEPTEMBER 2008 TYPICAL CHARACTERISTICS (continued) FREQUENCY vs INPUT VOLTAGE FREQUENCY vs INPUT VOLTAGE 500 600 VTONSEL (V) VV5FILT GND VVREF2 VTONSEL= GND 300 500 fSW - Frequency - kHz fSW - Frequency - kHz 400 VTONSEL = VVREF2 VTONSEL = VV5FILT 200 400 VTONSEL= GND 300 VTONSEL (V) 200 VV5FILT GND VVREF2 100 5 15 10 20 VTONSEL = VVREF2 100 25 5 VIN - Input Voltage - V 15 10 20 25 VIN - Input Voltage - V Figure 25. Channel 1 (5-V Setting) Figure 26. Channel 2 (3.3-V Setting) FREQUENCY vs OUTPUT CURRENT FREQUENCY vs OUTPUT CURRENT 250 200 VTONSEL = VV5FILT 400 CH1 VIN = 12 V VTONSEL = VV5VFILT 350 CH2 VIN = 12 V VTONSEL = VV5VFILT fSW - Frequency - kHz fSW - Frequency - kHz 300 150 100 Auto-Skip OOA 250 200 Auto-Skip 150 100 OOA 50 50 0 0.001 0.01 0.1 1 10 0 0.001 IOUT - Output Current - A Figure 27. Load Current (5-V Setting) 0.01 0.1 1 Figure 28. Load Current (3.3-V Setting) Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51427 10 IOUT - Output Current - A 23 TPS51427 SLUS819B - APRIL 2008 - REVISED SEPTEMBER 2008................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) FREQUENCY vs INPUT VOLTAGE FREQUENCY vs INPUT VOLTAGE 500 600 VTONSEL (V) VTONSEL= GND 300 VTONSEL= VVREF2 GND VREF2 V5FILT 500 fSW - Frequency - kHz 400 fSW - Frequency - kHz VTONSEL (V) GND VREF2 V5FILT VTONSEL= VV5FILT VTONSEL= GND 400 300 200 200 VTONSEL= VVREF2 100 100 5 10 15 20 25 5 10 VIN - Input Voltage - V 25 FREQUENCY vs OUTPUT CURRENT 350 350 CH1 VIN = 19 V VTONSEL = GND 300 250 200 150 Auto-Skip OOA 50 0 0.001 CH2 VIN = 19 V VTONSEL = GND 300 fSW - Frequency - kHz fSW - Frequency - kHz 20 Figure 30. Channel 2 (1.05-V Setting) FREQUENCY vs OUTPUT CURRENT 250 200 150 Auto-Skip 100 OOA 50 0.01 0.1 1 10 0 0.001 IOUT - Output Current - A 0.01 0.1 1 10 IOUT - Output Current - A Figure 31. Load Current (5-V Setting) 24 15 VIN - Input Voltage - V Figure 29. Channel 1 (1.5-V Setting) 100 VTONSEL= VV5FILT Submit Documentation Feedback Figure 32. Load Current (3.3-V Setting) Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51427 TPS51427 www.ti.com................................................................................................................................................ SLUS819B - APRIL 2008 - REVISED SEPTEMBER 2008 TYPICAL CHARACTERISTICS (continued) FREQUENCY vs OUTPUT VOLTAGE FREQUENCY vs OUTPUT VOLTAGE 450 500 VTONSEL= GND VTONSEL (V) GND 2 5 450 350 fSW - Frequency - kHz 400 fSW - Frequency - kHz VTONSEL (V) GND 2 5 VTONSEL= 2 V 300 250 VTONSEL= 5 V 200 VTONSEL= GND 400 350 VTONSEL= 5 V 300 250 VTONSEL= 2 V 150 200 0 1 2 4 3 5 0 0.5 1.0 1.5 2.0 VOUT - Output Voltage - V VOUT - Output Voltage - V Figure 33. Channel 1 Setting Figure 34. Channel 2 Setting 2.5 Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51427 3.0 25 TPS51427 SLUS819B - APRIL 2008 - REVISED SEPTEMBER 2008................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) 26 Figure 35. Channel 1 Gate Driver Performance Figure 36. Channel 2 Gate Driver Performance Figure 37. Channel 1 Load Step Figure 38. Channel 1 Load Release Figure 39. Channel 2 Load Step Figure 40. Channel 2 Load Release Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51427 TPS51427 www.ti.com................................................................................................................................................ SLUS819B - APRIL 2008 - REVISED SEPTEMBER 2008 APPLICATION INFORMATION Table 4. List of Materials COMPONENTS CONFIGURATION NO. 1 400 kHz/300 kHz Channel1: 5 V/8 A (fixed) Channel2: 3.3 V/10 A (fixed) CONFIGURATION NO. 2 CONFIGURATION NO. 3 400 kHz/500 kHz Channel1: 1.5V/10A (fixed) Channel2: 1.05 V/15 A(fixed) 400kHz/500kHz Channel1: 1.8V/10A (adj) Channel2: 1.1V/15A (adj) Input voltage 8 V VIN 22 V Input MLCC capacitors 4 x 10 F, 25 V Murata GRM31CR61E106KA12L 4 x 10 F, 25 V Murata GRM31CR61E106KA12L 4 x 10 F, 25 V Murata GRM31CR61E106KA12L Output capacitor 1 x 330 F, 6 V, 25 m, Sanyo, 6TPE330ML 2 x 330 F, 2.5 V, 12 m, Sanyo, 2R5TPE330MC 2 x 330 F, 2.5 V, 12 m, Sanyo, 2R5TPE330MC Output inductor Sumida, 4.3 H, CEP125NP-4R3M-U, 11.4 m Sumida, 2.2 H, CEP125NP-2R2M-U, 5.4 m Sumida, 2.2 H, CEP125NP-2R2M-U, 5.4 m High-side MOSFET International Rectifier, IRF7807V, International Rectifier, IRF7807V, International Rectifier, IRF7807V, 30 V, 8.3 A, 0.017 30V, 8.3A, 0.017 30V, 8.3A, 0.017 Low-side MOSFET International Rectifier, IRF7811AV, 30 V, 10.8 A, 0.011 International Rectifier, IRF7832, 30V, 20A, 0.004 International Rectifier, IRF7832, 30V, 20A, 0.004 ROCL 267 k for OCL of 10 A to 14 A 110 k for OCL of 12 A to 18 A 110 k for OCL of 12 A to 18 A Tie VFB1 to GND Tie VFB1 to V5FILT Output capacitor 1 x 330 F, 4 V, 18 m Sanyo, 4TPE330MI 2 x 470F, 2.5 V, 9 m, Sanyo, 2R5TPE470M9 2 x 470 F, 2.5 V, 9 m, Sanyo, 2R5TPE470M9 Output inductor Sumida, 3.2 H, 8.0 m, CEP125NP-3R2M-U Vishay, 1 H, 3 m, IHLP5050CE Vishay, 1 H, 3 m, IHLP5050CE High-side MOSFET International Rectifier, IRF7807V, International Rectifier, IRF7821, 30 V, 8.3 A, 0.017 30 V, 13 A, 0.009 International Rectifier, IRF7821, 30 V, 13 A, 0.009 Low-side MOSFET International Rectifier, IRF7832, 30 V, 20 A, 0.004 International Rectifier, IRF7832, 30 V, 20 A, 0.004 International Rectifier, IRF7832, 30 V, 20 A, 0.004 ROCL 110 k for OCL of 12 A to 18 A 169 k for OCL of 18 A to 26 A 169 k for OCL of 18 A to 26 A Tie REFIN2 to V5FILT Tie REFIN2 to VREF3 Channel1 RUPPER_DIV RLOWER_DIV 39.2 k, 1% 24.9 k, 1% Channel2 RUPPER_DIV RLOWER_DIV 44.2 k, 1% 54.9 k Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51427 27 TPS51427 SLUS819B - APRIL 2008 - REVISED SEPTEMBER 2008................................................................................................................................................ www.ti.com Figure 41. Configuration 1: System Rail 28 Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51427 TPS51427 www.ti.com................................................................................................................................................ SLUS819B - APRIL 2008 - REVISED SEPTEMBER 2008 Figure 42. Configuration 2: Low Voltage Rail (Fixed Voltage Settings) Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51427 29 TPS51427 SLUS819B - APRIL 2008 - REVISED SEPTEMBER 2008................................................................................................................................................ www.ti.com Figure 43. Configuration 3: Low-Voltage Dual Rail (Adjustable Voltage Settings) 30 Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51427 TPS51427 www.ti.com................................................................................................................................................ SLUS819B - APRIL 2008 - REVISED SEPTEMBER 2008 Loop Compensation and External Part Selection A simplified buck converter system using D-CAP mode is shown below in Figure 44. VIN TPS51427 DRVH One Shot Q1 IL Switching Logic VOUT DRVL Q2 ILOAD ESR Blanking Period COUT VFB L O A D RFB + High-Speed Comparator VREF UDG-08056 Figure 44. D-CAP Mode Operation Schematic tON triggered when VOUT declines to VREF level tON I Lo IRIPPLE ILOAD VRIPPLE VREF VRIPPLE = IRIPPLE x ESR Figure 45. D-CAP Mode Operation Waveforms The output voltage is compared with an internal reference voltage through scaling. The PWM comparator determines the timing to turn on the high side MOSFET. The gain and speed of the comparator is high enough to keep the voltage at the beginning of each on cycle (or the end of off cycle) substantially constant. The DC output voltage changes when the input voltage changes due to the fact that voltage regulation is maintained at the valley point. Therefore, as the output ripple amplitude increases when the input voltage increases, the DC output voltage increases as well. Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51427 31 TPS51427 SLUS819B - APRIL 2008 - REVISED SEPTEMBER 2008................................................................................................................................................ www.ti.com For loop stability, the 0-dB frequency, f0, defined in Equation 4 must be lower than of the switching frequency. f0 = f 1 SW 2p ESR COUT 4 (4) As f0 is determined solely by the output capacitor's characteristics, loop stability of D-CAP mode is determined by the capacitor's chemistry. For example, the output capacitance of specialty polymer capacitors (SP-CAP) is on the order of several hundred microfarads and an ESR of approximately 10 m. These values yield a 0-dB frequency of 100 kHz or less and the loop is stable. However, ceramic capacitors yield a f0 at more than 700 kHz which is not suitable for this operational mode. Although D-CAP mode provides many advantages such as ease-of-use, minimum external components, and extremely fast transient response, a sufficient amount of feedback signal needs to be provided to reduce the jitter level. In a TPS51427 design, it is generally recommended to optimize the output voltage ripple at around 1.5% of the targeted DC voltage in both Auto-skip and PWM mode operations. For example, if VVOUT1 = 1.5 V, the desired output ripple should be at least 1.5 V x 1.5% = 22.5 mV. This can be achieved by taking advantage of the output bulk capacitor ESR. The external component selection is much simpler in D-CAP mode. Below is a simplified design procedure targeting to the customers that are very familiar with SMPS design. 1. Determine the output voltage setting. For the fixed 5 V/3.3 V option, tie VFB1 pin to GND and REFIN2 to V5FILT. For the fixed 1.5 V/1.05 V configuration, tie VFB1 to V5FILT and REFIN2 to VREF3. TPS51427 also supports adjustable voltage options for both channels. The adjustable range for Channel1 is between 0.7 V and 5.9 V and for Channel2 is between 0.5 V and 2.5 V. Figure 46 shows how to configure the adjustable voltage option for Channel1 and Figure 47 shows the configuration for Channel2. Also, equations are provided in Table 5 to aid the design process. 2. Choose the output inductor. Output inductance is a function of VIN, VOUT, fSW and the desired ripple current. For available switching frequency settings with TPS51427, refer to Table 2. The process of choosing the right output inductance is an iterative one; many considerations need to be taken, such as the desired transient response, efficiency over the entire load range, load/line regulation, component availability and cost. Base the initial output inductance value upon where the ripple current is 25% to 50% of the maximum loading current. For transient optimized design, ripple factor can be higher; and for efficiency and load/line regulation optimized design, the ripple factor can be lower. L= 1 IIND(ripple ) f (V IN(max ) - VOUT VIN(max ) ) V OUT = 3 IOUT(max ) f (V IN(max ) - VOUT VIN(max ) ) V OUT (5) 3. Choose the output capacitor(s). Organic semiconductor capacitors or specialty polymer capacitor(s) are recommended. Determine ESR to meet the required ripple voltage indicated previous. ESR = VOUT 32 1.5% IRIPPLE (6) Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51427 TPS51427 www.ti.com................................................................................................................................................ SLUS819B - APRIL 2008 - REVISED SEPTEMBER 2008 Table 5. Design Assistance Channel1 FIXED VOLTAGE OPTIONS Channel2 1.5 V by shorting VFB1 to V5FILT 5 V by shorting VFB1 to GND 3.3 V by shorting REFIN2 to V5FILT VOUT2 is set by RUPPER_DIV, RLOWER_DIV, and VFB1 Figure 47 VOUT1 is set by RUPPER_DIV, RLOWER_DIV, and VFB1 Figure 46 ae R UPPER _ DIV + R LOW ER _ DIV VVOUT1 = VVFB1 c c R LOW ER _ DIV e ADJUSTABLE VOLTAGE OPTIONS 1.05 V by shorting REFIN2 to VREF3 ( ) ae RLOWER _ DIV VVREF2 VREFIN2 = c c R + RLOWER _ DIV e UPPER _ DIV o / / o ( ) (8) (7) where where * o / / o * * VVFB1 = 0.7 V VBAT VVREF = 2 V VVOUT2 = VREFIN2 VBAT TPS51427 TPS51427 10 VOUT1 30 VOUT2 RUPPER_DIV 1 11 VFB1 VREF2 RUPPER_DIV 32 REFIN2 RLOWER_DIV RLOWER_DIV UDG-08059 Figure 46. Channel1 Adjustable Voltage Configuration UDG-08060 Figure 47. Channel2 Adjustable Voltage Configuration Ripple Requirement in PWM Mode, Skip Mode and OOA Mode Since TPS51427 is a constant on time based controller, minimum ripple requirement at the output is necessary to keep the main voltage loop stable. For loop stability, the ESR zero frequency, f0 must be lower than 1/4 of the switching frequency. This requirement can be easily fulfilled by using either POSCAP or SPCAP, due to their similar characteristics. In order for a constant on time topology to work properly in a real world environment, there should not be any substantial phase delay contributed by the parasitic model of the output capacitors. Such delay would create distortion to the essential feedback signal necessary for the device to process. In a TPS51427 design, it is generally recommended to optimize the output voltage ripple at around 1.5% of the targeted DC voltage in both auto-skip and PWM mode operations. Higher ripple is better in terms of jitter performance, however, lower ripple improves the line regulation and efficiency performance. It is a common practice as an attainable goal to optimize the converter design in terms of regulation and efficiency. There is an additional voltage loop in the TPS51427 design that needs to be considered. OOA (out-of-audio) mode is designed to keep the minimum switching frequency at least 22 kHz in the light load/no load operation in order to minimize the audible noise in the notebook system design during standby mode. Both main voltage loop and OOA loop require certain output ripple in order for the device to function properly. If the ripple is too low, the main loop is unstable. If OOA mode operation is desired, the recommended ripple cannot be more than 1% of the target DC voltage. Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51427 33 TPS51427 SLUS819B - APRIL 2008 - REVISED SEPTEMBER 2008................................................................................................................................................ www.ti.com Current Limit Design Considerations The current limit of Channel1 can be set using the TRIP1 pin via an external small resistor to GND. Channel2 current limit can be set via the TRIP2 pin. The sourcing current for both Channel1 and Channel2 is 5 A at room temperature with 2900 ppm/C built-in temperature coefficient (to compensate for the temperature dependency of the RDS(on) of the low-side MOSFET). To take advantage of this feature, a good thermal coupling between the TPS51427 and the low-side MOSFET has to be obtained. The current limit adjustment range (VTRIPx) is between 0.2 V and 2 V. If 5 V is applied to the pin (TRIP1 and/or TRIP2) directly (VTRIPx > 3.1 V), TPS51427 assumes a default of a 100-mV current limit without temperature compensation. Once the minimum OCL level is determined, translate the minimum OCL point (DC) into minimum valley current by subtracting of the peak-to-peak inductor current. Then convert the current information into the voltage level for the TPS51427 to process. VOCLx = RDS(on )max I(MIN)OCLvalley (9) where * the low-side MOSFET at TJ = 25C The external resistor can be set using Equation 10. aeV + 5mV o ROCLx = 10 c OCLx / ITRIP e o (10) where * ITRIP = 5 A and the tolerance is 5% Once ROCLx is obtained, calculate the maximum VTRIPx voltage to make sure the maximum voltage on the TRIP1 pin and/or the TRIP2 pin is less than 3.1 V for the entire operating temperature range. The TRIPx voltage (VTRIPx ) can be calculated by Equation 11. VTRIPx = ITRIP ROCLx (11) And maximum VTRIPx voltage can be calculated by Equation 12. ( ) VTRIPx(max) = ITRIP ROCLx (1 + TOL ) 1 + 2900ppm / C (TJ - 25C ) (12) where * * * ITRIP = 5 A TOL = 5% TJ is assumed to be 125C for the worst case junction temperature Shutdown and Standby Control Logic Shutdown and Standby Control Logic Table 34 ENLDO LDO VREF2 VREF3 EN1 EN2 Channel1 Channel1 Low Off Low Low Low Off Off High On On Low Low Off Off High On On High High On On High On On High Low On Off High On On Low High Off On On On (after Channel1 is up) On (after Channel2 is up) On High On On High On On On (if VIN > 2.2 V) Off (if VIN < 2 V) High High Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51427 TPS51427 www.ti.com................................................................................................................................................ SLUS819B - APRIL 2008 - REVISED SEPTEMBER 2008 Layout Guidelines 1. Place one or two 10-F ceramic capacitor(s) for VIN between two channels. Add 1000-pF ceramic capacitor between drain of the high-side MOSFET and source of the low-side MOSFET of each channel. 2. Place VIN capacitors, VOUT1/VOUT2 capacitors and MOSFETs on the same side of the board. Positive terminal of VIN capacitor and drain of the high-side MOSFET should be as close as possible (within 10 mm if possible). Also place negative terminals of both VIN capacitor and VOUT capacitor, and source of the low-side MOSFET as close as possible. 3. GND terminal of the device (signal GND) and PGND terminal (power GND) should be connected with the lowest impedance near the device. 4. Trace of the switching node which is connected between the source of the high-side MOSFET, drain of the low-side MOSFET and the upstream of the output inductor should be as short and thick as possible. Use 40 mil of width (LL1 and LL2) for every ampere of load current. 5. LL1 and LL2 serve the phase node connections for the high-side drivers. Also, they are served as input to the current comparators for RDS(on) sensing and input voltage monitor for the on time control circuitry. Route the return of these two traces to device pins as wide and short as possible to eliminate the parasitic inductance effect to the accuracy of the measurement. 6. Place a low-pass filter MLCC capacitor with a value of 1-F from V5FILT to GND, as close as possible. 7. The output of LDO if configured as 5VLDO, requires at least 4.7-F of MLCC to GND. If it is configured as 3.3 VLDO, 10 F of MLCC is recommended. For optimized stability and transient response, use a value of 27 F if the output of LDO is configured as 1VLDO. VREF2 requires 0.1-F ceramic bypass capacitor to GND which should be placed as close to the device as possible. For VREF3, it generally requires a 1-F ceramic by pass capacitor to GND which also should be placed as close to the device as possible. 8. Connect the overcurrent setting resistors from TRIP1/TRIP2 to GND. The traces from TRIP1/TRIP2 should be routed as far as possible from the switching nodes. 9. 9. In the case of adjustable output voltage with external resistor dividers, the discharge path (VOx) can share the trace to the output capacitor with the feedback trace (VFB1/REFIN2). Please place the voltage setting resistors as close to the device as possible. Route the VOx and feedback traces as far from the high speed switching nodes as possible to avoid noise coupling. 10. Connections from the drivers to the respective gate of the high-side or the low-side MOSFETs should be as short as possible to reduce stray inductance. Use 0.65 mm (25 mils) or wider trace. 11. All sensitive analog traces and components such as VO1/VO2, VFB1/REFIN2, VREF2, VREF3, EN1/EN2, GND, VSW, PGOOD1/PGOOD2, TRIP1/TRIP2, ENLDO, LDOREFIN, V5FILT, TONSEL and SKIPSEL should be placed away from high-voltage switching nodes such as LLx, DRVLx or DRVHx nodes to avoid coupling. Use internal layer(s) as ground plane(s) and shield feedback traces from power traces and components. 12. In order to effectively remove heat from the package, prepare thermal land and solder to the package's thermal pad. 3 x 3 or more vias with a 0.33-mm (13mils) diameter connected from the thermal land to the internal ground plane should be used to help dissipation. Connect GND to the thermal land directly. Submit Documentation Feedback Copyright (c) 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51427 35 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS51427RHBR QFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TPS51427RHBR QFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TPS51427RHBT QFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TPS51427RHBT QFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS51427RHBR QFN RHB 32 3000 367.0 367.0 35.0 TPS51427RHBR QFN RHB 32 3000 367.0 367.0 35.0 TPS51427RHBT QFN RHB 32 250 210.0 185.0 35.0 TPS51427RHBT QFN RHB 32 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as "components") are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI's terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers' products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers' products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI's goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or "enhanced plastic" are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such components to meet such requirements. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP(R) Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2012, Texas Instruments Incorporated