1
FEATURES
DESCRIPTION
APPLICATIONS
TPS51427
TPS51427
www.ti.com
................................................................................................................................................ SLUS819B – APRIL 2008 – REVISED SEPTEMBER 2008
DUAL D-CAP™ SYNCHRONOUS STEP-DOWN CONTROLLERFOR NOTEBOOK POWER RAILS
23
•Fixed-Frequency Emulated On-Time Control;Frequency Selectable from Three Options
The TPS51427 is a dual synchronous step-downcontroller designed for notebook and mobile•D-CAP™ Mode Enables Fast Transient
communications applications. This device is part of aResponse Less than 100 ns
low-cost suite of notebook power bus regulators that•Advanced Ramp Compensation Allows Low
enables system designs with low external componentOutput Ripple with Minimal Jitter
counts. The TPS51427 includes two•Selectable PWM-Only/ OOA™/Auto-Skip Modes
pulse-width-modulation (PWM) controllers, SMPS1and SMPS2. The output of SMPS1 can be adjusted•Wide Input Voltage Range: 5.5 V to 28 V
from 0.7 V to 5.9 V, while the output of SMPS2 can•Dual Fixed or Adjustable SMPS:
be adjusted from 0.5 V to 2.5 V. This device also– 0.7 V to 5.9 V (Channel1)
features a low-dropout (LDO) regulator that providesa 5-V/3.3-V output, or adjustable from 0.7-V to 4.5-V– 0.5 V to 2.5 V (Channel2)
output via LDOREFIN. The fixed-frequency emulated•Fixed 3.3-V/5-V, or Adjustable Output 0.7-V to
adaptive on-time control supports seamless operation4.5-V LDO; Capable of Sourcing 100 mA
between PWM mode under heavy load conditions•Fixed 3.3-VREF Output Capable of Sourcing
and reduced frequency operation at light loads for10 mA
high-efficiency down to the milliampere range. Anintegrated boost switch enhances the high-side•Temperature Compensated Low-Side R
DS(on)
MOSFET to further improve efficiency. The mainCurrent Sensing
control loop is the D-CAP™ mode that is optimized•Adaptive Gate Drivers with Integrated Boost
for low equivalent series resistance (ESR) outputSwitch
capacitors such as POSCAP or SP-CAP. Advancedramp compensation minimizes jitter without degrading•Bootstrap Charge Auto Refresh
line and load regulation. R
DS(on)
current sensing•Integrated Soft Start, Tracking Soft Stop
methods offers maximum cost saving.•Independent PGOOD and EN for Each Channel
The TPS51427 supports supply input voltages thatrange from 5.5 V to 28 V. It is available in the 32-pin,5-mm × 5-mm QFN package (Green, RoHs-•Notebook I/O and System Bus Rails
compliant, and Pb-free). The device is specified from•Graphics Application
– 40 ° C to +85 ° C.•PDAs and Mobile Communication Devices
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2D-CAP, OOA are trademarks of Texas Instruments.3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
ABSOLUTE MAXIMUM RATINGS
(1)
DISSIPATION RATINGS
(1)
TPS51427
SLUS819B – APRIL 2008 – REVISED SEPTEMBER 2008 ................................................................................................................................................
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
(1)
ORDERABLET
A
PACKAGE PART NO. TRANSPORT MEDIA QUANTITY ECO STATUS
(2)
TPS51427RHBT 250 GreenPlastic Quad Flatpack– 40 ° C to +85 ° C Tape and Reel
(RoHs and No(32-pin QFN)
TPS51427RHBR 3000
Sb/Br)
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com .(2) Eco-Status information: Additional details including specific material content can be accessed at www.ti.com/leadfreeGREEN: Ti defines Green to mean Lead (Pb)-Free and in addition, uses less package materials that do not contain halogens, includingbromine (Br), or antimony (Sb) above 0.1% of total product weight.N/A: Not yet available Lead (Pb)-Free; for estimated conversion dates, go to www.ti.com/leadfree .Pb-FREE: Ti defines Lead (Pb)-Free to mean RoHS compatible, including a lead concentration that does not exceed 0.1% of totalproduct weight, and, if designed to be soldered, suitable for use in specified lead-free soldering processes.
Over operating free-air temperature range; all voltages are with respect to GND (unless otherwise noted).
PARAMETER VALUE UNIT
5V voltage range V5DRV, V5FILT – 0.3 to 7VIN, ENLDO – 0.3 to 30VBST1, VBST2 – 0.3 to 37
VVBST1, VBST2 (w.r.t. LLx) – 0.3 to 7Input voltage range
(2)
EN1, EN2, VOUT1, VOUT2, VFB1, REFIN2, TRIP1, TRIP2, SKIPSEL,
– 0.3 to 7TONSEL, VSW, LDOREFINTRIP1, TRIP2 – 0.3 to (V5FILT + 0.3)DRVH1, DRVH2 – 2 to 37DRVH1, DRVH2 (w.r.t. LLx) – 0.3 to 7Output voltage
LL1, LL2 – 2 to 30 Vrange
(2)
DRVL1, DRVL2, VREF2, PGOOD1, PGOOD2, LDO, VREF3 – 0.3 to 7PGND – 0.3 to 0.3T
stg
Storage temperature range – 55 to +150
° CT
J
Junction temperature range +150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values are with respect to the network ground terminal unless otherwise noted.
T
A
< +25 ° C DERATING FACTOR T
A
= +85 ° CPACKAGE POWER RATING ABOVE T
A
= +25 ° C POWER RATING
32Ld 5 × 5 QFN 2.320 W 23.2 mW/ ° C 0.93 W
(1) Dissipation ratings are calculated based on the usage of nine standard thermal vias and thermal pad soldered on the PCB. If thermalpad is not soldered to the PCB, the junction-to-ambient thermal resistance is 88.6 ° C/W.
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RECOMMENDED OPERATING CONDITIONS
TPS51427
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................................................................................................................................................ SLUS819B – APRIL 2008 – REVISED SEPTEMBER 2008
Over operating free-air temperature range (unless otherwise noted).
MIN TYP MAX UNIT
Supply input voltage range V5DRV, V5FILT 4.5 5.5 VInput voltage range VBST1, VBST2 – 0.1 34VBST1, VBST2 (with regard to LLx) – 0.1 5.5EN1, EN2, VOUT1, VFB1, REFIN2, TRIP1, TRIP2, SKIPSEL, TONSEL, – 0.1 5.5ENLDO,VSW, LDOREFINVOUT2 – 0.1 3.7Output voltage range DRVH1, DRVH2 – 0.8 34 VDRVH1, DRVH2 (w.r.t. LLx) – 0.1 5.5LL1, LL2 – 0.8 28DRVL1, DRVL2, VREF2, PGOOD1, PGOOD2, LDO, VREF3 – 0.1 5.5PGND – 0.1 0.1Operating free-air temperature, T
A
– 40 +85 ° C
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ELECTRICAL CHARACTERISTICS
TPS51427
SLUS819B – APRIL 2008 – REVISED SEPTEMBER 2008 ................................................................................................................................................
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Over recommended free-air temperature range, V
V5DRV
= 5 V, V
VIN
= 12 V (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLIES
VIN Input Voltage Range LDO in regulation 5.5 28 VVIN Operating Supply Current LDO switched over to VSW, 4.5-V to 5.5-V SMPS 5 10 µA5.5 V ≤V
VIN
≤28 V, T
A
= +25 ° C, no load, EN_LDO = 5VIN Standby Current 115 150 µAV, EN1 = EN2 = VSW = 0 V5.5 V ≤V
VIN
≤28 V, T
A
= +25 ° C, no load, EN_LDO =VIN Shutdown Current 12 20 µAEN1 = EN2 = VSW = 0 VT
A
= +25 ° C, no load, EN_LDO = EN1 = EN2 = REFIN2Quiescent Power Consumption = 5 V, VFB1 = SKIPSEL = 0 V, VOUT1 = VSW = 5.3 V, 5 7 mWVOUT2 = 3.5 V
PWM CONTROLLERS
5-V Preset output: 5.5 V ≤V
VIN
≤28 V, 4.975 5.1255.05VFB1 = 0 V, SKIPSEL = 5 V ( – 1.5%) (+1.5%)1.5-V Preset output: 5.5 V ≤V
VIN
≤28 V, 1.482 1.518VOUT1 Output Voltage Accuracy 1.50 VVFB1 = 5V, SKIPSEL = 5V ( – 1.2%) (+1.2%)Adjustable feedback output, 0.693 0.7070.705.5 V ≤V
VIN
≤28 V, SKIPSEL = 5 V ( – 1%) (+1%)VOUT1 Voltage Adjust Range 0.707 5.900 V5-V Preset output 0.20 VVFB1 Threshold Voltage
1.5-V Preset output 3.90 VVFB1 Input Current VFB1 = 0.8 V – 0.20 0.20 µA3.285 3.3753.3-V Preset output: REFIN2 = 5 V, 5.5 V ≤V
VIN
≤28 V,
3.33SKIPSEL = 5 V
( – 1.4%) (+1.4%)1.038 1.0621.05-V Preset output: REFIN2 = 3.3 V,VOUT2 Output Voltage Accuracy 1.05 V5.5 V ≤V
VIN
≤28 V, SKIPSEL= 5 V
(-1.2%) (+1.2%)0.99 1.01Tracking output: REFIN2 = 1.0 V, 5.5 V ≤V
VIN
≤28 V,
1.00SKIPSEL = 5 V
(-1%) (+1%)REFIN2 Voltage Adjust Range 0.50 2.50 VREFIN2 Input Current 0.5 V ≤V
VREFIN2
≤2.5 V – 0.2 0.2 µA1.05-V Preset output 3.00 3.45REFIN2 Threshold Voltage V3.3-V Preset output 3.90Either SMPS, SKIPSEL = 5 V, 0 A to 5 A
(1)
– 0.10%DC Load Regulation Either SMPS, SKIPSEL = 2 V, 0 A to 5 A
(1)
– 2.20%Either SMPS, SKIPSEL = GND, 0 A to 5 A
(1)
– 0.50%Line Regulation Either SMPS, 5.5 V < VIN < 28 V
(1)
0.005 %/VTONSEL = 0 V, 2 V, or OPEN (400 kHz),
895 1052 1209VOUT1 = 5.05 VChannel1 On-Time nsTONSEL = 5 V (200 kHz), VOUT1 = 5.05 V 1895 2105 2315TONSEL = 0 V (500 kHz), VOUT2 = 3.33 V 475 555 635Channel2 On-Time nsTONSEL = 2 V, OPEN, or 5 V (300 kHz),
833 925 1017VOUT2 = 3.33 VMinimum Off-Time 300 400 500 nsSoft Start Ramp Time Zero to full limit 1.8 msVOUT1, VOUT2 Discharge On
EN1 = EN2 = 0 V, VOUT1 = VOUT2 = 0.5 V 17 35 ΩResistance
OOA Operating Frequency SKIPSEL = 2 V or OPEN 22 30 kHz
(1) Ensured by design. Not production tested.
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................................................................................................................................................ SLUS819B – APRIL 2008 – REVISED SEPTEMBER 2008
ELECTRICAL CHARACTERISTICS (continued)Over recommended free-air temperature range, V
V5DRV
= 5 V, V
VIN
= 12 V (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LINEAR REGULATOR (LDO)
4.94 5.11LDOREFIN = VSW = 0 V, 0 < I
LDO
< 10 0mA,
5.0256 V < VIN < 28 V
( – 1.7%) (+1.7%)3.28 3.38LDOREFIN = 5 V, VSW = 0 V, 0 < I
LDO
< 100 mA,LDO Output Voltage 3.33 V5.5 V < VIN < 28 V
( – 1.5%) (+1.5%)0.98 1.02LDOREFIN = 0.5 V, VSW = 0 V, 0 < I
LDO
< 50 mA,
1.005.5V < VIN < 28 V
( – 2%) (+2%)LDOREFIN Input Range VLDO = 2 × VLDOREFIN 0.35 2.25 VLDOREFIN Leakage Current VLDOREFIN = 0 V or 5 V – 0.5 0.5 µAFixed LDO = 5 V 0.15LDOREFIN Threshold Voltage VFixed LDO = 3.3 V 3.90LDO Output Current VSW = GND , VIN = 5.5 V to 28 V 100 mALDO Output Current During
VSW = 5 V , VIN = 5.5 V to 28 V, LDOREFIN = 0 V 340 500 mASwitchover to 5 VLDO Output Current During
VSW = 3.3 V , VIN = 5.5 V to 28 V, LDOREFIN = 5 V 330 500 mASwitchover to 3.3 VLDO Short-Circuit Current VSW = LDO = 0 V 140 180 220 mA4.63 4.78 4.93Rising edge of VSW, LDOREFIN = 0 V
(92.6%) (95.6%) (98.6%)LDO 5-V Switchover Threshold VHysteresis 0.203.05 3.15 3.25Rising edge of VSW, LDOREFIN = 5 V
(92.5%) (95.5%) (98.5%)LDO 3.3-V Switchover Threshold VHysteresis 0.150LDO Switchover Switch On
LDO to VSW, VSW = 5 V, ILDO = 100 mA 0.7 1.5 ΩResistance
LDO Switchover Delay Turning on 3.96 msFalling edge of V5FILT 3.80 3.93 4.10LDO Undervoltage Lockout
VThreshold
Rising edge of V5FILT 4.20 4.37 4.50Falling edge of VIN 1.8VIN POR Threshold VRising edge of VIN 2.1Thermal-Shutdown Threshold Hysteresis = +10 ° C
(2)
+140 ° C
3.3V ALWAYS-ON LINEAR REGULATOR (VREF3)
3.250 3.350No external load, V
VSW
> 4.5 V 3.300( – 1.5%) (+1.5%)VREF3 Output Voltage V3.220 3.380No external load, V
VSW
< 4.0 V 3.300( – 2.4%) (+2.4%)VREF3 Load Regulation 0 mA < I
LOAD
< 10 mA 60 mVVREF3 Current Limit VREF3 = GND 15 20 mAFalling edge of VREF3 2.96VREF3 Undervoltage Lockout
VThreshold
Hysteresis 0.17
(2) Ensured by design. Not production tested.
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TPS51427
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ELECTRICAL CHARACTERISTICS (continued)Over recommended free-air temperature range, V
V5DRV
= 5 V, V
VIN
= 12 V (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
REFERENCE (REF)
1.98 2.02|I
VREF2
| = 0 µA 2.00( – 1%) (+1%)VREF2 Output Voltage V1.975 2.025|I
VREF2
| < 50 µA 2.00( – 1.25%) (+1.25%)VREF2 Sink Current VREF2 in regulation 50 µAFalling edge of VREF2 1.575 1.700 1.825VREF2 Undervoltage Lockout
VThreshold
Hysteresis 0.1
OUT1 FAULT DETECTION
Overvoltage Trip Threshold VFB1 with respect to nominal regulation point +12.5% +15% +17.5%Overvoltage Fault Propagation
VFB1 delay with 50-mV overdrive 10 µsDelay
Undervoltage Trip Threshold VFB1 with respect to nominal output voltage – 35% – 30% – 25%Undervoltage Fault Propagation
0.8 1 1.2 msDelay
Undervoltage Fault Enable Delay From ENx signal 10 20 30 msVFB1 with respect to nominal output, falling edge,PGOOD1 Lower Trip Threshold – 12.5% – 10% – 7.5%typical hysteresis = 5%PGOOD1 Low Propagation Delay Falling edge, 50-mV overdrive 10 µsPGOOD1 High Propagation Delay Rising edge, 50-mV overdrive 0.8 1.0 1.2 msPGOOD1 Output Low Voltage PGOOD1 Low impedance, I
SINK
= 4 mA 0.4 0.8 VOut-Of-Bound Threshold VFB1 with respect to nominal output voltage +5%PGOOD1 Leakage Current PGOOD1 High impedance, forced to 5.5 V 1 µA
OUT2 FAULT DETECTION
Overvoltage Trip Threshold REFIN2 with respect to nominal regulation point +12.5% +15.0% +17.5%Overvoltage Fault Propagation
REFIN2 delay with 50-mV overdrive 10 µsDelay
Undervoltage Trip Threshold REFIN2 with respect to nominal output voltage – 35% – 30% – 25%Undervoltage Fault Propagation
0.8 1 1.2 msDelay
Undervoltage Fault Enable Delay From ENx signal 10 20 30 msREFIN2 with respect to nominal output, falling edge,PGOOD2 Lower Trip Threshold – 12.5% – 10% – 7.5%typical hysteresis = 5%Out-Of-Bound Threshold REFIN2 with respect to nominal output voltage +5%PGOOD2 Low Propagation Delay Falling edge, 50-mV overdrive 10 µsPGOOD2 High Propagation Delay Rising edge, 50-mV overdrive 0.8 1.0 1.2 msPGOOD2 Output Low Voltage PGOOD2 Low impedance, I
SINK
= 4 mA 0.4 0.8 VPGOOD2 Leakage Current PGOOD2 High impedance, forced to 5.5 V 1 µA
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................................................................................................................................................ SLUS819B – APRIL 2008 – REVISED SEPTEMBER 2008
ELECTRICAL CHARACTERISTICS (continued)Over recommended free-air temperature range, V
V5DRV
= 5 V, V
VIN
= 12 V (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT LIMIT
TRIPx Adjustment Range 0.2 2.0 V4.75 5.25TRIPx Source Current 0.2 V < V
TRIPx
< 2 V, T
A
= +25 ° C 5 µA( – 5%) (+5%)TRIPx Current Temperature Coefficient on the basis of T
A
= +25 ° C
(3)
2900 ppm/ ° C13 27GND – LLx, V
TRIPx
= 0.2 V 20( – 35%) (+35%)42.5 57.5GND – LLx, V
TRIPx
= 0.5 V 50( – 15%) (+15%)Current-Limit Threshold (Positive,
mVAdjustable)
93 107GND – LLx, V
TRIPx
= 1 V 100( – 7%) (+7%)190 210GND – LLx, V
TRIPx
= 2 V 200( – 5%) (+5%)93 107Current-Limit Threshold (Positive, V
TRIPx
= 5.0 V, GND – LLx (no temperature
100 mVDefault) compensation)
( – 7%) (+7%)High threshold 3.0 3.2 3.3 VFixed 100-mV OCL TRIPxThreshold Voltage
Hysteresis 40 70 100 mVWith respect to valley current limit threshold,Current Limit Threshold (Negative) – 100%SKIPSEL = 5 VZero-Crossing Current Limit
SKIPSEL = 0 V, 2 V, or OPEN, GND – LLx – 3.5 0 3.5 mVThreshold
GATE DRIVERS
Source, VBSTx-DRVHx = 0.1 V 1.0 3.6DRVHx Gate-Driver
ΩOn-Resistance
Sink, DRVHx-LLx = 0.1 V 0.8 2.6Source, V5DRV-DRVLx = 0.1 V 1.2 4.0DRVLx Gate-Driver On-Resistance ΩSink, DRVLx-PGND = 0.1 V 0.6 1.5DRVHx Gate-Driver Source
VBSTx-LLx = 5 V, DRVHx = 2.0 V
(3)
1.8 ACurrent
DRVHx Gate-Driver Sink Current VBSTx-LLx = 5 V, DRVHx = 2.0 V
(3)
1.6 ADRVLx Gate-Driver Source
V5DRV-PGND = 5 V, DRVLx = 2.0 V
(3)
1.4 ACurrent
DRVLx Gate-Driver Sink Current V5DRV-PGND = 5 V, DRVLx = 2.0 V
(3)
2.6 ADRVHx low (DRVHx = 1 V) to DRVLx high (DRVLx = 4
20 30 50 nsV), LLx = – 0.05 VDead Time
DRVLx low (DRVLx = 1 V) to DRVHx high (DRVHx = 4
25 40 60 nsV), LLx = – 0.05 VInternal BST_ Switch
I
VBSTx
= 10 mA, V5DRV = 5 V, T
A
= +25 ° C 10 ΩOn-Resistance
VBSTx Leakage Current V
VBSTx
= 35 V, LLx = 28 V 0.01 2.0 µA
(3) Ensured by design. Not production tested.
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TPS51427
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ELECTRICAL CHARACTERISTICS (continued)Over recommended free-air temperature range, V
V5DRV
= 5 V, V
VIN
= 12 V (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUTS AND OUTPUTS
High level 2.9TONSEL Input Logic Levels Float level 1.85 2.25 VLow level 0.45High threshold (PWM Only) 2.9SKIPSEL Input Logic Levels Float level (OOA) 1.85 2.25 VLow level (Auto Skip) 0.45SKIPSEL, TONSEL Input Current SKIPSEL = TONSEL = 0 V 2.5 4.0 5.5 µASMPS On level 2.9EN1, EN2 Input Logic Levels Delay start level 1.85 2.25 VSMPS Off level 0.45EN1, EN2 Leakage Current EN1 = EN2 = 0 V – 0.1 0.1 µARising edge 1.3 1.65 1.9EN_LDO Input Logic Levels VHysteresis 0.6EN_LDO = 0 V 0.7 1.0 1.3EN_LDO Input Current µAEN_LDO = 30 V – 0.1 0 0.1
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DEVICE INFORMATION
TPS51427
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................................................................................................................................................ SLUS819B – APRIL 2008 – REVISED SEPTEMBER 2008
TERMINAL FUNCTIONSTERMINAL
NAME NO. I/O DESCRIPTION
DRVH1 15
High-side N-Channel FET driver outputs. LL referenced floating drivers. The gate drive voltage is defined by the voltage acrossO
VBST to LL node bootstrap capacitor.DRVH2 26
DRVL1 18
O Synchronous low-side MOSFET driver outputs. Ground referenced drivers. The gate drive voltage is defined by V5DRV voltage.DRVL2 23
EN1 14
Channel enable pins. If EN1 is connected to VREF2, Channel1 starts after Channel2 reaches regulation (delay start). If EN2 isI
connected to VREF2, Channel2 starts after Chanel1 reaches regulation.EN2 27
LDO Enable Input. The LDO is enabled if EN_LDO is within logic high level and disabled if EN_LDO is less than the logic lowEN_LDO 4 I
level.
GND 21 I Analog ground for both channels and LDO.
LL1 16
Phase node connections for high-side drivers. These connections also serve as inputs to current comparators for R
DS(on)
sensingI/O
and input voltage monitor for on-time control circuitry.LL2 25
Linear regulator output. The LDO regulator can provide a total of 100-mA external loads. The LDO regulates at 5 V If LDOREFINis connected to GND. When the LDO is set at 5 V and VSW is within a 5-V switchover threshold, the internal regulator shutsdown and the LDO output pin connects to VSW through a 0.7- Ωswitch. The LDO regulates at 3.3 V if LDOREFIN is connectedLDO 7 O
to V5FILT. When the LDO is set at 3.3 V and VSW is within a 3.3-V switchover threshold, the internal regulator shuts down andthe LDO output pin connects to VSW through a 0.7- Ωswitch. Bypass the LDO output with a minimum of 4.7- µF ceramiccapacitance.
LDO Reference Input. Connect LDOREFIN to GND for fixed 5-V operation. Connect LDOREFIN to V5FILT for fixed 3.3-VLDOREFIN 8 I operation. LDOREFIN can be used to program LDO output voltage from 0.7 V to 4.5 V. LDO output is twice the voltage ofLDOREFIN. There is no switchover in adjustable mode.
Ground pin for drivers and LS synchronous FET source terminals. This pin is also the input to zero crossing comparator andPGND 22 I
overcurrent comparator.
PGOOD1 13 Channel1/Channel2 power-good open-drain output. PGOOD1/PGOOD2 is low when the Channel1/Channel2 output voltage isO 10% less than the normal regulation point, at onset of OVP events, or during soft start. PGOOD1/PGOOD2 is high impedancePGOOD2 28
when the output is in regulation and the soft-start circuit has terminated. PGOOD1/PGOOD2 is low in shutdown.
Output voltage control for Channel2. Connect REFIN2 to V5FILT for fixed 3.3-V operation. Connect REFIN2 to VREF3 for fixedREFIN2 32 I
1.05-V operation. REFIN2 can be used to program Channel2 output voltage from 0.5 V to 2.5 V.
NC 20 -
Low-noise mode control. Connect SKIPSEL to GND for Auto Skip mode operation or to V5FILT for PWM mode (fixed frequency).SKIPSEL 29 I
Connect to VREF2 or leave floating for OOA™ mode operation.
Frequency select input. Connect to GND for 400-kHz/500-kHz operation. Connect to VREF2 (or leave open) forTONSEL 2 I 400-kHz/300-kHz operation. Connect to V5FILT for 200-kHz/300-kHz operation (5-V/3.3-V SMPS switching frequencies,respectively).
TRIP1 12
I Overcurrent trip point set input. Sourcing current is 5 µA at RT with 2900 ppm/ ° C temperature coefficient.TRIP2 31
Supply voltage for the low-side MOSFET driver DRVL1/DRVL2. Connect a 5-V power source to the V5DRV pin (bypass withV5DRV 19 I
4.7- µF MLCC capacitor to PGND if necessary).
V5FILT 3 I 5-V analog supply input.
Channel1 feedback input. Connect VFB1 to GND for fixed 5-V operation. Connect VFB1 to V5FILT for fixed 1.5-V operation.VFB1 11 I
Connect VFB1 to a resistive voltage divider from OUT1 to GND to adjust the output from 0.7 V to 5.9 V.
VBST1 17
I Supply input for high-side MOSFET driver (bootstrap terminal). Connect a capacitor from this pin to the respective LL terminals.VBST2 24
Power supply input. VIN supplies power to the linear regulators. The linear regulators are powered by Channel1 if VOUT1 is setVIN 6 I
greater than 5 V and VSW is tied to VOUT1.
VOUT1 10
O Output connections to SMPS. These terminals serve two functions: on-time adjustment and output discharge.VOUT2 30
VREF2 1 O 2-V reference output. Bypass to GND with a 0.1- µF capacitor. VREF2 can source up to 50 µA for external loads.
VREF3 5 O 3.3-V reference output. VREF3 can source up to 10 mA for external loads. Bypass to GND with a 1- µF capacitor.
VSW is the switchover source voltage for the LDO when LDOREFIN is connected to GND or V5FILT. Connect VSW to 5 V ifVSW 9 I
LDOREFIN is tied GND. Connect VSW to 3.3 V if LDOREFIN is tied to V5FILT.
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1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9 10 11 12 13 14 15 16
VREF2 VBST2
VSW REFIN2
VOUT1
VFB1
TRIP1
PGOOD1
EN1
DRVH1
LL1
252627
282930
3132
TONSEL
V5FILT
EN_LDO
VREF3
VIN
LDO
LDOREFIN
DRVL2
NC
GND
PGND
V5DRV
DRVL1
VBST1
TRIP2
VOUT2
SKIPSEL
PGOOD2
EN2
DVRH2
LL2
TPS51427
RHB PACKAGE
(TOP VIEW)
TPS51427
SLUS819B – APRIL 2008 – REVISED SEPTEMBER 2008 ................................................................................................................................................
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QFN-32, 5-mm × 5-mm(TOP VIEW)
NC = No connection.
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FUNCTIONAL BLOCK DIAGRAMS
140°C
/125°C
TPS51427
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DETAILED DESCRIPTION
BASIC PWM OPERATION
LIGHT LOAD CONDITIONS
( )
f
VIN VOUT VOUT
OUT(LL)
SW VIN
V V V
1
I2 L V
æ ö
- ´
æ ö
= ´ ç ÷
ç ÷ ç ÷
´ ´
è ø è ø
(1)
TPS51427
SLUS819B – APRIL 2008 – REVISED SEPTEMBER 2008 ................................................................................................................................................
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The main control loop of the TPS51427 is designed as an adaptive on-time pulse width modulation (PWM)controller. It supports a proprietary D-CAP™ mode that uses internal compensation circuitry and is suitable for aminimal external component count configuration when an appropriate amount of ESR at the output capacitor(s) isallowed. D-CAP mode can also enable stable operation when using capacitors with low ESR, such as specialtypolymer capacitors.
The basic operation of D-CAP mode can be described in this way: At the beginning of each cycle, thesynchronous high-side MOSFET turns on or goes to an ON state. This MOSFET turns off, or returns to an OFFstate, after an internal one-shot timer expires. The one-shot timer is determined by VIN and VOUT and keeps thefrequency fairly constant over the input voltage range under steady-state conditions; it is an adaptive on-timecontrol or fixed-frequency emulated on-time control. The MOSFET turns on again when the following twoconditions occur:•Feedback information, monitored at the VFB1/VOUT2 voltage, indicates insufficient output voltage; and•the inductor current information indicates that current is below the overcurrent limit.Operating in this manner, the controller regulates the output voltage. The synchronous low-side or the rectifyingMOSFET is turned on each OFF state to keep the conduction loss minimum.
The TPS51427 supports three selectable operating modes: PWM-only, Out-Of-Audio ( OOA™), and Auto-Skip.
If the SKIPSEL pin is connected to GND, Auto-Skip mode is selected. This mode enables a seamless transitionto the reduced frequency operation under light load conditions so that high efficiency is maintained over a widerange of load current. This frequency reduction is achieved smoothly and without an increase in V
OUT
ripple orload regulation.
Auto-Skip operation can be described in this way: As the output current decreases from a heavy load condition,the inductor current is also reduced. Eventually, the inductor current reaches the point that its valley equals zerocurrent; that is, the boundary between continuous conduction and discontinuous conduction modes. Therectifying MOSFET turns off when this zero inductor current is detected. Because the output voltage remainshigher than the reference voltage at this point, both high-side and low-side MOSFETs are turned off and wait forthe next cycle. As the load current decreases further, the converter runs in discontinuous conduction mode andtakes longer to discharge the output capacitor below the reference voltage. Note that the ON time remains thesame as that in the heavy load condition. On the other hand, when the output current increases from a light loadto a heavy load, the switching frequency increases to the preset value as the inductor current reaches thecontinuous conduction limit. The transition load point to the light load operation I
OUT(LL)
(that is, the thresholdbetween continuous conduction and discontinuous conduction mode) can be calculated as shown in Equation 1 :
Where f
SW
is the PWM switching frequency. Switching frequency versus output current under a light loadcondition is a function of L, f
SW
, V
IN
, and V
OUT
, but decreases at a near-proportional rate to the output currentfrom the I
OUT(LL)
threshold. For example, the frequency is approximately 60 kHz at I
OUT(LL)
/5 if the PWM switchingfrequency is 300 kHz.
PWM-only mode is selected if the SKIPSEL pin is connected to 5 V. The rectifying MOSFET does not turn offwhen the inductor current reaches zero. The converter runs in forced continuous conduction mode over theentire load range. System designers may want to use this mode to avoid certain frequencies under light loadconditions but do so at the cost of lower efficiency. However, keep in mind that the output has the capability toboth source and sink current in this mode. If the output terminal is connected to a voltage source that is higherthan the regulator target value, the converter sinks current from the output and boosts the charge into the inputcapacitors. This operation may cause an unexpected high voltage at VIN and may damage the power FETs.
If SKIPSEL pin is connected to VREF2 or left floating, OOA mode operation is selected.
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OUT-OF-AUDIO ( OOA™) OPERATION
RAMP COMPENSATION
LOW-SIDE DRIVER
HIGH-SIDE DRIVER
BOOSTRAP CHARGE AUTO REFRESH
PWM FREQUENCY AND ADAPTIVE ON-TIME CONTROL
TPS51427
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................................................................................................................................................ SLUS819B – APRIL 2008 – REVISED SEPTEMBER 2008
Table 1. SKIPSEL Operating Modes
SKIPSEL GND FLOAT/VREF2 V5IN
Operating Mode Auto Skip OOA™ PWM Only
If out-of-audio (OOA) operation is enabled, the switching frequency of the channel remains higher than theaudible frequency under any load condition, at a minimum of 22 kHz to minimize the audible noise in the system.The TPS51427 automatically reduces switching frequencies under light load conditions. The OOA control circuitmonitors the switching period and forces the high-side MOSFET to turn on if the switching frequency goes belowthe 22-kHz threshold.
The high-side MOSFET turns on even if the output voltage is higher than the target value; therefore, the outputvoltage tends to be higher when operating in OOA mode. The OOA control circuit detects the overvoltagecondition and prevents the voltage from rising by re-modulating the device on time. The overvoltage condition isdetected by the VFB1/VOUT2 voltages.
The inductor current ripple (peak-to-peak) should be less than two-thirds of the OCL setting for the OOA circuit towork properly at a 0-A load. To keep the OOA mode loop stable, the output voltage ripple cannot be too large. IfOOA mode operation is desired, the recommended output ripple voltage cannot be more than 1% of the targetdc voltage.
The TPS51427 employs an advanced ramp compensation technique in D-CAP mode to optimize jitterperformance. An internal ramp signal is added to the reference voltage to virtually increase the slope of theVFB1/VOUT2 down ramp, which the PWM comparator uses to determine the turn-on timing.
The low-side driver is designed to drive high-current, low R
DS(on)
, N-channel MOSFET(s). The drive capability isrepresented by its internal resistance: 1.2 Ωfor V5DRV to DRVLx and 0.6 Ωfor DRVLx to PGND. A dead time toprevent shoot-through is generated internally between the two transistors, with the top MOSFET off and bottomMOSFET on, and then with the bottom MOSFET off and the top MOSFET on. A 5-V bias voltage is deliveredfrom the V5DRV supply. The instantaneous drive current is supplied by an input capacitor connected betweenV5DRV and GND. The average drive current is equal to the gate charge at V
GS
= 5 V times the switchingfrequency.
The high-side driver is also designed to drive high-current, low R
DS(on)
, N-channel MOSFET(s). When configuredas a floating driver, a 5-V bias voltage is delivered from the V5DRV supply. The average drive current is alsocalculated by the gate charge at V
GS
= 5 V times the switching frequency. The instantaneous drive current issupplied by the floating capacitor between the VBSTx and LLx pins. The drive capability is represented by itsinternal resistance: 1.0 Ωfor VBSTx to DRVHx and 0.8 Ωfor DRVHx to LLx.
Boost undervoltage protection is activated during the device ON time when the voltage difference betweenDRVH and LL becomes less than 1.8 V. Upon detection of the undervoltage condition, the high-side gate driverimmediately turns off and the low-side gate driver turns on after the deadtime expires for the minimum off time inan attempt to recharge the boost capacitor.
The TPS51427 employs an adaptive on-time control scheme and does not have a dedicated onboard oscillator.However, the device runs with pseudo-constant frequency by feed-forwarding the input voltage and outputvoltage into the on-time one-shot timer. The frequencies are set by the TONSEL terminal connection as Table 2shows. The on-time is controlled: it is inversely proportional to the input voltage and proportional to the outputvoltage, so that the duty ratio maintains technically as VOUT/VIN with the same cycle time. Although theTPS51427 does not use VIN directly, the input voltage is monitored at the LLx pin during the ON state.
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ENABLE AND SOFT START
POWER-GOOD AND OUT-OF-BOUND OPERATION
OUTPUT SHUTDOWN AND DISCHARGE CONTROL
2-V REFERENCE (VREF2)
3-V REFERENCE (VREF3)
TPS51427
SLUS819B – APRIL 2008 – REVISED SEPTEMBER 2008 ................................................................................................................................................
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Table 2. TONSEL Terminal Connection Options
TONSEL GND VREF2 or Float V5FILT
Channel1 Frequency 400 kHz 400 kHz 200 kHz
Channel2 Frequency 500 kHz 300 kHz 300 kHz
TPS51427 has an internal digital soft-start timer that begins to ramp up to the maximum allowed current limitduring device startup. The soft-start ramp occurs in five steps of positive current limit; step sizes are 20%, 40%,60%, 80%, and 100%. Smooth control of the output voltage during device startup is maintained. In addition, iftracking discharge is required, the ENx pin can be used to control the output voltage discharge smoothly. At thebeginning of the soft-start period, the rectifying MOSFET maintains an off state until the top MOSFET turns on atleast once. This architecture prevents a high negative current from flowing back from the output capacitor in theevent of an output capacitor pre-charged condition.
If EN1 is connected to VREF2, Channel1 starts up after the Channel2 reaches regulation (delay start). If EN2 isconnected to VREF2, Channel2 starts up after the Channel1 reaches regulation (delay start).
When both ENx are low and ENLDO is low, the TPS51427 enters a shutdown state and consumes less than15 µA.
The TPS51427 has a power-good output (PGOODx) for each switching channel. The power-good functionactivates after the soft start finishes. If the output voltage reaches within ± 95% of the target value, internalcomparators detect a power-good state and the power-good signal goes high after a 1-ms internal delay. If theoutput voltage falls below 90% of the target value, the power-good signal goes low after a 10- µs internal delay.
When the output voltage exceeds +5% above of the target value while SKIPSEL is selected as auto-skip or OOAskip-mode, the out-of-bound operation starts. During the out-of-bound condition, the controller operates in forcedPWM-only mode. Turning on the low-side MOSFET beyond the zero inductor current quickly discharges theoutput capacitor. During this operation, the cycle-by-cycle negative overcurrent limit is also valid. Once the outputvoltage becomes back within regulation range, the controller resumes to auto-skip or OOA skip mode."
The TPS51427 discharges the output when ENx is low, or when the controller is shut down by the circuitprotection functions (OVP, UVP, UVLO, and thermal shutdown). The TPS51427 discharges the outputs using aninternal, 17- ΩMOSFET that is connected to VOUTx and PGND. The external low-side MOSFET does not turnon during the output discharge operation to avoid the possibility of causing a negative voltage at the output. Theoutput discharge time constant is a function of the output capacitance and the resistance of the internaldischarge MOSFET. This discharge ensures that on device restart, the regulated voltage always starts from 0 V.If an SMPS restarts before the discharge completes, the discharge action is terminated and switching resumesafter the reference level (ramped up by an internal digital-to-analog converter, or DAC) returns to the remainingoutput voltage. When shutdown mode activates, the 3.3-V VREF3 remains on.
The 2-V reference is useful for generating auxiliary voltages. The tolerance for this reference voltage is ± 1.25%over a 50- µA load and – 40 ° C to +85 ° C ambient temperature range. This reference is enabled when ENLDOgoes high, and shuts down after both switching channels are turned off and ENLDO is shut down. If this output isforcibly tied to ground, both SMPSs are turned off without a latch. Bypass the VREF2 pin to GND with aminimum 0.1- µF ceramic capacitor.
The 3.3-V reference (VREF3) is accurate to ± 1.5% over temperature, making VREF3 useful as a precisionsystem reference for the real-time clock (RTC) circuit in many notebook applications. VREF3 can supply up to 10mA for external loads. Bypass VREF3 to GND with a 1- µF capacitor. VREF3 is activated when VIN rises above2.1 V, and remains on even when the SMPS and LDO are both shut down. VREF3 is deactivated if VIN fallsbelow 1.8 V. In thermal shutdown conditions, VREF3 remains activate.
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LDO
( )
LDO min LDO
5 V
C 4.7 F
V
= ´ m
(2)
CURRENT SENSING AND OVERCURRENT PROTECTION
( )
f
VIN VOUT VOUT
RIPPLE
OCP TRIP TRIP
VIN
V V V
I1
I I I
2 2 L V
æ ö
- ´
æ ö æ ö
= + = + ´ ç ÷
ç ÷ ç ÷ ç ÷
´ ´
è ø
è ø è ø
(3)
TPS51427
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When the LDOREFIN pin is connected to GND, the TPS51427 internal linear regulator produces a fixed 5-V LDOoutput; when LDOREFIN is connected to V5FILT, the linear regulator produces a fixed 3.3-V LDO output. TheLDO regulator can supply up to 100 mA for external loads. Bypass the LDO with a minimum 4.7- µF ceramiccapacitor. When the LDO is fixed at 5 V, and VSW voltage is equal to or greater than 4.7 V, the 5 V LDOswitches off after a 3.8-ms delay, and the 5V rail is bootstrapped to the VSW output, thereby improving theefficiency of the converter. A glitch-free switchover is also accomplished. The switchover impedance from theVSW pin to the LDO pin is typically 0.7 Ω. In the same way, when the LDO is fixed at 3.3-V and the VSW voltageis equal to or greater than 3.15 V, the 3.3-V LDO switches off after a delay of 4 ms, and the 3.3-V rail isbootstrapped to the VSW output.
In adjustable mode, the LDO output can be set from 0.7 V to 4.5 V. The LDO output voltage is equal to two timesthe LDOREFIN voltage. There is no switchover action in adjustable mode.
For the 5-V LDO output, a 4.7- µF ceramic capacitor (minimum) is required from the LDO to GND. For the 3.3-VLDO output, a 10- µF ceramic capacitor (minimum) is required from the LDO to GND. If a lower voltage LDOoutput is desired, scale the output capacitance of the LDO according to Equation 2 .
For example, if V
LDO
= 1 V, C
LDO(min)
= 23.5 µF. Use the standard capacitance value to choose 27 µF for the 1-VLDO output.
In order to provide the most cost-effective solution, the TPS51427 supports low-side MOSFET R
DS(on)
sensing forovercurrent protection. In any setting, the output signal of the current amplifier becomes 100 mV at theovercurrent limit (OCL) set point. This configuration means that the current sensing amplifier normalizes thecurrent information signal based on the OCL setting.
The TPS51427 supports cycle-by-cycle OCL control. The controller does not allow the next ON cycle while thecurrent level is above the trip threshold. The overcurrent trip threshold voltage is determined by the TRIPx pin asTable 3 shows. The TRIPx terminal sources 5- µA current with a 2900ppm/ ° C temperature slope, with respect toits +25 ° C value, to compensate the temperature dependency of the MOS R
DS(on)
. The trip level is set to thevoltage across R
TRIPx
when TRIPx is between 200 mV and 2 V at room temperature. When the TRIPx pin is tiedto 5 V directly, the controller defaults to 100 mV fixed OCL setting. With this option, temperature compensation isnot obtained.
Table 3. Overcurrent Trip Threshold Voltage
TRIPx 0.2 V to 2 V 5 V
OCL threshold in R
DS(on)
sensing 20 mV to 200 mV 100 mV
Temperature Coefficient (ppm/ ° C) 2900 None
The overcurrent condition is detected during the OFF state; therefore, I
TRIP
sets the valley level of the inductorcurrent. Thus, the load current at overcurrent threshold, I
OCP
, can be calculated in Equation 3 .
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OVERVOLTAGE/UNDERVOLTAGE PROTECTION
UNDERVOLTATGE LOCKOUT (UVLO) PROTECTION
THERMAL SHUTDOWN
TPS51427
SLUS819B – APRIL 2008 – REVISED SEPTEMBER 2008 ................................................................................................................................................
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In an overcurrent condition, the current to the load exceeds the current to the output capacitor. As a result, theoutput voltage tends to drop, and ends up crossing the undervoltage protection threshold, and the device shutsdown.
The TPS51427 also supports a cycle-by-cycle negative overcurrent limit in PWM-only mode. The negativeovercurrent limit is set to be negative, but at the same absolute value as the positive overcurrent limit. If theoutput voltage continues to rise, the bottom MOSFET is always on; the inductor current reduces and reversedirection after it reaches zero. When there is too much negative current in the inductor, the bottom MOSFETturns off and a new on-time period is initiated; that is, the top MOSEFET turns on to allow current to flow intoVIN. After the on-time expires, the bottom MOSFET turns on again. This protection ensures a maximumallowable discharge capability when the output voltage continues to rise, effectively reducing the possibility of theovervoltage protection (OVP) circuitry.
The TPS51427 monitors the feedback voltage for Channel1 and output voltage for Channel2 to detect both over-and undervoltage conditions. When the output voltage becomes 15% higher than the target value, the OVPcomparator output goes high after a 10- µs propagation delay; the circuit then latches the top MOSFET driver offand the bottom MOSFET driver on, until the negative OCL limit is reached. At that time, the bottom MOSFETturns off and the top MOSFET turns on for the minimum on-time. Once the minimum on-time expires, the bottomMOSFET turns on again. This process repeats until the valley current of the inductor is above the negativeovercurrent limit. Once the inductor valley current is greater than the OCL, the bottom MOSFET remains on untilit is reset. Upon OVP activation, both PGOODx outputs are pulled low.
When the voltage becomes lower than 70% of the target voltage, the undervoltage protection (UVP) comparatoroutput goes high and an internal UVP delay counter begins counting. After 1 ms, the TPS51427 latches both topand bottom MOSFETs off and shuts off the other channel as well. This function is enabled after the device softstart completes.
The TPS51427 has V5FILT undervoltage lockout (UVLO) protection. When the V5FILT voltage is lower than theUVLO threshold voltage, the TPS51427 shuts off. This feature is a non-latched protection circuit.
The TPS51427 monitors the temperature of the die itself. If the temperature exceeds the threshold value(typically +140 ° C), the TPS51427 shuts down. This feature is a non-latched protection circuit.
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TYPICAL CHARACTERISTICS
SYSTEM DUAL RAILS
0.001
0
101
20
h– Efficiency – %
0.10.01
60
80
40
100
VIN (V)
8
12
20
IOUT – Output Current – A
CH1
Auto-Skip Mode
VTONSEL = V5FILT
0.001
0
101
20
h– Efficiency – %
0.10.01
60
80
40
100
VIN (V)
8
12
20
IOUT – Output Current – A
CH2
Auto-Skip Mode
VTONSEL = V5FILT
0.001
0
101
20
h– Efficiency – %
0.10.01
60
80
40
100
IOUT – Output Current – A
VIN (V)
8
12
20
CH1
OOA Mode
VTONSEL = V5FILT
0.001
0
20
h– Efficiency – %
60
80
40
100
IOUT – Output Current – A
101
VIN (V)
8
12
20
0.10.01
CH2
OOA Mode
VTONSEL = V5FILT
TPS51427
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................................................................................................................................................ SLUS819B – APRIL 2008 – REVISED SEPTEMBER 2008
EFFICIENCY EFFICIENCYvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 1. 5-V Efficiency in Auto-Skip Mode Figure 2. 3.3-V Efficiency in Auto-Skip Mode
EFFICIENCY EFFICIENCYvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 3. 5-V Efficiency in OOA Mode Figure 4. 3.3-V Efficiency in OOA Mode
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0.001
0
101
20
h– Efficiency – %
0.10.01
60
80
40
100
VIN (V)
8
12
20
IOUT – Output Current – A
CH1
PWM Mode
VTONSEL = V5FILT
0.001
0
20
h– Efficiency – %
60
80
40
100
IOUT – Output Current – A
1010.10.01
CH2
PWM Mode
VTONSEL = V5FILT
VIN (V)
8
12
20
TPS51427
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TYPICAL CHARACTERISTICS (continued)
EFFICIENCY EFFICIENCYvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 5. 5-V Efficiency in PWM Mode Figure 6. 3.3-V Efficiency in PWM Mode
OUTPUT VOLTAGE OUTPUT VOLTAGEvs vsINPUT VOLTAGE INPUT VOLTAGE
Figure 7. 5-V Line Regulation Figure 8. 3.3-V Line Regulation
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0.001
4.98
1010.01
OOA
Auto-Skip
PWM Only
IOUT – Output Current – mA
VOUT – Output Voltage – V
5.00
5.02
5.06
5.08
5.10
5.12
5.14
5.16
5.18
Mode
OOA
Auto-Skip
PWM Only
5.04
0.1
CH1
VIN = 12 V
VTONSEL = V5FILT
0.001
3.24
1010.01
OOA
Auto-Skip
PWM Only
IOUT – Output Current – mA
VOUT – Output Voltage – V
3.26
3.28
3.30
3.32
3.34
3.36
3.38
3.40
3.42
Mode
OOA
Auto-Skip
PWM Only
0.1
CH2
VIN = 12 V
VTONSEL = V5FILT
LOW VOLTAGE DUAL RAILS
0.001
0
101
20
h– Efficiency – %
0.10.01
60
80
40
100
VIN (V)
8
12
20
IOUT – Output Current – A
CH1
Auto-Skip Mode
VTONSEL = GND
10
30
50
70
90
0.001
0
101
20
h– Efficiency – %
0.10.01
60
80
40
100
VIN (V)
8
12
20
IOUT – Output Current – A
CH2
Auto-Skip Mode
VTONSEL = GND
10
30
50
70
90
TPS51427
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................................................................................................................................................ SLUS819B – APRIL 2008 – REVISED SEPTEMBER 2008
TYPICAL CHARACTERISTICS (continued)
OUTPUT VOLTAGE OUTPUT VOLTAGEvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 9. 5-V Load Regulation Figure 10. 3.3-V Load Regulation
EFFICIENCY EFFICIENCYvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 11. 1.5-V Efficiency in Auto-Skip mode Figure 12. 1.05-V Efficiency in Auto-Skip Mode
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0.001
0
20
h– Efficiency – %
60
80
40
100
IOUT – Output Current – A
101
VIN (V)
8
12
20
0.10.01
CH1
OOA Mode
VTONSEL = GND
10
30
50
70
90
0.001
0
101
20
h– Efficiency – %
0.10.01
60
80
40
100
VIN (V)
8
12
20
IOUT – Output Current – A
CH2
Auto-Skip Mode
VTONSEL = GND
0.001
0
101
20
h– Efficiency – %
0.10.01
60
80
40
100
VIN (V)
8
12
20
IOUT – Output Current – A
CH1
PWM Mode
VTONSEL = GND
0.001
0
20
h– Efficiency – %
60
80
40
100
IOUT – Output Current – A
1010.10.01
CH2
PWM Mode
VTONSEL = GND
VIN (V)
8
12
20
TPS51427
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TYPICAL CHARACTERISTICS (continued)
EFFICIENCY EFFICIENCYvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 13. 1.5-V Efficiency in OOA mode Figure 14. 1.05-V Efficiency in OOA mode
EFFICIENCY EFFICIENCYvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 15. 1.5-V Efficiency in PWM mode Figure 16. 1.05-V Efficiency in PWM mode
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0.001
1.500
1010.01
OOA
Auto-Skip
PWM Only
IOUT – Output Current – A
VOUT – Output Voltage – V
1.505
1.515
1.520
1.525
1.530
Mode
OOA
Auto-Skip
PWM Only
1.510
0.1
CH1
VIN = 12 V
VTONSEL = GND
0.001
1.054
1010.01
OOA
Auto-Skip
PWM Only
IOUT – Output Current – mA
VOUT – Output Voltage – V
1.056
1.058
1.062
1.066
1.068
1.070
1.072
1.074
1.076
Mode
OOA
Auto-Skip
PWM Only
1.060
0.1
1.064
CH2
VIN = 12 V
VTONSEL = GND
TPS51427
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................................................................................................................................................ SLUS819B – APRIL 2008 – REVISED SEPTEMBER 2008
TYPICAL CHARACTERISTICS (continued)
OUTPUT VOLTAGE OUTPUT VOLTAGEvs vsINPUT VOLTAGE INPUT VOLTAGE
Figure 17. 1.5-V Line Regulation Figure 18. 1.05-V Line Regulation
OUTPUT VOLTAGE OUTPUT VOLTAGEvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 19. 1.5-V Load Regulation Figure 20. 1.05-V Load Regulation
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0
3.0
20010050
VIN (V)
6
12
25
VIN = 6 V
VIN = 12 V
VIN = 25 V
IOUT – Output Current – mA
3.5
4.0
4.5
5.0
5.5
150
VOUT – Output Voltage – V
0
2.0
20010050
VIN (V)
6
12
25
VIN = 6 V
VIN = 12 V
VIN = 25 V
IOUT – Output Current – mA
2.5
3.0
3.5
4.0
150
VOUT – Output Voltage – V
0
1.991
15010050
VIN = 6 V
VIN = 12 V
VIN = 25 V
IOUT – Output Current – mA
VVREF – Voltage Reference – V
1.992
1.993
1.994
1.995
1.996
1.997
1.998
1.999
2.000
VIN (V)
6
12
25
TPS51427
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TYPICAL CHARACTERISTICS (continued)
OUTPUT VOLTAGE OUTPUT VOLTAGEvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 21. 5-V LDO Load Regulation Figure 22. 3.3-V LDO Load Regulation
OUTPUT VOLTAGE OUTPUT VOLTAGEvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 23. 2-V Reference Load Regulation Figure 24. 3.3-V Reference Load Regulation
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5
100
252010
VIN – Input Voltage – V
fSW – Frequency – kHz
200
300
500
400
15
VTONSEL (V)
VV5FILT
GND
VVREF2
VTONSEL= GND
VTONSEL = VV5FILT
VTONSEL = VVREF2
5
100
252010
VIN – Input Voltage – V
fSW – Frequency – kHz
200
300
400
15
VTONSEL (V)
VV5FILT
GND
VVREF2
VTONSEL= GND VTONSEL = VV5FILT
VTONSEL = VVREF2
500
600
0
fSW – Frequency – kHz
50
200
250
100
150
OOA
Auto-Skip
CH1
VIN = 12 V
VTONSEL = VV5VFILT
0.001 1010.01
IOUT – Output Current – A
0.1
0
fSW – Frequency – kHz
100
200
400
300
CH2
VIN = 12 V
VTONSEL = VV5VFILT
50
150
350
250
OOA
Auto-Skip
0.001 1010.01
IOUT – Output Current – A
0.1
TPS51427
www.ti.com
................................................................................................................................................ SLUS819B – APRIL 2008 – REVISED SEPTEMBER 2008
TYPICAL CHARACTERISTICS (continued)
FREQUENCY FREQUENCYvs vsINPUT VOLTAGE INPUT VOLTAGE
Figure 25. Channel 1 (5-V Setting) Figure 26. Channel 2 (3.3-V Setting)
FREQUENCY FREQUENCYvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 27. Load Current (5-V Setting) Figure 28. Load Current (3.3-V Setting)
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5
100
251510
VIN – Input Voltage – V
300
400
500
20
200
VTONSEL= GND
VTONSEL= VVREF2 VTONSEL= VV5FILT
VTONSEL (V)
GND
VREF2
V5FILT
fSW – Frequency – kHz
5
100
251510
VIN – Input Voltage – V
fSW – Frequency – kHz
300
400
600
20
200
500
VTONSEL (V)
GND
VREF2
V5FILT
VTONSEL= VVREF2 VTONSEL= VV5FILT
VTONSEL= GND
0.001
0
1010.01
OOA
Auto-Skip
IOUT – Output Current – A
50
200
250
300
350
100
0.1
CH1
VIN = 19 V
VTONSEL = GND
150
fSW – Frequency – kHz
0.001
0
1010.01
IOUT – Output Current – A
50
200
250
300
350
100
0.1
CH2
VIN = 19 V
VTONSEL = GND
150
OOA
Auto-Skip
fSW – Frequency – kHz
TPS51427
SLUS819B – APRIL 2008 – REVISED SEPTEMBER 2008 ................................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS (continued)
FREQUENCY FREQUENCYvs vsINPUT VOLTAGE INPUT VOLTAGE
Figure 29. Channel 1 (1.5-V Setting) Figure 30. Channel 2 (1.05-V Setting)
FREQUENCY FREQUENCYvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 31. Load Current (5-V Setting) Figure 32. Load Current (3.3-V Setting)
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0
150
531
VTONSEL= GND
VOUT – Output Voltage – V
fSW – Frequency – kHz
200
300
400
450
4
VTONSEL (V)
GND
2
5
250
350
2
VTONSEL= 2 V
VTONSEL= 5 V
0
200
3.0
1.5
0.5
VTONSEL= GND
VOUT – Output Voltage – V
fSW – Frequency – kHz
250
350
450
500
2.5
VTONSEL (V)
GND
2
5
300
400
1.0
VTONSEL= 2 V
VTONSEL= 5 V
2.0
TPS51427
www.ti.com
................................................................................................................................................ SLUS819B – APRIL 2008 – REVISED SEPTEMBER 2008
TYPICAL CHARACTERISTICS (continued)
FREQUENCY FREQUENCYvs vsOUTPUT VOLTAGE OUTPUT VOLTAGE
Figure 33. Channel 1 Setting Figure 34. Channel 2 Setting
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TYPICAL CHARACTERISTICS (continued)
TPS51427
SLUS819B – APRIL 2008 – REVISED SEPTEMBER 2008 ................................................................................................................................................
www.ti.com
Figure 35. Channel 1 Gate Driver Performance Figure 36. Channel 2 Gate Driver Performance
Figure 37. Channel 1 Load Step Figure 38. Channel 1 Load Release
Figure 39. Channel 2 Load Step Figure 40. Channel 2 Load Release
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APPLICATION INFORMATION
Table 4. List of Materials
TPS51427
www.ti.com
................................................................................................................................................ SLUS819B – APRIL 2008 – REVISED SEPTEMBER 2008
COMPONENTS CONFIGURATION NO. 1 CONFIGURATION NO. 2 CONFIGURATION NO. 3
400 kHz/300 kHz Channel1: 5 400 kHz/500 kHz Channel1: 400kHz/500kHz Channel1:V/8 A (fixed) Channel2: 3.3 V/10 1.5V/10A (fixed) Channel2: 1.05 1.8V/10A (adj) Channel2:A (fixed) V/15 A(fixed) 1.1V/15A (adj)Input voltage 8 V ≤V
IN
≤22 V4 x 10 µF, 25 V 4 x 10 µF, 25 V 4 x 10 µF, 25 VInput MLCC capacitors Murata Murata MurataGRM31CR61E106KA12L GRM31CR61E106KA12L GRM31CR61E106KA12L
Channel1
1 x 330 µF, 6 V, 25 m Ω, Sanyo, 2 x 330 µF, 2.5 V, 12 m Ω , 2 x 330 µF, 2.5 V, 12 m Ω,Output capacitor
6TPE330ML Sanyo, 2R5TPE330MC Sanyo, 2R5TPE330MCSumida, 4.3 µH, Sumida, 2.2 µH, Sumida, 2.2 µH,Output inductor
CEP125NP-4R3M-U, 11.4 m ΩCEP125NP-2R2M-U, 5.4 m ΩCEP125NP-2R2M-U, 5.4 m Ω
International Rectifier, IRF7807V, International Rectifier, IRF7807V, International Rectifier, IRF7807V,High-side MOSFET
30 V, 8.3 A, 0.017 Ω30V, 8.3A, 0.017 Ω30V, 8.3A, 0.017 Ω
International Rectifier,
International Rectifier, IRF7832, International Rectifier, IRF7832,Low-side MOSFET IRF7811AV, 30 V, 10.8 A, 0.011
30V, 20A, 0.004 Ω30V, 20A, 0.004 ΩΩ
R
OCL
267 k Ωfor OCL of 10 A to 14 A 110 k Ωfor OCL of 12 A to 18 A 110 k Ωfor OCL of 12 A to 18 AR
UPPER_DIV
39.2 k Ω, 1%Tie VFB1 to GND Tie VFB1 to V5FILTR
LOWER_DIV
24.9 k Ω, 1%
Channel2
1 x 330 µF, 4 V, 18 m ΩSanyo, 2 x 470 µF, 2.5 V, 9 m Ω, Sanyo, 2 x 470 µF, 2.5 V, 9 m Ω , Sanyo,Output capacitor
4TPE330MI 2R5TPE470M9 2R5TPE470M9Sumida, 3.2 µH, 8.0 m Ω, Vishay, 1 µH, 3 m Ω, Vishay, 1 µH, 3 m Ω,Output inductor
CEP125NP-3R2M-U IHLP5050CE IHLP5050CEInternational Rectifier, IRF7807V, International Rectifier, IRF7821, International Rectifier, IRF7821,High-side MOSFET
30 V, 8.3 A, 0.017 Ω30 V, 13 A, 0.009 Ω30 V, 13 A, 0.009 Ω
International Rectifier, IRF7832, International Rectifier, IRF7832, International Rectifier, IRF7832,Low-side MOSFET
30 V, 20 A, 0.004 Ω30 V, 20 A, 0.004 Ω30 V, 20 A, 0.004 Ω
R
OCL
110 k Ωfor OCL of 12 A to 18 A 169 k Ωfor OCL of 18 A to 26 A 169 k Ωfor OCL of 18 A to 26 AR
UPPER_DIV
44.2 k Ω, 1%Tie REFIN2 to V5FILT Tie REFIN2 to VREF3R
LOWER_DIV
54.9 k Ω
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 27
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TPS51427
SLUS819B – APRIL 2008 – REVISED SEPTEMBER 2008 ................................................................................................................................................
www.ti.com
Figure 41. Configuration 1: System Rail
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TPS51427
www.ti.com
................................................................................................................................................ SLUS819B – APRIL 2008 – REVISED SEPTEMBER 2008
Figure 42. Configuration 2: Low Voltage Rail (Fixed Voltage Settings)
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TPS51427
SLUS819B – APRIL 2008 – REVISED SEPTEMBER 2008 ................................................................................................................................................
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Figure 43. Configuration 3: Low-Voltage Dual Rail (Adjustable Voltage Settings)
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Loop Compensation and External Part Selection
Switching
Logic
DRVH
TPS51427
DRVL
One Shot
Blanking
Period
+
RFB
Q1
Q2
IL
ESR
COUT
L
O
A
D
ILOAD
VOUT
VFB
High-Speed Comparator VREF
UDG-08056
VIN
Lo
I
tON
tON triggered when VOUT declines to VREF level
VRIPPLE = IRIPPLE x ESR
ILOAD
VREF
IRIPPLE
VRIPPLE
TPS51427
www.ti.com
................................................................................................................................................ SLUS819B – APRIL 2008 – REVISED SEPTEMBER 2008
A simplified buck converter system using D-CAP mode is shown below in Figure 44 .
Figure 44. D-CAP Mode Operation Schematic
Figure 45. D-CAP Mode Operation Waveforms
The output voltage is compared with an internal reference voltage through scaling. The PWM comparatordetermines the timing to turn on the high side MOSFET. The gain and speed of the comparator is high enough tokeep the voltage at the beginning of each on cycle (or the end of off cycle) substantially constant. The DC outputvoltage changes when the input voltage changes due to the fact that voltage regulation is maintained at thevalley point. Therefore, as the output ripple amplitude increases when the input voltage increases, the DC outputvoltage increases as well.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 31
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SW
0
OUT
f
1
f2 ESR C 4
= £
p´ ´
(4)
( )
( )
()
( ) ( )
( )
()
( )
f f
OUT OUT OUT OUT
IN max IN max
IND ripple IN max OUT max IN max
V V V V V V
1 3
LI V I V
- ´ - ´
= ´ = ´
´ ´
(5)
OUT
RIPPLE
1.5%
ESR V I
= ´
(6)
TPS51427
SLUS819B – APRIL 2008 – REVISED SEPTEMBER 2008 ................................................................................................................................................
www.ti.com
For loop stability, the 0-dB frequency, f
0
, defined in Equation 4 must be lower than of the switching frequency.
As f
0
is determined solely by the output capacitor ’ s characteristics, loop stability of D-CAP mode is determined bythe capacitor ’ s chemistry. For example, the output capacitance of specialty polymer capacitors (SP-CAP) is onthe order of several hundred microfarads and an ESR of approximately 10 m Ω. These values yield a 0-dBfrequency of 100 kHz or less and the loop is stable. However, ceramic capacitors yield a f
0
at more than 700 kHzwhich is not suitable for this operational mode.
Although D-CAP mode provides many advantages such as ease-of-use, minimum external components, andextremely fast transient response, a sufficient amount of feedback signal needs to be provided to reduce the jitterlevel. In a TPS51427 design, it is generally recommended to optimize the output voltage ripple at around 1.5% ofthe targeted DC voltage in both Auto-skip and PWM mode operations. For example, if V
VOUT1
= 1.5 V, thedesired output ripple should be at least 1.5 V x 1.5% = 22.5 mV. This can be achieved by taking advantage ofthe output bulk capacitor ESR.
The external component selection is much simpler in D-CAP mode. Below is a simplified design proceduretargeting to the customers that are very familiar with SMPS design.1. Determine the output voltage setting.
For the fixed 5 V/3.3 V option, tie VFB1 pin to GND and REFIN2 to V5FILT. For the fixed 1.5 V/1.05 Vconfiguration, tie VFB1 to V5FILT and REFIN2 to VREF3. TPS51427 also supports adjustable voltageoptions for both channels. The adjustable range for Channel1 is between 0.7 V and 5.9 V and for Channel2is between 0.5 V and 2.5 V. Figure 46 shows how to configure the adjustable voltage option for Channel1and Figure 47 shows the configuration for Channel2. Also, equations are provided in Table 5 to aid thedesign process.2. Choose the output inductor.
Output inductance is a function of V
IN
, V
OUT
,f
SW
and the desired ripple current. For available switchingfrequency settings with TPS51427, refer to Table 2 . The process of choosing the right output inductance isan iterative one; many considerations need to be taken, such as the desired transient response, efficiencyover the entire load range, load/line regulation, component availability and cost. Base the initial outputinductance value upon where the ripple current is 25% to 50% of the maximum loading current. For transientoptimized design, ripple factor can be higher; and for efficiency and load/line regulation optimized design, theripple factor can be lower.
3. Choose the output capacitor(s).
Organic semiconductor capacitors or specialty polymer capacitor(s) are recommended. Determine ESR tomeet the required ripple voltage indicated previous.
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( )
( )
LOW ER _ DIV VREF2
REFIN2
UPPER _ DIV LOWER _ DIV
R V
V
R R
æ ö
´
ç ÷
=ç ÷
+
è ø
UPPER _ DIV LOW ER _ DIV
VOUT1 VFB1
LOW ER _ DIV
R R
V V R
æ ö
+
ç ÷
= ´ ç ÷
è ø
10
11
VOUT1
VFB1
RUPPER_DIV
RLOWER_DIV
TPS51427
VBAT
UDG-08059
30
1
32
VOUT2
VREF2
REFIN2
RUPPER_DIV
RLOWER_DIV
TPS51427
VBAT
UDG-08060
Ripple Requirement in PWM Mode, Skip Mode and OOA Mode
TPS51427
www.ti.com
................................................................................................................................................ SLUS819B – APRIL 2008 – REVISED SEPTEMBER 2008
Table 5. Design Assistance
Channel1 Channel2
FIXED
1.5 V by shorting VFB1 to 3.3 V by shorting 1.05 V by shortingVOLTAGE 5 V by shorting VFB1 to GND
V5FILT REFIN2 to V5FILT REFIN2 to VREF3OPTIONS
VOUT2 is set by R
UPPER_DIV
, R
LOWER_DIV
, andVFB1 Figure 47VOUT1 is set by R
UPPER_DIV
, R
LOWER_DIV
, and VFB1 Figure 46
ADJUSTABLE
VOLTAGE
(8)OPTIONS
(7)
wherewhere
•V
VREF
= 2 V•V
VFB1
= 0.7 V
•V
VOUT2
= V
REFIN2
Figure 46. Channel1 Adjustable Voltage Configuration Figure 47. Channel2 Adjustable Voltage Configuration
Since TPS51427 is a constant on time based controller, minimum ripple requirement at the output is necessaryto keep the main voltage loop stable. For loop stability, the ESR zero frequency, f
0
must be lower than 1/4 of theswitching frequency. This requirement can be easily fulfilled by using either POSCAP or SPCAP, due to theirsimilar characteristics. In order for a constant on time topology to work properly in a real world environment,there should not be any substantial phase delay contributed by the parasitic model of the output capacitors. Suchdelay would create distortion to the essential feedback signal necessary for the device to process.
In a TPS51427 design, it is generally recommended to optimize the output voltage ripple at around 1.5% of thetargeted DC voltage in both auto-skip and PWM mode operations. Higher ripple is better in terms of jitterperformance, however, lower ripple improves the line regulation and efficiency performance. It is a commonpractice as an attainable goal to optimize the converter design in terms of regulation and efficiency.
There is an additional voltage loop in the TPS51427 design that needs to be considered. OOA (out-of-audio)mode is designed to keep the minimum switching frequency at least 22 kHz in the light load/no load operation inorder to minimize the audible noise in the notebook system design during standby mode. Both main voltage loopand OOA loop require certain output ripple in order for the device to function properly. If the ripple is too low, themain loop is unstable. If OOA mode operation is desired, the recommended ripple cannot be more than 1% ofthe target DC voltage.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 33
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Current Limit Design Considerations
( ) ( )
OCLx DS on max MIN OCLvalley
V R I= ´
(9)
OCLx
OCLx
TRIP
V 5mV
R 10 I
æ ö
+
= ´ ç ÷
è ø
(10)
TRIPx TRIP OCLx
V I R= ´
(11)
( ) ( )
( )
TRIPx(max) TRIP OCLx J
V I R 1 TOL 1 2900ppm / C T 25 C= ´ ´ + ´ + ° ´ - °
(12)
Shutdown and Standby Control Logic
TPS51427
SLUS819B – APRIL 2008 – REVISED SEPTEMBER 2008 ................................................................................................................................................
www.ti.com
The current limit of Channel1 can be set using the TRIP1 pin via an external small resistor to GND. Channel2current limit can be set via the TRIP2 pin. The sourcing current for both Channel1 and Channel2 is 5 µA at roomtemperature with 2900 ppm/ ° C built-in temperature coefficient (to compensate for the temperature dependency ofthe R
DS(on)
of the low-side MOSFET). To take advantage of this feature, a good thermal coupling between theTPS51427 and the low-side MOSFET has to be obtained.
The current limit adjustment range (VTRIPx) is between 0.2 V and 2 V. If 5 V is applied to the pin (TRIP1 and/orTRIP2) directly (V
TRIPx
> 3.1 V), TPS51427 assumes a default of a 100-mV current limit without temperaturecompensation.
Once the minimum OCL level is determined, translate the minimum OCL point (DC) into minimum valley currentby subtracting of the peak-to-peak inductor current. Then convert the current information into the voltage level forthe TPS51427 to process.
where
•the low-side MOSFET at T
J
= 25 ° C
The external resistor can be set using Equation 10 .
where
•I
TRIP
= 5 µA and the tolerance is ± 5%
Once R
OCLx
is obtained, calculate the maximum V
TRIPx
voltage to make sure the maximum voltage on the TRIP1pin and/or the TRIP2 pin is less than 3.1 V for the entire operating temperature range.
The TRIPx voltage (V
TRIPx
) can be calculated by Equation 11 .
And maximum VTRIPx voltage can be calculated by Equation 12 .
where
•I
TRIP
= 5 µA•TOL = 5%•T
J
is assumed to be 125 ° C for the worst case junction temperature
Shutdown and Standby Control Logic Table
ENLDO LDO VREF2 VREF3 EN1 EN2 Channel1 Channel1
Low Off Low Low Low Off OffHigh On On Low Low Off OffHigh On On High High On OnHigh On On High Low On OffOn (if V
IN
> 2.2 V)High On On Low High Off OnOff (if V
IN
< 2 V)
On (after Channel1High On On High On
is up)On (after Channel2High On On High Onis up)
34 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
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Layout Guidelines
TPS51427
www.ti.com
................................................................................................................................................ SLUS819B – APRIL 2008 – REVISED SEPTEMBER 2008
1. Place one or two 10- µF ceramic capacitor(s) for V
IN
between two channels. Add 1000-pF ceramic capacitorbetween drain of the high-side MOSFET and source of the low-side MOSFET of each channel.2. Place V
IN
capacitors, VOUT1/VOUT2 capacitors and MOSFETs on the same side of the board. Positiveterminal of V
IN
capacitor and drain of the high-side MOSFET should be as close as possible (within 10 mm ifpossible). Also place negative terminals of both V
IN
capacitor and V
OUT
capacitor, and source of the low-sideMOSFET as close as possible.3. GND terminal of the device (signal GND) and PGND terminal (power GND) should be connected with thelowest impedance near the device.4. Trace of the switching node which is connected between the source of the high-side MOSFET, drain of thelow-side MOSFET and the upstream of the output inductor should be as short and thick as possible. Use 40mil of width (LL1 and LL2) for every ampere of load current.5. LL1 and LL2 serve the phase node connections for the high-side drivers. Also, they are served as input tothe current comparators for R
DS(on)
sensing and input voltage monitor for the on time control circuitry. Routethe return of these two traces to device pins as wide and short as possible to eliminate the parasiticinductance effect to the accuracy of the measurement.6. Place a low-pass filter MLCC capacitor with a value of 1- µF from V5FILT to GND, as close as possible.7. The output of LDO if configured as 5VLDO, requires at least 4.7- µF of MLCC to GND. If it is configured as3.3 VLDO, 10 µF of MLCC is recommended. For optimized stability and transient response, use a value of27 µF if the output of LDO is configured as 1VLDO. VREF2 requires 0.1- µF ceramic bypass capacitor toGND which should be placed as close to the device as possible. For VREF3, it generally requires a 1- µFceramic by pass capacitor to GND which also should be placed as close to the device as possible.8. Connect the overcurrent setting resistors from TRIP1/TRIP2 to GND. The traces from TRIP1/TRIP2 shouldbe routed as far as possible from the switching nodes.9. 9. In the case of adjustable output voltage with external resistor dividers, the discharge path (VOx) can sharethe trace to the output capacitor with the feedback trace (VFB1/REFIN2). Please place the voltage settingresistors as close to the device as possible. Route the VOx and feedback traces as far from the high speedswitching nodes as possible to avoid noise coupling.10. Connections from the drivers to the respective gate of the high-side or the low-side MOSFETs should be asshort as possible to reduce stray inductance. Use 0.65 mm (25 mils) or wider trace.11. All sensitive analog traces and components such as VO1/VO2, VFB1/REFIN2, VREF2, VREF3, EN1/EN2,GND, VSW, PGOOD1/PGOOD2, TRIP1/TRIP2, ENLDO, LDOREFIN, V5FILT, TONSEL and SKIPSELshould be placed away from high-voltage switching nodes such as LLx, DRVLx or DRVHx nodes to avoidcoupling. Use internal layer(s) as ground plane(s) and shield feedback traces from power traces andcomponents.
12. In order to effectively remove heat from the package, prepare thermal land and solder to the package ’ sthermal pad. 3 × 3 or more vias with a 0.33-mm (13mils) diameter connected from the thermal land to theinternal ground plane should be used to help dissipation. Connect GND to the thermal land directly.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 35
Product Folder Link(s): TPS51427
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS51427RHBR QFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
TPS51427RHBR QFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
TPS51427RHBT QFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
TPS51427RHBT QFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS51427RHBR QFN RHB 32 3000 367.0 367.0 35.0
TPS51427RHBR QFN RHB 32 3000 367.0 367.0 35.0
TPS51427RHBT QFN RHB 32 250 210.0 185.0 35.0
TPS51427RHBT QFN RHB 32 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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