OPTOPLANAR(R) HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER LSTTL TO PACKAGE 6 74OL6000 74OL6001 74OL6010 74OL6011 SYMBOL BUFFER 6 1 1 INVERTER 6 1 DESCRIPTION OPTOLOGICTM is the first family of truly logic compatible optically coupled logic interface gates. The family consists of four device types offering LSTTL to TTL and LSTTL to CMOS interfacing. Each of these interfacing functions is available as a buffer (A=B), or as an inverter (A=B). The LSTTL input compatibility is provided by an input integrated circuit, with industry standard logic levels. This input amplifier IC switches a temperature compensated current source driving a high speed 850 nm AlGaAs LED emitter. This novel integration scheme eliminates CTR degradation over time and temperature. The emitter is optically coupled to an integrated photodetector/high-gain, high-speed output amplifier IC. The superior 15kV/S common-mode noise rejection is ensured through the use of an optically transparent noise shield. The TTL compatible output has a totem-pole with a fan-out of 10. The CMOS compatible output has an open collector Schottkyclamped transistor that interfaces to any CMOS logic between 4.5 and 15 volts. The 74OL6010/11 may also by used to drive power MOSFETS or transistors up to 15 volts. The Optologic coupler family typically offers propagation of delays of 60 ns and can support 15 MBaud data communication. The two input chips and the output chip are assembled in a 6-pin DIP high insulation voltage plastic package. Fairchild's proprietary OPTOPLANAR(R) construction provides a withstand test voltage of 5300 VRMS (1 minute). FEATURES APPLICATIONS * Industry first LSTTL to TTL and LSTTL to CMOS complete logic-to-logic optocoupler * Incorporates LED drive circuitry -- use as logic gate * Very high speed * Choice of buffer or inverter * Choice of TTL or CMOS compatible output up to 15 volts * Fan-out of 10 TTL loads, fan-in 1 LSTTL load * Internal noise shield -- very high CMR of 15 kV/S * UL recognized (File #E90700) * Same noise immunity as LSTTL/TTL. * * * * * * * * (c) 2003 Fairchild Semiconductor Corporation Transmission line interface -- receiver and driver Excellent as bridged receiver in fast LAN highways Bus interface Logic family interface with ground loop noise elimination High speed AC/DC voltage sensing Driver for power semiconductor devices Level shifting Replaces fast pulse transformers Page 1 of 15 10/1/03 OPTOPLANAR(R) HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER LSTTL TO Vcc Vcc 22 k TYP. 74OL6000 74OL6001 74OL6010 74OL6011 Vcc 150 TYP. RL INPUT OUTPUT GND LSTTL INPUT CIRCUIT OUTPUT GND CMOS OUTPUT CIRCUIT GND TTL OUTPUT CIRCUIT All Inputs 74OL6000/01 Output 74OL6010/11 Output PIN CONFIGURATION 1-VCCI (Input VCC) 6-VCCO (Output VCC) 2-VIN (Data In) 5-VO (Data Out) 3-GND, (Input GND) 4-GNDO (Output GND) DEVICE CONFIGURATION Logic Compatibility Part Number Logic Function Output Configuration TTL BUFFER TOTEM POLE LSTTL TTL INVERTER TOTEM POLE 74OL 6010 LSTTL CMOS BUFFER OPEN COLLECTOR 74OL 6011 LSTTL CMOS INVERTER OPEN COLLECTOR Input Output 74OL 6000 LSTTL 74OL 6001 (c) 2003 Fairchild Semiconductor Corporation Page 2 of 15 10/1/03 OPTOPLANAR(R) HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS LSTTL TO TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER 74OL6000 74OL6001 74OL6010 74OL6011 SCHEMATIC 74OL OL6000 74OL OL6001 74OL OL6010 74OL OL6011 NOISE SHIELD NOISE SHIELD NOISE SHIELD NOISE SHIELD 1 6 1 6 1 6 1 6 2 5 2 5 2 5 2 5 3 4 3 4 3 4 3 4 LSTLL to TTL Buffer (c) 2003 Fairchild Semiconductor Corporation LSTLL to TTL Inverter LSTLL to CMOS Buffer Page 3 of 15 LSTLL to CMOS Inverter 10/1/03 OPTOPLANAR(R) HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER LSTTL TO 74OL6000 74OL6001 74OL6010 74OL6011 ELECTRICAL CHARACTERISTICS (TA = 0C to 70C Unless otherwise specified) Test Conditions Parameter Symbol Min Typ* Max Units Notes 74OL6000 TTL OUTPUT 74OL6000/01 Input Supply Voltage Output Supply Voltage High-Level Input Voltage Low-Level Input Voltage Input Clamp Voltage High-Level Input Current Low-Level Input Current Input Supply Current (high) Input Supply Current (low) VCCI VCCO VIH VIL VIK IIH IIL ICCIH ICCIL 4.5 4.5 2.0 High-Level Output Voltage VOH 2.4 Low-Level Output Voltage VOL 5.0 5.0 5.5 5.5 0.8 -1.2 1.0 40.0 -200.0 -400.0 10.0 14.0 10.0 14.0 3.0 V V V V V A A mA mA V VIN = 2.0 V V VIN = 0.8V mA VIN = VIH mA VIN = 0.8 V -40.0 mA VIN = VIH 0.6 0.3 0.5 -8.0 -10.0 High-Level Output Current IOH Low-Level Output Current IOL 16.0 Short-Circuit Output Current IOS -5.0 -25.0 Output Supply Current (high) ICCOH 9.0 15.0 mA VIN = VIH Output Supply Current (low) ICCOL 8.0 12.0 mA VIN = VIL 74OL6001 74OL6000/01 VCCI = 4.5 V, II = -18 mA VCCI = 5.5 V, VIH = 4.5 V VCCI = 5.5 V, VIL = 0.4 V VCCI = 5.5 V, VIN = VIH VCCI = 5.5 V, VIN = VIL VCCI = 4.5 V, VCCO = 4.5 V, VIN = 0.8 V IOH = -400 mA VCCI = 4.5 V, VCCO = 4.5 V, IOL = 16 mA VIN = 2.0V VCCI = 4.5 V, VCCO = 4.5 V, IOL = 4 mA VCCI = 4.5 V, VCCO = 4.5 V, VIN = VIL VOH = 2.4 V VCCI = 4.5 V, VCCO = 4.5 V, VIN = 2.0V VOL = 0.6 V VIN = VIL VCCI = 5.5 V, VCCO = 5.5 V, VCCI = 5.5 V, VO = VOH, VIN = VIL VCCO= 5.5 V VCCI = 5.5 V, VO = VOL, VIN = VIH VCCO = 5.5 V 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 *All typical values are at TA=25C SWITCHING CHARACTERISTCS (TA = 25C Unless otherwise specified) Parameter TTL OUTPUT 74OL6000/01 Propagation Delay Time For Output Low Level Propagation Delay Time For Output High Level Output Rise Time For Output High Level Output Fall Time For Output Low Level (c) 2003 Fairchild Semiconductor Corporation Symbol Min tPHL tPLH tr tf Typ Max Units 60 70 45 5 100 100 Page 4 of 15 ns ns n ns Test Conditions VCCI = 5 V, VCCO = 5 V Fig. Notes 15, 17 15, 17 15, 17 15, 17 1 1 1 1 10/1/03 OPTOPLANAR(R) HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER LSTTL TO 74OL6000 74OL6001 74OL6010 74OL6011 ELECTRICAL CHARACTERISTICS (TA = 0C to 70C Unless otherwise specified) Test Conditions Parameter Symbol Min Typ* Max Units Notes 74OL6010 74OL6011 CMOS OUTPUT 74OL6010/11 Input Supply Voltage Output Supply Voltage High-Level Input Voltage Low-Level Input Voltage Input Clamp Voltage High-Level Input Current Low-Level Input Current Input Supply Current (high) Input Supply Current (low) VCCI VCCO VIH VIL VIK IIH IIL ICCIH ICCIL 4.5 4.5 2.0 5.0 V V V 0.8 V -1.2 V 1.0 40.0 A -200.0 -400.0 A 10.0 14.0 mA 10.0 14.0 mA 5.5 15.0 0.6 Low-Level Output Voltage 0.4 VOL V VIN = 0.8V VIN = 2.0V 0.5 High-Level Output Current IOH Low-Level Output Current IOL Output Supply Current (high) Output Supply Current (low) 1.0 74OL6010/11 100.0 16.0 A mA 9.0 12.0 11.0 18.0 8.0 12.0 11.0 18.0 ICCOH ICCOL VIN = VIH VIN = VIL VIN = 0.8 V VIN = 2.0V mA VIN = VIH VIN = VIL mA VIN = VIL VIN = VIH VCCI = 4.5 V, II = -18 mA VCCI = 5.5 V, VIH = 4.5 V VCCI = 5.5 V, VIL = -0.4 V VCCI = 5.5 V, VIN = VIH VCCI = 5.5 V, VIN = VIL VCCI = 4.5 V, VCCO = 4.5 V, IOL = 16 mA VCCI = 4.5 V, VCCO = 4.5 V, IOL = 4 mA VCCI = 4.5 V, VOH = 15 V, VCCO = 4.5 - 15 V VCCI = 4.5 V, VOL = 0.6V, VCCO = 4.5 - 15 V VCCI = 5.5 V, VO = VOH, VCCO = 4.5 V VCCI = 5.5 V, VO = VOL, VCCO = 15 V VCCI = 5.5 V, VO = VOL, VCCO = 4.5 V VCCI = 5.5 V, VO = VOL, VCCO = 15 V 1 1,3 1 1 1 1 1 1 1 1 1 1 1 1 *All typical values are at TA=25C SWITCHING CHARACTERISTCS (TA = 25C Unless otherwise specified) Parameter TTL OUTPUT 74OL6010/11 Propagation Delay Time For Output Low Level Propagation Delay Time For Output High Level Output Rise Time For Output High Level Output Fail Time For Output Low Level (c) 2003 Fairchild Semiconductor Corporation Symbol Min tPHL tPLH tr tf Typ Max Units 60 100 50 5 Page 5 of 15 120 180 ns ns ns ns Test Conditions VCCI = 5 V, VCCO = 5 V, RL = 470 Fig. Notes 15, 18 15, 18 15, 18 15, 18 1 1 1 1 10/1/03 OPTOPLANAR(R) HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER LSTTL TO 74OL6000 74OL6001 74OL6010 74OL6011 ABSOLUTE MAXIMUM RATINGS (TA = 25C unless otherwise specified) Parameter Symbol Device Value Units Storage Temperature TSTG All -55 to +125 C Operating Temperature TOPR All 0 to +70 C Lead Solder Temperature TSOL All 260 for 10 sec C PD All 350 mW Input Supply Voltage VCCI All 7 V Input Voltage VIN All 7 V mA TOTAL DEVICE Power Dissipation EMITTER DETECTOR Average Output Current All 40 74OL6000/01 7 74OL6010/11 18 74OL6000/01 7 74OL6010/11 18 IO (avg) Output Supply Voltage VCCO Output Voltage VO V V ELECTRICAL CHARACERISTICS (TA = 0C to 70C Unless otherwise specified) Parameter Symbol Min Typ Max Units Test Conditions Fig. Notes Common Mode Transient Immunity at Logic High Level Output CMH 5000 15000 V/S Common Mode Transient Immunity at Logic Low Level Output CML -5000 -15000 V/S Common Mode Coupling Capacitance CCM 0.005 pF Capacitance (input-output) CI-O 0.7 pF VI-O = 0, f = 1 MHz 2 Withstand Insulation Test Voltage VISO VRMS TA = 25C, t = 1 min, II-O 1mA 2 Insulation Resistance RISO VI-O = 500 VDC 2 74OL6000/01/10/11 (c) 2003 Fairchild Semiconductor Corporation 5300 10 Page 6 of 15 VCCI = 5 V, VCCO = 5 V, VCM = 50 Vp-p 16, 19 16, 19 10/1/03 OPTOPLANAR(R) HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER LSTTL TO Figure 1. Input Current vs. Ambient Temperature 74OL6000 74OL6001 74OL6010 74OL6011 Figure 2. Input Supply Current vs. Ambient Temperature 15 100 IIH II - INPUT CURRENT (A) 0 -100 ICCI - INPUT SUPPLY CURRENT (mA) 14 VCCI = 5.5V VIH = 4.5V VIL = 0.4V IIL -200 13 12 ICCIH - 74OL6000-6010 ICCIL - 74OL6001-6011 11 10 9 8 ICCIH - 74OL6001-6011 ICCIL - 74OL6000-6010 7 6 -300 -40 -20 0 20 40 60 80 5 -40 100 Figure 3. Output Supply Current vs. Ambient Temperature IO - OUTPUT SUPPLY CURRENT (mA) ICCO - OUTPUT SUPPLY CURRENT (mA) ICCOH ICCOL ICCOH ICCOL ICCOH ICCOL 9 74OL6010/6011 VCCI = 5.5V VCCO = 15V 74OL6010/6011 74OL6000/6001 VCCI = 5.5V VCCO = 5.5V 60 80 100 -20 0 20 40 60 80 IOL 40 VCCI = 4.5V VCCO = 4.5V VOL = 0.6V VOH = 2.4V 30 20 10 0 IOH -10 (74OL6000/6001) -20 VCCI = 5.5V VCCO = 5.5V -30 -40 100 -20 0 20 40 60 80 100 TA - AMBIENT TEMPERATURE (C) Figure 5. High-Level Output Voltage vs. Ambient Temperature Figure 6. Low-Level Output Voltage vs. Ambient Temperature 0.5 VOL - LOW-LEVEL OUTPUT VOLTAGE (V) 5 VOH - HIGH-LEVEL OUTPUT VOLTAGE (V) 40 50 TA - AMBIENT TEMPERATURE (C) VCCI = 4.5V VCCO = 4.5V IOH = -400A 4 3 2 1 0 -40 20 60 12 0 -40 0 Figure 4. Output Current vs. Ambient Temperature 15 3 -20 TA - AMBIENT TEMPERATURE (C) TA - AMBIENT TEMPERATURE (C) 6 VCCI = 5.5V -20 0 20 40 60 80 @ IOL = 16mA 0.3 @ IOL = 4mA 0.2 VCCI = 4.5V VCCO = 4.5V 0.1 -40 100 -20 0 20 40 60 80 100 TA - AMBIENT TEMPERATURE (C) TA - AMBIENT TEMPERATURE (C) (c) 2003 Fairchild Semiconductor Corporation 0.4 Page 7 of 15 10/1/03 OPTOPLANAR(R) HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER LSTTL TO Figure 7. 74OL6010/11 Leakage Current vs. Ambient Temperature 74OL6000 74OL6001 74OL6010 74OL6011 Figure 8. 74OL6000/01 Switching Times vs. Ambient Temperature VCCIN = 4.5V VCCO = 15V VOUT = 15V 4 VCCI = 5.0V VCCO = 5.0V P.W = 200ns PERIOD = 1S 200 SWITCHING TIME (ns) IOH - LEAKAGE CURRENT (A) 5 3 2 tPLH tPHL tr 100 50 10 tf 5 1 0 -40 -20 0 20 40 60 80 1 -40 100 -20 TA - AMBIENT TEMPERATURE (C) RL = 470 P.W = 200ns PERIOD = 1S tPLH SWITCHING TIME (ns) 200 tPLH tr tPHL tr 100 50 10 tf tf 5 1 -40 -20 0 20 40 60 80 40 60 80 100 100 11 10 9 8 VCCO = 5V VCCO = 5V VOH = 2V VOL = 0.8V RL = 470 (74OL6010/6011) 7 6 5 4 3 2 1 0 500 TA - AMBIENT TEMPERATURE (C) 1000 15000 2000 2500 Figure 11. Supply Current vs. Supply Voltage Figure 12. Power Dissipation vs. Ambient Temperature PT - TOTAL PACKAGE POWER DISSIPATION (mW) VCM - COMMON MODE TRANSIENT 12 ICCO ICC 10 ICC - SUPPLY CURRENT (mA) 20 Figure 10. Common Mode Rejection vs. Common Mode Voltage CM - COMMON MODE TRANSIENT IMMUNITY (KV/S) Figure 9. 74OL6010/11 Switching Times vs. Ambient Temperature VCCO = 5V VCCO = 15V VCCI = 5V 0 TA - AMBIENT TEMPERATURE (C) 8 6 VCCO RANGE FOR 74OL6000/6001 4 2 0 4 5 6 7 8 9 10 11 12 13 300 @TA = 55C 200 VCCI = 5.5V @TA = 70C @TA = 85C 100 VCCI = 4.5V 0 4 14 15 5 6 7 8 9 10 11 12 13 14 15 VCCO - OUTPUT SUPPLY VOLTAGE (V) VCC - SUPPLY VOLTAGE (V) (c) 2003 Fairchild Semiconductor Corporation MAXIMUM ALLOWABLE POWER DISSIPATION @ TA = 25C Page 8 of 15 10/1/03 OPTOPLANAR(R) HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER LSTTL TO Figure 14. Input Current vs. Input Voltage Figure 13. Input Threshold Voltage vs. Ambient Temperature 1.6 100 1.5 IIN - INPUT CURRENT (A) VINTH - INPUT THRESHOLD VOLTAGE (V) 74OL6000 74OL6001 74OL6010 74OL6011 1.4 1.3 1.2 1.1 -100 -200 VCCI = 5.0V VCCO = 5.0V 1.0 0 VCCI = 4.5V 0.0 -40 -300 -20 0 20 40 60 80 0 100 1 2 TA - AMBIENT TEMPERATURE (C) 3 4 5 6 VIN - INPUT VOLTAGE (V) Figure 15. Switching Time Test Circuit Figure 16. Common Mode Rejection Test Circuit VCCO +5 V VCCI +5 V 1 .1F .1F PULSE GEN PW =200ns PERIOD = 1S tr = 5ns Zo = 50 VCCO +5 V 6 .1F 470 (74OL6010/11) 2 5 3 4 H/L 1 6 .1F 470 (74OL6010/11) 1k 2 5 3 6 L/H CL* VO *CL = 15pF STRAY CAPACITANCE INCLUDING PROBE - + VCM (c) 2003 Fairchild Semiconductor Corporation Page 9 of 15 10/1/03 OPTOPLANAR(R) HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER LSTTL TO 74OL6000 74OL6001 74OL6010 74OL6011 Figure 18. Switching Parameters 74OL6010/11 Figure 17. 74OL6000/01 Switching Times vs. Ambient Temperature INPUT, VI 3.2V INPUT, VI 3.2V 1.3V 1.3V tPLH tPLH tPHL tPHL 90% 90% OUTPUT, VO (74OL6000) OUTPUT, VO (74OL6010) 1.3V 10% 50% 10% tr tf tr tf tf tr tf tr 90% 90% OUTPUT, VO (74OL6001) 1.3V 10% tPHL 50V 0V VOH = tPLH Figure 20. Suggested PCB Lay-Out Figure 19. Common Mode Rejection Waveforms dVCM dt 10% tPHL tPLH VCM 50% OUTPUT, VO (74OL6011) INPUT VCC BUS VCM tr INPUT GND BUS OUTPUT GND BUS OUTPUT VCC BUS CMH 1 6 2 5 3 4 VO = 2.0V (MIN.) DATA IN .1F .1F DATA OUT VO = 0.8V (MAX.) VOL CML NOTE 1. The VCCO and VCCI supply voltages to the device must each be bypassed by a 0.1F capacitor or larger. This can be either a ceramic or solid tantalum capacitor with good high frequency characteristics. Its purpose is to stabilize the operation of the highgain amplifiers. Failure to provide the bypass will impair the DC and switching properties. The total lead length between capacitor and optocoupler should not exceed 1.5mm. See Fig. 20. 2. Device considered a two-terminal device. Pins 1, 2 and 3 shorted together, and Pins 4, 5 and 6 shorted together. 3. For example, assuming a VCCI of 5.0V, and an ambient temperature of 70C, the maximum allowable VCCO is 12.1V. (c) 2003 Fairchild Semiconductor Corporation Page 10 of 15 10/1/03 OPTOPLANAR(R) HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER LSTTL TO Package Dimensions (Through Hole) 74OL6000 74OL6001 74OL6010 74OL6011 Package Dimensions (Surface Mount) PIN 1 ID. 0.350 (8.89) 0.330 (8.38) 3 2 PIN 1 ID. 1 0.270 (6.86) 0.240 (6.10) 0.350 (8.89) 0.330 (8.38) 4 SEATING PLANE SEATING PLANE 0.270 (6.86) 0.240 (6.10) 0.070 (1.78) 0.045 (1.14) 0.200 (5.08) 0.115 (2.92) 5 6 0.300 (7.62) TYP 0.070 (1.78) 0.045 (1.14) 0.200 (5.08) 0.165 (4.18) 0.020 (0.51) MIN 0.154 (3.90) 0.100 (2.54) 0.016 (0.41) 0.008 (0.20) 0.022 (0.56) 0.016 (0.41) 0.016 (0.40) 0.008 (0.20) 0.022 (0.56) 0.016 (0.41) 0 to 15 0.020 (0.51) MIN 0.100 (2.54) TYP 0.016 (0.40) MIN 0.315 (8.00) MIN 0.405 (10.30) MAX 0.300 (7.62) TYP Lead Coplanarity : 0.004 (0.10) MAX 0.100 (2.54) TYP Package Dimensions (0.4" Lead Spacing) Recommended Pad Layout for Surface Mount Leadform PIN 1 ID. 0.070 (1.78) 0.270 (6.86) 0.240 (6.10) 0.060 (1.52) SEATING PLANE 0.350 (8.89) 0.330 (8.38) 0.415 (10.54) 0.070 (1.78) 0.045 (1.14) 0.100 (2.54) 0.295 (7.49) 0.030 (0.76) 0.200 (5.08) 0.135 (3.43) 0.154 (3.90) 0.100 (2.54) 0.004 (0.10) MIN 0.016 (0.40) 0.008 (0.20) 0 to 15 0.022 (0.56) 0.016 (0.41) 0.100 (2.54) TYP 0.400 (10.16) TYP NOTE All dimensions are in inches (millimeters) (c) 2003 Fairchild Semiconductor Corporation Page 11 of 15 10/1/03 OPTOPLANAR(R) HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER LSTTL TO 74OL6000 74OL6001 74OL6010 74OL6011 ORDERING INFORMATION Option Order Entry Identifier Description .S Surface Mount Lead Bend SD .SD Surface Mount; Tape and Reel W .W 0.4" Lead Spacing .300 VDE 0884 .300W VDE 0884, 0.4" Lead Spacing S 300 300W 3S 3SD .3S VDE 0884, Surface Mount .3SD VDE 0884, Surface Mount, Tape and Reel MARKING INFORMATION 1 3 74OL6000 2 V XX YY K 6 4 5 Definitions 1 Fairchild logo 2 Device number 3 VDE mark (Note: Only appears on parts ordered with VDE option - See order entry table) 4 Two digit year code, e.g., `03' 5 Two digit work week ranging from `01' to `53' 6 Assembly package code (c) 2003 Fairchild Semiconductor Corporation Page 12 of 15 10/1/03 OPTOPLANAR(R) HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER LSTTL TO 74OL6000 74OL6001 74OL6010 74OL6011 Reflow Profile (Black Package, No Suffix) Temperature (C) 300 215C, 10-30 s 250 225 C peak 200 150 Time above 183C, 60-150 sec 100 50 Ramp up = 3C/sec * Peak reflow temperature: 225C (package surface temperature) * Time of temperature higher than 183C for 60-150 seconds * One time soldering reflow is recommended 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 Time (Minute) (c) 2003 Fairchild Semiconductor Corporation Page 13 of 15 10/1/03 OPTOPLANAR(R) HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER LSTTL TO 74OL6000 74OL6001 74OL6010 74OL6011 APPLICATION Local area data communication systems can greately improve their noise immunity by including OPOTOLOGIC gates in the design. The Optologic input amplifier offers the feature of very high input impedance that permits their use as bridged line receivers. The system show above illustrates an optically isolated transmitter and multidrop receiver system. The network uses a 74OL6000 and buffer (Figure D) to isolate the transmitter and drive the 75 coax cable. This application uses a 1000 ft. aerial suspension 75 CATV coax cable with data taps at 250 ft. intervals. The 74OL6001s function as bridged receivers, and as many as 30 receivers could be placed along the line with minimal signal degradation. The communication cable is terminated with a single 75 load at the far end of the line. Signal quality "Eye Pattern" is shown in Figures A, B and C with a 10MBaud NRZ Psuedo-Random Sequence (PRS). Traces 1-3 in Figure A describes the transmitter section. Traces 4-7 in Figure B show the output of the four Optologic bridged terminations. Traces 8-11 in Figure C illustrate "Eye Pattern" as seen at the output of a 74LS04 logic gate. The data quality is well preserved in that only a 30% Eye closure is seen at the receiver located 1000 ft. from the transmitter. The data communication system is completely optically isolated from all of the terminal equipments. Power for the transmitter (VCCO) and receiver (VCCI) is taken from an isolated power supply and distributed through a drain or messenger wire. Figure A HORIZONTAL = 20 ns/DIV VERTICAL = 2 V/DIV 0.1 F 1.1 K Figure B 42-11 10 Figure C HORIZONTAL = 20 ns/DIV VERTICAL = 2 V/DIV PRSG 100 ns BIT INTERVAL 1 2 42-12, 02 HORIZONTAL = 20 ns/DIV VERTICAL = 2 V/DIV 42-13/03 1000 FT. 3 75 TERMINAION 74 OL 6000 BUFFER 250 FT. 250 FT. 250 FT. 250 FT. 2N4252 100 F 74 OL 6001 4 2N4252 1.1 K 8 74 OL 6001 LS04 9 74 OL 6001 6 5 LS04 10 74 OL 6001 7 LS04 11 LS04 2N2222 1 K ALL DIODES 1N6263 Figure D Buffer (c) 2003 Fairchild Semiconductor Corporation Page 14 of 15 10/1/03 OPTOPLANAR(R) HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS LSTTL TO TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER 74OL6000 74OL6001 74OL6010 74OL6011 DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. (c) 2003 Fairchild Semiconductor Corporation 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Page 15 of 15 10/1/03