Preliminary W26A02 128K x 16 CMOS STATIC RAM GENERAL DESCRIPTION The W26A02 is a normal-speed, very low-power CMOS static RAM organized as 131072 x 16 bits that operates on a wide voltage range from 1.65V to 1.95V power supply. The W26A02, W26A02-LE and W26A02-LI, can meet the requirement of various operating temperature. This device is manufactured using Winbond's high performance CMOS technology. FEATURES * * * * * * Low power consumption Access time: 70 nS 1.65V to 1.95V supply voltage Fully static operation All inputs and outputs directly TTL compatible Three-state outputs PIN CONFIGURATIONS * Battery back-up operation capability * Data retention voltage: 1.0V (min.) * Data byte control - #LB (I/O1 - I/O8), #UB (I/O9 - I/O16) * Available packages: 44-pin type two TSOP, and TFBGA BLOCK DIAGRAM CLK GEN. PRECHARGE CKT. R O W CORE CELL ARRAY A4 A3 A4 A3 A2 A1 A0 #CS I/O1 I/O2 I/O3 I/O4 V DD V SS I/O5 I/O6 I/O7 I/O8 #WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A5 A6 A7 #OE #UB #LB I/O16 I/O15 I/O14 I/O13 VSS VDD I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 44-pin TSOP A15 A14 A16 A1 A2 A0 I/O1 : I/O16 1 2 3 4 5 #OE #UB I/O11 I/O12 I/O13 I/O14 NC A8 A0 A3 A5 NC NC A14 A12 A9 A1 A4 A6 A7 A16 A15 A13 A10 A2 #CS I/O2 I/O4 I/O5 I/O6 #WE A11 I/O CKT. COLUMN DECODER DATA CNTRL. CLK GEN. A7 A6 A5 A8 A9 A10 A11 A12 #WE #CS #UB #LB #OE PIN DESCRIPTION SYMBOL #LB I/O9 I/O10 VSS VDD I/O15 I/O16 NC 128 X 16 COLUMNS A13 A0 - A16 TFBGA TOP VIEW A B C D E F G H 1024 ROWS D E C O D E R I/O1 - I/O16 #CS #WE #LB #UB #OE VDD VSS NC 6 NC I/O1 I/O3 VDD VSS I/O7 I/O8 NC -1- DESCRIPTION Address Inputs Data Inputs/Outputs Chip Select Input Write Enable Input Lower byte select Upper byte select Output Enable Input Power Supply Ground No Connection Publication Release Date: May 6, 2002 Revision A1 Preliminary W26A02 TRUTH TABLE VDD CURRENT I/O1 - I/O8 I/O9 - I/O16 Not Selected High Z High Z ISB, ISB1 X Output Disable High Z High Z IDD L L 2 Bytes Read DOUT DOUT IDD H L H Lower Byte Read DOUT High Z IDD L H H L Upper Byte Read High Z DOUT IDD L X L L L 2 Bytes Write DIN DIN IDD L X L L H Lower Byte Write DIN High Z IDD L X L H L Upper Byte Write High Z DIN IDD X X X H H Not Selected High Z High Z ISB, ISB1 #CS #OE #WE #LB #UB H X X X X L H H X L L H L L L MODE -2- Preliminary W26A02 DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER RATING UNIT -0.5 to +2.6 V Input/Output to VSS Potential -0.5 to VDD +0.3 V Allowable Power Dissipation 1.0 W -65 to +150 C Supply Voltage to VSS Potential Storage Temperature Operating Temperature LE -20 to 85 LI -40 to 85 C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. Operating Characteristics (VSS = 0V; TA (C) = -20 to 85 for LE, -40 to 85 for LI) PARAMETER SYM. W26A02 TEST UNIT CONDITIONS MIN. MAX. Operating Power Voltage VDD - 1.65 1.95 V Input Low Voltage VIL - -0.2 +0.4 V Input High Voltage VIH - +1.4 VDD +0.2 V Input Leakage Current ILI VIN = VSS to VDD -1 +1 A Output Leakage Current ILO VI/O = VSS to VDD; #CS = VIH (min.) or #OE = VIH (min.) or #WE = VIL (max.) -1 +1 A Output Low Voltage VOL IOL = +0.1 mA - 0.2 V Output High Voltage VOH IOH = -0.1 mA 1.4 - V Operating Power Supply Current IDD #CS = VIL (max.), I/O = 0 mA; Cycle = min. Duty = 100% - 25 mA ISB #CS = VIH (min.) - 0.3 mA ISB1 #CS VDD -0.2V - 5 A Standby Power Supply Current -3- Publication Release Date: May 6, 2002 Revision A1 Preliminary W26A02 CAPACITANCE (TA = 25 C, f = 1 MHz) PARAMETER SYM. CONDITIONS MAX. UNIT Input Capacitance CIN VIN = 0V 8 pF Input/Output Capacitance CI/O VOUT = 0V 10 pF Note: These parameters are sampled but not 100% tested. AC CHARACTERISTICS AC Test Conditions PARAMETER CONDITIONS Input Pulse Levels 0V to 1.6V Input Rise and Fall Times 5 nS Input and Output Timing Reference Level 0.9V Output Load See the drawing below AC Test Loads and Waveform 1 TTL 1 TTL OUTPUT OUTPUT 5 pF Including Jig and Scope 30 pF Including Jig and Scope (For TCLZ, TOLZ, TCHZ, TOHZ, TWHZ, TOW ) 1.6V 90% 10% 0V 90% 10% 5 nS 5 nS -4- Preliminary W26A02 AC Characteristics, continued (VSS = 0V; TA (C) = -20 to 85 for LE, -40 to 85 for LI) Read Cycle PARAMETER W26A02 SYMBOL UNIT MIN. MAX. Read Cycle Time TRC 70 - nS Address Access Time TAA - 70 nS Chip Select Access Time TACS - 70 nS Output Enable to Output Valid TAOE - 35 nS #UB, #LB Access Tim TBA - Chip Selection to Output in Low Z TCLZ* 10 - nS Output Enable to Output in Low Z TOLZ* 5 - nS #UB, #LB Enable to Output in Low Z TBLZ* 5 - nS Chip Deselection to Output in High Z TCHZ* - 30 nS Output Disable to Output in High Z TOHZ* - 30 nS #UB, #LB Disable to Output in High Z TBHZ* - 30 nS Output Hold from Address Change TOH 10 - nS 70 nS These parameters are sampled but not 100% tested Write Cycle PARAMETER W26A02 SYMBOL UNIT MIN. MAX. Write Cycle Time TWC 70 - nS Chip Selection to End of Write TCW 60 - nS Address Valid to End of Write TAW 60 - nS #UB, #LB Select to End of Write TBW 60 - nS Address Setup Time TAS 0 - nS Write Pulse Width TWP 55 - nS TWR 0 - nS Data Valid to End of Write TDW 40 - nS Data Hold from End of Write TDH 0 - nS Write to Output in High Z TWHZ* - 30 nS Output Disable to Output in High Z TOHZ* - 30 nS Output Active from End of Write TOW 5 - nS Write Recovery Time #CS, #WE These parameters are sampled but not 100% tested -5- Publication Release Date: May 6, 2002 Revision A1 Preliminary W26A02 TIMING WAVEFORMS Read Cycle 1 (Address Controlled) TRC Address TAA TOH TOH D OUT Read Cycle 2 (Chip Select Controlled, #OE = VIL, #WE= VIH) TRC Address #CS TACS TCHZ TCLZ #OE TOLZ TAOE TOHZ TBA #UB / #LB TBHZ HIGH-Z TBLZ HIGH-Z D OUT -6- Preliminary W26A02 Timing Waveforms, continued Read Cycle 3 (Output Enable Controlled) TR CC Address T AA #OE T OH T AOE T OLZ #CS T ACS T CHZ T OHZ TCLZ D OUT Write Cycle 1 (#OE Clock) T WC Address TWR #OE TCW #CS TBW #UB/#LB TAW TWP #WE TAS D OUT TDW TDH D IN -7- Publication Release Date: May 6, 2002 Revision A1 Preliminary W26A02 Timing Waveforms, continued Write Cycle 2 (#OE = VIL Fixed) TWC Address TCW TWR #CS TBW #UB/#LB TAW #WE TWP TAS TWHZ (1, 4) TOH TOW (2) (3) D OUT TDW TDH DIN Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from DOUT are the same as the data written to DIN during the write cycle. 3. DOUT provides the read data for the next address. 4. Transition is measured 500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested. -8- Preliminary W26A02 DATA RETENTION CHARACTERISTICS (TA (C) = -20 to 85 for LE; -40 to 85 for LI) PARAMETER SYM. TEST CONDITIONS VDD for Data Retention VDR #CS VDD -0.2V Data Retention Current IDDDR #CS VDD -0.2V, VDD = 1.8V Chip Deselect to Data Retention Time TCDR Operation Recovery Time TR MIN. TYP. MAX. UNIT 1.0 - - V - - 5 A 0 - - nS TRC* - - nS See data retention waveform * Read Cycle Time DATA RETENTION WAVEFORM VDD 0.9 x V DD > 1.0V VDR = TCDR 0.9 x V DD TR #CS > = V DD - 0.2V #CS ORDERING INFORMATION PART NO. ACCESS TIME (nS) OPERATING VOLTAGE (V) STANDBY CURRENT (A) OPERATING TEMPERATURE (C) W26A02B-70LE 70 1.8V/5 A -20 to 85 TFBGA W26A02H-70LE 70 1.8V/5 A -20 to 85 TSOP(II) W26A02B-70LI 70 1.8V/5 A -40 to 85 TFBGA W26A02H-70LI 70 1.8V/5 A -40 to 85 TSOP(II) PACKAGE Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. -9- Publication Release Date: May 6, 2002 Revision A1 Preliminary W26A02 PACKAGE DIMENSIONS 44-pin Standard Type Two TSOP Y Dimension in inches Dimension in mm Symbol A D H Min. A2 A 1 L1 e L b M A A1 A2 b c D E E D 0.10 (0.004) c TFBGA - 10 - Nom. Max. Min. HD e L L1 Y Nom. Max. 0.047 1.20 0.05 0.002 0.037 0.039 0.041 0.95 1.00 1.05 0.010 0.014 0.018 0.25 0.35 0.45 0.005 0.006 0.007 0.12 0.15 0.17 0.721 0.725 0.729 18.31 18.41 18.51 0.396 0.400 0.404 10.06 10.16 10.26 0.455 0.463 0.471 11.56 11.76 11.96 0.80 0.031 0.016 0.020 0.024 0.40 0.031 0.60 0.80 0.004 o 0 0.50 o 5 0.10 o 0 o 5 Preliminary W26A02 VERSION HISTORY VERSION DATE PAGE A1 May 6, 2002 - DESCRIPTION Initial Issued Headquarters Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd. No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office Winbond Electronics Corporation Japan Winbond Electronics (H.K.) Ltd. 9F, No.480, Rueiguang Rd., Neihu Chiu, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 11 - Publication Release Date: May 6, 2002 Revision A1