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Optimum Technology Matching® Applied
GaAs HBT
InGaP HBT
GaAs MESFET
SiGe BiCMOS
Si BiCMOS
SiGe HBT
GaAs pHEMT
Si CMOS
Si BJT
GaN HEMT
Functional Block Diagram
RF MICRO DEVICES®, RFMD®, Optimum Technology Matching®, Enabling Wireless Connectivity™, PowerStar®, POLARIS™ TOTAL RADIO™ and UltimateBlue™ are trademarks of RFMD, LLC. BLUETOOTH is a trade-
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Product Description
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com.
BiFET HBT
LDMOS
Synth
Phase
det.
Ref.
divider
RFFC5071A
Synth
Phase
det.
Ref.
divider
RFFC5072A
RFFC5071A/2A
WIDEBAND SYNTHESIZER/VCO WITH
INTEGRATED 6GHz MIXER
The RFFC5071A and RFFC5072A are re-configurable frequency conversion devices
with integrated fractional-N phased locked loop (PLL) synthesizer, voltage con-
trolled oscillator (VCO) and either one or two high linearity mixers. The fractional-N
synthesizer takes advantage of an advanced sigma-delta modulator that delivers
ultra-fine step sizes and low spurious products. The VCO features temperature com-
pensation circuits that deliver stable performance across the operating tempera-
ture range of -40°C to +85°C. The PLL/VCO engine combined with an external loop
filter allows the user to generate local oscillator (LO) signals from 85MHz to
4200MHz. The LO signal is buffered and routed to the integrated RF mixers which
are used to up/down-convert frequencies ranging from 30MHz to 6000MHz. The
mixer bias current is programmable and can be reduced for applications requiring
lower power consumption. Both devices can be configured to work as signal
sources by bypassing the integrated mixers. Device programming is achieved via a
simple 3-wire serial interface. In addition, a unique programming mode allows up to
four devices to be controlled from a common serial bus. This eliminates the need
for separate chip-select control lines between each device and the host controller.
Up to six general purpose outputs are provided, which can be used to access inter-
nal signals (the LOCK signal, for example) or to control front end components. Both
devices operate with a 2.7V to 3.3V power supply.
Features
85MHz to 4200MHz LO
Frequency Range
Fractional-N Synthesizer with
Very Low Spurious Levels
Typical Step Size 1.5Hz
Fully Integrated Low Phase Noise
VCO and LO Buffers
Integrated Phase Noise
• 0.18° rms at 1GHz
• 0.52° rms at 3GHz
High Linearity RF Mixer(s)
30MHz to 6000MHz Mixer
Frequency Range
Input IP3 +23dBm
Mixer Bias Adjustable for Low
Power Operation
Full Duplex Mode (RFFC5071A)
2.7V to 3.3V Power Supply
Low Current Consumption
3- or 4-Wire Serial Interface
Applications
Wideband Radios
Distributed Antenna Systems
Diversity Receivers
Software Defined Radios
Frequency Band Shifters
Point-to-Point Radios
WiMax/LTE Infrastructure
Satellite Communications
Wideband Jammers
Remote Radio Heads
DS140110
Package: QFN, 32-Pin, 5mm x 5mm
2 of 26
RFFC5071A/2A
DS140110
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support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com.
Absolute Maximum Ratings
Parameter Rating Unit
Supply Voltage (VDD) -0.5 to +3.6 V
Input Voltage (VIN) any pin -0.3 to VDD + 0.3 V
RF/IF mixer input power +15 dBm
Operating Temperature Range -40 to +85 °C
Storage Temperature Range -65 to +150 °C
Parameter Specification Unit Condition
Min. Typ. Max.
ESD Requirements
Human Body Model 2000 V DC Pins
1500 V All Pins
Charge Device Model 500 V All Pins
Operating Conditions
Supply voltage (VDD) 2.7 3.0 3.3 V
Temperature (TOP) -40 +85 °C
Logic Inputs/Outputs (VDD = Supply to DIG_VDD pin)
Input low voltage -0.3 +0.5 V
Input high voltage VDD / 1.5 VDD V
Input low current -10 +10 AInput = 0V
Input high current -10 +10 AInput = V
DD
Output low voltage 0 0.2*VDD V
Output high voltage 0.8*VDD VDD V
Load resistance 10 k
Load capacitance 20 pF
GPO Drive Capability
Sink Current 20 mA At VOL = +0.6V
Source Current 20 mA At VOL = +2.4V
Output Impedance 25
Static
Supply Current (IDD) with 1GHz LO 106 mA Low current, MIX_IDD=1, one mixer enabled.
132 mA High linearity, MIX_IDD=6, one mixer enabled.
Standby 2 mA Reference oscillator and bandgap only.
Power Down Current 300 A ENBL=0 and REF_STBY=0
Mixer 1/2 (Mixer output driving 4:1 balun)
Gain -2 dB Not including balun losses
Noise Figure <3000MHz 10 dB Low current setting
13 dB High linearity setting
Noise Figure <4000MHz 11 dB Low current setting
15 dB High linearity setting
Caution! ESD sensitive device.
Exceeding any one or a combination of the Absolute Maximum Rating conditions may
cause permanent damage to the device. Extended application of Absolute Maximum
Rating conditions to the device may reduce device reliability. Specified typical perfor-
mance or functional operation of the device under Absolute Maximum Rating condi-
tions is not implied.
The information in this publication is believed to be accurate and reliable. However, no
responsibility is assumed by RF Micro Devices, Inc. ("RFMD") for its use, nor for any
infringement of patents, or other rights of third parties, resulting from its use. No
license is granted by implication or otherwise under any patent or patent rights of
RFMD. RFMD reserves the right to change component circuitry, recommended appli-
cation circuitry and specifications at any time without prior notice.
RFMD Green: RoHS compliant per EU Directive 2002/95/EC, halogen free
per IEC 61249-2-21, < 1000ppm each of antimony trioxide in polymeric
materials and red phosphorus as a flame retardant, and <2% antimony in
solder.
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RFFC5071A/2A
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Parameter Specification Unit Condition
Min. Typ. Max.
Mixer 1/2 (Mixer output driving 4:1 balun) (continued)
IIP3 +10 dBm Low current setting
+23 dBm High linearity setting
Input Port Frequency range 30 6000 MHz
Mixer input return loss 10 dB 100 differential
Output port frequency range 30 4500 MHz
Mixer 1/2 (Mixer output driving 1:1 balun)
Output Port Frequency Range 30 6000 MHz
Gain -7 dB Not including balun losses
Reference Oscillator
External reference frequency 10 104 MHz
Reference divider ratio 1 7
External reference input level 500 800 1500 mVp-p AC-coupled
Synthesizer (PLL Closed Loop, 52MHz Reference)
Synthesizer Output Frequency 85 4200 MHz
Phase detector frequency 52 MHz
Phase noise (LO = 1GHz) -108 dBc/Hz 10kHz offset
-107 dBc/Hz 100kHz offset
-135 dBc/Hz 1MHz offset
0.18 ° RMS integrated from 1kHz to 40MHz
Phase noise (LO = 2GHz) -102 dBc/Hz 10kHz offset
-101 dBc/Hz 100kHz offset
-130 dBc/Hz 1MHz offset
0.33 ° RMS integrated from 1kHz to 40MHz
Phase noise (LO = 3GHz) -98 dBc/Hz 10kHz offset
-98 dBc/Hz 100kHz offset
-125 dBc/Hz 1MHz offset
0.52 ° RMS integrated from 1kHz to 40MHz
Phase noise (LO = 4GHz) -96 dBc/Hz 10kHz offset
-95 dBc/Hz 100kHz offset
-124 dBc/Hz 1MHz offset
0.67 ° RMS integrated from 1kHz to 40MHz
Normalized phase noise floor -214 dBc/Hz Measured at 20kHz to 30kHz offset
Voltage Controlled Oscillator
Open loop phase noise at 1MHz offset
2.5GHz LO frequency -133 dBc/Hz VCO3, LO Divide by 2
2.0GHz LO frequency -134 dBc/Hz VCO2, LO Divide by 2
1.5GHz LO frequency -136 dBc/Hz VCO1, LO Divide by 2
Open loop phase noise at 10MHz offset
2.5GHz LO frequency -149 dBc/Hz VCO3, LO Divide by 2
2.0GHz LO frequency -150 dBc/Hz VCO2, LO Divide by 2
1.5GHz LO frequency -151 dBc/Hz VCO1, LO Divide by 2
External LO Input
LO Input Frequency Range 85 4200 MHz LO Divide by 1
LO Input Frequency Range 85 5400 MHz LO Divide by 2
External LO Input Level 0 dBm Driven from 50 Source Via a 1:1 Balun
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RFFC5071A/2A
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Note 1: An RC low-pass filter could be used on this line to reduce digital noise.
Note 2: If the device is under software control this input can be configured as a general purpose output (GPO).
Note 3: Connect a 51K resistor from this pin to ground. This pin is sensitive to low frequency noise injection.
Note 4: DC voltage should not be applied to this pin. Use either an AC coupling capacitor as part of lumped element matching
network or a transformer (see application schematic).
Note 5: This pin must be connected to ANA_VDD2 using an RF choke or transformer (see application schematic).
Pin Names and Descriptions
Pin Name Description
1ENBL/GPO5
Device Enable pin (see note 1 and 2).
2 EXT_LO External local oscillator input (See note 4).
3 EXT_LO_DEC Decoupling pin for external local oscillator (See note 4).
4REXT
External bandgap bias resistor (See note 3).
5 ANA_VDD1 Analog supply. Use good RF decoupling.
6LFILT1
Phase detector output. Low-frequency noise-sensitive node.
7LFILT2
Loop filter op-amp output. Low-frequency noise-sensitive node.
8LFILT3
VCO control input. Low-frequency noise-sensitive node.
9MODE/GPO6
Mode select pin (See note 1 and 2).
10 REF_IN Reference input. Use AC coupling capacitor.
11 NC
12 TM Connect to ground.
13 MIX1_IPN Differential input 1 (see note 4). On RFFC5072A this pin is NC.
14 MIX1_IPP Differential input 1 (see note 4). On RFFC5072A this pin is NC.
15 GPO1/ADD1 General purpose output / MultiSlice address bit.
16 GPO2/ADD2 General purpose output / MultiSlice address bit.
17 MIX1_OPN Differential output 1 (see note 5). On RFFC5072A this pin is NC.
18 MIX1_OPP Differential output 1 (see note 5). On RFFC5072A this pin is NC.
19 DIG_VDD Digital supply. Should be decoupled as close to the pin as possible.
20 NC Leave circuit open.
21 NC
22 ANA_VDD2 Analog supply. Use good RF decoupling.
23 MIX2_IPP Differential input 2 (see note 4).
24 MIX2_IPN Differential input 2 (see note 4).
25 GPO3/FM General purpose output / frequency control input.
26 GPO4/LD/DO General purpose output / Lock detect output / serial data out.
27 MIX2_OPN Differential output 2. (see note 5).
28 MIX2_OPP Differential output 2. (see note 5).
29 RESETX Chip reset (active low). Connect to DIG_VDD if asynchronous reset is not required.
30 ENX Serial interface select (active low) (See note 1).
31 SCLK Serial interface clock (see note 1).
32 SDATA Serial interface data (see note 1).
Exposed paddle Ground reference, should be connected to PCB ground through a low impedance path.
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Theory of Operation
The RFFC5071A and RFFC5072A are wideband RF frequency converter chips which include a fractional-N synthesizer and a
low noise VCO core. The RFFC5071A has an LO signal multiplexer, two LO buffer circuits, and two RF mixers. The RFFC5072A
has a single LO buffer circuit and one RF mixer. Both devices have an integrated voltage reference and low drop out regulators
supplying critical circuit blocks such as the VCOs and synthesizer. Synthesizer programming, device configuration and control
are achieved through a mixture of hardware and software controls. All on-chip registers are programmed through a simple 3-
wire serial interface.
VCO
The VCO core in the RFFC5071A and RFFC5072A consists of three VCOs which, in conjunction with the integrated LO dividers
of /2 to /32, cover the LO range of 85MHz to 4200MHz. Each VCO has 128 overlapping bands which are used to achieve low
VCO gain and optimal phase noise performance across the whole tuning range. The chip automatically selects the correct VCO
(VCO auto-select) and VCO band (VCO coarse tuning) to generate the desired LO frequency based on the values programmed
into the PLL1 and PLL2 registers banks.
The VCO auto-select and VCO coarse tuning are triggered every time ENBL is taken high, or if the PLL re-lock self clearing bit is
programmed high. Once the correct VCO and band have been selected the PLL will lock onto the correct frequency. During the
band selection process, fixed capacitance elements are progressively connected to the VCO resonant circuit until the VCO is
oscillating approximately at the correct frequency. The output of this band selection, CT_CAL, is made available in the read-
back register. A value of 127 or 0 in this register indicates that the coarse tuning was unsuccessful, and this will also be indi-
cated by the CT_FAILED flag also available in the read-back register. A CT_CAL value between 1 and 126 indicates a success-
ful calibration, the actual value being dependent on the desired frequency as well as process variation for a particular device.
The band select process will center the VCO tuning voltage at about 0.8V, compensating for manufacturing tolerances and pro-
cess variation as well as environmental factors including temperature. The VCOs have temperature compensation circuits so
the PLL will hold lock over the entire operating temperature range of -40°C to +85°C. This is true regardless of the tempera-
ture at which the VCO band selection is performed. The VCO gain is also held stable across temperature, maintaining consis-
tent loop bandwidth and synthesizer phase noise.
The RFFC5071A and RFFC5072A feature a differential LO input to allow the mixer to be driven from an external LO source. The
fractional-N PLL can be used with an external VCO driven into this LO input, which may be useful to reduce phase noise in
some applications. This may also require an external op-amp, dependant on the tuning voltage required by the external VCO.
In the RFFC5071A the LO signal is routed to mixer 1, mixer 2, or both mixers depending on the state of the MODE pin (or MODE
bit if under software control) and the value of the FULLD bit. Setting FULLD high puts the device into Full Duplex mode and both
mixers are enabled.
Fractional-N PLL
The RFFC5071A and RFFC5072A contain a charge pump-based fractional-N phase locked loop (PLL) for controlling the three
VCOs. The PLL includes automatic calibration systems to counteract the effects of process and environmental variations,
ensuring repeatable loop response and phase noise performance. As well as the VCO auto-select and coarse tuning, there is a
loop filter calibration mechanism which can be enabled if required. This operates by adjusting the charge pump current to
maintain loop bandwidth. This can be useful for applications where the LO is tuned over a wide frequency range.
The PLL has been designed to use a reference frequency of between 10MHz and 104MHz from an external source, which is
typically a temperature controlled crystal oscillator (TCXO). A reference divider (divide by 1 to divide by 7) is supplied and
should be programmed to limit the frequency at the phase detector to a maximum of 52MHz.
Two PLL programming banks are provided, the first bank is preceded by the label PLL1 and the second bank is preceded by the
label PLL2. For the RFFC5071A these banks are used to program mixer 1 and mixer 2 respectively, and are selected automati-
cally as the mixer is selected using MODE. For the RFFC5072A mixer 2 and register bank PLL2 are normally used.
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RFFC5071A/2A
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The VCO outputs are first divided down in a high frequency prescalar. The output of this high frequency prescalar then enters
the N divider, which is a fractional divider containing a dual-modulus prescaler and a digitally spur-compensated fractional
sequence generator. This allows very fine frequency steps and minimizes fractional spurs. The fractional energy is randomized
and appears as fractional noise at frequency offsets above 100kHz which will be attenuated by the loop filter. An external loop
filter is used, giving flexibility in setting loop bandwidth for optimizing phase noise and lock time, for example.
The synthesizer step size is typically 1.5Hz when using a 26MHz reference frequency. The exact step size for any reference and
LO frequency can be calculated using the following formula:
(FREF * P) / (R * 224 * LO_DIV)
Where FREF is the reference frequency, R is the reference division ratio, P is the prescalar division ratio, and LO_DIV is the LO
divider value.
Pin 26 (GPO4) can be configured as a lock detect pin. The lock status is also available in the read-back register. The lock detect
function is a window detector on the VCO tuning voltage. The lock flag will be high to show PLL lock which corresponds to the
VCO tuning voltage being within the specified range, typically 0.30V to 1.25V.
The lock time of the PLL will depend on a number of factors; including the loop bandwidth and the reference frequency at the
phase detector. This clock frequency determines the speed at which the state machine and internal calibrations run. A 52MHz
phase detector frequency will give fastest lock times, of typically <50secs when using the PLL re-lock bit.
Phase Detector and Charge Pump
The phase detector provides a current output to drive an active loop filter. The charge pump output current is set by the value
contained in the P1_CP_DEF and P2_CP_DEF fields in the loop filter configuration register. The charge pump current is given
by approximately 3A/bit, and the fields are 6 bits long. This gives default value (31) of 93A and maximum value (63) of
189A.
If the automatic loop bandwidth calibration is enabled the charge pump current is set by the calibration algorithm based upon
the VCO gain.
The phase detector will operate with a maximum input frequency of 52MHz.
Loop Filter
The active loop filter is implemented using the on-chip low noise op-amp with external resistors and capacitors. The internal
configuration of the chip is shown below with the recommended active loop filter. The op-amp gives a tuning voltage range of
typically +0.1V to +2.4V. The recommended loop filter shown is designed to give the lowest integrated phase noise for refer-
ence frequencies of between 26MHz and 52MHz. The external loop filter gives the flexibility to optimize the loop response for
any particular application and combination of reference and VCO frequencies.
LFILT1
8p2
180p 22K
470R 470R
330p 330p
LFILT2
LFILT3
+1.1V
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External Reference
The RFFC5071A and RFFC5072A have been designed to use an external reference such as a TCXO. The typical input will be a
0.8Vp-p clipped sine wave, which should be AC-coupled into the reference input. When the PLL is not in use, it may be desir-
able to turn off the internal reference circuits, by setting the REFSTBY bit low, to minimize current draw while in standby mode.
On cold start, or if REFSTBY is programmed low, the reference circuits will need a warm-up period. This is set by the SU_WAIT
bits. This will allow the clock to be stable and immediately available when the ENBL bit is asserted high, allowing the PLL to
assume normal operation.
If the current consumption of the reference circuits in standby mode, typically 2mA, is not critical, then the REFSTBY bit can be
set high. This allows the fastest startup and lock time after ENBL is taken high.
Wideband Mixer
The mixers are wideband, double-balanced Gilbert cells. They support RF/IF frequencies from 30MHz up to 6000MHz. Each
mixer has an input port and an output port that can be used for either IF or RF (in other words, for up- or down-conversion). The
mixer current can be programmed to between about 15mA and 45mA depending on linearity requirements. The majority of the
mixer current is sourced through the output pins via either a center-tapped balun or an RF choke in the external matching cir-
cuitry to the supply.
The RF mixer input and output ports are differential and require baluns and simple matching circuits optimized to the specific
application frequencies. A conversion gain of approximately -2dB (not including balun losses) is achieved with 100 differen-
tial input impedance, and the outputs driving 200 differential load impedance. Increasing the mixer output load increases
the conversion gain.
The mixer has a broadband common gate input. The input impedance is dominated by the resistance set by the mixer 1/gm
term, which is inversely proportional to the mixer current setting. The resistance will be approximately 85 at the default mixer
current setting (100). There is also some shunt capacitance at the mixer input, and the inductance of the bond wires (about
0.5nH on each pin) to consider at higher frequencies. The following diagram is a simple model of the mixer input impedance:
The mixer output is high impedance, consisting of approximately 2k resistance in parallel with some capacitance, approxi-
mately 1pF dependent on PCB layout. The mixer output does not require a conjugate matching network. It is a constant current
output which will drive a real differential load of between 50 and 500, typically 200. Since the mixer output is a constant
current source, a higher resistance load will give higher output voltage and gain. A shunt inductor can be used to resonate with
the mixer output capacitance at the frequency of interest. This inductor may not be required at lower frequencies where the
impedance of the output capacitance is less significant. At higher output frequencies the inductance of the bond wires (about
0.5nH on each pin) becomes more significant. Above about 4500MHz, it is beneficial to lower the output load to 50 to mini-
mize the effect of the ouput capacitance. The following diagram is a simple model of the mixer output:
RFFC507xA
Mixer Input
0.5nH
0.5nH
Rin
Typ 85
0.5pF
RFFC507xA
Mixer Output
0.5nH
0.5nH
1K
1pF
1K
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The RFFC5071A mixer layout and pin placement has been optimized for high mixer-to-mixer isolation of greater than 60dB. The
mixers can be set up to operate in half duplex mode (1 mixer active) or full duplex mode (both mixers active). This selection is
done via control of MODE and by setting the FULLD bit. When in full duplex mode, either PLL register bank can be used, the LO
signal is routed to both mixers.
Serial Interface
All on-chip registers in the RFFC5071A and RFFC5072A are programmed using a proprietary 3-wire serial bus which supports
both write and read operations. Synthesizer programming, device configuration, and control are achieved through a mixture of
hardware and software controls. Certain functions and operations require the use of hardware controls via the ENBL, MODE,
and RESETB pins in addition to programming via the serial bus. Alternatively there is the option to control the chip completely
via the serial bus.
The serial data interface can be configured for 4-wire operation by setting the 4WIRE bit in the SDI_CTRL register high. Then
pin 26 is used as the data out pin, and pin 32 is the serial data in pin.
Hardware Control
Three hardware control pins are provided: ENBL, MODE, and RESETB.
The ENBL pin has two functions: to enable the analog circuits in the chip and to trigger the VCO auto-selection and coarse tun-
ing mechanisms. The VCO auto-selection and coarse tuning is initiated when the ENBL pin is taken high. Every time the fre-
quency of the synthesizer is reprogrammed, ENBL has to be asserted high to initiate these mechanisms and then to initiate the
PLL locking. Alternatively following the programming of a new frequency the PLL re-lock self clearing bit could be used.
The RESETB pin is a hardware reset control that will reset all digital circuits to their startup state when asserted low. The device
includes a power-on-reset function, so this pin should not normally be required, in which case it should be connected to the
positive supply.
The MODE pin controls which mixer(s) and PLL programming register bank is active.
Serial Data Interface Control
The normal mode of operation uses the 3-wire serial data interface to program the device registers, and three extra hardware
control lines: MODE, ENBL and RESETB.
When the device is under software control, achieved by setting the SIPIN bit in the SDI_CTRL register high, then the hardware
can be controlled via the SDI_CTRL register. When this is the case, the three hardware control lines are not required. If the
device is under software control, pins 1 and 9 can be configured as general purpose outputs (GPO).
Mode FULLD Active PLL
Register Bank
Active
Mixer
LOW 0 1 1
HIGH 0 2 2
LOW 1 1 1 and 2
HIGH 1 2 1 and 2
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Multi-Slice Mode
The Multi-Slice mode of operation allows up to four chips to be controlled from a common serial bus. The device address pins
(15 and 16) ADD1 and ADD2 are used to set the address of each part.
On power up, and after a reset, the devices ignore the address pins ADD1 and ADD2 and any data presented to the serial bus
will be programmed into all the devices. However, once the ADDR bit in the SDI_CTRL register is set, each device then adopts
an address according to the state of the address pins on the device.
General Purpose Outputs
The general purpose outputs (GPOs) can be controlled via the GPO register and will depend on the state of MODE since they
can be set in different states corresponding to either mixer path 1 or 2. For example, the GPOs can be used to drive LEDs or to
control external circuitry such as switches or low power LNAs.
Each GPO pin can supply approximately 20mA load current. The output voltage of the GPO high state will drop with increased
current drive by approximately 25mV/mA. Similarly the output voltage of the GPO low state will rise with increased current,
again by approximately 25mV/mA.
External Modulation
The RFFC5071A and RFFC5072A fractional-N synthesizer can be used to modulate the frequency of the VCO. There are two
dedicated registers, EXT_MOD and FMOD, which can be used to configure the device as a modulator. It is possible to modulate
the VCO in two ways:
1.Binary FSK
The MODSETUP bits in the EXT_MOD register are set to 11. GPO3 is then configured as an input and used to control the signal
frequency. The frequency deviation is set by the MODSTEP and MODULATION bits in the EXT_MOD and FMOD registers respec-
tively.
The modulation frequency is calculated according to the following formula:
Where MODULATION is a 2's complement number and FPD is the phase detector frequency.
2.Continuous Modulation
The MODSETUP bits in the EXT_MOD register are set to 01. The frequency deviation is set by the MODSTEP and MODULATION
bits in the EXT_MOD and FMOD registers respectively. The VCO frequency is then changed by writing a new value into the MOD-
ULATION bits, the VCO frequency is instantly updated. An arbitrary frequency modulation can then be performed dependant
only on the rate at which values are written into the FMOD register.
Slice2
(0)
Slice2
(1)
Slice2
(2)
Slice2
(3)
A1 A2
ENX
SDATA
SCLK
VddVdd Vdd Vdd
A1 A2 A1 A2 A1 A2
FMOD 2MODSTEP FPD MODULATION216
=
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The modulation frequency is calculated according to the following formula:
Where MODULATION is a 2's complement number and FPD is the phase detector frequency.
Programming Information
The RFFC5071A and RFFC5072A share a common serial interface and control block. Please refer to the Register Maps and
Programming Guide which are available for download from http://rfmd.com/products/IntSynthMixer/.
Evaluation Boards
Evaluation boards for RFFC5071A and RFFC5072A are provided as part of a design kit, along with the necessary cables and
programming software tool to enable full evaluation of the device. Design kits can be ordered from www.rfmd.com or from local
RFMD sales offices and authorized sales channels. For ordering codes please see “Ordering Information” on page 26.
For further details on how to set up the design kits go to http://rfmd.com/products/IntSynthMixer/.
The standard evaluation boards are configured with 3.7GHz ceramic baluns on the RF ports and wideband transformers on the
IF ports. On the RFFC5071A evaluation board, mixer 1 is configured for down-conversion and mixer 2 is configured for up-con-
version. On the RFFC5072A evaluation board, mixer 2 is configured for down conversion.
FMOD 2MODSTEP FPD MODULATION216
=
11 of 26
RFFC5071A/2A
DS140110
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com.
Detailed Functional Block Diagram
Note: Wideband transmission line transformer baluns shown above for operation to ~2.5GHz. Substitute baluns for higher fre-
quency applications as required.
Pre-
scaler
Mux
/2n
[n=1..5]
N
divider
Sequence
generator
Phase
detector
Reference
divider
Charge
pump
GPO
Control
Biasing
& LDOs
Lock
Flag
XO
Ext LO
51K
+3V
MODE
ENBL
RESET
ENX
SDATA
SCLK
RFXF8553
4:1 Balun
+3V
OP1
RFXF8553
4:1 Balun
+3V
OP2
RFXF9503
1:1 Balun IP2
RFXF9503
1:1 Balun
IP1
Loop
Filter
3-Wire
Serial
Bus
Control
Lines
Mixer 2
Mixer 1
RFFC5071A Only
12 of 26
RFFC5071A/2A
DS140110
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com.
RFFC5071A Pin Out
RFFC5072A Pin Out
1
2
3
4
5
6
7
8
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
24
23
22
21
20
19
18
17
Exposed
paddle
ENBL/GPO5
EXT_LO
EXT_LO_DEC
REXT
ANA_VDD1
LFILT1
LFILT2
LFILT3
GPO2/ADD2
GPO1/ADD1
MIX1_IPP
MIX1_IPN
TM
REF_IN
MODE/GPO6
GPO3/FM
GPO4/LD/DO
MIX2_OPN
MIX2_OPP
RESETX
ENX
SCLK
SDATA
MIX2_IPN
MIX2_IPP
ANA_VDD2
NC
NC
DIG_VDD
MIX1_OPP
MIX1_OPN
NC
1
2
3
4
5
6
7
8
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
24
23
22
21
20
19
18
17
Exposed
paddle
ENBL/GPO5
EXT_LO
EXT_LO_DEC
REXT
ANA_VDD1
LFILT1
LFILT2
LFILT3
GPO2/ADD2
GPO1/ADD1
TM
REF_IN
MODE/GPO6
GPO3/FM
GPO4/LD/DO
MIX_OPN
MIX_OPP
RESETX
ENX
SCLK
SDATA
MIX_IPN
MIX_IPP
ANA_VDD2
NC
NC
DIG_VDD
NC
NC
NC
NC
NC
13 of 26
RFFC5071A/2A
DS140110
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com.
Wideband Application Schematic (<2.5GHz)
51K
R1
33pF
C1
33pF
C2
33pF
C3
33pF
C5
VDD A2
VDD D
8.2pF
C8
180pF
C9
330pF
C10
22K
R3
470RR2
VDD A2
VDD A2
100pF
C20
100pF
C21
100pF
C23
100pF
C24
100pF
C26
100pF
C27
100pF
C28
100pF
C29
100pF
C30
1
2
J1
RF _OP 2
1
2
J2
RF _IP2
1
2
J3
RF _OP 1
1
2
J4
RF _IP1
VDD A1
33pF
C13
33pF
C14
33pF
C15
1nF
C16
330pF
C17
470RR6
100pF
C6
RF _OP 2_P
RF _OP 2_N
RF _IP2_P
RF _IP2_N
RF _OP 1_N
RF _OP 1_P
RF _OP 1
RF _IP2
RF _OP 2
RF _IP1_N
RF _IP1_P
10nF
C19
10nF
C18
43
61
2
T2
RF XF 9503
4
3
6
1
2
T3
RF XF 8553
43
61
2
T4
RF XF 9503
4
3
6
1
2
T1
RF XF 8553
50Ω
50Ω
50Ω
50Ω
RF _IP1
10nF
C34
33pF
C36
33pF
C35
LFILT3
LFILT3
LFILT1
LFILT1
LFILT2
LFILT2
Loop Filter
470R
R9
GPIO2
GPIO1
GPIO4
GPIO3
220R
R25
E NBL
SDA TA
SCL K
ENX
RE SE TX
MODE
XTALP
10
E NBL
1
EXT _LO
2
EXT _LO_DEC
3
RE XT
4
ANA_V DD1
5
LFILT1
6
LFILT2
7
LFILT3
8
MODE
9
XTALN
11
GPIO1
15
TM
12
MIX1_IO1N
13
MIX1_IO1P
14
GPIO2
16
ANA_V DD2 22
MI X1 _IF_IO2N 17
MI X1 _IF_IO2P 18
DI G_V DD 19
NC 20
NC 21
RESET X 29
MI X2 _IF_IO2P 23
MI X2 _IF_IO2N 24
GPIO3 25
GPIO426
MIX2_IO1
P27
MIX2_IO1N 28
SDATA 32
ENX 30
SCLK 31
GND
33
U1
RFFC5071A _R FFC 5072A
10nF
C44
120R
R3 1
470R
R3 2
VDD A2
10nF
C43
D1 GRE E N
LOCK DET ECT LED
VC
1
OUT 3
GND
2
VC C 4
U2
VC TC XO
+2.8V
VDD A2
RFFC5071A Only
14 of 26
RFFC5071A/2A
DS140110
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com.
Narrowband 3.7GHz Application Schematic
51K
R1
33pF
C1
33pF
C2
33pF
C3
33pF
C5
VDD A2
VDD D
8.2pF
C8
180pF
C9
330pF
C10
22K
R3
470RR2
VDD A2
100pF
C23
100pF
C24
100pF
C26
100pF
C27
100pF
C28
15pF
C29
15pF
C30
1
2
J1
RF _OP 2
1
2
J2
IF_IP2
1
2
J3
IF_OP1
1
2
J4
RF _IP1
VDD A1
33pF
C13
33pF
C14
33pF
C15
1nF
C16
330pF
C17
470RR6
RF _OP 2_P
RF _OP 2_N
IF_IP2_P
IF_IP2_N
IF_OP1_N
IF_OP1_P
IF_OP1
IF_IP2
RF _OP 2
RF _IP1_N
RF _IP1_P
10nF
C19
10nF
C18
43
61
2
T2
RF XF 9503
4
3
6
1
2
T3
RF XF 8553
50Ω
50Ω
50Ω
50Ω
RF _IP1
10nF
C34
33pF
C36
33pF
C35
LFILT3
LFILT3
LFILT1
LFILT1
LFILT2
LFILT2
Loop Filter
470R
R9
GPIO2
GPIO1
GPIO4
GPIO3
220R
R25
E NBL
SDA TA
SCL K
ENX
RE SE TX
MODE
XTALP
10
E NBL
1
EXT _LO
2
EXT _LO_DEC
3
RE XT
4
ANA_V DD1
5
LFILT1
6
LFILT2
7
LFILT3
8
MODE
9
XTALN
11
GPIO1
15
TM
12
MIX1_IO1N
13
MIX1_IO1P
14
GPIO2
16
ANA_V DD2 22
MI X1 _IF_IO2N 17
MI X1 _IF_IO2P 18
DI G_V DD 19
NC 20
NC 21
RESET X 29
MI X2 _IF_IO2P 23
MI X2 _IF_IO2N 24
GPIO3 25
GPIO426
MIX2_IO1
P27
MIX2_IO1N 28
SDATA 32
ENX 30
SCLK 31
GND
33
U1
RFFC5071A _RFFC5072A
10nF
C44
120R
R3 1
470R
R3 2
VDD A2
10nF
C43
D1 GRE E N
LOCK DET ECT LED
VC
1
OUT 3
GND
2
VC C 4
Y1
VC TC XO
+2.8V
VDD A2
RFFC5071A Only
JOHANSON
3700BL1 5B 050
1
2
34
5
6
U3
VDD A2
15pF
C21
JOHA NSON
3700BL1 5B 200
1
2
3
4
5
6
U2L1
3.3nH
Mixer 2 Up Conversion Circuit
Mixer 1 Down Conversion Circuit
15 of 26
RFFC5071A/2A
DS140110
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com.
Typical Synthesizer Performance Characteristics
VDD = +3V and TA = +27°C unless stated.
-160.0
-150.0
-140.0
-130.0
-120.0
-110.0
-100.0
-90.0
-80.0
-70.0
-60.0
1 10 100 1000 10000 100000
Phase Noise (dBc/Hz)
Offset Frequency (KHz)
Synthesizer Phase Noise
5200MHz VCO Frequency, 26MHz Crystal Oscillator
2600MHz
1300MHz
650MHz
325MHz
162.5MHz
-160.0
-150.0
-140.0
-130.0
-120.0
-110.0
-100.0
-90.0
-80.0
-70.0
-60.0
1 10 100 1000 10000 100000
Phase Noise (dBc/Hz)
Offset Frequency (KHz)
Synthesizer Phase Noise
5200MHz VCO Frequency, 52MHz Crystal Oscillator
2600MHz
1300MHz
650MHz
325MHz
162.5MHz
-160.0
-150.0
-140.0
-130.0
-120.0
-110.0
-100.0
-90.0
-80.0
-70.0
-60.0
1 10 100 1000 10000 100000
Phase Noise (dBc/Hz)
Offset Frequency (KHz)
Synthesizer Phase Noise
4000MHz VCO Frequency, 26MHz Crystal Oscillator
4000MHz
2000MHz
1000MHz
500MHz
250MHz
125MHz
-160.0
-150.0
-140.0
-130.0
-120.0
-110.0
-100.0
-90.0
-80.0
-70.0
-60.0
1 10 100 1000 10000 100000
Phase Noise (dBc/Hz)
Offset Frequency (KHz)
Synthesizer Phase Noise
3000MHz VCO Frequency, 52MHz Crystal Oscillator
3000MHz
1500MHz
750MHz
375MHz
187.5MHz
93.75MHz
-160.0
-150.0
-140.0
-130.0
-120.0
-110.0
-100.0
-90.0
-80.0
-70.0
-60.0
1 10 100 1000 10000 100000
Phase Noise (dBc/Hz)
Offset Frequency (KHz)
Synthesizer Phase Noise
3000MHz VCO Frequency, 26MHz Crystal Oscillator
3000MHz
1500MHz
750MHz
375MHz
187.5MHz
93.75MHz
-160.0
-150.0
-140.0
-130.0
-120.0
-110.0
-100.0
-90.0
-80.0
-70.0
-60.0
1 10 100 1000 10000 100000
Phase Noise (dBc/Hz)
Offset Frequency (KHz)
Synthesizer Phase Noise
4000MHz VCO Frequency, 52MHz Crystal Oscillator
4000MHz
2000MHz
1000MHz
500MHz
250MHz
125MHz
16 of 26
RFFC5071A/2A
DS140110
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com.
Typical Synthesizer Performance Characteristics
VDD = +3V and TA = +27°C unless stated.
Note:
26MHz Crystal Oscillator: NDK ENA3523A
52MHz Crystal Oscillator: NDK ENA3560A
-160.0
-150.0
-140.0
-130.0
-120.0
-110.0
-100.0
-90.0
-80.0
-70.0
-60.0
1.0 10.0 100.0 1000.0 10000.0 100000.0
Phase Noise (dBc/Hz)
Offset Frequency (KHz)
Synthesizer Phase Noise vs Temperature
2000MHz LO Frequency, 26MHz TCXO
-40 Deg C
+25 Deg C
+85 Deg C
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0 600 1200 1800 2400 3000 3600 4200
RMS Integrated Phase Noise (Degrees)
LO Frequency (MHz)
Synthesiser RMS Integrated Phase Noise
Integration Bandwidth 1KHz to 40MHz
26MHz TCXO
52MHz TCXO
-160.0
-150.0
-140.0
-130.0
-120.0
-110.0
-100.0
-90.0
-80.0
-70.0
-60.0
1.0 10.0 100.0 1000.0 10000.0 100000.0
Phase Noise (dBc/Hz)
Offset Frequency (KHz)
Synthesizer Phase Noise vs Temperature
1500MHz LO Frequency, 26MHz TCXO
-40 Deg C
+25 Deg C
+85 Deg C
-160.0
-150.0
-140.0
-130.0
-120.0
-110.0
-100.0
-90.0
-80.0
-70.0
-60.0
1.0 10.0 100.0 1000.0 10000.0 100000.0
Phase Noise (dBc/Hz)
Offset Frequency (KHz)
Synthesizer Phase Noise vs Temperature
2600MHz LO Frequency, 26MHz TCXO
-40 Deg C
+25 Deg C
+85 Deg C
17 of 26
RFFC5071A/2A
DS140110
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com.
Typical VCO Performance Characteristics
VDD = +3V and TA = +27°C unless stated.
0
20
40
60
80
100
120
140
0
5
10
15
20
25
30
35
1200 1300 1400 1500 1600 1700 1800 1900
CT_CAL Word
Kvco (MHz/V)
VCO Frequency /2 (MHz)
VCO1 Frequency versus Kvco & CT_CAL
LO Divide by 2
Kvco
CT_CAL
0
20
40
60
80
100
120
140
0
5
10
15
20
25
30
35
1700 1800 1900 2000 2100 2200 2300 2400
CT_CAL Word
Kvco (MHz/V)
VCO Frequency /2 (MHz)
VCO2 Frequency versus Kvco & CT_CAL
LO Divide by 2
Kvco
CT_CAL
0
20
40
60
80
100
120
140
0
5
10
15
20
25
30
35
2200 2300 2400 2500 2600 2700 2800 2900 3000
CT_CAL Word
Kvco (MHz/V)
VCO Frequency /2 (MHz)
VCO3 Frequency versus Kvco & CT_CAL
LO Divide by 2
Kvco
CT_CAL
-160.0
-150.0
-140.0
-130.0
-120.0
-110.0
-100.0
-90.0
-80.0
-70.0
-60.0
10.0 100.0 1000.0 10000.0 100000.0
Phase Noise (dBc/Hz)
Offset Frequency (KHz)
VCO Phase Noise
With LO Divide by 1
4000MHz VCO2
3500MHz VCO2
3000MHz VCO1
-160.0
-150.0
-140.0
-130.0
-120.0
-110.0
-100.0
-90.0
-80.0
-70.0
-60.0
10.0 100.0 1000.0 10000.0 100000.0
Phase Noise (dBc/Hz)
Offset Frequency (KHz)
VCO Phase Noise
With LO Divide by 2
2500MHz VCO3
2000MHz VCO2
1500MHz VCO1
18 of 26
RFFC5071A/2A
DS140110
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com.
Typical Supply Current Performance Characteristics
VDD = +3V and TA = +27°C unless stated.
90.0
100.0
110.0
120.0
130.0
140.0
150.0
1234567
Current (mA)
Mixer Bias Current Setting (MIX_IDD)
Total Supply Current versus Mixer Bias Setting
One Mixer Enabled, LO Frequency = 1000MHz
-40 Deg C, +2.7V
-40 Deg C, +3.0V
-40 Deg C, +3.3V
+27 Deg C, +2.7V
+27 Deg C, +3.0V
+27 Deg C, +3.3V
+85 Deg C, +2.7V
+85 Deg C, +3.0V
+85 Deg C, +3.3V
RFFC5071A Typical Operang Current in mA in Full Duplex Mode
Both mixers enabled, LO Frequency of 1000MHz, +3V supply
MIX2_IDD MIX1_IDD
1 2 3 4 5 6 7
1 129 134 139 144 149 154 159
2 134 139 144 150 155 160 165
3 139 144 150 155 160 165 170
4 144 150 155 160 165 170 175
5 149 155 160 165 170 175 180
6 154 160 165 170 175 180 185
7 159 164 170 175 180 185 190
70.0
80.0
90.0
100.0
110.0
120.0
130.0
140.0
150.0
160.0
170.0
0 500 1000 1500 2000 2500 3000 3500 4000 4500
Supply Current (mA)
LO Frequency (MHz)
Total Supply Current versus LO Frequency
One Mixer Enabled, +3.0V Supply Voltage
MIX_IDD = 1
MIX_IDD = 2
MIX_IDD = 3
MIX_IDD = 4
MIX_IDD = 5
MIX_IDD = 6
MIX_IDD = 7
19 of 26
RFFC5071A/2A
DS140110
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com.
Typical RF Mixer1 Performance Characteristics
VDD = +3V and TA = +27°C unless stated. As measured on RFFC5071A wideband evaluation board.
See application schematic on page 13.
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
1234567
Noise Figure (dB)
Mixer Bias Current Setting (MIX1_IDD)
Mixer 1 Noise Figure versus Bias Current
LO Frequency = 1000MHz, IF Output = 100MHz
-40 Deg C, +2.7V
-40 Deg C, +3.0V
-40 Deg C, +3.6V
+27 Deg C, +2.7V
+27 Deg C, +3.0V
+27 Deg C, +3.6V
+85 Deg C, +2.7V
+85 Deg C, +3.0V
+85 Deg C, +3.6V
-2.0
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
1234567
Pin 1dB (dBm)
Mixer Bias Current Setting (MIX1_IDD)
Mixer 1 Input Power for 1dB Compression
LO Frequency = 1000MHz, IF Output = 100MHz
-40 Deg C, +2.7V
-40 Deg C, +3.0V
-40 Deg C, +3.6V
+27 Deg C, +2.7V
+27 Deg C, +3.0V
+27 Deg C, +3.6V
+85 Deg C, +2.7V
+85 Deg C, +3.0V
+85 Deg C, +3.6V
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
500 750 1000 1250 1500 1750 2000
Noise Figure (dB)
LO Frequency (MHz)
Mixer 1 Noise Figure versus Frequency
IF Output = 100MHz
MIX_IDD = 1
MIX_IDD = 2
MIX_IDD = 3
MIX_IDD = 4
MIX_IDD = 5
MIX_IDD = 6
MIX_IDD = 7
0.0
5.0
10.0
15.0
20.0
25.0
30.0
0.0
5.0
10.0
15.0
20.0
25.0
30.0
500 750 1000 1250 1500 1750 2000 2250
Pin 1dB (dBm)
IIP3 (dBm)
RF Input Frequency (MHz)
Mixer 1 Linearity Performance
MIX_IDD = 5, +3.0V, IF Output = 100MHz
Input IP3 Pin 1dB
-10.0
-9.0
-8.0
-7.0
-6.0
-5.0
-4.0
-3.0
-2.0
-1.0
0.0
400 600 800 1000 1200 1400 1600 1800 2000
Conversion Gain (dB)
RF Input Frequency (MHz)
Conversion Gain of Mixer 1
IF Output = 100MHz
-40 Deg C, +2.7V
-40 Deg C, +3.0V
-40 Deg C, +3.6V
+27 Deg C, +2.7V
+27 Deg C, +3.0V
+27 Deg C, +3.6V
+85 Deg C, +2.7V
+85 Deg C, +3.0V
+85 Deg C, +3.6V
0.0
5.0
10.0
15.0
20.0
25.0
30.0
1234567
Input IP3 (dBm)
Mixer Bias Current Setting (MIX1_IDD)
Mixer 1 Input IP3 versus Bias Current
LO Frequency = 1000MHz, IF Output = 100MHz
-40 Deg C, +2.7V
-40 Deg C, +3.0V
-40 Deg C, +3.6V
+27 Deg C, +2.7V
+27 Deg C, +3.0V
+27 Deg C, +3.6V
+85 Deg C, +2.7V
+85 Deg C, +3.0V
+85 Deg C, +3.6V
20 of 26
RFFC5071A/2A
DS140110
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com.
Typical RF Mixer 2 Performance Characteristics
VDD = +3V and TA = +27°C unless stated. As measured on RFFC5071A wideband evaluation board.
See application schematic on page 13.
0.0
5.0
10.0
15.0
20.0
25.0
30.0
1234567
Input IP3 (dBm)
Mixer Bias Current Setting (MIX2_IDD)
Mixer 2 Input IP3 versus Bias Current
LO Frequency = 1000MHz, IF Output = 100MHz
-40 Deg C, +2.7V
-40 Deg C, +3.0V
-40 Deg C, +3.6V
+27 Deg C, +2.7V
+27 Deg C, +3.0V
+27 Deg C, +3.6V
+85 Deg C, +2.7V
+85 Deg C, +3.0V
+85 Deg C, +3.6V
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
500 750 1000 1250 1500 1750 2000
Noise Figure (dB)
LO Frequency (MHz)
Mixer 2 Noise Figure versus Frequency
IF Output = 100MHz
MIX_IDD = 1
MIX_IDD = 2
MIX_IDD = 3
MIX_IDD = 4
MIX_IDD = 5
MIX_IDD = 6
MIX_IDD = 7
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
1234567
Noise Figure (dB)
Mixer Bias Current Setting (MIX2_IDD)
Mixer 2 Noise Figure versus Bias Current
LO Frequency = 1000MHz, IF Output = 100MHz
-40 Deg C, +2.7V
-40 Deg C, +3.0V
-40 Deg C, +3.6V
+27 Deg C, +2.7V
+27 Deg C, +3.0V
+85 Deg C, +2.7V
+85 Deg C, +3.0V
+85 Deg C, +3.6V
0.0
5.0
10.0
15.0
20.0
25.0
30.0
0.0
5.0
10.0
15.0
20.0
25.0
30.0
500 750 1000 1250 1500 1750 2000 2250
Pin 1dB (dBm)
IIP3 (dBm)
RF Input Frequency (MHz)
Mixer 2 Linearity Performance
MIX_IDD = 5, +3.0V, IF Output = 100MHz
Input IP3 Pin 1dB
-10.0
-9.0
-8.0
-7.0
-6.0
-5.0
-4.0
-3.0
-2.0
-1.0
0.0
400 600 800 1000 1200 1400 1600 1800 2000
Conversion Gain (dB)
RF Input Frequency (MHz)
Conversion Gain of Mixer 2
IF Output = 100MHz
-40 Deg C, +2.7V
-40 Deg C, +3.0V
-40 Deg C, +3.6V
+27 Deg C, +2.7V
+27 Deg C, +3.0V
+27 Deg C, +3.6V
+85 Deg C, +2.7V
+85 Deg C, +3.0V
+85 Deg C, +3.6V
-2.0
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
1234567
Pin 1dB (dBm)
Mixer Bias Current Setting (MIX2_IDD)
Mixer 2 Input Power for 1dB Compression
LO Frequency = 1000MHz, IF Output = 100MHz
-40 Deg C, +2.7V
-40 Deg C, +3.0V
-40 Deg C, +3.6V
+27 Deg C, +2.7V
+27 Deg C, +3.0V
+27 Deg C, +3.6V
+85 Deg C, +2.7V
+85 Deg C, +3.0V
+85 Deg C, +3.6V
21 of 26
RFFC5071A/2A
DS140110
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com.
Typical Performance Characteristics of Both RF Mixers
VDD = +3V and TA = +27°C unless stated. As measured on RFFC5071A wideband evaluation board.
See application schematic on page 13.
-70.0
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
200 400 600 800 1000 1200 1400 1600 1800 2000
LO Leakage (dBm)
LO Frequency (MHz)
Typical LO Leakage at Mixer Output
+3.0V Supply Voltage
Path 1, -40 Deg C
Path 1, +27 Deg C
Path 1, +85 Deg C
Path 2, -40 Deg C
Path 2, +27 Deg C
Path 2, +85 Deg C
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
400.0 600.0 800.0 1000.0 1200.0 1400.0 1600.0
Level at Mixer 1 Output (dBm)
RF Input Frequency (MHz)
LO & RF Leakage at Mixer 1 Output
RF Input Power 0dBm, MIX1_IDD = 4
IF Output at 100MHz
LO Leakage (High Side)
RF Leakage
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
400.0 600.0 800.0 1000.0 1200.0 1400.0 1600.0
Level at Mixer 2 Output (dBm)
RF Input Frequency (MHz)
LO & RF Leakage at Mixer 2 Output
RF Input Power 0dBm, MIX2_IDD = 4
IF Output at 100MHz
LO Leakage (High Side)
RF Leakage
40.0
50.0
60.0
70.0
80.0
90.0
100.0
0 500 1000 1500 2000 2500
Isolation (dB)
RF Input Frequency (MHz)
Mixer to Mixer Isolation in Full Duplex Mode
LO = 915MHz & MIX_IDD = 4
-40 Deg C
25 Deg C
+85 Deg C
22 of 26
RFFC5071A/2A
DS140110
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com.
Typical Performance Characteristics at 3.7GHz
VDD = +3V and TA = +27°C unless stated. As measured on RFFC5071A 3.7GHz narrowband evaluation board.
Down conversion. See application schematic on page 14.
-10.0
-9.0
-8.0
-7.0
-6.0
-5.0
-4.0
-3.0
-2.0
-1.0
0.0
3400 3500 3600 3700 3800 3900 4000 4100 4200
Conversion Gain (dB)
RF Input Frequency (MHz)
Conversion Gain of Mixer 1
Down Conversion with IF Output = 200MHz
-40 Deg C, +2.7V
-40 Deg C, +3.0V
-40 Deg C, +3.3V
+27 Deg C, +2.7V
+27 Deg C, +3.0V
+27 Deg C, +3.3V
+85 Deg C, +2.7V
+85 Deg C, +3.0V
+85 Deg C, +3.3V
0.0
5.0
10.0
15.0
20.0
25.0
30.0
1234567
Input IP3 (dBm)
Mixer Bias Current Setting (MIX1_IDD)
Mixer 1 Input IP3 versus Bias Current
RF Frequency = 4000MHz, IF Output = 200MHz
-40 Deg C, +2.7V
-40 Deg C, +3.0V
-40 Deg C, +3.3V
+27 Deg C, +2.7V
+27 Deg C, +3.0V
+27 Deg C, +3.3V
+85 Deg C, +2.7V
+85 Deg C, +3.0V
+85 Deg C, +3.3V
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
3200 3400 3600 3800 4000 4200 4400
LO Leakage (dBm)
LO Frequency (MHz)
Typical LO Leakage at Mixer 1 Output
+3.0V Supply Voltage
-40 Deg C +27 Deg C
+85 Deg C
0.0
5.0
10.0
15.0
20.0
25.0
30.0
0.0
5.0
10.0
15.0
20.0
25.0
30.0
3400 3500 3600 3700 3800 3900 4000 4100 4200
Pin 1dB (dBm)
IIP3 (dBm)
RF Input Frequency (MHz)
Mixer 1 Linearity Performance
MIX_IDD = 5, +3.0V, IF Output = 200MHz
Input IP3 Pin 1dB
-80.0
-70.0
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
3400 3500 3600 3700 3800 3900 4000 4100 4200
Level at Mixer 1 Output (dBm)
RF Input Frequency (MHz)
LO & RF Leakage at Mixer 1 Output
RF Input Power -10dBm, MIX1_IDD = 4
IF Output at 200MHz
LO Leakage (Low Side)
RF Leakage
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
18.0
3400 3500 3600 3700 3800 3900 4000 4100 4200
Noise Figure (dB)
RF Input Frequency (MHz)
Mixer 1 Noise Figure versus Frequency
IF Output = 200MHz
MIX_IDD = 1
MIX_IDD = 2
MIX_IDD = 3
MIX_IDD = 4
MIX_IDD = 5
MIX_IDD = 6
MIX_IDD = 7
23 of 26
RFFC5071A/2A
DS140110
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com.
Typical Performance Characteristics at 3.7GHz
VDD = +3V and TA = +27°C unless stated. As measured on RFFC5071A 3.7GHz narrowband evaluation board.
Up conversion. See application schematic on page 14, L1 = 3.3nH.
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
3600 3800 4000 4200 4400 4600 4800 5000 5200
LO Leakage (dBm)
LO Frequency (MHz)
Typical LO Leakage at Mixer 2 Output
+3.0V Supply Voltage, MIX_IDD = 4, L1 = 3.3nH
-40°C
+27°C
+85°C
-80.0
-70.0
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
2800 3000 3200 3400 3600 3800 4000 4200 4400 4600
Level at Mixer 2 Output (dBm)
RF Output Frequency (MHz)
IF and LO Leakage at Mixer 2 Output
IF Input Power -10dBm, MIX_IDD = 4, L1 = 3.3nH
RF Output
LO Leakage (Low Side)
IF Leakage at 500MHz
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
18.0
20.0
1234567
Noise Figure (dB)
Mixer Bias Current Setting (MIX2_IDD)
Mixer 2 Noise Figure versus Bias Current
IF Input = 500MHz, RF Output = 4000MHz, L1= 3.3nH
-40°C, +2.7V -40°C, +3.0V
-40°C, +3.3V +27°C, +2.7V
+27°C, +3.0V +27°C, +3.3V
+85°C, +2.7V +85°C, +3.0V
+85°C, +3.3V
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
18.0
20.0
3200 3400 3600 3800 4000 4200 4400
Noise Figure (dB)
RF Output Frequency (MHz)
Mixer 2 Noise Figure versus Frequency
Up Conversion with IF Input = 500MHz, L1 = 3.3nH
MIX_IDD = 1 MIX_IDD = 2
MIX_IDD = 3 MIX_IDD = 4
MIX_IDD = 5 MIX_IDD = 6
MIX_IDD = 7
-16.0
-14.0
-12.0
-10.0
-8.0
-6.0
-4.0
-2.0
0.0
2750 3000 3250 3500 3750 4000 4250 4500 4750
Conversion Gain (dB)
RF Output Frequency (MHz)
Conversion Gain of Mixer 2
Up Conversion with IF Input = 500MHz, L1= 3.3nH
-40°C, +2.7V
-40°C, +3.0V
-40°C, +3.3V
+27°C, +2.7V
+27°C, +3.0V
+27°C, +3.3V
+85°C, +2.7V
+85°C, +3.0V
+85°C, +3.3V
0.0
5.0
10.0
15.0
20.0
25.0
30.0
0.0
5.0
10.0
15.0
20.0
25.0
30.0
3200 3300 3400 3500 3600 3700 3800 3900 4000 4100 4200
Pin 1dB (dBm)
IIP3 (dBm)
RF Output Frequency (MHz)
Mixer 2 Linearity Performance
MIX_IDD = 5, +3.0V, IF Input = 500MHz, L1 = 3.3nH
Input IP3 Pin 1dB
24 of 26
RFFC5071A/2A
DS140110
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com.
Typical Performance Characteristics at 3.7GHz
VDD = +3V and TA = +27°C unless stated. As measured on RFFC5071A 3.7GHz narrowband evaluation board.
Up conversion. See application schematic on page 14, L1 = 3.9nH.
Conversion Gain (dB)
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
18.0
20.0
3200 3400 3600 3800 4000 4200 4400
Noise Figure (dB)
RF Output Frequency (MHz)
Mixer 2 Noise Figure versus Frequency
Up Conversion with IF Input = 500MHz, L1 = 3.9nH
MIX_IDD = 1 MIX_IDD = 2
MIX_IDD = 3 MIX_IDD = 4
MIX_IDD = 5 MIX_IDD = 6
MIX_IDD = 7
-16.0
-14.0
-12.0
-10.0
-8.0
-6.0
-4.0
-2.0
0.0
2750 3000 3250 3500 3750 4000 4250 4500 4750
Conversion Gain (dB)
RF Output Frequency (MHz)
Conversion Gain of Mixer 2
Up Conversion with IF Input = 500MHz, L1= 3.9nH
-40°C, +2.7V
-40°C, +3.0V
-40°C, +3.3V
+27°C, +2.7V
+27°C, +3.0V
+27°C, +3.3V
+85°C, +2.7V
+85°C, +3.0V
+85°C, +3.3V
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
18.0
20.0
1234567
Noise Figure (dB)
Mixer Bias Current Setting (MIX2_IDD)
Mixer 2 Noise Figure versus Bias Current
IF Input = 500MHz, RF Output = 3700MHz, L1= 3.9nH
-40
°
C, +2.7V
-40
°
C, +3.0V
-40
°
C, +3.3V
+27
°
C, +2.7V
+27
°
C, +3.0V
+27
°
C, +3.3V
+85
°
C, +2.7V
+85
°
C, +3.0V
+85
°
C, +3.3V
0.0
5.0
10.0
15.0
20.0
25.0
30.0
0.0
5.0
10.0
15.0
20.0
25.0
30.0
3200 3300 3400 3500 3600 3700 3800 3900 4000 4100 4200
Pin 1dB (dBm)
IIP3 (dBm)
RF Output Frequency (MHz)
Mixer 2 Linearity Performance
MIX_IDD = 5, +3.0V, IF Input = 500MHz
, L1= 3.9nH
Input IP3 Pin 1dB
-80.0
-70.0
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
2800 3000 3200 3400 3600 3800 4000 4200 4400 4600
Level at Mixer 2 Output (dBm)
RF Output Frequency (MHz)
IF and LO Leakage at Mixer 2 Output
IF Input Power -10dBm, MIX_IDD = 4, L1 = 3.9nH
RF Output
LO Leakage (Low Side)
IF Leakage at 500MHz
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
3600 3800 4000 4200 4400 4600 4800 5000 5200
LO Leakage (dBm)
LO Frequency (MHz)
Typical LO Leakage at Mixer 2 Output
+3.0V Supply Voltage, MIX_IDD = 4, L1 = 3.9nH
-40°C
+27°C
+85°C
26 of 26
RFFC5071A/2A
DS140110
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com.
Ordering Information
RFFC5071A
RFFC5072A
Part Number Description Devices/Container
RFFC5071ASB 32-pin QFN 5-Piece sample bag
RFFC5071ASQ 32-pin QFN 25-Piece sample bag
RFFC5071ASR 32-pin QFN 100-Piece reel
RFFC5071ATR7 32-pin QFN 750-Piece reel
RFFC5071ATR13 32-pin QFN 2500-Piece reel
DKFC5071A Complete Design Kit (3.7GHz Baluns) 1 Box
Part Number Description Devices/Container
RFFC5072ASB 32-pin QFN 5-Piece sample bag
RFFC5072ASQ 32-pin QFN 25-Piece sample bag
RFFC5072ASR 32-pin QFN 100-Piece reel
RFFC5072ATR7 32-pin QFN 750-Piece reel
RFFC5072ATR13 32-pin QFN 2500-Piece reel
DKFC5072A Complete Design Kit (3.7GHz Baluns) 1 Box
