HCPL-M600, HCPL-M601, HCPL-M611 Small Outline, 5 Lead, High CMR, High Speed, Logic Gate Optocouplers Data Sheet Description Features These small outline high CMR, high speed, logic gate optocouplers are single channel devices in a five lead miniature footprint. They are electrically equivalent to the following Avago optocouplers (except there is no output enable feature): * Surface Mountable * Very Small, Low Profile JEDEC Registered Package Outline * Compatible with Infrared Vapor Phase Reflow and Wave Soldering Processes * Internal Shield for High Common Mode Rejection (CMR) HCPL-M601: 10,000 V/s at VCM = 50 V HCPL-M611: 15,000 V/s at VCM = 1000 V * High Speed: 10 Mbd * LSTTL/TTL Compatible * Low Input Current Capability: 5 mA * Guaranteed ac and dc Performance over Temperature: -40C to 85C * Recognized under the Component Program of U.L. (File No. E55361) for Dielectric Withstand Proof Test Voltage of 3750 Vac, 1 Minute * Lead Free Option SO-5 Package HCPL-M600 HCPL-M601 HCPL-M611 Standard DIP 6N137 HCPL-2601 HCPL-2611 SO-8 Package HCPL-0600 HCPL-0601 HCPL-0611 The SO-5 JEDEC registered (MO-155) package outline does not require "through holes" in a PCB. This package occupies approximately one fourth the footprint area of the standard dual-in-line package. The lead profile is designed to be compatible with standard surface mount processes. The HCPL-M600/01/11 optically coupled gates combine a GaAsP light emitting diode and an integrated high gain photon detector. The output of the detector I.C. is an Opencollector Schottky-clamped transistor. The internal shield provides a guaranteed common mode transient immunity specification of 5,000 V/s for the HCPL-M601, and 10,000 V/s for the HCPL-M611. This unique design provides maximum ac and dc circuit isolation while achieving TTL compatibility. The optocoupler ac and dc operational parameters are guaranteed from -40C to 85C allowing trouble free system performance. Applications * * * * * * * * * Isolated Line Receiver Simplex/Multiplex Data Transmission Computer-Peripheral Interface Microprocessor System Interface Digital Isolation for A/D, D/A Conversion Switching Power Supply Instrument Input/Output Isolation Ground Loop Elimination Pulse Transformer Replacement CAUTION: The small device geometries inherent to the design of this bipolar component increase the component's susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. The SO-5 JEDEC registered (MO-155) package outline does not require "through holes" in a PCB. This package occupies approximately one fourth the footprint area of the standard dual-in-line package. The lead profile is designed to be compatible with standard surface mount processes. The HCPL-M600/01/11 optically coupled gates combine a GaAsP light emitting diode and an integrated high gain photon detector. The output of the detector I.C. is an Open-collector Schottky-clamped transistor. The internal shield provides a guaranteed common mode transient immunity specification of 5,000 V/s for the HCPL-M601, and 10,000 V/s for the HCPL-M611. This unique design provides maximum ac and dc circuit isolation while achieving TTL compatibility. The optocoupler ac and dc operational parameters are guaranteed from 40C to 85C allowing trouble free system performance. The HCPL-M600/01/11 are suitable for high speed logic interfacing, input/output buffering, as line receivers in environments that conventional line receivers cannot tolerate, and are recommended for use in extremely high ground or induced noise environments. Ordering Information HCPL-xxxx is UL Recognized with 3750 Vrms for 1 minute per UL1577. Option Part number RoHS Compliant Non RoHS Compliant HCPL-M600 HCPL-M611 -000E No option -500E #500 HCPL-M601 -000E No option -500E #500 -560E - Package SO-5 Surface Mount Gull Wing Tape& Reel UL 5000 Vrms/ IEC/EN/DIN EN 1 Minute rating 60747-5-2 Quantity X X 100 per tube X 1500 per reel X SO-5 100 per tube X X X X 1500 per reel X 1500 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Combination of Option 020 and Option 060 is not available. Example 1: HCPL-M600-500E to order product of Surface Mount SO-5 package in Tape and Reel packaging with RoHS compliant. Example 2: HCPL-M601 to order product of Surface Mount SO-5 package in tube packaging and non RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation `#XXX' is used for existing products, while (new) products launched since 15th July 2001 and RoHS compliant option will use `-XXXE`. Outline Drawing (JEDEC MO-155) ANODE 1 4.4 0.1 (0.173 0.004) MXXX XXX 6 7.0 0.2 (0.276 0.008) VCC 5 VOUT CATHODE 3 4 GND 0.4 0.05 (0.016 0.002) 3.6 0.1* (0.142 0.004) 0.102 0.102 (0.004 0.004) 2.5 0.1 (0.098 0.004) 0.15 0.025 (0.006 0.001) 7 MAX. 1.27 BSC (0.050) 0.71 MIN. (0.028) MAX. LEAD COPLANARITY = 0.102 (0.004) DIMENSIONS IN MILLIMETERS (INCHES) * MAXIMUM MOLD FLASH ON EACH SIDE IS 0.15 mm (0.006) NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX. Land Pattern Recommendation Schematic + 4.4 (0.17) IF ICC 6 1 IO 5 1.3 (0.05) 2.5 (0.10) - 4 3 VO GND HCPL-M601/11 SHIELD 2.0 (0.080) 0.64 (0.025) 8.27 (0.325) USE OF A 0.1 F BYPASS CAPACITOR MUST BE CONNECTED BETWEEN PINS 6 AND 4 (SEE NOTE 1). HCPL-M600 Schematic VCC TRUTH TABLE (POSITIVE LOGIC) LED OUTPUT ON L OFF H Recommended Operating Conditions Parameter Input Current, Low Level Input Current, High Level Supply Voltage, Output Fan Out (RL = 1 k) Output Pull-Up Resistor Operating Temperature Symbol Min. Max. Units IFL* 0250 A IFH 5 15 mA VCC 4.5 5.5 V N 5 TTL Loads RL 330 4,000 TA -40 85 C * The off condition can also be guaranteed by ensuring that VF(off ) 0.8 volts. Absolute Maximum Ratings (No Derating Required up to 85C) Storage Temperature..............................................................................-55C to +125C Operating Temperature............................................................................-40C to +85C Forward Input Current - IF (see Note 2)...............................................................20 mA Reverse Input Voltage - VR ..............................................................................................5 V Supply Voltage - VCC (1 Minute Maximum)................................................................7 V Output Collector Current - IO ................................................................................50 mA Output Collector Power Dissipation....................................................................85 mW Output Collector Voltage - VO . ......................................................................................7 V (Selection for higher output voltages up to 20 V is available) Infrared and Vapor Phase Reflow Temperature........................................ see below Solder Reflow Thermal Profile 300 TEMPERATURE (C) PREHEATING RATE 3C + 1C/-0.5C/SEC. REFLOW HEATING RATE 2.5C 0.5C/SEC. 200 PEAK TEMP. 245C PEAK TEMP. 240C 2.5C 0.5C/SEC. SOLDERING TIME 200C 30 SEC. 160C 150C 140C PEAK TEMP. 230C 30 SEC. 3C + 1C/-0.5C 100 PREHEATING TIME 150C, 90 + 30 SEC. 50 SEC. TIGHT TYPICAL LOOSE ROOM TEMPERATURE 0 0 50 100 150 200 250 TIME (SECONDS) Note: Non-halide flux should be used. Recommended Pb-Free IR Profile tp Tp TEMPERATURE TL Tsmax 260 +0/-5 C 20-40 SEC. 217 C RAMP-UP 3 C/SEC. MAX. 150 - 200 C RAMP-DOWN 6 C/SEC. MAX. Tsmin ts PREHEAT 60 to 180 SEC. 25 tL t 25 C to PEAK TIME Note: Non-halide flux should be used. TIME WITHIN 5 C of ACTUAL PEAK TEMPERATURE 60 to 150 SEC. NOTES: THE TIME FROM 25 C to PEAK TEMPERATURE = 8 MINUTES MAX. Tsmax = 200 C, Tsmin = 150 C Insulation Related Specifications Parameter Symbol Value Units Conditions Min. External Air Gap L(IO1) 5 mm Measured from input terminals (Clearance) to output terminals Min. External Tracking Path L(IO2) 5 mm Measured from input terminals (Creepage) to output terminals Min. Internal Plastic Gap 0.08 mm Through insulation distance (Clearance) conductor to conductor Tracking Resistance CTI 175 V DIN IEC 112/VDE 0303 Part 1 Isolation Group (per DIN VDE 0109) IIIa Material Group DIN VDE 0109 Electrical Specifications Over recommended temperature (TA = -40C to 85C) unless otherwise specified. (See note 1.) Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note Input Threshold ITH2 5 mA VCC = 5.5 V, IO 13 mA, 13 Current VO = 0.6 V High Level Output IOH 5.5 100 A VCC = 5.5 V, VO = 5.5 V 1 Current IF = 250 A Low Level Output VOL 0.4 0.6 V VCC = 5.5 V, IF = 5 mA,2, 4, Voltage IOL (Sinking) = 13 mA 5, 13 High Level Supply ICCH 4 7.5 mA VCC = 5.5 V, IF = 0 mA, Current Low Level Supply ICCL 6 10.5 mA VCC = 5.5 V, IF = 10 mA, Current Input ForwardVF 1.4 1.75 V TA = 25C, IF=10 mA 3 Voltage 1.5 1.3 1.85 IF = 10 mA Input Reverse BVR 5 IR = 10 A Breakdown Voltage Input Capacitance CIN 60 pF VF = 0V, f = 1 MHz Input Diode VF/TA -1.6 mV/C IF = 10 mA 12 Temperature Coefficient Input-Output VISO 3750 VRMS RH 50%, t = 1 min. 3, 4 Insulation Resistance RI-O 1012 VI-O = 500 V 3 (Input-Output) Capacitance CI-O 0.6 pF f = 1 MHz 3 (Input-Output) *All typicals at TA = 25C, VCC = 5 V. Switching Specifications Over recommended temperature (TA = -40C to 85C), VCC = 5 V, IF = 7.5 mA unless otherwise specified. Parameter Symbol Device HCPL- Min. Typ.* Propagation tPLH 20 48 Delay Time to High Output Level 25 50 Propagation tPHL Delay Time to Low Output Level Max. 75 Unit ns TA = 25C 100 75 Test Conditions RL = 350 CL = 15 pF TA = 25C 100 Fig.Note 6, 7 8 6, 7 |tPHL - tPLH| 3.5 6 8 40 Propagation tPSK Delay Skew 35 9 Output Rise trise24 Time (10%-90%) 10 10 Output Fall tfall Time (10%-90%) 10 Pulse Width Distortion 5 10, 11 10 M600 10,000 V/s VCM = 10 V VO(min) = 2 V 11 7, 9 Common |CMH| RL = 350 Mode Transient M601 5,000 10,000 VCM = 50 V IF = 0 mA Immunity at High M611 10,000 15,000 VCM = 1000 V TA = 25C Output Level M600 10,000 VCM = 10 V VO(max) = 0.8 V 11 8, 9 Common |CMH| Mode Transient M601 5,000 10,000 VCM = 50 VRL = 350 IF = 7.5 mA Immunity at Low M611 10,000 15,000 VCM = 1000 V TA = 25C Output Level *All typicals at TA = 25C, VCC = 5 V. Notes: 1. Bypassing of the power supply line is required with a 0.1 F ceramic disc capacitor adjacent to each optocoupler. The total lead length between both ends of the capacitor and the isolator pins should not exceed 10 mm. 2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not exceed 20 mA. 3. Device considered a two terminal device: pins 1 and 3 shorted together, and pins 4, 5 and 6 shorted together. 4. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage 4500 VRMS for 1 second (Leakage detection current limit, II-O 5 A). 5. The tPLH propagation delay is measured from 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge of the output pulse. 6. The tPHL propagation delay is measured from 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge of the output pulse. 7. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state (i.e., VOUT > 2.0 V). 8. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i.e., VOUT > 0.8 V). 9. For sinusoidal voltages, (|dVCM|/dt)max = fCMVCM(p-p). 10. See application section; "Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew" for more information. 11. tPSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the worst case operating condition range. 10 5 0 -60 -40 -20 0 20 40 60 80 100 0.5 0.4 IO = 12.8 mA IO = 16 mA 0.3 IO = 6.4 mA 0.2 IO = 9.6 mA 0.1 -60 -40 -20 TA - TEMPERATURE - C VO - OUTPUT VOLTAGE - V INPUT MONITORING NODE 1 2 3 1.20 1.30 4 +5 V 1 VCC 6 0.1F BYPASS RL *CL 3 GND 4 RM *CL IS APPROXIMATELY 15 pF WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE. Figure 4. Output Voltage vs. Forward Input current. HCPL-M600 fig 4 IF = 7.5 mA INPUT IF IF = 3.75 mA IOL - LOW LEVEL OUTPUT CURRENT - mA tPHL 1.5 V 60 IF = 10 mA, 15 mA Figure 6. Test Circuit for tPHL and tPLH. 40 IF = 5.0 mA HCPL-M600 fig 6 20 0 20 40 60 80 100 TA - TEMPERATURE - C Figure 5. Low Level Output Current vs. Temperature. HCPL-M600 fig 5 tPLH OUTPUT VO VCC = 5.0 V VOL = 0.6 V 0 -60 -40 -20 1.50 Figure 3. Input Diode Forward Characteristic. 6 5 IF - FORWARD INPUT CURRENT - mA 80 1.40 1.60 VF - FORWARD VOLTAGE - VOLTS 5 RL = 4 K 1 0.01 0.001 1.10 80 100 RL = 1 K 0 0.1 PULSE GEN. ZO = 50 tf = tr = 5 ns RL = 350 2 0 60 1.0 HCPL-M600 fig 3 IF 3 40 IF + VF - HCPL-M600 Figure 2 VCC = 5 V TA = 25 C 4 20 Figure 2. Low Level Output Voltage vs. Temperature. HCPL-M600 fig 1 5 0 TA = 25C 10 TA - TEMPERATURE - C Figure 1. High Level Output Current vs. Temperature. 6 100 VCC = 5.5 V IF = 5.0 mA IF - FORWARD CURRENT - mA VCC = 5.5 V VO = 5.5 V IF = 250 A VOL - LOW LEVEL OUTPUT VOLTAGE - V IOH - HIGH LEVEL OUTPUT CURRENT - A 15 OUTPUT VO MONITORING NODE 80 tPLH , RL = 4 K tPHL , RL = 350 1 K 60 4 K tPLH , RL = 1 K 40 tPLH , RL = 350 20 0 -60 -40 -20 0 20 40 80 100 60 VCC = 5.0 V TA = 25C 75 tPLH , RL = 350 60 tPLH , RL = 1 K 45 tPHL , RL = 350 1 K 4 K 30 5 7 9 Figure 7. Propagation Delay vs. Temperature. tr, tf - RISE, FALL TIME - ns VCC = 5.0 V IF = 7.5 mA 20 10 RL = 350 k 0 RL = 1 k -10 -60 -40 -20 0 1 VCC 6 A 5 VFF 3 GND 0.1 F BYPASS 350 OUTPUT VO MONITORING NODE 4 40 RL = 350 _ + PULSE GENERATOR ZO = 50 TA - TEMPERATURE - C VCM Figure 10. Rise and Fall Time vs. Temperature. HCPL-M600 fig 10 VO VCM (PEAK) 0V 5V dVF/dT - FORWARD VOLTAGE TEMPERATURE COEFFICIENT - mV/C VO 0.5 V SWITCH AT A: IF = 0 mA VO (MIN.) SWITCH AT B: IF = 7.5 mA VO (MAX.) CMH CML -2.4 -2.2 Figure 11. Test Circuit for Common Mode Transient Immunity and Typical Waveforms. -2.0 HCPL-M600 fig 11 -1.8 -1.6 -1.4 1 60 10 100 IF - PULSE INPUT CURRENT - mA Figure 12. Temperature Coefficient for Forward Voltage vs. Input Current. HCPL-M600 Figure 12 80 100 Figure 9. Pulse Width Distortion vs. Temperature. +5 V B RL = 1 k -1.2 0.1 40 IF tRISE tFALL 290 20 20 TA - TEMPERATURE - C HCPL-M600 fig 9 RL = 350 , 1 k, 4 k 0 -60 -40 -20 0 20 40 60 80 100 15 RL = 4 k 30 HCPL-M600 fig 8 RL = 4 k 60 13 Figure 8. Propagation Delay vs. Pulse Input Current. HCPL-M600 fig 7 300 11 40 IF - PULSE INPUT CURRENT - mA TA - TEMPERATURE - C VCC = 5.0 V IF = 7.5 mA tPLH , RL = 4 K 90 PWD - PULSE WIDTH DISTORTION - ns 105 VCC = 5.0 V IF = 7.5 mA tP - PROPAGATION DELAY - ns tP - PROPAGATION DELAY - ns 100 Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew Propagation delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propagation delay from low to high (tPLH) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (tPHL) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low (see Figure 7). Pulse-width distortion (PWD) results when tPLH and tPHL differ in value. PWD is defined as the difference between tPLH and tPHL and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 20-30% of the minimum pulse width is tolerable; the exact figure depends on the particular application (RS232, RS422, T-1, etc.). operating temperature). As illustrated in Figure 15, if the inputs of a group of optocouplers are switched either ON or OFF at the same time, tPSK is the difference between the shortest propagation delay, either tPLH or tPHL, and the longest propagation delay, either tPLH or tPHL. As mentioned earlier, tPSK can determine the maximum parallel data transmission rate. Figure 11 is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. Propagation delay skew, tPSK, is an important parameter to consider in parallel data applications where synchroniza tion of signals on parallel data lines is a concern. If the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delays is large enough, it will determine the maximum rate at which parallel data can be sent through the optocouplers. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure 16 shows that there will be uncertainty in both the data and the clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice tPSK. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either tPLH or tPHL, for any given group of optocouplers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and The tPSK specified optocouplers offer the advantages of guaranteed specifications for propagation delays, pulsewidth distortion and propagation delay skew over the recommended temperature, and input current, and power supply ranges. ITH - INPUT THRESHOLD CURRENT - mA 6 5 VCC = 5.0 V VO = 0.6 V VCC1 5V 6 IF VF 2 1 4 2 1 20 40 60 * DIODE D1 (1N916 OR EQUIVALENT) IS NOT REQUIRED FOR UNITS WITH OPEN COLLECTOR OUTPUT. 80 100 TA - TEMPERATURE - C Figure 13. Input Threshold Current vs. Temperature. Figure 14. Recommended TTL/LSTTL to TTL/LSTTL Interface Circuit. HCPL-M600 fig 13 HCPL-M600 fig 14 DATA IF INPUTS 50% CLOCK 1.5 V VO IF DATA 50% OUTPUTS VO 1.5 V tPSK CLOCK tPSK Figure 15. Illustration of Propagation Delay Skew - tPSK. GND 2 SHIELD RL = 4 k 0 0.1 F BYPASS 3 GND 1 0 -60 -40 -20 5 1 *D1 RL = 350 RL = 1 k VCC 2 390 470 4 3 5V tPSK Figure 16. Parallel Data Transmission Example. HCPL-M600 fig 15 HCPL-M600 fig 16 For product information and a complete list of distributors, please go to our website: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries. Data subject to change. Copyright (c) 2007 Avago Technologies Limited. All rights reserved. Obsoletes AV01-0562EN AV01-0941EN - December 24, 2007