1
3
2
4
8
6
7
5
V
CC
GND
V
OUT
Hermetically Sealed, Low IF,
Wide VCC, High Gain
Optocouplers
Technical Data
Features
• Dual Marked with Device
Part Number and DSCC
Drawing Number
• Manufactured and Tested on
a MIL-PRF-38534 Certified
Line
• QML-38534, Class H and K
• Five Hermetically Sealed
Package Configurations
• Performance Guaranteed,
Over -55°C to +125°C
• Low Input Current
Requirement: 0.5 mA
• High Current Transfer
Ratio: 1500% Typical @
IF= 0.5 mA
• Low Output Saturation
Voltage: 0.11 V Typical
• 1500 Vdc Withstand Test
Voltage
• High Radiation Immunity
• 6N138/9, HCPL-2730/31
Function Compatibility
• Reliability Data
Applications
• Military and Space
• High Reliability Systems
• Telephone Ring Detection
• Microprocessor System
Interface
• Transportation, Medical, and
Life Critical Systems
• Isolated Input Line Receiver
• EIA RS-232-C Line Receiver
• Voltage Level Shifting
• Isolated Input Line Receiver
• Isolated Output Line Driver
• Logic Ground Isolation
• Harsh Industrial Environments
• Current Loop Receiver
• System Test Equipment
Isolation
• Process Control
Input/Output Isolation
Description
These units are single, dual, and
quad channel, hermetically sealed
optocouplers. The products are
capable of operation and storage
over the full military temperature
range and can be purchased as
either standard product or with
full MIL-PRF-38534 Class Level
H or K testing or from the appro-
priate DSCC Drawing. All devices
are manufactured and tested on a
MIL-PRF-38534 certified line and
are included in the DSCC Quali-
fied Manufacturers List QML-
38534 for Hybrid Microcircuits.
Each channel contains a GaAsP
light emitting diode which is
optically coupled to an integrated
high gain photon detector. The
high gain output stage features
an open collector output providing
both lower saturation voltage and
higher signaling speed than
possible with conventional photo-
Darlington optocouplers. The
shallow depth and small junctions
offered by the IC process
provides better radiation
immunity than conventional
photo transistor optocouplers.
The supply voltage can be
operated as low as 2.0 V without
adversely affecting the
parametric performance.
Functional Diagram
Multiple Channel Devices
Available
Truth Table
(Positive Logic)
Input Output
On (H) L
Off (L) H
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.
*See matrix for available extensions.
5962-89810
HCPL-573X
HCPL-673X
5962-89785
5962-98002
6N140A*
HCPL-675X
83024
HCPL-570X
HCPL-177K
2
These devices have a 300%
minimum CTR at an input current
of only 0.5 mA making them ideal
for use in low input current
applications such as MOS, CMOS,
low power logic interfaces or line
receivers. Compatibility with high
voltage CMOS logic systems is
assured by specifying ICCH and
IOH at 18 Volts.
Upon special request, the follow-
ing device selections can be
made: CTR minimum of up to
600% at 0.5 mA, and lower
output leakage current levels to
100 µA.
Package styles for these parts are
8 and 16 pin DIP through hole
(case outlines P and E respec-
tively), 16 pin DIP flat pack (case
outline F), and leadless ceramic
chip carrier (case outline 2).
Devices may be purchased with a
variety of lead bend and plating
options. See Selection Guide
table for details. Standard
Military Drawing (SMD) parts are
available for each package and
lead style.
Because the same electrical die
(emitters and detectors) are used
for each channel of each device
listed in this data sheet, absolute
maximum ratings, recommended
operating conditions, electrical
specifications, and performance
characteristics shown in the
figures are similar for all parts
except as noted. Additionally, the
same package assembly processes
and materials are used in all
devices. These similarities justify
the use of a common data base
for die related reliability and
certain limited radiation test
results.
Selection Guide-Package Styles and Lead Configuration Options
16 pin 20 Pad
Package 16 pin DIP 8 pin DIP 8 pin DIP Flat Pack LCCC
Lead Style Through Hole Through Hole Through Hole Unformed Leads Surface Mount
Channels 4 1 2 4 2
Common Channel Wiring VCC, GND None VCC, GND VCC, GND None
HP Part # & Options
Commercial 6N140A* HCPL-5700 HCPL-5730 HCPL-6750 HCPL-6730
MIL-PRF-38534 Class H 6N140A/883B HCPL-5701 HCPL-5731 HCPL-6751 HCPL-6731
MIL-PRF-38534 Class K HCPL-177K HCPL-570K HCPL-573K HCPL-675K HCPL-673K
Standard Lead Finish Gold Plate Gold Plate Gold Plate Gold Plate Solder Pads
Solder Dipped Option #200 Option #200 Option #200
Butt Cut/Gold Plate Option #100 Option #100 Option #100
Gull Wing/Soldered Option #300 Option #300 Option #300
Crew Cut/Gold Plate Option #600 Option #600 Option #600
Class H SMD Part #
Prescript for all below None 5962- 5962- None 5962-
Either Gold or Solder 8302401EX 8981001PX 8978501PX 8302401FX 89785022X
Gold Plate 8302401EC 8981001PC 8978501PC 8302401FC
Solder Dipped 8302401EA 8981001PA 8978501PA 89785022A
Butt Cut/Gold Plate 8302401YC 8981001YC 8978501YC
Butt Cut/Soldered 8302401YA 8981001YA 8978501YA
Gull Wing/Soldered 8302401XA 8981001XA 8978501ZA
Crew Cut/Gold Plate 8302401ZC Available Available
Crew Cut/Soldered 8302401ZA Available Available
Class K SMD Part #
Prescript for all below 5962- 5962- 5962- 5962- 5962-
Either Gold or Solder 9800201KEX 8981002KPX 8978503KPX 9800201KFX 8978504K2X
Gold Plate 9800201KEC 8981002KPC 8978503KPC 9800201KFC
Solder Dipped 9800201KEA 8981002KPA 8978503KPA 8978504K2A
Butt Cut/Gold Plate 9800201KYC 8981002KYC 8978503KYC
Butt Cut/Soldered 9800201KYA 8981002KYA 8978503KYA
Gull Wing/Soldered 9800201KXA 8981002KXA 8978503KZA
Crew Cut/Gold Plate 9800201KZC Available Available
Crew Cut/Soldered 9800201KZA Available Available
*JEDEC registered part.
3
Functional Diagrams
16 pin DIP 8 pin DIP 8 pin DIP 16 pin Flat Pack 20 Pad LCCC
Through Hole Through Hole Through Hole Unformed Leads Surface Mount
4 Channels 1 Channel 2 Channels 4 Channels 2 Channels
Note: All DIP and flat pack devices have common VCC and ground. LCCC (leadless ceramic chip carrier) package has isolated channels
with separate VCC and ground connections.
5
7
6
8
12
10
11
9
GND
V
O4
V
O3
1
3
2
4
16
14
15
13
V
CC
V
O2
V
O1
1
3
2
4
8
6
7
5
V
CC
GND
V
O2
V
O1
5
7
6
8
12
10
11
9
GND
V
O4
V
O3
1
3
2
4
16
14
15
13
V
CC
V
O2
V
O1
Outline Drawings
16 Pin DIP Through Hole, 4 Channels
Leadless Device MarkingLeaded Device Marking
1
3
2
4
8
6
7
5
V
CC
GND
V
OUT
GND
1
V
O2
19
20
2
3
V
O1
87
V
CC2
V
CC1
10
GND
2
15
13
12
4.45 (0.175)
MAX.
20.06 (0.790)
20.83 (0.820)
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MIN.
0.89 (0.035)
1.65 (0.065)
8.13 (0.320)
MAX.
7.36 (0.290)
7.87 (0.310)
0.20 (0.008)
0.33 (0.013)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
3.81 (0.150)
MIN.
HP QYYWWZ
XXXXXX
XXXXXXX
XXX USA
50434
HP LOGO
HP P/N
DSCC SMD*
DSCC SMD*
PIN ONE/
ESD IDENT
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
COUNTRY OF MFR.
HP FSCN*
*QUALIFIED PARTS ONLY
•
HP QYYWWZ
XXXXXX
XXXX
XXXXXX
USA 50434
HP P/N
PIN ONE/
ESD IDENT
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
DSCC SMD*
DSCC SMD*
HP FSCN*
*QUALIFIED PARTS ONLY
•
4
Outline Drawings (continued)
16 Pin Flat Pack, 4 Channels
20 Terminal LCCC Surface Mount, 2 Channels 8 Pin DIP Through Hole, 1 and 2 Channel
8.13 (0.320)
MAX.
5.23
(0.206)
MAX.
2.29 (0.090)
MAX.
7.24 (0.285)
6.99 (0.275)
1.27 (0.050)
REF.
0.46 (0.018)
0.36 (0.014)
11.13 (0.438)
10.72 (0.422)
2.85 (0.112)
MAX.
0.89 (0.035)
0.69 (0.027)
0.31 (0.012)
0.23 (0.009)
0.88 (0.0345)
MIN.
9.02 (0.355)
8.76 (0.345)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
8.70 (0.342)
9.10 (0.358)
4.95 (0.195)
5.21 (0.205)
1.78 (0.070)
2.03 (0.080) 1.02 (0.040) (3 PLCS)
4.95 (0.195)
5.21 (0.205)
8.70 (0.342)
9.10 (0.358)
1.78 (0.070)
2.03 (0.080)
0.51 (0.020)
0.64
(0.025)
(20 PLCS)
1.52 (0.060)
2.03 (0.080)
METALIZED
CASTILLATIONS (20 PLCS)
2.16 (0.085)
TERMINAL 1 IDENTIFIER
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
SOLDER THICKNESS 0.127 (0.005) MAX.
1.14 (0.045)
1.40 (0.055)
3.81 (0.150)
MIN.
4.32 (0.170)
MAX.
9.40 (0.370)
9.91 (0.390)
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MIN.
0.76 (0.030)
1.27 (0.050)
8.13 (0.320)
MAX.
7.36 (0.290)
7.87 (0.310)
0.20 (0.008)
0.33 (0.013)
7.16 (0.282)
7.57 (0.298)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
5
Hermetic Optocoupler Options
Option Description
100
200
300
600
Lead finish is solder dipped rather than gold plated. This option is available on commercial and hi-rel
product in 8 and 16 pin DIP. DSCC Drawing part numbers contain provisions for lead finish. All leadless
chip carrier devices are delivered with solder dipped terminals as a standard feature.
Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is
available on commercial and hi-rel product in 8 and 16 pin DIP (see drawings below for details). Contact
factory for the availability of this option on DSCC part types.
Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This option is
available on commercial and hi-rel product in 8 and 16 pin DIP (see drawings below for details). This
option has solder dipped leads.
Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is
available on commercial and hi-rel product in 8 and 16 pin DIP (see drawings below for details).
1.14 (0.045)
1.40 (0.055)
4.32 (0.170)
MAX.
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MIN.
1.14 (0.045)
1.40 (0.055)
4.32 (0.170)
MAX.
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MIN.
7.36 (0.290)
7.87 (0.310)
0.20 (0.008)
0.33 (0.013)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
1.40 (0.055)
1.65 (0.065)
4.57 (0.180)
MAX.
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MIN.
3.81 (0.150)
MIN.
1.14 (0.045)
1.25 (0.049)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MIN. 7.36 (0.290)
7.87 (0.310)
0.20 (0.008)
0.33 (0.013)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
3.81 (0.150)
MAX.
1.02 (0.040)
TYP.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MIN.
0.51 (0.020)
MIN.
4.57 (0.180)
MAX.
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
1.40 (0.055)
1.65 (0.065) 9.65 (0.380)
9.91 (0.390)
5° MAX.
4.57 (0.180)
MAX.
0.20 (0.008)
0.33 (0.013)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
6
Absolute Maximum Ratings
Storage Temperature Range, TS.................................. -65°C to +150°C
Operating Temperature, TA......................................... -55°C to +125°C
Case Temperature, TC............................................................... +170°C
Junction Temperature, TJ......................................................... +175°C
Lead Solder Temperature ................................................ 260°C for 10s
Output Current, IO (Each Channel)..............................................40 mA
Output Voltage, VO (Each Channel) .................................-0.5 to 20 V[1]
Supply Voltage, VCC ..........................................................-0.5 to 20 V[1]
Output Power Dissipation (Each Channel) ............................. 50 mW[2]
Peak Input Current (Each Channel, <1 ms Duration) .................20 mA
Average Input Current, IF (Each Channel)............................... 10 mA[3]
Reverse Input Voltage, VR (Each Channel)......................................... 5V
Package Power Dissipation, PD (each channel) ........................200 mW
ESD Classification
(MIL-STD-883, Method 3015)
HCPL-5700/01/0K and 6730/31/3K .................................. (∆∆), Class 2
6N140A, 6N140A/883B, HCPL-177K,
HCPL-6750/51/5K and HCPL-5730/31/3K................ (Dot), Class 3
Recommended Operating Conditions
Parameter Symbol Min. Max. Units
Input Voltage, Low Level (Each Channel) VF(OFF) 0.8 V
Input Current, High Level (Each Channel) IF(ON) 0.5 5 mA
Supply Voltage VCC 2.0 18 V
Output Voltage VO2.0 18 V
ANODE
3
CATHODE 6
5
V
CC
V
O
I
CC
GND
I
O
I
F
2
+
–
V
F
8
8 Pin Ceramic DIP Single Channel Schematic
7
Electrical Characteristics, T
A= -55°C to +125°C, unless otherwise specified
Group
A[13]
Sym- Sub-
Parameter bol Test Conditions Group Min. Typ.** Max. Units Fig. Note
Current Transfer CTR* IF= 0.5 mA, VO= 0.4 V, 1, 2, 3 300 1500 % 3 4, 5
Ratio VCC = 4.5 V
IF= 1.6 mA, VO= 0.4 V, 300 1000
VCC = 4.5 V
IF= 5 mA, VO= 0.4 V, 200 500
VCC = 4.5 V
Logic Low Output VOL IF= 0.5 mA, IOL = 1.5 mA, 1, 2, 3 0.11 0.4 V 2 4
Voltage VCC = 4.5 V
IF= 1.6 mA, IOL = 4.8 mA, 0.13 0.4 4, 16
VCC = 4.5 V
IF= 5 mA, IOL = 10 mA, 0.16 0.4 4
VCC = 4.5 V
Logic High Output IOH*I
F
=2 µA, VO= 18 V, 1, 2, 3 0.001 250 µA4
I
OHX 250 µA 4, 6
Logic Single Channel ICCL*I
F
= 1.6 mA, VCC = 18 V 1, 2, 3 1.0 2 mA 15
Low and LCCC
Dual Channel IF1 =I
F2 = 1.6 mA, 1.0 4 4
VCC = 18 V
Quad Channel IF1 = IF2 =I
F3 =I
F4 = 1.6 mA 1.7 4
VCC = 18 V
Logic Single Channel ICCH*I
F
= 0 mA, VCC = 18 V 1, 2, 3 0.001 20 µA15
High and LCCC
Dual Channel IF1 =I
F2 = 0 mA, 40
VCC = 18 V
Quad Channel IF1 =I
F2 =I
F3 =I
F4 =0 mA 40
V
CC = 18 V
Input Single and VF*I
F
= 1.6 mA 1 1.0 1.4 1.7 V 1 4
2 1.7
3 1.8
LCCC 1, 2, 3 1.0 1.4 1.8
Quad Channel 1, 2 1.4 1.7
3 1.8
Input Reverse BVR*I
R
= 10 µA 1, 2, 3 5 V 4
Breakdown Voltage
Input-Output II-O* 45% Relative Humidity 1 1.0 µA 7, 12
Insulation TA=25°C, t = 5 s,
Leakage Current VI-O = 1500 VDC
Capacitance Between CI-O f = 1 MHz, TA=25°C 4 4 pF 4, 8
Input-Output 14, 17
*For JEDEC registered parts.
**All typical values are at VCC = 5 V, TA = 25°C.
Current
Supply
Current
Supply
Current
V
CC = 18 V
Forward
Voltage
Limits
Dual Channel
8
Electrical Characteristics (cont) TA= -55°C to +125°C, unless otherwise specified
Group
A[13]
Sym- Sub-
Parameter bol Test Conditions Group Min. Typ.** Max. Units Fig. Note
Propagation Delay tPHL*I
F
= 0.5 mA, RL= 4.7 kΩ, 9, 10, 11 30 100 µs 5, 6, 4
Time to Logic Low VCC = 5 V 7, 8
tPHL IF= 1.6 mA, RL= 1.5 kΩ, 9, 10, 11 5 30 4, 16
VCC =5 V
t
PHL*I
F
= 5 mA, RL= 680 Ω, 9 2 5 4, 17
10, 11 10
9, 10, 11 10 4, 16
Propagation Delay tPLH*I
F
= 0.5 mA, RL= 4.7 kΩ, 9, 10, 11 17 60 µs 5, 6, 4
Time to Logic High VCC = 5 V 7, 8
tPLH IF= 1.6 mA, RL= 1.5 kΩ, 9, 10, 11 14 50 4, 16
VCC =5 V
t
PLH*I
F
= 5 mA, RL= 680 Ω, 9 8 20 4, 17
10, 11 30
9, 10, 11 30 4, 16
Common Mode |CML|V
CC = 5 V, |V CM| = 25 VP-P[17] 9, 10, 11 500 1000 V/µs9
Transient Immunity IF= 1.6 mA 4, 10
at Low Output Level RL= 1.5 kΩ11, 14
Common Mode |CMH|V
CC = 5 V, |V CM| = 25 VP-P[17] 9, 10, 11 500 1000 V/µs9
Transient Immunity IF= 0 mA 4, 10
at High Output Level RL= 1.5 kΩ11, 14
*For JEDEC registered parts.
**All typical values are at VCC =5 V, T
A=25°C.
|V CM| = 50 VP-P[16]
Typical Characteristics, T
A=25°C, VCC =5V
Parameter Sym. Typ. Units Test Conditions Note
Input Capacitance CIN 60 pF VF= 0V, f = 1 MHz 4
Input Diode Temperature ∆VF/∆TA-1.8 mV/°CI
F
= 1.6 mA 4
Coefficient
Resistance (Input-Output) RI-O 1012 ΩVI-O = 500 V 4, 8
Capacitance (Input-Output) CI-O 2.0 pF f = 1MHz 4, 8
Dual and Quad Channel Product Only
Input-Input Leakage Current II-I 0.5 nA Relative Humidity = 45%, 9
VI-I = 500 V, t = 5 s
Resistance (Input-Input) RI-I 1012 ΩVI-I = 500 V 9
Capacitance (Input-Input) CI-I 1.0 pF f = 1 MHz 9
at Output
at Output
VCC =5 V
V
CC =5 V
Limits
|V CM| = 50 VP-P[16]
9
Notes:
1. GND Pin should be the most negative
voltage at the detector side. Keeping
VCC as low as possible, but greater
than 2.0 V, will provide lowest total
IOH over temperature.
2. Output power is collector output
power plus total supply power for the
single channel device. For the dual
channel device, output power is
collector output power plus one half
the total supply power. For the quad
channel device, output power is
collector output power plus one
fourth of total supply power. Derate
at 1.66 mW/°C above 110°C.
3. Derate IF at 0.33 mA/°C above 110°C.
4. Each channel.
5. CURRENT TRANSFER RATIO is
defined as the ratio of output
collector current, IO, to the forward
LED input current, IF, times 100%.
6. IOHX is the leakage current resulting
from channel to channel optical
crosstalk. IF=2 µA for channel under
test. For all other channels,
IF= 10 mA.
7. All devices are considered two-
terminal devices; measured between
all input leads or terminals shorted
together and all output leads or
terminals shorted together.
8. Measured between each input pair
shorted together and all output
connections for that channel shorted
together.
9. Measured between adjacent input
pairs shorted together for each multi-
channel device.
10. CML is the maximum rate of rise of
the common mode voltage that can be
sustained with the output voltage in
the logic low state (VO < 0.8 V). CMH
is the maximum rate of fall of the
common mode voltage that can be
sustained with the output voltage in
the logic high state (VO > 2.0 V).
11. In applications where dV/dt may
exceed 50,000 V/µs (such as a static
discharge) a series resistor, RCC,
should be included to protect the
detector ICs from destructively high
surge currents. The recommended
value is: 1 (V)
RCC = ——––––––– kΩ
0.15 IF (mA)
for single channel;
1 (V)
RCC = ——––––––– kΩ
0.3 IF (mA)
for dual channel;
1 (V)
RCC = —–––––—–– kΩ
0.6 IF (mA)
for quad channel.
12. This is a momentary withstand test,
not an operating condition.
13. Standard parts receive 100% testing
at 25°C (Subgroups 1 and 9). SMD
and 883B parts receive 100% testing
at 25,125, and -55°C (Subgroups 1
and 9, 2 and 10, 3 and 11,
respectively).
14. Parameters tested as part of device
initial characterization and after
design and process changes.
Parameters guaranteed to limits
specified for all lots not specifically
tested.
15. The HCPL-6730, HCPL-6731, and
HCPL-673K dual channel parts
function as two independent single
channel units. Use the single channel
parameter limits.
16. Not required for 6N140A, 6N140A/
883B, HCPL-177K, HCPL-6750/51/
5K, 8302401, and 5962-9800201
types.
17. Required for 6N140A, 6N140A/883B,
HCPL-177K, HCPL-6750/51/5K,
8302401, and 5962-9800201 types.
10
Figure 2. Normalized DC Transfer
Characteristics. Figure 3. Normalized Current
Transfer Ratio vs. Input Diode
Forward Current.
Figure 1. Input Diode Forward
Current vs. Forward Voltage.
Figure 4. Normalized Supply Current
vs. Input Diode Forward Current. Figure 5. Propagation Delay to Logic
Low vs. Input Pulse Period. Figure 6. Propagation Delay vs.
Temperature.
Figure 7. Propagation Delay vs. Input
Diode Forward Current.
11
Figure 8. Switching Test Circuit (f, tP
not JEDEC registered).
Figure 9. Test Circuit for Transient Immunity and
Typical Waveforms.
Figure 10. Recommended Drive Circuitry Using TTL Open-Collector Logic.
GND
V
CC
I
F
R
L
R
CC
*56 Ω
1.0 µF
+5 V
V
O
* SEE NOTE 11
D.U.T.
Rm
I
F
MONITOR
PULSE GEN.
Z
O
= 50 Ω
t
r
, t
f
= 50 ns
f = 100 Hz
t
PULSE
= 0.5ms
C
L
**
** C
L
INCLUDES PROBE AND STRAY WIRING CAPACITANCE.
V
FF
GND
V
CC
I
F
V
CM
R
L
R
CC
* 56 Ω
1.0 µF
+5 V
V
O
+–
PULSE GEN.
* SEE NOTE 11
A
BD.U.T.
GND
V
CC
I
LEAK
V
O
D.U.T.
R
2
MAY BE OMITTED
IF ADDITIONAL FANOUT
IS NOT USED.
R
1
R
2
V
CC
R
2
>2.4 - V
F
I
F
R
1
<V
CC
- V
F
- I
F
R
2
I
F
+
I
LEAK
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Data subject to change.
Copyright © 1997 Hewlett-Packard Co.
Obsoletes 5964-2063E
Printed in U.S.A. 5966-2799E (12/97)
MIL-PRF-38534 Class H,
Class K, and DSCC SMD
Test Program
Hewlett-Packard’s Hi-Rel
Optocouplers are in compliance
with MIL-PRF-38534 Class H and
K. Class H and Class K devices
are also in compliance with DSCC
drawings 83024, 5962-89785,
5962-89810, and 5962-98002.
Testing consists of 100% screen-
ing and quality conformance
inspection to MIL-PRF-38534.
Figure 11. Operating Circuit for Burn-In and Steady State Life Tests.
GND
V
CC
V
O
D.U.T.*
* ALL CHANNELS TESTED SIMULTANEOUSLY.
V
OC
CONDITIONS: I
F
= 10 mA
V
CC
+ 18 V
V
IN
+–
(EACH OUTPUT)
(EACH INPUT)
I
O
= 40 mA
T
A
= +125 °C
0.01 µF
