Document Number: 91174 www.vishay.com
S09-0518-Rev. B, 13-Apr-09 1
Power MOSFET
IRFIB5N65A, SiHFIB5N65A
Vishay Siliconix
FEATURES
• Low Gate Charge Qg Results in Simple Drive
Requirement
• Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
• Fully Characterized Capacitance and Avalanche Voltage
and Current
• Compliant to RoHS directive 2002/95/EC
APPLICATIONS
• Switch Mode Power Supply (SMPS)
• Uninterruptible Power Supply
• High Speed Power Switching
• High Voltage Isolation = 2.5 kVRMS (t = 60 s, f = 60 Hz)
TYPICAL SMPS TOPOLOGIES
• Single Transistor Flyback
• Single Transistor Forward
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting TJ = 25 °C, L = 24 mH, RG = 25 Ω, IAS = 5.2 A (see fig. 12).
c. ISD ≤ 5.2 A, dI/dt ≤ 90 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.
e. Drain current limited by maximum junction temperature.
PRODUCT SUMMARY
VDS (V) 650
RDS(on) (Ω)V
GS = 10 V 0.93
Qg (Max.) (nC) 48
Qgs (nC) 12
Qgd (nC) 19
Configuration Single
N-Channel MOSFET
G
D
S
S
D
G
TO-220 FULLPAK
Available
RoHS*
COMPLIANT
ORDERING INFORMATION
Package TO-220 FULLPAK
Lead (Pb)-free IRFIB5N65APbF
SiHFIB5N65A-E3
SnPb IRFIB5N65A
SiHFIB5N65A
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage VDS 650 V
Gate-Source Voltage VGS ± 30
Continuous Drain Currente
VGS at 10 V TC = 25 °C ID
5.1
A
Continuous Drain Current TC = 100 °C 3.2
Pulsed Drain CurrentaIDM 21
Linear Derating Factor 0.48 W/°C
Single Pulse Avalanche EnergybEAS 325 mJ
Repetitive Avalanche CurrentaIAR 5.2 A
Repetitive Avalanche EnergyaEAR 6mJ
Maximum Power Dissipation TC = 25 °C PD60 W
Peak Diode Recovery dV/dtcdV/dt 2.8 V/ns
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to + 150 °C
Soldering Recommendations (Peak Temperature)dfor 10 s 300
Mounting Torque 6-32 or M3 screw 10 lbf · in
1.1 N · m
* Pb containing terminations are not RoHS compliant, exemptions may apply
www.vishay.com Document Number: 91174
2S09-0518-Rev. B, 13-Apr-09
IRFIB5N65A, SiHFIB5N65A
Vishay Siliconix
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.
c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDS.
d. t = 60 s, f = 60 Hz.
THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL TYP. MAX. UNIT
Maximum Junction-to-Ambient RthJA -65
°C/W
Maximum Junction-to-Case (Drain) RthJC -2.1
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = 250 µA 650 - - V
VDS Temperature Coefficient ΔVDS/TJ Reference to 25 °C, ID = 1 mAd- 670 - mV/°C
Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 µA 2.0 - 4.0 V
Gate-Source Leakage IGSS V
GS = ± 30 V - - ± 100 nA
Zero Gate Voltage Drain Current IDSS
VDS = 650 V, VGS = 0 V - - 25 µA
VDS = 520 V, VGS = 0 V, TJ = 125 °C - - 250
Drain-Source On-State Resistance RDS(on) V
GS = 10 V ID = 3.1 Ab- - 0.93 Ω
Forward Transconductance gfs VDS = 50 V, ID = 3.1 A 3.9 - - S
Dynamic
Input Capacitance Ciss VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
- 1417 -
pF
Output Capacitance Coss - 177 -
Reverse Transfer Capacitance Crss -7.0-
Output Capacitance Coss VGS = 0 V
VDS = 1.0 V, f = 1.0 MHz - 1912 -
VDS = 520 V, f = 1.0 MHz - 48 -
Effective Output Capacitance Coss eff. VDS = 0 V to 520 Vc-84-
Total Gate Charge Qg
VGS = 10 V ID = 5.2 A, VDS = 400 V
see fig. 6 and 13b
--48
nC Gate-Source Charge Qgs --12
Gate-Drain Charge Qgd --19
Turn-On Delay Time td(on)
VDD = 325 V, ID = 5.2 A
RG = 9.1 Ω, RD = 62 Ω,
see fig. 10b
-14-
ns
Rise Time tr -20-
Turn-Off Delay Time td(off) -34-
Fall Time tf -18-
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current IS
MOSFET symbol
showing the
integral reverse
p - n junction diode
--5.2
A
Pulsed Diode Forward CurrentaISM --21
Body Diode Voltage VSD TJ = 25 °C, IS = 5.2 A, VGS = 0 Vb--1.5V
Body Diode Reverse Recovery Time trr TJ = 25 °C, IF = 5.2 A, dI/dt = 100 A/µsb- 493 739 ns
Body Diode Reverse Recovery Charge Qrr -2.13.2µC
Forward Turn-On Time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
S
D
G
Document Number: 91174 www.vishay.com
S09-0518-Rev. B, 13-Apr-09 3
IRFIB5N65A, SiHFIB5N65A
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Fig. 1 - Typical Output Characteristics
Fig. 2 - Typical Output Characteristics
Fig. 3 - Typical Transfer Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
0.1
1
10
100
0.1 1 10 100
20µs PULSE WIDTH
T = 25 C
J°
TOP
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
V , Drain-to-Source Voltage (V)
I , Drain-to-Source Current (A)
DS
D
4.5V
0.1
1
10
100
1 10 100
20µs PULSE WIDTH
T = 150 C
J°
TOP
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
V , Drain-to-Source Voltage (V)
I , Drain-to-Source Current (A)
DS
D
4.5V
0.1
1
10
100
4.0 5.0 6.0 7.0 8.0 9.0
V = 100V
20µs PULSE WIDTH
DS
V , Gate-to-Source Voltage (V)
I , Drain-to-Source Current (A)
GS
D
T = 25 C
J°
T = 150 C
J°
-60 -40 -20 020 40 60 80100 120 140 160
0.0
0.5
1.0
1.5
2.0
2.5
3.0
T , Junction Temperature ( C)
R , Drain-to-Source On Resistance
(Normalized)
J
DS(on)
°
V=
I =
GS
D
10V
5.2A
www.vishay.com Document Number: 91174
4S09-0518-Rev. B, 13-Apr-09
IRFIB5N65A, SiHFIB5N65A
Vishay Siliconix
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
0
400
800
1200
1600
2000
1 10 100 1000
C, Capacitance (pF)
DS
V , Drain-to-Source Voltage (V)
A
V = 0V, f = 1MHz
C = C + C , C SHORTED
C = C
C = C + C
GS
iss gs gd ds
rss gd
oss ds gd
iss
oss
rss
010 20 30 40 50
0
4
8
12
16
20
Q , Total Gate Charge (nC)
V , Gate-to-Source Voltage (V)
G
GS
FOR TEST CIRCUIT
SEE FIGURE
I =
D
13
5.2A
V= 130V
DS
V= 325V
DS
V= 520V
DS
0.1
1
10
100
0.2 0.4 0.6 0.81.0 1.2
V ,Source-to-Drain Voltage (V)
I , Reverse Drain Current (A)
SD
SD
V = 0 V
GS
T = 25 C
J°
T = 150 C
J°
0.1
1
10
100
10 100 1000 10000
OPERATION IN THIS AREA LIMITED
BY RDS(on)
Single Pulse
T
T
= 150 C
= 25 C
°
°
J
C
V , Drain-to-Source Voltage (V)
I , Drain Current (A)I , Drain Current (A)
DS
D
10us
100us
1ms
10ms
Document Number: 91174 www.vishay.com
S09-0518-Rev. B, 13-Apr-09 5
IRFIB5N65A, SiHFIB5N65A
Vishay Siliconix
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10a - Switching Time Test Circuit
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms
25 50 75 100 125 150
0.0
1.0
2.0
3.0
4.0
5.0
6.0
T , Case Temperature ( C)
I , Drain Current (A)
°
C
D
V
DS
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
R
D
V
GS
R
G
D.U.T.
10 V
+
-
VDD
V
DS
90 %
10 %
V
GS
td(on) trtd(off) tf
0.01
0.1
1
10
0.00001 0.0001 0.001 0.01 0.1 1 10
Notes:
1. Duty factor D = t / t
2. Peak T = P x Z + T
1 2
JDM thJC C
P
t
t
DM
1
2
t , Rectangular Pulse Duration (s)
Thermal Response (Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
A
R G
IAS
0.01 Ω
tp
D.U.T.
L
VDS
+
-VDD
Driver
A
15 V
20 V
t
p
V
DS
I
AS
www.vishay.com Document Number: 91174
6S09-0518-Rev. B, 13-Apr-09
IRFIB5N65A, SiHFIB5N65A
Vishay Siliconix
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Fig. 12d - Typical Drain-to Source Voltage vs. Avalanche
Current
Fig. 13a - Basic Gate Charge Waveform
Fig. 13b - Gate Charge Test Circuit
25 50 75 100 125 150
0
200
400
600
800
Starting T , Junction Temperature ( C)
E , Single Pulse Avalanche Energy (mJ)
J
AS
°
ID
TOP
BOTTOM
2.3A
3.3A
5.2A
700
720
740
760
780
800
0123456
A
DSav
av
I , Avalanche Current (A)
V , Avalanche Voltage (V)
QG
QGS QGD
VG
Charge
10 V
D.U.T.
3 mA
VGS
VDS
IGID
0.3 µF
0.2 µF
50 kΩ
12 V
Current regulator
Current sampling resistors
Same type as D.U.T.
+
-
Document Number: 91174 www.vishay.com
S09-0518-Rev. B, 13-Apr-09 7
IRFIB5N65A, SiHFIB5N65A
Vishay Siliconix
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.c om/ppg?91174.
P.W.Period
dI/dt
Diode recovery
dV/dt
Ripple ≤5 %
Body diode forward drop
Re-applied
voltage
Reverse
recovery
current
Body diode forward
current
V
GS
= 10 V*
V
DD
I
SD
Driver gate drive
D.U.T. I
SD
waveform
D.U.T. V
DS
waveform
Inductor crurent
D = P.W.
Period
+
-
+
+
+
-
-
-
* VGS = 5 V for logic level devices
Peak Diode Recovery dV/dt Test Circuit
RG
VDD
• dV/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by duty factor "D"
• D.U.T. - device under test
D.U.T. Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
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Revision: 08-Feb-17 1Document Number: 91000
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