56F8300
16-bit Hybrid Controllers
freescale.com
56F8367
Evaluation Modul e User Manual
MC56F8367EVMUM
Rev. 1
10/2004
56F80x User’s Manual
Document Revision History
Version History Description of Change
Rev 1.0 Initial Public Release
TABLE OF CONTENTS
Table of Contents
Freescale Semiconductor i
Preliminary
Preface vii
Chapter 1
Introduction
1.1 MC56F8367EVM Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2 MC56F8367EVM Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.3 MC56F8367EVM Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Chapter 2
Technical Summary
2.1 MC56F8367 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.2 Program and Data Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.2.1 SRAM Bank 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.2.2 SRAM Bank 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.3 RS-232 Serial Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.4 Clock Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.5 Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.5.1 EXTBOOT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.5.2 EMI_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.5.3 CLKMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.6 Debug LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.7 Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.7.1 JTAG Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.7.2 Parallel JTAG Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.8 External Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.9 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.10 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.11 Daughter Card Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.11.1 Peripheral Daughter Card Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.11.2 Memory Daughter Card Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.12 Motor Control PWM Signals and LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
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Preliminary
2.13 CAN Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2.13.1 FlexCAN #1 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2.13.2 FlexCAN #2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
2.14 Software Feature Jumpers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2.15 Peripheral Expansion Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
2.15.1 Address Bus Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
2.15.2 Data Bus Expansion Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
2.15.3 External Memory Control Signal Expansion Connector. . . . . . . . . . . . . . . . . . . . . 2-29
2.15.4 Encoder #0 / Quad Timer Channel A Expansion Connector. . . . . . . . . . . . . . . . . . 2-29
2.15.5 Encoder #1 / SPI #1 Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
2.15.6 Timer Channel C Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
2.15.7 Timer Channel D Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
2.15.8 A/D Port A Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
2.15.9 A/D Port B Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
2.15.10 Serial Communications Port #0 Expansion Connector . . . . . . . . . . . . . . . . . . . . . . 2-33
2.15.11 Serial Communications Port #1 Expansion Connector . . . . . . . . . . . . . . . . . . . . . . 2-33
2.15.12 Serial Peripheral Interface #0 Expansion Connector. . . . . . . . . . . . . . . . . . . . . . . . 2-34
2.15.13 FlexCAN #1 Expansion Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
2.15.14 FlexCAN #2 Expansion Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
2.15.15 PWM Port A Expansion Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
2.15.16 PWM Port B Expansion Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36
2.16 Test Points. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36
Appendix A
MC56F8367EVM Schematics
Appendix B
MC56F8367EVM Bill of Material
LIST OF FIGURES
List of Figures
Freescale Semiconductor iii
Preliminary
1-1 Block Diagram of the MC56F8367EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1-2 MC56F8367 Default Jumper Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1-3 Connecting the MC56F8367EVM Cables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
2-1 Schematic Diagram of the External CS0 Memory Interface. . . . . . . . . . . . . . . . . . . 2-5
2-2 Schematic Diagram of the External CS1 / CS4 Memory Interface. . . . . . . . . . . . . . 2-6
2-3 Schematic Diagram of the RS-232 Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2-4 Schematic Diagram of the Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2-5 Schematic Diagram of the Debug LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2-6 Block Diagram of the Parallel JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2-7 Schematic Diagram of the User Interrupt Interface. . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2-8 Schematic Diagram of the Reset Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2-9 Schematic Diagram of the Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2-10 PWM Group A Interface and LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2-11 CAN #1 Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2-12 CAN #2 Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2-13 Software Feature Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2-14 Typical Analog Input RC Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
MC56F8 367 EVM User Manu al, Rev. 1
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Preliminary
LIST OF TABLES
List of Tables
Freescale Semiconductor v
Preliminary
1-1 MC56F8367EVM Default Jumper Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
2-1 SCI #0 Jumper Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2-2 RS-232 Serial Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2-3 EXTBOOT Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2-4 EMI Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2-5 EMI Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2-6 LED Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2-7 JTAG Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2-8 Parallel JTAG Interface Disable Jumper Selection . . . . . . . . . . . . . . . . . . . . . . 2-12
2-9 Parallel JTAG Interface Connector Description . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2-10 Parallel JTAG Interface Voltage Jumper Selection. . . . . . . . . . . . . . . . . . . . . . 2-14
2-11 Peripheral Daughter Card Connector Description . . . . . . . . . . . . . . . . . . . . . . . 2-17
2-12 Memory Daughter Card Connector Description . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2-13 CAN #1 Header Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
2-14 CAN #2 Header Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2-15 CAN #2 Pass-Through Jumper Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2-16 External Memory Address Bus Connector Description. . . . . . . . . . . . . . . . . . . 2-27
2-17 External Memory Address Bus Connector Description. . . . . . . . . . . . . . . . . . . 2-28
2-18 External Memory Control Signal Connector Description . . . . . . . . . . . . . . . . . 2-29
2-19 Timer A Signal Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
2-20 SPI #1 Signal Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
2-21 Timer Channel C Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
2-22 Timer Channel D Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
2-23 A/D Port A Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
2-24 A/D Port B Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
2-25 SCI #0 Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
MC56F8 367 EVM User Manu al, Rev. 1
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Preliminary
2-26 SCI #1 Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
2-27 SPI #0 Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
2-28 CAN #1 Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
2-29 CAN #2 Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
2-30 PWM Port A Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
2-31 PWM Port B Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36
Preface
Freescale Semiconductor vii
Preliminary
Preface
This reference manual describes in detail the hardware on the 56F8367 Evaluation Module.
Audience
This document is intended for application developers who are creating software for devices using
the Freescale 56F8367 part or a member of the 56F8300 family that is compatible with this part.
Examples would include the 56F8346 and the 56F8357 devices.
Organization
This manual is organized into two chapters and two appendices:
•Chapter 1, Introduction provides an overview of the EVM and its features.
•Chapter 2, Technical Summary describes in detail the 56F8367 hardware.
•Appendix A, "MC56F8367EVM Schematics"contains the schematics of the
MC56F8367EVM.
•Appendix B, "MC56F8367EVM Bill of Material" provides a list of the materials used on the
MC56F8367EVM board.
Suggested Reading
More documentation on the 56F8367 and the MC56F8367EVM kit may be found at URL:
www.freescale.com
MC56F8 367 EVM User Manu al, Rev. 1
viii Freescale Semicondu ctor
Preliminary
Notation Conventions
This manual uses the following notational conventions:
Definitions, Acronyms, and Abbreviations
Definitions, acronyms and abbreviations for terms used in this document are defined below for
reference.
Term or Value Symbol Examples Exceptions
Active High Signals
(Logic One) No special symbol
attached to the signal
name
A0
CLKO
Active Low Signals
(Logic Zero) Noted with an
overbar in text and in
most figures
WE
OE In schematic drawings,
Active Low Signals may be
noted by a backslash: /WE
Hexadec imal Values Begin with a “$” sym-
bol $0FF0
$80
Decimal Values No special symbol
attached to the
number
10
34
Bin ary Valu es Begi n with the l etter “ b”
attached to the number b1010
b0011
Numbers Consider ed pos it iv e
unless specifically
noted as a negative
value
5
-10 Voltage is often shown as
positive: +3.3V
Blue Text Linkable on-line ...refer to Chapter 7, License
Bold Reference sources,
paths, emphasis ...see:
http://www.freescale.com/
A/D Analog-to-Digital; a method of converting Analog signals to Digital values
ADC Analog-to-Digital Converter; a peripheral on the 56F8367 part
CAN Controller Area Network; serial communications peripheral and method
CiA CAN in Automation; an international CAN user’s group that coordinates
standards for CAN communications protocols
D/A Digital-to-Analog; a method of converting Digital values to an Analog form
DSP Digital Signal Processor or Digital Signal Processing
Preface
Freescale Semiconductor ix
Preliminary
56F8367 Hybrid controller with motor control peripherals
EOnCE Enhanced On-Chip Emulation; a debug bus and port was created to enable a
designer to create a low-cost hardware interface for a professional-quality
debug environment
EVM Evaluation Module; a hardware platform which allows a customer to evaluate
the silicon and develop his application
FlexCAN Flexable CAN Interface Module; a peripheral on the 56F8367 part
GPIO General Purpose Input and Output port on Freescale’s family of hybrid
controllers; does not share pin functionality with any other peripheral on the
chip and can only be set as an input, output or level-sensitive interrupt input
IC Integrated Circuit
JTAG Joint Test Action Group; a bus protocol/interface used for test and debug
LED Light Emitting Diode
LQFP Low-profile Quad Flat Package
MPIO Multi-Purpose Input and Output port on Freescale’s family of hybrid
controllers; shares package pins with other peripherals on the chip and can
function as a GPIO
OnCETM On-Chip Emulation, a debug bus and port created to allow a means for low-cost
hardware to provide a professional-quality debug environment
PCB Printed Circuit Board
PLL Phase Locked Loop
PWM Pulse Width Modulation
QuadDec Quadrature Decoder; a peripheral on the 56F8367 part
RAM Random Access Memory
R/C Resistor/Capacitor Network
ROM Read-Only Memory
SCI Serial Communications Interface; a peripheral on Freescale’s family of hybrid
controllers
SPI Serial Peripheral Interface; a peripheral on Freescale’s family of hybrid
controllers
SRAM Static Random Access Memory
WS Wait State
MC56F8 367 EVM User Manu al, Rev. 1
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Preliminary
References
The following sources were referenced to produce this manual:
[1] DSP56800E Reference Manual, DSP56800ERM, Freescale Semiconductor, Inc.
[2] 56F8300 Peripheral User Manual, MC56F8300UM, Freescale Semiconductor, Inc.
[3] 56F8367 Technical Data, MC56F8367, Freescale Semiconductor, Inc .
[4] CiA Draft Recommendation DR-303-1, Cabling and Connector Pin Assignment,
Version 1.0, CAN in Automation
[5] CAN Specification 2.0B, BOSCH or CAN in Automation
Introduction, Rev. 1
Freescale Semiconductor 1-1
Preliminary
Chapter 1
Introduction
The MC56F8367EVM is used to demonstrate the abilities of the 56F8367 hybrid controller and
to provide a hardware tool allowing the development of applications.
The MC56F8367EVM is an evaluation module board that includes a 56F8367 part, peripheral
expansion connectors, a CAN interface, 512KB of external memory and a pair of daughter card
connectors. The daughter card connectors are for signal monitoring and user feature
expandability.
The MC56F8367EVM is designed for the following purposes:
• Allowing new users to become familiar with the features of the 56800E architecture. The
tools and examples provided with the MC56F8367EVM facilitate evaluation of the
feature set and the benefits of the family.
• Serving as a platform for real-time software development. The tool suite enables the user
to develop and simulate routines, download the software to on-chip or on-board RAM, run
it, and debug it using a debugger via the JTAG/Enhanced OnCE (EOnCE) port. The
breakpoint features of the EOnCE port enable the user to easily specify complex break
conditions and to execute user-developed software at full speed until the break conditions
are satisfied. The ability to examine and modify all user-accessible registers, memory and
peripherals through the EOnCE port greatly facilitates the task of the developer.
• Serving as a platform for hardware development. The hardware platform enables the user
to connect external hardware peripherals. The on-board peripherals can be disabled,
providing the user with the ability to reassign any and all of the processor's peripherals.
The EOnCE port's unobtrusive design means that all memory on the board and on the
processor is available to the user.
MC56F8 367 EVM User Manu al, Rev. 1
1-2 Freescale Semiconductor
Preliminary
1.1 MC56F8367EVM Architecture
The MC56F8367EVM facilitates the evaluation of various features present in the 56F8367 part.
The MC56F8367EVM can be used to develop real-time software and hardware products. The
MC56F8367EVM provides the features necessary for a user to write and debug software,
demonstrate the functionality of that software and interface with the user's application-specific
device(s). The MC56F8367EVM is flexible enough to allow a user to fully exploit the 56F8367's
features to optimize the performance of his product, as shown in Figure 1-1.
Figure 1-1. Block Diagram of the MC56F8367EVM
MC56F8367
RESET
MODE/IRQ
Address,
Data &
Control
JTAG/EOnCE
XTAL/
EXTAL
SPI #0
SCI #0
Timer C
PWMA
+3.3V & GND
+3.3V A & AGND
+3.3VREF
Peripheral
Expansion
Connectors
Mode/IRQ Logic
Program Memory
128K x 16-bit
SRAM
Memory
Expansion
Connector
JTAG
Connector
Parallel
JTAG
Interface
8.00MHz
Crystal
DSub
25-Pin
Data Memory
128K x 16-bit
SRAM
DSub
9-Pin
PWM LEDs
RS-232
Interface
Power Supply
+3.3V, +3.3V A, +5V
& +3.3VREF
SCI #1
Reset Logic
Memory
Daughter Card
Connector
CAN #2 Interface
Debug LEDs
CAN #2 Bus
Header
CAN #2 Bus
DaisyChain
Peripheral
Daughter Card
Connector
Timer D
ADCA
QuadDec #0
PWMB
ADCB
QuadDec #1
FlexCAN #2
CAN #1 Interface CAN #1 Bus
Header
CAN #1 Bus
DaisyChain
FlexCAN #1
MC56F8367EVM Configura tion Jumpers
Introduction, Rev. 1
Freescale Semiconductor 1-3
Preliminary
1.2 MC56F8367EVM Configuration Jumpers
Ninteen jumper groups, (JG1-JG19), shown in Figure 1-2, are used to configure various features
on the MC56F8367EVM board. Table 1-1 describes the default jumper group settings.
Figure 1-2. MC56F8367 Default Jumper Options
MC56F8357EVM
U4
J3
JTAG
P2
S/N
LED3
P1
Y1
U1
U2
S2 S1
S3 P3
PC0
JG2
JG6
U8
RESET IRQB
IRQA
1
2
JG9
JG18
JG3
JG1
JG15
JG10
JG9
1
JG15
3
JG10
PC1
PC2
PC3
PD6
PD7
PWMA0
PWMA1
PWMA2
PWMA3
PWMA4
PWMA5
U3
U9
JG19
JG13
JG8
J20
J21
JG16
J10
J9
J2
J1
J7 J8 J6 J12 J14
J16
J11 J13 J15 J19 J14
1
JG19 3
1
JG16
3
3
4
1
JG1
3
JG2 JG3
JG18
1
2
JG14
3
4
JG5 JG7
JG11
JG12
JG6 JG4
1
2
JG8
3
4
JG17
JG13
J22
J23
J18
J17
JG12
JG11
J5
JG4 JG5 J24 JG7
J4
JG17
MC56F8 367 EVM User Manu al, Rev. 1
1-4 Freescale Semiconductor
Preliminary
Table 1-1. MC56F8367EVM Default Jumper Options
Jumper
Group Comment Jumpers
Connections
JG1 Use on-bo ard EXTAL crystal input for oscillator 1–2
JG2 Use on-board XTAL crystal input for oscillator 1–2
JG3 Enable on-board Parallel JTAG Host/Target Interface NC
JG4 Enable Internal Boot Mode 1–2
JG5 Enable A0 - A23 for external memory accesses NC
JG6 Enable Crystal Mode 1–2
JG7 Enable SRAM Memory Bank 0 (use CS0) 1–2
JG8 Enable SRAM Memory Bank 1 (use CS1 & CS4) 1–2 & 3–4
JG9 Pass RXD0 & TXD0 to RS-232 level converter 1–2 & 3–4
JG10 Enable RS-232 output NC
JG11 Pass RS-232 RST to CTS 1–2
JG12 Pass Temperature Diode to ANA7 1–2
JG13 CAN #1 termination selected 1–2
JG14 Pass CAN2_TX & CAN2_RX to CAN tranceiver 1–2 & 3–4
JG15 High selected on User Jumper #0 1–2
JG16 High selected on User Jumper #1 1–2
JG17 CAN2 termination selected 1–2
JG18 Analog Ground to Digital Ground not reconnected NC
JG19 Use +3.3V for Printer Interface to on-board Parallel JTAG Host/Target 1-2
MC56F8367EVM Connect ions
Introduction, Rev. 1
Freescale Semiconductor 1-5
Preliminary
1.3 MC56F8367EVM Connections
An interconnection diagram is shown in Figure 1-3 for connecting the PC and the external
+12.0V DC/AC power supply to the MC56F8367EVM board.
Figure 1-3. Connecting the MC56F8367EVM Cables
Perform the following steps to connect the MC56F8367EVM cables:
1. Connect the parallel extension cable to the parallel port of the host computer.
2. Connect the other end of the parallel extension cable to P1, shown in Figure 1-3, on the
MC56F8367EVM board. This provides the connection which allows the host computer to
control the board.
3. Make sure that the external +12V DC, 1.2A power supply is not plugged into a +120V AC
power source.
4. Connect the 2.1mm output power plug from the external power supply into P3, shown in
Figure 1-3, on the MC56F8367EVM board.
5. Apply power to the external power supply. The green Power-On LED, LED13, will
illuminate when power is correctly applied.
PC-compatible
cable
computer
Parall el extension
MC56F8367EVM
External
+12V
power
P1
P3
Connect cable
to parallel / printer port
with 2.1mm,
receptacle
connector
MC56F8 367 EVM User Manu al, Rev. 1
1-6 Freescale Semiconductor
Preliminary
Technical Summary, Rev. 1
Freescale Semiconductor 2-1
Preliminary
Chapter 2
Technical Summary
The MC56F8367EVM is designed as a versatile development card using the 56F8367 processor,
allowing the creation of real-time software and hardware products to support a new generation of
applications in servo and motor control, digital and wireless messaging, digital answering
machines, feature phones, modems, and digital cameras. The power of the 16-bit 56F8367
processor, combined with the on-board 128K x 16-bit external Program/Data Static RAM
(SRAM), 128K x 16-bit external Data/Program SRAM, RS-232 interface, CAN interface,
daughter card interface, peripheral expansion connectors and parallel JTAG interface, makes the
MC56F8367EVM ideal for developing and implementing many motor controlling algorithms, as
well as for learning the architecture and instruction set of the 56F8367 processor.
The main features of the MC56F8367EVM, with board and schematic reference designators,
include:
• MC56F8367VPY60, a 16-bit +3.3V/+2.5V hybrid controller operating at 60MHz [U1]
• External Fast Static RAM (FSRAM) memory, configured as:
— 128K x 16-bit of memory [U2] with 0 wait state at 60MHz via CS0
— 128K x 16-bit of memory [U3] with 0 wait state at 60MHz via CS1/CS4
• 8.00MHz crystal oscillator, for base processor frequency generation [Y1]
• Optional external oscillator frequency input connectors [JG1 and JG2]
• Joint Test Action Group (JTAG) port interface connector, for an external debug Host
Target Interface [J3]
• On-board parallel JTAG host target interface, with a connector for a PC printer port cable
[P1], including a disable jumper [JG3] and a printer port voltage selection jumper [JG19]
• RS-232 interface, for easy connection to a host processor [U4 and P2], including a disable
jumper [JG10]
• RTS and CTS RS-232 control signal access [JG11]
• CAN interface, for high speed, 1.0Mbps, FlexCAN communications [U10 and J20]
MC56F8 367 EVM User Manu al, Rev. 1
2-2 Freescale Semiconductor
Preliminary
• CAN bypass and bus termination [J21 and JG13]
• CAN #2 interface, for high speed, 1.0Mbps, FlexCAN communications [U11 and J22]
• CAN #2 bypass and bus termination [J23 and JG17]
• CAN #2 interface signal isolation [JG14]
• Peripheral Daughter Card connector, to allow the user to connect his own SCI, SPI or
GPIO-compatible peripheral to the hybrid controller [J1]
• Memory Daughter Card connector, to allow the user to connect his own memory or
memory device to the device [J2]
• SCI #0 expansion connector, to allow the user to connect his own SCI #0 /
MPIO-compatible peripheral [J13]
• SCI #1 expansion connector, to allow the user to connect his own SCI #1 /
MPIO-compatible peripheral [J14]
• SPI #0 expansion connector, to allow the user to connect his own SPI #0 /
MPIO-compatible peripheral [J11]
• SPI #1 expansion connector, to allow the user to connect his own SPI #1 /
MPIO-compatible peripheral [J12]
• PWMA expansion connector, to allow the user to connect his own PWMA-compatible
peripheral [J7]
• PWMB expansion connector, to allow the user to connect his own PWMB-compatible
peripheral [J8]
• CAN #1 expansion connector, to allow the user to connect his own CAN physical layer
peripheral [J18]
• CAN #2 expansion connector, to allow the user to connect his own CAN physical layer
peripheral [J19]
• Timer A expansion connector, to allow the user to connect his own Timer A / Encoder
#0-compatible peripheral [J15]
• Timer C expansion connector, to allow the user to connect his own Timer C-compatible
peripheral [J16]
• Timer D expansion connector, to allow the user to connect his own Timer D-compatible
peripheral [J17]
• ADC A expansion connector, to allow the user to attach his own A/D Port A-compatible
peripheral [J9]
Technical Summary, Rev. 1
Freescale Semiconductor 2-3
Preliminary
• ADC B expansion connector, to allow the user to attach his own A/D Port B-compatible
peripheral [J10]
• Address bus expansion connector, to allow the user to monitor the external address bus
[J4]
• Data bus expansion connector, to allow the user to monitor the external data bus [J5]
• External memory bus control signal connector, to allow the user to monitor the external
memory bus [J6]
• On-board power regulation provided from an external +12V DC-supplied power input
[P3]
• Light Emitting Diode (LED) power indicator [LED13]
• Six on-board real-time user debugging LEDs [LED1 - 6]
• Six on-board Port A PWM monitoring LEDs [LED7 - 12]
• Internal/external (EXTBOOT) boot mode selector [JG4]
• Address range (EMI_MODE) boot mode selector [JG5]
• Clock mode (CLKMODE) boot selector [JG6]
• Temperature sense diode to ANA7 selector [JG12]
• Manual reset push button [S1]
• Manual interrupt push button for IRQA [S2]
• Manual interrupt push button for IRQB [S3]
• General-purpose jumper on GPIO PE4 [JG15]
• General-purpose jumper on GPIO PE7 [JG16]
MC56F8 367 EVM User Manu al, Rev. 1
2-4 Freescale Semiconductor
Preliminary
2.1 MC56F8367
The MC56F8367EVM uses a Freescale MC56F8357VPY60 part, designated as U1 on the board
and in the schematics. This part will operate at a maximum external bus speed of 60MHz. A full
description of the 56F8367, including functionality and user information, is provided in these
documents:
• 56F8367 Technical Data Sheet, (56F8367): Electrical and timing specifications, pin
descriptions, device-specific peripheral information and package descriptions (this
document)
•56F8300 Peripheral User Manual, (MC56F8300UM): Detailed description of peripherals
of the 56F8300 family of devices
•DSP56800E Reference Manual, (DSP56800ERM): Detailed description of the 56800E
family architecture, 16-bit core processor, and the instruction set
Refer to these documents for detailed information about chip functionality and operation. They
can be found on this URL:
www.freescale.com
2.2 Program and Data Memory
The MC56F8367EVM contains two 128K x 16-bit Fast Static RAM banks. SRAM bank 0 is
controlled by CS0 and SRAM bank 1 is controlled by CS1 and CS4. This provides a total of
256K x 16 bits of external memory.
Program and Data Memory
Technical Summary, Rev. 1
Freescale Semiconductor 2-5
Preliminary
2.2.1 SRAM Bank 0
SRAM bank 0, which is controlled by CS0, uses a 128K x 16-bit Fast Static RAM (GSI
GS72116, labeled U2) for external memory expansion; see the FSRAM schematic diagram in
Figure 2-1. CS0 can be configured to use this memory bank as 16 bits of Program memory, Data
memory, or both. Additionally, CS0 can be configured to assign this memory’s size and starting
address to any modulo address space.
This memory bank will operate with zero wait state access while the MC56F8357 is running at
60MHz and can be disabled by removing the jumper at JG7.
Figure 2-1. Schematic Diagram of the External CS0 Memory Interface
MC56F8367 GS72116
A0 - A16
D0 - D15
RD
WR
A0 - A16
DQ0 - DQ15
OE
WE
CE
1
2
JG7
+3.3V
Jumper Pi n 1-2 :
Enable SRAM
PS / CS0
Jumper Removed:
Disable SRAM
MC56F8 367 EVM User Manu al, Rev. 1
2-6 Freescale Semiconductor
Preliminary
2.2.2 SRAM Bank 1
SRAM bank 1, which is controlled by CS1 and CS2, uses a 128K x 16-bit Fast Static RAM (GSI
GS72116, labeled U3) for external memory expansion; see the FSRAM schematic diagram in
Figure 2-2. Using CS1 and CS4, this memory bank can be configured as byte (8-bit) or word
(16-bit) accessable Program memory, Data memory, or both. Additionally, CS1 and CS4 can be
configured to assign this memory’s size and starting address to any modulo address space.
This memory bank will operate with zero wait state access while the 56F8367 is running at
60MHz and can be disabled by removing the jumpers at JG8.
Figure 2-2. Schematic Diagram of the External CS1 / CS4 Memory Interface
MC56F8367 GS72116
A0 - A16
D0 - D15
RD
WR
A0 - A16
DQ0 - DQ15
OE
WE
CE
JG8
Jumper Pin 1-2:
Enable SRAM Low Byte
DS / CS 1
PD2 / CS4 LB
HB
Jumper Pin 3-4:
Enable SRAM High Byte
1
3
2
4
RS-232 Serial Communications
Technical Summary, Rev. 1
Freescale Semiconductor 2-7
Preliminary
2.3 RS-232 Serial Communications
The MC56F8367EVM provides an RS-232 interface by the use of an RS-232 level converter,
Maxim MAX3245EEAI, designated as U4. Refer to the RS-232 schematic diagram in
Figure 2-3. The RS-232 level converter transitions the SCI port’s +3.3V signal levels to
RS-232-compatible signal levels and connects to the host’s serial port via connector P2.
RTS/CTS flow control is provided on JG11 as a jumper, but could be implemented using
uncommitted GPIO signals. The SCI port #0 signals can be isolated from the RS-232 level
converter by removing the jumpers in JG9; see Table 2-1. The pin-out of connector P2 is listed in
Table 2-2. The RS-232 level converter/transceiver can be disabled by placing a jumper at JG10.
Figure 2-3. Schematic Diagram of the RS-232 Interface
.Table 2-1. SCI #0 Jumper Options
JG9
Pin # Signal Pin # Signal
1 TXD0 2 RS-232 TXD
3 RXD0 4 RS-232 RXD
MC56F8367 RS-232
Lev el Converte r
Interface
TXD0
RXD0 R1 in
T1 out
T1 in
R1 out
FORCEOFF
JG10
6
3
2
7
8
4
5
x
1
9
+3.3V
Jumper Removed:
Enable RS-232
P2
JG9
12
34
1
2
Jumper Pin 1-2:
Disable RS-232
R2 in
T2 out
JG11
1
2T2 in
R2 out
RTS
CTS
TXD
RXD
MC56F8 367 EVM User Manu al, Rev. 1
2-8 Freescale Semiconductor
Preliminary
.
2.4 Clock Source
The MC56F8367EVM uses an 8.00MHz crystal, Y1, connected to its external crystal inputs,
EXTAL and XTAL. To achieve its maximum internal operating frequency, the 56F8367 uses its
internal PLL to multiply the input frequency. An external oscillator source can be connected to
the processor by using the oscillator bypass connectors, JG1 and JG2; see Figure 2-4. If the input
frequency is above 8MHz, then the EXTAL input should be jumpered to ground by adding a
jumper between JG1 pins 2 and 3. The input frequency would then be injected on JG2’s pin 2. If
the input frequency is below 4MHz, then the input frequency can be injected on JG1’s pin 2.
Figure 2-4. Schematic Diagram of the Clock Interface
Table 2-2. RS-232 Serial Connector Description
P2
Pin # Signal Pin # Signal
1 Jumper to 6 & 4 6 Jumper to 1 & 4
2TXD7CTS
3RXD8RTS
4 Jumper to 1 & 6 9 NC
5GND
MC56F8367
External
Oscillator
Headers
JG1
1
2
3
1
2
EXTAL
XTAL
JG2
8.00MHz
Operating Mode
Technical Summary, Rev. 1
Freescale Semiconductor 2-9
Preliminary
2.5 Operating Mode
The MC56F8367EVM provides three boot mode selection jumpers, EXTBOOT, EMI_MODE
and CLKMODE, to provide boot-up mode options.
2.5.1 EXTBOOT
The MC56F8367EVM provides an external/internal boot mode jumper, JG4. This jumper is used
to select the internal or external memory operation of the processor as it exits reset. Refer to the
56F8300 Peripheral User Manual and the 56F8367 Technical Data Sheet for a complete
description of the chip’s operating modes. Table 2-3 shows the two external boot operation
modes available on the 56F8367.
2.5.2 EMI_MODE
The MC56F8367EVM provides an EMI boot mode jumper, JG5. This jumper is used to select
the external memory addressing range operating mode of the processor as it exits reset. The user
can select between a 64K address space or an 8M address space. Refer to the 56F8300
Peripheral User Manual and the 56F8367 Technical Data Sheet for a complete description of
the chip’s operating modes. Table 2-4 shows the two EMI operation modes available on the
56F8367.
Table 2-3. EXTBOOT Operating Mode Selection
Operating Mode JG4 Comment
0 1 - 2 Bootstrap from internal memory (GND)
3 No Jumper Bootstrap from external memory (+3.3V)
Table 2-4. EMI Operating Mode Selection
Operating Mode JG5 Comment
V1 1 - 2 A0 - A15 (64K) available for external memory bus (GND)
V2 No Jumper A0 - A23 (8M) available for external memory bus (+3.3V)
MC56F8 367 EVM User Manu al, Rev. 1
2-10 Freescale Semiconductor
Preliminary
2.5.3 CLKMODE
The MC56F8367EVM provides a clock boot mode jumper, JG6. This jumper is used to select the
type of clock source being provided to the processor as it exits reset. The user can select between
the use of a crystal or an oscillator as the clock source for the processor. Refer to the 56F8300
Peripheral User Manual and the 56F8367 Technical Data Sheet for a complete description of
the chip’s operating modes. Table 2-5 shows the two CLKMODE operation modes available on
the 56F8367.
2.6 Debug LEDs
Six on-board Light Emitting Diodes, (LEDs), are provided to allow real-time debugging for user
programs. These LEDs will allow the programmer to monitor program execution without having
to stop the program during debugging; refer to Figure 2-5. Table 2-6 describes the control of
each LED.
Setting PC0, PC1, PC2, PC3, PD6, or PD7 to a Logic One value will turn on the associated LED.
Table 2-5. EMI Operating Mode Selection
Operating Mode JG6 Comment
Crystal 1 - 2 Enables the external clock drive logic so an external
crystal can be used as the input clock source. (GND)
Oscillator No Jumper Disables the external clock drive logic. Use oscillator
input on XTAL and Ground on EXTAL. (3.3V)
Table 2-6. LED Control
Controlled by
User LED Color Signal
LED1 RED Port C Bit 0 (PC0)
LED2 YELLOW Port C Bit 1 (PC1)
LED3 GREEN Port C Bit 2 (PC2)
LED4 RED Port C Bit 3 (PC3)
LED5 YELLOW Port D Bit 6 (PD6)
LED6 GREEN Port D Bit 7 (PD7)
Debug Support
Technical Summary, Rev. 1
Freescale Semiconductor 2-11
Preliminary
Figure 2-5. Schematic Diagram of the Debug LED Interface
2.7 Debug Support
The MC56F8367EVM provides an on-board parallel JTAG host target interface and a JTAG
interface connector for external target interface support. Two interface connectors are provided to
support each of these debugging approaches. These two connectors are designated the JTAG
connector and the host parallel interface connector.
MC56F8367 INV E RT ING BU F FER
PC0
PC1
PC2
GREEN LED
YELLOW LED
RED LED +3.3V
GREEN LED
YELLOW LED
RED LED
PC3
PD6
PD7
MC56F8 367 EVM User Manu al, Rev. 1
2-12 Freescale Semiconductor
Preliminary
2.7.1 JTAG Connector
The JTAG connector on the MC56F8367EVM allows the connection of an external host target
interface for downloading programs and working with the 56F8367’s registers. This connector is
used to communicate with an external host target interface, which passes information and data
back and forth with a host processor running a debugger program. Table 2-7 shows the pin-out
for this connector.
When this connector is used with an external host target interface, the parallel JTAG interface
should be disabled by placing a jumper in jumper block JG3. Reference Table 2-8 for this
jumper’s selection options.
Table 2-7. JTAG Connector Description
J3
Pin # Signal Pin # Signal
1 TDI 2 GND
3 TDO 4 GND
5 TCK 6 GND
7 NC 8 KEY
9 RESET 10 TMS
11 +3.3V 12 NC
13 DE 14 TRST
Table 2-8. Parallel JTAG Interface Disable Jumper Selection
JG3 Comment
No jumpers Enables On-board Parallel JTAG Inte rface
1 - 2 Disables on-board Parallel JTAG Interface
Debug Support
Technical Summary, Rev. 1
Freescale Semiconductor 2-13
Preliminary
2.7.2 Parallel JTAG Interface Connector
The Parallel JTAG Interface Connector, P1, allows the 56F8367 to communicate with a parallel
printer port on a Windows PC; reference Figure 2-6. Using this connector, the user can
download programs and work with the 56F8367’s registers. Table 2-9 shows the pin-out for this
connector. When using the parallel JTAG interface, the jumper at JG3 should be removed, as
shown in Table 2-8. The printer port interface voltage of +3.3V or +5.0V can be selected by a
jumper on JG19, as shown in Table 2-10.
Figure 2-6. Block Diagram of the Parallel JTAG Interface
DB-25 Connector Parallel JTAG Interface MC56F8367
TDI
TDO
P_TRST
TMS
TCK
P_RESET
OUT
OUT OUT
OUT
OUT
OUT
IN
IN IN
IN
IN
IN
EN
TDI
TDO
TRST
TMS
TCK
RESET
JG3
1
2
+3.3V
Jumper Removed:
Enable JTAG I/F
Jumper Pin 1-2:
Disable JTAG I/F
P_DE OUT
IN DE
JG19
1
2
3
Vcc
+3.3V
+5.0V
MC56F8 367 EVM User Manu al, Rev. 1
2-14 Freescale Semiconductor
Preliminary
Table 2-9. Parallel JTAG Interface Connector Description
P1
Pin # Signal Pin # Signal
1NC14NC
2 PORT_RESET 15 PORT_IDENT
3PORT_TMS16 NC
4 PORT_TCK 17 NC
5 PORT_TDI 18 GND
6PORT_
TRST 19 GND
7PORT_DE20 GND
8PORT_IDENT21 GND
9PORT_VCC22 GND
10 NC 23 GND
11 PORT_TDO 24 GND
12 NC 25 GND
13 PORT_CONNECT
Table 2-10. Parallel JTAG Interface Voltage Jumper Selection
JG19 Comment
1 - 2 Interface with the PC’s printer port using +3 .3V signals
2 - 3 Interface with the PC’s printer port using +5 .0V signals
Reset
Technical Summary, Rev. 1
Freescale Semiconductor 2-15
Preliminary
2.8 External Interrupts
Two on-board push button switches are provided for external interrupt generation, as shown in
Figure 2-7. S2 allows the user to generate a hardware interrupt for signal line IRQA. S3 allows
the user to generate a hardware interrupt for signal line IRQB. These two switches allow the user
to generate interrupts for his user-specific programs.
Figure 2-7. Schematic Diagram of the User Interrupt Interface
2.9 Reset
Logic is provided on the 56F8367 to generate an internal power-on reset. Additional reset logic is
provided to support the reset signals from the JTAG connector, the parallel JTAG interface and
the user reset push button, S1; refer to Figure 2-8.
Figure 2-8. Schematic Diagram of the Reset Interface
MC56F8367
IRQA
IRQB
+3.3V
+3.3V
10K
10K
S2
S3
0.1µF
0.1µF
RESET
PUSHBUTTON MANUAL RESET
JTAG_TAP_RESET
JTAG_RESET RESET
TRST
S1
MC56F8 367 EVM User Manu al, Rev. 1
2-16 Freescale Semiconductor
Preliminary
2.10 Power Supply
The main power input to the MC56F8367EVM, +12V DC at 1.2A, is through a 2.1mm coax
power jack. This input power is rectified to provide a DC supply input. This allows a user the
option to use a +12V AC power supply. A 1.2 Amp power supply is provided with the
MC56F8367EVM; however, less than 500mA is required by the EVM. The remaining current is
available for custom control applications when connected to the daughter card connectors. The
MC56F8367EVM provides +5.0V DC regulation for the CAN interface and additional
regulators. The MC56F8367EVM provides +3.3V DC voltage regulation for the processor,
memory, D/A, ADC, parallel JTAG interface and supporting logic; refer to Figure 2-9.
Additional voltage regulation logic provides a low-noise +3.3V DC voltage reference to the
processor’s A/D VREFH. A jumper, JG18, and resistor, R66, are provided to allow the analog and
digital grounds to be isolated on the MC56F8367EVM board. This allows the analog ground
reference point to be provided on a custom board attached to the MC56F8367EVM daughter card
connectors. By removing R66, the AGND reference is disconnected from the
MC56F8367EVM’s digital ground. By placing a jumper on JG18, the AGND is reconnected to
the MC56F8367EVM’s digital ground. Power applied to the MC56F8367EVM is indicated with
a power-on LED, referenced as LED13. Optionally, the user can provide the +2.5 DC voltage
needed by the processor’s core on connector J24 and disable the on-chip core voltage regulator
by moving the resistor at R72 to R71. Additonally, four zero ohm resistors or shorting wires must
be added at R67, R68, R69, and R70 to allow the external +2.5V DC to pass to the 56F8367.
Figure 2-9. Schematic Diagram of the Power Supply
+5.0V DC
+12V DC/AC Power
Condition CAN
56F8367
VDD_IO & PLL
+3.3V
Regulator
P3
MC56F8367EVM
Parts
56F8367
VREFH
+3.3V DC
+3.3VA DC
+5.0V
Regulator
56F8367
ADC
+3.3V
Regulator +3.3VA DC
56F8367
VDD Core
+2.5V DC
Ext In 1
2
J24
U15
R67 - R70
Bridge
Rectifier
Input
+3.3V
Regulator
Power On
Daughter Card Connectors
Technical Summary, Rev. 1
Freescale Semiconductor 2-17
Preliminary
2.11 Daughter Card Connectors
The EVM board contains two daughter card connectors. One connector, J1, contains the
processor’s peripheral port signals. The second connector, J2, contains the processor’s external
memory bus signals.
2.11.1 Peripheral Daughter Card Connector
The processor’s peripheral port signals are connected to the peripheral daughter card connector,
J1. The peripheral daughter card connector is used to connect a daughter card or a user-specific
daughter card to the processor’s peripheral port signals. The peripheral port daughter card
connector is a 100-pin high-density connector with signals for the IRQs, reset, SPI, SCI, PWM,
ADC and Quad Timer ports. Table 2-11 shows the peripheral daughter card connector’s
signal-to-pin assignments.
Table 2-11. Peripheral Daughter Card Connector Description
J1
Pin # Signal Pin # Signal
1 +12V 2 +12V
3 GND 4 GND
5 +5.0V 6 +5.0V
7 GND 8 GND
9 +3.3V 10 +3.3V
11 GND 12 GND
13 PHASEA0 / TA0 / PC4 14 PHASEB0 / TA1 / PC5
15 INDEX0 / TA2 / PC6 16 HOME0 / TA3 / PC7
17 GND 18 GND
19 PHASEA1 / PC0 / TB0 / SCLK1 20 PHASEB1 / PC1 / TB1 / MOSI1
21 INDEX1 / PC2 / TB2 / MISO1 22 HOME1 / PC3 / TB3 / SS1
23 TXD0 / PE0 24 TXD1 / PD6
25 TXD0 / PE0 26 TXD1 / PD6
27 RXD0 / PE1 28 RXD1 / PD7
MC56F8 367 EVM User Manu al, Rev. 1
2-18 Freescale Semiconductor
Preliminary
29 IRQA 30 IRQB
31 RXD0 / PE1 32 RXD1 / PD7
33 PWMB0 34 PWMB1
35 PWMB2 36 PWMB3
37 PWMB4 38 PWMB5
39 GND 40 GND
41 ISB0 / PD10 42 ISB1 / PD11
43 ISB2 / PD12 44 GND
45 FAULTB1 46 FAULTB0
47 FAULTB3 48 FAULTB2
49 GND 50 GND
51 PWMA0 52 PWMA1
53 PWMA2 54 PWMA3
55 PWMA4 56 PWMA5
57 GND 58 GND
59 FAULTA0 60 FAULTA1
61 FAULTA2 62 MISO0 / PE6
63 ISA0 / PC8 64 ISA1 / PC9
65 ISA2 / PC10 66 RSTO
67 MOSI0 / PE5 68 SS0 / PE7
69 TD0 / PE10 70 TD1 / PE11
71 SCLK0 / PE7 72 TC0 / PE8
73 CAN_TX 74 CAN_RX
75 MOSI0 / PE5 76 MISO0 / PE6
77 SCLK0 / PE4 78 SS0 / PE7
Table 2-11. Peripheral Daughter Card Connector Description (Continued)
J1
Pin # Signal Pin # Signal
Daughter Card Connectors
Technical Summary, Rev. 1
Freescale Semiconductor 2-19
Preliminary
2.11.2 Memory Daughter Card Connector
The processor’s external memory bus signals are connected to the memory daughter card
connector, J2. Table 2-12 shows the port signal-to-pin assignments.
79 GND 80 GND
81 +VREFH 82 +VREFH
83 GNDA 84 GNDA
85 AN0 86 AN1
87 AN2 88 AN3
89 AN4 90 AN5
91 AN6 92 AN7
93 AN8 94 AN9
95 AN10 96 AN11
97 AN12 98 AN13
99 AN14 100 AN15
Table 2-12. Memory Daughter Card Connector Description
J2
Pin # Signal Pin # Signal
1 A4 / PA12 2 A5 / PA13
3 A3 / PA11 4 A6 / PE2
5 A2 / PA10 6 A7 / PE3
7 A1 / PA9 8 RD
9GND10GND
11 A0 / PA8 12 DS / CS1
13 PS / CS0 14 PD0 / CS2 / CAN2_TX
Table 2-11. Peripheral Daughter Card Connector Description (Continued)
J1
Pin # Signal Pin # Signal
MC56F8 367 EVM User Manu al, Rev. 1
2-20 Freescale Semiconductor
Preliminary
15 D0 / PF9 16 D 15 / PF8
17 D1 / PF10 18 D14 / PF7
19 GND 20 GND
21 GND 22 GND
23 D2 / PF11 24 D13 / PF6
25 D3 / PF12 26 D12 / PF5
27 D4 / PF13 28 D11 / PF4
29 D5 / PF14 30 D10 / PF3
31 GND 32 GND
33 GND 34 GND
35 D6 / PF15 36 D9 / PF2
37 D7 / PF0 38 D8 / PF1
39 WR 40 PD1 / CS3 / CAN2_RX
41 A15 / PA7 42 A8 / PA0
43 GND 44 GND
45 A14 / PA6 46 A9 / PA1
47 A13 / PA5 48 A10 / PA2
49 A12 / PA4 50 A11 / PA3
51 PB0 / A16 52 GND
53 GND 54 GND
55 +3.3V 56 +3.3V
57 GND 58 GND
59 +5.0V 60 +5.0V
Table 2-12. Memory Daughter Card Connector Description (Continued)
J2
Pin # Signal Pin # Signal
Motor Control PWM Signals and LEDs
Technical Summary, Rev. 1
Freescale Semiconductor 2-21
Preliminary
2.12 Motor Control PWM Signals and LEDs
The 56F8367 has two independent groups of dedicated PWM units. Each unit contains six PWM,
three phase current sense inputs and four fault input lines. PWM group A’s PWM lines are
connected to a set of six PWM LEDs via inverting buffers. The buffers are used to isolate and
drive the Processor’s PWM group A’s outputs to the PWM LEDs. The PWM LEDs indicate the
status of PWM group A signals; refer to Figure 2-10. PWM Group A and B signals are routed
out to headers, J7 and J8 respectively, and to the peripheral daughter card connector for easy use
by the end user.
Figure 2-10. PWM Group A Interface and LEDs
LED
+3.3V
LED9
MC56F8367
LED10
LED11
LED12
LED7
LED8
PWMA0
PWMA1
PWMA2
PWMA3
PWMA5
Buffer
PWMA0
Yellow LED
PWMA1
PWMA2
PWMA3
PWMA4
PWMA5
Green LED
Yellow LED
Green LED
Yellow LED
Green LED
Phase A Top
Phase A Bottom
Phase B Top
Phase B Bottom
Phase C Top
Phase C Bottom
PWMA4
MC56F8 367 EVM User Manu al, Rev. 1
2-22 Freescale Semiconductor
Preliminary
2.13 CAN Interfaces
The MC56F8367EVM board contains two FlexCAN interfaces. The primary CAN interface uses
the CAN1_RX and CAN1_TX pins on the 56F8367. The secondary CAN interface uses the
CAN2_RX and CAN2_TX pins on the 56F8367.
2.13.1 FlexCAN #1 Interface
The MC56F8367EVM board contains a CAN physical-layer interface chip that is attached to the
FlexCAN port’s CAN1_RX and CAN1_TX pins on the 56F8367. The EVM board uses a Phillips
high-speed, 1.0Mbps, physical layer interface chip, PCA82C250. Due to the +5.0V operating
voltage of the CAN interface chip, a pull-up to +5.0V is required to level shift the transmit data
output line from the 56F8367. The CANH and CANL signals pass through inductors before
attaching to the CAN bus connectors. A primary, J20, and daisy-chain, J21, CAN connector are
provided to allow easy daisy-chaining of CAN devices. CAN bus termination of 120 ohms can be
provided by adding a jumper to JG13. Refer to Table 2-14 for the CAN connector signals and
Figure 2-12 for a connection diagram.
Figure 2-11. CAN #1 Interface
MC56F8367
+5.0V
CAN Trans ceiver
J20
Daisy-Chain CAN #1
Connector
J21
CAN #1 Bus
Connector
CAN Bus #1
Terminator
JG13
120
PCA82C250
1K
CAN1_TX
CAN1_RX
1
2
3
45
4
35
CANH
CANL
TXD
RXD
CAN Interfaces
Technical Summary, Rev. 1
Freescale Semiconductor 2-23
Preliminary
2.13.2 FlexCAN #2 Interface
The MC56F8367EVM board contains a second FlexCAN port, the CAN2_RX and CAN2_TX
pins on the 56F8367. These signals pass through an isolation jumper, JG14, before going to the
CAN physical layer interface. The EVM board uses a Phillips high-speed, 1.0Mbps, physical
layer interface chip, PCA82C250. Due to the +5.0V operating voltage of the CAN interface chip,
a pull up to +5.0V is required to level shift the transmit data output line from the 56F8367. The
CAN2H and CAN2L signals pass through inductors before attaching to the CAN bus connectors.
A primary, J22, and daisy-chain, J23, CAN connector are provided to allow easy daisy-chaining
of CAN devices. CAN bus termination of 120 ohms can be provided by adding a jumper to JG17.
Refer to Figure 2-12 for a connection diagram and to Table 2-14 and Table 2-15 for the CAN
connector signals.
Table 2-13. CAN #1 Header Des cription
J20 and J21
Pin # Signal Pin # Signal
1NC2NC
3 CANL 4 CANH
5GND6NC
7NC8NC
9NC10NC
MC56F8 367 EVM User Manu al, Rev. 1
2-24 Freescale Semiconductor
Preliminary
Figure 2-12. CAN #2 Interface
Table 2-14. CAN #2 Header Description
J22 and J23
Pin # Signal Pin # Signal
1NC2NC
3 CAN2L 4 CAN2H
5GND6NC
7NC8NC
9NC10NC
Table 2-15. CAN #2 Pass-Through Jumper Description
JG14
Pin # Signal Pin # Signal
1PD02CAN2_TX
3 PD1 4 CAN2_RX
MC56F8367
+5.0V
CAN Transceiver
J22
Daisy-Chain
CAN #2
Connector
J23
CAN #2 Bus
Connector
CAN #2 Bus
Terminator
JG17
120
PCA82C250
1K
PD0 / CAN2_TX
PD1 / CAN2_RX
1
2
3
45
4
35
CANH
CANL
TXD
RXD
1
34
2
JG14
Software Feature Jumpers
Technical Summary, Rev. 1
Freescale Semiconductor 2-25
Preliminary
2.14 Software Feature Jumpers
The MC56F8367EVM board contains two software feature jumpers that allow the user to select
user-defined software features. Two GPIO port pins, PE4 and PE7, are pulled high or low with
10K ohm resistors on JG15 and JG16. Attaching a jumper between pins 1 and 2 will place a high
or 1 on the port pin. Attaching a jumper between pins 2 and 3 will place a low or 0 on the port
pin; see Figure 2-13.
Figure 2-13. Software Feature Jumpers
MC56F8367 JG15 User Jumper
#0
SCLK0 / PE4
SS0 / PE7
1
23
10K +3.3V
JG16 User Jumper
#1
1
23
10K
10K
+3.3V
10K
MC56F8 367 EVM User Manu al, Rev. 1
2-26 Freescale Semiconductor
Preliminary
2.15 Peripheral Expansion Connectors
The EVM board contains a group of peripheral expansion connectors used to gain access to the
resources of the 56F8367. The following signal groups have expansion connectors:
• External Memory Address Bus (A0 - A23)
General Purpose Port A (bits 0 - 13)
General Purpose Port E (bits 2 & 3)
General Purpose Port B (bit 0 - 7)
• External Memory Data Bus (D0 - D15)
General Purpose Port F (bits 0 - 15)
• External Memory Control
General Purpose Port D (bits 0 - 5, 8 & 9)
• Quadrature Decoder #0
Quad Timer Channel A
• Quadrature Decoder #1
Serial Peripheral Interface Port #1
Quad Timer Channel B
General Purpose Port C (bits 0 - 3)
• Quad Timer Channel C
General Purpose Port E (bits 8 & 9)
• Quad Timer Channel D
General Purpose Port E (bits 10 - 13)
• A/D Input Port A
• A/D Input Port B
• Serial Communications Port #0 / General Purpose Port E (bits 0 and 1)
• Serial Communications Port #1 / General Purpose Port D (bits 6 and 7)
• Serial Peripheral Interface Port #0 / General Purpose Port E (bits 4 - 7)
• PWM Port A / General Purpose Port C (bits 8 - 10)
• PWM Port B / General Purpose Port C (bits 0 - 3)
• CAN Port #1
• CAN Port #2
Peripheral Expansion Connector s
Technical Summary, Rev. 1
Freescale Semiconductor 2-27
Preliminary
2.15.1 Address Bus Expansion Connector
The address bus expansion connector contains the 56F8367’s 24 external memory address signal
lines. Address lines A6 and A7 can optionally be used as GPIO Port E lines (bits 2 and 3).
Address lines A8 - A15 can optionally be used as GPIO Port A lines (bits 0 - 7). Address lines
A0 - A5 can optionally be used as GPIO Port A lines (bits 8 - 13). Address lines A16 - A23 are
MPIO signals, which can be configured as A16 - A23 or GPIO Port B bits 0 - 7. Refer to
Table 2-16 for the address bus connector information.
Table 2-16. External Memory Address Bus Connector Description
J4
Pin # Signal Pin # Signal
1 A0 / PA8 2 A1 / PA9
3 A2 / PA10 4 A3 / PA11
5 A4 / PA12 6 A5 / PA13
7 A6 / PE2 8 A7 / PE3
9 A8 / PA0 10 A9 / PA1
11 A10 / PA2 12 A11 / PA3
13 A12 / PA4 14 A13 / PA5
15 A14 / PA6 16 A15 / PA7
17 PB0 / A16 18 PB1 / A17
19 PB2 / A18 20 PB3 / A19
21 PB4 / A20 22 PB5 / A21
23 PB6 / A22 24 PB7 / A23
19 GND 20 +3.3V
MC56F8 367 EVM User Manu al, Rev. 1
2-28 Freescale Semiconductor
Preliminary
2.15.2 Data Bus Expansion Connector
The data bus expansion connector contains the 56F8367’s 16 external memory data signal lines.
Refer to Table 2-17 for the data bus connector information. Data lines D0 - D15 can also be used
as GPIO Port F lines (bits 0 - 15).
Table 2-17 . Ex ternal Memory Address Bus Connector Description
J5
Pin # Signal Pin # Signal
1 D0 / PF9 2 D1 / PF10
3 D2 / PF11 4 D3 / PF12
5 D4 / PF13 6 D5 / PF14
7 D6 / PF15 8 D7 / PF0
9 D8 / PF1 10 D9 / PF2
11 D10 / PF3 12 D11 / PF4
13 D12 / PF5 14 D13 / PF6
15 D14 / PF7 16 D15 / PF8
17 GND 18 +3.3V
Peripheral Expansion Connector s
Technical Summary, Rev. 1
Freescale Semiconductor 2-29
Preliminary
2.15.3 External Memory Control Signal Expansion Connector
The external memory control signal connector contains the 56F8367’s external memory control
signal lines. CS2 and CS3 are MPIO signals, which can be configured as GPIO Port D lines (bits
0 and 1). Refer to Table 2-18 for the names of these signals.
2.15.4 Encoder #0 / Quad Timer Channel A Expansion Connector
The Encoder #0 / Quad Timer Channel A port is an MPIO port attached to the Timer A expansion
connector. This port can be configured as a Quadrature Decoder interface port or as a Quad
Timer port. Refer to Table 2-19 for the signals attached to the connector.
Table 2-18. External Memory Control Signal Connector Description
J6
Pin # Signal Pin # Signal
1RD
2IRQA
3WR4IRQB
5PS / CS0 6DS / CS1
7 PD0 / CS2 / CAN2_TX 8 PD1 / CS3 / CAN2_RX
PD2 / CS4 PD3 / CS5
PD4 / CS6 PD5 / CS7
9 CLKO 10 RESET
11 GND 12 RSTO
Table 2-19. Timer A Signal Connector Description
J15
Pin # Signal Pin # Signal
1 PHASEA0 / TA0 2 PHASEB0 / TA1
3 INDEX0 / TA2 4 HOME0 / TA3
5 GND 6 +3.3V
MC56F8 367 EVM User Manu al, Rev. 1
2-30 Freescale Semiconductor
Preliminary
2.15.5 Encoder #1 / SPI #1 Expansion Connector
The Encoder #1 / SPI #1 port is an MPIO port attached to the SPI #1 expansion connector. This
port can be configured as a Quadrature Decoder interface port, a Serial Peripherial Interface,
Quad Timer port or General Purpose I/O port. Refer to Table 2-20 for the signals attached to the
connector.
2.15.6 Timer Channel C Expansion Connector
The Timer Channel C port is a Quad Timer port attached to the Timer C expansion connector.
This port can be configured as a Quad Timer port or a General Purpose I/O port. Refer to
Table 2-21 for the signals attached to the connector.
Table 2-20. SPI #1 Signal Connector Description
J12
Pin # Signal Pin # Signal
1 PHASEB1 / MOSI1 / TB1 / PC1 2 INDEX1 / MISO1 / TB2 / PC2
3 PHASEA1 / SCLK1 / TB0 / PC0 4 HOME1 / SS1 / TB3 / PC3
5GND 6+3.3V
Table 2-21. Timer Channel C Connector Description
J16
Pin # Signal Pin # Signal
1 TC0 / PE8 2 TC1 / PE9
3GND4+3.3V
Peripheral Expansion Connector s
Technical Summary, Rev. 1
Freescale Semiconductor 2-31
Preliminary
2.15.7 Timer Channel D Expansion Connector
The Timer Channel D port is a Quad Timer attached to the Timer D expansion connector. This
port can be configured as a Quad Timer port or a General Purpose I/O port. Refer to Table 2-22
for the signals attached to the connector.
2.15.8 A/D Port A Expansion Connector
The eight-channel Analog-to-Digital conversion Port A is attached to this connector. Refer to
Table 2-23 for connection information. There is a Resistor/Connector (R/C) network on each of
the Analog Port A input signals; see Figure 2-14.
Table 2-22. Timer Channel D Connector Description
J17
Pin # Signal Pin # Signal
1 TD0 / PE10 2 TD1 / PE11
3 TD2 / PE12 4 TD3 / PE13
3 GND 4 +3.3V
Table 2-23. A/D Port A Connector Description
J9
Pin # Signal Pin # Signal
1 AN0 2 AN1
3 AN2 4 AN3
5 AN4 6 AN5
7 AN6 8 AN7
9 GNDA 10 +VREFH
MC56F8 367 EVM User Manu al, Rev. 1
2-32 Freescale Semiconductor
Preliminary
Figure 2-14. Typical Analog Input RC Filter
2.15.9 A/D Port B Expansion Connector
The eight-channel Analog-to-Digital conversion Port B is attached to this connector. Refer to
Table 2-24 for connection information. There is an R/C network on each of the Analog Port B
input signals; see Figure 2-14.
Table 2-24. A/D Port B Connec tor Description
J10
Pin # Signal Pin # Signal
1 AN8 2 AN9
3AN104AN11
5AN126AN13
7AN148AN15
9GNDA10+V
REFH
To Processor’s Analog
Port
100 ohm
Analog Input
0.0022uF
Peripheral Expansion Connector s
Technical Summary, Rev. 1
Freescale Semiconductor 2-33
Preliminary
2.15.10 Serial Communications Port #0 Expansion Connector
The Serial Communications Port #0 is an MPIO port attached to the SCI #0 expansion connector.
This port can be configured as a Serial Communications Interface or as a General Purpose I/O
port. Refer to Table 2-25 for connection information.
2.15.11 Serial Communications Port #1 Expansion Connector
The Serial Communications Port #1 is an MPIO port attached to the SCI #1 expansion connector.
This port can be configured as a Serial Communications Interface or as a General Purpose I/O
port. Refer to Table 2-26 for connection information.
Table 2-25. SCI #0 Connector Description
J13
Pin # Signal Pin # Signal
1 TXD0 / PE0 2 RXD0 / PE1
3GND4+3.3V
5GND6+5.0V
Table 2-26. SCI #1 Connector Description
J14
Pin # Signal Pin # Signal
1 TXD1 / PD6 2 RXD1 / PD7
3GND4+3.3V
5GND6+5.0V
MC56F8 367 EVM User Manu al, Rev. 1
2-34 Freescale Semiconductor
Preliminary
2.15.12 Serial Peripheral Interface #0 Expansion Connector
The Serial Peripheral Interface #0 is an MPIO port attached to this connector. This port can be
configured as a Serial Peripheral Interface or as a General Purpose I/O port. Refer to Table 2-27
for the connection information.
2.15.13 FlexCAN #1 Expansion Connector
The FlexCAN Port #1 is attached to this connector. Refer to Table 2-28 for connection
information.
Table 2-27. SPI #0 Connector Description
J11
Pin # Signal Pin # Signal
1 MOSI0 / PE5 2 MISO0 / PE6
3 SCLK0 / PE4 4 SS0 / PE7
5 GND 6 +3.3V
Table 2-28. CAN #1 Connector Description
J18
Pin # Signal Pin # Signal
1CAN1_TX2 GND
3 CAN1_RX 4 GND
Peripheral Expansion Connector s
Technical Summary, Rev. 1
Freescale Semiconductor 2-35
Preliminary
2.15.14 FlexCAN #2 Expansion Connector
The FlexCAN Port #2 is attached to this connector. Refer to Table 2-29 for connection
information.
2.15.15 PWM Port A Expansion Connector
The PWM Port A is attached to this connector. Refer to Table 2-30 for connection information.
Table 2-29. CAN #2 Connector Description
J19
Pin # Signal Pin # Signal
1CAN2_TX2 GND
3 CAN2_RX 4 GND
Table 2-30. PWM Port A Connector Description
J7
Pin # Signal Pin # Signal
1 PWMA0 2 PWMA1
3 PWMA2 4 PWMA3
5 PWMA4 6 PWMA5
7 FAULTA0 8 FAULTA1
9 FAULTA2 10 FAULTA3
11 ISA0 / PC8 12 ISA1 / PC9
13 ISA2 / PC10 14 GND
MC56F8 367 EVM User Manu al, Rev. 1
2-36 Freescale Semiconductor
Preliminary
2.15.16 PWM Port B Expansion Connector
The PWM Port B is attached to this connector. Refer to Table 2-31 for connection information.
2.16 Test Points
The MC56F8367EVM board has a total of seven test points:
• Analog Ground (AGND)
• Three Digital Grounds (GND)
• +3.3V
• +3.3VA
• +5.0V
Table 2-31. PWM Port B Connector Description
J8
Pin # Signal Pin # Signal
1 PWMB0 2 PWMB1
3 PWMB2 4 PWMB3
5 PWMB4 6 PWMB5
7 FAULTB0 8 FAULTB1
9 FAULTB2 10 FAULTB3
11 ISB0 / PD10 12 ISB1 / PD11
13 ISB2 / PD12 14 GN D
MC56F8367EVM Schematics, Rev. 1
Freescale Semiconductor Appendix A-1
Preliminary
Appendix A
MC56F8367EVM Schematics
MC56F8 367 EVM User Manu al, Rev. 1
Appendix A-2 Freescale Semiconductor
Preliminary
Figure A-1. 56F8367 Processor
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
Single trace
to GNDA
Use on-chip
regulators
Single trace
to GNDA
Use external
+2.5V Supply
DSCO Design
MC56F8367 Proce sso r
MC56F8367EVM.DSN
1.0
114Thursday, September 02, 2004
B
Digital Signal Controller Operation
2100 East Elliot Road
Tempe, Arizona 85284
Title Document
Date:
Size
Designer: Sheet of
Rev.
Number
(512) 895-7215 FAX: (480) 413-2510
VCAPC1
VCAPC3
VCAPC4
VCAPC2
VREFN
VREFMID
VREFP
FAULTB3
FAULTB2
FAULTB1
FAULTB0
FAULTA2
FAULTA1
FAULTA0
TEMP_SENSE ANA7
OCR_DIS
FAULTA3
TEMP_SENSE
PWMA1
PWMA2
PWMA5
ISA1
ISA0
ISA2
FAULTA0
FAULTA1
FAULTA2
PWMA0
PWMA4
PWMA3
PHASEA0
HOME0
INDEX0
PHASEB0
ANA6
ANA0
ANA7
ANA2
ANA1
ANA5
ANA4
ANA3
CAN_RX
CAN_TX
TXD0
RXD0
TXD1
RXD1
PB0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
EXTBOOT
EMI_MODE
ISB1
ANB6
ANB5
ANB1
PWMB2
FAULTB1
FAULTB0
ANB4
PWMB4
PWMB5
PWMB1
ANB0
PWMB3
ISB0
ANB2
FAULTB2
ANB3
PWMB0
FAULTB3
ISB2
ANB7
PHASEB1
HOME1
TC0
TD0
TD1
/IRQA
/IRQB
/WR
/RD
/PS
/DS
PD0
PD1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
TDI
TDO
TMS
/TRST
TCK
FAULTA3
TC1
TD2
TD3
PB1
PB2
PB3
PB4
PB5
PB6
PB7
EXTAL
XTAL
/RESET
/RSTO
CLKO
MISO0
/SS0
SCLK0
MOSI0
CLKMODE
PD2
PD3
PD4
PD5
PHASEA1
INDEX1
+3.3VA
+3.3V_PLL
+VREFH
+3.3V
+2.5V
+3.3V
C58
100pF
C57
0.001uF
C14
0.1uF
C15
0.1uF C16
0.1uF C17
0.1uF
R19
47K
R20
47K
R21
47K
R22
47K
C6
2.2uF C7
2.2uF C8
2.2uF C9
2.2uF
R67
0 Ohm
DNP
R68
0 Ohm
DNP
R69
0 Ohm
DNP
R70
0 Ohm
DNP
R15
47K
R16
47K
R17
47K
JG12
12
R72
0 Ohm
R71
0 Ohm
DNP
R18
47K
U1B
MC56F8367VPY60
1
16
31
42
77
96
134
27
41
74
80
125
62
144
92
113
110
114
115
141
2
112
111
109
95
15
91
160
VDD_IO1
VDD_IO2
VDD_IO3
VDD_IO4
VDD_IO5
VDD_IO6
VDD_IO7
VSS_IO1
VSS_IO2
VSS_IO3
VSS_IO4
VSS_IO5
VCAPC1
VCAPC2
VDDA_OSC_PLL
VREFH
VREFN
VDDA_ADC
VSSA_ADC
VPP1
VPP2
VREFP
VREFMID
VREFLO
VCAPC3
VCAPC4
OCR_DIS
VSS_IO6
C77
0.1uF
U1A
MC56F8367VPY60
154
10
11
12
13
14
17
18
19
20
21
22
23
24
25
26
53
54
51
52
70
71
83
86
88
89
90
28
29
30
32
149
150
151
152
153
33
49
50
38
39
40
43
44
45
61
63
64
65
66
67
68
69
72
73
75
76
78
79
81
82
84
85
124
93
94
97
98
126
127
128
116
117
118
119
120
121
122
123
108
129
130
133
136
137
138
139
140
145
146
147
148
142
143
7
8
6
9
4
5
3
159
55
56
99
34
35
36
37
57
58
59
60
155
156
157
158
100
101
102
103
104
105
106
107
87
135
131
132
46
47
48
A0/PA8
A1/PA9
A2/PA10
A3/PA11
A4/PA12
A5/PA13
A6/PE2
A7/PE3
A8/PA0
A9/PA1
A10/PA2
A11/PA3
A12/PA4
A13/PA5
A14/PA6
A15/PA7
PS/CS0/PD8
DS/CS1/PD9
WR
RD
D0/PF9
D1/PF10
D2/PF11
D3/PF12
D4/PF13
D5/PF14
D6/PF15
D7/PF0
D8/PF1
D9/PF2
D10/PF3
D11/PF4
D12/PF5
D13/PF6
D14/PF7
D15/PF8
PB0/A16
TXD1/PD6
RXD1/PD7
PWMB0
PWMB1
PWMB2
PWMB3
PWMB4
PWMB5
ISB0/PD10
ISB1/PD11
ISB2/PD12
IRQA
IRQB
FAULTB0
FAULTB1
FAULTB2
FAULTB3
PWMA0
PWMA1
PWMA2
PWMA3
PWMA4
PWMA5
FAULTA0
FAULTA1
FAULTA2
EXTBOOT
XTAL
EXTAL
RSTO
RESET
ISA0/PC8
ISA1/PC9
ISA2/PC10
ANB0
ANB1
ANB2
ANB3
ANB4
ANB5
ANB6
ANB7
TEMP_SENSE
TD0/PE10
TD1/PE11
TC0/PE8
TRST
TCK
TMS
TDI
TDO
SS0/PE7
SCLK0/PE4
MISO0/PE6
MOSI0/PE5
CAN1_TX
CAN1_RX
PHASEB1/TB1/MOSI1/PC1
INDEX1/TB2/MISO1/PC2
PHASEA1/TB0/SCLK1/PC0
HOME1/TB3/SS1/PC3
TXD0/PE0
RXD0/PE1
CLKO
EMI_MODE
PD0/CS2/CAN2_TX
PD1/CS3/CAN2_RX
CLKMODE
PB1/A17
PB2/A18
PB3/A19
PB4/A20/Prescaler_Clock
PD2/CS4
PD3/CS5
PD4/CS6
PD5/CS7
PHASEA0/TA0/PC4
PHASEB0/TA1/PC5
INDEX0/TA2/PC6
HOME0/TA3/PC7
ANA0
ANA1
ANA2
ANA3
ANA4
ANA5
ANA6
ANA7
FAULTA3
TC1/PE9
TD2/PE12
TD3/PE13
PB5/A21/SYS_CLK
PB6/A22/SYS_CLKx2
PB7/A23/OSC_CLOCK
MC56F8367EVM Schematics, Rev. 1
Freescale Semiconductor Appendix A-3
Preliminary
Figure A-2. Reset, Mode, Clock & IRQs
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
12
3
DS1818
IRQB PUSHBUTTON
IRQA PUSHBUTTON
User
SOFTWARE FEATURE JUMPERS
#0
Jumper
Jumper
#1
User
BOOT MODE JUMPER
INT BOOT
EXT BOOT NC
1 - 2
NC
1 - 2
EMI A0-A23
EMI MODE JUMPER
EMI A0-A15
OSC BYPASS
RESET PUSHBUTTON
OPTIONAL
CLOCK MODE JUMPER
1 - 2
EXT OSC
USE CRYSTAL
NC
PE4
PE7
DSCO Design
RESET, MODE, CLOCK & IRQ S
MC56F8367EVM.DSN
1.0
214Thursday, September 02, 2004
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Digital Signal Controller Operation
2100 East Elliot Road
Tempe, Arizona 85284
Title Document
Date:
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Number
(512) 895-7215 FAX: (480) 413-2510
/POR
/IRQB
/IRQA SCLK0
/SS0
EXTBOOT
EMI_MODE
/POR
EXTAL
XTAL
CLKMODE
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V +3.3V
R4
10K
C18
0.1uF
R3
10K
C19
0.1uF
S2
S3
JG15
1
2
3
R8
10K
R9
10K
R11
10K
R10
10K JG16
1
2
3
R5
10K
JG4
1
2
JG5
1
2
R6
10K
Y1
8.00MHz R1
1M
U16
DS1818
21
3
Vcc RST
GND
R2
10K
JG2
12
JG1
12
3
S1 JG6
1
2
R7
10K
MC56F8 367 EVM User Manu al, Rev. 1
Appendix A-4 Freescale Semiconductor
Preliminary
Figure A-3. Program [W ord] (CS0) & Data [Byte] (CS1 /CS4) SRAM Memory
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
128Kx16-bit Program Memory (CS0) 128Kx16-bit Data Memory (CS1/CS4)
NC
OPTION JG8
1-2SRAM WORD ENABLE
SRAM DISABLE
NC
OPTION
CS0 ENABLE JUM PER
1-2SRAM ENABLE
SRAM DISABLE
CS1/CS4 ENABLE JUM PE R
3-4
SRAM UPPER BYTE ENABLE
SRAM LOWER BYTE ENABLE
NC
1-2
3-4
NC
NC
A16
JG7
A17
A18
Note:
Note: A17 & A18 are
N/C on GS72116.
Note: A17 & A18 are
N/C on GS72116.
GS71116ATP 64Kx16-bit
GS72116ATP 128Kx16-bit
GS74116ATP 256Kx16-bit
IS61LV51216 512Kx16-bit
DSCO Design
PROGRAM [WORD] (CS0) and DATA [BYTE] (CS1/CS4) SRAM MEMORY
MC56F8367EVM.DSN
1.0
314Thursday, September 02, 2004
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Digital Signal Controller Operation
2100 East Elliot Road
Tempe, Arizona 85284
Title Document
Date:
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Number
(512) 895-7215 FAX: (480) 413-2510
D2
D5
D13
D4
D0
D6
D15
D11
D3
D10
D1
D7
D12
D9
D8
D14
A15
A11
A1
A12
A10
A3
A14
A5
A9
A6
A8
A0
A7
A13
A2
A4
PB0
/ECS4
/ECS1
/UB
/LB
/ECS0
/RD
/WR
/ECS4
/ECS1
/CE
PB1
PB2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
PB0
/PS /RD
/WR
PB1
PB2
PD2
/DS
+3.3V
+3.3V
+3.3V +3.3V
R14
10K
R13
10K
R31
1K
R30
1K
R12
10K
JG7
12
U2
GS72116TP-7
7
8
1
9
10213
14
3
15
16
4
29
30
5
31
32
18
35
36
19 37
38
20
21
24
25
26
27
42
43
44
40
39
41
17
6
22
34
12
33
11
23
28
DQ1
DQ2
A4
DQ3
DQ4A3 DQ5
DQ6
A2
DQ7
DQ8
A1
DQ9
DQ10
A0
DQ11
DQ12
A15
DQ13
DQ14
A14 DQ15
DQ16
A13
A12
A11
A10
A9
A8
A7
A6
A5
UB
LB
OE
WE
CE
A16
VSS2
VSS1
VDD2
VDD1
A17
A18
U3
GS72116TP-7
7
8
1
9
10213
14
3
15
16
4
29
30
5
31
32
18
35
36
19 37
38
20
21
24
25
26
27
42
43
44
40
39
41
17
6
22
34
12
33
11
23
28
DQ1
DQ2
A4
DQ3
DQ4A3 DQ5
DQ6
A2
DQ7
DQ8
A1
DQ9
DQ10
A0
DQ11
DQ12
A15
DQ13
DQ14
A14 DQ15
DQ16
A13
A12
A11
A10
A9
A8
A7
A6
A5
UB
LB
OE
WE
CE
A16
VSS2
VSS1
VDD2
VDD1
A17
A18
JG8
1
32
4R32
1K
MC56F8367EVM Schematics, Rev. 1
Freescale Semiconductor Appendix A-5
Preliminary
Figure A-4. RS-232 and SCI Connectors
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
RS-232 SHUTDOWN JUMPER
1 - 2
N/C
RS-232 ENABLE
RS-232 DISABLE
CONNECTOR
CTS
DSR
DTR
RXD
TXD
RTS
DCD
SCI #0
RS-232
GND
DSCO Design
RS-232 AND SCI C ONNECTORS
MC56F8367EVM.DSN
1.0
414Thursday, September 02, 2004
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Digital Signal Controller Operation
2100 East Elliot Road
Tempe, Arizona 85284
Title Document
Date:
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Number
(512) 895-7215 FAX: (480) 413-2510
R4IN
R5IN
R3IN
T3IN
/EN
RTS1
T3IN
RS232EN
/EN
R3IN
R4IN
R5IN
TXD
RXD
CTS
TX_IN
RX_OUT
RTS1
CTS1
CTS1
RTS
TXD0
RXD0
+3.3V
+3.3V +3.3V
R37
1K
R38
1K
R36
1K
R35
1K
R34
1K
C10
1.0uF
C11
1.0uF C13
1.0uF
C12
1.0uF
JG10
1
2
R33
1K
P2
5
9
4
8
3
7
2
6
1
U4
MAX3245EEAI
27
1
26
2
23
28
14
13
12
19
18
17
16
15 8
7
6
5
4
11
10
9
22
24 3
25
20
21
V+
C2+
VCC
C2-
FORCEON
C1+
T1IN
T2IN
T3IN
R1OUT
R2OUT
R3OUT
R4OUT
R5OUT R5IN
R4IN
R3IN
R2IN
R1IN
T3OUT
T2OUT
T1OUT
FORCEOFF
C1- V-
GND
R2OUTB
INVALID
JG9
1
32
41
1
1
1
1
1
JG11
1
2
MC56F8 367 EVM User Manu al, Rev. 1
Appendix A-6 Freescale Semiconductor
Preliminary
Figure A-5. User Debug LEDs
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
USER
LEDS
PC3
PC1
PC2
PC0
RED LED
YELLOW LED
GREEN LED
RED LED
PD6
PD7
YELLOW LED
GREEN LED
DSCO Design
USER DEBUG LED S
MC56F8367EVM.DSN
1.0
514Thursday, September 02, 2004
A
Digital Signal Controller Operation
2100 East Elliot Road
Tempe, Arizona 85284
Title Document
Date:
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Number
(512) 895-7215 FAX: (480) 413-2510
HOME1
INDEX1
PHASEB1
PHASEA1
RXD1
TXD1
+3.3V
U6B
74AC04
3 4
U6C
74AC04
5 6
U6D
74AC04
9 8
R60
270
R59
270
LED1
R58
270
U6A
74AC04
1 2
LED3
LED2
LED4
U6E
74AC04
11 10
U6F
74AC04
13 12 R63
270
R62
270
LED6
LED5
R61
270
MC56F8367EVM Schematics, Rev. 1
Freescale Semiconductor Appendix A-7
Preliminary
Figure A-6. PWM Port A State LEDs
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
PWM STATE
LEDS
YELLOW LED
YELLOW LED
GREEN LED
GREEN LED
GREEN LED
YELLOW LED
DSCO Design
PWM PORT A STATE LE DS
MC56F8367EVM.DSN
1.0
614Thursday, September 02, 2004
A
Digital Signal Controller Operation
2100 East Elliot Road
Tempe, Arizona 85284
Title Document
Date:
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Number
(512) 895-7215 FAX: (480) 413-2510
PWMA4
PWMA1
PWMA0
PWMA5
PWMA2
PWMA3
+3.3V
R52
270
R53
270
R54
270
R55
270
R56
270
R57
270
U5A
74AC04
1 2
U5B
74AC04
3 4
U5C
74AC04
5 6
U5D
74AC04
9 8
U5E
74AC04
11 10
U5F
74AC04
13 12
LED7
LED8
LED9
LED10
LED11
LED12
MC56F8 367 EVM User Manu al, Rev. 1
Appendix A-8 Freescale Semiconductor
Preliminary
Figure A-7. High-Speed CAN Port #1 Interface
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
CAN BUS CONNECTOR DAISY-CHAIN
CAN BUS CONNECTOR
CAN BUS
TERMINATION
DSCO Design
HIGH-SPEED CAN PORT #1 INTERFA CE
MC56F8367EVM.DSN
1.0
714Thursday, September 02, 2004
A
Digital Signal Controller Operation
2100 East Elliot Road
Tempe, Arizona 85284
Title Document
Date:
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Number
(512) 895-7215 FAX: (480) 413-2510
CANL
BCANHBCANL
BCANH
BCANL
BCANL BCANH
CANH BCANH
BCANL
CAN_TX
CAN_RX
+5.0V
+5.0V
U10
PCA82C250T
1
4
2
3
5
6
7
8
TXD
RXD
GND
VCC
VREF
CANL
CANH
SLOPE
R28
1K
T11
J20
1
3
5
7
9
2
4
6
8
10
J21
1
3
5
7
9
2
4
6
8
10
JG13
1
2
R40
120
1/4W
L6
MC56F8367EVM Schematics, Rev. 1
Freescale Semiconductor Appendix A-9
Preliminary
Figure A-8. High-Speed CAN Port #2 Interface
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
CAN BUS CONNECTOR DAISY-CHAIN
CAN BUS CONNECTOR
CAN BUS
TERMINATION
DSCO Design
HIGH-SPEED CAN PORT #2 INTERFA CE
MC56F8367EVM.DSN
1.0
814Thursday, September 02, 2004
A
Digital Signal Controller Operation
2100 East Elliot Road
Tempe, Arizona 85284
Title Document
Date:
Size
Designer: Sheet of
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Number
(512) 895-7215 FAX: (480) 413-2510
CAN2_RX
CAN2_TX
CAN2L
BCAN2HBCAN2L
BCAN2H
BCAN2L
BCAN2L BCAN2H
CAN2H BCAN2H
BCAN2L
PD1
PD0
+5.0V
+5.0V
U11
PCA82C250T
1
4
2
3
5
6
7
8
TXD
RXD
GND
VCC
VREF
CANL
CANH
SLOPE
R29
1K
T21
J22
1
3
5
7
9
2
4
6
8
10
J23
1
3
5
7
9
2
4
6
8
10
JG17
1
2
R41
120
1/4W
L7
JG14
1
32
4
MC56F8 367 EVM User Manu al, Rev. 1
Appendix A-10 Freescale Semiconductor
Preliminary
Figure A-9. Daughter Card Connectors
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
Daughter Address/Data Connector
/CS0
/CS1
/CS2/CAN2_TX
/CS3/CAN2_RX
A16 A17
/CS6 /CS7
/CS5 /CS4
A19 A18
TA2
TA1
Daughter Peripheral Port Connector
PC1/TB1/MOSI1
PE0
PC3/TB3/SS1
PC0/TB0/SCLK1
PE4
PE1
PE6
PE5
PC2/TB2/MISO1
PD7
TA0
PE7
PD6
TA3
GND
GND
GND
GND
GND
GNDGND
GND
A20
DSCO Design
DAUGHTER CARD CONNECTORS
MC56F8367EVM.DSN
1.0
914Thursday, September 02, 2004
A
Digital Signal Controller Operation
2100 East Elliot Road
Tempe, Arizona 85284
Title Document
Date:
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Number
(512) 895-7215 FAX: (480) 413-2510
GNDGNDA
GNDGND
GND GND
GND
GNDGND
GNDGND
GND
GND
GND
GND
GND
GNDA
GND
GNDA
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND A5
A6
A7
A4
A3
A2
A1 /RD
/PS
A0 PD0
/DS
D0
D1 D15
D14
D12
D13
D10
D11
D3
D2
D5
D4
PD1
A11
D9
A10
A9
A8
D8
A15
A12
PB0
D7
A13
/WR
A14
D6
PWMA1
AN12
AN10
/SS0
TD1
PWMB3
AN13
AN1
AN6
TC0
FAULTA0
PWMB2
FAULTB3
RXD1
PWMA3
FAULTB1
PHASEB1
/IRQB/IRQA
PWMB5
PWMA0
CAN_TX
FAULTA2
ISB0
AN11
PHASEB0
FAULTB0
HOME1
PHASEA0
INDEX0
ISA2
FAULTA1
CAN_RX
INDEX1
ISA0
TD0
FAULTB2
PWMA5
ISB1
TXD1
RXD0
AN14
AN0
PWMB1
AN2
PHASEA1
MOSI0
ISB2
PWMA2
AN9
AN7
AN4
HOME0
MISO0
TXD0
AN8
/RSTO
SCLK0
AN5
AN3
ISA1
PWMB4
PWMB0
PWMA4
AN15
/SS0
MISO0
SCLK0
MOSI0
TXD1
RXD1
TXD0
RXD0
PB4
PB1
PB2PB3
PD2PD3
PD4 PD5
+3.3V
+5.0V
+5.0V
+3.3V
+3.3VA
+12V+12V
+3.3VA
+5.0V
+3.3V
+5.0V
+3.3V
J2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
51 52
53 54
55 56
57 58
59 60
J1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
51 52
53 54
55 56
57 58
59 60
61 62
63 64
65 66
67 68
69 70
71 72
73 74
75 76
77 78
79 80
81 82
83 84
85 86
87 88
89 90
91 92
93 94
95 96
97 98
99 100
MC56F8367EVM Schematics, Rev. 1
Freescale Semiconductor Appendix A-11
Preliminary
Figure A-10. Processor Port Expansion Connectors
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
TA3TA2
TA1
SPI #0
PWMB
SCI #0
TIMER CHANNEL C TIMER CHANNEL DTIMER CHANNEL A
CAN #1
A/D PORT B
PWMA
SPI #1 SCI #1
A/D PORT A
TA0
DATA BUS ADDRESS CONTROL
A16
ADDRESS BUS
/CS2 /CS3
/CS0 /CS1
SCLK1
MOSI1 MISO1
/SS1
A22
A18
A20
A17
A19
A21
A23
/CS4
/CS6
/CS5
/CS7
CAN #2
CAN2_TX
CAN2_RX
QUAD-DECODER #1
QUAD-DECODER #0
&
&
DSCO Design
PROCESSOR PORT EXPANSION CONNECTORS
MC56F8367EVM.DSN
1.0
10 14Thursday, September 02, 2004
B
Digital Signal Controller Operation
2100 East Elliot Road
Tempe, Arizona 85284
Title Document
Date:
Size
Designer: Sheet of
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Number
(512) 895-7215 FAX: (480) 413-2510
PWMB0
PWMB2
PWMB4
PWMB1
PWMB3
PWMB5
FAULTB0
FAULTB2 FAULTB1
FAULTB3
ISB0
ISB2 ISB1
PWMA0
PWMA2
PWMA4
PWMA1
PWMA3
PWMA5
FAULTA0
FAULTA2 FAULTA1
ISA0 ISA1
ISA2
MOSI0 MISO0
SCLK0 /SS0 PHASEB1 INDEX1
PHASEA1 HOME1
INDEX0 HOME0
PHASEB0PHASEA0
TXD0 RXD0 TXD1 RXD1
TD0 TD1TC0
CAN_TX
CAN_RX
AN0 AN1
AN2 AN3
AN4 AN5
AN6 AN7
AN8 AN9
AN10 AN11
AN12 AN13
AN14 AN15
/IRQB
/IRQA
/WR
/RD
/PS
PB0
PD0 /DS
A1
A3
A5
A7
A9
A11
A13
A15
A4
A6
A8
A10
A12
A14
A2
A0 D0 D1
D2 D3
D4 D5
D6 D7
D8 D9
D10 D11
D12 D13
D14 D15
PB1
PB3
PB5
PB7PB6
PB2
PB4
FAULTA3
/RSTO
/RESETCLKO
PD2
PD4
PD1
PD3
PD5
PD0
PD1
TC1 TD2 TD3
+3.3V
+3.3V
+3.3V
+5.0V +5.0V
+3.3V
+3.3V
+3.3VA +3.3VA
+3.3V
+3.3V
+3.3V
+3.3V
J8
1
3
5
7
9
11
13
2
4
6
8
10
12
14
J7
1
3
5
7
9
11
13
2
4
6
8
10
12
14
J11
1
3
5
2
4
6
J12
1
3
5
2
4
6
J15
1
3
5
2
4
6
J13
1
3
5
2
4
6
J14
1
3
5
2
4
6
J16
1
32
4
J18
1
32
4
J9
1
3
5
7
9
2
4
6
8
10
J10
1
3
5
7
9
2
4
6
8
10
J5
12
34
56
78
910
11 12
13 14
15 16
17 18
J4
1
3
5
7
9
11
13
15
17
19
21
23
25
2
4
6
8
10
12
14
16
18
20
22
24
26
J6
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
16
J19
1
32
4
J17
1
3
5
2
4
6
MC56F8 367 EVM User Manu al, Rev. 1
Appendix A-12 Freescale Semiconductor
Preliminary
Figure A-11. Parallel JTAG Host Target Interface and JTAG Connector
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
Parallel JTAG Interface
KEY
JTAG Connector
On-Board
Host Target Interface
Disable
PORT_DE
PORT_VCC
DSCO Design
PARALLEL JTAG HOST TARGET INTERF ACE AND JTAG CONNECTOR
MC56F8367EVM.DSN
1.0
11 14Thursday, September 02, 2004
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Digital Signal Controller Operation
2100 East Elliot Road
Tempe, Arizona 85284
Title Document
Date:
Size
Designer: Sheet of
Rev.
Number
(512) 895-7215 FAX: (480) 413-2510
/J_RESET
P_RESET
/J_TRST
/J_RESET
TDO
P_RESET
TMS
TCK
/J_TRST
PORT_TDO
PORT_TMS
/PORT_TRST
PORT_TCK
PORT_TDI
PORT_CONNECT
PORT_RESET
PORT_IDENT
/J_RESET
/J_TRST
/DE
P_DE
/J_TRST
PWR
/DE
TDI
PWR
TDO
P_DE
/CCEN
PORT_PU
PORT_CONNECT
PORT_PU
TDI
TDO
TCK
TMS
/RESET
/TRST
/POR
+3.3V
+3.3V
+3.3V
+3.3V
+Vsel
+Vsel
+5.0V
+3.3V
R51
51 Ohm
R48
5.1K
R42
5.1K J3
1
3
5
7
9
11
13
2
4
6
8
10
12
14
R23
47K
R24
47K
JG3
1
2
P1 1
3
2
15
14
16 4
17 5
18 6
19 7
20 8
21 9
22 10
23 11
24 12
25 13 R50
51 Ohm
Q1
2N2222A
U7A
74AC00
1
23
U7D
74AC00
12
13 11
U7B
74AC00
4
56
U7C
74AC00
9
10 8
R47
5.1K
R27
47K
R25
47K
R26
47K
R46
5.1K
R44
5.1K R45
5.1K
R43
5.1K
U8
MC74HC244DW
18
16
14
12
9
7
5
3
19
1
2
4
6
8
11
13
15
1720
10
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
2G
1G
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4VCC
GND
U9
MC74LCX244DW
18
16
14
12
9
7
5
3
19
1
2
4
6
8
11
13
15
17
20
10
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
2G
1G
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
VCC
GND
R76
0 Ohm
R73
0 Ohm R74
0 Ohm
R77
0 Ohm
R75
0 Ohm
11
R95
1K
DNP
R94
1K
JG19
12
3
MC56F8367EVM Schematics, Rev. 1
Freescale Semiconductor Appendix A-13
Preliminary
Figure A-12. A/D Input Filters
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
NOTE: Use a single trace
for GNDA signals to the
common GNDA point.
DSCO Design
A/D INPUT FILTE RS
MC56F8367EVM.DSN
1.0
12 14Thursday, September 02, 2004
A
Digital Signal Controller Operation
2100 East Elliot Road
Tempe, Arizona 85284
Title Document
Date:
Size
Designer: Sheet of
Rev.
Number
(512) 895-7215 FAX: (480) 413-2510
ANA7
ANB0
ANB1
ANB2
ANB3
ANB4
ANB5
ANB6
ANB7
ANA0
ANA1
ANA2
ANA3
ANA4
ANA5
ANA6
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
C59
0.0022uF
C60
0.0022uF
C61
0.0022uF
C62
0.0022uF
C63
0.0022uF
C64
0.0022uF
C65
0.0022uF
C66
0.0022uF
C67
0.0022uF
C68
0.0022uF
C69
0.0022uF
C70
0.0022uF
C71
0.0022uF
C72
0.0022uF
C73
0.0022uF
C74
0.0022uF
R85
100
R86
100
R87
100
R88
100
R89
100
R90
100
R91
100
R92
100
R93
100
R78
100
R79
100
R80
100
R81
100
R82
100
R83
100
R84
100
MC56F8 367 EVM User Manu al, Rev. 1
Appendix A-14 Freescale Semiconductor
Preliminary
Figure A-13. Power Supplies
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
EXTERNAL POWER INPUT
7-12V DC/AC
123
4
MC33269
3.3V AND 5.0V
REGULATOR
TEST POINT
POWER GOOD LED
NOTE: Remove 0 OHM
resistor to use Analog
GND isolation jumper.
Single trace
to GNDA.
+3.3V +3.3VA GROUND ANALOG GROUND +5.0V
TEST POINT TEST POINT
GROUND
TEST POINT
GROUND
TEST POINT TEST POINT TEST POINT
External +2.5V
Power Supply
Input
+2.5V Input
+2.5V Ground Reference
NOTE: To measure +3.3V supply
current, remove L2 and replace
with amp meter.
Typ 135mA
+3.3V
1
2
34
REG113NA3/3K
3.3V REF
REGULATOR
5
DSCO Design
POWER SUPPLIES
MC56F8367EVM.DSN
1.0
13 14Thursday, September 02, 2004
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Digital Signal Controller Operation
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Title Document
Date:
Size
Designer: Sheet of
Rev.
Number
(512) 895-7215 FAX: (480) 413-2510
+3.3V
+3.3V
+3.3V_PLL
+3.3VA+3.3V
VCC
+3.3VA
+5.0V
+5.0V
+5.0V
+12V
+5.0V
+5.0V
+2.5V
+5.0V +VREFH
C20
0.1uF
U12
MC33269DT-5.0
3 2
41
VIN VOUT
VOUTGND L1
FERRITE BEAD
L5
FERRITE BEAD
+
C3
47uF
10VDC
+
C1
470uF
16VDC
+
C2
47uF
10VDC
L4
FERRITE BEAD
TP5
1
TP6
1
TP1
1
TP4
1
TP2
1
TP3
1
D2
FM4001
P3 1
3
2
-+
D1
3
1
4
2
C21
0.1uF
+
C5
47uF
10VDC
U13
MC33269DT-3.3
3 2
41
VIN VOUT
VOUTGND
R64
270
LED13
GREEN LED
L3
FERRITE BEAD
L2
FERRITE BEAD
+
C4
47uF
10VDC
C22
0.1uF JG18
1
2
R66
0 Ohm
U14
MC33269DT-3.3
3 2
41
VIN VOUT
VOUTGND
D3
FM4001
DNP
D4
FM4001
DNP
TP7
1
J24
1
2
U15
REG113NA-3.3/3K
15
4
2
3
VIN VOUT
NR
GND
EN
+
C75
10uF
6VDC
C76
0.01uF
R65
10 Ohm
MC56F8367EVM Schematics, Rev. 1
Freescale Semiconductor Appendix A-15
Preliminary
Figure A-14. Bypass Capacitors
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
MC56F8367
GS72116
A/D CONNECTOR
ADDRESS BUS
CONNECTOR CONNECTOR
DATA BUS
MAX3245GS72116
A/D CONNECTOR
U4
J4 J5 J9 J10
U1
U3
U2
PERIPHERAL CONNECTOR
J1 J2
MEMORY CONNECTOR
74AC04 74AC00 74LCX244
74AC04 74HC244 U9U8
U7
U5 U6 U10
PCA82C250 U11
PCA82C250
DSCO Design
BYPASS CAPACITOR S
MC56F8367EVM.DSN
1.0
14 14Thursday, September 02, 2004
B
Digital Signal Controller Operation
2100 East Elliot Road
Tempe, Arizona 85284
Title Document
Date:
Size
Designer: Sheet of
Rev.
Number
(512) 895-7215 FAX: (480) 413-2510
+3.3V +3.3V
+VREFH
+3.3V+3.3V +3.3VA
+3.3V
+3.3V
+3.3V +3.3V
+3.3VA
+5.0V +3.3V +12V +3.3VA +5.0V +3.3V +3.3V
+3.3V +3.3V +3.3V+3.3V +Vsel +5.0V +5.0V
C48
0.1uF
C29
0.1uF
C47
0.1uF
C53
0.01uF
C49
0.1uF
C55
0.01uF C51
0.1uF
DNP
C52
0.01uF C27
0.1uF
C26
0.1uF
C25
0.1uF
C24
0.1uF
C23
0.1uF C54
0.01uF C28
0.1uF
C30
0.1uF C56
0.01uF
C50
0.1uF
C40
0.1uF C41
0.1uF C42
0.1uF C43
0.1uF C44
0.1uF C45
0.1uF C46
0.1uF
C37
0.1uF C35
0.1uF
C38
0.1uF C39
0.1uF C36
0.1uF C31
0.1uF C32
0.1uF
MC56F8 367 EVM User Manu al, Rev. 1
Appendix A-16 Freescale Semiconductor
Preliminary
MC56F8367EVM Bill of Material, Rev. 1
Freescale Semiconductor Appendix B-1
Preliminary
Appendix B
MC56F8367EVM Bill of Material
Qty Description Ref. Designators Vendor Part #
Integrated Circuits
1 MC56F8 367 U1 Freescale, MC56 F83 67VPY60
2 128K x 16-Bit SRAM U2, U3 GSI, GS72116ATP-8
1 RS-232 Tran sceiver U4 Maxim, MAX3245EEAI
2 74AC04 U5, U6 ON Semiconductor, MC74AC04AD
1 74AC00 U7 Fairchild, 74AC00SC
1 74HC244 U8 ON Semiconductor, MC74LHC44AADW
1 74LCX244 U9 ON Semiconductor, MC74LCX244ADW
2 CAN Transceiver U10, U11 Philips Semiconductor, PCA82C250T
1 +5.0V Voltage Regulator U12 ON Semiconductor, MC33269DT-5
2 +3.3V Voltage Regulator U13, U14 ON Semiconductor, MC33269DT-3.3
1 +3.3V Voltage Regulator U15 Burr-Brown, REG113NA-3.3
0 Power-On Reset U16 (Optional) Dallas Semiconductor, DS1818
Resistors
11MΩR1 SMEC, RC73L2A105OHMJT
13 10KΩR2 - R14 SMEC, RC73L2A103OHMJT
13 47KΩR15 - R27 SMEC, RC73L2A473OHMJT
12 1KΩR28 - R38, R94 SMEC, RC73L2A103OHMJT
01KΩR95 (Optional) SMEC, RC73L2A103OHMJT
2120Ω, 1/4W R40, R41 YAGEO, CFR 120QBK
75.1KΩR42 - R48 SMEC, RC73L2A512OHMJT
MC56F8 367 EVM User Manu al, Rev. 1
Appendix B-2 Freescale Semiconductor
Preliminary
251ΩR50, R51 SMEC, RC73L2A51OHMJT
13 270Ω R52 - R64 SMEC, RC73L2 A27 1O H MJT
110ΩR65 SMEC, RC73L2A100OHMJT
70ΩR66, R72 - R77 SMEC, RC73JP2A
00ΩR67 - R71 (Optional) SMEC, RC73JP2A
16 100ΩR78 - R93 SMEC, RC7 3L2 A10 1O H MJ T
Inductors
5 1.0mH FERRITE BEAD L1 - L5 Panasonic, EXC-ELSA35V
2 CAN Bus Filter L6, L7 EPCOS, B82790-S0513-N201
LEDs
2 Red LED LED1, LED4 Hewle tt-Packard, HSMS-C650
5 Yellow LED LED2, LED5, LED7, LED9,
LED11 Hewlett-Pac kar d, HSMY-C65 0
6 Green LED LED3, LED6, LED8, LED10,
LED12, LED13 Hewlett-Packa rd, HSMG -C65 0
Diode
1 +50V 1A BRIDGE RECT D1 DIODES, DF02S
1 S2B-FM401 D2 Vishay, DL4001DICT
0 S2B-FM401 D3, D4 (Optional) Vishay, DL4001DICT
Qty Description Ref. Designators Vendor Part #
MC56F8367EVM Bill of Material, Rev. 1
Freescale Semiconductor Appendix B-3
Preliminary
Capacitors
1470µF, +16V DC C1 ELMA, RV-16V471MH10R
447µF, +16V DC C2 - C5 ELMA, RV2-16V470M-R
42.2µF, +25V DC
(Low ESR) C6 - C9 TAIYO YUDEN, CELMK212BJ225MG-T
41.0µF, +25V DC C10 - C13 SMEC, MCCE105K3NR-T1
37 0.1µF C14 - C32, C35 - C51, C77 SMEC, MCCE104K2NR-T1
60.01µF C52 - C56, C76 SMEC, MCCE103K2NR-T1
10.001µF C57 SMEC, MCCE102K2NR-T1
1 100pF C58 SMEC, MCCE101K2NR-T1
16 0.0022µF C59 - C74 SMEC, MCCE222K2NR-T1
110µF, +10V DC C75 KEMET, T494B106M010AS
Jumpers
43 × 1 Bergstick JG1, J G15, JG16, JG19 SAMT EC, TS W-10 3-07-S- S
12 1 × 2 Bergstick JG2 - JG7, JG10 - JG13,
JG17, JG18 SAMTEC, TSW-102-07-S-S
32 × 2 Bergstick JG8 , JG9, JG14 SAMTEC, TSW-10 2-07-S- D
Test Points
3 GND Test Point TP1, TP2, TP3 KEYSTONE, 5001, BLACK
1 +3.3V Test Point TP4 KEYSTONE, 5000, RED
1 +3.3V A Test Point TP5 KEYSTONE, 5004, YELLOW
1 GNDA Test Point TP6 KEYSTONE, 5002, WHITE
1 +5.0V Test Point TP7 KEYSTONE, 5003, ORANGE
Crystals
1 8.00MHz Crystal Y1 CTS, ATS08ASM-T
Qty Description Ref. Designators Vendor Part #
MC56F8 367 EVM User Manu al, Rev. 1
Appendix B-4 Freescale Semiconductor
Preliminary
Connectors
1 DB25M Connector P1 AMPHENOL, 617-C025P-AJ121
1 DE9S Connector P2 AMPHENOL, 617-C009S-AJ120
1 2.1mm c oax
Power Connector P3 Switchcraft, RAPC-722
1 Peripheral Daughter
Card Connector J1 HRS, FX6-100P-0.8SV2
1 Memory Bus Daughter
Card Connector J2 HRS, FX6-60P-0.8SV2
1 7 x 2 JTAG Header J3 SAMTEC, TSW-106-07-S-D
1 13 x 2 Header J4 SAMTEC, TSW-106-13-S-D
1 9 x 2 Header J5 SAMTEC, TSW-106-09-S-D
1 8 x 2 Header J6 SAMTEC, TSW-106-08-S-D
2 7 x 2 Header J7, J8 SAMTEC, TSW-106-07-S-D
6 5 x 2 Header J9, J10, J20 - J23 SAMTEC, TSW-106-05-S-D
6 3 x 2 Header J11 - J15, J17 SAMTEC, TSW-106-03-S-D
3 2 x 2 Header J16, J18, J19 SAMTEC, TSW-106-02-S-D
1 1 x 2 Header J24 SAMTEC, TSW-106-02-S-S
Switches
3 SPST Push button S1 - S3 Panasonic, EVQ-PAD05R
Transistors
1 2N2222A Q1 ZETEX, FMMT2222ACT
Miscellaneous
18 Shunt SH1 - SH13 Samtec, SNT-100-BL-T
4 Rubber Feet RF1 - RF4 3M, SJ5018BLKC
INDEX
Index
Freescale Semiconductor Index - 1
Preliminary
Numerics
1.2 Amp power supply 2-16
56F8300 Peripheral User Manual 2-4
56F8357 Technical Data Sheet 2-4
8.00MHz crystal oscillator 2-1
A
A/D viii
ADC viii
Analog-to-Digital
A/D viii
Analog-to-Digital Converter
ADC viii
C
CAN viii
bus termination 2-2
bypass 2-2
interface 2-1
CA N in Automation
CiA viii
CAN physical layer peripheral 2-2
CiA viii
Controller Area Network
CAN viii
D
D/A viii
Daughter Card Expansion
interface 2-1
Debugging 2-10
Digital Signal Processo r or Digi tal Signal Processing
DSP viii
Digital-to-Analog
D/A viii
DSP viii
DSP568 00E Reference Manual 2-4
E
Enhanced On-Chip Emulation
EOnCE ix
EOnce ix
Evaluati on Modu le
EVM ix
EVM ix
External oscillator frequency input 2-1
F
FlexCAN ix
FlexCAN Interface Module
FlexCAN ix
FSRAM 2-1, 2-5, 2-6
G
General Purpose Inpu t and Output
GPIO ix
GPIO ix, 2-27
H
Host Parallel Interface Connector 2-11
Host Target Interface 2-11
I
IC ix
Integrated Circuit
IC ix
J
Joint Test Action Group
JTAG ix
JTAG ix, 2-1
JTAG/Enhanced OnCE (EOnCE) 1-1
Jumper Group 1-4
JG1 1-4
JG10 1-4
JG11 1-4
JG12 1-4
JG13 1-4
JG14 1-4
JG15 1-4
JG16 1-4
JG17 1-4
JG18 1-4
JG19 1-4
JG2 1-4
JG3 1-4
JG4 1-4
JG5 1-4
JG6 1-4
JG7 1-4
JG8 1-4
JG9 1-4
MC56F8 367 EVM User Manu al, Rev. 1
Index - 2 Freescale Semiconductor
Preliminary
L
LED ix
Light Emitting Diode
LED ix
Low-profile Quad Flat Package
LQFP ix
LQFP ix
M
MPIO ix, 2-30
Multi Purpose Input and Output
MPIO ix
O
On-board power regulation 2-3
OnCE ix
On-Chi p Emulat i on
OnCE ix
P
Parallel JTAG Host Target Interface 2-1
PCB ix
peripheral port signals 2-17
Phase Locked Loop
PLL ix
PLL ix
Printed Circuit Board
PCB ix
Pulse Width Modulation
PWM ix
PWM ix
PWMA-compatible peripheral 2-2
PWMB-compatible peripheral 2-2
Q
QuadDec ix
Quadrature Decoder
interface port 2-29
QuadDec ix
R
R/C ix
RAM ix
Random Access Memory
RAM ix
Read -Only Memory
ROM ix
real-time debugging 2-10
Resistor/Capacitor Network
R/C ix
ROM ix
RS-232 2-1
level converter 2-7
schematic diagram 2-7
S
SCI ix
SCI/MPIO-compatib le periph eral 2-2
Serial Communications Interface
SCI ix
Serial Peripheral Interface
SPI ix
SPI ix
SPI/MPIO-compatible peripheral 2-2
SRAM ix
external data 2-1
external program 2-1
Static Random Access Memory
SRAM ix
T
Timer- compat ible perip heral 2-2
W
Wait State
WS ix
WS ix
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Freescale™ and the Free scale logo ar e trad emar ks of Freescal e Semico nducto r,
Inc. All other produ ct or service names are the property of the ir respe ctive owners.
This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc. 2004. All righ ts reserved.
MC56F8367EVMUM
Rev. 1
10/2004
