APLUS MAKE YOUR PRODUCTION A-PLUS
ASM0406C
DATA SHEET
APLUS INTEGRATED CIRCUITS INC.
Address:
3 F-10, No. 32, Sec. 1, Chenggung Rd., Taipei,
Taiwan 115, R.O.C.
(115)台北市南港區成功路㆒段 32 號3樓之 10.
TEL: 886-2-2782-9266
FAX: 886-2-2782-9255
WEBSITE : http: //www.aplusinc.com.tw
Sales E-mail: Mr. Jason
sales@aplusinc.com.tw
Technology E-mail: Mr. George
service@aplusinc.com.tw
ASM0406C – VERY LOW-COST VOICE SYNTHESIZER WITH 4-BIT MICROPROCESSOR
1.0 General Description
The ASM0406C is very low cost voice synthesizer with 4-bit microprocessor. It has various
features including 4-bit ALU, ROM, RAM, I/O ports, timers, clock generator, watchdog
timer(WDT), voice synthesizer, etc. It consists of 22 instructions in the device. With CMOS
technology and halt function can minimize power dissipation. Its architecture is similar to RISC,
with two stages of instruction pipeline. It allows all instructions to be executed in a single cycle,
except for program branches and data table read instructions (which need two instruction
cycles).
1.1 Feature
Single power supply can operate from 2.4V through 5V
Internal Program ROM: 4K x 10-bit
1 sets of 15-bit DPR can access up to 16K x 10 bits data memory space
Data Registers:
• 64 x 4-bit data RAM (00-1Fh plus 40h-5Fh)
• Unbanked special function registers (SFR) range: 20h-3Fh
I/O Ports:
• PRA: 4-bit I/O Port A (2Bh)
• PRB: 2-bit Output Port B (2Dh)
On-chip clock generator: Resistive Clock Drive(RM)
Timer: 1
• Timer0: a 9-bit auto-reload timer/counter
Stack: 2-level subroutine nesting
HALT and Release from HALT function to reduce power consumption
Watch Dog Timer (WDT)
Instruction: 1-cycle instruction except for table read and program branches which are 2-cycles
Number of instruction: 22
The Voice function can be implemented by microprocessor instruction
• One 8-bit COUT output for ASMxxxxx
1
ASM0406C
FIGURE 1.1 : Block Diagram of ASM0406C
COUT
OSC
VDD/GND
ROM
1
PC[11:0]
ROM Latch
Instruction
Latch
Instruction
Decoder
0
PCH(8) PCL(4)
PCLATCH(8)
DPR3,2,1 Program
DLATCH(10)
Clock Generator
Power on Reset
Test select
P1,P2,P3,P4
enter test mode
Timer0(9)
Reset Chip
Stack
(
12
)
Data Bus[3:0
]
Instruction Bus [9:0]
ROM_ADDR[14:0]
ROM_Data[9:0]
Data Bus[3:0]
Control Signal
ADDR[14:0]
=000b
(ADDR[14:12])
PRASL(4)
weak or strong
pull-low for PRA,
(Data)
Instruction Bus [9:0]
Instruction Bus [9:0]
( Voice synthesizer )
One-Channel
SRAM
(64 x 4)
40h-5Fh
(2-Level)
ALU(4)
Register(4)
Accumlator
(
4
)
Immediate
(
4
)
DPR[14:0]
RESET pin
Reset Chip
PRA0
00h-1Fh
PRA(4)
PRB(2)
PRB, PRC
COUT
2
ASM0406C
FIGURE 1.2 : External ROM Map of ASM0406C
Data ROM
12bit x 2 STACK
Reset Vector
PC[11:0]
03FFFh(16Kx10-bits)
00FFFh(4K)
00000h-00FFFh
Pro
ram and data ROM
15-bit Data Pointer
00000h
00400h
Reserved for Testing
00080h
00080h-003FFh
00000h-03FFFh
3
ASM0406C
1.2 Pin-Out
ASM0406C Pin-Out
VDD I - Power supply during operation
PRA3-1 I/O STI
Std./O.D.
I/O port with programmable strong pull-low or weak pull-low or
fix-input-floating capability
Output type with standard or Open-Drain output
PRA0/RESET I/O STI
Std./O.D.
I/O port with programmable strong pull-low or weak pull-low or
fix-input-floating capability
Output type with standard or Open-Drain output
Mask option selected as an external RESET pin with weak pull-low capability
OSC I - RM mode Oscillator input
COUT O - Current Output of Audio
GND I - Circuit Ground Potential
TEST O - Enter Test Mode. ( TEST = High )
PRB0-1 O Std./O.D. Output type with standard or Open-Drain output
1.3 Application circuit
4
ASM0406C
1.4 Bonding Diagram
ASM0406C
16K x 10 bit ROM
6
7
8
9
5
4
1
2
3
10
11
CHIP SIZE: X= 1550+80(um) , Y= 1360+80(um)
Substrate must be connected to GND.
ASM0406C Pad Location Chip Size: X= 1550 + 80 (um), Y=1360 + 80 (um)
PAD # PAD Name X Y PAD # PAD Name X Y
1 RA3 -664.92 -275.52 7 TEST 105.44 -600.2
2 RA2 -664.92 -403.64 8 COUT 303.96 -600.2
3 RA1 -662.64 -600.2 9 VDD 683.04 -600.2
4 RA0 -468.24 -600.2 10 RB0 664.92 -399.2
5 OSC -281.04 -600.2 11 RB1 664.92 -280.8
6 GND -111.72 -600.2
5
ASM0406C
X= 1550+80(um)
Y= 1360+80(um)
1.5 DC Characteristics for ASMxxxxx
SYMBOL PARAMETER VDD MIN. TYP. MAX. UNIT CONDITION
VDD OPERATING VOLTAGE 2.4 3 5.0 V depending on Freq.
3 1
Isb STANDBY
5 1
uA 4MHz, RM
in HALT Mode
3 2
Iop
SUPPLY
CURRENT OPERATING 5 7
mA 4MHz, RM
IO Floating
3 3
5 9
Iih INPUT CURRENT
/Internal pull low 5 -5.2
uA
4MHz, RM
in HALT Mode
(IO Ports with weak
pull-high pull-low)
3 -3
Ioh OUTPUT HIGH CURRENT 5 -8
3 7
Iol OUTPUT LOW CURRENT 5 20
3 4
Cout DA CURRENT OUT
(FULL SCALE) 5 5.2
mA
4MHz, RM
(IO ports)
dF/F FREQUENCY
STABILITY -10 10 % Fosc(3v- 2.4v)
Fosc (3v)
dF/F Fosc VARIATION -20 20 % VDD=3V,
Rosc=850k, 4MHz
FIGURE 1.3 : Frequency Range for Rosc in RM mode
Resistor(k ohm) 1200 1000 820 560
3v Freq.(MHz) 2.92 3.51 4.13 7.02
Rosc & Freq.
2.92
3.51
4.13
7.02
0
2
4
6
8
0 200 400 600 800 1000 1200 1400
Rosc k ohm
Freq. MHz
6
ASM0406C