Figure 1. Application with VIN to ground short protection, using optional P-MOSFET sensing
Description
The A8502 is a multi-output white LED driver for small-size
LCD backlighting. It integrates a current-mode boost converter
with internal power switch and two current sinks. The boost
converter can drive up to 24 LEDs, 12 LEDs per string, at
120 mA. The LED sinks can be paralleled together to achieve
even higher LED currents, up to 240 mA. The A8502 can
operate with a single power supply, from 5 to 40 V, which
allows the part to withstand load dump conditions encountered
in automotive systems.
If required, the A8502 can drive an external P-FET to
disconnect the input supply from the system in the event of
a fault. The A8502 provides protection against output short
and overvoltage, open or shorted diode, open or shorted LED
pin, shorted boost switch or inductor, shorted FSET or ISET
resistor, and IC overtemperature. A dual level cycle-by-cycle
current limit function provides soft start and protects the internal
current switch against high current overloads.
The A8502 has a synchronization pin that allows PWM
switching frequencies to be synchronized in the range of
580 kHz to 2.3 MHz. The high switching frequency allows
the A8502 to operate above the AM radio band.
A8502-DS, Rev. 3
Features and Benefits
• AEC-Q100 qualified
Wide input voltage range of 5 to 40 V for start/stop, cold
crank and load dump requirements
• Fully integrated LED current sinks and boost converter
with 60 V DMOS
• Sync function to synchronize boost converter switching
frequency up to 2.3 MHz, allowing operation above the
AM band
• Excellent input voltage transient response
• Single resistor primary OVP minimizes VOUT leakage
• Internal secondary OVP for redundant protection
• LED current of 120 mA per channel
• Drives up to 12 series LEDs in 2 parallel strings
• 0.7% to 0.8% LED to LED matching accuracy
• PWM and analog dimming inputs
• 5000:1 PWM dimming at 200 Hz
• Provides driver for optional external PMOS input
disconnect switch
• Extensive protection against:
Shorted boost switch or inductor
Shorted FSET or ISET resistor
Shorted output
Open or shorted LED pin
Open boost Schottky
Overtemperature (OTP)
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
Package: 16-pin TSSOP with exposed
thermal pad (suffix LP) Applications:
LCD backlighting or LED lighting for:
Automotive infotainment
Automotive cluster
Automotive center stack
Typical Application Circuit
Not to scale
A8502
Continued on the next page…
GATE SW
Q1
D1
L1
CVDD
OVP
VOUT
ROVP COUT
RSC
RADJ
VSENSE
VIN
VDD
PWM/EN
APWM
ISET
FSET/SYNC
AGND PGND
COMP
CPRZ
CZ
LED2
LED1
FAULT
PAD
A8502
120
VC
10 H 2 A / 60 V
137 k
0.033
249
100 k
RISET
8.25 kRFSET
10 k
4.7 F
50 V
CIN
4.7 F
50 V
CC
22 nF
RC
20
0.1 F
0.47 F
120 pF
VIN
10 to 14 V
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8502
2
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Absolute Maximum Ratings*
Characteristic Symbol Notes Rating Unit
LEDx Pins –0.3 to 55 V
OVP Pin –0.3 to 60 V
VIN, VSENSE, GATE Pins VSENSE and GATE pins should not exceed VIN
by more than 0.4 V –0.3 to 40 V
SW Pin Continuous –0.6 to 62 V
t < 50 ns –1.0 V
¯
F
¯
¯
A
¯¯¯
U ¯¯
L
¯
¯
T
¯
Pin -0.3 to 40 V
ISET, FSET, APWM, COMP Pins –0.3 to 5.5 V
All Other Pins –0.3 to 7 V
Operating Ambient Temperature TARange K –40 to 125 ºC
Maximum Junction Temperature TJ(max) 150 ºC
Storage Temperature Tstg –55 to 150 ºC
*Stresses beyond those listed in this table may cause permanent damage to the device. The Absolute Maximum ratings are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Electrical
Characteristics table is not implied. Exposure to Absolute Maximum-rated conditions for extended periods may affect device reliability.
Selection Guide
Part Number Packing*
A8502KLPTR-T 4000 pieces per 13-in. reel
*Contact Allegro® for additional packing options
The A8502 is provided in a 16-pin TSSOP package (suffix LP) with
an exposed pad for enhanced thermal dissipation. It is lead (Pb) free,
with 100% matte tin lead frame plating.
Description (continued)
Table of Contents
Specifications 2
Pin-out Diagram and Terminal List 3
Characteristic Performance 8
Functional Description 11
Enabling the IC 11
Powering up: LED pin short-to-ground check 11
Soft start function 13
Frequency selection 13
Sync 14
LED current setting and LED dimming 15
PWM dimming 15
APWM pin 16
Analog dimming 18
LED short detect 18
Overvoltage protection 18
Boost switch overcurrent protection 21
Input overcurrent protection and
disconnect switch 22
Setting the current sense resistor 23
Input UVLO 23
VDD 23
Shutdown 24
Fault protection during operation 24
Application Information 26
Design Example for Boost Configuration 26
Design Example for SEPIC Configuration 30
Package Outline Drawing 34
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8502
3
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Pin-out Diagram
Terminal List Table
Number Name Function
1 VDD Output of internal LDO; connect a 0.1 F decoupling capacitor between this pin and ground.
2 PGND Power ground for internal DMOS device.
3 OVP Overvoltage Condition (OVP) sense; connect the ROVP resistor from VOUT to this pin to
adjust the overvoltage protection.
4 SW The drain of the internal DMOS switch of the boost converter.
5 GATE Output gate driver pin for external P-channel FET control.
6 VSENSE
Connect this pin to the negative sense side of the current sense resistor RSC. The threshold
voltage is measured as VIN – VSENSE . There is also a fixed current sink to allow for trip
threshold adjustment.
7 VIN Input power to the A8502 as well as the positive input used for current sense resistor.
8¯
F
¯
¯
A
¯¯¯
U ¯¯
L
¯
¯
T
¯
Indicates a fault condition. Connect a 100 k resistor between this pin and the required logic
level voltage. The pin is an open drain type configuration that will be pulled low when a fault
occurs.
9 COMP Output of the error amplifier and compensation node. Connect a series RZ-CZ network from
this pin to ground for control loop compensation.
10 APWM Analog trimming option for dimming. Applying a digital PWM signal to this pin adjusts the
internal ISET current.
11 PWM/EN PWM dimming pin, used to control the LED intensity by using pulse width modulation. Also
used to enable the A8502.
12 FSET/SYNC
Frequency/synchronization pin. A resistor RFSET from this pin to ground sets the switching
frequency. This pin can also be used to synchronize two or more A8502s in the system. The
maximum synchronization frequency is 2.3 MHz.
13 ISET Connect the RISET resistor between this pin and ground to set the 100% LED current.
14 AGND LED signal ground.
15 LED1 Connect the cathode of the LED string to this pin.
16 LED2 Connect the cathode of the LED sring to this pin.
–PAD
Exposed pad of the package providing enhanced thermal dissipation. This pad must be
connected to the ground plane(s) of the PCB with at least 8 vias, directly in the pad.
Thermal Characteristics may require derating at maximum conditions, see application information
Characteristic Symbol Test Conditions* Value Unit
Package Thermal Resistance RJA
On 2-layer PCB, 3 in.
248.5 ºC/W
On 4-layer PCB based on JEDEC standard 34 ºC/W
*Additional thermal information available on the Allegro website
VDD
PGND
OVP
SW
GATE
VSENSE
VIN
FAULT
LED2
LED1
AGND
ISET
FSET/SYNC
PWM/EN
APWM
COMP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PAD
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8502
4
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Functional Block Diagram
VDD
Regulator
UVLO
Internal
Soft Start
Enable
PWM
Thermal
Shutdown
Open/Short
LED Detect
ISET
Fault
LED
Driver
1.235 V
Ref
Driver
Circuit
Internal VCC
Internal VCC
VREF
Internal VCC
VREF
VREF
ISS
ISS
IADJ
GOFF
100 k
AGND
Current
Sense
Input Current
Sense Amplifier
PMOS
Driver
Diode
Open
Sense
OVP
Sense
Oscillator
SW
VIN
FSET/SYNC
COMP
VSENSE
GATE
PWM/EN
APWM
PAD
PGND AGND
ISET
OVP
LED2
LED1
FAULT
AGND
PGND
+
+
+
+
+
Fault
Fault
Fault
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8502
5
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ELECTRICAL CHARACTERISTICS1,2 Valid at VIN = 16 V, TA = 25°C, indicates specifications guaranteed by design and
characterization over the full operating temperature range with TA = TJ = –40°C to 125°C; unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
Input Voltage Specifications
Operating Input Voltage Range3VIN 5 40 V
UVLO Start Threshold VUVLOrise VIN rising 4.35 V
UVLO Stop Threshold VUVLOfall VIN falling 3.90 V
UVLO Hysteresis2VUVLOHYS 300 450 600 mV
Input Currents
Input Quiescent Current IQPWM/EN = VIH ; SW = 2 MHz, no load 5.5 10 mA
Input Sleep Supply Current IQSLEEP VIN = 16 V, VPWMEN = VFSETSYNC = 0 V 2.0 10.0 A
Input Logic Levels (PWM/EN and APWM)
Input Logic Level-Low VIL VIN throughout operating input voltage range 400 mV
Input Logic Level-High VIH VIN throughout operating input voltage range 1.5 V
PWM/EN Pin Open Drain
Pull-down Resistor RPWMEN PWM/EN = 5 V 60 100 140 k
APWM Pull-down Resistor RAPWM PWM/EN = VIH 60 100 140 k
APWM
APWM Frequency2fAPWM VIH = 2 V, VIL = 0 V 20 1000 kHz
Error Amplifier
Open Loop Voltage Gain AVOL 44 48 52 dB
Transconductance gmICOMP = ±10 A 750 990 1220 A/V
Source Current IEA(SRC) VCOMP = 1.5 V –350 A
Sink Current IEA(SINK) VCOMP = 1.5 V 350 A
COMP Pin Pull-down Resistance RCOMP ¯
F
¯
¯
A
¯
U ¯¯
L
¯
¯
T
¯
= 0 2000 
Overvoltage Protection
Overvoltage Threshold VOVP(th) OVP connected to VOUT 7.7 8.1 8.5 V
OVP Sense Current IOVPH 188 199 210 A
OVP Leakage Current IOVPLKG ROVP = 40.2 k, VIN = 16 V, PWM/EN = VIL 0.1 1 A
Secondary Overvoltage Protection VOVP(sec) 53 55 58 V
Boost Switch
Switch On-Resistance RSW ISW = 0.750 A, VIN = 16 V 75 300 600 m
Switch Leakage Current ISWLKG VSW = 16 V, PWM/EN = VIL 0.1 1 A
Switch Current Limit ISW(LIM) 3.0 3.5 4.2 A
Secondary Switch Current Limit2ISW(LIM2)
Higher than ISW(LIM)(max) for all conditions,
device latches when detected 7.00 A
Soft Start Boost Current Limit ISWSS(LIM) Initial soft start current for boost switch 700 mA
Minimum Switch On-Time tSWONTIME 60 85 111 ns
Minimum Switch Off-Time tSWOFFTIME 30 47 68 ns
Continued on the next page…
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8502
6
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Oscillator Frequency
Oscillator Frequency fSW
RFSET = 10 k1.8 2 2.2 MHz
RFSET = 20 k0.9 1 1.1 MHz
RFSET = 35.6 k520 580 640 kHz
FSET/SYNC Pin Voltage VFSET RFSET = 10 k1.00 V
FSET Frequency Range fFSET 580 2500 kHz
Synchronization
Synchronized PWM Frequency fSWSYNC 580 2300 kHz
Synchronization Input
Minimum Off-Time tPWSYNCOFF 150 ns
Synchronization Input
Minimum On-Time tPWSYNCON 150 ns
SYNC Input Logic Voltage
VSYNC(H) FSET/SYNC pin, high level 0.4 V
VSYNC(L) FSET/SYNC pin, low level 2.0 V
LED Current Sinks
LEDx Accuracy ErrLED ISET = 120 A2%
LEDx Matching LEDx ISET = 120 A1%
LEDx Regulation Voltage VLED VLED1 = VLED2 , ISET = 120 A 620 720 820 mV
ISET to ILEDx Current Gain AISET ISET = 120 A 960 980 1000 A/A
ISET Pin Voltage VISET 0.988 1.003 1.018 V
Allowable ISET Current ISET 40 120 A
VLED Short Detect VLEDSC
While LED sinks are in regulation, sensed
from LEDx pin to ground 4.6 5.1 5.6 V
Soft Start LEDx Current ILEDSS
Current through each enabled LEDx pin
during soft start 3.2 mA
Maximum PWM Dimming
Until Off-Time2tPWML
Measured while PWM/EN = low, during
dimming control and internal references
are powered-on (exceeding tPWML results in
shutdown)
32,750 fSW
cycles
Minimum PWM On-Time tPWMH First cycle when powering-up device 0.75 2 s
PWM High to LED-On Delay tdPWM(on)
Time between PWM enable and LED current
reaching 90% of maximum 0.5 1 s
PWM Low to LED-Off Delay tdPWM(off)
Time between PWM enable going low and
LED current reaching 10% of maximum 360 500 ns
ELECTRICAL CHARACTERISTICS1,2 (continued) Valid at VIN = 16 V, TA = 25°C, indicates specifications guaranteed by design
and characterization over the full operating temperature range with TA = TJ = –40°C to 125°C; unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
Continued on the next page…
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8502
7
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ELECTRICAL CHARACTERISTICS1,2 (continued) Valid at VIN = 16 V, TA = 25°C, indicates specifications guaranteed by design
and characterization over the full operating temperature range with TA = TJ = –40°C to 125°C; unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
GATE Pin
GATE Pin Sink Current IGSINK VGS = VIN 104 A
Gate Fault Shutdown Greater than
2X Current2tGFAULT2 3s
Gate Fault Shutdown Greater than
1–2X Current tGFAULT1 10,000 fSW
cycles
Gate Voltage VGS
Gate to source voltage measured when gate
is on –6.7 V
VSENSE Pin
VSENSE Pin Sink Current IADJ 18.8 20.3 21.8 A
VSENSE Trip Point VSENSEtrip1
Measured between VIN and VSENSE,
RADJ = 0 94 104 114 mV
VSENSE 2X Trip2VSENSEtrip2
2X VSENSEtrip , instantaneous shutdown,
RADJ = 0 180 mV
¯
F
¯
¯
A
¯
¯
U ¯¯
L
¯
¯
T
¯
Pin
¯
F
¯
¯
A
¯
U ¯¯
L
¯
¯
T
¯
Pull-Down Voltage VFAULT IFAULT = 1 mA 0.5 V
¯
F
¯
¯
A
¯
U ¯¯
L
¯
¯
T
¯
Pin Leakage Current IFAULTLKG VFAULT = 5 V 1A
Thermal Protection (TSD)
Thermal Shutdown Threshold2TSD Temperature rising 165 ºC
Thermal Shutdown Hysteresis2TSDHYS 20 ºC
1For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing); positive current is defined as
going into the node or pin (sinking).
2Ensured by design and characterization, not production tested.
3Minimum VIN = 5 V is only required at startup. After startup is completed, the IC is able to function down to VIN = 4 V.
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8502
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
-50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 1300-50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 1300
-50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 1300-50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 1300
-50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 1300-50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 1300
7.7
7.6
7.8
7.9
8.0
8.1
8.2
8.3
8.4
VOVP(th) (V)
190
192
194
196
198
200
202
204
206
208
210
IOVPH (μA)
3.60
3.61
3.62
3.63
3.64
3.65
3.66
3.67
3.68
3.69
3.70
1.80
1.85
1.90
1.95
2.00
2.05
2.10
2.15
2.20
f
SW
(MHz)
Switching Frequency
OVP Pin Sense Current OVP Pin Overvoltage Threshold
4.00
4.05
4.10
4.15
4.20
4.25
4.30
4.35
4.40
V
UVLOrise
(V)V
UVLOfall
(V)
0
1
2
3
4
5
6
7
8
9
10
IQSLEEP (μA)
VIN Input Sleep Mode Current
versus Ambient Temperature
VIN UVLO Start Threshold Voltage
VIN UVLO Stop Threshold Voltage
versus Ambient Temperature
versus Ambient Temperature versus Ambient Temperature
versus Ambient Temperature versus Ambient Temperature
Temperature (°C)
Temperature (°C)
Temperature (°C)
Temperature (°C)
Temperature (°C)
Temperature (°C)
Characteristic Performance
TA = TJ
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8502
9
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
-50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 1300-50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 1300
-50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 1300-50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 1300
-50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 1300-50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 1300
3.0
2.5
2.0
1.5
1.0
0.5
0
Err
LED
(%)
LED Current Setpoint Accuracy
-6.9
-6.8
-6.7
-6.6
-6.5
-6.4
-6.3
V
GS
(V)
Input Disconnect Switch
Voltage
Gate to Source
118.2
118.0
117.8
117.6
117.4
117.2
117.0
ILED (mA)
I
SET
= 120 μA
I
SET
= 120 μA
-0.5
-0.3
-0.1
0.1
0.3
0.5
$LEDx (%)
LED to LED Matching Accuracy
960
965
970
975
980
985
990
995
1000
A
ISET
Temperature (°C)
Temperature (°C)
Temperature (°C)
Temperature (°C)
Temperature (°C)
ISET to LED Current Gain versus Ambient Temperature
versus Ambient Temperature
LED Current
versus Ambient Temperature
versus Ambient Temperature
versus Ambient Temperature
20.0
20.1
20.2
20.3
20.4
20.5
20.6
20.7
20.8
IADJ (μA)
VSENSE Pin Sink Current
Temperature (°C)
versus Ambient Temperature
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8502
10
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
100
95
90
85
80
75
70
65
60
Eciency (%)
100
95
90
85
80
75
70
Eciency (%)
Input Voltage, VIN (V)
Eciency for Various LED Conguraons
ILED = 80 mA, LED Vf 3.2 V
Eciency for Various LED Conguraons
ILED = 100 mA, LED Vf 3.2 V
Input Voltage, VIN (V)
5.5 7.0 8.5 10.0 13.0 16.011.5 14.5
5.5 7.0 8.5 10.0 13.0 16.011.5 14.5
2 strings, 6 series LEDs each
2 strings, 7 series LEDs each
2 strings, 8 series LEDs each
2 strings, 6 series LEDs each
2 strings, 7 series LEDs each
2 strings, 8 series LEDs each
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8502
11
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
The A8502 incorporates a current-mode boost controller with
internal DMOS switch, and two LED current sinks. It can be
used to drive two LED strings of up to 12 white LEDs in series,
with current up to 120 mA per string. For optimal efficiency, the
output of the boost stage is adaptively adjusted to the minimum
voltage required to power both LED strings. This is expressed by
the following equation:
VOUT = max ( VLED1 , VLED2 ) + VREG (1)
where
VLEDx is the voltage drop across LED strings 1 and 2, and
VREG is the regulation voltage of the LED current sinks (typi-
cally 0.72 V at the maximum LED current).
Enabling the IC
The IC turns on when a logic high signal is applied on the
PWM/EN pin with a minimum duration of tPWMH for the first
clock cycle, and the input voltage present on the VIN pin is
greater than the 4.35 V necessary to clear the UVLO (VUVLOrise )
threshold. The power-up sequence is shown in figure 2. Before
the LEDs are enabled, the A8502 driver goes through a system
check to determine if there are any possible fault conditions that
might prevent the system from functioning correctly. Also, if the
FSET/SYNC pin is pulled low, the IC will not power-up. More
information on the FSET/SYNC pin can be found in the Sync
section of this datasheet.
Powering up: LED pin short-to-ground check
The VIN pin has a UVLO function that prevents the A8502
from powering-up until the UVLO threshold is reached. After
the VIN pin goes above UVLO, and a high signal is present on
the PWM/EN pin, the IC proceeds to power-up. As shown in
figure 3, at this point the A8502 enables the disconnect switch
and checks if any LEDx pins are shorted to ground and/or are not
used.
The LED detect phase starts when the GATE voltage of the
disconnect switch is equal to VIN – 4.5 V. After the voltage
threshold on the LEDx pins exceeds 120 mV, a delay of between
3000 and 4000 clock cycles is used to determine the status of the
pins. Thus, the LED detection duration varies with the switching
Functional Description
Figure 2. Power-up diagram; shows VDD (ch1, 2 V/div.), FSET/SYNC (ch2,
1 V/div.), ISET (ch3, 1 V/div.), and PWM/EN (ch4, 2 V/div.) pins,
time = 200 s/div.
t
VDD
PWM/EN
FSET/SYNC
ISET
C1
C3
C4
C2
Figure 3. Power-up diagram; shows the relationship of an LEDx pin with
respect to the gate voltage of the disconnect switch (if used) during the
LED detect phase, as well as the duration of the LED detect phase for a
switching frequency of 2 MHz; shows GATE (ch1, 5 V/div.), LED (ch2,
500 mV/div.), ISET (ch3, 1 V/div.), and PWM/EN (ch4, 5 V/div.) pins,
time = 500 s/div.
t
GATE
GATE = VIN – 4.5 V
LED detection period
PWM/EN
LEDx
ISET
C1
C3
C4
C2
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8502
12
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4A. An LED detect occurring when both LED pins are selected to be used;
shows LED1 (ch1, 500 mV/div.), LED2 (ch2, 500 mV/div.), ISET (ch3,
1 V/div.), and PWM/EN (ch4, 5 V/div.) pins, time = 500 s/div.
4B. Example with LED2 pin not being used; the detect voltage is
about 150 mV; shows LED1 (ch1, 500 mV/div.), LED2 (ch2, 500 mV/div.),
ISET (ch3, 1 V/div.), and PWM/EN (ch4, 5 V/div.) pins, time = 500 s/div.
4C. Example with one LED shorted to ground. The IC will not proceed with
power-up until the shorted LED pin is released, at which point the LED is
checked to see if it is being used; shows LED1 (ch1, 500 mV/div.), LED2 (ch2,
500 mV/div.), ISET (ch3, 1 V/div.), and PWM/EN (ch4, 5 V/div.) pins,
time = 1 ms/div.
t
LED detection period
PWM/EN
LED2
LED1
ISET
C1
C3
C4
C2
t
Pin shorted
Short removed
PWM/EN
LED2
LED1
ISET
C1
C3
C4
C2
t
LED detection period
PWM/EN
LED2
LED1
ISET
C1
C3
C4
C2
frequency, as shown in the following table:
Switching Frequency
(MHz)
Detection Time
(ms)
2 1.5 to 2
1 3 to 4
0.800 3.75 to 5
0.600 5 to 6.7
The LED pin detection voltage thresholds are as follows:
LED Pin Voltage LED Pin Status Action
<70 mV Short-to-ground Power-up is halted
150 mV Not used LED removed from operation
325 mV LED pin in use None
All unused pins should be connected with a 1.54 k resistor to
ground, as shown in figure 5. The unused pin, with the pull-down
resistor, will be taken out of regulation at this point and will not
contribute to the boost regulation loop.
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8502
13
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
If a LEDx pin is shorted to ground the A8502 will not proceed
with soft start until the short is removed from the LEDx pin. This
prevents the A8502 from powering-up and putting an uncon-
trolled amount of current through the LEDs.
Soft start function
During soft start the LEDx pins are set to sink (ILEDSS) and the
boost switch current is reduced to the ISWSS(LIM) level to limit
the inrush current generated by charging the output capacitors.
When the converter senses that there is enough voltage on the
LEDx pins the converter proceeds to increase the LED current to
the preset regulation current and the boost switch current limit is
switched to the ISW(LIM) level to allow the A8502 to deliver the
necessary output power to the LEDs. This is shown in figure 6.
Frequency selection
The switching frequency on the boost regulator is set by the resis-
tor connected to the FSET/SYNC pin. The switching frequency
can be can be anywhere from 580 kHz to 2.3 MHz. Figure 7
shows the typical switching frequencies, in MHz, for given resis-
tor values, in k.
In case during operation a fault occurs that will increase the
switching frequency, the FSET/SYNC pin is clamped to a
maximum switching frequency of no more than 3.5 MHz. If the
FSET/SYNC pin is shorted to GND the part will shut down. For
more details see the Fault Mode table later in this datasheet.
Figure 5. Channel select setup: (left) using only channel LED1,
(right) using both channels.
GND
1.54 k
A8502
LED1
LED2
LED1
LED2
GND
A8502
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1
fSW (MHz)
Resistance for RSET (kΩ)
10.0 30.020.012.5 32.522.517.515.0 25.0 35.0
Figure 6. Startup diagram showing the input current, output voltage, and
output current; shows IOUT (ch1, 200 mA/div.), IIN (ch2, 1 A/div.), VOUT
(ch3, 20 V/div.), and PWM/EN (ch4, 5 V/div.), time = 1 ms/div.
Figure 7. Typical Switching Frequency versus value of RFSET resistor.
t
Inrush current caused by
enabling the disconnect
switch (when used) Operation during
ISWSS(lim)
Normal operation
ISW(lim)
PWM/EN
IIN
IOUT
VOUT
C1
C3
C4
C2
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8502
14
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Sync
The A8502 can also be synchronized using an external clock
on the FSET/SYNC pin. Figure 8 shows the correspondence of
a sync signal and the FSET/SYNC pin, and figure 9 shows the
result when a sync signal is detected: the LED current does not
show any variation while the frequency changeover occurs. At
power-up if the FSET/SYNC pin is held low, the IC will not
power-up. Only when the FSET/SYNC pin is tri-stated to allow
the pin to rise, to about 1 V, or when a synchronization clock is
detected, will the A8502 try to power-up.
The basic requirement of the sync signal is 150 ns minimum on-
time and 150 ns minimum off time, as indicated by the specifica-
tions for tPWSYNCON and tPWSYNCOFF
. Figure 10 shows the timing
for a synchronization clock into the A8502 at 2.2 MHz. Thus any
pulse with a duty cycle of 33% to 66% at 2.2 MHz can be used to
synchronize the IC.
The SYNC pulse duty cycle ranges for selected switching fre-
quencies are:
SYNC Pulse Frequency
(MHz)
Duty Cycle Range
(%)
2.2 33 to 66
2 30 to 70
1 15 to 85
0.800 12 to 88
0.600 9 to 91
If during operation a sync clock is lost, the IC will revert to the
preset switching frequency that is set by the resistor RFSET. Dur-
ing this period the IC will stop switching for a maximum period
of about 7 s to allow the sync detection circuitry to switch over
to the externally preset switching frequency.
If the clock is held low for more than 7 s, the A8502 will shut
down. In this shutdown mode the IC will stop switching, the
input disconnect switch is open, and the LEDs will stop sinking
current. To shutdown the IC into low power mode, the user must
disable the IC using the PWM pin, by keeping the pin low for a
period of 32,750 clock cycles. If the FSET/SYNC pin is released
at any time after 7 s, the A8502 will proceed to soft start.
Figure 9. Transition of the SW waveform when the SYNC pulse is
detected. The A8502 switching at 2 MHz, applied SYNC pulse at 1 MHz;
shows VOUT (ch1, 20 V/div.), IOUT (ch2, 200 mA/div.), FSET/SYNC (ch3,
2 V/div.), and SW node (ch4, 20 V/div.), time = 5 s/div.
t
SW node
FSET/SYNC
IOUT
VOUT
C1
C3
C4
C2
Figure 8. Diagram showing a synchronized FSET/SYNC pin and switch
node; shows VOUT (ch1, 20 V/div.), IOUT (ch2, 200 mA/div.), FSET/SYNC
(ch3, 2 V/div.), and SW node (ch4, 20 V/div.), time = 2 s/div.
t
SW node
2 MHz operation 1 MHz operation
FSET/SYNC
IOUT
VOUT
C1
C3
C4
C2
150 ns
150 ns
T = 454 ns
154 ns
t
PWSYNCON
t
PWSYNCOFF
Figure 10. SYNC pulse on and off time requirements.
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8502
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Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
LED current setting and LED dimming
The maximum LED current can be up to 120 mA per channel,
and is set through the ISET pin. To set the ILED current, connect
a resistor, RISET, between this pin and ground, according to the
following formula:
RISET = (1.003 × 980) / ILED (2)
where ILED is in A and RISET is in . This sets the maximum cur-
rent through the LEDs, referred to as the 100% current. Standard
RISET values, at gain equals 980, are as follows:
Standard Closest RISET
Resistor Value
(kΩ)
LED current per LED, ILED
(mA)
8.25 120
9.76 100
12.1 80
15.0 65
PWM dimming
The LED current can be reduced from the 100% current level
by PWM dimming using the PWM/EN pin. When the PWM/EN
pin is pulled high, the A8502 turns on and all enabled LEDs sink
100% current. When PWM/EN is pulled low, the boost converter
and LED sinks are turned off. The compensation (COMP) pin is
floated, and critical internal circuits are kept active. The typical
PWM dimming frequencies fall between 200 Hz and 1 kHz. Fig-
ures 11A to 11D provide examples of PWM switching behavior.
Figure 11A. Typical PWM diagram showing VOUT, ILED, and COMP pin as
well as the PWM signal. PWM dimming frequency is 500 Hz at 50% duty
cycle; shows VOUT (ch1, 10 V/div.), COMP (ch2, 2 V/div.), PWM (ch3,
5 V/div.), and ILED (ch4, 50 mA/div.), time = 500 s/div.
t
ILED
PWM
COMP
VOUT
C1
C3
C4
C2
Figure 11B. Typical PWM diagram showing VOUT, ILED, and COMP pin as
well as the PWM signal. PWM dimming frequency is 500 Hz at 1% duty
cycle ; shows VOUT (ch1, 10 V/div.), COMP (ch2, 2 V/div.), PWM (ch3,
5 V/div.), and ILED (ch4, 50 mA/div.), time = 500 s/div.
Figure 11D. Delay from falling edge of PWM signal to LED current turn off;
shows PWM (ch1, 2 V/div.), and ILED (ch2, 50 mA/div.), time = 200 ns/div.
Figure 11C. Delay from rising edge of PWM signal to LED current; shows
PWM (ch1, 2 V/div.), and ILED (ch2, 50 mA/div.), time = 200 ns/div.
t
ILED
PWM
C1
C2
t
ILED
PWM
COMP
VOUT
C1
C3
C4
C2
t
ILED
PWM
C1
C2
W ide Input Voltage Range, High Ef ficiency
Fault Tolerant LED Driver
A8502
16
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Another important feature of the A8502 is the PWM signal to
LED current delay. This delay is typically less than 500 ns, which
allows greater accuracy at low PWM dimming duty cycles, as
shown in figure 12.
APWM pin
The APWM pin is used in conjunction with the ISET pin (see fig-
ure 13). This is a digital signal pin that internally adjusts the ISET
current. When this pin is not used it should be tied to ground.
The typical input signal frequency is between 20 kHz and 1 MHz.
The duty cycle of this signal is inversely proportional to the per-
centage of current that is delivered to the LEDs (figure 14).
To use this pin for a trim function, the user should set the maxi-
mum output current to a value higher than the required current by
at least 5%. The LED ISET current is then trimmed down to the
appropriate value. Another consideration that also is important
is the limitation of the user APWM signal duty cycle. In some
cases it might be preferable to set the maximum ISET current to be
25% to 50% higher, thus allowing the APWM signal to have duty
cycles that are between 25% and 50%.
Figure 13. Simplified block diagram of the APWM and ISET circuit.
Figure 14. Output current versus duty cycle; 200 kHz APWM signal.
Figure 15. Percentage Error of the LED current versus PWM duty cycle;
200 kHz APWM signal.
APWM
Current
Adjust
ISET
Current
Mirror
LED
Driver
ISET
RISET
PWM
A8502
150
100
50
0
IOUT (mA)
PWM Duty Cycle, D (%)
0406020 80 100
–15
–10
–5
0
PWM Duty Cycle, D (%)
0406020 80 100
ErrLED (%)
10
8
6
4
2
0
ErrLED (%)
PWM Duty Cycle, D (%)
0.1 1 10 100
Worst-case
Typical
Figure 12. Percentage Error of the LED current versus PWM duty cycle
(at 200 Hz PWM frequency).