ATL50/E2 Series
17
Embedded E2 Memory Normal Operations
BYTE MODE SIGNAL BYTEMD: BYTEMD controls if the
E2 will read/write a byte or a word at a time. If BYTEMD is
high, then only 1 byte is read or written to. If BYTEMD is
low, then a 2-byte word will be read or written to. If
BYTEMD is low (word mode) and byte 1 is addressed, then
byte 0 will be active as well. The same applies for bytes 2 &
3, 4 & 5 ..... 62 & 63.
READ: Reads may be byte or words (16 bits) according to
BYTEMD signal. When LOAD is low and READ is high,
rising edge of CLOCK latches address data and data
stored at the memory location determined by the address
pins is asserted on the DOUT[15:0] pins. Read mode is
deactivated when LOAD or BUSY are high.
BYTE WRITE: When WRTLOCK is low and LOAD is high,
rising edge of CLOCK latches address and input data.
Write cycle starts when LOAD falls. The signal CLOCK
may be a free running clock. In that case, LOAD should
change synchronously with CLOCK falling to preclude
inadvertent cases of CLOCK and LOAD momentarily high
together. If CLOCK is static high, then a byte write could
also be accomplished by using LOAD signal alone. In that
case, the address and data are acquired on LOAD rising.
PAGE WRITE: The page write operation of E2 allows 1 to
64 bytes of data to be written into the device during a single
internal programming period. A page write operation is ini-
tiated in the same manner as a byte write. The first byte
written can then be followed by 1 to 63 additional bytes
clock in by CLOCK while holding LOAD high. Data may be
loaded into the data latches in any order within the page
boundary of 64 bytes.
Embedded E2 Memory Test Modes Operations
In test mode (TSTMD = 1)
•The address register is converted into an address
counter and a rising edge on INCR increments the
address.
•CLEAR presets the address counter to 7FFh.
•CLOCK no longer latches address.
•The first INCR rising edge places the address counter at
000h.
READ: While READ and TSTMD is high, clear the address
counter by pulsing CLEAR high. High pulse on INCR incre-
ment the address counter and data stored at the memory
location determined by the address counter is asserted on
the DOUT[15:0] pins.
WRITE: Write Operation in test mode is similar to the nor-
mal write except address is now changed by the INCR
signal. With LOAD low, clear the address counter with a
high pulse of CLEAR. Next, assert LOAD and pulse INCR
to increment address. Then rising edge of CLOCK latches
DIN[15:0]. Subsequent bytes are written by changing DIN,
pulsing INCR and then latching data with CLOCK. Write
cycle starts when LOAD falls. To continue writing following
pages, do not activate CLEAR.
BLOCK WRITE: Block write could be used to set (1’s) or
clear (0’s) the whole E2. While BLKMD is high and BLK-
DAT is valid, assert LOAD. BLKDAT is then acquired on
the rising edge of CLOCK. Write operation begins after
LOAD falls. BLKDAT must be stable while LOAD and
CLOCK are high. CLOCK can be left high always and
block writing can be accomplished using only the LOAD
signal.
EVEN/ODD BLOCK PAGE WRITES: While BLKE/BLKO is
high, assert LOAD. While DIN is valid, pulse CLOCK to
latch in data and continue for a whole page. Write opera-
tion begins after LOAD falls.
Test Mode Pins
Pin Description
BLKMD When high, a block write will be performed.
BLKDAT Data to be written when in the block mode. If in the BLKMD, then make DIN = BLKDAT.
BLKE Enables BLKDAT data to be written to the even pages. Active-high.
BLKO Enables BLKDAT data to be written to the odd pages. Active-high.
TSTMD Converts the address register to an address counter in the TSTMD.
CLEAR Clears the address register when high.
INCR On the rising edge, increments the address when TSTMD is high.
MARGIN Used in the read mode to read the E2 cell with a bias condition. If READ and MARGIN are high, the E2 is in the
read margin mode.
VMARGIN Bias condition used when MARGIN is high.