ICS952703BFLF - Integrated Device Technology

Integrated

Circuit

Systems, Inc.

ICS952703

Preliminary Product Preview

0813B—05/17/05

Pin Configuration

VDDREF 1 48 VDDLAPIC

**FS0/REF0 2 47 IOAPIC1

**FS1/REF1 3 46 IOAPIC0

**Mode/REF2 4 45 GNDAPIC

GNDREF 5 44 VDDSRC

X1 6 43 SRCCLKT

X2 7 42 SRCCLKC

GNDZ 8 41 GND

ZCLK0 9 40 CPUCLKODT1

ZCLK1 10 39 GNDCPU

VDDZ 11 38 CPUCLKODT0

SCLK 12 37 CPUCLKODC0

VDDPCI 13 36 AVDD

*FS2/PCICLK_F0 14 35 AGND

*FS3/PCICLK_F1 15 34 IREF

PCICLK0 16 33 SDATA

PCICLK1 17 32 GNDAGP

GNDPCI 18 31 AGPCLK0

VDDPCI 19 30 AGPCLK1

PCICLK2 20 29 VDDAGP

*(PCI_STO P#)PCICLK3 21 28 AVDD48

*(CPU_STOP#)PCICLK4 22 27 12_48MHz/SEL12_48#MHz*

*(PD#)PCICLK5 23 26 24_48MHz/SEL24_48#MHz**~

GNDPCI 24 25 GND48

48-SSOP

* Internal Pull-Up Resistor

** Internal Pull-Down Resistor

~ This output have 1.5X Drive Strength

ICS952703

Recommended Application:

SiS741 style chipset with 964 South Bridge.

Output Features:

• 1 - Pair of differential open drain CPU outputs

• 1 - Single-ended open drain CPU output

• 1 - Pair of current mode differential serial reference clock

• 8 - PCICLK @ 3.3V including 2 PCI clock free running

• 2 - AGPCLK @ 3.3V

• 3 - REF @ 3.3V

• 2 - ZCLK @ 3.3V

• 2 - IOAPIC @ 2.5V

• 1 - 12_48MHz @ 3.3V

• 1 - 24_48MHz @ 3.3V

Key Specifications:

• CPU Output Jitter <250ps

• AGP Output Jitter <250ps

• ZCLK Output Jitter <250ps

• PCI Output Jitter <500ps

• CPU-AGP/PCI/ZCLK skew: 2.5ns~3.5ns

Programmable Timing Control Hub for K7TM System

Functionality

Features/Benefits:

• Selectable synchronous/asynchronous AGP/PCI

frequency

• Programmable output frequency.

• Programmable output divider ratios.

• Programmable output rise/fall time.

• Programmable output skew.

• Programmable spread percentage for EMI control.

• Watchdog timer technology to reset system

if system malfunctions.

• Programmable watch dog safe frequency.

• Support I2C Index read/write and block read/write

operations.

• Uses external 14.318MHz reference input.

Bit3 Bit2 Bit1 Bit0 CPU SRC ZCLK AGP PCI

FS3 FS2 FS1 FS0 MHz MHz MHz MHz MHz

0 0 0 0 0 200.00 100.00 133.33 66.66 33.33

0 0 0 0 1 200.01 100.00 133.34 66.67 33.33

0 0 0 1 0 200.97 100.00 133.98 66.99 33.49

0 0 0 1 1 190.11 100.00 126.74 63.37 31.69

0 0 1 0 0 100.00 100.00 133.33 66.66 33.33

0 0 1 0 1 100.00 100.00 133.34 66.67 33.33

0 0 1 1 0 100.99 100.00 134.66 67.33 33.66

0 0 1 1 1 95.00 100.00 126.66 63.33 31.67

0 1 0 0 0 166.66 100.00 133.33 66.66 33.33

0 1 0 0 1 166.65 100.00 133.32 66.66 33.33

0 1 0 1 0 161.59 100.00 129.27 64.64 32.32

0 1 0 1 1 151.97 100.00 121.57 60.79 30.39

0 1 1 0 0 133.33 100.00 133.33 66.66 33.33

0 1 1 0 1 133.34 100.00 133.34 66.67 33.33

0 1 1 1 0 133.98 100.00 133.98 66.99 33.49

0 1 1 1 1 126.66 100.00 126.66 63.33 31.67

1 0 0 0 0 206.02 100.00 137.35 68.67 34.34

1 0 0 0 1 210.00 100.00 140.00 70.00 35.00

1 0 0 1 0 214.06 100.00 142.70 71.35 35.68

1 0 0 1 1 217.90 100.00 145.27 72.63 36.32

1 0 1 0 0 103.01 100.00 137.35 68.67 34.34

1 0 1 0 1 105.00 100.00 140.00 70.00 35.00

1 0 1 1 0 106.99 100.00 142.65 71.33 35.66

1 0 1 1 1 109.01 100.00 145.35 72.68 36.34

1 1 0 0 0 164.66 100.00 131.73 65.86 32.93

1 1 0 0 1 167.91 100.00 134.33 67.17 33.58

1 1 0 1 0 171.22 100.00 136.98 68.49 34.24

1 1 0 1 1 174.38 100.00 139.50 69.75 34.88

1 1 1 0 0 137.32 100.00 137.32 68.66 34.33

1 1 1 0 1 140.00 100.00 140.00 70.00 35.00

1 1 1 1 0 142.67 100.00 142.67 71.34 35.67

1 1 1 1 1 145.33 100.00 145.33 72.66 36.33

Bit4

Integrated

Circuit

Systems, Inc.

ICS952703

Preliminary Product Preview

0813B—05/17/05

The ICS952703 is a two chip clock solution for desktop designs using SiS741 style chipsets. When used with a zero delay

buffer such as the ICS9179-16 for PC133 or the ICS93735 for DDR applications it provides all the necessary clocks signals

for such a system.

The ICS952703 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the

first to introduce a whole product line which offers full programmability and flexibility on a single clock device. Employing the

use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the

output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each

individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting

under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment.

General Description

Block Diagram

PLL2 Frequency

Dividers

Programmable

Spread

PLL1

Programmable

Frequency

Dividers

STOP

Logic

ZCLK (1:0)

X2 XTAL

CPU_STOP#

PCI_STOP#

SCLK

SEL24_48MHZ

SEL12_48MHz

PD#

FS (3:0)

MODE

SDATA Control

Logic PCICLK (5:0)

AGPCLK (1:0)

12_48MHZ

24_48MHZ

REF (2:0)

CPUCLKODC0

SRCCLKT

SRCCLKC

CPUCLKODT (1:0)

IOAPIC (1:0)

PCICLKF (1:0)

Integrated

Circuit

Systems, Inc.

ICS952703

Preliminary Product Preview

0813B—05/17/05

Pin Description

PIN # PIN NAME PIN

TYPE DESCRIPTION

1VDDREF PWR Ref, XTAL power supply, nominal 3.3V

2 **FS0/REF0 I/O Frequency select latch input pin / 14.318 MHz reference clock.

3 **FS1/REF1 I/O Frequency select latch input pin / 14.318 MHz reference clock.

4 **Mode/REF2 I/O Function select latch input pin, 0=Desktop Mode, 1=Mobile Mode / Ref clock output.

5 GNDREF PWR Ground pin for the REF outputs.

6 X1 IN Crystal input, Nominally 14.318MHz.

7 X2 OUT Crystal output, Nominally 14.318MHz

8 GNDZ PWR Ground pin for the ZCLK outputs

9 ZCLK0 OUT 3.3V Hyperzip clock output.

10 ZCLK1 OUT 3.3V Hyperzip clock output.

11 VDDZ PWR Power supply for ZCLK clocks, nominal 3.3V

12 SCLK IN Clock pin of I2C circuitry 5V tolerant

13 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V

14 *FS2/PCICLK_F0 I/O Frequency select latch input pin / 3.3V PCI free running clock output.

15 *FS3/PCICLK_F1 I/O Frequency select latch input pin / 3.3V PCI free running clock output.

16 PCICLK0 OUT PCI clock output.

17 PCICLK1 OUT PCI clock output.

18 GNDPCI PWR Ground pin for the PCI outputs

19 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V

20 PCICLK2 OUT PCI clock output.

21 *(PCI_STOP#)PCICLK3 I/O Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low. This

input is activated by the MODE selection pin / PCI clock output.

22 *(CPU_STOP#)PCICLK4 I/O Stops all CPUCLKs besides the CPUCLK_F clocks at logic 0 level, when input low. This

input is activated by the MODE selection pin / PCI clock output.

23 *(PD#)PCICLK5 I/O Asynchronous active low input pin used to power down the device into a low power state /

PCI clock output.

24 GNDPCI PWR Ground pin for the PCI outputs

25 GND48 PWR Ground pin for the 48MHz outputs

26 24_48MHz/SEL24_48#MHz**~ I/O 24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 = 24MHz.

27 12_48MHz/SEL12_48#MHz* I/O 12/48MHz clock output / Latched select input for 12/48MHz output. 0=48MHz, 1 = 12MHz.

28 AVDD48 PWR Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V

29 VDDAGP PWR Power supply for AGP clocks, nominal 3.3V

30 AGPCLK1 OUT AGP clock output

31 AGPCLK0 OUT AGP clock output

32 GNDAGP PWR Ground pin for the AGP outputs

33 SDATA I/O Data pin for I2C circuitry 5V tolerant

34 IREF OUT This pin establishes the reference current for the SRCCLK pairs. This pin requires a fixed

precision resistor tied to ground in order to establish the appropriate current.

35 AGND PWR Analog Ground pin for Core PLL

36 AVDD PWR 3.3V Analog Power pin for Core PLL

37 CPUCLKODC0 OUT "Complememtary" clocks of differential pair CPU outputs. These open drain outputs need

an external 1.5V pull-up.

38 CPUCLKODT0 OUT True clock of differential pair CPU outputs. These open drain outputs need an external

1.5V pull-up.

39 GNDCPU PWR Ground pin for the CPU outputs

40 CPUCLKODT1 OUT True clock of differential pair CPU outputs. These open drain outputs need an external

1.5V pull-up.

41 GND PWR Ground pin.

42 SRCCLKC OUT Complement clock of differential pair for S-ATA support.

+/- 300ppm accuracy required.

43 SRCCLKT OUT True clock of differential pair for S-ATA support.

+/- 300ppm accuracy required.

44 VDDSRC PWR Supply for SRC clocks, 3.3V nominal

45 GNDAPIC PWR Ground pin for the IOAPIC outputs.

46 IOAPIC0 OUT IOAPIC clock outputs, norminal 2.5V.

47 IOAPIC1 OUT IOAPIC clock outputs, norminal 2.5V.

48 VDDLAPIC PWR Power pin for the IOAPIC outputs. 2.5V.

* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ 1.5X Drive Strength

Integrated

Circuit

Systems, Inc.

ICS952703

Preliminary Product Preview

0813B—05/17/05

General SMBus serial interface information for the ICS952703

How to Write:

•Controller (host) sends a start bit.

• Controller (host) sends the write address D2 (H)

• ICS clock will

acknowledge

• Controller (host) sends the begining byte location = N

• ICS clock will

acknowledge

• Controller (host) sends the data byte count = X

• ICS clock will

acknowledge

• Controller (host) starts sending

Byte N through

Byte N + X -1

(see Note 2)

• ICS clock will

acknowledge

each byte

one at a time

• Controller (host) sends a Stop bit

How to Read:

• Controller (host) will send start bit.

• Controller (host) sends the write address D2 (H)

• ICS clock will

acknowledge

• Controller (host) sends the begining byte

location = N

• ICS clock will

acknowledge

• Controller (host) will send a separate start bit.

• Controller (host) sends the read address D3 (H)

• ICS clock will

acknowledge

• ICS clock will send the data byte count = X

• ICS clock sends

Byte N + X -1

• ICS clock sends

Byte 0 through byte X (if X

(H)

was written to byte 8)

• Controller (host) will need to acknowledge each

byte

• Controllor (host) will send a not acknowledge bit

• Controller (host) will send a stop bit

ICS (Slave/Receiver)

WR ACK

ACK

PstoP bit

X Byte

Index Block Writ e Operation

Slave Address D2(H)

Beginning Byte = N

WRite

starT bit

Controller (Host)

Byte N + X - 1

Data Byte Count = X

Beginning Byte N

T starT bit

WR WRite

RT Repeat starT

RD ReaD

Beginning Byte N

Byte N + X - 1

N Not acknowledge

PstoP bit

Slave Address D3(H)

Index Block Read Operation

Slave Address D2(H)

Beginning Byte = N ACK

ACK

Data Byte Count = X

ACK

ICS (Slave/Receiver)

Controller (Host)

X Byte

ACK

Integrated

Circuit

Systems, Inc.

ICS952703

Preliminary Product Preview

0813B—05/17/05

Table1: Frequency Selection Table

Bit3 Bit2 Bit1 Bit0 CPU SRC ZCLK AGP PCI Spread %

FS3 FS2 FS1 FS0 MHz MHz MHz MHz MHz

0 0 0 0 0 200.00 100.00 133.33 66.66 33.33 0.5% down

0 0 0 0 1 200.01 100.00 133.34 66.67 33.33 0.35% center

0 0 0 1 0 200.97 100.00 133.98 66.99 33.49 0.35% center

0 0 0 1 1 190.11 100.00 126.74 63.37 31.69 0.35% center

0 0 1 0 0 100.00 100.00 133.33 66.66 33.33 0.5% down

0 0 1 0 1 100.00 100.00 133.34 66.67 33.33 0.35% center

0 0 1 1 0 100.99 100.00 134.66 67.33 33.66 0.35% center

0 0 1 1 1 95.00 100.00 126.66 63.33 31.67 0.35% center

0 1 0 0 0 166.66 100.00 133.33 66.66 33.33 0.5% down

0 1 0 0 1 166.65 100.00 133.32 66.66 33.33 0.35% center

0 1 0 1 0 161.59 100.00 129.27 64.64 32.32 0.35% center

0 1 0 1 1 151.97 100.00 121.57 60.79 30.39 0.35% center

0 1 1 0 0 133.33 100.00 133.33 66.66 33.33 0.5% down

0 1 1 0 1 133.34 100.00 133.34 66.67 33.33 0.35% center

0 1 1 1 0 133.98 100.00 133.98 66.99 33.49 0.35% center

0 1 1 1 1 126.66 100.00 126.66 63.33 31.67 0.35% center

1 0 0 0 0 206.02 100.00 137.35 68.67 34.34 0.35% center

1 0 0 0 1 210.00 100.00 140.00 70.00 35.00 0.35% center

1 0 0 1 0 214.06 100.00 142.70 71.35 35.68 0.35% center

1 0 0 1 1 217.90 100.00 145.27 72.63 36.32 0.35% center

1 0 1 0 0 103.01 100.00 137.35 68.67 34.34 0.35% center

1 0 1 0 1 105.00 100.00 140.00 70.00 35.00 0.35% center

1 0 1 1 0 106.99 100.00 142.65 71.33 35.66 0.35% center

1 0 1 1 1 109.01 100.00 145.35 72.68 36.34 0.35% center

1 1 0 0 0 164.66 100.00 131.73 65.86 32.93 0.35% center

1 1 0 0 1 167.91 100.00 134.33 67.17 33.58 0.35% center

1 1 0 1 0 171.22 100.00 136.98 68.49 34.24 0.35% center

1 1 0 1 1 174.38 100.00 139.50 69.75 34.88 0.35% center

1 1 1 0 0 137.32 100.00 137.32 68.66 34.33 0.35% center

1 1 1 0 1 140.00 100.00 140.00 70.00 35.00 0.35% center

1 1 1 1 0 142.67 100.00 142.67 71.34 35.67 0.35% center

11111

145.33 100.00 145.33 72.66 36.33 0.35% center

Bit4

Integrated

Circuit

Systems, Inc.

ICS952703

Preliminary Product Preview

0813B—05/17/05

I2C Table: Frequency Select Register

Bit 7 SS_EN Spread Enable RW 1

Bit 6 SEL12_48MHz Output Select RW Latch

Bit 5 SEL24_48MHz Output Select RW Latch

Bit 4 Bit4 Freq Select Bit 4 RW 0

Bit 3 FS3 Freq Select Bit 3 RW Latch

Bit 2 FS2 Freq Select Bit 2 RW Latch

Bit 1 FS1 Freq Select Bit 1 RW Latch

Bit 0 FS0 Freq Select Bit 0 RW Latch

I2C Table: Output Control Register

Bit 7 REF0 Output Control RW 1

Bit 6 REF1 Output Control RW 1

Bit 5 REF2 Output Control RW 1

Bit 4 SRCCLKT/C Output Control RW 1

Bit 3 PCICLK_F0 Output Control RW 1

Bit 2 PCICLK_F1 Output Control RW 1

Bit 1 PCICLK0 Output Control RW 1

Bit 0 PCICLK1 Output Control RW 1

I2C Table: Output Control Register

Bit 7 PCICLK2 Output Control RW 1

Bit 6 PCICLK3 Output Control RW 1

Bit 5 PCICLK4 Output Control RW 1

Bit 4 PCICLK5 Output Control RW 1

Bit 3 24_48MHz Output Control RW 1

Bit 2 12_48MHz Output Control RW 1

Bit 1 AGPCLK1 Output Control RW 1

Bit 0 AGPCLK0 Output Control RW 1

I2C Table: Out

ut Control Re

ister

Bit 7 Reserved Reserved RW 1

Bit 6 Reserved Reserved RW 0

Bit 5 IREF Bit1 RW 1

Bit 4 IREF Bit0 RW 0

Bit 3 Vendor_ID3 RW 0

Bit 2 Vendor_ID2 RW 0

Bit 1 Vendor_ID1 RW 0

Bit 0 Vendor_ID0 RW 1

IREF Mulitiplier

Programming Bits

00 = 5 x Iref 10 = 6 x Iref

01 = 4 x Iref 11 = 7 x Iref

Control Function Type

Name Type

PWD

Pin #

Byte 2

Byte 1 Pin #

Name TypeByte 0 Pin #

Control Function

Name

43,42

Byte 3

TypeControl Function

Control Function

OFF

48MHz

Enable

48MHz

12MHz

24MHz

Enable

Disable

Enable

Disable

Disable Enable

Disable

Enable

Disable Enable

See Table1: Frequency Selection Table

Disable Enable

Disable

Vendor ID

Integrated

Circuit

Systems, Inc.

ICS952703

Preliminary Product Preview

0813B—05/17/05

I2C Table: Output Skew Control Register

Bit 7 PCISkw3 RW 0000:0 0100:150 1000:300 1100:450 X

Bit 6 PCISkw2 RW 0001:N/A 0101:N/A 1001:N/A 1101:600 X

Bit 5 PCISkw1 RW 0010:N/A 0110:N/A 1010:N/A 1110:750 X

Bit 4 PCISkw0 RW 0011:N/A 0111:N/A 1011:N/A 1111:900 X

Bit 3 AGPSkw3 RW 0000:0 0100:150 1000:300 1100:450 X

Bit 2 AGPSkw2 RW 0001:N/A 0101:N/A 1001:N/A 1101:600 X

Bit 1 AGPSkw1 RW 0010:N/A 0110:N/A 1010:N/A 1110:750 X

Bit 0 AGPSkw0 RW 0011:N/A 0111:N/A 1011:N/A 1111:900 X

I2C Table: Output Divider Control Register

Bit 7 ZCLKDiv3 RW 0000:/2 0100:/4 1000:/8 1100:/16 X

Bit 6 ZCLKDiv2 RW 0001:/3 0101:/6 1001:/12 1101:/24 X

Bit 5 ZCLKDiv1 RW 0010:/5 0110:/10 1010:/20 1110:/40 X

Bit 4 ZCLKDiv0 RW 0011:/7 0111:/14 1011:/28 1111:/56 X

Bit 3 AGPDiv3 RW 0000:/2 0100:/4 1000:/8 1100:/16 X

Bit 2 AGPDiv2 RW 0001:/3 0101:/6 1001:/12 1101:/24 X

Bit 1 AGPDiv1 RW 0010:/5 0110:/10 1010:/20 1110:/40 X

Bit 0 AGPDiv0 RW 0011:/7 0111:/14 1011:/28 1111:/56 X

I2C Table: Output Drive Control Register

Bit 7 PCIStr1 RW 1

Bit 6 PCIStr0 RW 1

Bit 5 PCIStr1 RW 1

Bit 4 PCIStr0 RW 1

Bit 3 PCIStr1 RW 1

Bit 2 PCIStr0 RW 1

Bit 1 AGPStr1 RW 1

Bit 0 AGPStr0 RW 1

I2C Table: Reserved Register

Bit 7 Reserved Reserved RW 1

Bit 6 Reserved Reserved RW 1

Bit 5 Reserved Reserved RW 1

Bit 4 Reserved Reserved RW 1

Bit 3 Reserved Reserved RW 1

Bit 2 Reserved Reserved RW 1

Bit 1 Reserved Reserved RW 1

Bit 0 Reserved Reserved RW 1

CPU-AGP 7 Step Skew

Control (ps)

Type

Pin #

Byte 6

NameByte 5 Pin #

Byte 4 Pin # Name

Name

PCICLKF (1:0)

Strength Control

PCICLK (2:0) Strength

Control

PCICLK (5:3) Strength

Control

AGPCLK Strength

Control

TypeName

Type 0 1

Type

PWD

Pin #

Byte 7

Control Function

AGP Divider Ratio

Programmaing Bits

ZCLK Divider Ratio

Programmaing Bits

00 = 0.63X 10 = 0.88X

01 = 0.75X 11 = 1.00X

00 = 0.63X 10 = 0.88X

10 = 0.90X

01 = 0.75X 11 = 1.00X

00 = 0.63X 10 = 0.88X

Control Function

CPU-PCI 7 Step Skew

Control (ps)

01 = 0.80X 11 = 1.00X

01 = 0.75X 11 = 1.00X

00 = 0.70X

Integrated

Circuit

Systems, Inc.

ICS952703

Preliminary Product Preview

0813B—05/17/05

I2C Table: Byte Count Register

Bit 7 BC7 RW 0

Bit 6 BC6 RW 0

Bit 5 BC5 RW 0

Bit 4 BC4 RW 0

Bit 3 BC3 RW 1

Bit 2 BC2 RW 1

Bit 1 BC1 RW 1

Bit 0 BC0 RW 1

I2C Table: WD Time Control & Async Frequency Selection Register

Bit 7 Reserved Reserved RW 0

Bit 6 ASYNC1 RW 0

Bit 5 ASYNC0 RW 0

Bit 4 Reserved Reserved RW 0

Bit 3 WDTCtrl Watch Dog Time base

Control RW 0

Bit 2 WD2 WD Timer Bit 2 RW 1

Bit 1 WD1 WD Timer Bit 1 RW 1

Bit 0 WD0 WD Timer Bit 0 RW 1

Fix PLL Async Freq

Programming bits

See Table 2: Asynchronous Frequency

Selection Table

Type

TypeName

PWDByte 9 Pin # Name

PWDByte 8 Pin #

Byte Count

Programming b(7:0)

Control Function

Control Function 0 1

Reserved Reserved

These bits represent X*290ms (or 1.16S)

the watchdog timer waits before it goes to

alarm mode. Default is 7 X 290ms = 2s.

290ms Base

1160ms Base

Writing to this register will configure how

many bytes will be read back, default is

0F = 15 bytes.

I2C Table: VCO Control Select Bit & WD Timer Control Register

Bit 7 M/NEN M/N Programming

Enable RW 0

Bit 6 WDEN Watchdog Enable RW 0

Bit 5 WDStatus WD Alarm Status R 0

Bit 4 WD SF4 RW 0

Bit 3 WD SF3 RW 0

Bit 2 WD SF2 RW 0

Bit 1 WD SF1 RW 0

Bit 0 WD SF0 RW 0

PWDTypeByte 10 Pin # Control FunctionName

Watch Dog Safe Freq

Programming bits

Writing to these bit will configure the safe

frequency as Byte0 bit (4:0).

Disable

Normal Alarm

Enable

Table 2: Asynchronous Frequency Selection Table

B9 bit6 B9 bit5 SRC ZCL

AGP PCI

0 0 Main PLL Main PLL Main PLL Main PLL

0 1 100 133.33 66.66 33.33

1 0 100 150.00 75 37.5

1 1 100 133.33 80 40

Integrated

Circuit

Systems, Inc.

ICS952703

Preliminary Product Preview

0813B—05/17/05

I2C Table: VCO Frequency Control Register

Bit 7 N Div8 N Divider Prog bit 8 RW X

Bit 6 N Div9 N Divider Prog bit 9 RW X

Bit 5 M Div5 RW X

Bit 4 M Div4 RW X

Bit 3 M Div3 RW X

Bit 2 M Div2 RW X

Bit 1 M Div1 RW X

Bit 0 M Div0 RW X

I2C Table: VCO Frequency Control Register

Bit 7 N Div7 RW X

Bit 6 N Div6 RW X

Bit 5 N Div5 RW X

Bit 4 N Div4 RW X

Bit 3 N Div3 RW X

Bit 2 N Div2 RW X

Bit 1 N Div1 RW X

Bit 0 N Div0 RW X

I2C Table: Spread Spectrum Control Register

Bit 7 SSP7 RW X

Bit 6 SSP6 RW X

Bit 5 SSP5 RW X

Bit 4 SSP4 RW X

Bit 3 SSP3 RW X

Bit 2 SSP2 RW X

Bit 1 SSP1 RW X

Bit 0 SSP0 RW X

I2C Table: Spread Spectrum Control Register

Bit 7 Reserved Reserved R 0

Bit 6 SSP14 RW X

Bit 5 SSP13 RW X

Bit 4 SSP12 RW X

Bit 3 SSP11 RW X

Bit 2 SSP10 RW X

Bit 1 SSP9 RW X

Bit 0 SSP8 RW X

M Divider Programming

bits

PWD

PWDByte 11 Pin # Name

Name

Byte 12 Pin #

Name

Type

N Divider Programming

b(7:0)

Control Function

Byte 13 Pin #

PWD

Byte 14 Pin # Name TypeControl Function

-Spread Spectrum

Programming b(14:8)

Spread Spectrum

Programming b(7:0)

Control Function

TypeControl Function 0 1

The decimal representation of M and N

Divier in Byte 11 and 12 will configure the

VCO frequency. Default at power up =

latch-in or Byte 0 Rom table.

VCO Frequency = 14.318 x [NDiv(9:0)+8]

/ [MDiv(5:0)+2]

These Spread Spectrum bits in Byte 13

and 14 will program the spread

pecentage. It is recommended to use

ICS Spread % table for spread

programming.

These Spread Spectrum bits in Byte 13

and 14 will program the spread

pecentage. It is recommended to use

ICS Spread % table for spread

programming.

The decimal representation of M and N

Divier in Byte 11 and 12 will configure the

VCO frequency. Default at power up =

latch-in or Byte 0 Rom table.

VCO Frequency = 14.318 x [NDiv(9:0)+8]

/ [MDiv(5:0)+2]

Integrated

Circuit

Systems, Inc.

ICS952703

Preliminary Product Preview

0813B—05/17/05

Absolute Maximum Ratings

Stresses above those listed under

Absolute Maximum Ratings

may cause permanent damage to the device. These ratings are stress

specifications only and functional operation of the device at these or any other conditions above those listed in the operational

sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product

reliability.

Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 4.6 V

I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 3.6V

Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V

Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C

Electrical Characteristics - Input/Supply/Common Output Parameters

TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input High Voltage VIH 2V

DD + 0.3 V

Input Low Voltage VIL VSS - 0.3 0.8 V

Input High Current IIH VIN

= VDD 5mA

Input Low Current IIL1 VIN

= 0 V; Inputs with no pull-up resistors -5 mA

Input Low Current IIL2 VIN

= 0 V; Inputs with pull-up resistors -200 mA

Operating Supply

Current IDD(op) CL = 0 pF; Select @ 100MHz 180 mA

Power Down Supply

Current IDDPD

CL = 0 pF; With input address to Vdd or

GND 40 mA

Input frequency FiVDD = 3.3 V; 11 16 MHz

CIN Logic Inputs 5 pF

CINX X1 & X2 pins 27 45 pF

Transition Time1Ttrans To 1st crossing of target Freq. 3 ms

Clk Stabilization1TSTAB From VDD = 3.3 V to 1% target Freq. 3 ms

Skew1TCPU-PCI VT = 1.5 V 1.5 4 ns

1Guaranteed by design, not 100% tested in production.

Input Capacitance1

Integrated

Circuit

Systems, Inc.

ICS952703

Preliminary Product Preview

0813B—05/17/05

Electrical Characteristics - CPUCLKT/C

TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Current Source

Output Impedance Zo1 VO = Vx3000 Ω

Output High Voltage VOH3 IOH = -1 mA 2.4 V

Output Low Voltage VOL3 IOL = 1 mA 0.4

Rise Time tr3 VOL = 0.175V, VOH = 0.525V 175 700 ps

Fall Time tf3 VOH = 0.175V VOL = 0.525V 175 700 ps

Duty Cycle dt3 V

= 50% 45 55 %

Skew tsk3 V

= 50% 100 ps

Jitter, Cycle to cycle t

c-c

c1VT = 50% 150 ps

Electrical Characteristics - PCICLK

TA = 0 - 70°C; VDD = 3.3 V,+/-5%; CL = 30 pF

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output High Voltage VOH1 IOH = -18 mA 2.1 V

Output Low Voltage VOL1 IOL = 9.4 mA 0.4 V

Output High Current IOH1 VOH = 2.0 V -22 mA

Output Low Current IOL1 VOL = 0.8 V 16 57 mA

Rise Time1tr1 VOL = 0.4 V, VOH = 2.4 V 2 ns

Fall Time1tf1 VOH = 2.4 V, VOL = 0.4 V 2 ns

Duty Cycle1dt1 V

= 1.5 V 45 55 %

Skew1tsk1 V

= 1.5 V 500 ps

c-c

c1V

= 1.5 V 500 ps

tjabs1 VT = 1.5 V 500 ps

1Guaranteed by design, not 100% tested in production.

Jitter

Integrated

Circuit

Systems, Inc.

ICS952703

Preliminary Product Preview

0813B—05/17/05

Electrical Characteristics - AGPCLK

TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output Frequency FO1 MHz

Output Impedance RDSP11VO = VD

*(0.5) 12 55 Ω

Output High Voltage VOH1IOH = -1 mA 2.4 V

Output Low Voltage VOL1IOL = 1 mA 0.55 V

Output High Current IOH1V OH@MIN = 1.0 V, V OH@MAX = 3.135 V -33 -33 mA

Output Low Current IOL1VOL @MIN = 1.95 V, VOL @MAX = 0.4 V 30 38 mA

Rise Time tr11VOL = 0.4 V, VOH = 2.4 V 0.5 2 ns

Fall Time tf11VOH = 2.4 V, VOL = 0.4 V 0.5 2 ns

Duty Cycle dt11V

= 1.5 V 45 55 %

Skew tsk11V

= 1.5 V 250 ps

Jitter tjcyc-cyc1VT = 1.5 V 3V66 250 ps

Electrical Characteristics - REF

TA = 0 - 70°C; VDD = 3.3 V , +/-5%; CL = 10 - 20 pF (unless otherwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output High Voltage VOH5 IOH = -12 mA 2.6 V

Output Low Voltage VOL5 IOL = 9 mA 0.4 V

Output High Current IOH5 VOH = 2.0 V -22 mA

Output Low Current IOL5 VOL = 0.8 V 16 mA

Rise Time1tr5 VOL = 0.4 V, VOH = 2.4 V 4 ns

Fall Time1tf5 VOH = 2.4 V, VOL = 0.4 V 4 ns

Duty Cycle1dt5 V

= 1.5 V 45 55 %

c-c

c5 V

= 1.5 V 1000 ps

tjabs5 VT = 1.5 V 800 ps

Jitter1

Integrated

Circuit

Systems, Inc.

ICS952703

Preliminary Product Preview

0813B—05/17/05

Electrical Characteristics - ZCLK

TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output Frequency FO1 MHz

Output Impedance RDSP11VO = VD

*(0.5) 12 55 Ω

Output High Voltage VOH1IOH = -1 mA 2.4 V

Output Low Voltage VOL1IOL = 1 mA 0.55 V

Output High Current IOH1V OH@MIN = 1.0 V, V OH@MAX = 3.135 V -33 -33 mA

Output Low Current IOL1VOL @MIN = 1.95 V, VOL @MAX = 0.4 V 30 38 mA

Rise Time tr11VOL = 0.4 V, VOH = 2.4 V 0.5 2 ns

Fall Time tf11VOH = 2.4 V, VOL = 0.4 V 0.5 2 ns

Duty Cycle dt11V

= 1.5 V 45 55 %

Skew tsk11V

= 1.5 V 250 ps

Jitter tjcyc-cyc1VT = 1.5 V 250 ps

Integrated

Circuit

Systems, Inc.

ICS952703

Preliminary Product Preview

0813B—05/17/05

Fig. 1

Shared Pin Operation -

Input/Output Pins

The I/O pins designated by (input/output) serve as dual

signal functions to the device. During initial power-up, they

act as input pins. The logic level (voltage) that is present on

these pins at this time is read and stored into a 5-bit internal

data latch. At the end of Power-On reset, (see AC

characteristics for timing values), the device changes the

mode of operations for these pins to an output function. In

this mode the pins produce the specified buffered clocks to

external loads.

To program (load) the internal configuration register for these

pins, a resistor is connected to either the VDD (logic 1) power

supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K)

resistor is used to provide both the solid CMOS programming

voltage needed during the power-up programming period and to

provide an insignificant load on the output clock during the

subsequent operating period.

Via to

VDD

Clock trace to load

Series Term. Res.

Programming

Header

Via to Gnd

Device

Pad

2K W

8.2K W

Figure 1 shows a means of implementing this function

when a switch or 2 pin header is used. With no jumper is

installed the pin will be pulled high. With the jumper in

place the pin will be pulled low. If programmability is not

necessary, than only a single resistor is necessary. The

programming resistors should be located close to the series

termination resistor to minimize the current loop area. It is

more important to locate the series termination resistor

close to the driver than the programming resistor.

Integrated

Circuit

Systems, Inc.

ICS952703

Preliminary Product Preview

0813B—05/17/05

The impact of asserting the PCI_STOP# signal will be the following. All PCI and stoppable PCI_F clocks will latch low in their next

high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge.

PCI_STOP#

PCI_F 33MHz

PCI 33MHz

tsu

Assertion of PCI_STOP# Waveforms

PCI_STOP# - Assertion (transition from logic "1" to logic "0")

The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via assertion

of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown. The final state

of the stopped CPU signals is CPUT=Low and CPUC=High. There is to be no change to the output drive current values. The CPUT

will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven.

CPU_STOP# - Assertion (transition from logic "1" to logic "0")

Assertion of CPU_STOP# Waveforms

CPU_STOP# Functionality

#POTS_UPCTUPCCUPC

1lamroNlamroN

0tluM*feritaolF

CPU_STOP#

CPUT

CPUC

Integrated

Circuit

Systems, Inc.

ICS952703

Preliminary Product Preview

0813B—05/17/05

Ordering Information

ICS952703yFLFT

Designation for tape and reel packaging

RoHS Compliant

Package Type

F = SSOP

Revision Designator (will not correlate with datasheet revision)

Device Type

Prefix

ICS = Standard Device

Example:

ICS 95XXXX y F LF - T

INDEX

AREA

INDEX

AREA

1 2

h x 45°

E1 E

SEATING

PLANE

SEATING

PLANE

- C -

.10 (.004) C

MIN MAX MIN MAX

A 2.41 2.80 .095 .110

A1 0.20 0.40 .008 .016

b 0.20 0.34 .008 .0135

c 0.13 0.25 .005 .010

E 10.03 10.68 .395 .420

E1 7.40 7.60 .291 .299

h 0.38 0.64 .015 .025

L 0.50 1.02 .020 .040

α0° 8° 0° 8°

MIN MAX MIN MAX

48 15.75 16.00 .620 .630

10-0034

Reference Doc.: JEDEC Publication 95, MO-118

VARIATIONS

SEE VARIATIONS SEE VARIATIONS

ND mm. D (inch)

SEE VARIATIONS SEE VARIATIONS

0.635 BASIC 0.025 BASIC

SYMBOL

In Millimeters In Inches

COMMON DIMENSIONS COMMON DIMENSIONS

Integrated

Circuit

Systems, Inc.

ICS952703

Preliminary Product Preview

0813B—05/17/05

Revision History

Rev. Issue Date Description Page #

B 5/17/2005 Added LF Ordering Information 16