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Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. HD74LV273A Octal D-type Flip-Flops with Clear REJ03D0330-0300Z (Previous ADE-205-273A (Z)) Rev.3.00 Jun. 25, 2004 Description The HD74LV273A has eight edges trigger D-type flip-flops with clear in a 20-pin package. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear input when low sets all outputs to a low state. Low-voltage and high-speed operation is suitable for batterypowered products (e.g., notebook computers), and the low-power consumption extends the battery life. Features * VCC = 2.0 V to 5.5 V operation * All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) * All outputs VO (Max.) = 5.5 V (@VCC = 0 V) * Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25C) * Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25C) * Output current 6 mA (@VCC = 3.0 V to 3.6 V), 12 mA (@VCC = 4.5 V to 5.5 V) Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD74LV273AFPEL SOP-20 pin (JEITA) FP-20DAV FP EL (2,000 pcs/reel) HD74LV273ARPEL HD74LV273ATELL SOP-20 pin (JEDEC) TSSOP-20 pin FP-20DBV TTP-20DAV RP T EL (1,000 pcs/reel) ELL (2,000 pcs/reel) Note: Please consult the sales office for the above package availability. Function Table Inputs CLR CLK D Output Q L H H H X X H L X L H L Q0 Note: H: High level L: Low level X: Immaterial : Low to high transition : High to low transition Q0: Output level before the indicated steady state input conditions were established. Rev.3.00 Jun. 25, 2004 page 1 of 9 HD74LV273A Pin Arrangement CLR 1 20 VCC 1Q 2 19 8Q 1D 3 18 8D 2D 4 17 7D 2Q 5 16 7Q 3Q 6 15 6Q 3D 7 14 6D 4D 8 13 5D 4Q 9 12 5Q 11 CLK GND 10 (Top view) Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage range Input voltage range*1 Output voltage range*1, 2 VCC VI VO V V V Input clamp current Output clamp current Continuous output current IIK IOK IO Continuous current through VCC or GND ICC or IGND -0.5 to 7.0 -0.5 to 7.0 -0.5 to VCC + 0.5 -0.5 to 7.0 -20 50 25 50 Maximum power dissipation at 3 Ta = 25C (in still air)* PT 835 757 mW Storage temperature Tstg -65 to 150 C mA mA mA mA Conditions Output: H or L VCC: OFF VI < 0 VO < 0 or VO > VCC VO = 0 to VCC SOP TSSOP Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The maximum package power dissipation was calculated using a junction temperature of 150C. Rev.3.00 Jun. 25, 2004 page 2 of 9 HD74LV273A Recommended Operating Conditions Item Symbol Min Max Unit Supply voltage range VCC Input voltage range Output voltage range Output current VI VO IOH 2.0 0 0 -- -- -- -- -- -- -- -- 0 0 0 5.5 5.5 VCC -50 -2 -6 -12 50 2 6 12 200 100 20 V V V A mA -40 85 C IOL Input transition rise or fall rate t /v Operating free-air temperature Ta Conditions A mA ns/V Note: Unused or floating inputs must be held high or low. Logic Diagram 1D CLK 3 11 1D 1Q C1 R CLR 1 To Seven Other Channels Rev.3.00 Jun. 25, 2004 page 3 of 9 2 1Q H or L VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V HD74LV273A DC Electrical Characteristics Ta = -40 to 85C Item Symbol VCC (V) Min Typ Max Unit Input voltage VIH 1.5 VCC x 0.7 VCC x 0.7 VCC x 0.7 -- -- -- -- VCC - 0.1 2.0 2.48 3.8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.5 VCC x 0.3 VCC x 0.3 VCC x 0.3 -- -- -- -- 0.1 0.4 0.44 0.55 1 20 V Input current Quiescent supply current IIN ICC 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 Min to Max 2.3 3.0 4.5 Min to Max 2.3 3.0 4.5 0 to 5.5 5.5 Output leakage current IOFF 0 -- -- Input capacitance CIN 3.3 -- 2 VIL Output voltage VOH VOL Test Conditions A A IOH = -50 A IOH = -2 mA IOH = -6 mA IOH = -12 mA IOL = 50 A IOL = 2 mA IOL = 6 mA IOL = 12 mA VI = 5.5 V or GND VI = VCC or GND, IO = 0 5 A VI or VO = 0 V to 5.5 V -- pF VI = VCC or GND V Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. Rev.3.00 Jun. 25, 2004 page 4 of 9 HD74LV273A Switching Characteristics VCC = 2.5 0.2 V Ta = 25C Ta = -40 to 85C Test Conditions Item Symbol Min Typ Max Min Max Unit Maximum clock frequency fmax 55 45 95 75 -- -- 45 40 -- -- MHz CL = 15 pF CL = 50 pF Propagation delay time th tW 10.3 10.4 13.1 12.9 -- -- -- -- -- 19.0 18.3 22.8 22.1 -- -- -- -- -- 1.0 1.0 1.0 1.0 10.5 4.0 1.0 7.0 8.5 21.0 20.5 25.5 25.0 -- -- -- -- -- CL = 15 pF Hold time Pulse width -- -- -- -- 8.5 4.0 0.5 6.5 7.0 ns Setup time tPHL tPLH/tPHL tPHL tPLH/tPHL tSU CL = 50 pF ns ns ns FROM (Input) TO (Output) CLR Q CLK Q CLR Q CLK Q Data CLR inactive CLR L CLK H or L VCC = 3.3 0.3 V Ta = 25C Ta = -40 to 85C Test Conditions Item Symbol Min Typ Max Min Max Unit Maximum clock frequency fmax 75 50 140 110 -- -- 65 45 -- -- MHz CL = 15 pF CL = 50 pF Propagation delay time th tW 6.9 7.1 8.7 9.1 -- -- -- -- -- 13.6 13.6 17.1 17.1 -- -- -- -- -- 1.0 1.0 1.0 1.0 6.5 2.5 1.0 6.0 6.5 16.0 16.0 19.5 19.5 -- -- -- -- -- CL = 15 pF Hold time Pulse width -- -- -- -- 5.5 2.5 1.0 5.0 5.5 ns Setup time tPHL tPLH/tPHL tPHL tPLH/tPHL tSU CL = 50 pF ns ns ns FROM (Input) TO (Output) CLR Q CLK Q CLR Q CLK Q Data CLR inactive CLR L CLK H or L VCC = 5.0 0.5 V Ta = 25C Ta = -40 to 85C Test Conditions Item Symbol Min Typ Max Min Max Unit Maximum clock frequency fmax 120 80 205 160 -- -- 100 70 -- -- MHz CL = 15 pF CL = 50 pF Propagation delay time th tW 4.7 4.8 6.0 6.2 -- -- -- -- -- 8.5 9.0 10.5 11.0 -- -- -- -- -- 1.0 1.0 1.0 1.0 4.5 2.0 1.0 5.0 5.0 10.0 10.5 12.0 12.5 -- -- -- -- -- CL = 15 pF Hold time Pulse width -- -- -- -- 4.5 2.0 1.0 5.0 5.0 ns Setup time tPHL tPLH/tPHL tPHL tPLH/tPHL tSU Rev.3.00 Jun. 25, 2004 page 5 of 9 CL = 50 pF ns ns ns FROM (Input) TO (Output) CLR Q CLK Q CLR Q CLK Q Data CLR inactive CLR L CLK H or L HD74LV273A Output-skew Characteristics Ta = 25C Ta = -40 to 85C Item Symbol VCC = (V) Min Max Min Max Unit Output skew tsk (O) 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 -- -- -- 2.0 1.5 1.0 -- -- -- 2.0 1.5 1.0 ns Note: Skew between any outputs of the same package switching in the same direction. This parameter is warranted but not production tested. Operating Characteristics CL = 50 pF Ta = 25C Item Symbol VCC = (V) Min Typ Max Unit Test Conditions Power dissipation capacitance CPD 3.3 5.0 -- -- 15.9 17.1 -- -- pF f = 10 MHz Noise Characteristics CL = 50 pF Ta = 25C Item Symbol VCC = (V) Min Typ Max Unit Quiet output, maximum dynamic VOL Quiet output, minimum dynamic VOL VOL (P) 3.3 -- 0.4 0.8 V VOL (V) 3.3 -- -0.4 -0.8 V Quiet output, minimum dynamic VOH VOH (V) 3.3 -- 2.9 -- V High-level dynamic input voltage VIH (D) 3.3 2.31 -- -- V Low-level dynamic input voltage VIL (D) 3.3 -- -- 0.99 V Test Circuit Measurement point CL* Note: C L includes the probe and jig capacitance. Rev.3.00 Jun. 25, 2004 page 6 of 9 Test Conditions HD74LV273A tf tr * Waveform - 1 Timing input 10 % t su 90 % 50 % V CC 90 % 50 % V CC VCC 10 % th 0V VCC Data input 50 % V CC 50 % V CC 0V tw VCC Input 50 % V CC 50 % V CC 0V tf tr * Waveform - 2 10 % Input 90 % 50 % V CC 90 % 50 % V CC VCC 10 % t PHL t PLH 0V VOH 50 % V CC In phase output 50 % V CC VOL t PHL t PLH VOH Out of phase output 50 % V CC 50 % V CC VOL Notes: 1. Input waveform: PRR 1 MHz, Zo = 50 , tr 3 ns, tf 3 ns 2. The output is measured one at a time with one transition per measurement. Rev.3.00 Jun. 25, 2004 page 7 of 9 HD74LV273A Package Dimensions As of January, 2002 Unit: mm 12.6 13 Max 11 1 10 1.27 *0.40 0.06 0.20 7.80 +- 0.30 1.15 0 - 8 0.10 0.10 0.80 Max *0.20 0.05 2.20 Max 5.5 20 0.70 0.20 0.15 0.12 M Package Code JEDEC JEITA Mass (reference value) *Pd plating FP-20DAV -- Conforms 0.31 g As of January, 2003 Unit: mm 12.8 13.2 Max 11 1 10 1.27 *0.40 0.06 0.20 0.10 0.935 Max *0.25 0.05 2.65 Max 7.50 20 0.25 10.40 +- 0.40 1.45 0 - 8 0.57 0.70 +- 0.30 0.15 0.12 M *Ni/Pd/Au plating Rev.3.00 Jun. 25, 2004 page 8 of 9 Package Code JEDEC JEITA Mass (reference value) FP-20DBV Conforms -- 0.52 g HD74LV273A As of January, 2002 Unit: mm 6.50 6.80 Max 11 1 10 4.40 20 0.65 *0.20 0.05 1.0 0.13 M 6.40 0.20 *Pd plating Rev.3.00 Jun. 25, 2004 page 9 of 9 0.07 +0.03 -0.04 0.10 *0.15 0.05 1.10 Max 0.65 Max 0 - 8 0.50 0.10 Package Code JEDEC JEITA Mass (reference value) TTP-20DAV -- -- 0.07 g Sales Strategic Planning Div. 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