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RT
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HV
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LM5104
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LM5104 High-Voltage Half-Bridge Gate Driver With Adaptive Delay
1 Features 3 Description
The LM5104 High-Voltage Gate Driver is designed to
1• Drives Both a High-Side and Low-Side N-Channel drive both the high-side and the low-side N-channel
MOSFET MOSFETs in a synchronous buck configuration. The
• Adaptive Rising and Falling Edges With floating high-side driver can work with supply voltages
Programmable Additional Delay up to 100 V. The high-side and low-side gate drivers
are controlled from a single input. Each change in
• Single Input Control state is controlled in an adaptive manner to prevent
• Bootstrap Supply Voltage Range up to 118-V DC shoot-through issues. In addition to the adaptive
• Fast Turnoff Propagation Delay (25 ns Typical) transition timing, an additional delay time can be
• Drives 1000-pF Loads With 15-ns Rise and Fall added, proportional to an external setting resistor. An
Times integrated high-voltage diode is provided to charge
high-side gate drive bootstrap capacitor. A robust
• Supply Rail Undervoltage Lockout level shifter operates at high speed while consuming
• SOIC and WSON-10 4-mm × 4-mm Package low power and providing clean level transitions from
the control logic to the high-side gate driver.
2 Applications Undervoltage lockout is provided on both the low-side
and the high-side power rails. This device is available
• Current Fed Push-Pull Power Converters in the standard SOIC and the WSON packages.
• High Voltage Buck Regulators
• Active Clamp Forward Power Converters Device Information(1)
• Half-Bridge and Full-Bridge Converters PART NUMBER PACKAGE BODY SIZE (NOM)
SOIC (8) 4.90 mm × 3.91 mm
LM5104 WSON (10) 4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Block Diagram
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5104
SNVS269D –JANUARY 2004–REVISED DECEMBER 2014
www.ti.com
Table of Contents
7.3 Feature Description................................................... 9
1 Features.................................................................. 17.4 Device Functional Modes........................................ 10
2 Applications ........................................................... 18 Application and Implementation ........................ 11
3 Description............................................................. 18.1 Application Information............................................ 11
4 Revision History..................................................... 28.2 Typical Application ................................................. 11
5 Pin Configuration and Functions......................... 39 Power Supply Recommendations...................... 14
6 Specifications......................................................... 49.1 Power Dissipation Considerations .......................... 14
6.1 Absolute Maximum Ratings ...................................... 410 Layout................................................................... 15
6.2 ESD Ratings.............................................................. 410.1 Layout Guidelines ................................................. 15
6.3 Recommended Operating Conditions....................... 410.2 Layout Example .................................................... 16
6.4 Thermal Information.................................................. 411 Device and Documentation Support................. 16
6.5 Electrical Characteristics........................................... 511.1 Trademarks........................................................... 16
6.6 Switching Characteristics.......................................... 611.2 Electrostatic Discharge Caution............................ 16
6.7 Typical Characteristics.............................................. 611.3 Glossary................................................................ 16
7 Detailed Description.............................................. 912 Mechanical, Packaging, and Orderable
7.1 Overview................................................................... 9Information........................................................... 16
7.2 Functional Block Diagram......................................... 9
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (March 2013) to Revision D Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision B (March 2013) to Revision C Page
• Changed layout of National Data Sheet to TI format ........................................................................................................... 11
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VDD
HB
HO
HS
LO
VSS
IN
RT
110
29
38
47
NC NC
56
VDD
HB
HO
HS
LO
VSS
IN
RT
18
27
36
4 5
SOIC-8
LM5104
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SNVS269D –JANUARY 2004–REVISED DECEMBER 2014
5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
DPR Package
10-Pin WSON
Top View
Pin Functions
PIN NAME DESCRIPTION APPLICATION INFORMATION
SOIC WSON
Locally decouple to VSS using ESR/ESL capacitor, located
1 1 VDD Positive gate drive supply as close to IC as possible.
Connect the positive terminal to bootstrap capacitor to the
HB pin and connect negative terminal to HS. The
2 2 HB High-side gate driver bootstrap rail Bootstrap capacitor should be placed as close to IC as
possible
Connect to gate of high-side MOSFET with short low
3 3 HO High-side gate driver output inductance path.
Connect to bootstrap capacitor negative terminal and
4 4 HS High-side MOSFET source connection source of high-side MOSFET.
Resistor from RT to ground programs the deadtime
between high- and low-side transitions. The resistor
5 7 RT Deadtime programming pin should be located close to the IC to minimize noise
coupling from adjacent traces.
Logic 1 equals High-side ON and Low-side OFF. Logic 0
6 8 IN Control input equals High-side OFF and Low-side ON.
7 9 VSS Ground return All signals are referenced to this ground.
Connect to the gate of the low-side MOSFET with a short
8 10 LO Low-side gate driver output low inductance path.
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6 Specifications
6.1 Absolute Maximum Ratings(1)(2)
MIN MAX UNIT
VDD to VSS –0.3 18 V
VHB to VHS –0.3 18 V
IN to VSS –0.3 VDD + 0.3 V
LO Output –0.3 VDD + 0.3 V
HO Output VHS – 0.3 VHB + 0.3 V
VHS to VSS −1 100 V
VHB to VSS 118 V
RT to VSS –0.3 5 V
Junction Temperature 150 °C
Storage temperature range, Tstg –55 150 °C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Recommended Operating Conditions
under which operation of the device is specified. Recommended Operating Conditions do not imply performance limits. For performance
limits and associated test conditions, see Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions MIN MAX UNIT
VDD 9 14 V
HS –1 100 V
HB VHS + 8 VHS + 14 V
HS Slew Rate < 50 V/ns
Junction Temperature –40 125 °C
6.4 Thermal Information LM5104
THERMAL METRIC(1) D DPR UNIT
8 PINS 10 PINS
RθJA Junction-to-ambient thermal resistance 114.5 37.9
RθJC(top) Junction-to-case (top) thermal resistance 61.1 38.1
RθJB Junction-to-board thermal resistance 55.6 14.9 °C/W
ψJT Junction-to-top characterization parameter 9.7 0.4
ψJB Junction-to-board characterization parameter 54.9 15.2
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a 4.4
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
MIN and MAX limits apply over the full operating junction temperature range. Unless otherwise specified, TJ= +25°C, VDD =
VHB = 12 V, VSS = VHS = 0 V, RT = 100kΩ. No Load on LO or HO.
PARAMETER TEST CONDITIONS MIN(1) TYP MAX(1) UNIT
SUPPLY CURRENTS
IDD VDD Quiescent Current LI = HI = 0 V 0.4 0.6 mA
IDDO VDD Operating Current f = 500 kHz 1.9 3 mA
IHB Total HB Quiescent Current LI = HI = 0 V 0.06 0.2 mA
IHBO Total HB Operating Current f = 500 kHz 1.3 3 mA
IHBS HB to VSS Current, Quiescent VHS = VHB = 100 V 0.05 10 µA
IHBSO HB to VSS Current, Operating f = 500 kHz 0.08 mA
INPUT PINS
VIL Low Level Input Voltage Threshold 0.8 1.8 V
VIH High Level Input Voltage Threshold 1.8 2.2 V
RIInput Pulldown Resistance 100 200 500 kΩ
TIME DELAY CONTROLS
VRT Nominal Voltage at RT 2.7 3 3.3 V
IRT RT Pin Current Limit RT = 0 V 0.75 1.5 2.25 mA
TD1 Delay Timer, RT = 10 kΩ58 90 130 ns
TD2 Delay Timer, RT = 100 kΩ140 200 270 ns
UNDER VOLTAGE PROTECTION
VDDR VDD Rising Threshold 6.0 6.9 7.4 V
VDDH VDD Threshold Hysteresis 0.5 V
VHBR HB Rising Threshold 5.7 6.6 7.1 V
VHBH HB Threshold Hysteresis 0.4 V
BOOT STRAP DIODE
VDL Low-Current Forward Voltage IVDD-HB = 100 µA 0.60 0.9 V
VDH High-Current Forward Voltage IVDD-HB = 100 mA 0.85 1.1 V
RDDynamic Resistance IVDD-HB = 100 mA 0.8 1.5 Ω
LO GATE DRIVER
VOLL Low-Level Output Voltage ILO = 100 mA 0.25 0.4 V
VOHL ILO = –100 mA
High-Level Output Voltage 0.35 0.55 V
VOHL = VDD – VLO
IOHL Peak Pullup Current VLO = 0 V 1.6 A
IOLL Peak Pulldown Current VLO = 12 V 1.8 A
HO GATE DRIVER
VOLH Low-Level Output Voltage IHO = 100 mA 0.25 0.4 V
VOHH IHO = –100 mA,
High-Level Output Voltage 0.35 0.55 V
VOHH = VHB – VHO
IOHH Peak Pullup Current VHO = 0 V 1.6 A
IOLH Peak Pulldown Current VHO = 12 V 1.8 A
(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
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8 9 10 11 12 13 14 15 16 17 18
VDD, VHB (V)
0.00
0.20
0.40
0.60
0.80
1.00
1.20
CURRENT (mA)
IDD, RT = 10k
IDD, RT = 100k
IHB, RT = 10k, 100k
110 100 1000
FREQUENCY (kHz)
10
100
CURRENT (mA)
VDD = 12V
RT = 10k
CL = 0 pF
CL = 1000 pF
CL = 4400 pF
CL = 2200 pF
CL = 470 pF
1
0
LM5104
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6.6 Switching Characteristics
MAX limits apply over the full operating junction temperature range. Unless otherwise specified, TJ= +25°C, VDD = VHB = 12
V, VSS = VHS = 0 V, No Load on LO or HO .
PARAMETER TEST CONDITIONS MIN(1) TYP MAX(1) UNIT
tLPHL Lower Turn-Off Propagation Delay 25 56
(IN Rising to LO Falling)
tHPHL Upper Turn-Off Propagation Delay ns
25 56
(IN Falling to HO Falling)
tRC, tFC Either Output Rise/Fall Time CL= 1000 pF 15
tR, tFEither Output Rise/Fall Time (3V to 9V) CL= 0.1 µF 0.6 µs
tBS Bootstrap Diode Turn-Off Time IF= 20 mA, IR= 200 mA 50 ns
(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
6.7 Typical Characteristics
Figure 1. IDD vs Frequency Figure 2. Operating Current vs Temperature
Figure 4. Quiescent Current vs Temperature
Figure 3. Quiescent Current vs Supply Voltage
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-50 -25 0 25 50 75 100 125 150
TEMPERATURE (°C)
6.30
6.40
6.50
6.60
6.70
6.80
6.90
7.00
7.10
7.20
7.30
THRESHOLD (V)
VHBR
VDDR
-50 -25 0 25 50 75 100 125 150
TEMPERATURE (°C)
0.100
0.200
0.300
0.400
0.500
0.600
0.700
VOH (V)
VDD = VHB = 8V
VDD = VHB = 12V
VDD = VHB = 16V
1.00E-06
1.00E-05
1.00E-04
1.00E-03
1.00E-02
1.00E-01
ID (A)
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
VD (V)
T = 25°C
T = -40°C
T = 150°C
-25 0_25 50_75_100_125_150_
TEMPERATURE (oC)
0.30
0.35
0.40
0.45
0.50
0.55
0.60
HYSTERESIS (V)
-50
VHBH
VDDH
0.1 1 10 100 1000
FREQUENCY (kHz)
10
100
1000
10000
100000
CURRENT (PA)
HB = 12V,
HS = 0V
CL = 470 pF
CL = 0 pF
CL = 4400 pF
CL = 2200 pF
CL = 1000 pF
2 4 6 8 10 12
HO, LO (V)
CURRENT (A)
0
SINKING
SOURCING
VDD = VHB = 12V, HS = 0V
0.00
0.20
0.40
0.60
0.80
1.00
1.20
1.40
1.60
1.80
2.00
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SNVS269D –JANUARY 2004–REVISED DECEMBER 2014
Typical Characteristics (continued)
Figure 6. HO & LO Peak Output Current vs Output Voltage
Figure 5. IHB vs Frequency
Figure 8. Undervoltage Threshold Hysteresis vs
Figure 7. Diode Forward Voltage Temperature
Figure 9. Undervoltage Rising Threshold vs Temperature Figure 10. LO and HO Gate Drive—High-Level Output
Voltage vs Temperature
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-50 -25 0 25 50 75 100 125 150
TEMPERATURE (°C)
20
30
40
50
60
70
80
90
100
110
120
TIME (ns)
LO,HO Turn On
Delay (tD)
LO,HO Effective Dead
Time (tP + tRT)
LO,HO Turn Off
Delay (tD)
-50 -25 0 25 50 75 100 125 150
TEMPERATURE (°C)
20
40
60
80
100
120
140
160
180
200
220
TIME (ns)
LO,HO Turn On
Delay (tD)
LO,HO Effective Dead
Time (tP + tRT)
LO,HO Turn Off Delay (tD)
-50 -25 0 25 50 75 100 125 150
TEMPERATURE (°C)
20.0
22.0
24.0
26.0
28.0
30.0
32.0
34.0
36.0
38.0
40.0
DELAY (ns)
THPHL
TLPHL
-50 -25 0 25 50 75 100 125 150
TEMPERATURE (°C)
0.100
0.150
0.200
0.250
0.300
0.350
0.400
VOL (V)
VDD = VHB = 8V
VDD = VHB = 12V
VDD = VHB = 16V
LM5104
SNVS269D –JANUARY 2004–REVISED DECEMBER 2014
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Typical Characteristics (continued)
Figure 11. LO and HO Gate Drive—Low-Level Output Figure 12. Turn Off Propagation Delay vs Temperature
Voltage vs Temperature
Figure 13. Timing vs Temperature RT = 10K Figure 14. Timing vs Temperature RT = 100K
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LO
DRIVER
HO
DRIVER
UVLO
RT
UVLO
IN
VDD
HS
LEVEL
SHIFT
VSS
HV
LM5104
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SNVS269D –JANUARY 2004–REVISED DECEMBER 2014
7 Detailed Description
7.1 Overview
The LM5104 High Voltage gate driver is designed to drive both the high side and the low side N-Channel
MOSFETs in a synchronous buck configuration. The floating high-side driver is capable of working with supply
voltages up to 100 V. The high side and low side gate drivers are controlled from a single input. Each change in
state is controlled in an adaptive manner to prevent shoot-through issues. In addition to the adaptive transition
timing, an additional delay time can be added, proportional to an external setting resistor. An integrated high
voltage diode is provided to charge high side gate drive bootstrap capacitor. A robust level shifter operates at
high speed while consuming low power and providing clean level transitions from the control logic to the high
side gate driver. Under-voltage lockout is provided on both the low side and the high side power rails.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Adaptive Shoot-Through Protection
LM5104 is a high voltage, high speed dual output driver designed to drive top and bottom MOSFET’s connected
in synchronous buck or half-bridge configuration, from one externally provided PWM signal. LM5104 features
adaptive delay to prevent shoot-through current through top and bottom MOSFETs during switching transitions.
Referring to the timing diagram Figure 16, the rising edge of the PWM input (IN) turns off the bottom MOSFET
(LO) after a short propagation delay (tP). An adaptive circuit in the LM5104 monitors the bottom gate voltage (LO)
and triggers a programmable delay generator when the LO pin falls below an internally set threshold (≈Vdd/2).
The gate drive of the upper MOSFET (HO) is disabled until the deadtime expires. The upper gate is enabled
after the TIMER delay (tP+TRT), and the upper MOSFET turns-on. The additional delay of the timer prevents
lower and upper MOSFETs from conducting simultaneously, thereby preventing shoot-through.
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Feature Description (continued)
A falling transition on the PWM signal (IN) initiates the turn-off of the upper MOSFET and turn-on of the lower
MOSFET. A short propagation delay (tP) is encountered before the upper gate voltage begins to fall. Again, the
adaptive shoot-through circuitry and the programmable deadtime TIMER delays the lower gate turn-on time. The
upper MOSFET gate voltage is monitored and the deadtime delay generator is triggered when the upper
MOSFET gate voltage with respect to ground drops below an internally set threshold (≈Vdd/2). The lower gate
drive is momentarily disabled by the timer and turns on the lower MOSFET after the deadtime delay expires
(tP+TRT).
The RT pin is biased at 3V and current limited to 1mA. It is designed to accommodate a resistor between 5K and
100K, resulting in an effective dead-time proportional to RT and ranging from 90ns to 200ns. RT values below 5K
will saturate the timer and are not recommended.
7.3.2 Start-up and UVLO
Both top and bottom drivers include undervoltage lockout (UVLO) protection circuitry which monitors the supply
voltage (VDD) and bootstrap capacitor voltage (VHB – VHS) independently. The UVLO circuit inhibits each driver
until sufficient supply voltage is available to turn-on the external MOSFETs, and the built-in hysteresis prevents
chattering during supply voltage transitions. When the supply voltage is applied to VDD pin of LM5104, the top
and bottom gates are held low until VDD exceeds UVLO threshold, typically about 6.9 V. Any UVLO condition on
the bootstrap capacitor will disable only the high-side output (HO).
7.4 Device Functional Modes
IN Pin LO Pin HO Pin
L H L
H L H
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RGATE
CBOOT
HO
HS
LO
VSS
HB
LM5104 L
(Optional external
fast recovery diode)
IN
VDD
VIN
VCC
PWM
CONTROLLER
GND
VDD
OUT1
OUT2
RT C
LM5104
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SNVS269D –JANUARY 2004–REVISED DECEMBER 2014
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM5104 is one of the latest generation of high-voltage gate drivers which are designed to drive both the
high-side and low-side N-channel MOSFETs in a half-bridge/full bridge configuration or in a synchronous buck
circuit. The floating high-side driver can operate with supply voltages up to 100 V. This allows for N-channel
MOSFET control in half-bridge, full-bridge, push-pull, two switch forward and active clamp topologies.
Table 1. Highlights
FEATURE BENEFIT
Adaptive Rising and Falling Edges with Programmable Additional Allows optimization of gate drive timings to account for device
Delay differences between high-side and low-side positions.
Single Input Control Direct drive from lower cost PWM controllers
Internal Bootstrap Diode Reduces parts count and PCB real estate
8.2 Typical Application
Figure 15. LM5104 Driving MOSFETs Connected in Synchronous Buck Configuration
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BOOT
43.01nc
C
2.2V
=
TOTAL
0.95
Q 43nC 10 A
100kHz
= + m ´
Max
TOTAL gmax HBO
SW
D
Q Q I F
= + ´
TOTAL
BOOT
HB
Q
C
V
=
D
LM5104
SNVS269D –JANUARY 2004–REVISED DECEMBER 2014
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Typical Application (continued)
8.2.1 Design Requirements
PARAMETER VALUE
Gate Driver IC LM5104
Mosfet CSD18531Q5A
VDD 10 V
Qgmax 43 nC
Fsw 200 kHz
DMax 95%
IHBO 10 µA
VDH 1.1 V
VHBR 7.1 V
VHBH 0.4 V
8.2.2 Detailed Design Procedure
ΔVHB = VDD – VDH – VHBL
where
• VDD = Supply voltage of the gate drive IC
• VDH = Bootstrap diode forward voltage drop
• Vgsmin = Minimum gate source threshold voltage (1)
(2)
(3)
The quiescent current of the bootstrap circuit is 10 µA which is negligible compared to the Qgs of the MOSFET.
(4)
QTOTAL = 43.01 nC (5)
In practice the value for the CBOOT capacitor should be greater than that calculated to allow for situations where
the power stage may skip pulse due to load transients. In this circumstance the boot capacitor must maintain the
HB pin voltage above the UVLO voltage for the HB circuit.
As a general rule the local VDD bypass capacitor should be 10 times greater than the value of CBOOT.
VHBL = VHBR – VHBH (6)
VHBL = 6.7 V (7)
ΔVHB = 10 V – 1.1 V – 6.7 V (8)
ΔVHB = 2.2 V (9)
(10)
CBOOT = 19.54 nF (11)
The bootstrap and bias capacitors should be ceramic types with X7R dielectric. The voltage rating should be
twice that of the maximum VDD to allow for loss of capacitance once the devices have a DC bias voltage across
them and to ensure long-term reliability of the devices.
An additional delay turn-on delay can be programmed using an external resistor, RT. Figure 17 shows the
relationship between the turnon delay time and the resistor value for RT.
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75
100
125
150
175
200
RT (k:)
DELAY (ns)
10 20 30 40 50 60 70 80 90 100
VDD = 12V, HB = 12V,
CL = 0, HS = 0
THPLH
TLPLH
LM5104
WAVEFORMS IN
LO
HO
tp+TRT
tp
Td
50%
50%
50%
LM5104
VDD
HB
HS
VSS
IN
RT
Adapt
Logic
Adapt
Logic
DLY
Logic
DLY
Logic
Driver
Driver
HO
LO
tp+TRT
tp
Td
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8.2.3 Application Curves
Figure 16. Application Timing Waveforms
Figure 17. Turn On Delay vs RT Resistor Value
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0.1
_
1.0
_10.0_100.0 1000.0_
SWITCHING FREQUENCY (kHz)
POWER (W)
0.001
0.010
0.100
1.000
CL = 4400 pF
CL = 2200 pF
CL = 0 pF
CL = 470 pF
CL = 1000 pF
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9 Power Supply Recommendations
9.1 Power Dissipation Considerations
The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate
driver losses are related to the switching frequency (f), output load capacitance on LO and HO (CL), and supply
voltage (VDD) and can be roughly calculated as:
PDGATES = 2 • f • CL• VDD2(12)
There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and
HO outputs. The plot in Figure 18 shows the measured gate driver power dissipation versus frequency and load
capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the
power losses driving the output loads and agrees well with Equation 12. This plot can be used to approximate
the power losses due to the gate drivers.
Figure 18. Gate Driver Power Dissipation (LO + HO)
VCC = 12V, Neglecting Diode Losses
The bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the
bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Since each of these
events happens once per cycle, the diode power loss is proportional to frequency. Larger capacitive loads
require more current to recharge the bootstrap capacitor resulting in more losses. Higher input voltages (VIN) to
the half bridge result in higher reverse recovery losses. The following plot was generated based on calculations
and lab measurements of the diode recovery time and current under several operating conditions. This can be
useful for approximating the diode power dissipation.
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10.0 kHz 100.0 kHz 1000.0 kHz
SWITCHING FREQUENCY (kHz)
0.001
0.010
0.100
1.000
POWER (W)
1.0 kHz
CL = 0 pF
CL = 4400 pF
10.0 kHz 100.0 kHz 1000.0 kHz
SWITCHING FREQUENCY (kHz)
0.001
0.010
0.100
1.000
POWER (W)
1.0 kHz
CL = 0 pF
CL = 4400 pF
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SNVS269D –JANUARY 2004–REVISED DECEMBER 2014
Power Dissipation Considerations (continued)
Figure 19. Diode Power Dissipation VIN = 80V Figure 20. Diode Power Dissipation VIN = 40V
The total IC power dissipation can be estimated from the above plots by summing the gate drive losses with the
bootstrap diode losses for the intended application. Because the diode losses can be significant, an external
diode placed in parallel with the internal bootstrap diode (refer to Figure 15) can be helpful in removing power
from the IC. For this to be effective, the external diode must be placed close to the IC to minimize series
inductance and have a significantly lower forward voltage drop than the internal diode.
10 Layout
10.1 Layout Guidelines
The optimum performance of high- and low-side gate drivers cannot be achieved without taking due
considerations during circuit board layout. Following points are emphasized.
1. A low ESR/ESL capacitor must be connected close to the IC, and between VDD and VSS pins and between
HB and HS pins to support high peak currents being drawn from VDD during turnon of the external MOSFET.
2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be
connected between MOSFET drain and ground (VSS).
3. To avoid large negative transients on the switch node (HS) pin, the parasitic inductances in the source of top
MOSFET and in the drain of the bottom MOSFET (synchronous rectifier) must be minimized.
4. Grounding considerations:
– a) The first priority in designing grounding connections is to confine the high peak currents from charging
and discharging the MOSFET gate in a minimal physical area. This will decrease the loop inductance and
minimize noise issues on the gate terminal of the MOSFET. The MOSFETs should be placed as close as
possible to the gate driver.
– b) The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground
referenced bypass capacitor and low-side MOSFET body diode. The bootstrap capacitor is recharged on
the cycle-by-cycle basis through the bootstrap diode from the ground referenced VDD bypass capacitor.
The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length
and area on the circuit board is important to ensure reliable operation.
5. The resistor on the RT pin must be placed very close to the IC and seperated from high current paths to
avoid noise coupling to the time delay generator which could disrupt timer operation.
Copyright © 2004–2014, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LM5104
Q HS
Q LS
LM5104
C VDD
CBOOT
Q HS
Q LS
LM5104
C VDD
CBOOT
LM5104
SNVS269D –JANUARY 2004–REVISED DECEMBER 2014
www.ti.com
10.2 Layout Example
Figure 21. LM5104 Component Placement
11 Device and Documentation Support
11.1 Trademarks
All trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated
Product Folder Links: LM5104
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jan-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM5104M NRND SOIC D 8 95 Non-RoHS
& Green Call TI Call TI -40 to 125 5104
M
LM5104M/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 5104
M
LM5104MX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 5104
M
LM5104SD/NOPB ACTIVE WSON DPR 10 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 5104SD
LM5104SDX/NOPB ACTIVE WSON DPR 10 4500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 5104SD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jan-2021
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM5104MX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM5104SD/NOPB WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5104SDX/NOPB WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Jul-2018
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM5104MX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM5104SD/NOPB WSON DPR 10 1000 210.0 185.0 35.0
LM5104SDX/NOPB WSON DPR 10 4500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Jul-2018
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
10X 0.35
0.25
3 0.1
2.6 0.1
0.8
0.7
8X 0.8
10X 0.5
0.3
(0.1) TYP
2X
3.2
0.05
0.00
B4.1
3.9 A
4.1
3.9
(0.2)
WSON - 0.8 mm max heightDPR0010A
PLASTIC SMALL OUTLINE - NO LEAD
4218856/B 01/2021
PIN 1 INDEX AREA
SEATING PLANE
0.08 C
1
56
10
PIN 1 ID 0.1 C A B
0.05 C
THERMAL PAD
EXPOSED
SEE ALTERNATIVE
LEAD DETAIL
11
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE 3.000
20.000
FULL R
ALTERNATIVE LEAD
DETAIL
BOTTOM VIEW SIDE VIEW
www.ti.com
EXAMPLE BOARD LAYOUT
(R0.05) TYP
8X (0.8)
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
(2.6)
(3.8)
10X (0.3)
10X (0.6)
(3)
( 0.2) VIA
TYP
(1.25)
(1.05)
WSON - 0.8 mm max heightDPR0010A
PLASTIC SMALL OUTLINE - NO LEAD
4218856/B 01/2021
SYMM
1
56
10
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
11
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
SOLDER MASK
OPENING
SOLDER MASK
METAL UNDER
SOLDER MASK
DEFINED
EXPOSED
METAL
METAL
EDGE
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED
METAL
www.ti.com
EXAMPLE STENCIL DESIGN
10X (0.3)
10X (0.6)
8X (0.8)
4X
(1.31)
4X (1.15)
(0.76)
(3.8)
(R0.05) TYP
(0.68)
WSON - 0.8 mm max heightDPR0010A
PLASTIC SMALL OUTLINE - NO LEAD
4218856/B 01/2021
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
77% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
SYMM
1
56
10
SYMM
METAL
TYP
11
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
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