CY7C421
512 × 9 Asynchronous FIFO
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 38-06001 Rev. *K Revised September 14, 2016
512 × 9 Asy nchronous FIFO
Features
■Asynchronous First-In First-Out (FIFO) Buffer Memories
❐512 × 9 (CY7C421)
■Dual-Ported RAM Cell
■High Speed 50 MHz Read and Write Independent of Depth and
Width
■Low Operating Power: ICC = 35 mA
■Empty and Full Flags (Half Full Flag in Standalone)
■TTL Compatible
■Retransmit in Standalone
■Expandable in Width
■PLCC, 7 × 7 TQFP, 300-Mil Molded SOJ
■Pb-free Packages Available
■Pin Compatible and Functionally Equivalent to IDT7201, and
AM7201
Functional Description
The CY7C421 is a first-in first-out (FIFO) memory offered in
300-mil wide SOJ, TQFP & PLCC packages and it is 512 words
by 9 bits wide. Each FIFO memory is organized such that the
data is read in the same sequential order that it was written. Full
and empty flags are provided to prevent overflow and underflow.
Three additional pins are also provided to facilitate unlimited
expansion in width, depth, or both. The depth expansion
technique steers the control signals from one device to another
in parallel. This eliminates the serial addition of propagation
delays, so that throughput is not reduced. Data is steered in a
similar manner.
The read and write operations may be asynchronous; each can
occur at a rate of 50 MHz. The write operation occurs when the
write (W) signal is LOW. Read occurs when read (R) goes LOW.
The nine data outputs go to the high impedance state when R is
HIGH.
A Half Full (HF) output flag that is valid in the standalone and
width expansion configurations is provided. In the depth
expansion configuration, this pin provides the expansion out
(XO) information that is used to tell the next FIFO that it is
activated.
In the standalone and width expansion configurations, a LOW on
the retransmit (RT) input causes the FIFO to retransmit the data.
Read enable (R) and write enable (W) must both be HIGH during
retransmit, and then R is used to access the data.
The CY7C421 is fabricated using an advanced 0.65-micron
P-well CMOS technology. Input ESD protection is greater than
2000 V and latch up is prevented by careful layout and guard
rings.
For a complete list of related documentation, click here.
Selection Guide
512 × 9 -15 -20
Frequency (MHz) 40 33.3
Maximum Access Time (ns) 15 20
ICC1 (mA) 35 35
CY7C421512 × 9 Asynchronous FIFO
CY7C421
Document Number: 38-06001 Rev. *K Page 2 of 22
Logic Block Diagram
RAM ARRAY
512x 9
READ
CONTROL
WRITE
CONTROL
WRITE
POINTER
RESET
LOGIC
EXPANSION
LOGIC
DATA INPUTS
(D0–D 8)
THREE-
STATE
BUFFERS
DATA OUTPUTS
(Q0–Q 8)
W
READ
POINTER
FLAG
LOGIC
R
XI
EF
FF
XO/HF
MR
FL/RT
CY7C421
Document Number: 38-06001 Rev. *K Page 3 of 22
Contents
Pin Configurations ...........................................................4
Pin Definitions ..................................................................5
Maximum Ratings .............................................................6
Operating Range ............................................................... 6
Electrical Characteristics .................................................6
Electrical Characteristics .................................................6
Capacitance ...................................................................... 7
AC Test Loads and Waveforms .......................................7
Switching Characteristics ................................................8
Switching Waveforms ......................................................9
Architecture ....................................................................13
Dual-Port RAM ..........................................................13
Resetting the FIFO ....................................................13
Writing Data to the FIFO ...........................................13
Reading Data from the FIFO .....................................13
Standalone/Width Expansion Modes ........................13
Depth Expansion Mode ............................................. 13
Use of the Empty and Full Flags ...............................14
Ordering Information ...................................................... 15
Ordering Code Definitions ......................................... 15
Package Diagrams .......................................................... 16
Acronyms ........................................................................ 19
Document Conventions ................................................. 19
Units of Measure ....................................................... 19
Document History Page ................................................. 20
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC®Solutions ....................................................... 22
Cypress Developer Community .................................22
Technical Support ..................................................... 22
CY7C421
Document Number: 38-06001 Rev. *K Page 4 of 22
Pin Configurations
Figure 1. 32-pin PLCC/LCC (Top View) Figure 2. 28-pin DIP (Top View) Figure 3. 32-pIn TQFP (Top View)
4 3 2 1 323130
14 15 1617 181920
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
FL/RT
MR
EF
XO/HF
Q
7
D
6
Q
6
D
7
NC
D
2
D
1
D
0
XI
FF
Q
0
Q
1
NC
Q
2
D
D
W
NC
V
D
D
3
8
cc
4
5
Q
Q
GND
NC
R
Q
Q
3
8
4
5
7C421
1
2
3
4
5
6
7
8
9
10
11
12
15
16
17
18
19
20
24
23
22
21
13
14
25
28
27
26
7C421
W
D8
D3
D2
D1
D0
XI
FF
Q0
Q1
Q2
GND
Vcc
D4
FL/RT
MR
EF
XO/HF
Q7
R
Q3
Q8
D5
D6
D7
Q6
Q5
Q4
26
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9 101112131415
32 3130 29 28 27 25
Q1
XI
Q0
D1
D0
NC
NC
FF
D6
D5
D4
VCC
W
D8
D3
D2
D7
FL/RT
NC
NC
MR
EF
XO/HF
Q7
Q2
Q3
Q8
GND
R
Q4
Q5
Q6
16
7C421
CY7C421
Document Number: 38-06001 Rev. *K Page 5 of 22
Pin Definitions
Signal Name Description I/O Function
WWrite Signal I Write into the FIFO
RRead Signal I Read from the FIFO
D0–D8Input Data I Data into the FIFO
Q0–Q8Output Data O Data Out from the FIFO
XI Expansion In I Cascaded: Connected to XO of pervious device
Non-Cascaded: Connected to VCC
XO Expansion Out O Cascaded: Connected to XI of next device
Non-Cascaded: Connected to VCC
HF Half Full Flag O Half-full flag: When HF is LOW, half of the FIFO is full.
FF Full Flag O When FF is LOW, the FIFO is full.
EF Empty Flag O When EF is LOW, the FIFO is empty.
MR Master Reset I FIFO Reset
RT Retransmit I Causes FIFO to retransmit the data
FL First Load I Width expansion: Connected to VCC
Depth expansion: when Gnd indicates that part is first to be loaded all others connected to
VCC
VCC Power I Voltage Supply
GND Ground I Ground
CY7C421
Document Number: 38-06001 Rev. *K Page 6 of 22
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.[1]
Storage Temperature ............................... –65 °C to +150 °C
Ambient Temperature
with Power Applied .................................. –55 °C to +125 °C
Supply Voltage to Ground Potential .............–0.5 V to +7.0 V
DC Voltage Applied to Outputs
in High Z State .............................................–0.5 V to +7.0 V
DC Input Voltage .........................................–0.5 V to +7.0 V
Power Dissipation ........................................................ 1.0 W
Output Current, into Outputs (LOW) ........................... 20 mA
Static Discharge Voltage
(per MIL–STD–883, Method 3015) ......................... > 2000 V
Latch Up Current ...................................................> 200 mA
Operating Range
Range Ambient Temperature[2] VCC
Commercial 0 °C to +70 °C 5 V ± 10%
Industrial –40 °C to +85 °C 5 V ± 10%
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions All Speed Grades Unit
Min Max
VOH Output HIGH Voltage VCC = Min, IOH = –2.0 mA 2.4 – V
VOL Output LOW Voltage VCC = Min, IOL = 8.0 mA – 0.4 V
VIH Input HIGH Voltage Commercial 2.0 VCC V
Industrial 2.2 VCC
VIL Input LOW Voltage [3] 0.8 V
IIX Input Leakage Current GND < VI < VCC –10 +10 μA
IOZ Output Leakage Current R > VIH, GND < VO < VCC –10 +10 μA
IOS Output Short Circuit Current [4] VCC = Max, VOUT = GND – –90 mA
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions -15 -20 Unit
Min Max Min Max
ICC Operating Current VCC = Max, IOUT = 0 mA,
f = fMAX
Commercial – 65 – 55 mA
Industrial – 100 – 90
ICC1 Operating Current VCC = Max, IOUT = 0 mA,
f = 20 MHz
Commercial – 35 – 35 mA
ISB1 Standby Current All Inputs = VIH Min Commercial – 10 – 10 mA
Industrial – 15 – 15
ISB2 Power Down Current All Inputs > VCC – 0.2 VCommercial–5–5mA
Industrial –8–8
Notes
1. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power up.
2. TA is the “instant on” case temperature.
3. VIL(Min) = –2.0 V for pulse durations of less than 20 ns.
4. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
CY7C421
Document Number: 38-06001 Rev. *K Page 7 of 22
Capacitance
Parameter [5] Description Test Conditions Max Unit
CIN Input Capacitance TA = 25 °C, f = 1 MHz, VCC = 4.5 V 6pF
COUT Output Capacitance 6pF
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
3.0 V
5 V
OUTPUT
R1 500 Ω
R2
333Ω
30 pF
INCLUDING
JIGAND
SCOPE
GND
90%
10%
90%
10%
≤3ns ≤3ns
5 V
OUTPUT
R1 500 Ω
R2
333Ω
5pF
INCLUDING
JIGAND
SCOPE
OUTPUT 2 V
Equivalent to: THÉ VENIN EQUIVALENT
(b)(a)
ALL INPUT PULSES
200Ω
Note
5. Tested initially and after any design or process changes that may affect these parameters.
CY7C421
Document Number: 38-06001 Rev. *K Page 8 of 22
Switching Characteristics
Over the Operating Range
Parameter [6] Description -15 -20 Unit
Min Max Min Max
tRC Read Cycle Time 25 –30 –ns
tAAccess Time –15 –20 ns
tRR Read Recovery Time 10 –10 –ns
tPR Read Pulse Width 15 –20 –ns
tLZR[7] Read LOW to Low Z 3 – 3 – ns
tDVR[7, 8] Data Valid after Read HIGH 5 – 5 – ns
tHZR[7, 8] Read HIGH to High Z –15 –15 ns
tWC Write Cycle Time 25 –30 –ns
tPW Write Pulse Width 15 –20 –ns
tHWZ[7] Write HIGH to Low Z 5 – 5 – ns
tWR Write Recovery Time 10 –10 –ns
tSD Data Setup Time 8 – 12 –ns
tHD Data Hold Time 0 – 0 – ns
tMRSC MR Cycle Time 25 –30 –ns
tPMR MR Pulse Width 15 –20 –ns
tRMR MR Recovery Time 10 –10 –ns
tRPW Read HIGH to MR HIGH 15 –20 –ns
tWPW Write HIGH to MR HIGH 15 –20 –ns
tRTC Retransmit Cycle Time 25 –30 –ns
tPRT Retransmit Pulse Width 15 –20 –ns
tRTR Retransmit Recovery Time 10 –10 –ns
tEFL MR to EF LOW –25 –30 ns
tHFH MR to HF HIGH –25 –30 ns
tFFH MR to FF HIGH –25 –30 ns
tREF Read LOW to EF LOW –15 –20 ns
tRFF Read HIGH to FF HIGH –15 –20 ns
tWEF Write HIGH to EF HIGH –15 –20 ns
tWFF Write LOW to FF LOW –15 –20 ns
tWHF Write LOW to HF LOW –15 –20 ns
tRHF Read HIGH to HF HIGH –15 –20 ns
tRAE Effective Read from Write HIGH –15 –20 ns
tRPE Effective Read Pulse Width after EF HIGH 15 –20 –ns
tWAF Effective Write from Read HIGH –15 –20 ns
tWPF Effective Write Pulse Width after FF HIGH 15 –20 –ns
tXOL Expansion Out LOW Delay from Clock –15 –20 ns
tXOH Expansion Out HIGH Delay from Clock –15 –20 ns
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V and output loading of the specified IOL/IOH and 30 pF load capacitance,
as in part (a) of Figure 4 on page 7, unless otherwise specified.
7. tHZR transition is measured at +200 mV from VOL and –200 mV from VOH. tDVR transition is measured at the 1.5V level. tHWZ and tLZR transition is measured at
±100 mV from the steady state.
8. tHZR and tDVR use capacitance loading as in part (b) of Figure 4 on page 7.
CY7C421
Document Number: 38-06001 Rev. *K Page 9 of 22
Switching Waveforms
Figure 5. Asynchronous Read and Write
Figure 6. Master Reset
Figure 7. Half-full Flag
DATA VALIDDATA VALID
DATA VALID DATA VALID
tSD tHD
tRC tPR
tAtRR tA
tLZR tDVR tHZR
tWC
tPW tWR
R
Q0–Q 8
W
D0–D 8
MR
R,W
HF
FF
EF
tMRSC
tPMR
tEFL
tHFH
tFFH
tRPW
tWPW tRMR
[9]
[10]
HALF FULL+1HALF FULL HALF FULL
W
R
HF
tWHF
tRHF
Notes
9. W and R ≥ VIH around the rising edge of MR.
10. tMRSC = tPMR + tRMR.
CY7C421
Document Number: 38-06001 Rev. *K Page 10 of 22
Figure 8. Last Write to First Read Full Flag
Figure 9. Last Read to First Write Empty Flag
Figure 10. Retransmit [11]
Switching Waveforms (continued)
LAST WRITE FIRST READ ADDITIONAL
READS FIRST WRITE
tWFF tRFF
R
W
FF
VALID
LAST READ FIRST WRITE ADDITIONAL
WRITES FIRST READ
VALID
tREF tWEF
tA
W
R
EF
Q0–Q8
tRTC
tPRT
tRTR
FL/RT
R,W
[12]
Notes
11. EF, HF and FF may change state during retransmit as a result of the offset of the read and write pointers, but flags are valid at tRTC.
12. tRTC = tPRT + tRTR.
CY7C421
Document Number: 38-06001 Rev. *K Page 11 of 22
Figure 11. Empty Flag and Read Data Flow-through Mode
Figure 12. Full Flag and Write Data Flow-through Mode
Switching Waveforms (continued)
W
R
EF
D0–D8
Q0–Q8 DATA VALID
tRAE
tREF
tWEF
tHWZ
tA
tRPE
R
W
FF
D0–D8
Q0–Q8
DATA VALID
DATA VALID
tWAF tWPF
tWFF
tRFF
tSD
tHD
tA
CY7C421
Document Number: 38-06001 Rev. *K Page 12 of 22
Figure 13. Expansion Timing Diagrams
Switching Waveforms (continued)
R
W
XO1(XI2)
D0–D 8DATA VALID
DATA DATA
VALID VALID
tXOL tXOH
tHD
tSD tSD
tHD
tXOL
tLZR
tA
tDVR
tXOH
tA
tDVR
tHZR
XO1(XI2)
Q0–Q 8
WRITE TO LAST PHYSICAL
LOCATION OF DEVICE 1 WRITE TO FIRST PHYSICAL
LOCATION OF DEVICE 2
READ FROM LAST PHYSICAL
LOCATION OF DEVICE 1 READ FROM FIRST PHYSICAL
LOCATION OF DEVICE 2
tWR
tRR
DATA VALID
[13]
[13]
Note
13. Expansion Out of device 1 (XO1) is connected to Expansion In of device 2 (XI2).
CY7C421
Document Number: 38-06001 Rev. *K Page 13 of 22
Architecture
The CY7C421 FIFO consist of an array of 512 words of 9 bits
each (implemented by an array of dual-port RAM cells), a read
pointer, a write pointer, control signals (W, R, XI, XO, FL, RT,
MR), and Full, Half Full, and Empty flags.
Dual-Port RAM
The dual-port RAM architecture refers to the basic memory cell
used in the RAM. The cell itself enables the read and write
operations to be independent of each other, which is necessary
to achieve truly asynchronous operation of the inputs and
outputs. A second benefit is that the time required to increment
the read and write pointers is much less than the time required
for data propagation through the memory, which is the case if
memory is implemented using the conventional register array
architecture.
Resetting the FIFO
Upon power up, the FIFO must be reset with a Master Reset
(MR) cycle. This causes the FIFO to enter the empty condition
signified by the Empty flag (EF) being LOW, and both the Half
Full (HF) and Full flags (FF) being HIGH. Read (R) and write (W)
must be HIGH tRPW/tWPW before and tRMR after the rising edge
of MR for a valid reset cycle. If reading from the FIFO after a reset
cycle is attempted, the outputs are in the high impedance state.
Writing Data to the FIFO
The availability of at least one empty location is indicated by a
HIGH FF. The falling edge of W initiates a write cycle. Data
appearing at the inputs (D0–D8) tSD before and tHD after the
rising edge of W are stored sequentially in the FIFO.
The EF LOW-to-HIGH transition occurs tWEF after the first
LOW-to-HIGH transition of W for an empty FIFO. HF goes LOW
tWHF after the falling edge of W following the FIFO actually being
Half Full. Therefore, the HF is active after the FIFO is filled to half
its capacity plus one word. HF remains LOW while less than one
half of total memory is available for writing. The LOW-to-HIGH
transition of HF occurs tRHF after the rising edge of R when the
FIFO goes from half full +1 to half full. HF is available in
standalone and width expansion modes. FF goes LOW tWFF
after the falling edge of W, during the cycle in which the last
available location is filled. Internal logic prevents FIFO overflow.
Writes to a full FIFO are ignored and the write pointer is not
incremented. FF goes HIGH tRFF after a read from a full FIFO.
Reading Data from the FIFO
The falling edge of R initiates a read cycle provided EF is not
LOW. Data outputs (Q0–Q8) are in a high impedance condition
between read operations (R HIGH), when the FIFO is empty, or
when the FIFO is not the active device in the depth expansion
mode.
When one word is in the FIFO, the falling edge of R initiates a
HIGH-to-LOW transition of EF. The rising edge of R causes the
data outputs to go to the high impedance state and remain such
until a write is performed. Reads to an empty FIFO are ignored
and do not increment the read pointer. From the empty condition,
the FIFO can be read tWEF after a valid write.
The retransmit feature is beneficial when transferring packets of
data. It enables the receiver to acknowledge receipt of data and
retransmit, if necessary.
The Retransmit (RT) input is active in the standalone and width
expansion modes. The retransmit feature is intended for use
when a number of writes equal to or less than the depth of the
FIFO have occurred since the last MR cycle. A LOW pulse on RT
resets the internal read pointer to the first physical location of the
FIFO. R and W must both be HIGH for tPRT and tRTR after
retransmit is asserted. With every read cycle after retransmit, the
data from the first physical location of FIFO is read until the read
pointer equals write pointer. Full, Half Full, and Empty flags are
governed by the relative locations of the read and write pointers
and are updated during a retransmit cycle. Data written to the
FIFO after activation of RT are also transmitted. Full depth of
FIFO data can be repeatedly retransmitted.
Standalone/Width Expansion Modes
Standalone and width expansion modes are set by grounding
Expansion In (XI) and tying First Load (FL) to VCC. FIFOs can be
expanded in width to provide word widths greater than nine in
increments of nine. During width expansion mode, all control line
inputs are common to all devices, and flag outputs from any
device can be monitored.
Depth Expansion Mode
Depth expansion mode (see Figure 14 on page 14) is entered
when, during a MR cycle, Expansion Out (XO) of one device is
connected to Expansion In (XI) of the next device, with XO of the
last device connected to XI of the first device. In the depth
expansion mode the First Load (FL) input, when grounded,
indicates that this part is the first to be loaded. All other devices
must have this pin HIGH. To enable the correct FIFO, XO is
pulsed LOW when the last physical location of the previous FIFO
is written to and pulsed LOW again when the last physical
location is read. Only one FIFO is enabled for read and one for
write at any particular time. All other devices are in standby.
FIFOs can also be expanded simultaneously in depth and width.
Consequently, any depth or width FIFO can be created of word
widths in increments of 9. When expanding in depth, a composite
FF must be created by ORing the FFs together. Likewise, a
composite EF is created by ORing the EFs together. HF and RT
functions are not available in depth expansion mode.
CY7C421
Document Number: 38-06001 Rev. *K Page 14 of 22
Use of the Empty and Full Flags
To achieve maximum frequency, the flags must be valid at the
beginning of the next cycle. However, because they can be
updated by either edge of the read or write signal, they must be
valid by one-half of a cycle. Cypress FIFOs meet this
requirement.
The reason for why the flags should be valid by the next cycle is
complex. The “effective pulse width violation” phenomenon can
occur at the full and empty boundary conditions, if the flags are
not properly used. The empty flag must be used to prevent
reading from an empty FIFO and the full flag must be used to
prevent writing into a full FIFO.
For example, consider an empty FIFO that is receiving read
pulses. Because the FIFO is empty, the read pulses are ignored
by the FIFO, and nothing happens. Next, a single word is written
into the FIFO, with a signal that is asynchronous to the read
signal. The (internal) state machine in the FIFO goes from empty
to empty+1. However, it does this asynchronously with respect
to the read signal, so that the effective pulse width of the read
signal cannot be determined, because the state machine does
not look at the read signal until it goes to the empty+1 state.
Similarly, the minimum write pulse width may be violated by
trying to write into a full FIFO, and asynchronously performing a
read. The empty and full flags are used to avoid these effective
pulse width violations, but to do this and operate at the maximum
frequency, the flag must be valid at the beginning of the next
cycle.
Figure 14. Depth Expansion
CY7C421
W
MR
XI
FL
EF
XO
FF
XI
FL
EF
XO
XI
FL
EF
XO
FF
R
EMPTY
FULL
Q
9
9
9
9
FF
VCC
* FIRSTDEVICE
*
9
CY7C421
CY7C421
D
CY7C421
Document Number: 38-06001 Rev. *K Page 15 of 22
Ordering Code Definitions
Ordering Information
Speed
(ns) Ordering Code
Package
Diagram Package Type Operating
Range
15 CY7C421-15AXC 51-85063 32-pin TQFP (Pb-free) Commercial
20 CY7C421-20JXC 51-85002 32-pin PLCC (Pb-free) Commercial
CY7C421-20VXC 51-85031 28-pin (300 Mils) Molded SOJ (Pb-free)
CY7C421
Document Number: 38-06001 Rev. *K Page 16 of 22
Package Diagrams
Figure 15. 32-pin TQFP (7 × 7 × 1.0 mm) A3210 Package Outline, 51-85063
51-85063 *E
CY7C421
Document Number: 38-06001 Rev. *K Page 17 of 22
Figure 16. 32-pin PLCC (0.453 × 0.553 Inches) J32 Package Outline, 51-85002
Package Diagrams (continued)
51-85002 *E
CY7C421
Document Number: 38-06001 Rev. *K Page 18 of 22
Figure 17. 28-pin SOJ (300 Mils) V28.3 (Molded SOJ V21) Package Outline, 51-85031
Package Diagrams (continued)
51-85031 *F
CY7C421
Document Number: 38-06001 Rev. *K Page 19 of 22
Acronyms Document Conventions
Units of Measure
Acronym Description
DIP Dual In-line Package
FIFO First-In First-Out
I/O Input/Output
LCC Leadless Chip Carrier
PLCC Plastic Leaded Chip Carrier
RAM Random Access Memory
SOJ Small Outline J-lead
TQFP Thin Quad Flat Pack
TTL Transistor-Transistor Logic
Symbol Unit of Measure
°C degree Celsius
MHz megahertz
µA microampere
mA milliampere
mm millimeter
mV millivolt
ns nanosecond
% percent
pF picofarad
Vvolt
Wwatt
CY7C421
Document Number: 38-06001 Rev. *K Page 20 of 22
Document History Page
Document Title: CY7C421, 512 × 9 Asynchronous FIFO
Document Number: 38-06001
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
** 106462 SZV 07/11/01 Change from Spec Number: 38-00079 to 38-06001
*A 122332 RBI 12/30/02 Updated Maximum Ratings:
Added Note 1 and referred the same note in “maximum ratings”.
*B 383597 PCX See ECN Added Pb-Free Logo.
Updated Ordering Information (Added the following MPNs:
CY7C419-10JXC, CY7C419-15JXC, CY7C419-15VXC, CY7C421-10JXC,
CY7C421-15AXC, CY7C421-20JXC, CY7C421-20VXC, CY7C425-10AXC,
CY7C425-10JXC, CY7C425-15JXC, CY7C425-20JXC, CY7C425-20VXC,
CY7C429-10AXC, CY7C429-15JXC, CY7C429-20JXC, CY7C433-10AXC,
CY7C433-10JXC, CY7C433-15JXC, CY7C433-20AXC, CY7C433-20JXC).
*C 2623658 VKN /
PYRS
12/17/08 Removed 26-pin CerDIP, 32-pin RLCC, 28-pin molded DIP packages related
information in all instances across the document.
Removed Military Temperature Range related Information in all instances
across the document.
Updated Ordering Information (Added MPN CY7C421-20JXI, removed MPNs
CY7C419/25/29/33).
*D 2714768 VKN /
AESA 06/04/2009 Updated Logic Block Diagram.
Updated Pin Configurations.
Updated Package Diagrams.
*E 2896039 RAME 03/19/2010 Added Contents.
Updated Ordering Information (Removed inactive parts from the data sheet).
Updated Package Diagrams.
Updated Sales, Solutions, and Legal Information (Updated links).
*F 3110157 ADMU 12/14/2010 Added Ordering Code Definitions under Ordering Information.
*G 3324980 ADMU 07/26/2011 Updated title to read as “CY7C421, 512 × 9 Asynchronous FIFO”.
Updated Features.
Updated Functional Description (Removed
CY7C420/424/425/428/429/432/433 related information).
Updated Selection Guide (Removed -10, -25, -30, -40 and -65 speed bins
related information).
Updated Electrical Characteristics (Removed -10, -25, -30, -40 and -65 speed
bins related information).
Updated Switching Characteristics (Removed -10, -25, -30, -40 and -65 speed
bins related information).
Updated Architecture (Removed CY7C420/424/425/428/429/432/433 related
information).
Updated Package Diagrams.
Added Acronyms and Units of Measure.
Updated to new template.
*H 3697624 SMCH 08/07/2012 Added Pin Definitions.
Updated Architecture (Updated Reading Data from the FIFO (Updated
description)).
*I 4082890 SMCH 07/31/2013 Updated Ordering Information (Updated part numbers).
Updated to new template.
Completing Sunset Review.
*J 4581652 SMCH 11/26/2014 Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
CY7C421
Document Number: 38-06001 Rev. *K Page 21 of 22
*K 5436569 NILE 09/14/2016 Updated Package Diagrams:
spec 51-85063 – Changed revision from *D to *E.
spec 51-85002 – Changed revision from *D to *E.
spec 51-85031 – Changed revision from *E to *F.
Updated to new template.
Completing Sunset Review.
Document History Page (continued)
Document Title: CY7C421, 512 × 9 Asynchronous FIFO
Document Number: 38-06001
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
Document Number: 38-06001 Rev. *K Revised September 14, 2016 Page 22 of 22
CY7C421
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