0.1 1 10 100
ISOURCE (mA)
0.01
0.1
1
10
VOUT from V+ (V)
VS = ±15V
125°C
85°C
25°C
-40°C
25V/DIV
5 Ps/DIV
VS = ±15V, AV = +1
INPUT
10 pF
2,200 pF
8,600 pF
12,200 pF
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LM7321x Single and LM7322x Dual Rail-to-Rail Input and Output ±15-V, High-Output
Current and Unlimited Capacitive Load Operational Amplifier
1 Features 3 Description
The LM732xx devices are rail-to-rail input and output
1• (VS= ±15, TA= 25°C, Typical Values Unless amplifiers with wide operating voltages and high-
Specified.) output currents. The LM732xx family is efficient,
• Wide Supply Voltage Range 2.5 V to 32 V achieving 18-V/µs slew rate and 20-MHz unity gain
• Output Current +65 mA/−100 mA bandwidth while requiring only 1 mA of supply current
per op amp. The LM732xx device performance is fully
• Gain Bandwidth Product 20 MHz specified for operation at 2.7 V, ±5 V and ±15 V.
• Slew Rate 18 V/µs The LM732xx devices are designed to drive unlimited
• Capacitive Load Tolerance Unlimited capacitive loads without oscillations. All LM7321x and
• Input Common-Mode Voltage 0.3-V Beyond Rails LM7322x parts are tested at −40°C, 125°C, and
• Input Voltage Noise 15 nV/√Hz 25°C, with modern automatic test equipment. High
performance from −40°C to 125°C, detailed
• Input Current Noise 1.3 pA/√Hz specifications, and extensive testing makes them
• Supply Current/Channel 1.1 mA suitable for industrial, automotive, and
• Distortion THD+Noise −86 dB communications applications.
• Temperature Range −40°C to 125°C Greater than rail-to-rail input common-mode voltage
• Tested at −40°C, 25°C and 125°C at 2.7 V, ±5 V, range with 50 dB of common-mode rejection across
±15 V. this wide voltage range, allows both high-side and
low-side sensing. Most device parameters are
• LM732xx are Automotive Grade Products that are insensitive to power supply voltage, and this makes
AEC-Q100 Grade 1 Qualified. the parts easier to use where supply voltage may
vary, such as automotive electrical systems and
2 Applications battery powered equipment. These amplifiers have
• Driving MOSFETs and Power Transistors true rail-to-rail output and can supply a respectable
amount of current (15 mA) with minimal head- room
• Capacitive Proximity Sensors from either rail (300 mV) at low distortion (0.05%
• Driving Analog Optocouplers THD+Noise).
• High-Side Sensing Device Information(1)
• Below Ground Current Sensing PART NUMBER PACKAGE BODY SIZE (NOM)
• Photodiode Biasing SOIC (8) 4.90 mm × 3.91 mm
LM7321
• Driving Varactor Diodes in PLLs LM7322 SOT (5) 2.90 mm × 1.60 mm
• Wide Voltage Range Power supplies LM7322 VSSOP (8) 3.00 mm × 3.00 mm
• Automotive (1) For all available packages, see the orderable addendum at
• International Power Supplies the end of the data sheet.
Output Swing vs. Sourcing Current Large Signal Step Response
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
8.2 Functional Block Diagram....................................... 20
1 Features.................................................................. 18.3 Feature Description................................................. 20
2 Applications ........................................................... 18.4 Device Functional Modes........................................ 23
3 Description............................................................. 19 Application and Implementation ........................ 25
4 Revision History..................................................... 29.1 Application Information............................................ 25
5 Description continued........................................... 39.2 Typical Application ................................................. 25
6 Pin Configuration and Functions......................... 310 Power Supply Recommendations ..................... 27
7 Specifications......................................................... 411 Layout................................................................... 27
7.1 Absolute Maximum Ratings ..................................... 411.1 Layout Guidelines ................................................. 27
7.2 ESD Ratings.............................................................. 411.2 Layout Example .................................................... 27
7.3 Recommended Operating Conditions....................... 412 Device and Documentation Support................. 28
7.4 Thermal Information.................................................. 412.1 Related Links ........................................................ 28
7.5 2.7-V Electrical Characteristics ............................... 512.2 Community Resources.......................................... 28
7.6 ±5-V Electrical Characteristics................................. 712.3 Trademarks........................................................... 28
7.7 ±15-V Electrical Characteristics............................... 812.4 Electrostatic Discharge Caution............................ 28
7.8 Typical Characteristics............................................ 10 12.5 Glossary................................................................ 28
8 Detailed Description............................................ 20 13 Mechanical, Packaging, and Orderable
8.1 Overview................................................................. 20 Information........................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (March 2013) to Revision E Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision C (May 2008) to Revision D Page
• Changed layout of National Data Sheet to TI format ........................................................................................................... 25
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OUT B
1
2
3
45
6
7
8
OUT A
-IN A
+IN A
V-
V+
-IN B
+IN B
-
+
-
+
A
B
V+
1
2
3
4 5
6
7
8
N/C
-IN
+IN
V-
N/C
OUT
N/C
-
+
OUT
V-
+IN
V+
-IN
1
2
3
5
4
-
+
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SNOSAW8E –MAY 2008–REVISED SEPTEMBER 2015
5 Description continued
There are several package options for each part. Standard SOIC versions of both parts make upgrading existing
designs easy. LM7322x are offered in a space-saving 8-Pin VSSOP package. The LM7321x are offered in small
SOT-23 package, which makes it easy to place this part close to sensors for better circuit performance.
6 Pin Configuration and Functions
DBV Package D Package
5-Pin SOT-23 8-Pin SOIC
Top View Top View
DGK Package
8-Pin VSSOP or SOIC
Top View
Pin Functions
PIN I/O DESCRIPTION
SOT-23 VSSOP,
NAME SOIC NO.
NO. SOIC NO.
OUT 1 6 — O Output
OUT A — — 1 O Output for Amplifier A
OUT B — — 7 O Output for Amplifier B
V+ 5 7 7 P Positive Supply
V– 2 4 4 P Negative Supply
+IN 3 3 — I Noninverting Input
–IN 4 2 — I Inverting Input
+IN A — — 3 I Noninverting Input for Amplifier A
–IN A — — 2 I Inverting Input for Amplifier A
+IN B — — 5 I Noninverting Input for Amplifier B
–IN B — — 6 I Inverting Input for Amplifier B
N/C — 1, 5, 8 — — No connection
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
VIN Differential ±10 V
Output Short Circuit Current See (3)
Supply Voltage (VS= V+- V−) 35 V
Voltage at Input/Output pins V++ 0.8 V−−0.8 V
Junction Temperature(4) 150 °C
Soldering Infrared or Convection (20 sec.) 235 °C
Information: Wave Soldering (10 sec.) 260 °C
Storage Temperature −65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C. Short circuit test is a momentary test. Output short circuit duration is
infinite for VS≤6V at room temperature and below. For VS> 6V, allowable short circuit duration is 1.5 ms.
(4) The maximum power dissipation is a function of TJ(MAX), RθJA. The maximum allowable power dissipation at any ambient temperature is
PD= (TJ(MAX)) – TA)/ RθJA. All numbers apply for packages soldered directly onto a PCB.
7.2 ESD Ratings VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(2) ±2000
Charged-device model (CDM), per JEDEC specification JESD22-
V(ESD) Electrostatic discharge(1) ±1000 V
C101(3)
Machine Model 200
(1) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions MIN MAX UNIT
Supply Voltage (VS= V+- V−) 2.5 32 V
Temperature Range(1) −40 125 °C
(1) The maximum power dissipation is a function of TJ(MAX), RθJA. The maximum allowable power dissipation at any ambient temperature is
PD= (TJ(MAX)) – TA)/ RθJA. All numbers apply for packages soldered directly onto a PCB.
7.4 Thermal Information LM7321
THERMAL METRIC(1) D (SOIC) DBV (SOT) DGK (VSSOP) UNIT
8 PINS 5 PINS 8 PINS
RθJA(2) Junction-to-ambient thermal resistance 165 325 235 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) The maximum power dissipation is a function of TJ(MAX), RθJA. The maximum allowable power dissipation at any ambient temperature is
PD= (TJ(MAX)) – TA)/ RθJA. All numbers apply for packages soldered directly onto a PCB.
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7.5 2.7-V Electrical Characteristics
Unless otherwise specified, all limits ensured for TA= 25°C, V+= 2.7 V, V−= 0 V, VCM = 0.5 V, VOUT = 1.35 V, and RL> 1 MΩ
to 1.35 V.(1)
PARAMETER TEST CONDITION MIN(2) TYP(3) MAX(2) UNIT
−5 ±0.7 +5
VOS Input Offset Voltage VCM = 0.5 V and VCM = 2.2 V mV
TA= –40°C to +125°C −6 +6
Input Offset Voltage
TC VOS VCM = 0.5 V and VCM = 2.2 V(4) ±2 µV/C
Temperature Drift
−2−1.2
VCM = 0.5 V(5) TA= –40°C to +125°C −2.5
IBInput Bias Current µA
0.45 1
VCM = 2.2 V(5) TA= –40°C to +125°C 1.5
20 200
IOS Input Offset Current VCM = 0.5 V and VCM = 2.2 V nA
TA= –40°C to +125°C 300
70 100
0 V ≤VCM ≤1 V TA= –40°C to +125°C 60
Common-Mode
CMRR dB
Rejection Ratio 55 70
0 V ≤VCM ≤2.7 V TA= –40°C to +125°C 50
78 104
Power Supply Rejection
PSRR 2.7 V ≤VS≤30 V dB
Ratio TA= –40°C to +125°C 74
−0.3 −0.1
Common-Mode Voltage CMRR > 50 dB
Range (Min) TA= –40°C to +125°C 0
CMVR V
2.8 3
Common-Mode Voltage CMRR > 50 dB
Range (Max) TA= –40°C to +125°C 2.7
65 72
0.5 V ≤VO≤2.2 V
RL= 10 kΩto 1.35 V TA= –40°C to +125°C 62
AVOL Open-Loop Voltage Gain dB
59 66
0.5 V ≤VO≤2.2 V
RL= 2 kΩto 1.35V TA= –40°C to +125°C 55 50 150
RL= 10 kΩto 1.35 V
VID = 100 mV TA= –40°C to +125°C 160
Output Voltage Swing
High 100 250
RL= 2 kΩto 1.35 V
VID = 100 mV TA= –40°C to +125°C 280 mV from
VOUT either rail
20 120
RL= 10 kΩto 1.35 V
VID =−100 mV TA= –40°C to +125°C 150
Output Voltage Swing
Low 40 120
RL= 2 kΩto 1.35 V
VID =−100 mV TA= –40°C to +125°C 150
30 48
Sourcing
VID = 200 mV, VOUT = 0 V(6) TA= –40°C to +125°C 20
IOUT Output Current mA
Sinking 40 65
VID =−200 mV, VOUT = 2.7 TA= –40°C to +125°C 30
V(6)
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ> TA.
(2) All limits are ensured by testing or statistical analysis.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4) Offset voltage temperature drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
(5) Positive current corresponds to current flowing into the device.
(6) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C. Short circuit test is a momentary test. Output short circuit duration is
infinite for VS≤6 V at room temperature and below. For VS> 6 V, allowable short circuit duration is 1.5 ms.
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2.7-V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for TA= 25°C, V+= 2.7 V, V−= 0 V, VCM = 0.5 V, VOUT = 1.35 V, and RL> 1 MΩ
to 1.35 V.(1)
PARAMETER TEST CONDITION MIN(2) TYP(3) MAX(2) UNIT
0.95 1.3
LM7321 TA= –40°C to +125°C 1.9
ISSupply Current mA
2 2.5
LM7322 TA= –40°C to +125°C 3.8
SR Slew Rate(7) AV= +1, VI= 2-V Step 8.5 V/µs
fuUnity Gain Frequency RL= 2 kΩ, CL= 20 pF 7.5 MHz
GBW Gain Bandwidth f = 50 kHz 16 MHz
Input Referred Voltage
enf = 2 kHz 11.9 nV/√H
Noise Density
Input Referred Current
inf = 2 kHz 0.5 pA/√H
Noise Density V+= 1.9 V, V−=−0.8 V
Total Harmonic
THD+N f = 1 kHz, RL= 100 kΩ, AV= +2 −77 dB
Distortion + Noise VOUT = 210 mVPP
CT Rej. Crosstalk Rejection f = 100 kHz, Driver RL= 10 kΩ60 dB
(7) Slew rate is the slower of the rising and falling slew rates. Connected as a Voltage Follower.
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7.6 ±5-V Electrical Characteristics
Unless otherwise specified, all limited ensured for TA= 25°C, V+= 5 V, V−=−5V, VCM = 0 V, VOUT = 0 V, and RL> 1 MΩto 0
V.(1)
PARAMETER TEST CONDITION MIN(2) TYP(3) MAX(2) UNIT
−5 ±0.7 +5
VCM =−4.5 V and VCM =
VOS Input Offset Voltage mV
4.5 V TA= –40°C to +125°C −6 +6
Input Offset Voltage
TC VOS VCM =−4.5 V and VCM = 4.5 V(4) ±2 µV/°C
Temperature Drift VCM =−4.5 V(5) −2.0 −1.2
TA= –40°C to +125°C −2.5
IBInput Bias Current µA
VCM = 4.5 V(5) 0.45 1
TA= –40°C to +125°C 1.5
20 200
VCM =−4.5 V and VCM =
IOS Input Offset Current nA
4.5 V TA= –40°C to +125°C 300
80 100
−5 V ≤VCM ≤3 V TA= –40°C to +125°C 70
Common Mode
CMRR dB
Rejection Ratio 65 80
−5 V ≤VCM ≤5 V TA= –40°C to +125°C 62
78 104
Power Supply Rejection 2.7 V ≤VS≤30 V,
PSRR dB
Ratio VCM =−4.5 V TA= –40°C to +125°C 74
−5.3 −5.1
Common-Mode Voltage CMRR > 50 dB
Range (Min) TA= –40°C to +125°C −5
CMVR V
5.1 5.3
Common-Mode Voltage CMRR > 50 dB
Range (Max) TA= –40°C to +125°C 5
74 80
−4 V ≤VO≤4 V
RL= 10 kΩto 0 V TA= –40°C to +125°C 70
Open-Loop Voltage
AVOL dB
Gain 68 74
−4 V ≤VO≤4 V
RL= 2 kΩto 0 V TA= –40°C to +125°C 65 100 250
RL= 10 kΩto 0 V
VID = 100 mV TA= –40°C to +125°C 280
Output Voltage Swing
High 160 350
RL= 2 kΩto 0 V mV
VID = 100 mV TA= –40°C to +125°C 450 from
VOUT either
35 200
RL= 10 kΩto 0 V rail
VID =−100 mV TA= –40°C to +125°C 250
Output Voltage Swing
Low 80 200
RL= 2 kΩto 0 V
VID =−100 mV TA= –40°C to +125°C 250
Sourcing 35 70
VID = 200 mV, VOUT =−5TA= –40°C to +125°C 20
V(6)
IOUT Output Current mA
Sinking 50 85
VID =−200 mV, VOUT = 5 TA= –40°C to +125°C 30
V(6)
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ> TA.
(2) All limits are ensured by testing or statistical analysis.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4) Offset voltage temperature drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
(5) Positive current corresponds to current flowing into the device.
(6) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C. Short circuit test is a momentary test. Output short circuit duration is
infinite for VS≤6 V at room temperature and below. For VS> 6 V, allowable short circuit duration is 1.5 ms.
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±5-V Electrical Characteristics (continued)
Unless otherwise specified, all limited ensured for TA= 25°C, V+= 5 V, V−=−5V, VCM = 0 V, VOUT = 0 V, and RL> 1 MΩto 0
V.(1)
PARAMETER TEST CONDITION MIN(2) TYP(3) MAX(2) UNIT
1.0 1.3
LM7321 TA= –40°C to 2
+125°C
ISSupply Current VCM =−4.5 V mA
2.3 2.8
LM7322 TA= –40°C to 3.8
+125°C
SR Slew Rate(7) AV= +1, VI= 8-V Step 12.3 V/µs
fuUnity Gain Frequency RL= 2 kΩ, CL= 20 pF 9 MHz
GBW Gain Bandwidth f = 50 kHz 16 MHz
Input Referred Voltage f = 2 kHz
en14.3 nV/√H
Noise Density
Input Referred Current f = 2 kHz
in1.35 pA/√H
Noise Density
Total Harmonic f = 1 kHz, RL= 100 kΩ, AV= +2
THD+N −79 dB
Distortion + Noise VOUT = 8 VPP
CT Rej. Crosstalk Rejection f = 100 kHz, Driver RL= 10 kΩ60 dB
(7) Slew rate is the slower of the rising and falling slew rates. Connected as a Voltage Follower.
7.7 ±15-V Electrical Characteristics
Unless otherwise specified, all limited ensured for TA= 25°C, V+= 15 V, V−=−15 V, VCM = 0 V, VOUT = 0 V, and RL> 1 MΩto
15 V.(1)
PARAMETER TEST CONDITION MIN(2) TYP(3) MAX(2) UNIT
−6 ±0.7 +6
VCM =−14.5 V and
VOS Input Offset Voltage mV
VCM = 14.5 V –40°C to +125°C −8 +8
Input Offset Voltage
TC VOS VCM =−14.5 V and VCM = 14.5 V(4) ±2 µV/°C
Temperature Drift
−2−1.1
VCM =−14.5 V(5) –40°C to +125°C −2.5
IBInput Bias Current µA
0.45 1
VCM = 14.5 V(5) –40°C to +125°C 1.5
30 300
VCM =−14.5 V and
IOS Input Offset Current nA
VCM = 14.5 V –40°C to +125°C 500
80 100
−15 V ≤VCM ≤12 V –40°C to +125°C 75
Common-Mode Rejection
CMRR dB
Ratio 72 80
−15 V ≤VCM ≤15 V –40°C to +125°C 70
78 100
Power Supply Rejection 2.7 V ≤VS≤30 V, VCM
PSRR dB
Ratio = −14.5 V –40°C to +125°C 74
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ> TA.
(2) All limits are ensured by testing or statistical analysis.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4) Offset voltage temperature drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
(5) Positive current corresponds to current flowing into the device.
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±15-V Electrical Characteristics (continued)
Unless otherwise specified, all limited ensured for TA= 25°C, V+= 15 V, V−=−15 V, VCM = 0 V, VOUT = 0 V, and RL> 1 MΩto
15 V.(1)
PARAMETER TEST CONDITION MIN(2) TYP(3) MAX(2) UNIT
−15.3 −15.1
Common-Mode Voltage CMRR > 50 dB
Range (Min) –40°C to +125°C −15
CMVR V
15.1 15.3
Common-Mode Voltage CMRR > 50 dB
Range (Max) –40°C to +125°C 15
75 85
−13 V ≤VO≤13 V
RL= 10 kΩto 0 V –40°C to +125°C 70
AVOL Open-Loop Voltage Gain dB
70 78
−13 V ≤VO≤13 V
RL= 2 kΩto 0 V –40°C to +125°C 65 150 300
RL= 10 kΩto 0 V
VID = 100 mV –40°C to +125°C 350
Output Voltage Swing
High 250 550
RL= 2 kΩto 0 V mV
VID = 100 mV –40°C to +125°C 650 from
VOUT either
60 200
RL= 10 kΩto 0 V rail
VID =−100 mV –40°C to +125°C 250
Output Voltage Swing
Low 130 300
RL= 2 kΩto 0 V
VID =−100 mV –40°C to +125°C 400
Sourcing 40 65
VID = 200 mV, VOUT =−15 V(6)
IOUT Output Current mA
Sinking 60 100
VID =−200 mV, VOUT = 15 V(6)
1.1 1.7
LM7321 –40°C to +125°C 2.4
ISSupply Current VCM =−14.5 V mA
2.5 4
LM7322 –40°C to +125°C 5.6
SR Slew Rate(7) AV= +1, VI= 20-V Step 18 V/µs
fuUnity Gain Frequency RL= 2 kΩ, CL= 20 pF 11.3 MHz
GBW Gain Bandwidth f = 50 kHz 20 MHz
Input Referred Voltage f = 2 kHz
en15 nV/√H
Noise Density
Input Referred Current
inf = 2 kHz 1.3 pA/√H
Noise Density
Total Harmonic Distortion f = 1 kHz, RL100 kΩ,
THD+N −86 dB
+Noise AV= +2, VOUT = 23 VPP
CT Rej. Crosstalk Rejection f = 100 kHz, Driver RL= 10 kΩ60 dB
(6) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C. Short circuit test is a momentary test. Output short circuit duration is
infinite for VS≤6 V at room temperature and below. For VS> 6 V, allowable short circuit duration is 1.5 ms.
(7) Slew rate is the slower of the rising and falling slew rates. Connected as a Voltage Follower.
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0.1 1 10 100
ISOURCE (mA)
0.01
0.1
1
10
VOUT from V+ (V)
VS = ±15V
125°C
85°C
25°C
-40°C
0.1 1 10 100
ISINK (mA)
0.01
0.1
1
10
VOUT from V- (V)
VS = ±15V
125°C
85°C
25°C
-40°C
0.1 1 10 100
ISOURCE (mA)
0.01
0.1
1
10
VOUT from V+ (V)
VS = ±5V
125°C
85°C
25°C
-40°C
0.1 1 10 100
ISINK (mA)
0.01
0.1
1
10
VOUT from V- (V)
VS = ±5V
125°C
85°C
25°C
-40°C
0.1 1 10 100
ISOURCE (mA)
0.01
0.1
1
10
VOUT from V+ (V)
VS = 2.7V
125°C
85°C
25°C
-40°C
0.1 1 10 100
ISINK (mA)
0.01
0.1
1
10
VOUT from V- (V)
VS = 2.7V
125°C
85°C
25°C
-40°C
LM7321
,
LM7322
SNOSAW8E –MAY 2008–REVISED SEPTEMBER 2015
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7.8 Typical Characteristics
Unless otherwise specified: TA= 25°C.
Figure 1. Output Swing vs. Sourcing Current Figure 2. Output Swing vs. Sinking Current
Figure 3. Output Swing vs. Sourcing Current Figure 4. Output Swing vs. Sinking Current
Figure 5. Output Swing vs. Sourcing Current Figure 6. Output Swing vs. Sinking Current
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-6 -4 -2 0 0 4 6
VCM (V)
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
VOS (mV)
25°C
VS = ±5V
85°C
125°C
-40°C
-6 -4 -2 02 4 6
VCM (V)
-2.5
-2.25
-2
-1.75
-1.5
-1.25
-1
VOS (mV)
VS = ±5V
-40°C
25°C
85°C
125°C
-1 0 1 2 3 4
-2.5
-2.3
-2.1
-1.9
-1.7
-1.5
-1.3
-1.1
-0.9
-0.7
-0.5
VOS (mV)
VCM (V)
-40°C
25°C
85°C
125°C
VS = 2.7V
-1 0 1 2 3 4
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
VOS (mV)
VCM (V)
85°C
-40°C
-40°C
125°C
25°C
125°C
VS = 2.7V
-3 -2 -1 0 1 2 3
VOS (mV)
0
2
4
6
8
10
12
PERCENTAGE (%)
VS = ±5V
-1 0 1 2 3 4
-2.5
-2.3
-2.1
-1.9
-1.7
-1.5
-1.3
-1.1
-0.9
-0.7
-0.5
VOS (mV)
VCM (V)
-40°C
25°C
85°C
125°C
VS = 2.7V
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,
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SNOSAW8E –MAY 2008–REVISED SEPTEMBER 2015
Typical Characteristics (continued)
Unless otherwise specified: TA= 25°C.
Figure 7. VOS Distribution Figure 8. VOS vs. VCM (Unit 1)
Figure 9. VOS vs. VCM (Unit 2) Figure 10. VOS vs. VCM (Unit 3)
Figure 11. VOS vs. VCM (Unit 1) Figure 12. VOS vs. VCM (Unit 2)
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0 10 20 30 40
-2.5
-2.3
-2.1
-1.9
-1.7
-1.5
-1.3
-1.1
VOS (mV)
VS (V)
-40°C
25°C
85°C
125°C
VCM = V- +0.5V
05 10 15 20 25 30 35 40
VS (V)
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
VOS (mV)
VCM = V- +0.5V
85°C
125°C
-40°C
25°C
-20 -15 -10 -5 0 5 10 15 20
-1
0
VOS (mV)
VCM (V)
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1 VS = ±15V
-40°C
25°C
85°C 125°C
-20 -15 -10 -5 0 5 10 15 20
-2.5
-0.5
VOS (mV)
VCM (V)
-2.3
-2.1
-1.9
-1.7
-1.5
-1.3
-1.1
-0.9
-0.7 VS = ±15V
-40°C
25°C
85°C
125°C
-6 -4 -2 02 4 6
VCM (V)
-2.5
-2.25
-2
-1.75
-1.5
-1.25
-1
-0.75
-0.5
VOS (mV)
-40°C
25°C
85°C
125°C
VS = ±5V
-20 -15 -10 -5 0 5 10 15 20
VCM (V)
VOS (mV)
-2.25
-2
-1.75
-1.5
-1.25
-1 VS = ±15V
-40°C
25°C
85°C
125°C
LM7321
,
LM7322
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Typical Characteristics (continued)
Unless otherwise specified: TA= 25°C.
Figure 14. VOS vs. VCM (Unit 1)
Figure 13. VOS vs. VCM (Unit 2)
Figure 15. VOS vs. VCM (Unit 2) Figure 16. VOS vs. VCM (Unit 3)
Figure 18. VOS vs. VS(Unit 2)
Figure 17. VOS vs. VS(Unit 1)
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-5 -3 -1 1 3 5
-1.5
-1
-0.5
0
0.5
1
IBAIS (PA)
VCM (V)
VS = ±5V
-40°C
25°C
125°C 85°C
00.5 1 1.5 2 2.5 3
VCM (V)
-1.5
-1
-0.5
0
0.5
1
IBIAS (PA)
VS = 2.7V -40°C 25°C
85°C 125°C
05 10 15 20 25 30 35 40
VS (V)
-2.2
-2
-1.8
-1.6
-1.4
-1.2
-1
VOS (mV)
-40°C
25°C
85°C
125°C
VCM = V+ -0.5V
0 5 10 15 20 25 30 35 40
-1
0
VOS (mV)
VS (V)
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
85°C
125°C
25°C
-40°C
VCM = V+ -0.5V
05 10 15 20 25 30 35 40
VS (V)
-2.5
-2
-1.5
-1
-0.5
0
VOS (mV)
-40°C
25°C
85°C
125°C
VCM = V- +0.5V
05 10 15 20 25 30 35 40
VS (V)
-2
-1.8
-1.6
-1.4
-1.2
-1
VOS (mV)
VCM = V+ -0.5V
-40°C
25°C
85°C
125°C
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,
LM7322
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SNOSAW8E –MAY 2008–REVISED SEPTEMBER 2015
Typical Characteristics (continued)
Unless otherwise specified: TA= 25°C.
Figure 20. VOS vs. VS(Unit 1)
Figure 19. VOS vs. VS(Unit 3)
Figure 21. VOS vs. VS(Unit 2) Figure 22. VOS vs. VS(Unit 3)
Figure 23. IBIAS vs. VCM Figure 24. IBIAS vs. VCM
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-6 -4 -2 0 2 4 6
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
IS (mA)
VCM (V)
VS = ±5V
125°C
85°C
25°C
-40°C
-1 0 1 2 3 4
0
0.5
1
1.5
2
2.5
3
3.5
IS (mA)
VCM (V)
125°C
85°C
25°C
-40°C
VS = 2.7V
-1 0 1 2 3 4
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
IS (mA)
VCM (V)
VS = 2.7V 125°C
85°C
25°C
-40°C
0 10 20 30 40
0.3
0.35
0.4
0.45
0.5
0.55
0.6
0.65
0.7
IBIAS (PA)
VS (V)
VCM = V+ -0.5V
-40°C
25°C
85°C
125°C
-15 -10 -5 0 5 10 15
VCM (V)
-1.5
-1
-0.5
0
0.5
1
IBIAS (PA)
VS = ±15V
125°C 85°C
25°C -40°C
05 10 15 20 25 30 35 40
VS (V)
-1.6
-1.5
-1.4
-1.3
-1.2
-1.1
-1
IBIAS (PA)
VCM = V- +0.5V
-40°C
25°C
85°C 125°C
LM7321
,
LM7322
SNOSAW8E –MAY 2008–REVISED SEPTEMBER 2015
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Typical Characteristics (continued)
Unless otherwise specified: TA= 25°C.
Figure 26. IBIAS vs. VS
Figure 25. IBIAS vs. VCM
Figure 27. IBIAS vs. VSFigure 28. ISvs. VCM (LM7321)
Figure 29. ISvs. VCM (LM7322) Figure 30. ISvs. VCM (LM7321)
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0 5 10 15 20 25 30 35 40
0
4.5
IS (mA)
VS (V)
0.5
1
1.5
2
2.5
3
3.5
4125°C 85°C
25°C
-40°C
VCM = V+ -0.5V
0 10 20 30 40
0
0.5
1
1.5
2
2.5
IS (mA)
VS (V)
VCM = V+ -0.5V
125°C 85°C
25°C
-40°C
5 15 25 35
0 10 20 30 40
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
IS (mA)
VS (V)
125°C
85°C
25°C
-40°C
VCM = V- +0.5V
515 25 30
-20 -15 -10 -5 0 5 10 15 20
0
4.5
IS (mA)
VCM (V)
0.5
1
1.5
2
2.5
3
3.5
4
25°C 85°C
25°C
-40°C
VS = ±15V
85°C
-6 -4 -2 02 4 6
VCM (V)
0
0.5
1
1.5
2
2.5
3
3.5
4
IS (mA)
125°C
25°C
-40°C
VS = ±5V
-20 -15 -10 -5 0 5 10 15 20
VCM (V)
0
0.5
1
1.5
2
2.5
IS (mA)
VS = ±15V
125°C 85°C
25°C
-40°C
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,
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SNOSAW8E –MAY 2008–REVISED SEPTEMBER 2015
Typical Characteristics (continued)
Unless otherwise specified: TA= 25°C.
Figure 31. ISvs. VCM (LM7322) Figure 32. ISvs. VCM (LM7321)
Figure 33. ISvs. VCM (LM7322) Figure 34. ISvs. VS(LM7321)
Figure 36. ISvs. VS(LM7321)
Figure 35. ISvs. VS(LM7322)
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-20
0
20
40
60
140
GAIN (dB)
1k 10k 100k 1M 10M
FREQUENCY (Hz)
80
100
120
100M
VS = r15V
RL = 10 M:
PHASE
GAIN
0
23
45
68
90
113
135
PHASE (q)
-23
158
20 pF
50 pF
200 pF
100 pF
50 pF
200 pF
100 pF
1000 pF
500 pF
1000 pF
500 pF
0 10 20 30 40
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
VOUT from RAIL (V)
VS (V)
RL = 10 k:
-40°C
25°C
85°C
125°C
0 10 20 30 40
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
VOUT from RAIL (V)
VS (V)
RL = 2 k:125°C
85°C
25°C
-40°C
05 10 15 20 25 30 35 40
VS (V)
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
VOUT from RAIL (V)
RL = 10 k:
-40°C
125°C
85°C
25°C
0 10 20 30 40
0
0.05
0.1
0.15
0.2
0.25
0.3
VOUT from RAIL (V)
VS (V)
-40°C
125°C
85°C
25°C
RL = 2 k:
05 10 15 20 25 30 35 40
VS (V)
0
0.5
1
1.5
2
2.5
3
IS (mA)
125°C 85°C
25°C
-40°C
VCM = V- +0.5V
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,
LM7322
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Typical Characteristics (continued)
Unless otherwise specified: TA= 25°C.
Figure 37. ISvs. VS(LM7322) Figure 38. Positive Output Swing vs. Supply Voltage
Figure 39. Positive Output Swing vs. Supply Voltage Figure 40. Negative Output Swing vs. Supply Voltage
Figure 42. Open-Loop Frequency Response with Various
Figure 41. Negative Output Swing vs. Supply Voltage Capacitive Load
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10 1k 1M
FREQUENCY (Hz)
0
40
100
-PSRR (dB)
100k
10k
100
80
60
20
10
30
50
70
90 VS = 30V
VCM = 2V
VS = 10V
VCM = 2V VS = 2.7V
VCM = 2V
10 1k 1M
FREQUENCY (Hz)
0
40
120
+PSRR (dB)
100k
10k
100
100
60
20
80
VS = 2.7V
VCM = 0.7V
VS = 10V
VCM = 8V
VS = 30V
VCM = 28V
10 100 1000
0
10
20
30
40
50
60
70
PHASE MARGIN (°)
CAPACITIVE LOAD (pF)
RL = 600:
RL = 2 k:
RL = 10 M:, 10 k:, 100 k:
VS = ±15V
10 1k 1M
FREQUENCY (Hz)
0
40
100
CMRR (dB)
100k
10k
100
80
60
20
10
30
50
70
90 VS = ±15V
-20
0
20
40
60
140
GAIN (dB)
1k 10k 100k 1M 10M
FREQUENCY (Hz)
80
100
120
100M
VS = r15V
CL = 20 pF
PHASE
GAIN
0
23
45
68
90
113
135
PHASE (q)
-23
158
10 M:
2 k:
600:
100 k:
10 k:
2 k:
600:
-20
0
20
40
60
140
GAIN (dB)
1k 10k 100k 1M 10M
FREQUENCY (Hz)
80
100
120
100M
RL = 2 k:
CL = 20 pF
0
23
45
68
90
113
135
PHASE (q)
-23
158
VS = 10V
VS = 30V
VS = 2.7V
VS = 30V
VS = 2.7V
VS = 10V
PHASE
GAIN
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Typical Characteristics (continued)
Unless otherwise specified: TA= 25°C.
Figure 43. Open-Loop Frequency Response with Various Figure 44. Open-Loop Frequency Response with Various
Resistive Load Supply Voltage
Figure 46. CMRR vs. Frequency
Figure 45. Phase Margin vs. Capacitive Load
Figure 47. +PSRR vs. Frequency Figure 48. −PSRR vs. Frequency
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110 100 1k 100k
FREQUENCY (Hz)
1
10
100
1000
10k
CURRENT NOISE (pA/
Hz)
VOLTAGE NOISE (nV
Hz)
0.1
1
10
100
VOLTAGE
CURRENT
VS = ±15V
0
10 1k 1M
FREQUENCY (Hz)
-80
-50
THD+N (dB)
100k
10k
100
-20
-30
-60
-70
-40
-10
VS = 2.7V, VCM = 0.8V
VS = ±5V
VS = ±15V
AV = +2
VIN = 520 mVPP
RL = 100 k:
110 100 1k 100k
FREQUENCY (Hz)
1
10
100
1000
10k
CURRENT NOISE (pA/
Hz)
VOLTAGE NOISE (nV
Hz)
0.1
1
10
100
VOLTAGE
CURRENT
VS = 2.7V
110 100 1k 100k
FREQUENCY (Hz)
1
10
100
1000
10k
CURRENT NOISE (pA/
Hz)
VOLTAGE NOISE (nV
Hz)
0.1
1
10
100
VOLTAGE
CURRENT
VS = ±5V
25V/DIV
5 Ps/DIV
VS = ±15V, AV = +1
INPUT
10 pF
2,200 pF
8,600 pF
12,200 pF
1000 pF
750 pF
500 pF
330 pF
100 pF
10 pF
INPUT
100 mV/DIV
200 ns/DIV
VS = ±5V
AV = +1
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LM7322
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Typical Characteristics (continued)
Unless otherwise specified: TA= 25°C.
Figure 49. Small Signal Step Response Figure 50. Large Signal Step Response
Figure 51. Input Referred Noise Density vs. Frequency Figure 52. Input Referred Noise Density vs. Frequency
Figure 53. Input Referred Noise Density vs. Frequency Figure 54. THD+N vs. Frequency
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0.001 0.1 100
OUTPUT AMPLITUDE (VPP)
-90
-70
0
THD+N (dB)
10
1
0.01
-20
-30
-80
-10
-40
-50
-60
VS = ±15V
f = 1 kHz
RL = 100 k:
AV = +2
0.001 0.01 0.1 1 10
OUTPUT AMPLITUDE (VPP)
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
THD+N (dB)
VS = 2.7V
VCM = 0.8V
f = 1 kHz
RL = 100 k:
AV = +2
0.001 0.1 100
OUTPUT AMPLITUDE (VPP)
-90
-70
0
THD+N (dB)
10
1
0.01
-20
-30
-80
-10
-40
-50
-60
VS = ±5V
f = 1 kHz
RL = 100 k:
AV = +2
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SNOSAW8E –MAY 2008–REVISED SEPTEMBER 2015
Typical Characteristics (continued)
Unless otherwise specified: TA= 25°C.
Figure 56. THD+N vs. Output Amplitude
Figure 55. THD+N vs. Output Amplitude
Figure 57. THD+N vs. Output Amplitude
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±
+
-IN
+IN
OUT
V+
V-
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SNOSAW8E –MAY 2008–REVISED SEPTEMBER 2015
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8 Detailed Description
8.1 Overview
The LM732xx devices are rail-to-rail input and output amplifiers with wide operating voltages and high-output
currents. The LM732xx family is efficient, achieving 18-V/µs slew rate and 20-MHz unity gain bandwidth while
requiring only 1 mA of supply current per op amp. The LM732xx device performance is fully specified for
operation at 2.7 V, ±5 V and ±15 V.
The LM732xx devices are designed to drive unlimited capacitive loads without oscillations. All LM7321x and
LM7322x parts are tested at −40°C, 125°C, and 25°C, with modern automatic test equipment. High performance
from −40°C to 125°C, detailed specifications, and extensive testing makes them suitable for industrial,
automotive, and communications applications.
Greater than rail-to-rail input common-mode voltage range with 50 dB of common-mode rejection across this
wide voltage range, allows both high-side and low-side sensing. Most device parameters are insensitive to power
supply voltage, and this makes the parts easier to use where supply voltage may vary, such as automotive
electrical systems and battery-powered equipment. These amplifiers have true rail-to-rail output and can supply a
respectable amount of current (15 mA) with minimal head room from either rail (300 mV) at low distortion (0.05%
THD+Noise).
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 Output Short Circuit Current and Dissipation Issues
The LM732xx output stage is designed for maximum output current capability. Even though momentary output
shorts to ground and either supply can be tolerated at all operating voltages, longer lasting short conditions can
cause the junction temperature to rise beyond the absolute maximum rating of the device, especially at higher
supply voltage conditions. Below supply voltage of 6 V, the output short circuit condition can be tolerated
indefinitely.
With the op amp tied to a load, the device power dissipation consists of the quiescent power due to the supply
current flow into the device, in addition to power dissipation due to the load current. The load portion of the
power itself could include an average value (due to a DC load current) and an AC component. DC load current
would flow if there is an output voltage offset, or the output AC average current is non-zero, or if the op amp
operates in a single supply application where the output is maintained somewhere in the range of linear
operation.
Therefore,
PTOTAL = PQ+ PDC + PAC (1)
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PD(MAX) = 150°C ± 125°C
165°C/W = 0.15 W
PD(MAX) = 150°C ± 125°C
235°C/W = 0.11 W
PD(MAX) = 150°C ± 25°C
165°C/W = 0.76 W
PD(MAX) = 150°C ± 25°C
235°C/W = 0.53 W
PD(MAX) = TJ(MAX) - TA
TJA
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SNOSAW8E –MAY 2008–REVISED SEPTEMBER 2015
Feature Description (continued)
The Op Amp Quiescent Power Dissipation is calculated as:
PQ= IS× VS
where
• IS: Supply Current
• VS: Total Supply Voltage (V+−V−) (2)
The DC Load Power is calculated as:
PDC = IO× (Vr- Vo)
where
• VO: Average Output Voltage
• Vr: V+for sourcing and V−for sinking current (3)
The AC Load Power is calculated as PAC = See Table 1.
Table 1 shows the maximum AC component of the load power dissipated by the op amp for standard Sinusoidal,
Triangular, and Square Waveforms:
Table 1. Normalized AC Power Dissipated in the Output Stage for Standard Waveforms
PAC (W.Ω/V2)
Sinusoidal Triangular Square
50.7 × 10−346.9 × 10−362.5 × 10−3
The table entries are normalized to VS2/RL. To figure out the AC load current component of power dissipation,
simply multiply the table entry corresponding to the output waveform by the factor VS2/RL. For example, with ±12-
V supplies, a 600-Ωload, and triangular waveform power dissipation in the output stage is calculated as:
PAC = (46.9 × 10−3) × (242/600) = 45.0 mW (4)
The maximum power dissipation allowed at a certain temperature is a function of maximum die junction
temperature (TJ(MAX)) allowed, ambient temperature TA, and package thermal resistance from junction to ambient,
θJA.
(5)
For the LM732xx, the maximum junction temperature allowed is 150°C at which no power dissipation is allowed.
The power capability at 25°C is given by the following calculations:
For VSSOP package:
(6)
For SOIC package:
(7)
Similarly, the power capability at 125°C is given by:
For VSSOP package:
(8)
For SOIC package:
(9)
Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: LM7321 LM7322
-40 -20 0 20 40 60 80 100 120 140 160
0
0.2
0.4
0.6
0.8
1
1.2
1.4
POWER CAPABILITY (W)
TEMPERATURE (°C)
Operating area
Maximum thermal capability line (SOIC)
Maximum thermal capability line (MSOP)
LM7321
,
LM7322
SNOSAW8E –MAY 2008–REVISED SEPTEMBER 2015
www.ti.com
Figure 58 shows the power capability vs. temperature for VSSOP and SOIC packages. The area under the
maximum thermal capability line is the operating area for the device. When the device works in the operating
area where PTOTAL is less than PD(MAX), the device junction temperature will remain below 150°C. If the
intersection of ambient temperature and package power is above the maximum thermal capability line, the
junction temperature will exceed 150°C and this should be strictly prohibited.
Figure 58. Power Capability vs. Temperature
When high power is required and ambient temperature can't be reduced, providing air flow is an effective
approach to reduce thermal resistance therefore to improve power capability.
8.3.2 Estimating the Output Voltage Swing
It is important to keep in mind that the steady-state output current will be less than the current available when
there is an input overdrive present. For steady-state conditions, the Output Voltage vs. Output Current plot
(Typical Characteristics section) can be used to predict the output swing. Figure 59 and Figure 60 show this
performance along with several load lines corresponding to loads tied between the output and ground. In each
cases, the intersection of the device plot at the appropriate temperature with the load line would be the typical
output swing possible for that load. For example, a 1-kΩload can accommodate an output swing to within 250
mV of V−and to 330 mV of V+(VS= ±15 V) corresponding to a typical 29.3 VPP unclipped swing.
Figure 59. Output Sourcing Characteristics With Load Figure 60. Output Sinking Characteristics With Load Lines
Lines
22 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated
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LM7321
,
LM7322
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SNOSAW8E –MAY 2008–REVISED SEPTEMBER 2015
8.4 Device Functional Modes
8.4.1 Driving Capacitive Loads
The LM732xx are specifically designed to drive unlimited capacitive loads without oscillations as shown in
Figure 61.
Figure 61. ±5% Settling Time vs. Capacitive Load
In addition, the output current handling capability of the device allows for good slewing characteristics even with
large capacitive loads as shown in Figure 62 and Figure 63.
Figure 62. +SR vs. Capacitive Load Figure 63. −SR vs. Capacitive Load
The combination of these features is ideal for applications such as TFT flat panel buffers, A/D converter input
amplifiers, and so forth.
However, as in most op amps, addition of a series isolation resistor between the op amp and the capacitive load
improves the settling and overshoot performance.
Output current drive is an important parameter when driving capacitive loads. This parameter will determine how
fast the output voltage can change. Referring to the Slew Rate vs. Capacitive Load Plots (Typical Characteristics
section), two distinct regions can be identified. Below about 10,000 pF, the output Slew Rate is solely determined
by the compensation capacitor value of the op amp and available current into that capacitor. Beyond 10 nF, the
Slew Rate is determined by the available output current of the op amp.
Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: LM7321 LM7322
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,
LM7322
SNOSAW8E –MAY 2008–REVISED SEPTEMBER 2015
www.ti.com
Device Functional Modes (continued)
NOTE
Because of the lower output sourcing current compared to the sinking one, the Slew Rate
limit under heavy capacitive loading is determined by the positive transitions.
An estimate of positive and negative slew rates for loads larger than 100 nF can be made by dividing the short
circuit current value by the capacitor.
For the LM732xx, the available output current increases with the input overdrive. Referring to Figure 64 and
Figure 65, it can be seen that both sourcing and sinking short circuit current increase as input overdrive
increases. In a closed-loop amplifier configuration, during transient conditions while the fed back output has not
quite caught up with the input, there will be an overdrive imposed on the input allowing more output current than
would normally be available under steady-state condition. Because of this feature, the output stage quiescent
current of the op amp can be kept to a minimum, thereby reducing power consumption, while enabling the device
to deliver large output current when the need arises (such as during transients).
Figure 64. Output Short Circuit Sourcing Current vs. Input Figure 65. Output Short Circuit Sinking Current vs. Input
Overdrive Overdrive
Figure 66 shows the output voltage, output current, and the resulting input overdrive with the device set for AV=
+1 and the input tied to a 1-VPP step function driving a 47-nF capacitor. As can be seen, during the output
transition, the input overdrive reaches 1-V peak and is more than enough to cause the output current to increase
to its maximum value (see Figure 64 and Figure 65 plots).
NOTE
Because of the larger output sinking current compared to the sourcing one, the output
negative transition is faster than the positive one.
Figure 66. Buffer Amplifier Scope Photo
24 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM7321 LM7322
LM7321
,
LM7322
www.ti.com
SNOSAW8E –MAY 2008–REVISED SEPTEMBER 2015
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Similar High-Output Devices
The LM7332 is a dual rail-to-rail amplifier with a slightly lower GBW capable of sinking and sourcing 100 mA. It is
available in SOIC and VSSOP packages.
The LM4562 is dual op amp with very low noise and 0.7-mV voltage offset.
The LME49870 and LME49860 are single and dual low-noise amplifiers that can work from ±22-V supplies.
9.1.2 Other High Performance SOT-23 Ampliers
The LM7341 is a 4-MHz rail-to-rail input and output part that requires only 0.6 mA to operate, and can drive
unlimited capacitive load. It has a voltage gain of 97 dB, a CMRR of 93 dB, and a PSRR of 104 dB.
The LM6211 is a 20-MHz part with CMOS input, which runs on ±12-V or 24-V single supplies. It has rail-to-rail
output and low noise.
The LM7121 has a gain bandwidth of 235 MHz.
Detailed information on these parts can be found at www.ti.com.
9.2 Typical Application
Figure 67 shows a typical application where the LM732xx is used as a buffer amplifier for the VCOM signal
employed in a TFT LCD flat panel:
Figure 67. VCOM Driver Application Schematic
9.2.1 Design Requirements
For this example application, the supply voltage is +5 V, and noninverting gain is necessary.
Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: LM7321 LM7322
90
1k 100k 10M
FREQUENCY (Hz)
0
30
60
CROSSTALK REJECTION (dB)
100M
1M
10k
80
70
50
40
20
10
VS = ±15V
VS = ±5V
V+ = 1.8V
VCM = 0.9V
LM7321
,
LM7322
SNOSAW8E –MAY 2008–REVISED SEPTEMBER 2015
www.ti.com
Typical Application (continued)
9.2.2 Detailed Design Procedure
Figure 68 shows the time domain response of the amplifier when used as a VCOM buffer/driver with VREF at
ground. In this application, the op amp loop will try and maintain its output voltage based on the voltage on its
noninverting input (VREF) despite the current injected into the TFT simulated load. As long as this load current is
within the range tolerable by the LM732xx (45-mA sourcing and 65-mA sinking for ±5-V supplies), the output will
settle to its final value within less than 2 μs.
Figure 68. VCOM Driver Performance Scope Photo
9.2.3 Application Curve
Figure 69. Crosstalk Rejection vs. Frequency
26 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated
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,
LM7322
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SNOSAW8E –MAY 2008–REVISED SEPTEMBER 2015
10 Power Supply Recommendations
The use of supply decoupling is mandatory in most applications. As with most relatively high-speed or high-
output current op amps, best results are achieved when each supply line is decoupled with two capacitors; a
small value ceramic capacitor ( about 0.01 μF) placed very close to the supply lead in addition to a large value
Tantalum or Aluminum (> 4.7 μF). The large capacitor can be shared by more than one device if necessary. The
small ceramic capacitor maintains low supply impedance at high frequencies while the large capacitor will act as
the charge bucket for fast load current spikes at the op amp output. The combination of these capacitors will
provide supply decoupling and will help keep the op amp oscillation free under any load.
11 Layout
11.1 Layout Guidelines
Take care to minimize the loop area formed by the bypass capacitor connection between supply pins and
ground. A ground plane underneath the device is recommended; any bypass components to ground should have
a nearby via to the ground plane. The optimum bypass capacitor placement is closest to the corresponding
supply pin. Use of thicker traces from the bypass capacitors to the corresponding supply pins will lower the
power supply inductance and provide a more stable power supply.
The feedback components should be placed as close to the device as possible to minimize stray parasitics.
11.2 Layout Example
Figure 70. LM732xx Layout Example
Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 27
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,
LM7322
SNOSAW8E –MAY 2008–REVISED SEPTEMBER 2015
www.ti.com
12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY
LM7321 Click here Click here Click here Click here Click here
LM7322 Click here Click here Click here Click here Click here
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM7321 LM7322
PACKAGE OPTION ADDENDUM
www.ti.com 8-Oct-2015
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM7321MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM732
1MA
LM7321MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM732
1MA
LM7321MF/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AU4A
LM7321MFE/NOPB ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AU4A
LM7321MFX/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AU4A
LM7321QMF/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AR8A
LM7321QMFE/NOPB ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AR8A
LM7321QMFX/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AR8A
LM7322MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM732
2MA
LM7322MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM732
2MA
LM7322MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AZ4A
LM7322MME/NOPB ACTIVE VSSOP DGK 8 250 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AZ4A
LM7322QMA/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM732
2QMA
LM7322QMAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM732
2QMA
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 8-Oct-2015
Addendum-Page 2
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM7321, LM7321-Q1, LM7322, LM7322-Q1 :
•Catalog: LM7321, LM7322
•Automotive: LM7321-Q1, LM7322-Q1
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
PACKAGE OPTION ADDENDUM
www.ti.com 8-Oct-2015
Addendum-Page 3
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM7321MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM7321MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LM7321MFE/NOPB SOT-23 DBV 5 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LM7321MFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LM7321QMF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LM7321QMFE/NOPB SOT-23 DBV 5 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LM7321QMFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LM7322MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM7322MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM7322MME/NOPB VSSOP DGK 8 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM7322QMAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Dec-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM7321MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM7321MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LM7321MFE/NOPB SOT-23 DBV 5 250 210.0 185.0 35.0
LM7321MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LM7321QMF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LM7321QMFE/NOPB SOT-23 DBV 5 250 210.0 185.0 35.0
LM7321QMFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LM7322MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM7322MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
LM7322MME/NOPB VSSOP DGK 8 250 210.0 185.0 35.0
LM7322QMAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Dec-2016
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
0.22
0.08 TYP
0.25
3.0
2.6
2X 0.95
1.9
1.45 MAX
0.15
0.00 TYP
5X 0.5
0.3
0.6
0.3 TYP
8
0 TYP
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/D 11/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/D 11/2018
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/D 11/2018
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
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