TDA9109/N LOW-COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS .. .. . .. .. . . . . .. .. .. . HORIZONTAL SELF-ADAPTATIVE DUAL PLL CONCEPT 150kHz MAXIMUM FREQUENCY X-RAY PROTECTION INPUT I2C CONTROLS : H-POSITION, FREQUENCY GENERATOR FOR BURN-IN MODE VERTICAL VERTICAL RAMP GENERATOR 50 TO 165Hz AGC LOOP GEOMETRY TRACKING WITH VPOS & VAMP I2C CONTROLS : VAMP, VPOS, S-CORR, C-CORR DC BREATHING COMPENSATION I2C GEOMETRY CORRECTIONS VERTICAL PARABOLA GENERATOR (Pincushion, Keystone) HORIZONTAL DYNAMIC PHASE (Side Pin Balance & Parallelogram) HORIZONTAL AND VERTICAL DYNAMIC FOCUS (Horizontal Focus Amplitude, Horizontal Focus Symmetry, Vertical Focus Amplitude) GENERAL SYNC PROCESSOR 12V SUPPLY VOLTAGE 8V REFERENCE VOLTAGE HOR. & VERT. LOCK/UNLOCK OUTPUTS READ/WRITE I 2C INTERFACE VERTICAL MOIRE B+ REGULATOR - INTERNAL PWM GENERATOR FOR B+ CURRENT MODE STEP-UP CONVERTER - S WI TCHABL E TO STEP-DOWN CONVERTER 2 - I C ADJUSTABLEB+ REFERENCE VOLTAGE - OUTPUT PULSES SYNCHRONIZED ON HORIZONTAL FREQUENCY - INTERNAL MAX. CURRENT LIMITATION COMPARED WITH THE TDA9109, THE TDA9109/N HAS : - NO I2C FREE RUNNING FREQUENCY ADJUSTMENT - FIXED HORIZONTAL DUTY CYCLE (48%) - INCREASED MAX. STORAGE TIME OF THE HORIZONTAL SCANNING TRANSISTOR . June 1998 DESCRIPTION The TDA9109/N is a monolithic integrated circuit assembledin 32-pin shrink dual in line plastic package. This IC controls all the functions related to the horizontal and vertical deflection in multimode or multi-frequency computer display monitors. The internal sync processor, combined with the very powerful geometry correction block make the TDA9109/N suitable for very high performance monitors, using very few external components. The horizontaljitter level is very low. It is particularly well suited for high-end 15" and 17" monitors. Combined with the ST7275 Microcontroller family, TDA9206 (Video preamplifier) and STV942x (OnScreen Display controller) the TDA9109/N allows fully I2C bus controlled computer display monitors to be built with a reduced number of external components. SHRINK32 (Plastic Package) ORDER CODE : TDA9109/N 1/32 TDA9109/N 2/32 H/HVIN 1 32 5V VSYNCIN 2 31 SDA HLOCKOUT 3 30 SCL PLL2C 4 29 VCC C0 5 28 BOUT R0 6 27 GND PLL1F 7 26 HOUT HPOSITION 8 25 XRAY HFOCUSCAP 9 24 EWOUT FOCUS-OUT 10 23 VOUT HGND 11 22 VCAP HFLY 12 21 VREF HREF 13 20 VAGCCAP COMP 14 19 VGND REGIN 15 18 BREATH ISENSE 16 17 B+GND 9109N-01.EPS PIN CONNECTIONS TDA9109/N PIN CONNECTIONS Pin Name 1 H/HVIN 2 VSYNCIN 3 HLOCKOUT 4 PLL2C 5 C0 6 R0 7 PLL1F Function TTL compatible Horizontal sync Input (separate or composite) TTL compatible Vertical sync Input (for separated H&V) First PLL Lock/Unlock Output (0V unlocked - 5V locked) Second PLL Loop Filter Horizontal Oscillator Capacitor Horizontal Oscillator Resistor First PLL Loop Filter 8 HPOSITION 9 HFOCUSCAP Horizontal Position Filter (capacitor to be connected to HGND) 10 FOCUSOUT 11 HGND 12 HFLY Horizontal Flyback Input (positive polarity) 13 HREF Horizontal Section Reference Voltage (to be filtered) 14 COMP B+ Error Amplifier Output for frequency compensation and gain setting 15 REGIN Regulation Input of B+ control loop 16 ISENSE Sensing of external B+ switching transistor current, or switch for step-down converter 17 B+GND Ground (related to B+ reference adjustment) 18 BREATH DC Breathing Input Control (compensation of vertical amplitude against EHV variation) Horizontal Dynamic Focus Oscillator Capacitor Mixed Horizontal and Vertical Dynamic Focus Output Horizontal Section Ground 19 VGND 20 VAGCCAP Vertical Section Ground 21 VREF Vertical Section Reference Voltage (to be filtered) 22 VCAP Vertical Sawtooth Generator Capacitor 23 VOUT Vertical Ramp Output (with frequency independant amplitude and S or C Corrections if any). It is mixed with vertical position voltage and vertical moire. 24 EWOUT 26 HOUT Horizontal Drive Output (internal transistor, open collector) 25 XRAY X-RAY protection input (with internal latch function) Memory Capacitor for Automatic Gain Control Loop in Vertical Ramp Generator 27 GND General Ground (referenced to VCC) 28 BOUT B+ PWM Regulator Output 29 VCC Supply Voltage (12V typ) 30 SCL I2C Clock Input 31 SDA I2C Data Input 32 5V 9109N-01.TBL Pin Cushion - E/W Correction Parabola Output Supply Voltage (5V typ.) 3/32 TDA9109/N QUICK REFERENCE DATA Value Unit Horizontal Frequency 15 to 150 kHz Autosynch Frequency (for given R0 and C0) 1 to 4.5 f0 ae Horizontal Sync Polarity Input YES Polarity Detection (on both Horizontal and Vertical Sections) YES TTL Composite Sync YES Lock/Unlock Identification (on both Horizontal 1st PLL and Vertical Section) YES I2C Control for H-Position 10 XRAY Protection YES Fixed I2C Horizontal Duty Cycle 48 I2C Free Running Frequency Adjustment NO Stand-by Function YES Dual Polarity H-Drive Outputs NO Supply Voltage Monitoring YES PLL1 Inhibition Possibility NO Blanking Outputs NO % % Vertical Frequency 35 to 200 Hz Vertical Autosync (for 150nF on Pin 22 and 470nF on Pin 20) 50 to 165 Hz Vertical S-Correction YES Vertical C-Correction YES Vertical Amplitude Adjustment YES DC Breathing Control on Vertical Amplitude YES Vertical Position Adjustment YES East/West (E/W) Parabola Output (also known as Pin Cushion Output) YES E/W Correction Amplitude Adjustment YES Keystone Adjustment YES Internal Dynamic Horizontal Phase Control YES Side Pin Balance Amplitude Adjustment YES Parallelogram Adjustment YES Tracking of Geometric Corrections with Vertical Amplitude and Position YES Reference Voltage (both on Horizontal and Vertical) YES Dynamic Focus (both Horizontal and Vertical) 2 I C Horizontal Dynamic Focus Amplitude Adjustment YES YES I2C Horizontal Dynamic Focus Symmetry Adjustment YES I2C Vertical Dynamic Focus Amplitude Adjustment YES Detection of Input Sync Type (biased from 5V alone) YES Vertical Moire Output YES I2C Controlled V-Moire Amplitude YES Frequency Generator for Burn-in YES Fast I2C Read/Write 400 B+ Regulation adjustable by I2C YES 4/32 kHz 9109N-02.TBL Parameter 2 VSYNCIN 9109N-02.EPS GND 27 SCL 30 SDA 31 5V 32 VGND 19 VREF 21 XRAY 25 VCC 29 1 H/HVIN SYNC PROCESSOR I2C INTERFACE RESET GENERATOR VREF SYNC INPUT SELECT (1 bit) PLL1F HGND 11 HLOCKOUT 6 bits 4 X2 Spin Bal 6 bits X2 SAFETY PROCESSOR PHASE COMPARATOR 12 24 23 X2 TDA9109/N VAMPVDF 6 bits 18 X Keyst. 6 bits X2 E/W 7 bits VOUT BREATH 20 VPOS 7 bits VERTICAL OSCILLATOR RAMP GENERATOR VAMP 7 bits HOUT BUFFER 26 B+ CONTROLLER H-DUTY (48%) Amp & Symmetry 2 x 5 bits B+ Adjust 7 bits VCC XRAY PHASE SHIFTER GEOMETRY TRACKING VERTICAL Parallelogram MOIRE 6 bits CANCEL 5 BITS+ON/OFF VSYNC EWOUT VAGCCAP 22 S AND C CORRECTION 6 bits LOCK/UNLOCK IDENTIFICATION Forced Frequency 2 bits VCO 5 R0 PHASE/FREQUENCY COMPARATOR H-PHASE (7 bits) C0 6 HFLY 3 PLL2C VREF 8 HOUT HREF 13 HPOSITION 7 HFOCUSCAP 10 FOCUS 9 17 BGND 16 ISENSE 15 REGIN 28 B+OUT 14 COMP TDA9109/N BLOCK DIAGRAM VCAP 5/32 TDA9109/N Symbol VCC VDD VIN VESD Tstg Tj Toper Parameter Supply Voltage (Pin 29) Supply Voltage (Pin 32) Max Voltage on Pin 4 Pin 9 Pin 5 Pins 6, 7, 8, 14, 15, 16, 20, 22 Pin 10, 18, 23, 24, 25, 26, 28 Pins 1, 2, 3, 30, 31 Value 13.5 5.7 4.0 5.5 6.4 8.0 VCC VDD ESD susceptibility Human Body Model,100pF Discharge through 1.5k 2 EIAJ Norm,200pF Discharge through 0 300 Storage Temperature -40, +150 Junction Temperature +150 Operating Temperature 0, +70 Unit V V V V V V V V kV V o C o C o C 9109N-03.TBL ABSOLUTE MAXIMUM RATINGS Symbol Rth (j-a) Parameter Value Junction-Ambient Thermal Resistance Max. Unit o 65 C/W 9109N-04.TBL THERMAL DATA SYNC PROCESSOR Operating Conditions (VDD = 5V, T amb = 25oC) Symbol HsVR MinD Mduty VsVR VSW VSmD VextM IHLOCKOUT Parameter Voltage on H/HVIN Input Minimum Horizontal Input Pulses Duration Maximum Horizontal Input Signal Duty Cycle Voltage on VSYNCIN Minimum Vertical Sync Pulse Width Maximum Vertical Sync Input Duty Cycle Maximum Vertical Sync Width on TTL H/Vcomposite Sink and Source Current Test Conditions Pin 1 Pin 1 Pin 1 Pin 2 Pin 2 Pin 2 Pin 1 Pin3 Min. 0 0.7 Typ. Max. 5 25 5 0 5 15 750 250 Unit V s % V s % s A Electrical Characteristics (VDD = 5V, Tamb = 25oC) Symbol VINTH RIN TfrOut VHlock VoutT Parameter Horizontal and Vertical Input Logic Level (Pins 1, 2) Horizontal and Vertical Pull-Up Resistor Fall and Rise Time, Output CMOS Buffer Horizontal 1st PLL Lock Output Status (Pin 3) Extracted Vsync Integration Time (% of TH) on H/V Composite (see Note 1) Test Conditions Low Level High Level Pins 1, 2 Pin 3, COUT = 20pF Locked, ILOCKOUT = -250A Unlocked, I LOCKOUT = +250A C0 = 820pF Min. Typ. Max. 0.8 2.2 200 4.4 26 0 5 35 Min. Typ. 200 0.5 Unit V V k ns V V % Note 1 : TH is the horizontal period. I2C READ/WRITE (see Note 2) Electrical Characteristics (VDD = 5V,Tamb = 25oC) Symbol Parameter Test Conditions Max. Unit 400 kHz s s V V 2 Fscl Tlow Thigh Vinth VACK Maximum Clock Frequency Low period of the SCL Clock High period of the SCL Clock SDA and SCL Input Threshold Acknowledge Output Voltage on SDA input with 3mA Note 2 : See also I2C Table Control and I2C Sub Address Control. 6/32 Pin 30 Pin 30 Pin 30 Pins 30,31 Pin 31 1.3 0.6 2.2 0.4 9109N-05.TBL I C PROCESSOR TDA9109/N HORIZONTAL SECTION Operating Conditions Symbol Parameter Test Conditions Min. Typ. Max. Unit 150 k pF kHz 5 30 mA mA Unit VCO R0(Min.) C0(Min.) F(Max.) Minimum Oscillator Resistor Minimum Oscillator Capacitor Maximum Oscillator Frequency Pin 6 Pin 5 6 390 OUTPUT SECTION I12m HOI Maximum Input Peak Current Horizontal Drive Output Maximum Current Pin 12 Pin 26, Sunk current Electrical Characteristics (VCC = 12V, Tamb = 25oC) Symbol Parameter Test Conditions Min. Typ. Max. SUPPLY AND REFERENCE VOLTAGES VCC Supply Voltage Pin 29 10.8 12 13.2 V VDD Supply Voltage Pin 32 4.5 5 5.5 V ICC Supply Current Pin 29 50 mA IDD Supply Current Pin 32 5 mA VREF-H Horizontal Reference Voltage Pin 13, I = -2mA 7.4 8 8.6 VREF-V Vertical Reference Voltage Pin 21, I = -2mA 7.4 8 8.6 V IREF-H Max. Sourced Current on VREF-H Pin 13 5 mA IREF-V Max. Sourced Current on VREF-V Pin 21 5 mA V 1st PLL SECTION Delay Time for detecting polarity change (see Note 3) Pin 1 VVCO VCO Control Voltage (Pin 7) VREF-H = 8V f0 fH(Max.) 1.3 6.2 V V Vcog VCO Gain (Pin 7) R0 = 6.49k, C 0 = 820pF, dF/dV = 1/11R0C 0 17.1 kHz/V Hph Horizontal Phase Adjustment (see Note 4) % of Horizontal Period 10 % Horizontal Phase Setting Value (Pin 8) (see Note 4) Minimum Value Typical Value Maximum Value Sub-Address 01 Byte x1111111 Byte x1000000 Byte x0000000 2.8 3.4 4.0 V V V PLL1 Filter Current Charge PLL1 is Unlocked PLL1 is Locked 140 1 A mA Free Running Frequency R0 = 6.49k, C 0 = 820pF, f0 = 0.97/8R0C 0 22.8 kHz -150 ppm/C Vbmin Vbtyp Vbmax IPll1U IPll1L f0 df0/dT CR FF Notes : 3. 4. 5. 6. 0.75 Free Running Frequency Thermal Drift (No drift on external components) (see Note 5) PLL1 Capture Range (see Note 6) Forced Frequency FF1 Byte 11xxxxxx FF2 Byte 10xxxxxx R0 = 6.49k, C 0 = 820pF, from f0+0.5kHz to 4.5f0 fH(Min.) fH(Max.) Sub-Address 02 ms 25 90 kHz kHz 2f0 3f0 This delay is mandatory to avoid a wrong detection of polarity change in the case of a composite sync. See Figure 10 for explanation of reference phase. These parameters are not tested on each unit. They are measured during our internal qualification. This PLL capture range may be obtained only if f0 is adjusted (for instance by adjusting R0) . If not, more margin must be provided between fH (Min.) and f0, to cope with the components spread. 7/32 9109N-05.TBL HpolT TDA9109/N HORIZONTAL SECTION (continued) Electrical Characteristics (VCC = 12V, Tamb = 25oC) (continued) Symbol Parameter Test Conditions Min. Typ. Max. Unit 0.65 0.75 V 2nd PLL SECTION AND HORIZONTAL OUTPUT SECTION FBth Flyback Input Threshold Voltage (Pin 12) Hjit Horizontal Jitter At 31.4kHz 70 ppm HD Horizontal Drive Output Duty-Cycle Pin 26, see Note 7 48 % X-RAY Protection Input Threshold Voltage Pin 25, see Note 8 8 V Internal Clamping Levels on 2nd PLL Loop Filter (Pin 4) Low Level High Level 1.6 4.0 V V Threshold Voltage to Stop H-Out,V-Out, B-Out and Reset XRAY when VCC < VSCinh (see Note 8) Pin 29 7.5 V Horizontal Drive Output (low level) Pin 26, IOUT = 30mA XRAYth Vphi2 VSCinh HDvd 0.4 V HORIZONTAL DYNAMIC FOCUS FUNCTION HDFst Horizontal Dynamic Focus Sawtooth Minimum Level Maximum Level Pin 9, capacitor on HFOCUSCAP and C0 = 820pF, TH = 20s 2 4.7 V V HDFdis Horizontal Dynamic Focus Sawtooth Discharge Width Start by HFLY center 400 ns HDFDC Bottom DC Output Level RLOAD = 10k, Pin 10 TDHDF DC Output Voltage Thermal Drift (see Note 5) HDFamp Horizontal Dynamic Focus Amplitude Min Byte xxx11111 Typ Byte xxx10000 Max Byte xxx00000 Sub-Address 03, Pin 10, fH = 50kHz, Symmetry Typ. Horizontal Dynamic Focus Symmetry Sub-Address 04, fH = 50kHz, Typ. Amp B/A A/B A/B HDFKeyst Min A/B Byte xxx11111 Typ Byte xxx10000 Max A/B Byte xxx00000 2 2 2 V 200 ppm/C 1 1.5 3 VPP VPP VPP 3.5 1.0 3.5 VERTICAL DYNAMIC FOCUS FUNCTION (positive parabola) Vertical Dynamic Focus Parabola (added to horizontal) Amplitude with VAMP and VPOS Typical Min. Byte 000000 Typ. Byte 100000 Max. Byte 111111 Sub-Address 0F 0 0.5 1 VPP VPP VPP Parabola Amplitude Function of VAMP Sub-Address 05 (tracking between VAMP and VDF) with Byte 10000000 VPOS Typ. (see Figure 1 and Note 9) Byte 11000000 Byte 11111111 0.6 1 1.5 VPP VPP VPP VHDFKeyt Parabola Asymetry Function of VPOS Sub-Address 06 Control (tracking between VPOS and VDF) Byte x0000000 with VAMP Max. Byte x1111111 0.52 0.52 VPP VPP VDFAMP Notes : 5. These parameters are not tested on each unit. They are measured during our internal qualification. 7. Duty Cycle is the ratio between the output transistor OFF time and the period. The power transistor is controlled OFF when the output transistor is OFF. 8. See Figure 14. 9. S and C correction are inhibited so the output sawtooth has a linear shape. 8/32 9109N-05.TBL AMPVDF TDA9109/N VERTICAL SECTION Operating Conditions Symbol Parameter Test Conditions Min. Typ. Max. Unit 6.5 V OUTPUTS SECTION VEWM Maximum E/W Output Voltage Pin 24 VEWm Minimum E/W Output Voltage Pin 24 1.8 V R LOAD Minimum Load for less than 1% Vertical Amplitude Drift Pin 20 65 M Electrical Characteristics (VCC = 12V, Tamb = 25oC) Symbol Parameter Test Conditions Min. Typ. Max. Unit VERTICAL RAMP SECTION VRB Voltage at Ramp Bottom Point VREF-V = 8V, Pin 22 2 V VRT Voltage at Ramp Top Point (with Sync) VREF-V = 8V, Pin 22 5 V VRTF Voltage at Ramp Top Point (without Sync) Pin 22 VRT-0.1 V VSTD Vertical Sawtooth Discharge Time Pin 22, C22 = 150nF 70 s VFRF Vertical Free Running Frequency (see Note 10) C OSC (Pin 22) = 150nF Measured on Pin22 100 Hz ASFR AUTO-SYNC Frequency (see Note 11) C22 = 150nF 5% RAFD Ramp Amplitude Drift Versus Frequency at C 22 = 150nF 50Hz < f and f < 165Hz Maximum Vertical Amplitude (see Note 5) 200 ppm/Hz Ramp Linearity on Pin 22 (see Note 10) 2.5V < V27 and V27 < 4.5V 0.5 % Vertical Position Adjustment Voltage (Pin 23 - VOUT mean value) Sub Address 06 Byte x0000000 Byte x1000000 Byte x1111111 3.3 3.65 3.2 3.5 3.8 V V V Vertical Output Voltage (peak-to-peak on Pin 23) Sub Address 05 Byte x0000000 Byte x1000000 Byte x1111111 2.5 3.5 2.25 3 3.75 V V V VOR VOI Vertical Output Maximum Current (Pin 23) dVS Max Vertical S-Correction Amplitude (see Note 12) x0xxxxxx inhibits S-CORR x1111111 gives max S-CORR Sub Address 07 Vertical C-Corr Amplitude x0xxxxxx inhibits C-CORR Sub Address 08 V/VPP @ TV/2 Byte x1000000 Byte x1100000 Byte x1111111 Ccorr V/VPP at TV/4 V/VPP at 3TV/4 165 Hz 5 mA -4 +4 % % -3 0 3 % % % Notes : 5. These parameters are not tested on each unit. They are measured during our internal qualification. 10. With Register 07 at Byte x0xxxxxx (S correction is inhibited) and with Register 08 at Byte x0xxxxxx (C correction is inhibited), the sawtooth has a linear shape. 11. This is the frequency range for which the vertical oscillator will automatically synchronize, using a single capacitor value on Pin 22 and with a constant ramp amplitude. 12. TV is the vertical period. 9/32 9109N-05.TBL Rlin VPOS 50 TDA9109/N VERTICAL SECTION (continued) Electrical Characteristics (VCC = 12V, Tamb = 25oC) (continued) Symbol Parameter Test Conditions Min. Typ. Max. Unit DC Output Voltage with Typ. VPOS and Keystone inhibited Pin 24, see Figure 2 2.5 V East/West (E/W) FUNCTION EWDC TDEW DC DC Output Voltage Thermal Drift See Note 13 100 ppm/C EWpara Parabola Amplitude with Max. VAMP, Typ. VPOS, Keystone inhibited Subaddress 0A Byte 11111111 Byte 11000000 Byte 10000000 2.5 1.25 0 VPP VPP VPP Parabola Amplitude Function of VAMP Control (tracking between VAMP and E/W) with Typ. VPOS, Typ. E/W Amplitude and Keystone inhibited(see Note 10) Subaddress 05 Byte 10000000 Byte 11000000 Byte 11111111 0.45 0.8 1.25 VPP VPP VPP Keystone Adjustment Capability with Typ. VPOS, E/W inhibited and Max. Vertical Amplitude (see Note 10 and Figure 4) Subaddress 09 Byte 1x000000 Byte 1x111111 1 1 VPP VPP Intrinsic Keystone Function of VPO S Control (tracking between VPOS and E/W) with Max. E/W Amplitude and Max. Vertical Amplitude (see Note 13) A/B Ratio B/A Ratio Subaddress 06 EWtrack KeyAdj KeyTrack Byte x0000000 Byte x1111111 0.52 0.52 Side Pin Balance Parabola Amplitude (Figure 3) with Max. VAMP, Typ. VPOS and Parallelogram inhibited (see Notes 10 & 14) Subaddress 0D Byte x1111111 Byte x1000000 +1.4 -1.4 %TH %TH Side Pin Balance Parabola Amplitude function of VAMP Control (tracking between VAMP and SPB) with Max. SPB, Typ. VPOS and Parallelogram inhibited (see Notes 10 & 14) Subaddress 05 Byte 10000000 Byte 11000000 Byte 11111111 0.5 0.9 1.4 %TH %TH %TH P ara ll elo gr am A dju st men t Capa bilit y w ith M ax . V AM P , T yp . VP O S a n d M a x. S PB (see Notes 10 & 14) Subaddress 0E Byte x1111111 Byte x1000000 +1.4 -1.4 %TH %TH Intrinsic Parallelogram Function of VPOS Control ( tracki ng be tween VPO S and DHPC) with Max. VAMP, Max. SPB and Parallelogram inhibited (see Notes 10 & 14) A/B Ratio B/A Ratio Subaddress 06 INTERNAL DYNAMIC HORIZONTAL PHASE CONTROL SPBpara SPBtrack ParAdj Partrack Byte x0000000 Byte x1111111 0.52 0.52 VERTICAL MOIRE VMOIRE Vertical Moire (measured on VOUT : Pin 23) Subaddress 0C Byte 01x11111 6 mV BRRANG BRADj DC Breathing Control Range (see Note 15) V18 Vertical Output Variation versus DC Breathing Control (Pin 23) V18 VREF-V V18 = 4V 1 12 0 -10 V % % Notes : 10. With Register 07 at Byte x0xxxxxx (S correction is inhibited) and with Register 08 at Byte x0xxxxxx (C correction is inhibited), the sawtooth has a linear shape. 13. These parameters are not tested on each unit. They are measured during our internal qualification. 14. TH is the horizontal period. 15. When not used the DC breathing control pin must be connected to 12V. 10/32 9109N-05.TBL BREATHING COMPENSATION TDA9109/N B+ SECTION Operating Conditions Symbol FeedRes Parameter Test conditions Minimum Feedback Resistor Min. Resistor between Pins 15 and 14 Typ. Max. Unit 5 k Electrical Characteristics (VCC = 12V, Tamb = 25oC) OLG UGBW Parameter Test conditions Min. Error Amplifier Open Loop Gain At low frequency (see Note 16) Unity Gain Bandwidth (see Note 16) IRI Regulation Input Bias Current Current sourced by Pin 15 (PNP base) EAOI Error Amplifier Output Current Current sourced by Pin 14 Current sunk by Pin 14 CSG Current Sense Input Voltage Gain Pin 16 MCEth ISI Tonmax B+OSV IVREF VREFADJ Max. Unit 85 dB 6 MHz A 0.2 0.5 2 mA mA 3 Max Current Sense Input Threshold Pin 16 Voltage 1.2 V 1 A Maximum ON Time of the external % of Horizontal period, power transistor f0 = 27kHz (see Note 17) 100 % B+ Output Saturation Voltage V28 with I28 = 10mA 0.25 V Internal Reference Voltage On erroramp (+) input for Subaddress 0B Byte 1000000 4.8 V +20 -20 % % Pin 16 6 V Pin 28 100 ns Current Sense Input Bias Current I nt e rna l R ef er en ce Adjustment Range Current sunk by Pin 16 (NPN base) V ol tag e Byte 1111111 Byte 0000000 PWMSEL Threshold for step-up/step-down selection tFB+ Typ. Fall Time 9109N-05.TBL Symbol Notes : 16. These parameters are not tested on each unit. They are measured during our internal qualification procedure which includes characterization on batches coming from corners of our processes and also temperature characterization. 17. The external power transistor is OFF during 400ns of the HFOCUSCAP discharge. Figure 1 : Vertical Dynamic Focus Function B B A 9109N-03.EPS A HDFDC Figure 3 : EWPARA Dynamic Horizontal Phase Control Output 9109N-04.EPS VDFAMP Figure 2 : E/W Output EWDC Figure 4 : Keystone Effect on E/W Output (PCC Inhibited) B A DHPCDC 9109N-06.EPS SPBPARA 9109N-05.EPS Keyadj 11/32 TDA9109/N TYPICAL VERTICAL OUTPUT WAVEFORMS Function Sub Address Pin Byte Specification VOUTDC Effect on Screen 2.25V 10000000 Vertical Size 05 23 VOUTDC 3.75V 11111111 Vertical Position DC Control 06 23 VOUTDC = 3.2V VOUTDC = 3.5V VOUTDC = 3.8V x0000000 x1000000 x1111111 0xxxxxxx Inhibited Vertical S Linearity 07 V 23 1x111111 VPP 1x000000 Vertical C Linearity 08 VPP V V = 3% V PP 23 V 1x111111 VPP V = 3% V PP 12/32 9109N-06.TBL / 9109N-07.EPS TO 9109N-13.EPS V = 4% V PP TDA9109/N GEOMETRY OUTPUT WAVEFORMS Function Sub Address Pin 03 10 Byte Specification Effect on Screen Horizontal Dynamic Focus with : Flyback Amplitude TH Horizontal Dynamic Focus with : Symmetry 04 Flyback 10 TH E/W Inhibited Keystone (Trapezoid) Control 09 1x000000 1.0V 2.5V 1x111111 1.0V 2.5V 2.5V 0V 24 Keystone Inhibited E/W (Pin Cushion) Control 10000000 0A 24 2.5V 11111111 SPB Inhibited 1x000000 0E Parallelogram Inhibited 3.7V 1.4% TH 3.7V 1.4% TH 1x000000 0D Internal 1x111111 Vertical Dynamic Focus with Horizontal 1.4% TH Internal 1x111111 Side Pin Balance Control 3.7V 0F 9109N-07.TBL / 9109N-14.EPS TO 9109N-24.EPS Parrallelogram Control 10 1.4% TH 3.7V 2V TV 13/32 TDA9109/N I2C BUS ADDRESS TABLE Slave Address (8C) : Write Mode Sub Address Definition D8 D7 D6 D5 D4 D3 D2 D1 0 0 0 0 0 0 0 0 0 Horizontal Drive Selection 1 0 0 0 0 0 0 0 1 Horizontal Position 2 0 0 0 0 0 0 1 0 Forced Frequency 3 0 0 0 0 0 0 1 1 Sync Priority / Horizontal Focus Amplitude 4 0 0 0 0 0 1 0 0 Refresh / Horizontal Focus Keystone 5 0 0 0 0 0 1 0 1 Vertical Ramp Amplitude 6 0 0 0 0 0 1 1 0 Vertical Position Adjustment 7 0 0 0 0 0 1 1 1 S Correction 8 0 0 0 0 1 0 0 0 C Correction 9 0 0 0 0 1 0 0 1 E/W Keystone A 0 0 0 0 1 0 1 0 E/W Amplitude B 0 0 0 0 1 0 1 1 B+ Reference Adjustment C 0 0 0 0 1 1 0 0 Vertical Moire D 0 0 0 0 1 1 0 1 Side Pin Balance E 0 0 0 0 1 1 1 0 Parallelogram F 0 0 0 0 1 1 1 1 Vertical Dynamic Focus Amplitude Slave Address (8D) : Read Mode No sub address needed. 14/32 TDA9109/N I2C BUS ADDRESS TABLE (continued) D8 D7 D6 D5 [0] [0] D4 D3 D2 D1 [0] [0] WRITE MODE HDrive 0, off [1], on 00 01 02 03 Xray 1, reset [0] Horizontal Phase Adjustment [1] Forced Frequency 1, on 1, f0 x 2 [0], off [0], f0 x 3 Sync 0, Comp [1], Sep 04 Detect Refresh [0], off 05 Vramp 0, off [1], on 06 [0] [0] Horizontal Focus Amplitude [1] [0] [0] [0] [0] Horizontal Focus Keystone [1] [0] [0] [0] [0] Vertical Ramp Amplitude Adjustment [1] [0] [0] [0] [0] [0] [1] [0] Vertical Position Adjustment [0] [0] [0] S Correction [0] [0] [1] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] 07 S Select 1, on [0] 08 C Select 1, on [0] 09 E/W Key 0, off [1] 0A E/W Sel 0, off [1] 0B Test H 1, on [0], off [1] 0C Test V 1, on [0], off Moire 1, on [0] 0D SPB Sel 0, off [1] 0E Parallelo 0, off [1] [0] [0] [0] C Correction [1] [0] [0] [0] E/W Keystone [1] [0] [0] E/W Amplitude [1] [0] [0] [0] B+ Reference Adjustment [0] [0] [0] Vertical Moire [0] [0] [0] Side Pin Balance [1] [0] [0] [0] Parallelogram 0F [1] [0] [1] [0] [0] [0] Vertical Dynamic Focus Amplitude [0] [0] READ MODE Hlock 0, on [1], no Vlock 0, on [1], no Xray 1, on [0], off Polarity Detection V pol H/V pol [1], negative [1], negative Vext det [0], no det Sync Detection H/V det V det [0], no det [0], no det [ ] initial value Data is transferred with vertical sawtooth retrace. We recommend to set the unspecified bit to [0] in order to assure the compatibility with future devices. 15/32 TDA9109/N OPERATING DESCRIPTION I - GENERAL CONSIDERATIONS I.1 - Power Supply The typical values of the power supply voltages VCC and VDD are 12V and 5V respectively. Optimum operation is obtained for VCC between 10.8 and 13.2V and VDD between 4.5 and 5.5V. Inorderto avoiderraticoperationof thecircuit during the transient phase of VCC switching on, or off, the value of VCC is monitored : if VCC is less than 7.5V typ., the outputs of the circuit are inhibited. Similarly, before VDD reaches 4V, all the I2C register arereset to their defaultvalue (see I2C Control Table). In order to have very good power supply rejection, the circuit is internally supplied by several voltage references (typ. value : 8V). Two of these voltage references are externally accessible, one for the vertical and one for the horizontal part. They can be used to bias external circuitry (if ILOAD is less than 5mA). It is necessary to filter the voltage references by external capacitors connected to ground, in order to minimize the noise and consequently the "jitter" on vertical and horizontal output signals. I.2 - I2C Control TDA9109/N belongs to the I 2C controlled device family. Instead of being controlled by DC voltages on dedicated control pins, each adjustment can be done via the I2C Interface. The I2C bus is a serial bus with a clock and a data input. Thegeneral functionand thebus protocolare specified in the Philips-bus data sheets. Theinterface (Data and Clock)is a comparatorwith hysteresis ; the thresholds(less then 2.2V on rising edge, more than 0.8V on falling edge with 5V supply) are TTL-compatible. Spikes of up to 50ns are filtered by an integrator and the maximum clock speed is limited to 400kHz. The data line (SDA) can be used bidirectionally. In read-mode the IC sends reply information (1 byte) to the micro-processor. The bus protocol prescribes a full-byte transmission in all cases. The first byte after the start condition is used to transmit the IC-address (hexa 8C for write, 8D for read). 16/32 I.3 - Write Mode In write mode the second byte sent contains the subaddress of the selected function to adjust (or controlsto affect)and the thirdbyte the corresponding data byte. It is possible to send more than one data byte to the IC. If after the third byte no stop or start condition is detected, the circuit increments automatically by one the momentary subaddressin the subaddress counter (auto-increment mode). So it is possible to transmit immediately the following data bytes without sending the IC address or subaddress.This can be useful to reinitialize all the controls very quickly (flash manner). This procedure can be finished by a stop condition. The circuit has 14 adjustment capabilities: 1 for the horizontal part, 4 for the vertical, 2 for the E/W correction, 2 for the dynamic horizontal phase control,1 for the Moire option, 3 for the horizontal and the vertical dynamic focus and 1 for the B+ reference adjustment. 17 bits are also dedicated to several controls (ON/OFF, Horizontal Forced Frequency, Sync Priority, Detection Refresh and XRAY reset). I.4 - Read Mode During the read mode the second byte transmits the reply information. The reply byte contains the horizontal and vertical lock/unlock status, the XRAY activation status and, the horizontal and vertical polarity detection.It also contains the sync detection status which is used by the MCU to assign the sync priority. A stop conditionalways stops all the activities of the bus decoder and switches to high impedance both the data and clock line (SDA and SCL). 2 See I C subaddress and control tables. I.5 - Sync Processor The internal sync processor allows the TDA9109/N to accept : - separated horizontal & vertical TTL-compatible sync signal, - composite horizontal & vertical TTL-compatible sync signal. TDA9109/N OPERATING DESCRIPTION (continued) I.6 - Sync Identification Status The MCU can read (address read mode : 8D) the status register via the I 2C bus, and then select the sync priority depending on this status. Among other data this register indicates the presence of sync pulses on H/HVIN, VSYNCIN and (when 12V is supplied) whether a Vext has been extractedfrom H/HVIN. Both horizontaland vertical sync are detected even if only 5V is supplied. In order to choose the right sync priority the MCU may proceed as follows (see I2C Address Table) : - refresh the status register, - wait at least for 20ms (Max. vertical period), - read this status register. Sync priority choice should be : Figure 5 Comment Sync type Separated H & V Composite TTL H&V Of course, when the choiceis made,we canrefresh the sync detections and verify that the extracted Vsync is present and that no sync type change has occured. The sync processor also gives sync polarity information. I.7 - IC status The IC can inform the MCU about the 1st horizontal PLL and vertical section status (locked or not) and about the XRAY protection (activated or not). Resetting the XRAY internal latch can be done either by decreasing the VCC supply or directly resetting it via the I2C interface. I.8 - Sync Inputs Both H/HVIN and VSYNCIN inputs are TTL compatible triggers with hysterisis to avoid erratic detection. Both inputs include a pull up resistor connected to VDD. I.9 - Sync Processor Output The sync processor indicates on the HLOCKOUT Pin whether 1st PLL is locked to an incoming horizontal sync. HLOCKOUT is a TTL compatible 9109N-25.EPS No Yes V det II - HORIZONTAL PART II.1 - Internal Input Conditions A digital signal (horizontal sync pulse or TTL composite) is sent by the syncprocessor to the horizontal input. It may be positive or negative (see Figure 5). Using internal integration, both signals are recognized if Z/T < 25%. Synchronization occurs on the leading edge of the internal sync signal. The minimum value of Z is 0.7s. Another integration is able to extract the vertical pulse from compositesync if the duty cycle is higher than 25% (typically d = 35%) (see Figure 6). Figure 6 C TRAMEXT d 9109N-26.EPS Sync priority Subaddress 03 (D8) Yes Yes 1 Yes No 0 Vext H/V det det CMOS output. Its level goes to high when locked. In the same time the D8 bit of the status register is set to 0. This information is mainly used to trigger safety procedures (like reducing B+ value) as soon as a change is delected on the incoming sync. d The last feature performed is the removal of equalization pulses to avoid parasitic pulses on the phase comparator (which would be disturbed by missing or extraneous pulses). 17/32 TDA9109/N OPERATING DESCRIPTION (continued) ure 8). The VCO uses an external RC network. It delivers a linear sawtooth obtained by the charge and the discharge of the capacitor, with a current proportional to the current in the resistor. The typical thresholds of the sawtooth are 1.6V and 6.4V. The control voltage of the VCO is between 1.33V and 6V (see Figure 9). The theorical frequency range of this VCO is in the ratio of 1 to 4.5. The effective frequency range has to be smaller (1 to 4.2) due to clamp intervention on the filter lowest value. Figure 7 PLL1F 7 1.8k 1F 9109N-27.EPS II.2 - PLL1 The PLL1 consists of a phase comparator, an external filter and a voltage-controlled oscillator (VCO). The phase comparator is a "phase frequency" type designed in CMOS technology. This kind of phase detector avoids locking on wrong frequencies. It is followed by a "charge pump", composed of two current sources : sunk and sourced (typically I = 1mA when locked and I = 140A whenunlocked).This differencebetweenlock/unlock allows smooth catching of the horizontal frequency by PLL1. This effect is reinforced by an internal original slow down system when PLL1 is locked, avoiding the horizontal frequency changing too quickly. The dynamic behaviour of PLL1 is fixed by an external filter which integrates the current of the charge pump. A "CRC" filter is generally used (see Figure 7). The PLL1 is internally inhibited during extracted vertical sync (if any) to avoid taking in account missing pulses or wrong pulses on phase comparator.The inhibition is done by a switch located between the charge pump and the filter (see Fig- 4.7F Figure 8 : Block Diagram Lock/Unlock Status LOCKDET Tramext PLL1F 7 I2C Forced Frequency R0 C0 6 5 High 1 CHARGE PUMP COMP1 Low E2 PLL INHIBITION VCO HPOSITION OSC 8 Tramext I2C HPOS Adj. PHASE ADJUST 9109N-28.EPS H/HVIN INPUT INTERFACE Figure 9 : Details of VCO I0 2 6.4V I0 Loop Filter 7 RS FLIP FLOP 1.6V 4 I0 6 5 R0 6.4V C0 1.6V 0 0.875TH TH 18/32 9109N-29.EPS (1.3V < V7 < 6V) TDA9109/N OPERATING DESCRIPTION (continued) The sync frequencymust always be higherthan the free running frequency. For example, when using a sync range between 24kHz and 100kHz, the suggested free running frequency is 23kHz. This can be obtained only by adjusting f0 (for instance, making R0 adjustable). If no adjustment is possible, more margin must be provided to cope with the componentsspread : 8% for the IC, 1% for R0, 2 or 5% for C0, leading to 11% or 14% on f0. The same percentage of frequency range will lost at upper end of the range. Another feature is the capability for the MCU to force the horizontal frequency through I2C to 2xf0 or 3xf0 (for burn-in mode or safety requirements). In this case, the inhibition switch is opened, leaving PLL1 free, but the voltage on PLL1 filter is forced to 2.66V (for 2xf0) or 4.0V (for 3xf0). PLL1 ensuresthe coincidencebetween the leading edge of the sync signal and a phase reference obtained by comparison between the sawtooth of the VCO and an internal DC voltage which is I2C adjustable between 2.8V and 4.0V (corresponding to 10%) (see Figure 10). II.3 - PLL2 PLL2 ensures a constant position of the shaped flyback signal in comparison with the sawtooth of the VCO, taking into accountthe saturationtime Ts (see Figure 11). Figure 11 : PLL2 Timing Diagram H Osc Sawtooth 6.4V 4.0V 1.6V Flyback Internally Shaped Flyback H Drive 9109N-31.EPS Ts Figure 10 : PLL1 Timing Diagram Duty Cycle 7/8TH 1/8TH The duty cycle of H-drive is fixed (48%). 6.4V 2.8V < Vb < 4.0V Vb 1.6V Phase REF1 The TDA9109/N also includes a Lock/Unlock identification block which senses in real time whether PLL1 is locked or not on the incoming horizontal sync signal. The resulting information is available on HLOCKOUT (see Sync Processor). When PLL1 is unlocked, it forces HLOCKOUT to high level. The lock/unlock information is also available through the I2C read. 9109N-30.EPS H Synchro Phase REF1 is obtained by comparison between the sawtooth and a DC voltage adjustable between 2.8V and 4.0V. The PLL1 ensures the exact coincidence between the signal phase REF and HSYNC. A TH/10 phase adjustment is possible. The phase comparator of PLL2 (phase type comparator) is followed by a charge pump (typical output current : 0.5mA). The flyback input consists of an NPN transistor. This input must be current driven. The maximum recommendedinput current is 5mA(see Figure 12). The duty cycle is fixed (48%). The maximum storage time (Ts Max.) is (0.44TH TFLY/2). Typically, TFLY/TH is around 20% which means that Ts max is around 34% of TH. Figure 12 : Flyback Input Electrical Diagram 400 Q1 HFLY 12 20k 9109N-32.EPS H Osc Sawtooth 1/8TH 7/8TH GND 0V 19/32 TDA9109/N OPERATING DESCRIPTION (continued) II.4 - Output Section The H-drive signal is sent to the output through a shaping stage which also controls the H-drive duty cycle (I 2C adjustable) (see Figure 11). In order to secure the scanning power part operation, the output is inhibited in the following cases : - when VCC or VDD are too low, - when the XRAY protection is activated, - during the Horizontal flyback, - when the HDrive I2C bit control is off. The output stage consists of a NPN bipolar transistor. Only the collector is accessible (see Figure 13). The maximum output current is 30mA, and the corresponding voltage drop of the output VCEsat is 0.4V Max. Obviously the power scanning transistor cannot be directly driven by the integrated circuit. An interface has to be added between the circuit and the power transistor either of bipolar or MOS type. Figure 13 This protection is latched ; it may be reset either by VCC switch off or by I2C (see Figure 14). II.5 - X-RAY Protection The X-Ray protection is activated by application of a high level on the X-Ray input (8V on Pin 25). It inhibits the H-Drive and B+ outputs. V CC 9109N-33.EPS 26 H-DRIVE This output stage is intended for "reverse" base control, where setting the output NPN in off-state will control the power scanning transistor in offstate (see Application Diagram). II.6 - Horizontal and Vertical Dynamic Focus The TDA9109/N delivers a horizontal parabola which is added on a vertical parabola waveform on Pin 10. This horizontal parabola comes from a sawtooth in phase with flyback pulse middle.This sawtooth is present on Pin 9 where the horizontal focus capacitor should be the same as C0 to obtain the correct amplitude (from 2 to 4.7V typically). Symmetry and amplitude are I2C adjustable (see Figure 15). The vertical dynamic focus is tracked with VPOSand VAMP.Its amplitudecan be adjusted. It is also affected by S and C corrections. This positive signal once amplified is to be sent to the CRT focusing grids. Figure 14 : Safety Functions Block Diagram VCC Checking I2C Drive on/off HORIZONTAL OUTPUT INHIBITION VCC VSCinh XRAY Protection XRAY VCC off or I C Reset 2 S R Q I2C Ramp on/off VERTICAL OUTPUT INHIBITION Horizontal Flyback BOUT 20/32 9109N-34.EPS 0.7V TDA9109/N OPERATING DESCRIPTION (continued) Figure 15 Horizontal Flyback Internal Trigged Horizontal Flyback 4.7V Horizontal Focus Cap Sawtooth 9109N-35.EPS Horizontal Dynamic Focus Parabola Output 2V 400ns 2V III - VERTICAL PART III.1 - Function When the synchronization pulse is not present, an internal current source sets the free running frequency. For an external capacitor, COSC = 150nF, the typical free running frequency is 100Hz. The typical free running frequency can be calculated by : 1 f0 (Hz) = 1.5 10-5 COSC A negative or positive TTL level pulse applied on Pin 2 (VSYNC)as well as a TTLcomposite sync on Pin 1 can synchronize the ramp in the range [fmin , fmax]. This frequencyrange depends on the ext e rn al capa c it or con nect ed on Pin 2 2. A 150nF (5%) capacitor is recommended for 50Hz to 165Hz applications. The typical maximum and minimum frequency, at 25oC and without any correction (S correction or C correction), can be calculated by : f(Max.) = 2.5 x f0 and f(Min.) = 0.33 x f0 If S or C corrections are applied, these values are slighty affected. If a synchronization pulse is applied, the internal oscillator is synchonized immediately but its amplitude changes. An internal correction then adjusts it in less than half a second. The top value of the ramp (Pin 22)is sampled on the AGC capacitor (Pin 20) at each clock pulse and a transconductance amplifier modifies the charge current of the capacitor in such a way to make the amplitude again constant. The read status register provides the vertical LockUnlock and the vertical sync polarity information. We recommend the use of an AGC capacitor with low leakage current. A value lower than 100nA is mandatory. A good stability of the internal closed loop is reached by a 470nF 5% capacitor value on Pin 20 (VAGC). 2 III.2 - I C Control Adjustments S and C correction shapes can then be added to this ramp. These frequency independent S and C corrections are generated internally. Their amplitudes are adjustable by their respec2 tive I C registers. They can also be inhibited by their select bits. Finally, the amplitude of this S and C corrected ramp can be adjusted by the vertical ramp amplitude control register. The adjusted ramp is available on Pin 23 (VOUT) to drive an external power stage. The gain of this stage can be adjusted (25%) depending on its register value. The mean value of this ramp is driven by its own I2C register (vertical position). Its value is VPOS = 7/16 VREF-V 300mV. Usually VOUT is sent through a resistive divider to the inverting input of the booster. Since VPOS derives from VREF-V, the bias voltage sent to the non-inverting input of the booster should also derive from VREF-V to optimize the accuracy (see Application Diagram). III.3 - Vertical Moire By using the vertical moire, VPOS can be modulated from frame to frame. This function is intended to cancel the fringes which appearwhen line to line interval is very close to the CRT vertical pitch. The amplitude of the modulation is controlled by register VMOIRE on sub-address 0C and can be switched-off via the control bit D7. 21/32 TDA9109/N OPERATING DESCRIPTION (continued) Figure 16 : AGC Loop Block Diagram CHARGE CURRENT TRANSCONDUCTANCE AMPLIFIER REF 22 20 DISCH. VSYNCIN 2 SYNCHRO OSC CAP SAMPLING OSCILLATOR SAMPLING CAPACITANCE S CORRECTION VS_AMP SUB07/6bits POLARITY COR_C SUB08/6bits C CORRECTION Vlow 18 BREATH Sawth. Disch. 23 VOUT VMOIRE SUB0C/5bits VPOSITION SUB06/7bits III.4 - Basic Equations In first approximation,the amplitude of the ramp on Pin 23 (VOUT) is : VOUT - VPOS = (VOSC - VDCMID) (1 + 0.25 (V AMP)) with : - VDCMID = 7/16 VREF (middle value of the ramp on Pin 22, typically 3.5V) - VOSC = V22 (ramp with fixed amplitude) - VAMP = -1 for minimum vertical amplitude register value and +1 for maximum - VPOS is calculated by : VPOS = VDCMID + 0.3 VP with VP equals -1 for minimum vertical position register value and +1 for maximum The current available on Pin 22 is : 3 IOSC = VREF COSC f 8 with : COSC : capacitor connected on Pin 22 and f : synchronization frequency. III.5 - Geometric Corrections The principle is represented in Figure 17. Starting from the vertical ramp, a parabola-shaped current is generatedfor E/W correction (also known as Pin Cushion correction), dynamic horizontal 22/32 phase control correction, and vertical dynamic Focus correction. The parabola generator is made by an analog multiplier, the output current of which is equal to : 2 DI = k (VOUT - VDCMID) where VOUT is the vertical output ramp (typically between 2 and 5V) and VDCMID is 3.5V (for VREF-V = 8V). The VOUT sawtooth is typically centered on 3.5V. By changing the vertical position, the sawtooth shifts by 0.3V. In order to have good screen geometry for any end user adjustment, the TDA9109/N has the "geometry tracking" feature, which allows generation of a dissymetric parabola depending on the vertical position. Due to the large output stage voltage range (E/W, Keystone), the combination of tracking function with maximum vertical amplitude, maximum or minimum vertical position and maximum gain on the DAC control may lead to the output stage saturation. This must be avoided by limiting the output voltage with apropriate I2C registers values. 9109N-36.EPS VERT_AMP SUB05/7bits TDA9109/N OPERATING DESCRIPTION (continued) For the E/W part and the dynamic horizontal phase control part, a sawtooth-shapeddifferential current in the following form is generated : DI' = k' (VOUT - VDCMID) Then I and I' are added and converted into voltage for the E/W part. Each of the two E/W components or the two dynamic horizontal phase control ones may be inhibited by their own I2C select bit. The E/W parabola is available on Pin 24 via an emitter follower output stage which has to be biased by an external resistor (10k to ground). Since stable in temperature, the device can be DC coupled with an external circuitry. The vertical dynamic focus is combined with the horizontal focus on Pin 10. The dynamic horizontal phase control drives internally the H-position, moving the HFLY position on the horizontal sawtooth in the range of 1.4% TH both for side pin balance and parallelogram. Figure 17 : Geometric Corrections Principle V.Focus Amp HORIZONTAL DYNAMIC FOCUS 2 VDCMID (3.5V) 10 Dynamic Focus 23 Vertical Ramp VOUT Parabola Generator EW Amp VDCMID (3.5V) 24 EW Output Keystone Sidepin Amp To Horizontal Phase Sidepin Balance Output Current Parallelogram III.6 - E/W EWOUT = 2.5V + K1 (VOUT - VDCMID) + K2 (VOUT - VDCMID)2 K1 is adjustable by the keystone I2C register K2 is adjustable by the E/W amplitude I2C register III.7 - Dynamic Horizontal Phase Control IOUT = K3 (VOUT - VDCMID) + K4 (VOUT - VDCMID)2 K3 is adjustable by the parallelogram I2C register K4 is adjustable by the side pin balance I2C register 23/32 9109N-37.EPS VDCMID (3.5V) TDA9109/N OPERATING DESCRIPTION (continued) IV - DC/DC CONVERTER PART Operating Description - The power MOS is switched-onas for the step-up mode. - The feedback to the error amplifier is done as for the step-up mode. - The power MOS is switched-off when the HFOCUSCAP voltage get higher than the error amplifier output voltage. This unit controls the switch-mode DC/DC converter. It converts a DC constant voltage into the B+ voltage (roughly proportional to the horizontal frequency) necessary for the horizontal scanning. This DC/DC converter can be configured either in step-up or step-down mode. In both cases it operates very similarly to the well known UC3842. IV.1 - Step-up Mode Operating Description - The powerMOS is switched-on during the flyback (at the beginning of the positive slope of the horizontal focus sawtooth). - The power MOS is switched-off when its current reachesa predeterminedvalue. For this purpose, a sense resistor is inserted in its source. The voltage on this resistor is sent to Pin16 (ISENSE). - The feedback (coming either from the EHV or from the flyback) is divided to a voltage close to 4.8V and compared to the internal 4.8V reference (IVREF). The differenceisamplifiedby an error amplifier, the output of which controls the power MOS switch-off current. Main Features - Switching synchronized on the horizontal frequency, - B+ voltage always lower than the DC source, - No current limitation. IV.3- Step-up and Step-down Mode Comparison In step-down mode the control signal is inverted compared with the step-up mode. The reason for this is the following : - In step-up mode, the switch is a N-channel MOS referenced to ground and made conductive by a high level on its gate. - In step-down, a high-side switch is necessary. It can be either a P- or a N-channel MOS. - Fora P-channelMOS,thegateiscontrolleddirectly fromPin28througha capacitor(this allowstospare a Transformer).In thiscase,a negative-goingpulse isneededto makethe MOS conductive.Therefore it is necessary to invert the control signal. - For a N-channel MOS, a transformer is needed to control the gate. The polarity of the transformer can be easily adapted to the negativegoing control pulse. Main Features - Switching synchronized on the horizontal frequency, - B+ voltage always higher than the DC source, - Current limited on a pulse-by-pulse basis. IV.2 - Step-down Mode In step-down mode, the Isense information is not used any more and therefore not sent to the Pin16. This mode is selected by connecting this Pin16 to a DC voltage higher than 6V (for example VREF-V). Figure 18 : DC/DC Converter I 2C DAC 7bits HDF Disc 400ns Horizontal Dynamic Focus Sawtooth Iadjust 8V 12V C1 BOUT down 4.8V 20% 95dB A 1/3 down C2 28 S Q R up up 1.2V C3 1.2V Inhibit SMPS 6V C4 Command step-up/down 8V REGIN COMP 15 14 1M 22k TDA9109/N 16 L 9109N-38.EPS + VB+ 24/32 ISENSE TDA9109/N INTERNAL SCHEMATICS Figure 19 Figure 20 5V HLOCKOUT 9109N-39.EPS 3 Figure 21 9109N-40.EPS 200 Pins 1 -2 H/HVIN VSYNCIN 20k 5V Figure 22 12V 12V HREF 13 PLL2C HREF 13 4 5 Figure 23 9109N-42.EPS 9109N-41.EPS C0 Figure 24 HREF HREF 13 13 PLL1F 7 12V 9109N-43.EPS 9109N-44.EPS R0 6 25/32 TDA9109/N INTERNAL SCHEMATICS (continued) Figure 25 Figure 26 HREF HREF 12V 13 12V HPOSITION 8 Figure 27 9109N-46.EPS 9109N-45.EPS HFOCUS 9 CAP Figure 28 12V HREF 13 12V 12V HFOCUS 10 Figure 29 9109N-48.EPS 9109N-47.EPS HFLY 12 Figure 30 12V REGIN 15 26/32 9109N-50.EPS 9109N-49.EPS COMP 14 TDA9109/N INTERNAL SCHEMATICS (continued) Figure 31 Figure 32 12V 12V ISENSE 16 Figure 33 9109N-52.EPS 9109N-51.EPS BREATH 18 Figure 34 12V VCAP 22 12V 9109N-53.EPS 9109N-54.EPS VAGCCAP 20 Figure 35 Figure 36 12V 12V EWOUT 24 9109N-55.EPS 9109N-56.EPS VOUT 23 27/32 TDA9109/N INTERNAL SCHEMATICS (continued) Figure 37 Figure 38 12V 12V HOUT-BOUT Pins 26-28 Figure 39 12V 9109N-59.EPS Pins 30-31 SDA - SCL 28/32 9109N-58.EPS 9109N-57.EPS XRAY 25 TDA9109/N APPLICATION DIAGRAMS Figure 40 : Demonstration Board J16 J15 J14 +12V TP1 TP13 J11 PC1 47k CC2 10F 1 H/HVIN +5V L1 22H R39 4.7k R29 4.7k R42 100 +5V 32 C30 100F TP16 R41 100 C32 100nF C40 22pF SCL TP17 J12 R53 1k HOUT C48 10F 10 FOCUS DYN FOCUS 4 3 2 1 R24 10k R15 1k R34 1k R30 10k R17 270k R31 27k R38 2.2 3W R19 270k Q1 Q2 BC557 BC557 R9 470 +12V L4 47H TILT J13 E/W POWER STAGE R37 27k VOUT 23 +5V C42 1F +5V +12V R45 33k R49 22k R43 10k C43 47F C37 33pF C36 1F R7 10k EWOUT 24 5 L2 22H J1 C11 220pF C34 820pF 5% R25 1k J9 6 D2 1N4148 TP14 HFLY 7 C38 33pF C17 1F 9 HFOCUSC 8 8MHz R56 560 C49 100nF 8 HPOSITION XRAYIN 25 R8 10k 9 PWM0 C31 4.7F R36 1.8k 10 IC3 - STV9422 HOUTCOL 26 PWM7 +12V 7 PLL1F 11 FBLK J8 GGND 27 C13 10nF HOUT C22 33pF 6 R0 12 X1 R23 6.49k 1% C25 33pF R35 10k +12V B+OUT 28 PWM1 R10 10k 5 C0 C5 100F PWM6 +12V +12V C6 100nF VSYNC QA GND CC4 47pF PC2 47k VCC 29 4 PLL2C C28 820pF 5% TEST QB 8 B QB IA QA 7 V DD IB IA 6 HSYNC IB 5 24 G CDB TA2 CDA 4 23 PXCK TB2 TA1 3 22 R TB1 2 SCL 30 21 CKOUT VCC 1 3 HLOCKOUT C7 22nF 20 GND 9 19 XTALOUT 10 18 RST 11 17 SDA 12 16 PWM2 13 15 XTALIN 14 14 PWM3 15 ICC1 MC14528 16 13 SCL TP10 PWM5 SDA +12V CC1 100nF C45 10F SDA 31 2 VSYNCIN PWM4 CC3 47pF 4 3 2 1 C39 22pF +5V IC4 TDA9109/N R33 4.7k R18 39k E/W Q3 TIP122 C12 11 HGND VCAP 22 R52 3.9k 150nF C16 ( *) 12 HFLY J19 1 C27 47F 2 C33 100nF VREF 21 C3 47F HREF 13 HREF VAGCCAP 20 3 470nF 4 JP1 CON4 C51 100nF 14 COMP R50 1M C2 100nF R2 5.6k 7 C41 470pF BGND 17 16 ISENSE C47 100pF TP6 J2 +12V -12V TP4 TP3 J3 TP7 6 J6 3 5 1 4 R1 12k BREATH 18 R57 82k ISENSE IC1 TDA8172 C9 100nF C10 100F 35V 2 VGND 19 R40 36k 15 REGIN R51 1k C4 100nF C46 1nF REGIN C14 470F D1 1n4001 C15 C10 -12V 470F 1 C1 R3 220nF 1.5 C8 100nF R5 5.6k R11 V YOKE 220 0.5W 2 3 J18 R4 1 0.5W VERTICAL DEFLECTION STAGE GND R58 10 Q4 BC557 J17 B+OUT TP8 EHT COMP R75 10k R76 47k P1 10k R77 15k HOUT Q5 BC547 R74 10k R73 1M C60 100nF L3 22H C50 10F 9109N-60.EPS +12V ( * ) Optional 29/32 TDA9109/N APPLICATION DIAGRAMS (continued) 9109N-61.EPS Figure 41 : PCB Layout 30/32 TDA9109/N APPLICATION DIAGRAMS (continued) 9109N-62.EPS Figure 42 : Components Layout 31/32 TDA9109/N PMSDIP32.EPS PACKAGE MECHANICAL DATA 32 PINS - PLASTIC SHRINK DIP A A1 A2 B B1 C D E E1 e eA eB L Min. 3.556 0.508 3.048 0.356 0.762 0.203 27.43 9.906 7.620 2.540 Millimeters Typ. 3.759 3.556 0.457 1.016 0.254 27.94 10.41 8.890 1.778 10.16 3.048 Max. 5.080 4.572 0.584 1.397 0.356 28.45 11.05 9.398 Min. 0.140 0.020 0.120 0.014 0.030 0.008 1.080 0.390 0.300 12.70 3.810 0.100 Inches Typ. 0.148 0.140 0.018 0.040 0.010 1.100 0.410 0.350 0.070 0.400 0.120 Max. 0.200 0.180 0.023 0.055 0.014 1.120 0.435 0.370 0.500 0.150 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical comp onents in lifesupport devicesor systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics 1998 STMicroelectronics - All Rights Reserved 2 2 Purchase of I C Components of STMicroelectronics, conveys a license under the Philips I C Patent. Rights to use these components in a I 2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco- The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 32/32 SDIP32.TBL Dimensions