UTS4ACS 163/UTS54ACTS 163 Radiation-Hardened 4-Bit Synchronous Counters FEATURES e Internal look-ahead for fast counting Carry output for n-bit cascading Synchronous counting e Synchronously programmable = 1.2y radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply e Available QML Q or V processes Flexible package - 16-pin DIP - 16-iead flatpack DESCRIPTION The UTS4ACS 163 and the UTS4ACTS 163 are synchronous presettable 4-bit binary counters that feature internal carry look- ahead logic for high-speed counting designs. Synchronous op- eration occurs by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when in- structed by the count-enable inputs and internal gating. A buff- ered clock input triggers the four flip-flops on the rising (posi- tive-going) edge of the clock input waveform. The counters are fully programmable (i.e., they may be preset to any number between 0 and 15). Presetting is synchronous; applying a low level at the load input disables the counter and causes the outputs to agree with the load data after the next clock pulse. The clear function is synchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse. This synchronous clear allows the count length to be mod- ified by decoding the Q outputs for the maximum count desired. The counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that modify the operat- ing mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting the stable setup and hold times. The devices are characterized over full military temperature range of -55C to +125C. PINOUTS 16-Pin DIP Top View CLRC}1 1 [7] Yoo cLKE]2 1{(] RCo AQ3 1 Ae BCl4 1 Qn cs 107% oCle 1 ] Qo ENP] 7 1{_) ENT Vss (| 8 9 CJ LOAD 16-Lead Flatpack Top View cir 1 16 Vpp CLK 2 15 RCO A 3 4 Qa B 4 613 Qg c 5 12 Qc D 6 1 Qp ENP 7 10 ENT Vss 8 9 COAD LOGIC SYMBOL CTRDIV 16 CLR 5CT=0 LOAD M2 3cT=15 RCO ENT G3 ENP G4 CLK A 45D = (1) w% B OQ Q D 1 (8) Qp Note: These symbols are in accordance with ANSI/EEE Std 91-1984 andIEC Pub- lication 617-12. 97 Rad-Hard MSI LogicUTS4ACS163/UTS4ACTS 163 FUNCTION TABLE Operating Mode CLR CLK ENP ENT LOAD DATA A,B,C,D Qn RCO Reset (Clear) I tT xX x x xX L Parallel Load n? Tt x x ! I L L 3 T X x I h H 1 h Count 3 tT h h h Count | ! Inhibit we X 12 xX 3 xX Qn 1 h? x xX 2 hi? x Qn L H = High voltage level h = High voltage level one setup time prior to the low-to-high clock transition L = Low voltage level 1 = Low voltage level one setup time prior to the low-to-high clock transition Notes: 1. The RCO output is high when ENT is high and the counter is at terminal count HHHH. 2. The high-to-low transition of ENP or ENT should only occur while CLK is high for conventional operations. 3. The low-to-high transition of LOAD or CLR should only occur while CLK is high for conventional operations. LOGIC DIAGRAM cLik 2 CLR 14) Q A LOAD ENP ENT DATA A (15) Qs DATA B (12) Qe DATA C 1) Qy DATA D RCO Rad-Hard MSI Logic 98UTS4ACS 163/UTS4ACTS 163 RADIATION HARDNESS SPECIFICATIONS ! PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU & SEL Threshold ? 80 MeV-cm2/mg Neutron Fluence 1.0E14 nfcm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS Vpp Supply voltage 0.3 to 7.0 Vv Vio Voltage any pin +3 to Vpp +.3 v TstG Storage Temperature range 65 to +150 C T; Maximum junction temperature +175 C TLs Lead temperature (soldering 5 seconds) +300 C jc Thermal resistance junction to case 20 CAW U DC input current +10 mA Pp Maximum power dissipation 1 Ww Note: 1, Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS Vpp Supply voltage 4.5 to 5.5 Vv Vin Input voltage any pin Oto Vpp Vv Te Temperature range -55 to + 125 C Rad-Hard MSI LogicDC ELECTRICAL CHARACTERISTICS 7 (Vpp = 5.0V 410%; Vgs = OV , -55C < Te < +125C) UT54ACS163/UTS4ACTS 163 SYMBOL PARAMETER CONDITION MIN MAX UNIT Vin Low-level input voltage ! ACTS m 0.8 v ACS 3Vpp Vin High-level input voltage ! ACTS Vpp v ACS pp lin Input leakage current ACTS/ACS Vin = Vpp or Vss -1 1 HA Vor Low-level output voltage 3 ACTS lor = 8.0mA 0.40 Vv ACS Io. = L00RA 0.25 Vou High-level output voltage 3 ACTS lou = -8.0mA TVpp Vv ACS low = -100HA Vpp - 0.25 los Short-circuit output current 2-4 ACTS/ACS Vo = Vpp and Vgs -200 200 mA Protal Power dissipation 8? Cy = SOpF 19 mW/MHz Ippg Quiescent Supply Current Vpp = 5.SV 10 pA Cin Input capacitance > J = 1MHz @ 0V 15 pF Cout Output capacitance * f = IMHz @ 0V 15 pF Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: Vjy = Vjy(min) + 20%, - 0%; Vi, = Vy_(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to Vj4(min) and Vj, (max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-M-38510, for current density $ 5.0E5 amps/cm?, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and Vsx, at frequency of 1MHz and a signal amplitude of 50mV ns maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose $1 E6 rads{Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. Rad-Hard MSI LogicUTS4ACS 163/UT54ACTS 163 AC ELECTRICAL CHARACTERISTICS 2 (Vpp = 5.0V +10%; Vgg = OV !, -55C < Te < +125C) SYMBOL PARAMETER MINIMUM MAXIMUM | UNIT tPpHL CLK to Qa 1 24 ns tly CLK to Qa 1 22 ns teu CLK to RCO 1 22 ns tply CLK to RCO 1 24 ns toy ENT to RCO 1 13 ns teLy ENT to RCO 1 14 ns fax Maximum clock frequency 77 MHz tsu Setup time before CLK T 6 ns A,B,C,D LOAD ENP, ENT TLR low CLR high la Data hold time after CLK T 1 ns All synchronous inputs tw Minimum pulse width 7 ns CIR low CLK high CLK low Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose < 1E6 rads(Si). 101 Rad-Hard MSI Logic