CY7C1340F-100AI - Cypress Semiconductor Corp.

4-Mb (128K x 32) Pipelined DCD Sync SRAM

CY7C1340F

Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600

Document #: 38-05219 Rev. *A Revised January 19, 2004

Features

• Registered inputs and outputs for pipelined operation

• Optimal for performance (Double-Cycle deselect)

— Depth expansion without wait state

• 128K × 32-bit common I/O architecture

• 3.3V –5% and +10% core power supply (VDD)

• 3.3V / 2.5V I/O supply (VDDQ)

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

— 2.6 ns (for 225-MHz device)

— 2.8 ns (for 200-MHz device)

— 3.5 ns (for 166-MHz device)

— 4.0 ns (for 133-MHz device)

— 4.5 ns (for 100-MHz device)

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel

Pentium interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous Output Enable

• JEDEC-standard 100-pin TQFP package and pinout

• “ZZ” Sleep Mode option

Functional Description[1]

The CY7C1340F SRAM integrates 131,072 x 32 SRAM cells

with advanced synchronous peripheral circuitry and a two-bit

counter for internal burst operation. All synchronous inputs are

gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(CE1), depth-expansion Chip Enables (CE2 and CE3), Burst

Control inputs (ADSC, ADSP

, and ADV), Write Enables

(BW[A:D], and BWE), and Global Write (GW). Asynchronous

inputs include the Output Enable (OE) and the ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to four bytes wide as

controlled by the byte write control inputs. GW active LOW

causes all bytes to be written. This device incorporates an

additional pipelined enable register which delays turning off

the output buffers an additional cycle when a deselect is

executed.This feature allows depth expansion without penal-

izing system performance.

The CY7C1340F operates from a +3.3V core power supply

while all outputs operate with a +3.3V or a +2.5V supply. All

inputsand outputs are JEDEC-standard JESD8-5-compatible..

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Selection Guide

250 MHz 225 MHz 200 MHz 166 MHz 133 MHz 100 MHz Unit

Maximum Access Time 2.6 2.6 2.8 3.5 4.0 4.5 ns

Maximum Operating Current 325 290 265 240 225 205 mA

Maximum CMOS Standby Current 40 40 40 40 40 40 mA

Shaded areas contain advance information.

Please contact your local Cypress sales representative for availability of these parts.

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CY7C1340F

Document #: 38-05219 Rev. *A Page 2 of 17

Functional Block Diagram—128Kx32

ADDRESS

ADV

CLK BURST

COUNTER AND

LOGIC

CLR

ADSP

ADSC

MODE

BWD

BWC

BWB

BWA

BWE

CE1

CE2

CE3

DQD

BYTE

WRITE REGISTER

DQc

BYTE

WRITE REGISTER

DQB

BYTE

WRITE REGISTER

DQA

BYTE

WRITE REGISTER

ENABLE

OUTPUT

REGISTERS

SENSE

AMPS

MEMORY

ARRAY OUTPUT

BUFFERS

DQA

BYTE

WRITE DRIVER

DQB

BYTE

WRITE DRIVER

DQC

BYTE

WRITE DRIVER

DQD

BYTE

WRITE DRIVER

INPUT

REGISTERS

0,A1,A

A[1:0]

SLEEP

CONTROL

DQs

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CY7C1340F

Document #: 38-05219 Rev. *A Page 3 of 17

Pin Configurations

100-pin TQFP

Top View

DDQ

SSQ

DDQ

SSQ

DDQ

DQc

DDQ

SSQ

DQc

SSQ

DDQ

DQc

DDQ

SSQ

DDQ

CLK

BWE

ADSC

ADSP

ADV

100

CY7C1340F

(128K x 32)

MODE

BYTE C

BYTE D

BYTE B

BYTE A

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CY7C1340F

Document #: 38-05219 Rev. *A Page 4 of 17

Pin Descriptions

Pin TQFP Type Description

A0, A1, A 37,36,32,33

34,35,44,45,

46,47,48,49,

50,81,82,99,

100

Input-

Synchronous

Address Inputs used to select one of the 128K address locations. Sampled at

the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3

are sampled active. A[1:0] are fed to the two-bit counter.

BWA, BWB,

BWC, BWD

93,94,95,96 Input-

Synchronous Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes

to the SRAM. Sampled on the rising edge of CLK.

GW 88 Input-

Synchronous

Global Write Enable Input, active LOW. When asserted LOW on the rising edge

of CLK, a global write is conducted (ALL bytes are written, regardless of the values

on BW[A:D] and BWE).

BWE 87 Input-

Synchronous

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This

signal must be asserted LOW to conduct a byte write.

CLK 89 Input-

Clock

Clock Input. Used to capture all synchronous inputs to the device. Also used to

increment the burst counter when ADV is asserted LOW, during a burst operation.

CE198 Input-

Synchronous

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in

conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1

is HIGH.

CE297 Input-

Synchronous

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in

conjunction with CE1 and CE3 to select/deselect the device.

CE392 Input-

Synchronous

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in

conjunction with CE1 and CE2 to select/deselect the device.

OE 86 Input-

Asynchronous

Output Enable, asynchronous input, active LOW. Controls the direction of the

DQ pins. When LOW, the DQ pins behave as outputs. When deasserted HIGH, DQ

pins are three-stated, and act as input data pins. OE is masked during the first clock

of a read cycle when emerging from a deselected state.

ADV 83 Input-

Synchronous

Advance Input signal, sampled on the rising edge of CLK, active LOW. When

asserted, it automatically increments the address in a burst cycle.

ADSP 84 Input-

Synchronous

Address Strobe from Processor, sampled on the rising edge of CLK, active

LOW. When asserted LOW, addresses presented to the device are captured in the

address registers. A[1:0] are also loaded into the burst counter. When ADSP and

ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is

deasserted HIGH.

ADSC 85 Input-

Synchronous

Address Strobe from Controller, sampled on the rising edge of CLK, active

LOW. When asserted LOW, addresses presented to the device are captured in the

address registers. A[1:0] are also loaded into the burst counter. When ADSP and

ADSC are both asserted, only ADSP is recognized.

ZZ 64 Input-

Asynchronous

ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a

non-time-critical “sleep” condition with data integrity preserved. For normal opera-

tion, this pin has to be LOW or left floating. ZZ pin has an internal pull-down.

DQs 52,53,56,57,

58,59,62,63

68,69,72,73,

74,75,78,79

2,3,6,7,8,9,

12,13

18,19,22,23,

24,25,28,29

I/O-

Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that

is triggered by the rising edge of CLK. As outputs, they deliver the data contained

in the memory location specified by the addresses presented during the previous

clock rise of the read cycle. The direction of the pins is controlled by OE. When OE

is asserted LOW, the pins behave as outputs. When HIGH, DQs are placed in a

three-state condition.

VDD 15,41,65,

Power Supply Power supply inputs to the core of the device.

VSS 17,40,67,

Ground Ground for the core of the device.

VDDQ 4,11,20,27,

54,61,70,77

I/O Power

Supply

Power supply for the I/O circuitry.

[+] Feedback

CY7C1340F

Document #: 38-05219 Rev. *A Page 5 of 17

Functional Overview

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock.

The CY7C1340F supports secondary cache in systems

utilizing either a linear or interleaved burst sequence. The

interleaved burst order supports Pentium and i486

processors. The linear burst sequence is suited for processors

that utilize a linear burst sequence. The burst order is user

selectable, and is determined by sampling the MODE input.

Accesses can be initiated with either the Processor Address

Strobe (ADSP) or the Controller Address Strobe (ADSC).

Address advancement through the burst sequence is

controlled by the ADV input. A two-bit on-chip wraparound

burst counter captures the first address in a burst sequence

and automatically increments the address for the rest of the

burst access.

Byte write operations are qualified with the Byte Write Enable

(BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write

Enable (GW) overrides all byte write inputs and writes data to

all four bytes. All writes are simplified with on-chip

synchronous self-timed write circuitry.

Synchronous Chip Selects CE1, CE2, CE3 and an

asynchronous Output Enable (OE) provide for easy bank

selection and output three-state control. ADSP is ignored if

CE1 is HIGH.

Single Read Accesses

This access is initiated when the following conditions are

satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)

chip selects are all asserted active, and (3) the write signals

(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1

is HIGH. The address presented to the address inputs is

stored into the address advancement logic and the Address

sponding data is allowed to propagate to the input of the

Output Registers. At the rising edge of the next clock the data

is allowed to propagate through the output register and onto

the data bus within tco if OE is active LOW. The only exception

occurs when the SRAM is emerging from a deselected state

to a selected state, its outputs are always three-stated during

the first cycle of the access. After the first cycle of the access,

the outputs are controlled by the OE signal. Consecutive

single read cycles are supported.

The CY7C1340F is a double-cycle deselect part. Once the

SRAM is deselected at clock rise by the chip select and either

ADSP or ADSC signals, its output will three-state immediately

after the next clock rise.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions

are satisfied at clock rise: (1) ADSP is asserted LOW, and

(2) chip select is asserted active. The address presented is

loaded into the address register and the address

advancement logic while being delivered to the memory core.

The write signals (GW, BWE, and BW[A:D]) and ADV inputs are

ignored during this first cycle.

ADSP triggered write accesses require two clock cycles to

complete. If GW is asserted LOW on the second clock rise, the

data presented to the DQx inputs is written into the corre-

sponding address location in the memory core. If GW is HIGH,

then the write operation is controlled by BWE and BW[A:D]

signals. The CY7C1340F provides byte write capability that is

described in the Write Cycle Description table. Asserting the

Byte Write Enable input (BWE) with the selected Byte Write

input will selectively write to only the desired bytes. Bytes not

selected during a byte write operation will remain unaltered. A

synchronous self-timed write mechanism has been provided

to simplify the write operations.

Because the CY7C1340F is a common I/O device, the Output

Enable (OE) must be deasserted HIGH before presenting data

to the DQ inputs. Doing so will three-state the output drivers.

As a safety precaution, DQ are automatically three-stated

whenever a write cycle is detected, regardless of the state of

OE.

Single Write Accesses Initiated by ADSC

ADSC write accesses are initiated when the following condi-

tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is

deasserted HIGH, (3) chip select is asserted active, and

(4) the appropriate combination of the write inputs (GW, BWE,

and BW[A:D]) are asserted active to conduct a write to the

desired byte(s). ADSC triggered write accesses require a

single clock cycle to complete. The address presented is

loaded into the address register and the address

advancement logic while being delivered to the memory core.

The ADV input is ignored during this cycle. If a global write is

conducted, the data presented to the DQX is written into the

corresponding address location in the memory core. If a byte

write is conducted, only the selected bytes are written. Bytes

not selected during a byte write operation will remain

unaltered. A synchronous self-timed write mechanism has

been provided to simplify the write operations.

Because the CY7C1340F is a common I/O device, the Output

Enable (OE) must be deasserted HIGH before presenting data

to the DQX inputs. Doing so will three-state the output drivers.

As a safety precaution, DQX are automatically three-stated

whenever a write cycle is detected, regardless of the state of

OE.

VSSQ 5,10,21,26,

55,60,71,76

I/O Ground Ground for the I/O circuitry.

MODE 31 Input-

Static

Selects Burst Order. When tied to GND selects linear burst sequence. When tied

to VDD or left floating selects interleaved burst sequence. This is a strap pin and

should remain static during device operation. Mode Pin has an internal pull-up.

NC 14,16,38,39,

42,43,66,1,

30,51,80

No Connects. Not internally connected to the die.

Pin Descriptions (continued)

Pin TQFP Type Description

[+] Feedback

CY7C1340F

Document #: 38-05219 Rev. *A Page 6 of 17

Burst Sequences

The CY7C1340F provides a two-bit wraparound counter, fed

by A[1:0], that implements either an interleaved or linear burst

sequence. The interleaved burst sequence is designed specif-

ically to support Intel Pentium applications. The linear burst

sequence is designed to support processors that follow a

linear burst sequence. The burst sequence is user selectable

through the MODE input. Both read and write burst operations

are supported.

Asserting ADV LOW at clock rise will automatically increment

the burst counter to the next address in the burst sequence.

Both read and write burst operations are supported.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation “sleep” mode. Two

clock cycles are required to enter into or exit from this “sleep”

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the “sleep” mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected prior to entering

the “sleep” mode. CEs, ADSP, and ADSC must remain

inactive for the duration of tZZREC after the ZZ input returns

LOW.

Interleaved Burst Address Table

(MODE = Floating or VDD)

First

Address

A1, A0

Second

Address

A1, A0

Third

Address

A1, A0

Fourth

Address

A1, A0

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

Linear Burst Address Table

(MODE = GND)

First

Address

A1, A0

Second

Address

A1, A0

Third

Address

A1, A0

Fourth

Address

A1, A0

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min. Max. Unit

IDDZZ Snooze mode standby current ZZ > VDD − 0.2V 40 mA

tZZ Device operation to ZZ ZZ > VDD − 0.2V 2tCYC ns

tZZREC ZZ recovery time ZZ < 0.2V 2tCYC ns

tZZI ZZ Active to snooze current This parameter is sampled 2tCYC ns

tRZZI ZZ inactive to exit snooze current This parameter is sampled 0 ns

[+] Feedback

CY7C1340F

Document #: 38-05219 Rev. *A Page 7 of 17

Truth Table [2, 3, 4, 5, 6]

Operation

Address

Used CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ

Deselected Cycle, Power Down None H X X L X L X X X L-H Three-State

Deselected Cycle, Power Down None L L X L L X X X X L-H Three-State

Deselected Cycle, Power Down None L X H L L X X X X L-H Three-State

Deselected Cycle, Power Down None L L X L H L X X X L-H Three-State

Deselected Cycle, Power Down None L X H L H L X X X L-H Three-State

ZZ Mode, Power-Down None X X X H X X X X X X Three-State

Read Cycle, Begin Burst External L H L L L X X X L L-H Q

Read Cycle, Begin Burst External L H L L L X X X H L-H Three-State

Write Cycle, Begin Burst External L H L L H L X L X L-H D

Read Cycle, Begin Burst External L H L L H L X H L L-H Q

Read Cycle, Begin Burst External L H L L H L X H H L-H Three-State

Read Cycle, Continue Burst Next X X X L H H L H L L-H Q

Read Cycle, Continue Burst Next X X X L H H L H H L-H Three-State

Read Cycle, Continue Burst Next H X X L X H L H L L-H Q

Read Cycle, Continue Burst Next H X X L X H L H H L-H Three-State

Write Cycle, Continue Burst Next X X X L H H L L X L-H D

Write Cycle, Continue Burst Next H X X L X H L L X L-H D

Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q

Read Cycle, Suspend Burst Current X X X L H H H H H L-H Three-State

Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q

Read Cycle, Suspend Burst Current H X X L X H H H H L-H Three-State

Write Cycle, Suspend Burst Current X X X L H H H L X L-H D

Write Cycle, Suspend Burst Current H X X L X H H L X L-H D

Partial Truth Table for Read/Write[2, 7]

Function GW BWE BWABWBBWCBWD

Read H H X X X X

Read H L H H H H

Write byte A - DQAHLLHHH

Write byte B - DQBHLHLHH

Write byte C - DQCHLHHLH

Write byte D - DQDHLHHHL

Write all bytes H L L L L L

Write all bytes L X X X X X

Notes:

2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.

3. WRITE = L when any one or more Byte Write enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW = L. WRITE = H when all Byte write enable signals

(BWA, BWB, BWC, BWD), BWE, GW = H.

4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A:D]. Writes may occur only on subsequent clocks

after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is

a don't care for the remainder of the write cycle.

6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are three-state when OE

is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).

7. Table only lists a partial listing of the byte write combinations. Any combination of BW[A:D] is valid. Appropriate write will be done based on which byte write is

active.

[+] Feedback

CY7C1340F

Document #: 38-05219 Rev. *A Page 8 of 17

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature .................................... –65°C to +150°

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V

DC Voltage Applied to Outputs

in Three-State ..................................... –0.5V to VDDQ + 0.5V

DC Input Voltage....................................–0.5V to VDD + 0.5V

Current into Outputs (LOW) .........................................20 mA

Static Discharge Voltage............................................ >2001V

(per MIL-STD-883,Method 3015)

Latch -up Current..................................................... >200 mA

Operating Range

Range

Ambient

Temperature (TA)V

DD VDDQ

Commercial 0°C to +70°C 3.3V −5%/+10% 2.5V − 5%

to VDD

Industrial –40°C to +85°C

Electrical Characteristics Over the Operating Range[8, 9]

Parameter Description Test Conditions Min. Max. Unit

VDD Power Supply Voltage 3.135 3.6 V

VDDQ I/O Supply Voltage 2.375 VDD V

VOH Output HIGH Voltage VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA 2.4 V

VDDQ = 2.5V, VDD = Min., IOH = –2.0 mA 2.0 V

VOL Output LOW Voltage VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA 0.4 V

VDDQ = 2.5V, VDD = Min., IOL = 2.0 mA 0.4 V

VIH Input HIGH Voltage[8] VDDQ = 3.3V 2.0 VDD + 0.3V V

VDDQ = 2.5V 1.7 VDD + 0.3V V

VIL Input LOW Voltage[8] VDDQ = 3.3V –0.3 0.8 V

VDDQ = 2.5V –0.3 0.7 V

IXInput Load Current except ZZ

and MODE

GND ≤ VI ≤ VDDQ –5 5 µA

Input Current of MODE Input = VSS –30 µA

Input = VDD 5µA

Input Current of ZZ Input = VSS –5 µA

Input = VDD 30 µA

IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled –5 5 µA

IDD VDD Operating Supply Cur-

rent

VDD = Max., IOUT = 0 mA,

f = fMAX = 1/tCYC

4-ns cycle, 250 MHz 325 mA

4.4-ns cycle, 225 MHz 290 mA

5-ns cycle, 200 MHz 265 mA

6-ns cycle, 166 MHz 240 mA

7.5-ns cycle, 133 MHz 225 mA

10-ns cycle, 100 MHz 205 mA

ISB1 Automatic CE

Power-down

Current—TTL Inputs

VDD = Max., Device Deselected,

VIN ≥ VIH or VIN ≤ VIL, f = fMAX =

1/tCYC

4-ns cycle, 250 MHz 120 mA

4.4-ns cycle, 225 MHz 115 mA

5-ns cycle, 200 MHz 110 mA

6-ns cycle, 166 MHz 100 mA

7.5-ns cycle, 133 MHz 90 mA

10-ns cycle, 100 MHz 80 mA

Shaded areas contain advance information.

Notes:

8. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> –2V (Pulse width less than tCYC/2).

9. TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

[+] Feedback

CY7C1340F

Document #: 38-05219 Rev. *A Page 9 of 17

ISB2 Automatic CE

Power-down

Current—CMOS Inputs

VDD = Max., Device Deselected,

VIN ≤ 0.3V or VIN > VDDQ – 0.3V,

f = 0

All speeds 40 mA

ISB3 Automatic CE

Power-down

Current—CMOS Inputs

VDD = Max., Device Deselected,

or VIN ≤ 0.3V or VIN > VDDQ –

0.3V, f = fMAX = 1/tCYC

4-ns cycle, 250 MHz 105 mA

4.4-ns cycle, 225 MHz 100 mA

5-ns cycle, 200 MHz 95 mA

6-ns cycle, 166 MHz 85 mA

7.5-ns cycle, 133 MHz 75 mA

10-ns cycle, 100 MHz 65 mA

ISB4 Automatic CE Power-down

Current—TTL Inputs

VDD = Max., Device Deselected,

VIN ≥ VIH or VIN ≤ VIL, f = 0

All speeds 45 mA

Electrical Characteristics Over the Operating Range[8, 9]

Parameter Description Test Conditions Min. Max. Unit

Thermal Characteristics[10]

Parameter Description Test Conditions

TQFP

Package Unit

ΘJA Thermal Resistance

(Junction to Ambient)

Test conditions follow standard test

methods and procedures for measuring

thermal impedance, per EIA / JESD51.

41.83 °C/W

ΘJC Thermal Resistance

(Junction to case)

9.99 °C/W

Capacitance[10]

Parameter Description Test Conditions Max. Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz,

VDD = 3.3V

VDDQ = 3.3V

5pF

CCLK Clock Input Capacitance 5 pF

CI/O Input/Output Capacitance 5 pF

Note:

10. Tested initially and after any design or process change that may affect these parameters.

[+] Feedback

CY7C1340F

Document #: 38-05219 Rev. *A Page 10 of 17

AC Test Loads and Waveforms

OUTPUT

R = 317Ω

R = 351Ω

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT

RL= 50Ω

Z0= 50Ω

= 1.5V

3.3V ALL INPUT PULSES

VDD

GND

90%

10%

90%

10%

≤1ns ≤1ns

(c)

OUTPUT

R = 1667Ω

R =1538Ω

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT

RL= 50Ω

Z0= 50Ω

VL= 1.25V

2.5V ALL INPUT PULSES

VDD

GND

90%

10%

90%

10%

≤1ns ≤1ns

(c)

3.3V I/O Test Load

2.5V I/O Test Load

[+] Feedback

CY7C1340F

Document #: 38-05219 Rev. *A Page 11 of 17

Switching Characteristics Over the Operating Range [15, 16]

Parameter Description

250 MHz 225 MHz 200 MHz 166 MHz 133 MHz 100 MHz

UnitMin. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.

tPOWER VDD(Typical) to the first Access[11] 1.0 1.0 1.0 1.0 1.0 1.0 ms

Clock

tCYC Clock Cycle Time 4.0 4.4 5.0 6.0 7.5 10 ns

tCH Clock HIGH 1.7 2.0 2.0 2.5 3.0 3.5 ns

tCL Clock LOW 1.7 2.0 2.0 2.5 3.0 3.5 ns

Output Times

tCO Data Output Valid After CLK Rise 2.6 2.6 2.8 3.5 4.0 4.5 ns

tDOH Data Output Hold After CLK Rise 1.0 1.0 1.0 2.0 2.0 2.0 ns

tCLZ Clock to Low-Z[12, 13, 14] 0 0 0 0 0 0 ns

tCHZ Clock to High-Z[12, 13, 14] 2.6 2.6 2.8 3.5 4.0 4.5 ns

tOEV OE LOW to Output Valid 2.6 2.6 2.8 3.5 4.5 4.5 ns

tOELZ OE LOW to Output Low-Z[12, 13, 14] 0 0 0 0 0 0 ns

tOEHZ OE HIGH to Output

High-Z[12, 13, 14] 2.6 2.6 2.8 3.5 4.0 4.5 ns

Set-up Times

tAS Address Set-up Before CLK Rise 0.8 1.2 1.2 1.5 1.5 1.5 ns

tADS ADSC, ADSP Set-up Before CLK

Rise

0.8 1.2 1.2 1.5 1.5 1.5 ns

tADVS ADV Set-up Before CLK Rise 0.8 1.2 1.2 1.5 1.5 1.5 ns

tWES GW, BWE, BW[A:D] Set-up Before

CLK Rise

0.8 1.2 1.2 1.5 1.5 1.5 ns

tDS Data Input Set-up Before CLK

Rise

0.8 1.2 1.2 1.5 1.5 1.5 ns

tCES Chip Enable Set-up Before CLK

Rise

0.8 1.2 1.2 1.5 1.5 1.5 ns

Hold Times

tAH Address Hold After CLK Rise 0.4 0.5 0.5 0.5 0.5 0.5 ns

tADH ADSP , ADSC Hold After CLK Rise 0.4 0.5 0.5 0.5 0.5 0.5 ns

tADVH ADV Hold After CLK Rise 0.4 0.5 0.5 0.5 0.5 0.5 ns

tWEH GW,BWE, BW[A:D] Hold After CLK

Rise

0.4 0.5 0.5 0.5 0.5 0.5 ns

tDH Data Input Hold After CLK Rise 0.4 0.5 0.5 0.5 0.5 0.5 ns

tCEH Chip Enable Hold After CLK Rise 0.4 0.5 0.5 0.5 0.5 0.5 ns

Shaded areas contain advance information.

Notes:

11. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD minimum initially before a read or write operation

can be initiated.

12. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

13. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same

data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed

to achieve High-Z prior to Low-Z under the same system conditions.

14. This parameter is sampled and not 100% tested.

15. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.

16. Test conditions shown in (a) of AC Test Loads unless otherwise noted.

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CY7C1340F

Document #: 38-05219 Rev. *A Page 12 of 17

Switching Waveforms

Read Timing[17]

Note:

17. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

tCYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

ADSC

tAH

tAS

tCEH

tCES

GW, BWE,BW

Data Out (Q) High-Z

tDOH

tCO

ADV

tOEHZ

tCO

Single READ BURST READ

tOEV

tOELZ tCHZ

Burst wraps around

to its initial state

tADVH

tADVS

tWEH

tWES

tADH

tADS

Q(A2) Q(A2 + 1) Q(A2 + 2)

Q(A1) Q(A2) Q(A2 + 1) Q(A3)Q(A2 + 3)

A2 A3

Deselect

cycle

Burst continued with

new base address

ADV suspends burst

DON’T CARE UNDEFINED

[A:D]

CLZ

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CY7C1340F

Document #: 38-05219 Rev. *A Page 13 of 17

Write Timing[17, 18]

Note:

18. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW.

Switching Waveforms (continued)

tCYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

ADSC

tAH

tAS

tCEH

tCES

BWE,

BW[A:D]

ADV

BURST READ BURST WRITE

D(A2) D(A2 + 1) D(A2 + 1) D(A3) D(A3 + 1) D(A3 + 2)D(A2 + 3)

A2 A3

Extended BURST WRITE

D(A2 + 2)

Single WRITE

tADH

tADS

tADH

tADS

OEHZ

tADVH

tADVS

tWEH

tWES

tDH

tDS

tWEH

tWES

Byte write signals are ignored for first cycle when

ADSP initiates burst

ADSC extends burst

ADV suspends burst

DON’T CARE UNDEFINED

D(A1)

High-Z

Data in (D)

Data Out (Q)

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CY7C1340F

Document #: 38-05219 Rev. *A Page 14 of 17

Read/Write Timing[17, 19, 20]

Notes:

19. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.

20. GW is HIGH.

Switching Waveforms (continued)

CYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

ADSC

tAH

tAS

tCEH

tCES

Data Out (Q) High-Z

ADV

Single WRITE

D(A3)

A4 A5 A6

D(A5) D(A6)

Data In (D)

BURST READBack-to-Back READs

High-Z

Q(A2)Q(A1) Q(A4) Q(A4+1) Q(A4+2)

tWEH

tWES

Q(A4+3)

tOEHZ

tDH

tDS

tOELZ

tCLZ

tCO

Back-to-Back

WRITEs

BWE, BW

[A:D]

DON’T CARE UNDEFINED

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CY7C1340F

Document #: 38-05219 Rev. *A Page 15 of 17

Notes:

21. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.

22. DQs are in high-Z when exiting ZZ sleep mode.

Switching Waveforms (continued)

tZZ

ISUPPLY

CLK

tZZREC

LL INPUTS

(except ZZ)

DON’T CARE

IDDZZ

tZZI

tRZZI

Outputs (Q) High-Z

DESELECT or READ Only

Z Mode Timing [21, 22]

Ordering Information

Speed

(MHz) Ordering Code

Package

Name Package Type

Operating

Range

250 CY7C1340F-250AC A101 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Commercial

CY7C1340F-250AI A101 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Industrial

225 CY7C1340F-225AC A101 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Commercial

CY7C1340F-225AI A101 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Industrial

200 CY7C1340F-200AC A101 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Commercial

CY7C1340F-200AI A101 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Industrial

166 CY7C1340F-166AC A101 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Commercial

CY7C1340F-166AI A101 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Industrial

133 CY7C1340F-133AC A101 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Commercial

CY7C1340F-133AI A101 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Industrial

100 CY7C1340F-100AC A101 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Commercial

CY7C1340F-100AI A101 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Industrial

Shaded area contains advance information.

Please contact your local Cypress sales representative for availability of these parts.

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CY7C1340F

Document #: 38-05219 Rev. *A Page 16 of 17

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Intel and Pentium are registered trademarks, and i486 is a trademark, of Intel Corporation. PowerPC is a registered trademark

of IBM. All product and company names mentioned in this document are the trademarks of their respective holders.

Package Diagram

100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101

51-85050-*A

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CY7C1340F

Document #: 38-05219 Rev. *A Page 17 of 17

Document History Page

Document Title: CY7C1340F 4-Mb (128K x 32) Pipelined DCD Sync SRAM

Document Number: 38-05219

REV. ECN NO. Issue Date

Orig. of

Change Description of Change

** 119827 12/16/02 HGK New Data Sheet

*A 200143 See ECN SWI Final Data Sheet

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