VGAH222022Y490DP - AVX - Datasheet.Live

LT6411

6411f

TYPICAL APPLICATION

FEATURES

APPLICATIONS

DESCRIPTION

650MHz Differential ADC

Driver/Dual Selectable

Gain Ampliﬁ er

The LT

6411 is a dual ampliﬁ er with individually selectable

gains of +1, +2 and –1. The ampliﬁ ers have excellent dis-

tortion performance for driving ADCs as well as excellent

bandwidth and slew rate for video, data transmission and

other high speed applications. Single-ended to differential

conversion with a system gain of 2 is particularly straight-

forward by conﬁ guring one ampliﬁ er with a gain of +1

and the other ampliﬁ er with a gain of –1. The LT6411 can

be used on split supplies as large as ±6V and on a single

supply as low as 4.5V.

Each ampliﬁ er draws only 8mA of quiescent current when

enabled. When disabled, the output pins become high

impedance and each ampliﬁ er draws less than 350µA.

The LT6411 is manufactured on Linear Technology’s

proprietary, low voltage, complimentary, bipolar process

and is available in the ultra-compact, 3mm × 3mm, 16pin

QFN package.

■ 650MHz –3dB Small-Signal Bandwidth

■ 600MHz –3dB Large-Signal Bandwidth

■ High Slew Rate: 3300V/µs

■ Easily Conﬁ gured for Single-Ended to Differential

Conversion

■ 200MHz ±0.1dB Bandwidth

■ User Selectable Gain of +1, +2 and –1

■ No External Resistors Required

■ 46.5dBm Equivalent OIP3 at 30MHz When Driving an

ADC

■ IM3 with 2VP-P Composite, Differential Output:

–87dBc at 30MHz, –83dBc at 70MHz

■ –77dB SFDR at 30MHz, 2VP-P Differential Output

■ 6ns 0.1% Settling Time for 2V Step

■ Low Supply Current: 8mA per Ampiﬁ er

■ Differential Gain of 0.02%, Differential Phase of 0.01°

■ 50dB Channel Separation at 100MHz

■ Wide Supply Range: ±2.25V (4.5V) to ±6.3V (12.6V)

■ 3mm × 3mm 16-Pin QFN Package

■ Differential ADC Driver

■ Single-Ended to Differential Conversion

■ Differential Video Line Driver

Differential ADC Driver

30MHz 2-Tone 32768 Point FFT, LT6411

Driving an LTC

2249 14-Bit ADC

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

AIN–

6411 TA01a

LTC2249

14-BIT ADC

80Msps

AIN+

–

VCC

VEE

DGND

LT6411

30MHz

1.9VDC

INPUT

370Ω370Ω

24Ω

370Ω370Ω

FREQUENCY (MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–40

515 20 40

6411 TA01b

–20

–60

–130

–110

–90

–10

–50

–30

–70

10 25 30 35

32768 POINT FFT

TONE 1 AT 29.5MHz, –7dBFS

TONE 2 AT 30.5MHz, –7dBFS

IM3 = –87dBc

LT6411

6411f

ELECTRICAL CHARACTERISTICS

PACKAGE/ORDER INFORMATIONABSOLUTE MAXIMUM RATINGS

Total Supply Voltage (VCC to VEE) ..........................12.6V

Input Current (Note 2) ..........................................±10mA

Output Current (Continuous) ...............................±70mA

EN to DGND Voltage (Note 2) ..................................5.5V

Output Short-Circuit Duration (Note 3) ............ Indeﬁ nite

Operating Temperature Range (Note 4) ... –40°C to 85°C

Speciﬁ ed Temperature Range (Note 5) .... –40°C to 85°C

Storage Temperature Range ................... –65°C to 125°C

Junction Temperature ........................................... 125°C

(Note 1)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOS Input Referred Offset Voltage VIN = 0V, VOS = VOUT/2

●

3 ±10

±20

IIN Input Current ●–17 ±50 µA

RIN Input Resistance VIN = ±1V ●150 500 kΩ

CIN Input Capacitance f = 100kHz 1 pF

VCMR Maximum Input Common Mode Voltage

Minimum Input Common Mode Voltage

VCC – 1

VEE + 1

PSRR Power Supply Rejection Ratio VS (Total) = 4.5V to 12V (Note 6) ●56 62 dB

IPSRR Input Current Power Supply Rejection VS (Total) = 4.5V to 12V (Note 6) ●1 ±4 µA/V

AV ERR Gain Error VOUT = ±2V ●–1.2 ±5 %

AV MATCH Gain Matching VOUT = ±2V ±1 %

VOUT Maximum Output Voltage Swing RL = 1k

RL = 150Ω

RL = 150Ω●

±3.70

±3.25

±3.10

±3.95

±3.6

ISSupply Current, Per Ampliﬁ er

●

811

Supply Current, Disabled, per Ampliﬁ er VEN = 4V

VEN = Open

●

0.5

350

µA

IEN Enable Pin Current VEN = 0.4V

VEN = V+●

●

–200 –95

0.5 50

µA

DGND

VCC

VEE

IN2+

IN2–

IN1–

IN1+

OUT2

VCC

VEE

OUT1

5678

15 14

TOP VIEW

UD PACKAGE

16-LEAD (3mm × 3mm) PLASTIC QFN

TJMAX = 125°C, θJA = 68°C/W, θJC = 4.2°C/W

EXPOSED PAD (PIN 17) IS VEE, MUST BE SOLDERED TO PCB

ORDER PART NUMBER UD PART MARKING*

LT6411CUD

LT6411IUD

LCGP

Order Options Tape and Reel: Add #TR

Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges.

*Temperature grade is identiﬁ ed by a label on the shipping container.

The ● denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VS = ±5V, AV = 2, RL = 150Ω, CL = 1.5pF, VEN = 0.4V, VDGND = 0V,

unless otherwise noted.

LT6411

6411f

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

ISC Output Short-Circuit Current RL = 0Ω, VIN = ±1V ●±50 ±105 mA

SR Slew Rate ±1V on ±2V Output Step (Note 9) 1700 3300 V/µs

–3dB BW Small-Signal –3dB Bandwidth VOUT = 200mVP-P

, Single Ended 650 MHz

0.1dB BW Gain Flatness ±0.1dB Bandwidth VOUT = 200mVP-P

, Single Ended 200 MHz

FPBW Full Power Bandwidth 2V Differential VOUT = 2VP-P Differential, –3dB 600 MHz

Full Power Bandwidth 2V VOUT = 2VP-P (Note 7) 270 525 MHz

Full Power Bandwidth 4V VOUT = 4VP-P (Note 7) 263 MHz

All Hostile Crosstalk f = 10MHz, VOUT = 2VP-P

f = 100MHz, VOUT = 2VP-P

–75

–50

tsSettling Time 0.1% to VFINAL, VSTEP = 2V 6 ns

tr, tfSmall-Signal Rise and Fall Time 10% to 90%, VOUT = 200mVP-P 550 ps

dG Differential Gain (Note 8) 0.02 %

dP Difﬁ erential Phase (Note 8) 0.01 Deg

ELECTRICAL CHARACTERISTICS

The ● denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VS = ±5V, AV = 2, RL = 150Ω, CL = 1.5pF, VEN = 0.4V, VDGND = 0V,

unless otherwise noted.

The ● denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C.

VCC = 5V, VEE = 0V, AV = 2, No RLOAD, VEN = 0.4V, VDGND = 0V, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Noise/Harmonic Performance Input/Output Characteristics

1MHz Signal

HD Second/Third Harmonic Distortion 2VP-P Differential

2VP-P Differential, RL = 200Ω Differential

–88

–87

dBc

IMD31M Third-Order IMD 2VP-P Differential Composite, f1 = 0.95MHz,

f2 = 1.05MHz

–93 dBc

2VP-P Differential Composite, f1 = 0.95MHz,

f2 = 1.05MHz, RL = 200Ω Differential

–91 dBc

OIP31M Output Third-Order Intercept Differential, f1 = 0.95MHz, f2 = 1.05MHz (Note 10) 49.5 dBm

NF Noise Figure Single Ended 25.1 dB

en1M Input Referred Noise Voltage Density 8 nV/√Hz

P1dB 1dB Compression Point (Note 10) 19.5 dBm

10MHz Signal

HD Second/Third Harmonic Distortion 2VP-P Differential

2VP-P Differential, RL = 200Ω Differential

–85

–76

dBc

IMD310M Third-Order IMD 2VP-P Differential Composite, RL = 1k,

f1 = 9.5MHz, f2 = 10.5MHz

–92 dBc

2VP-P Differential Composite, f1 = 9.5MHz,

f2 = 10.5MHz, RL = 200Ω Differential

–89 dBc

OIP310M Output Third-Order Intercept Differential, f1 = 9.5MHz, f2 = 10.5MHz (Note 10) 49 dBm

NF Noise Figure Single Ended 24.7 dB

en10M Input Referred Noise Voltage Density 7.7 nV/√Hz

P1dB 1dB Compression Point (Note 10) 19.5 dBm

LT6411

6411f

ELECTRICAL CHARACTERISTICS

The ● denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VCC = 5V, VEE = 0V, AV = 2, No RLOAD, VEN = 0.4V, VDGND = 0V,

unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

30MHz Signal

HD Second/Third Harmonic Distortion 2VP-P Differential

2VP-P Differential, RL = 200Ω Differential

–77

–64

dBc

IMD330M Third-Order IMD 2VP-P Differential Composite, f1 = 29.5MHz,

Differential, f2 = 30.5MHz

–87 dBc

2VP-P Differential Composite, f1 = 29.5MHz,

f2 = 30.5MHz, RL = 200Ω Differential

–75 dBc

OIP330M Output Third-Order Intercept Differential, f1 = 29.5MHz, f2 = 30.5MHz (Note 10) 46.5 dBm

NF Noise Figure Single Ended 24.6 dB

en30M Input Referred Noise Voltage Density 7.6 nV/√Hz

P1dB 1dB Compression Point (Note 10) 19.5 dBm

70MHz Signal

HD Second/Third Harmonic Distortion 2VP-P Differential

2VP-P Differential, RL = 200Ω Differential

–63

–52

dBc

IMD370M Third-Order IMD 2VP-P Differential Composite, f1 = 69.5MHz,

Differential, f2 = 70.5MHz

–83 dBc

2VP-P Differential Composite, f1 = 69.5MHz,

f2 = 70.5MHz, RL = 200Ω Differential

–64 dBc

OIP370M Output Third-Order Intercept Differential, f1 = 69.5MHz, f2 = 70.5MHz (Note 10) 44.5 dBm

NF Noise Figure Single Ended 24.7 dB

en70M Input Referred Noise Voltage Density 7.7 nV/√Hz

P1dB 1dB Compression Point (Note 10) 19.5 dBm

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: This parameter is guaranteed to meet speciﬁ ed performance

through design and characterization. It is not production tested.

Note 3: As long as output current and junction temperature are kept

below the Absolute Maximum Ratings, no damage to the part will occur.

Depending on the supply voltage, a heat sink may be required.

Note 4: The LT6411C is guaranteed functional over the operating

temperature range of –40°C to 85°C.

Note 5: The LT6411C is guaranteed to meet speciﬁ ed performance from

0°C to 70°C. The LT6411C is designed, characterized and expected to

meet speciﬁ ed performance from –40°C and 85°C but is not tested or

QA sampled at these temperatures. The LT6411I is guaranteed to meet

speciﬁ ed performance from –40°C to 85°C.

Note 6: The two supply voltage settings for power supply rejection

are shifted from the typical ±VS points for ease of testing. The ﬁ rst

measurement is taken at VCC = 3V, VEE = –1.5V to provide the required 3V

headroom for the enable circuitry to function with EN, DGND and all inputs

connected to 0V. The second measurement is taken at VCC = 8V, VEE = –4V.

Note 7: Full power bandwidth is calculated from the slew rate:

FPBW = SR/(π • V

P-P)

Note 8: Differential gain and phase are measured using a Tektronix

TSG120YC/NTSC signal generator and a Tektronix 1780R video

measurement set. The resolution of this equipment is better than 0.05%

and 0.05°. Ten identical ampliﬁ er stages were cascaded giving an effective

resolution of better than 0.005% and 0.005°.

Note 9: Slew rate is 100% production tested on channel 1. Slew rate of

channel 2 is guaranteed through design and characterization.

Note 10: Since the LT6411 is a feedback ampliﬁ er with low output

impedance, a resistive load is not required when driving an ADC.

Therefore, typical output power is very small. In order to compare the

LT6411 with typical gm ampliﬁ ers that require 50Ω output loading, the

LT6411 output voltage swing driving an ADC is converted to OIP3 and

P1dB as if it were driving a 50Ω load.

LT6411

6411f

TYPICAL PERFORMANCE CHARACTERISTICS

Supply Current per Ampliﬁ er

vs Temperature

Supply Current per Ampiﬁ er

vs Supply Voltage

Supply Current per Ampliﬁ er

vs EN Pin Voltage

Output Offset Voltage

vs Temperature

Positive Input Bias Current

vs Input Voltage EN Pin Current vs EN Pin Voltage

Output Voltage vs Input Voltage

Output Voltage Swing vs ILOAD

(Output High)

Output Voltage Swing vs ILOAD

(Output Low)

EN PIN VOLTAGE (V)

EN PIN CURRENT (µA)

–20

–40

–60

–80

–100

–120

–140

6411 G06

134

VS = ±5V

VDGND = 0V

TA = –55°C

TA = 25°C

TA = 125°C

SOURCE CURRENT (mA)

OUTPUT VOLTAGE (V)

040

6411 G08

10 20 30 10050 60 70 80 90

VS = ±5V

AV = 2

VIN = 2V

TA = 125°C

TA = –55°C

TA = 25°C

040

10 20 30 10050 60 70 80 90

SINK CURRENT (mA)

OUTPUT VOLTAGE (V)

–1

–2

–3

–4

–5

6411 G09

VS = ±5V

AV = 2

VIN = –2V

TA = 125°C

TA = –55°C

TA = 25°C

All measurements are per ampliﬁ er with single-ended outputs unless otherwise noted.

–55 –15 25 45

TEMPERATURE (°C)

125

6411 G01

–35 5 65 85 105

VEN = 0V

VEN = 0.4V

SUPPLY CURRENT (mA)

VS = ±5V

RL = ∞

VIN+, VIN– = 0V

6411 G02

SUPPLY CURRENT (mA)

00123456

TOTAL SUPPLY VOLTAGE (V)

7 8 9 10 11 12

VCC = –VEE

VEN, VDGND, VIN+, VIN– = 0V

TA = 25°C

6411 G03

SUPPLY CURRENT (mA)

0 0.5 1.0 1.5 2.0

EN PIN VOLTAGE (V)

2.5 3.0 3.5 4.0

TA = –55°C

TA = 25°C

TA = 125°C

VS = ±5V

VDGND = 0V

VIN+, VIN– = 0V

TEMPERATURE (°C)

OFFSET VOLTAGE (mV)

6411 G04

–5

–10

–15

–20

–55 –15 25 45 125

–35 5 65 85 105

VS = ±5V

VIN = 0V

AV = 2

INPUT VOLTAGE (V)

–2.5

IN+ BIAS CURRENT (µA)

–20

1.5

6411 G05

–40

–60 –1.5 –0.5 0.5 2.5

20 VS = ±5V

AV = 2

TA = –55°C

TA = 25°C

TA = 125°C

6411 G07

INPUT VOLTAGE (V)

–4.5

OUTPUT VOLTAGE (V)

–1

–2

–3

–4

–5 –2.5 –0.5 0.5 4.5

–3.5 –1.5 1.5 2.5 3.5

TA = 25°C

TA = –55°C

VS = ±5V

RL = 1k

AV = 1

TA = 125°C

LT6411

6411f

Input Noise Spectral Density

Positive Input Impedance

vs Frequency PSRR vs Frequency

Frequency Response

vs Gain Conﬁ guration Gain Flatness vs Frequency

Frequency Response with

Capacitive Loads

Harmonic Distortion vs Frequency,

Differential Input

Harmonic Distortion vs Amplitude,

30MHz, Differential Input

Harmonic Distortion vs Load,

30MHz, Differential Input

TYPICAL PERFORMANCE CHARACTERISTICS

All measurements are per ampliﬁ er with single-ended outputs unless otherwise noted.

6553 G10

FREQUENCY (kHz)

0.001 0.01 1 10 1000.1

1000

100

INPUT NOISE (nV/√Hz OR pA/√Hz)

VS = ±5V

AV = 2

TA = 25°C

6411 G11

FREQUENCY (MHz)

0.01 0.1

INPUT IMPEDANCE (kΩ)

10 100 10001

1000

100

0.1

VS = ±5V

VIN = 0V

TA = 25°C

6411 G12

FREQUENCY (MHz)

REJECTION RATIO (dB)

0.001 0.01 1 10 1000.1

VS = ±5V

AV = 2

TA = 25°C

–PSRR

+PSRR

±PSRR

FREQUENCY (MHz)

–3

GAIN (dB)

0.1 10 100 1000

6411 G13

–6

AV = 2, VOUT = 200mVP-P

AV = 1, AV = –1,VOUT = 200mVP-P

AV = 2, VOUT = 2VP-P

AV = 1, VOUT = 2VP-P

AV = –1, VOUT = 2VP-P

VS = ±5V

RL = 150Ω

TA = 25°C

FREQUENCY (MHz)

5.8

NORMALIZED GAIN (dB)

6.4

6.5

5.7

5.6

6.3

6.0

6.2

6.1

5.9

0.1 10 100 1000

6411 G14

5.5

CHANNEL 1

CHANNEL 2

VS = ±5V

AV = 2

VOUT = 200mVP-P

RL = 150Ω

TA = 25°C

FREQUENCY (MHz)

AMPLITUDE (dB)

–2

–4

–6

6553 G15

0.1 1 10 100 1000

CL = 12pF

CL = 6.8pF

CL = 2.2pF

VS = ±5V

AV = 2

VOUT = 2VP-P

RL = 150Ω

TA = 25°C

FREQUENCY (MHz)

–100

DISTORTION (dBc)

–80

–60

–40

–20

10 100

6411 G16

0VOUT = 2VP-P, DIFFERENTIAL

AV = 2, VCC = 5V

VEE = 0V, VCM = 1.6V

DIFFERENTIAL RLOAD

TA = 25°C

–90

–70

–50

–30

–10

HD3, RL = 200Ω

HD3, RL = ∞

HD2, RL = ∞

HD2, RL = 200Ω

DIFFERENTIAL OUTPUT AMPLITUDE (VP-P)

0.4

–100

DISTORTION (dBc)

–90

–70

–60

–50

–30

0.8 1.2 1.4

6411 G17

–80

–20

–10

–40

0.6 1.0 1.6

HD3

HD2

1.8 2.0

AV = 2, VCC = 5V

VEE = 0V, VCM = 1.6V

RL = ∞

TA = 25°C

DIFFERENTIAL RLOAD (Ω)

DISTORTION (dBc)

–40

–20

800

1011 G06

–60

–80

–50

–30

–10

–70

–90

–100 200100 400300 600

HD3

HD2

700 900

500 1000

VOUT = 2VP-P, DIFFERENTIAL

AV = 2, VCC = 5V

VEE = 0V, VCM = 1.6V

TA = 25°C

LT6411

6411f

Third Order Intermodulation

Distortion vs Frequency,

Differential Input

Output Third Order Intercept

vs Frequency, Differential Input Output Impedance vs Frequency

Small-Signal Transient Response

Video Amplitude Transient

Response Large-Signal Transient Response

Crosstalk vs Frequency Gain Error Distribution Gain Matching Distribution

6411 G21

FREQUENCY (MHz)

0.01

100

OUTPUT IMPEDANCE (Ω)

100

0.1 0.1 110 100

1000

DISABLED

VEN = 4V

ENABLED

VEN = 0.4V VS = ±5V

RL = 150Ω

TA = 25°C

–3.0 0 2.0 3.0–2.0 –1.0 1.0

GAIN MATCHING–BETWEEN CHANNELS (%)

PERCENT OF UNITS (%)

6411 G27

VS = ±5V

VOUT = ±2V

RL = 150Ω

TA = 25°C

TYPICAL PERFORMANCE CHARACTERISTICS

All measurements are per ampliﬁ er with single-ended outputs unless otherwise noted.

FREQUENCY (MHz)

–100

THIRD ORDER IMD (dBc)

–90

–70

–60

–50

–30

20 40 50

6411 G19

–80

–20

–10

–40

10 30 60 70

RL = 200Ω

RL = ∞

VOUT = 2VP-P, COMPOSITE, DIFFERENTIAL

1MHz TONE SPACING

AV = 2, VCC = 5V

VEE = 0V, VCM = 1.6V

DIFFERENTIAL RLOAD

TA = 25°C

FREQUENCY (MHz)

OIP3 (dBm)

30 50

6411 G20

10 20 40 60 70

RL = ∞

COMPUTED FOR 50Ω ENVIRONMENT

RL = 200Ω

VOUT = 2VP-P, COMPOSITE, DIFFERENTIAL

1MHz TONE SPACING

AV = 2, VCC = 5V

VEE = 0V, VCM = 1.6V

DIFFERENTIAL RLOAD

TA = 25°C

TIME (ns)

OUTPUT (V)

0.15

0.10

0.05

–0.05

–0.10

–0.15 4 8 12 16

6411 G22

2020 6 10 14 18

VIN = 100mVP-P

AV = 2

VS = ±5V

RL = 150Ω

TA = 25°C

TIME (ns)

OUTPUT (V)

1.0

1.5

2.0

6411 G23

0.5

–0.5 246810

12 14 18 20

VIN = 700mVP-P

AV = 2

VS = ±5V

RL = 150Ω

TA = 25°C

TIME (ns)

OUTPUT (V)

–1

–2

–3

– 4

6411 G24

4 8 12 20142 6 10 18

VIN = 2.5VP-P

AV = 2

VS = ±5V

RL = 150Ω

TA = 25°C

FREQUENCY (MHz)

–120

AMPLITUDE (dB)

–100

–80

–60

–40

10 100

1635 G25

1000

–20

VS = ±5V

VOUT = 2VP-P

RL = 150Ω

TA = 25°C

DRIVE 2

LISTEN 1

DRIVE 1

LISTEN 2

GAIN ERROR–INDIVIDUAL CHANNEL (%)

–3.0

PERCENT OF UNITS (%)

3.0

6411 G26

0–2.0 –1.0 01.0 2.0

VS = ±5V

VOUT = ±2V

RL = 150Ω

TA = 25°C

LT6411

6411f

PIN FUNCTIONS

VEE (Pins 1, 2): Negative Supply Voltage. VEE pins are not

internally connected to each other and must all be con-

nected externally. Proper supply bypassing is necessary

for best performance. See the Applications Information

section.

VEE (Pins 3, 7): Negative Supply Voltage for Output Stage.

VEE pins are not internally connected to each other and

must all be connected externally. Proper supply bypassing

is necessary for best performance. See the Applications

Information section.

NC (Pin 4): This pin is not internally connected.

OUT2 (Pin 5): Output of Channel 2. The gain between the

input and the output of this channel is set by the connection

of the channel 2 input pins. See Table 1 in Applications

Information for details.

VCC (Pins 6, 9): Positive Supply Voltage for Output Stage.

VCC pins are not internally connected to each other and

must all be connected externally. Proper supply bypassing

is necessary for best performance. See the Applications

Information section.

OUT1 (Pin 8): Output of Channel 1. The gain between the

input and the output of this channel is set by the connection

of the channel 1 input pins. See Table 1 in Applications

Information for details.

VCC (Pin 10): Positive Supply Voltage. VCC pins are not

internally connected to each other and must all be con-

nected externally. Proper supply bypassing is necessary

for best performance. See the Applications Information

section.

EN (Pin 11): Enable Control Pin. An internal pull-up resis-

tor of 46k will turn the part off if the pin is allowed to ﬂ oat

and deﬁ nes the pin’s impedance. When the pin is pulled

low, the part is enabled.

DGND (Pin 12): Digital Ground Reference for Enable Pin.

This pin is normally connected to ground.

IN1+ (Pin 13): Channel 1 Positive Input. This pin has a

nominal impedance of 400kΩ and does not have an internal

termination resistor.

IN1– (Pin 14): This pin connects to the internal resistor

network of the channel 1 ampliﬁ er, connecting by a 370Ω

resistor to the inverting input.

IN2– (Pin 15): This pin connects to the internal resistor

network of the channel 2 ampliﬁ er, connecting by a 370Ω

resistor to the inverting input.

IN2+ (Pin 16): Channel 2 Positive Input. This pin has a

nominal impedance of 400kΩ and does not have an internal

termination resistor.

Exposed Pad (Pin 17): The pad is internally connected to

VEE (Pin 1). If split supplies are used, do not tie the pad

to ground.

LT6411

6411f

APPLICATIONS INFORMATION

Power Supplies

The LT6411 can be operated on as little as ±2.25V or a

single 4.5V supply and as much as ±6V or a single 12V

supply. Internally, each supply is independent to improve

channel isolation. Note that the Exposed Pad is internally

connected to VEE and must not be grounded when using

split supplies. Do not leave any supply pins disconnected

or the part may not function correctly!

Enable/Shutdown

The LT6411 has a TTL compatible shutdown mode con-

trolled by the EN pin and referenced to the DGND pin. If

the ampliﬁ er will be enabled at all times, the EN pin can

be connected directly to DGND. If the enable function is

desired, either driving the pin above 2V or allowing the

internal 46k pull-up resistor to pull the EN pin to the top

rail will disable the ampliﬁ er. When disabled, the DC output

impedance will rise to approximately 740Ω through the

internal feedback and gain resistors (assuming inputs at

ground). Supply current into the ampliﬁ er in the disabled

state will be primarily through VCC and approximately

equal to (VCC – VEN)/46k.

It is important that the two following constraints on the

DGND pin and the EN pin are always followed:

CC – VDGND ≥ 3V

–0.5V ≤ VEN – VDGND ≤ 5.5V

Split supplies of ±3V to ±5.5V will satisfy these require-

ments with DGND connected to 0V.

In dual supply cases with VCC less than 3V, DGND should

be connected to a potential below ground such as VEE.

Since the EN pin is referenced to DGND, it may need to be

pulled below ground in those cases. In order to protect the

internal enable circuitry, the EN pin should not be forced

more than 0.5V below DGND.

In single supply applications above 5.5V, an additional

resistor may be needed from the EN pin to DGND if the

pin is ever allowed to ﬂ oat. For example, on a 12V single

supply, a 33k resistor would protect the pin from ﬂ oating

too high while still allowing the internal pull-up resistor

to disable the part.

The DGND pin should not be pulled above the EN pin since

doing so will turn on an ESD protection diode. If the EN

pin voltage is forced a diode drop below the DGND pin,

current should be limited to 10mA or less.

The enable/disable times of the LT6411 are fast when

driven with a logic input. Turn on (from 50% EN input to

50% output) typically occurs in less than 50ns. Turn off

is slower, but is less than 300ns.

Gain Selection

The gain of the internal ampliﬁ ers of the LT6411 is conﬁ g-

ured by connecting the IN+ and IN– pins to the input signal

or ground in the combinations shown in Figure 1.

As shown in the Simpliﬁ ed Schematic, the IN– pins connect

to the internal gain resistor of each ampliﬁ er, and therefore,

each pin can be conﬁ gured independently. Floating the

IN– pins is not recommended as the parasitic capacitance

causes an AC gain of 2 at high frequencies, despite a DC

gain of +1. Both inputs are connected together in the gain

of +1 conﬁ guration to avoid this limitation.

–

–V

LT6411

IN+

AV = +2

IN–

OUT+

OUT–

–

–V

LT6411

IN+

AV = –1

IN–

OUT–

OUT+

6411 F01

–

–V

LT6411

IN+

AV = +1

IN–

OUT+

OUT–

Figure 1. LT6411 Conﬁ gured in Noninverting Gain of 2, Noninverting Gain of 1 and Inverting Gain of 1, All Shown with Dual Supplies

LT6411

6411f

APPLICATIONS INFORMATION

Input Considerations

The LT6411 input voltage range is from VEE + 1V to

VCC – 1V. Therefore, on split supplies the LT6411 input

range is always as large as or larger than the output swing.

On a single positive supply with a gain of +2 and IN– con-

nected to ground, however, the input range limit of +1V

limits the linear output low swing to 2V (1V multiplied by

the internal gain of 2).

The inputs can be driven beyond the point at which the

output clips so long as input currents are limited to

±10mA. Continuing to drive the input beyond the output

limit can result in increased current drive and slightly

increased swing, but will also increase supply current

and may result in delays in transient response at larger

levels of overdrive.

DC Biasing Differential Ampliﬁ er Applications

The inputs of the LT6411 must be DC biased within the

input common mode voltage range, typically VEE + 1V to

VCC – 1V. If the inputs are AC coupled or DC biased be-

yond the input voltage range of a driven A-to-D converter,

DC biasing or level shifting will be required. In the basic

circuit conﬁ gurations shown in Figure 1, the DC input

common mode voltage and the differential input signal

are both multiplied by the ampliﬁ er gain. In the gain of

+2 conﬁ guration, the DC common mode voltage gain can

be set to unity by adding a capacitor at the IN– pins as

shown in Figure 2.

If the inputs are AC coupled or the LT6411 is preceded

by a highpass ﬁ lter, the input common mode voltage can

be set by resistor dividers as shown in Figure 3. Adding

the blocking capacitor to the gain setting resistors sets

the input and output DC common mode voltages equal.

When using the LT6411 to drive an A-to-D converter, the

DC common mode voltage level will affect the harmonic

distortion of the combined ampliﬁ er/ADC system. Figure 4

shows the measured distortion of an LTC2249 ADC when

driven by the LT6411 at different common mode voltage

levels with the inputs conﬁ gured as shown in Figure 3.

Adjusting the DC bias voltage can optimize the design for

the lowest possible distortion.

If the input signals are within the input voltage range

and output swing of the LT6411, but outside the input

range of an ADC or other circuit the LT6411 is driving,

–

LT6411

IN+

IN–

CLARGE

VDC

OUT+

OUT–

VDC

6411 F02

Figure 2. LT6411 Conﬁ gured with a Differential Gain of 2

and Unity DC Common Mode Gain

–

LT6411

IN+

IN–

OUT+

OUT–

VDC

CLARGE

V+

VDC

6411 F03

Figure 3. Using Resistor Dividers to Set the

Input Common Mode Voltage When AC Coupling

VCM (V)

1.6

DISTORTION (dBc)

–70

–65 HD3

HD2

IM3

–60

2.4

6411 F04

–75

–80

–90 1.8 2.0 2.2

1.7 2.5

1.9 2.1 2.3

–85

–50

–55

VCC = 5V, VEE = 0V

AV= 2

TA = 25°C

Figure 4. Harmonic and Intermodulation Distortion of the

LT6411 Driving an LTC2249 Versus DC Common Mode

Voltage. Harmonic Distortion Measured with a –1dBFS Signal

at 30.2MHz. Intermodulation Distortion Measured with Two

–7dBFS Tones at 30.2MHz and 29.2MHz

LT6411

6411f

the output signals can be AC coupled and DC biased in a

manner similar to what is shown at the inputs in Figure

3. A simpler alternative when using an ADC such as the

LTC2249 is to use the ADC’s VCM pin to set the optimal

common mode voltage as shown in Figure 5.

If unity common mode gain and difference mode response

to DC is desired, there is another conﬁ guration available.

Figure 6 shows the LT6411 connected to provide a differ-

ential signal gain of +3 with unity common mode gain. For

differential signal gain between unity and +3, three resistors

can be added to provide attenuation and set the differential

input impedance of the stage as illustrated in Figure 7. The

general expression for the differential gain is:

VDIFF()

•

=+ +

Scaling factor ‘k’ is the multiple between the two equal-

value series input resistors and the resistor connected

between the two positive inputs. The correct value of R for

the external resistors can be computed from the desired

differential input impedance, ZIN, as a function of k and

the 370Ω internal gain setting resistors, as described in

the equation:

kZk

()

•

–

370

370 2 1

Ω

In Figure 7 k = 2 and R = 13.7Ω, setting the differential

gain to +2 and the differential input impedance to ap-

proximately 50Ω.

APPLICATIONS INFORMATION

–

–V

CLARGE

10k

LT6411

IN+

IN–

6411 F05

CLARGE

10k 2.2µF

LTC2249

VCM

–

LT6411

IN+

IN–

VCM

OUT+

OUT–

VCM

6411 F06

Figure 6. LT6411 Conﬁ gured for a Differential Gain of +3

and Unity Common Mode Gain with Response to DC

Figure 5. Level Shifting the Output Common Mode Voltage of the LT6411 Using the VCM Pin of an LTC2249

–

LT6411

IN+ R = 13.7Ω

R = 13.7Ω

IN–

k • R = 27.4Ω

VCM

OUT+

OUT–

VCM

6411 F07

Figure 7. LT6411 Conﬁ gured with a Differential Input Impedance

of 50Ω, a Differential Gain of +2 and Unity Common Mode Gain

LT6411

6411f

APPLICATIONS INFORMATION

Layout and Grounding

It is imperative that care is taken in PCB layout in order

to utilize the very high speed and very low crosstalk of

the LT6411. Separate power and ground planes are highly

recommended and trace lengths should be kept as short

as possible. If input or output traces must be run over a

distance of several centimeters, they should use a controlled

impedance with matching series and shunt resistances to

maintain signal ﬁ delity.

Series termination resistors should be placed as close to

the output pins as possible to minimize output capacitance.

See the Typical Performance Characteristics section for

a plot of frequency response with various output capaci-

tors—only 12pF of parasitic output capacitance causes

6dB of peaking in the frequency response!

Low ESL/ESR bypass capacitors should be placed as close

to the positive and negative supply pins as possible. One

4700pF ceramic capacitor is recommended for both VCC

and VEE. Additional 470pF ceramic capacitors with minimal

trace length on each supply pin will further improve AC

and transient response as well as channel isolation. For

high current drive and large-signal transient applications,

additional 1µF to 10µF tantalums should be added on each

supply. The smallest value capacitors should be placed

closest to the LT6411 package.

If the undriven input pins are not connected directly to a low

impedance ground plane, they must be carefully bypassed

to maintain minimal impedance over frequency. Although

crosstalk will be very dependent on the board layout, a

recommended starting point for bypass capacitors would

be 470pF as close as possible to each input pin with one

4700pF capacitor in parallel.

To maintain the LT6411’s channel isolation, it is beneﬁ cial

to shield parallel input and output traces using a ground

plane or power supply traces. Vias between topside

and backside metal may be required to maintain a low

inductance ground near the part where numerous traces

converge.

ESD Protection

The LT6411 has reverse-biased ESD protection diodes

on all pins. If any pins are forced a diode drop above the

positive supply or a diode drop below the negative sup-

ply, large currents may ﬂ ow through these diodes. If the

current is kept below 10mA, no damage to the devices

will occur.

Single-Ended to Differential Converter

Because the gains of each channel of the LT6411 can

be conﬁ gured independently, the LT6411 can be used to

provide a gain of +2 when amplifying differential signals

and when converting single-ended signals to differential.

With both channels connected to a single-ended input,

one channel conﬁ gured with a gain of +1 and the other

conﬁ gured with a gain of –1, the output will be a differential

version of the input with twice the peak-to-peak (differential)

amplitude. Figure 8 shows the proper connections and

Figure 9 displays the resulting performance when driv-

ing an LTC2249. This conﬁ guration can preserve signal

amplitude when converting single ended video signals to

differential signals when driving double terminated cables.

The 10k resistors in Figure 8 set the common mode volt-

age at the output. Figure 8. Single-Ended to Differential Converter

with Gain of +2 and Common Mode Control

TYPICAL APPLICATIONS

VCC

VEE

DGND

LT6411

OUT1

370Ω370Ω

OUT2

6411 F08

OUT+

OUT–

IN1+

IN1–

INPUT

1µF

IN2–

IN2+

10k0.1µF

–

10k

VCM

LT6411

6411f

TYPICAL APPLICATIONS

Figure 9. 2-Tone Response of the LT6411 Conﬁ gured with

Single-Ended Inputs Driving the LTC2249 at 29.5MHz, 30.5MHz

Twisted-Pair Line Driver

The LT6411 is ideal when used for driving inexpensive

unshielded twisted-pair wires as often found in telephone

or communications infrastructure. The input can be com-

posite video, or if three parts are used, RGB or similar and

can be either single ended or differential. The LT6411 has

excellent performance with all formats.

Double termination of the video cable will enhance ﬁ delity

and isolate the LT6411 from capacitive loads. Although

most twisted-pair cables have a characteristic impedance

Figure 10. Twisted-Pair Driver

FREQUENCY (MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–40

515 20 40

6411 F09

–20

–60

–130

–110

–90

–10

–50

–30

–70

10 25 30 35

32768 POINT FFT

TONE 1 AT 29.5MHz, –7dBFS

TONE 2 AT 30.5MHz, –7dBFS

IM3 = –90dBc

13 50Ω

100Ω

50Ω

–5V

6,9,10

1,2,3,7 6411 F10

RECEIVER

LT6411

AV = 2

IN+

IN–

–

11,12

of 100Ω, the cables can be terminated with a smaller

series resistance or a larger shunt resistance in order to

compensate for attenuation. A typical circuit for a twisted-

pair driver is shown in Figure 10.

Single Supply Differential ADC Driver

The LT6411 is well suited for driving differential analog

to digital converters. The low output impedance of the

LT6411 is capable of driving a variety of ﬁ lters as well as

interfacing with the typically high impedance inputs of

ADCs. In addition, the LT6411’s excellent distortion allows

the part to perform with an SFDR below the limits of many

high speed ADCs. The DC1057 demo board, shown sche-

matically in Figure 11 and physically in Figure 12, allows

implementation and testing of the LT6411 with a variety

of different Linear Technology high speed ADCs.

LT6411

6411f

TYPICAL APPLICATIONS

Figure 11. DC1057 Demo Circuit Schematic

Figure 12. Layout of DC1057 Demo Circuit

VCC

IN1+

CD4

0.1µF

C12

CD3

470pF

CD1

0.1µF

CD2

4700pF

9101112

12374

813

R10

VCC

R37

OPT

R13

R38

OPT

R14

R18

VEE

VCC

R17

OPT

VCC

10Ω

0603

10Ω

R12

10Ω

R35

12.1Ω

R36

12.1Ω

ADC

INPUTS

R11

10Ω

R19

0Ω

6411 F11

JP1

ENABLE

OPT

“B” CASE

VCC

GND

16 5

C6 C7

AIN+

AIN–

C10

TBD

0603

TBD

0603

TBD

0603

IN1–

IN2–

IN2+

OUT1

VEE

VCC

OUT2

VCC VCC

VEE

LT6411

EN DGND

VEE VEE VEE VEE NC

C31

OPT

“B” CASE

VEE

OPT

GND

C11

TBD

0603

OPT

0603

ETC1-1TTR

AIN+

AIN–

R16

0Ω

TBD

0603

CD5

470pF

CD8

0.1µF

0603

CD6

4700pF

CD7

1µF

LT6411

6411f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

SIMPLIFIED SCHEMATIC

VCC

VEE

VCC

46k

TO OTHER

AMPLIFIER

BIAS

IN+150Ω

370Ω

DGND

VEE

VCC

IN–

OUT

VEE

6411 SS

PACKAGE DESCRIPTION

UD Package

16-Lead Plastic QFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1691)

3.00 ± 0.10

(4 SIDES)

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

PIN 1

TOP MARK

(NOTE 6)

0.40 ± 0.10

BOTTOM VIEW—EXPOSED PAD

1.45 ± 0.10

(4-SIDES)

0.75 ± 0.05 R = 0.115

TYP

0.25 ± 0.05

PIN 1 NOTCH R = 0.20 TYP

OR 0.25 × 45° CHAMFER

15 16

0.50 BSC

0.200 REF

0.00 – 0.05

(UD16) QFN 0904

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

1.45 ± 0.05

(4 SIDES)

2.10 ± 0.05

3.50 ± 0.05

0.70 ±0.05

0.25 ±0.05

0.50 BSC

PACKAGE

OUTLINE

LT6411

6411f

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LT 0606 • PRINTED IN USA

RELATED PARTS

TYPICAL APPLICATION

PART NUMBER DESCRIPTION COMMENTS

LT1993-2 800MHz Low Distortion, Low Noise ADC Driver, AV = 2 3.8nV/√Hz Total Noise, Low Distortion to 100MHz

LT1993-4 900MHz Low Distortion, Low Noise ADC Driver, AV = 4 2.4nV/√Hz Total Noise, Low Distortion to 100MHz

LT1993-10 700MHz Low Distortion, Low Noise ADC Driver, AV = 10 1.9nV/√Hz Total Noise, Low Distortion to 100MHz

LT1994 Low Noise, Low Distortion Fully Differential Amplﬁ er 70MHz Gain Bandwidth Differential In and Out

LT6402-6 300MHz Low Distortion, Low Noise ADC Driver, AV = 2 3.8nV/√Hz Input Referred Noise, Low Distortion to 30MHz

LT6553 650MHz Gain of 2 Triple Video Ampliﬁ er Triple Ampliﬁ er with Fixed Gain

LT6554 650MHz Gain of 1 Triple Video Ampliﬁ er Triple Ampliﬁ er with Fixed Gain

In cases where lowering the noise ﬂ oor is paramount,

adding higher order lowpass or bandpass ﬁ ltering can

signiﬁ cantly increase signal-to-noise ratio. In Figure 13,

the LT6411 is shown driving an LTC2249 with a 2nd order

lowpass ﬁ lter that has been carefully chosen to ensure

optimal intermodulation distortion. The response is

shown in Figure 14. The ﬁ lter improves the SNR over the

unﬁ ltered case by 6dB to 69.5dB. With the ﬁ lter, the SNR

of the ADC and the LT6411 are comparable; better SNR

can be achieved by using either a higher resolution ADC

or additional ﬁ ltering. Figure 15 shows the corresponding

SFDR of –75.5dBc with a 30MHz tone. Figure 16 shows

the 2-tone response of the LT6411 with 29.5MHz and

30.5MHz inputs. Note that 0dBFS corresponds to a 2VP-P

differential signal.

Figure 13. Optimized 30MHz LT6411 Differential ADC Driver

Figure 15. SNR and SFDR of the LT6411 and Filter

Driving the LTC2249

Figure 16. 2-Tone Response of the LT6411 and Filter

Driving the LTC2249 at 29.5MHz, 30.5MHz

Figure 14. Frequency Response of the LT6411 and Filter

–

55Ω

80.6Ω

LT6411

390nH

LTC2249

390nH

55Ω

10Ω

AIN–

AIN+

10Ω

15pF

6411 F13

IN+

IN–

1.9VDC

FREQUENCY (MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–40

515 20 40

6411 F15

–20

–60

–130

–110

–90

–10

–50

–30

–70

10 25 30 35

8192 POINT FFT

fIN = 30MHz, –1dBFS

SNR = 69.5dB

SFDR = 75.5dB

FREQUENCY (MHz)

GAIN (dB)

10 100 1000

6411 F14

–3

–6

–9

–12

FREQUENCY (MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–40

515 20 40

6411 F16

–20

–60

–130

–110

–90

–10

–50

–30

–70

10 25 30 35

32768 POINT FFT

TONE 1 AT 29.5MHz, –7dBFS

TONE 2 AT 30.5MHz, –7dBFS

IM3 = –89.7dBc