IRF520 Data Sheet January 2002 9.2A, 100V, 0.270 Ohm, N-Channel Power MOSFET Features * 9.2A, 100V This N-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA09594. Ordering Information PART NUMBER * rDS(ON) = 0.270 * SOA is Power Dissipation Limited * Single Pulse Avalanche Energy Rated * Nanosecond Switching Speeds * Linear Transfer Characteristics * High Input Impedance * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards" Symbol PACKAGE BRAND D IRF520 TO-220AB IRF520 NOTE: When ordering, use the entire part number. G S Packaging JEDEC TO-220AB SOURCE DRAIN GATE DRAIN (FLANGE) (c)2002 Fairchild Semiconductor Corporation IRF520 Rev. B IRF520 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Dissipation Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg IRF520 100 100 9.2 6.5 37 20 60 0.4 36 -55 to 175 UNITS V V A A A V W W/oC mJ oC 300 260 oC oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BVDSS ID = 250A, VGS = 0V (Figure 10) 100 - - V Gate to Threshold Voltage VGS(TH) VGS = VDS, ID = 250A 2.0 - 4.0 V Zero Gate Voltage Drain Current IDSS On-State Drain Current (Note 2) ID(ON) Gate to Source Leakage Current IGSS Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) rDS(ON) gfs td(ON) tr td(OFF) - - 250 A - - 1000 A VDS > ID(ON) x rDS(ON)MAX, VGS = 10V (Figure 7) 9.2 - - A - - 100 nA - 0.25 0.27 2.7 4.1 - S VGS = 20V ID = 5.6A, VGS = 10V (Figure 8, 9) VDS 50V, ID = 5.6A (Figure 12) VDD = 50V, ID 9.2A, RG = 18, RL = 5.5 MOSFET Switching Times are Essentially Independent of Operating Temperature tf Qg(TOT) Gate to Source Charge Qgs Gate to Drain "Miller" Charge Qgd Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS Internal Drain Inductance VDS = 95V, VGS = 0V VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 150oC LD VGS = 10V, ID = 9.2A, VDS = 0.8 x Rated BVDSS, Ig(REF) = 1.5mA (Figure 14) Gate Charge is Essentially Independent of Operating Temperature VDS = 25V, VGS = 0V, f = 1MHz (Figure 11) Measured From the Contact Screw On Tab To Center of Die Measured From the Drain Lead, 6mm (0.25in) From Package to Center of Die Internal Source Inductance LS Thermal Resistance Junction to Case RJC Thermal Resistance Junction to Ambient RJA (c)2002 Fairchild Semiconductor Corporation Measured From the Source Lead, 6mm (0.25in) From Header to Source Bonding Pad Free Air Operation Modified MOSFET Symbol Showing the Internal Devices Inductances D - 9 13 ns - 30 63 ns - 18 70 ns - 20 59 ns - 10 30 nC - 2.5 - nC - 2.5 - nC - 350 - pF - 130 - pF - 25 - pF - 3.5 - nH - 4.5 - nH - 7.5 - nH - - 2.5 oC/W - - 80 oC/W LD G LS S IRF520 Rev. B IRF520 Source to Drain Diode Specifications PARAMETER SYMBOL Continuous Source to Drain Current ISD Pulse Source to Drain Current (Note 3) ISDM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode D MIN TYP MAX UNITS - - 9.2 A - - 37 A - - 2.5 V 5.5 100 240 ns 0.17 0.5 1.1 C G S Source to Drain Diode Voltage (Note 2) VSD Reverse Recovery Time trr Reverse Recovered Charge QRR TJ = 25oC, ISD = 9.2A, VGS = 0V (Figure 13) TJ = 25oC, ISD = 9.2A, dISD/dt = 100A/s TJ = 25oC, ISD = 9.2A, dISD/dt = 100A/s NOTES: 2. Pulse test: pulse width 300s, duty cycle 2%. 3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 25V, starting TJ = 25oC, L = 640mH, RG = 25, peak IAS = 9.2A. Unless Otherwise Specified 1.2 10 1.0 8 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER Typical Performance Curves 0.8 0.6 0.4 6 4 2 0.2 0 125 50 75 100 TC , CASE TEMPERATURE (oC) 25 0 150 175 0 25 50 75 100 125 175 150 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE ZJC, TRANSIENT THERMAL IMPEDANCE (oC/W) 10 1 0.5 0.2 0.1 0.1 PDM 0.05 0.02 0.01 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC + TC SINGLE PULSE 0.01 10-5 10-4 0.1 10-3 10-2 t1, RECTANGULAR PULSE DURATION (s) 1 10 FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE (c)2002 Fairchild Semiconductor Corporation IRF520 Rev. B IRF520 Typical Performance Curves Unless Otherwise Specified (Continued) 15 100 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 10s 100s 10 1ms 0.1 10ms OPERATION IN THIS AREA IS LIMITED BY rDS(ON) 1 TC = 25oC TJ = MAX RATED SINGLE PULSE 1 10V 12 VGS = 7V 9 VGS = 6V 6 VGS = 5V 3 VGS = 4V 0 10 100 VDS , DRAIN TO SOURCE VOLTAGE (V) 1000 0 20 10 40 30 VDS, DRAIN TO SOURCE VOLTAGE (V) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 10V VGS = 8V ID, DRAIN CURRENT (A) 12 VGS = 7V 9 VGS = 6V 6 3 VGS = 5V VGS = 4V 0 0 1 2 3 4 VDS, DRAIN TO SOURCE VOLTAGE (V) 102 VDS 50V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 10 1 175oC 0 2 4 6 10 8 VGS , GATE TO SOURCE VOLTAGE (V) FIGURE 7. TRANSFER CHARACTERISTICS 3.0 2.5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX NORMALIZED ON RESISTANCE rDS(ON), DRAIN TO SOURCE ON RESISTANCE 25oC 0.1 5 FIGURE 6. SATURATION CHARACTERISTICS 2.0 1.5 VGS = 10V 1.0 50 FIGURE 5. OUTPUT CHARACTERISTICS ID(ON), ON-STATE DRAIN CURRENT (A) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA 15 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 8V 0.5 2.4 ID = 9.2A, VGS = 10V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 1.8 1.2 0.6 VGS = 20V 0 0 8 24 16 ID, DRAIN CURRENT (A) 32 FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT (c)2002 Fairchild Semiconductor Corporation 40 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 TJ, JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE IRF520 Rev. B IRF520 Typical Performance Curves Unless Otherwise Specified (Continued) 1000 1.25 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD 1.15 800 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A 1.05 0.95 600 0.85 400 CISS 200 COSS CRSS 0.75 -60 60 0 120 0 180 TJ, JUNCTION TEMPERATURE (oC) VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 100 ISD, SOURCE TO DRAIN CURRENT (A) gfs, TRANSCONDUCTANCE (S) 5 TJ = 25oC 4 3 TJ = 175oC 2 1 VDS 50 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 0 0 3 6 9 ID, DRAIN CURRENT (A) 102 10 1 12 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 10 TJ = 175oC 1 TJ = 25oC 0.1 0 15 0.4 0.8 1.2 1.6 2.0 VSD, SOURCE TO DRAIN VOLTAGE (V) FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE VGS, GATE TO SOURCE VOLTAGE (V) 20 ID = 9.2A VDS = 20V VDS = 50V VDS = 80V 16 12 8 4 0 0 3 6 9 12 15 Qg, GATE CHARGE (nC) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE (c)2002 Fairchild Semiconductor Corporation IRF520 Rev. B IRF520 Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN IAS + RG REQUIRED PEAK IAS VDS VDD VDD - VGS DUT tP 0V IAS 0 0.01 tAV FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) td(OFF) tr RL VDS tf 90% 90% + RG - VDD 10% 0 10% DUT 90% VGS VGS 0 FIGURE 17. SWITCHING TIME TEST CIRCUIT 0.2F 50% PULSE WIDTH 10% FIGURE 18. RESISTIVE SWITCHING WAVEFORMS VDS (ISOLATED SUPPLY) CURRENT REGULATOR 12V BATTERY 50% VDD Qg(TOT) SAME TYPE AS DUT 50k Qgd 0.3F VGS Qgs D VDS DUT G 0 Ig(REF) S 0 IG CURRENT SAMPLING RESISTOR VDS ID CURRENT SAMPLING RESISTOR FIGURE 19. GATE CHARGE TEST CIRCUIT (c)2002 Fairchild Semiconductor Corporation IG(REF) 0 FIGURE 20. GATE CHARGE WAVEFORMS IRF520 Rev. B TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4