©2002 Fairchild Semiconductor Corporation IRF520 Rev. B
IRF520
9.2A, 100V, 0.270 Ohm, N-Channel
Power MOSFET
This N-Channel enhancement mode silicon gate power field
effect transistor is an advanced power MOSFET designed,
tested, and guaranteed to withstand a specified level of
energy in the breakdown avalanche mode of operation. All of
these power MOSFETs are designed for applications such
as switching regulators, switching convertors, motor drivers,
relay drivers, and drivers for high power bipolar switching
transistors requiring high speed and low gate drive power.
These types can be operated directly from integrated
circuits.
Formerly developmental type TA09594.
Features
• 9.2A, 100V
•r
DS(ON)
= 0.270
Ω
• SOA is Power Dissipation Limited
• Single Pulse Avalanche Energy Rated
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Packaging
JEDEC TO-220AB
Ordering Information
PART NUMBER PACKAGE BRAND
IRF520 TO-220AB IRF520
NOTE: When ordering, use the entire part number.
G
D
S
SOURCE
DRAIN (FLANGE)
DRAIN
GATE
Data Sheet January 2002
©2002 Fairchild Semiconductor Corporation IRF520 Rev. B
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
IRF520 UNITS
Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
DS
100 V
Drain to Gate Voltage (R
GS
= 20k
Ω)
(Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
100 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
T
C
= 100
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
9.2
6.5
A
A
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
37 A
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
GS
±
20 V
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P
D
60 W
Dissipation Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4 W/
o
C
Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E
AS
36 mJ
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J,
T
STG
-55 to 175
o
C
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
pkg
300
260
o
C
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 150
o
C.
Electrical Specifications
T
C
= 25
o
C, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BV
DSS
I
D
= 250
µ
A, V
GS
= 0V (Figure 10) 100 - - V
Gate to Threshold Voltage V
GS(TH)
V
GS
= V
DS
, I
D
= 250
µ
A 2.0 - 4.0 V
Zero Gate Voltage Drain Current I
DSS
V
DS
= 95V, V
GS
= 0V - - 250
µ
A
V
DS
= 0.8 x Rated BV
DSS
, V
GS
= 0V, T
J
= 150
o
C - - 1000
µ
A
On-State Drain Current (Note 2) I
D(ON)
V
DS
> I
D(ON)
x r
DS(ON)MAX
, V
GS
= 10V (Figure 7) 9.2 - - A
Gate to Source Leakage Current I
GSS
V
GS
=
±
20V - -
±
100 nA
Drain to Source On Resistance (Note 2) r
DS(ON)
I
D
= 5.6A, V
GS
= 10V (Figure 8, 9) - 0.25 0.27
Ω
Forward Transconductance (Note 2) gfs V
DS
≥
50V, I
D
= 5.6A (Figure 12) 2.7 4.1 - S
Turn-On Delay Time t
d(ON)
V
DD
= 50V, I
D
≈
9.2A, R
G
= 18
Ω
, R
L
= 5.5
Ω
MOSFET Switching Times are Essentially
Independent of Operating
Temperature
- 9 13 ns
Rise Time t
r
-3063ns
Turn-Off Delay Time t
d(OFF)
-1870ns
Fall Time t
f
-2059ns
Total Gate Charge
(Gate to Source + Gate to Drain)
Q
g(TOT)
V
GS
= 10V, I
D
= 9.2A, V
DS
= 0.8 x Rated BV
DSS
,
I
g(REF)
= 1.5mA (Figure 14) Gate Charge is
Essentially Independent of Operating
Temperature
-1030nC
Gate to Source Charge Q
gs
- 2.5 - nC
Gate to Drain “Miller” Charge Q
gd
- 2.5 - nC
Input Capacitance C
ISS
V
DS
= 25V, V
GS
= 0V, f = 1MHz
(Figure 11)
- 350 - pF
Output Capacitance C
OSS
- 130 - pF
Reverse Transfer Capacitance C
RSS
-25- pF
Internal Drain Inductance L
D
Measured From the Contact
Screw On Tab To Center of
Die
Modified MOSFET
Symbol Showing the
Internal Devices
Inductances
- 3.5 - nH
Measured From the Drain
Lead, 6mm (0.25in) From
Package to Center of Die
- 4.5 - nH
Internal Source Inductance L
S
Measured From the Source
Lead, 6mm (0.25in) From
Header to Source Bonding
Pad
- 7.5 - nH
Thermal Resistance Junction to Case R
θ
JC
- - 2.5
o
C/W
Thermal Resistance Junction to Ambient R
θ
JA
Free Air Operation - - 80
o
C/W
LD
LS
D
S
G
IRF520
©2002 Fairchild Semiconductor Corporation IRF520 Rev. B
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Continuous Source to Drain Current I
SD
Modified MOSFET Symbol
Showing the Integral
Reverse P-N Junction Diode
- - 9.2 A
Pulse Source to Drain Current (Note 3) I
SDM
- - 37 A
Source to Drain Diode Voltage (Note 2) V
SD
T
J
= 25
o
C, I
SD
= 9.2A, V
GS
= 0V (Figure 13) - - 2.5 V
Reverse Recovery Time t
rr
T
J
= 25
o
C, I
SD
= 9.2A, dI
SD
/dt = 100A/
µ
s 5.5 100 240 ns
Reverse Recovered Charge Q
RR
T
J
= 25
o
C, I
SD
= 9.2A, dI
SD
/dt = 100A/
µ
s 0.17 0.5 1.1
µ
C
NOTES:
2. Pulse test: pulse width
≤
300
µ
s, duty cycle
≤
2%.
3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).
4. V
DD
= 25V, starting T
J
= 25
o
C, L = 640mH, R
G
= 25
Ω,
peak I
AS
= 9.2A.
Typical Performance Curves
Unless Otherwise Specified
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE
G
D
S
TC, CASE TEMPERATURE (oC)
25 50 75 100 125 150 175
0
POWER DISSIPATION MULTIPLIER
0
0.2
0.4
0.6
0.8
1.0
1.2
TC, CASE TEMPERATURE (oC)
50 75 100 17525
10
8
6
0
4
ID, DRAIN CURRENT (A)
2
125 150
ZθJC, TRANSIENT
1
0.1
0.01
10-2
10-5 10-4 10-3 0.1 1 10
t1, RECTANGULAR PULSE DURATION (s)
PDM
t1
t2
10
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC + TC
SINGLE PULSE
0.5
0.02
0.05
0.2
0.01
0.1
THERMAL IMPEDANCE (oC/W)
IRF520
©2002 Fairchild Semiconductor Corporation IRF520 Rev. B
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS
FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
Typical Performance Curves Unless Otherwise Specified (Continued)
100
10
1
10001 10 100
0.1
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
TC = 25oC
TJ = MAX RATED
SINGLE PULSE
10µs
100µs
1ms
10ms
OPERATION IN THIS
AREA IS LIMITED
BY rDS(ON)
10V
VDS, DRAIN TO SOURCE VOLTAGE (V)
20050
15
12
9
0
6
ID, DRAIN CURRENT (A)
VGS = 7V
3
30
VGS = 6V
VGS = 8V PULSE DURATION = 80µs
10 40
VGS = 5V
VGS = 4V
DUTY CYCLE = 0.5% MAX
15
12
9
0
6
123405
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
3
VGS = 6V
VGS = 5V
VGS = 4V
VGS = 7V
VGS = 8V
VGS = 10V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
102
0.1 24680
ID(ON), ON-STATE DRAIN CURRENT (A)
VGS , GATE TO SOURCE VOLTAGE (V)
1
10
10
175oC25oC
VDS ≥ 50V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
ID, DRAIN CURRENT (A)
16 32040
2.5
2.0
1.5
0
1.0
rDS(ON), DRAIN TO SOURCE ON RESISTANCE
PULSE DURATION = 80µs
824
0.5
VGS = 10V
VGS = 20V
DUTY CYCLE = 0.5% MAX
3.0
1.8
0.6
060-60
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED ON RESISTANCE
2.4
1.2
0-40 -20 20 40 80 100 140120 160 180
ID = 9.2A, VGS = 10V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
IRF520
©2002 Fairchild Semiconductor Corporation IRF520 Rev. B
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
Typical Performance Curves Unless Otherwise Specified (Continued)
1.25
1.05
0.85
0 180
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
1.15
0.95
0.75
-60
BREAKDOWN VOLTAGE
60 120
ID = 250µA
VDS, DRAIN TO SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
1000
800
600
400
200
0
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
110 102
CISS
COSS
CRSS
ID, DRAIN CURRENT (A)
36912015
5
4
3
0
2
gfs, TRANSCONDUCTANCE (S)
1
TJ = 175oC
TJ = 25oC
PULSE DURATION = 80µs
VDS ≥ 50
DUTY CYCLE = 0.5% MAX
TJ = 175oC
ISD, SOURCE TO DRAIN CURRENT (A)
VSD, SOURCE TO DRAIN VOLTAGE (V)
100
10
0.1
0 0.4 1.2 1.6 2.0
0.8
TJ = 25oC
1
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
Qg, GATE CHARGE (nC)
36912015
20
8
0
VGS, GATE TO SOURCE VOLTAGE (V)
4
ID = 9.2A
16
12
VDS = 20V
VDS = 50V
VDS = 80V
IRF520
©2002 Fairchild Semiconductor Corporation IRF520 Rev. B
Test Circuits and Waveforms
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
VGS
RL
RG
DUT
+
-
VDD
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
0.3µF
12V
BATTERY 50kΩ
VDS
S
DUT
D
G
Ig(REF)
0
(ISOLATED
VDS
0.2µF
CURRENT
REGULATOR
ID CURRENT
SAMPLING
IG CURRENT
SAMPLING
SUPPLY)
RESISTOR RESISTOR
SAME TYPE
AS DUT
Qg(TOT)
Qgd
Qgs
VDS
0
VGS
VDD
IG(REF)
0
IRF520
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
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not intended to be an exhaustive list of all such trademarks.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
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