1. General description
The PCF8574/74A provides general-purpose remote I/O expansion via the two-wire
bidirectional I2C-bus (serial clock (SCL), serial data (SDA)).
The devices consist of eight quasi-bidirectional ports, 100 kHz I2C-bus interface, three
hardware address inputs and interrupt output operating between 2.5 V and 6 V. The
quasi-bidirectional port can be independently assigned as an input to monitor interrupt
status or keypads, or as an output to activate indicator devices such as LEDs. System
master can read from the input port or write to the output port through a single register.
The low current consumption of 2.5 A (typical, st atic) is great for mobile applications and
the latched output ports directly drive LEDs.
The PCF8574 and PCF8574A are identical, except for the different fixed portion of the
slave address. The three hardware address pins allow eight of each device to be on the
same I2C-bus, so there can be up to 16 of th ese I/O expand ers PCF8574/74A toge ther on
the same I2C-bus, supporting up to 128 I/Os (for example, 128 LEDs).
The active LOW open-drain interrupt output (INT) can be connected to the interrupt logic
of the microcontroller and is activated when any input state differs from its corresponding
input port register state. It is used to indicate to the microcontrolle r th at an input state has
changed and the device needs to be interroga ted without th e microcontrolle r continuously
polling the input register via the I2C-bus.
The internal Power-On Reset (POR) initializes the I/Os as inputs with a weak internal
pull-up 100 A current source.
2. Features and benefits
I2C-bus to parallel port expander
100 kHz I2C-bus in te r face (Standard-mode I2C-bus)
Operating supply voltage 2.5 V to 6 V with non-overvoltage tolerant I/O held to VDD
with 100 A current source
8-bit remote I/O pins that default to inputs at power-up
Latched outputs directly drive LEDs
Total package sink capability of 80 mA
Active LOW open- dr ain interr up t ou tp ut
Eight programmable slave addresse s using three address pins
Low standby current (2.5 A typical)
40 C to +85 C operation
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
Rev. 5 — 27 May 2013 Product data sheet
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 2 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA
Packages offered: DIP16, SO16, SSOP20
3. Applications
LED signs and displays
Servers
Key pads
Industrial control
Medical equipment
PLC
Cellular telephones
Mobile devices
Gaming machines
Instrumentation and test measurement
4. Ordering information
4.1 Ordering options
Table 1. Ordering information
Type number Topside mark Package
Name Description Version
PCF8574P PCF8574P DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
PCF8574AP PCF8574AP
PCF8574T/3 PCF8574T SO16 plastic small outline package; 16 leads; body width 7.5 mm SOT162-1
PCF8574AT/3 PCF8574AT
PCF8574TS/3 8574TS SSOP20 plastic shrink small outline package; 20 leads;
body width 4.4 mm SOT266-1
PCF8574ATS/3 8574A
Table 2. Ordering options
Type number Orderable
part number Package Packing method Minimum
order
quantity
Temperature range
PCF8574P PCF8574P,112 DIP16 Standard marking
* IC’s tube - DSC bulk pack 1000 Tamb =40 C to +85 C
PCF8574AP PCF8574AP,112 DIP16 Standard marking
* IC’s tube - DSC bulk pack 1000 Tamb =40 C to +85 C
PCF8574T/3 PCF8574T/3,512 SO16 S tandard marking
* tube dry pack 1920 Tamb =40 C to +85 C
PCF8574T/3,518 SO16 Reel 13” Q1/T1
*standard mark SMD dry pack 1000 Tamb =40 C to +85 C
PCF8574AT/3 PCF8574AT/3,512 SO16 S tandard marking
* tube dry pack 1920 Tamb =40 C to +85 C
PCF8574AT/3,518 SO16 Reel 13” Q1/T 1
*standard mark SMD dry pack 1000 Tamb =40 C to +85 C
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 3 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
5. Block diagram
PCF8574TS/3 PCF8574TS/3,112 SSOP20 S tandard marking
* IC’s tube - DSC bulk pack 1350 Tamb =40 C to +85 C
PCF8574TS/3,118 SSOP20 Reel 13” Q1/T1
*standard mark SMD 2500 Tamb =40 C to +85 C
PCF8574ATS/3 PCF8574ATS/3,118 SSOP20 Reel 13” Q1/T1
*standard mark SMD 2500 Tamb =40 C to +85 C
Table 2. Ordering options …continued
Type number Orderable
part number Package Packing method Minimum
order
quantity
Temperature range
Fig 1. Block diagram
Fig 2. Simplified schematic diagram of P0 to P7
002aad624
INT
I
2
C-BUS
CONTROL
LP FILTER
PCF8574
PCF8574A INTERRUPT
LOGIC
A0
A1
A2
INPUT
FILTER SHIFT
REGISTER
SDA
SCL 8 bits
write pulse
read pulse
POWER-ON
RESET
V
DD
V
SS
I/O
PORT
P0
P1
P2
P3
P4
P5
P6
P7
002aac109
write pulse
read pulse
D
CI S
FF
Q
power-on reset
data from Shift Register
Itrt(pu)
100 μAIOH
IOL
VDD
P0 to P7
VSS
D
CI S
FF
Q
data to Shift Register to interrupt logic
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 4 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 3. Pin configuration for DIP16 Fig 4. Pin configuratio n for SO16 Fi g 5. Pin configuratio n for
SSOP20
PCF8574P
PCF8574AP
A0 VDD
A1 SDA
A2 SCL
P0 INT
P1 P7
P2 P6
P3 P5
VSS P4
002aad625
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
A0 V
DD
A1 SDA
A2 SCL
P0 INT
P1 P7
P2 P6
P3 P5
V
SS
P4
PCF8574T/3
PCF8574AT/3
002aad626
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
PCF8574TS/3
PCF8574ATS/3
P7
SCL P6
n.c. n.c.
SDA P5
P4
A0
A1 P3
n.c. n.c.
A2 P2
P0 P1
002aad627
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
V
DD
INT
V
SS
Table 3. Pin description
Symbol Pin Description
DIP16, SO16 SSOP20
A0 1 6 address input 0
A1 2 7 address input 1
A2 3 9 address input 2
P0 4 10 quasi-bidirectional I/O 0
P1 5 11 quasi-bidirectional I/O 1
P2 6 12 quasi-bidirectional I/O 2
P3 7 14 quasi-bidirectional I/O 3
VSS 8 15 supply ground
P4 9 16 quasi-bidirectional I/O 4
P5 10 17 quasi-bidirectional I/O 5
P6 11 19 quasi-bidirectional I/O 6
P7 12 20 quasi-bidirectional I/O 7
INT 13 1 interrupt output (active LOW)
SCL 14 2 serial clock line
SDA 15 4 serial data line
VDD 16 5 supply voltage
n.c. - 3, 8, 13, 18 not connected
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 5 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
7. Functional description
Refer to Figure 1 “Block diagram.
7.1 Device address
Following a START condition, the bus master mus t sen d th e ad dr e ss of the slave it is
accessing and the oper ation it wants to perform (read or write) . The address for mat of th e
PCF8574/74A is shown in Figure 6. Slave address pins A2, A1 and A0 are held HIGH or
LOW to choose one of eight slave addresses. To conserve power, no internal pull-up
resistors are incorporated on A2, A1 or A0, so they must be externally held HIGH or LOW .
The address pins (A2, A1, A0) can connect to VDD or VSS directly or through resistors.
The last bit of the first byte defines the operation to be performed. When set to logic 1 a
read is selected, while a logic 0 selects a write operation (write operation is shown in
Figure 6).
7.1.1 Address maps
The PCF8574 a nd PCF8574A ar e functionally th e same, but have a dif feren t fixed por tion
(A6 to A3) of the slave address. This allows eight of the PCF8574 and eight of the
PCF8574A to be on the same I2C-bus without address conflict.
a. PCF8574 b. PCF8574A
Fig 6. PCF8574 and PCF8574A slave addresses
R/W
002aad628
0 1 0 0 A2 A1 A0
hardware
selectable
slave address
0
fixed
R/W
002aad629
0 1 1 1 A2 A1 A0
hardware
selectable
slave address
0
fixed
Table 4. PCF8574 address map
Pin connectivity Address of PCF8574 Address byte value 7-bit
hexadecimal
address
without R/W
A2 A1 A0 A6 A5 A4 A3 A2 A1 A0 R/W Write Read
VSS VSS VSS 0100000 - 40h 41h 20h
VSS VSS VDD 0100001 - 42h 43h 21h
VSS VDD VSS 0100010 - 44h 45h 22h
VSS VDD VDD 0100011 - 46h 47h 23h
VDD VSS VSS 0100100 - 48h 49h 24h
VDD VSS VDD 0100101 - 4Ah 4Bh 25h
VDD VDD VSS 0100110 - 4Ch 4Dh 26h
VDD VDD VDD 0100111 - 4Eh 4Fh 27h
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 6 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
8. I/O programming
8.1 Quasi-bidirectional I/Os
A quasi-bidirectional I/O is an input or output port without using a direction control register .
Whenever the master reads the register, the value returned to master depends on the
actual voltage or status of the pin. At power on, all the ports are HIGH with a weak 100 A
internal pull-up to VDD, but can be driven LOW by an internal transistor, or an external
signal. The I/O ports are entirely independent of each other, but each I/O octal is
controlled by the same read or write data byte.
Advantages of the quasi-b idir e ctio na l I/O over totem pole I/O inc lud e:
Better for driving LEDs since the p-channel (transistor to VDD) is small, which saves
die size and therefore cost. LED drive only requires an internal transistor to ground,
while the LED is connected to VDD through a current-limiting resistor. Totem pole I/O
have both n-chan n el an d p- ch an n el tran s istors, which allow solid HIGH and LOW
output levels without a pull-up resistor — good for logic levels.
Simpler architecture — on ly a sin gle register and the I/O can b e both input and output
at the same time. Totem pole I/O have a direction regis te r tha t spe cif ies the po rt pin
direction and it is always in that configuration unless the direction is explicitly
changed.
Does not require a command byte. The simplicity of one register (no need for the
pointer register or, technically, the command byte) is an advantage in some
embedded systems where every byte counts because of memory or bandwidth
limitations.
Table 5. PCF8574A address map
Pin connectivity Address of PCF8574A Address byte value 7-bit
hexadecimal
address
without R/W
A2 A1 A0 A6 A5 A4 A3 A2 A1 A0 R/W Write Read
VSS VSS VSS 0111000 - 70h 71h 38h
VSS VSS VDD 0111001 - 72h 73h 39h
VSS VDD VSS 0111010 - 74h 75h 3Ah
VSS VDD VDD 0111011 - 76h 77h 3Bh
VDD VSS VSS 0111100 - 78h 79h 3Ch
VDD VSS VDD 0111101 - 7Ah 7Bh 3Dh
VDD VDD VSS 0111110 - 7Ch 7Dh 3Eh
VDD VDD VDD 0111111 - 7Eh 7Fh 3Fh
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 7 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
There is only one register to control four possibilities of the port pin: Input HIGH, input
LOW, output HIGH, or output LOW.
Input HIGH: The master nee ds to write 1 to the register to se t the port as an input mode
if the device is not in the default power-on condition. The master reads the register to
check the input status. If the external source pulls the port pin up to VDD or drives
logic 1, then the master will read the value of 1.
Input LOW: The master needs to write 1 to the register to set the port to input mode if
the device is not in the default power-on condition. The master reads the register to
check the input status. If the external source pulls the port pin down to VSS or drives
logic 0, which sinks the weak 100 A current source, then the master will read the value
of 0.
Output HIGH: The master writes 1 to the re gister. There is an additional ‘accelerator’ or
strong pull-up current when the ma ster sets the port HIGH. Th e additional strong pu ll-up
is only active during the HIGH time of the acknowledge clock cycle. This accelerator
current helps the port’s 100 A current source make a faster rising edge into a heavily
loaded output, but only at the start of the acknowledge clock cycle to avoid bus
contention if an external signal is pulling the port LOW to VSS/driving the port with
logic 0 at the same time. After the half clock cycle there is only the 100 A current
source to hold the port HIGH.
Output LOW: The master writes 0 to the register. There is a strong current sink
transistor that holds the port pin LOW. A large current may flow into the port, which
could potentially damage the part if the master writes a 0 to the register and an extern al
source is pulling the port HIGH at the same time.
Fig 7. Simple quasi-bidirectional I/O
002aah683
V
DD
weak 100 µA
current source
(inactive when
output LOW) output HIGH
V
SS
output LOW
accelerator
pull-up
P port
P7 - P0
pull-down with
resistor to V
SS
or
external drive LOW
input LOW
pull-up with
resistor to V
DD
or
external drive HIGH
input HIGH
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 8 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
8.2 Writing to the port (Output mode)
The master (microcontroller) sends the START condition and slave address setting the
last bit of the address byte to logic 0 for the write mode. The PCF8574/7 4A acknowledges
and the master then sends the dat a byte for P7 to P0 to the port register. As the clock line
goes HIGH, the 8-bit data is presented on the port lines af ter it has been acknowledged by
the PCF8574/74A. If a LOW is written, the strong pull-down turns on and stays on. If a
HIGH is written, the strong pull-up turns on for 12of the clock cycle, then the line is held
HIGH by the weak curr en t sou r ce. The ma ste r ca n th en send a S TOP or ReSTART
condition or continue sending data. The number of data bytes that can be sent
successively is not limited and the previous data is overwritten every time a data byte has
been sent and acknowledged.
Ensure a logic 1 is written for any port that is being used as an input to ensure the strong
external pull-d o wn is tur ne d off.
Simple code WRITE mode:
<S> <slave address + write> <ACK> <data out> <ACK> <data out> <ACK> ...
<data out> <ACK> <P>
Remark: Bold type = generated by slave device .
Fig 8. Write mode (output)
A5 A4 A3 A2 A1 A0 0 ASA6
slave address
START condition R/W acknowledge
from slave
002aah349
P6 1P7
data 1
A
acknowledge
from slave
12345678SCL 9
SDA A
acknowledge
from slave
write to port
data output from port
t
v(Q)
P5
data 2
DATA 2 VALID
P4 P3 P2 P1 P0 P7 P4 P3 P2 P1 P0P6
P5
0
t
v(Q)
DATA 1 VALID
P5 output voltage
I
trt(pu)
I
OH
P5 pull-up output current
t
d(rst)
INT
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 9 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
8.3 Reading from a port (Input mode)
The port must have been previously written to logi c 1, which is the condition after
power-on reset. To enter the Rea d mode the master (microcontroller) addre sses the slave
device and sets the last bit of the address byte to logic 1 (address byte read). The slave
will acknowledge and then send the data byte to the master. The master will NACK and
then send the STOP condition or ACK and read the input register again.
The read of any pin being used as an output will indicate HIGH or LOW depending on the
actual state of the pin.
If the data on the input port chang es fast er than the master can read, this data may be
lost. The DATA 2 and DATA3 are lost because these da t a did not meet the setup time a nd
hold time (see Figure 9).
Simple code for Read mode:
<S> <slave address + read> <ACK> <data in> <ACK> ... <data in> <ACK> <data in>
<NACK> <P>
Remark: Bold type = generated by slave device .
8.4 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the
PCF8574/74A in a reset condition until VDD has reached VPOR. At that point, the reset
condition is released and the PCF8574/74A registers and I2C-bus/SMBus state machine
will initialize to their default states of all I/Os to inputs with weak current source to VDD.
Thereafter VDD must be lowered below VPOR and back up to the operation voltage for
power-on reset cycle.
A LOW-to-HIGH transition of SDA while SCL is HIGH is defined as the STOP condition (P). Transfer of data can be stopped at
any moment by a STOP condition. When this occurs, data present at the last acknowledge phase is valid (output mode). Input
data is lost.
Fig 9. Read mode (input)
A5 A4 A3 A2 A1 A0 1 ASA6
slave address
START condition R/W acknowledge
from slave
002aah383
data from port
A
acknowledge
from master
SDA 1
no acknowledge
from master
read from
port
data at
port
data from port
DATA 1
DATA 4
INT
DATA 4
DATA 2
DATA 3
P
STOP
condition
tv(INT) trst(INT)
th(D) tsu(D)
trst(INT)
DATA 1
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 10 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
8.5 Interrupt output (INT)
The PCF8574/74A provides an open-drain output (INT) which can be fed to a
corresponding input of the microcontroller (see Figure 10). As soon as a port input is
changed, the INT will be active (LOW) and notify the microcontroller.
An interrupt is generated at any rising or falling edge of the port inputs. Af ter time tv(Q), the
signal INT is valid.
The interrupt will reset to HIGH when data on the port is changed to the original setting or
data is read or written by the mast er.
In the Write mode, the interrupt may be reset (HIGH) on the rising edge of the
acknowledge bit of the address byte and also on the rising edge of the write to por t pulse.
The interrupt will always be reset (HIGH) on the falling edge of the write to port pulse (see
Figure 8).
The interrupt is reset (HIGH) in the Read mode on the rising edge of the read from port
pulse (see Figure 9).
During the interrupt reset, any I/O change close to the read or write pulse may not
generate an interrupt, or the interrupt will have a very short pulse. After the interrupt is
reset, any change in I/Os will be detected and transmitted as an INT.
At power-on reset all ports are in Input mode and the initial state of the ports is HIGH,
therefore, for any port pin that is pulled LOW or driven LOW by external source, the
interrupt output will be active (output LOW).
Fig 10. Application of multiple PCF8574/74As with interrupt
002aad634
VDD
MICROCONTROLLER
INT
PCF8574
INT
PCF8574
INT
device 1 device 2
PCF8574A
INT
device 16
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 11 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
9. Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-wire communication between different ICs or modules. The
two wires are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
9.1 Bit transfer
One data bi t is transferred durin g each clock pulse . The data o n the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 11).
9.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HI GH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 12).
9.2 System configuration
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 13).
Fig 11. Bit transfer
Fig 12. Definition of START and STOP conditions
mba608
SDA
SCL P
STOP condition
S
START condition
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 12 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
9.3 Acknowledge
The number of data bytes transferred between the START and th e STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit (see Figure 14). The acknowledge bit is an active LOW level (generated
by the receiving device) that indicates to the transmitter that the data transfer was
successful.
A slave receiver which is addresse d must gener ate an acknowledg e af ter the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocke d ou t of th e sla ve tr ansmitter. The device that wants to issue an
acknowledge bit has to pull down the SDA line during the acknowledge clock pulse, so
that the SDA line is stable LOW during the HIGH period of the acknowledge bi t related
clock pulse; set-up and hold times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter mus t leave the data line HIGH to enable the master to generate a STOP
condition.
Fig 13. System configuratio n
002aaa966
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
I2C-BUS
MULTIPLEXER
SLAVE
Fig 14. Acknowledgement on the I2C-bus
002aaa987
S
START
condition
9821
clock pulse for
acknowledgement
not acknowledge
acknowledge
data output
by transmitter
data output
by receiver
SCL from master
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 13 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
10. Application design-in information
10.1 Bidirectional I/O expander applications
In the 8-bit I/O expander application shown in Figure 15, P0 and P1 are inputs, and
P2 to P7 are outputs. When used in this configuration, during a write, the input (P0 and
P1) must be written as HIGH so the external devices fully control the input ports.
The desired HIGH or LOW logic levels may be written to the ports used as outputs (P2 to
P7). If 10 A internal output HIGH is not enough current source, the port needs external
pull-up resistor. During a read, the logic levels of the external devices driving the input
ports (P0 and P1) and the previous written logic level to the output ports (P2 to P7) will be
read.
The GPIO also has an interrupt line (INT) that can be connected to the interrupt logic of
the microcontroller. By sending an interrupt signal on this line, the remote I/O informs the
microprocessor that there has been a change of data on its ports without having to
communicate via the I2C-bus.
10.2 How to read and write to I/O expander (example)
In the application example of PCF8574 shown in Figure 15, the microcontroller wants to
control the P3 switch ON and the P7 LED ON when the temperature sensor P0 changes.
1. When the system power on:
Core Processor needs to issue an initial command to set P0 and P1 as inputs and
P[7:2] as outputs with value 1010 00 (LED off, MP3 off, camera on, audio off,
switch off and latch off).
2. Operation:
When the temperature changes above the threshold, the temperature sensor signal
will toggle from HIGH to LOW. The INT will be activated and notifies the ‘core
processor’ that there have been changes on the input pins. Read the input register.
If P0 = 0 (temperature sensor has changed), then turn on LED an d turn on switch.
3. Software code:
//System Power on
// write to PCF8574 with data 1010 0011b to set P[7:2] outputs and P[1:0] inputs
<S> <0100 0000> <ACK> <1010 0011> <ACK> <P>//Initial setting for PCF9574
Fig 15. Bidirectional I/O expander application
002aah384
VDD
temperature sensor
battery status
control for latch
control for switch
control for audio
control for camera
control for MP3
P0
P1
P2
P3
P4
P5
P6
P7
VDD
SDA
SCL
INT
A0
A1
A2
CORE
PROCESSOR
VDD
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 14 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
while (INT == 1); //Monitor the interrupt pin. If INT = 1 do nothing
//When INT = 0 then read input ports
<S> <slave address read> <ACK> <1010 0010> <NACK> <P> //Read PCF8574 data
If (P0 == 0) //Temperature sensor activated
{// write to PCF8574 with data 0010 1011b to turn on LED (P7), on Switch (P3)
and keep P[1:0] as input ports.
<S> <0100 0000> <ACK> <0010 1011> <ACK> <P> // Write to PCF8574
}
10.3 High current-drive load applications
The GPIO has a minimum guaranteed sinking current of 10 mA per bit at 5 V. In
applications requiring addition al drive, two port pins may be connected together to sin k up
to 20 mA current. Both bits must then always be turned on or off together. Up to five pins
can be connected together to drive 80 mA, which is the device recommended total limit.
Each pin needs its own limiting resistor as shown in Figure 16 to prevent dam ag e to the
device should all po rts not be tur ned on at th e sam e time .
10.4 Migration path
NXP offers newer, more capable drop- in replacements for the PCF8574/74A in newer
space-saving packages.
PCA9670 replaces the interrup t output of the PCA9674 with hardware r eset input to retain
the maximum number of addresses and the PCA9672 replaces address A2 of the
PCA9674 with hardware reset input to retain the interrupt but limit the number of
addresses.
Fig 16. High current-drive load application
002aah385
V
DD
P0
P1
P2
P3
P4
P5
P6
P7
V
DD
SDA
SCL
INT
A0
A1
A2
CORE
PROCESSOR
V
DD
LOAD
Table 6. Migration path
Type number I2C-bus
frequency Voltage range Number of
addresses
per device
Interrupt Reset To tal package
sink current
PCF8574/74A 100 k Hz 2.5 V to 6 V 8 yes no 80 mA
PCA8574/74A 400 kHz 2.3 V to 5.5 V 8 yes no 200 mA
PCA9674/74A 1 MHz Fm+ 2.3 V to 5.5 V 64 yes no 200 mA
PCA9670 1 MHz Fm+ 2.3 V to 5.5 V 64 no yes 200 mA
PCA9672 1 MHz Fm+ 2.3 V to 5.5 V 16 yes yes 200 mA
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 15 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
11. Limiting values
12. Thermal characteristics
Table 7. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage 0.5 +7 V
IDD supply current - 100 mA
ISS ground supply current - 100 mA
VIinput voltage VSS 0.5 VDD +0.5 V
IIinput current - 20 mA
IOoutput cur rent - 25 mA
Ptot total power dissipation - 400 mW
P/out power dissipation per output - 100 mW
Tj(max) maximum junction temperature - 125 C
Tstg storage temperature 65 +150 C
Tamb ambient temperature operating 40 +85 C
Table 8. Thermal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-a) thermal resistance from junction
to ambient SO16 package 115 C/W
SSOP20 package 136 C/W
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 16 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
13. Static characteristics
[1] The power-on reset circuit resets the I2C-bus logic at VDD <V
POR and sets all I/Os to logic 1 (with current source to VDD).
Table 9. Static characteristics
VDD = 2.5 V to 6 V; VSS =0V; T
amb =
40
C to +85
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supply
VDD supply voltage 2.5 - 6.0 V
IDD supply current operating mode; VDD = 6 V ; no load;
VI=V
DD or VSS; fSCL = 100 kHz - 40 100 A
Istb standby current standby mode; VDD = 6 V; no load;
VI=V
DD or VSS
-2.510 A
VPOR power-on reset voltage VDD =6V; noload; V
I=V
DD or VSS [1] -1.32.4V
Input SCL; input/outpu t S DA
VIL LOW-level input voltage 0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD -V
DD +0.5 V
IOL LOW-level output current V OL =0.4V 3 - - mA
ILleakage current VI=V
DD or VSS 1-+1 A
Ciinput capacitance VI=V
SS --7 pF
I/Os; P0 to P7
VIL LOW-level input voltage 0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD -V
DD +0.5 V
IIHL(max) maximum allowed input current
through protection diode VIVDD or VIVSS --400 A
IOL LOW-level output current V OL =1V; V
DD =5V 10 25 - mA
IOH HIGH-level output current VOH =V
SS 30 - 300 A
Itrt(pu) transient bo osted pull-up current HIGH during acknowledge (see
Figure 8); VOH =V
SS; VDD =2.5V -1- mA
Ciinput capacitance - - 10 pF
Cooutput capacitance - - 10 pF
Interrupt INT (see Figure 8)
IOL LOW-level output current V OL =0.4V 1.6 - - mA
ILleakage current VI=V
DD or VSS 1-+1 A
Select input s A0, A1, A2
VIL LOW-level input voltage 0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD -V
DD +0.5 V
ILI input leakage current pin at VDD or VSS 250 - +250 nA
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 17 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
14. Dynamic characteristics
[1] A ll the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH with an input
voltage swing of VSS to VDD.
Table 10. Dynam ic characteristics
VDD = 2.5 V to 6 V; VSS =0V; T
amb =
40
C to +85
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
I2C-bus timing[1] (see Figure 17)
fSCL SCL clock frequency - - 10 0 kHz
tBUF bus free time between a STOP and
STARTcondition 4.7 - - s
tHD;STA hold time (repeated) START condition 4 - - s
tSU;STA set-up time for a repeated START condition 4.7 - - s
tSU;STO set-up time for STOP condition 4 - - s
tHD;DAT data hold time 0 - - n s
tVD;DAT data valid time - - 3.4 s
tSU;DAT data set-up time 250 - - ns
tLOW LOW period of the SCL clock 4.7 - - s
tHIGH HIGH period of the SCL clock 4 - - s
trrise time of both SDA and SCL signals - - 1 s
tffall time of both SDA and SCL signals - - 0.3 s
Port timing (see Figure 8 an d Figure 9)
tv(Q) data output valid time CL100 pF - - 4 s
tsu(D) data input set-up time CL100 pF 0 - - s
th(D) data input hold time CL100 pF 4 - - s
Interrupt INT timing (see Figure 9)
tv(INT) valid time on pin INT from port to INT;
CL100 pF --4s
trst(INT) reset time on pin INT from SCL to INT;
CL100 pF --4s
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 18 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
Rise and fall times refer to VIL and VIH.
Fig 17. I2C-bus timing diagram
002aab175
protocol START
condition
(S)
bit 7
MSB
(A7)
bit 6
(A6) bit 0
(R/W) acknowledge
(A)
STOP
condition
(P)
SCL
SDA
tHD;STA tSU;DAT tHD;DAT
tf
tBUF
tSU;STA tLOW tHIGH
tVD;ACK tSU;STO
1 / fSCL
tr
tVD;DAT
0.3 × VDD
0.7 × VDD
0.3 × VDD
0.7 × VDD
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 19 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
15. Package outline
Fig 18. Package outline SOT38-4 (DIP16)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT38-4 95-01-14
03-02-13
MH
c
(e )
1
ME
A
L
seating plane
A1
wM
b1
b2
e
D
A2
Z
16
1
9
8
E
pin 1 index
b
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
UNIT A
max. 12 b1(1) (1) (1)
b2cD E e M Z
H
L
mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
min. A
max. bmax.
w
ME
e1
1.73
1.30 0.53
0.38 0.36
0.23 19.50
18.55 6.48
6.20 3.60
3.05 0.2542.54 7.62 8.25
7.80 10.0
8.3 0.764.2 0.51 3.2
inches 0.068
0.051 0.021
0.015 0.014
0.009
1.25
0.85
0.049
0.033 0.77
0.73 0.26
0.24 0.14
0.12 0.010.1 0.3 0.32
0.31 0.39
0.33 0.030.17 0.02 0.13
DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4
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Product data sheet Rev. 5 — 27 May 2013 20 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
Fig 19. Package outline SOT162-1 (SO16)
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZ
ywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
2.65 0.3
0.1 2.45
2.25 0.49
0.36 0.32
0.23 10.5
10.1 7.6
7.4 1.27 10.65
10.00 1.1
1.0 0.9
0.4 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.1
0.4
SOT162-1
8
16
wM
bp
D
detail X
Z
e
9
1
y
0.25
075E03 MS-013
pin 1 index
0.1 0.012
0.004 0.096
0.089 0.019
0.014 0.013
0.009 0.41
0.40 0.30
0.29 0.05
1.4
0.055
0.419
0.394 0.043
0.039 0.035
0.016
0.01
0.25
0.01 0.004
0.043
0.016
0.01
X
θ
A
A1
A2
HE
Lp
Q
E
c
L
vMA
(A )
3
A
0 5 10 mm
scale
SO16: plastic small outline package; 16 leads; body width 7.5 mm SOT162-1
99-12-27
03-02-19
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 21 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
Fig 20. Package outline SOT266-1 (SSOP20)
UNIT A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
01.4
1.2 0.32
0.20 0.20
0.13 6.6
6.4 4.5
4.3 0.65 1 0.2
6.6
6.2 0.65
0.45 0.48
0.18 10
0
o
o
0.13 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
0.75
0.45
SOT266-1 MO-152 99-12-27
03-02-19
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
X
(A )
3
A
y
0.25
110
20 11
pin 1 index
0 2.5 5 mm
scale
SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm SOT266-1
A
max.
1.5
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 22 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
16. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate prec a ut io ns ar e taken as
described in JESD625-A or equivalent standards.
17. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
17.2 Wave and reflow soldering
W ave soldering is a joinin g technology in which the joint s are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
Through-hole components
Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered ,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
17.3 Wave soldering
Key characteristics in wave soldering are:
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 23 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave pa rameters, and the time during which components are
exposed to the wave
Solder bath specifications, including temperature and impurities
17.4 Reflow soldering
Key characteristics in reflow soldering are:
Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to
higher minimum peak temperatures (see Figure 21) than a SnPb process, thus
reducing the process window
Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enoug h for the solder to make reliable solder joint s (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in acco rdance with
Table 11 an d 12
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperat ures during reflow
soldering, see Figure 21.
Table 11. SnPb eutectic process (from J-STD-0 20D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350 350
< 2.5 235 220
2.5 220 220
Table 12. Lead-free process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350 350 to 2000 > 2000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 24 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
18. Soldering of through-hole mount p ackages
18.1 Introduction to soldering through-hole mount packages
This text gives a very brief insight into wave, dip an d ma n ua l sold er ing .
Wave soldering is the preferred method for mounting of through-hole mount IC packages
on a printed-circuit board.
18.2 Soldering by dipping or by solder wave
Driven by legislatio n an d en viron m en tal forces the worldwide use of lead-free solder
pastes is increasing. Typical dwell time of the leads in the wave ranges from
3 seconds to 4 seconds at 250 C or 265 C, depending on solder ma terial a pplied, Sn Pb
or Pb-free respectively.
The total contact time of successive solder waves must not exceed 5 seconds.
The device may be mounted up to the seating plane, but the temperature of the plastic
body must not exceed the specified maximum storage temperature (Tstg(max)). If the
printed-circuit board has been pre-heated, forced cooling may be necessary immediately
after soldering to keep the temperature within the permissible limit.
18.3 Manual soldering
Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the
seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is
less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is
between 300 C and 400 C, contact may be up to 5 seconds.
MSL: Moisture Sensitivity Level
Fig 21. Temperature profiles for large and small components
001aac844
temperature
time
minimum peak temperature
= minimum soldering temperature
maximum peak temperature
= MSL limit, damage level
peak
temperature
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 25 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
18.4 Package related soldering information
[1] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit
board.
[2] For PMFP packages hot bar soldering or manual soldering is suitable.
Table 13. Suitability of through-hole mount IC packages for dipping and wave soldering
Package Soldering method
Dipping Wave
CPGA, HCPGA - suitable
DBS, DIP, HDIP, RDBS, SDIP, SIL suitable suitable[1]
PMFP[2] - not suitable
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 26 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
19. Soldering: PCB footprints
Fig 22. PCB footprint for SOT162-1 (SO16); reflow soldering
DIMENSIONS in mm
Ay By D1 D2 Gy HyP1
11.200 6.400 2.400 0.700
C
0.800 10.040 8.600
Gx
11.450
sot162-1_fr
Hx
11.9001.270
SOT162-1
solder land
occupied area
Footprint information for reflow soldering of SO16 package
AyByGy
C
Hy
Hx
Gx
P1
Generic footprint pattern
Refer to the package outline drawing for actual layout
P2
(0.125) (0.125)
D1
D2 (4x)
P2
1.320
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 27 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
Fig 23. PCB footprint for SOT266-1 (SSOP20); reflow soldering
DIMENSIONS in mm
Ay By D1 D2 Gy HyP1
7.200 4.500 1.350 0.400
C
0.600 6.900 5.300
Gx
7.450
sot266-1_fr
Hx
7.3000.650
SOT266-1
solder land
occupied area
Footprint information for reflow soldering of SSOP20 package
P2
0.750
P2
Gy
C
Hy
(0.125)
AyBy
(0.125)
Hx
Gx
P1 D1
D2 (4x)
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 28 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
20. Abbreviations
Table 14. Abbreviations
Acronym Description
CDM Charged-Device Model
CMOS Complementary Metal Oxide Semiconductor
I/O Input/Output
I2C-bus Inter IC bus
ESD ElectroStatic Discharge
FF Flip-Flop
GPIO General Purpose Input/Output
HBM Human Body Model
IC Integrated Circuit
LED Light Emitting Diode
LP Low-Pass
PLC Programmable Logic Controller
POR Power-On Reset
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 29 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
21. Revision history
Table 15. Revision history
Document ID Release date Data sheet statu s Change notice Supersedes
PCF8574_PCF8574A v.5 20130527 Product data sheet - PCF8574 v.4
Modifications: The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate.
Electrical parameter letter-symbols and their definitions are updated to confo r m to NXP
presentation standards.
Section 1 “General description: updated
Section 2 “Features and benefits:
third bullet item: appended “with non-overvoltage tolerant I/O held to VDD with 100 A
current source”
added (new) fourth and seventh bullet items
added sixth bullet item: “Total package sink capability of 80 mA”
ninth bullet changed from “(10 A maximum)” to “(2.5 A typical)”
deleted (old) 11th, 12th and 13th bullet items
Added (new) eighth bullet item “Mobile devices”
Table 1 “Ordering information:
Type number corrected from “PCF8574T” to “PCF8574/3”
Type number corrected from “PCF8574AT” to “PCF8574AT/3”
Type number corrected from “PCF8574TS” to “PCF8574TS/3”
Type number corrected from “PCF8574ATS” to “PCF8574ATS/3”
Added Section 4.1 “Ordering options
Figure 4 “Pin configuration for SO16: updated typ e numbers (appended “/3”)
Figure 5 “Pin configuration for SSOP20: update d type numbers (appended “/3”)
Section 6.2 “Pin description: combined DIP16, SO16 and SSOP20 pin descriptions into
one table (Table 3)
Section 7 “Functional description reorganized
Section 7.1 “Device address, first paragraph, fourth sentence: appended “so they must be
externally held HIGH or LOW”
Table 4 “PCF8574 address map updated: added column for 7-bit hexadecimal address
without R/W
Table 5 “PCF8574A address map updated: add ed column for 7-bit hexadecimal address
without R/W
Section 8.1 “Quasi-bidirectional I/Os: re-written and pl aced before Section 8.4 “Power-on
reset
added Section 8.2 “Writing to the port (Output mode)
added Section 8.3 “Reading from a port (Input mode)
Figure 9 “Read mode (input): changed symbol “tps” to “tsu
Section 8.4 “Power-on reset re-written
Section 8.5 “Interrupt output (INT)” re-written
Figure 10 “Application of multiple PCF8574/74As with inte rrupt updated: changed
device 16 from “PCF8574” to “PCF8574A”
Section 9.3 “Acknowledge, first paragraph, third sentence re-written.
Added Section 10 “Application design-in information
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 30 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
Modifications: (continued) Table 7 “Limiting values:
changed parameter description for symbol II from “DC input current” to “input current”
changed parameter description for symbol IO from “DC output current” to “output
current”
changed parameter description for symbol I SS from “supply current” to “ground supply
current”
changed symbol “PO” to “P/out”
added Tj(max) limits
Added Section 12 “Thermal characteristics
Table 9 “Static characteristics:
table title changed from “DC characteri stics” to “Static characteristics”
sub-section “I/Os; P0 to P7”: changed parameter description for symbol Itrt(pu)
from “transient pull-up current” to “transient boosted pull-up current”
moved sub-section “Port timing” to Table 10 “Dynamic characteristics
sub-section “Interrupt INT”: moved sub-sub-section “Timing” to Table 10 “Dynamic
characteristics
Table 10 “Dynamic characteristics:
sub-section “I2C-bus timing”: deleted symbol/parameter “tSW, tolerable spike width on
bus”
sub-section “Port timing”: changed symbol/parameter from “tpv, output data valid time”
to “tv(Q), data output valid time”
sub-section “Port timing”: changed symbol/parameter from “tsu, input data set-up time”
to “tsu(D), data input set-up time”
sub-section “Port timing”: changed symbol/parameter from “th, input data hold time”
to “th(D), data input hold time
sub-section “Interrupt INT”: changed parameter description for symbol tv(INT)
from “INT output valid time” to “valid time on pin INT
sub-section “Interrupt INT”: changed parameter description for symbol trst(INT)
from “INT reset delay time” to “reset time on pin INT
Added Section 19 “Soldering: PCB footprints
PCF8574 v.4
(9397 750 10462) 20021122 Product specification - PCF8574 v.3
PCF8574 v.3
(9397 750 09911) 20020729 Product specification - PCF8574 v.2
PCF8574 v.2
(9397 750 01758) 19970402 Product specification - PCF8574_PCF8574A v.1
PCF8574_PCF8574A v.1
(9397 750 70011) 199409 Product specification - -
Table 15. Revision history …continued
Document ID Release date Data sheet statu s Change notice Supersedes
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 31 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
22. Legal information
22.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The prod uct sta tus of device (s) descri bed in this d ocument m ay have cha nged since thi s docume nt was publish ed and ma y diffe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
22.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
22.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect , incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconduct ors’ aggregate and cumulati ve liability toward s
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descripti ons, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associate d with t heir
applications and products.
NXP Semiconductors does not accept any liabil ity related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress rating s only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product develop ment.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 32 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors prod uct is automotive qualified,
the product is not suitable for automotive use. It i s neit her qua lified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y
liability, damages or failed produ ct cl aims resulting from custome r design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
22.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
I2C-bus — logo is a trademark of NXP B.V.
23. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
© NXP B.V. 2013. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 27 May 2013
Document identifier: PCF8574_PCF8574A
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
24. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7 Functional de scription . . . . . . . . . . . . . . . . . . . 5
7.1 Device address. . . . . . . . . . . . . . . . . . . . . . . . . 5
7.1.1 Address maps. . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 I/O programming . . . . . . . . . . . . . . . . . . . . . . . . 6
8.1 Quasi-bidirectional I/Os . . . . . . . . . . . . . . . . . . 6
8.2 Writing to the port (Output mode). . . . . . . . . . . 8
8.3 Reading from a port (Input mode) . . . . . . . . . . 9
8.4 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 9
8.5 Interrupt output (INT) . . . . . . . . . . . . . . . . . . . 10
9 Characteristics of the I2C-bus . . . . . . . . . . . . 11
9.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
9.1.1 START and STOP conditions. . . . . . . . . . . . . 11
9.2 System configuration . . . . . . . . . . . . . . . . . . . 11
9.3 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 12
10 Application design-in information . . . . . . . . . 13
10.1 Bidirectional I/O expander applicati ons . . . . . 13
10.2 How to read and write to I/O expander
(example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
10.3 High current-drive load applications . . . . . . . . 14
10.4 Migration path. . . . . . . . . . . . . . . . . . . . . . . . . 14
11 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 15
12 Thermal characteristics . . . . . . . . . . . . . . . . . 15
13 Static characteristics. . . . . . . . . . . . . . . . . . . . 16
14 Dynamic characteristics . . . . . . . . . . . . . . . . . 17
15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19
16 Handling information. . . . . . . . . . . . . . . . . . . . 22
17 Soldering of SMD packages . . . . . . . . . . . . . . 22
17.1 Introduction to soldering . . . . . . . . . . . . . . . . . 22
17.2 Wave and reflow soldering . . . . . . . . . . . . . . . 22
17.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 22
17.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 23
18 Soldering of through-hole mount packages . 24
18.1 Introduction to soldering through-hole mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
18.2 Soldering by dipping or by solder wave . . . . . 24
18.3 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 24
18.4 Package related soldering information. . . . . . 25
19 Soldering: PCB footprints . . . . . . . . . . . . . . . 26
20 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 28
21 Revision history . . . . . . . . . . . . . . . . . . . . . . . 29
22 Legal information . . . . . . . . . . . . . . . . . . . . . . 31
22.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 31
22.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
22.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 31
22.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 32
23 Contact information . . . . . . . . . . . . . . . . . . . . 32
24 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33