12-Bit Power Amplifier Current Controller with
ADC, DACs, and Temperature and Current Sensors
Data Sheet
AD7293
Rev. D Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2016–2018 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
4 closed-loop power amplifier (PA) drain current controllers
Built-in PA protection, sequencing, and alert features
Compatible with both depletion mode and enhancement mode
power amplifiers
Highly integrated
4 uncommitted 12-bit analog-to-digital converter (ADC) inputs
±0.5 LSB typical integral nonlinearity (INL)
Eight 12-bit voltage digital-to-analog converters (DACs)
1.3 µs maximum settling
4 high-side current sense amplifiers, ±0.1% gain error
2 external temperature sensor inputs, ±1.1°C accuracy
Internal temperature sensor, ±1.25°C accuracy
2.5 V on-chip reference
Flexible monitoring and control ranges
ADC input ranges: 0 V to 1.25 V, 0 V to 2.5 V, and 0 V to 5 V
Bipolar DAC ranges: 0 V to +5 V, −4 V to +1 V, and −5 V to 0 V
Bipolar DAC reset and clamping relative to VCLAMPx voltage
Unipolar DAC ranges: 0 V to 5 V, 2.5 V to 7.5 V, and 5 V to 10 V
Current sense gain: 6.25, 12.5, 25, 50, 100, and more
Adjustable closed-loop setpoint ramp time
High-side voltage current sensing
4 current sense inputs
4 V to AVSS + 60 V, ±200 mV input range
Small package and flexible interface
Serial port interface (SPI) with VDRIVE supporting 1.8 V, 3 V, and
5 V interfaces
56-lead LFCSP
Temperature range: −40°C to +125°C
APPLICATIONS
GaN and GaAs power amplifier monitoring and controls
Base station power amplifiers
General-purpose system monitoring and controls
GENERAL DESCRIPTION
The AD7293 is a PA drain current controller containing
functionality for general-purpose monitoring and control of
current, voltage, and temperature, integrated into a single chip
solution with an SPI-compatible interface.
The device features a 4-channel, 12-bit successive approximation
register (SAR) ADC, eight 12-bit DACs (four bipolar and four
unipolar with output ranges that can be configured to shut
down under external pin control), a ±1.25°C accurate internal
temperature sensor, and eight general-purpose input/output
(GPIO) pins.
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
13016-001
4 ANALO G I NP UTS
AD7293
UNIPOLAR
DAC
0V TO 5V
2.5V TO 7.5V
5V TO 10V
0V TO +5V
–4V TO +1V
–5V TO 0V
BIPOLAR
DAC
PAV
DD
PA_ON
PMOS
CONTROL
×1
2
ALERT
AND LI M IT
REGISTERS
CONTROL
LOGIC
MUX
2.5V1.25V
PRECISION
2.5V
REFERENCE
4 CURRENT
SENSE
4 RSx+ PIN
MONITORING 4 SUPPLY
MONITORING4 BIP OLAR DAC
MONITORING
12-BIT
SAR ADC
TEMPERATURE
SENSOR
4 CURRENT
SENSORS
4 BIPOL AR DACs
4 UNIPOL AR DACsDAC CLAMP ING
Σ
–
+
D1+
D1–
D0+
D0–
DGND
AGND
SPI
INTERFACE
SCLK
DOUT
DIN
CS
RESET
LOGIC
RESET
FACTORY TEST
GPIO0/IS BLANK
GPIO1/CONVST
GPIO2/BUSY
GPIO3/ALERT0
GPIO4/ALERT1
GPIO5/SLEEP0
GPIO6/SLEEP1
GPIO7/LDAC
DIGITAL
INPUT/OUTPUT LDAC AND
CLAMP CONT ROL
Figure 1.
The device also includes limit registers for alert functions and four
high-side current sense amplifiers to measure current across
external shunt resistors. These amplifiers can be optionally set to
operate as part of four independent closed-loop drain current
controllers.
A high accuracy 2.5 V internal reference is provided to drive the
DACs and the ADC. The 12-bit ADC monitors and digitizes the
internal temperature sensor, and two inputs are included for the
external diode temperature sensors.
Note that throughout this data sheet, multifunction pins, such
as GPIO4/ALERT1, are referred to either by the entire pin name
or by a single function of the pin, for example, ALERT1, when
only that function is relevant.
PRODUCT HIGHLIGHTS
1. Four independent closed-loop drain current controllers.
2. Built-in monitoring, sequencing, and alert features.
3. Compatible with both depletion mode and enhancement
mode power amplifiers.
AD7293 Data Sheet
Rev. D | Page 2 of 79
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Simplified Functional Block Diagram ........................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 3
Functional Block Diagrams ............................................................. 4
Specifications ..................................................................................... 6
ADC ............................................................................................... 6
DAC ................................................................................................ 7
Temperature Sensor ..................................................................... 8
Current Sensor .............................................................................. 9
Closed-Loop Specifications......................................................... 9
General ......................................................................................... 10
Timing Characteristics .............................................................. 11
Absolute Maximum Ratings .......................................................... 13
Thermal Resistance .................................................................... 13
ESD Caution ................................................................................ 13
Pin Configuration and Function Descriptions ........................... 14
Typical Performance Characteristics ........................................... 17
Theory of Operation ...................................................................... 22
Analog-to-Digital Converter (ADC) Overview ..................... 22
ADC Transfer Functions ........................................................... 22
Analog Inputs .............................................................................. 23
Current Sensor ............................................................................ 23
Temperature Sensor ................................................................... 24
Internal Channel Monitoring ................................................... 25
DAC Operation ........................................................................... 25
Reference ..................................................................................... 27
VDRIVE Feature .............................................................................. 27
Open-Loop Mode ....................................................................... 27
Closed-Loop Mode .................................................................... 27
Digital Input/Output Registers ................................................. 29
Load DAC (LDAC Pin).............................................................. 29
Alerts and Limits ........................................................................ 29
AVDD and AVSS Alarm ................................................................ 31
Maximum and Minimum Pages ............................................... 31
Hysteresis ..................................................................................... 31
Register Settings.............................................................................. 32
Registers Common to All Pages ............................................... 33
Result 0/DAC Input (Page 0x00) .............................................. 34
Result 1 (Page 0x01) ................................................................... 36
Configuration (Page 0x02) ........................................................ 37
Sequence (Page 0x03) ................................................................ 46
High Limit 0 (Page 0x04) .......................................................... 48
High Limit 1 (Page 0x05) .......................................................... 49
Low Limit 0 (Page 0x06) ............................................................ 50
Low Limit 1 (Page 0x07) ............................................................ 51
Hysteresis 0 (Page 0x08) ............................................................ 52
Hysteresis 1 (Page 0x09) ............................................................ 53
Minimum 0 (Page 0x0A) ........................................................... 54
Minimum 1 (Page 0x0B) ........................................................... 55
Maximum 0 (Page 0x0C) .......................................................... 56
Maximum 1 (Page 0x0D) .......................................................... 57
Offset 0 (Page 0x0E) ................................................................... 58
Offset 1 (Page 0x0F) ................................................................... 60
Alert (Page 0x10) ........................................................................ 61
ALERT0 Pin Routing (Page 0x11) ........................................... 63
ALERT1 Pin Routing (Page 0x12) ........................................... 67
Serial Port Interface ........................................................................ 71
Interface Protocol ....................................................................... 71
Modes of Opertion ..................................................................... 72
Applications Information .............................................................. 76
Base Station Power Amplifier Control .................................... 76
Depletion Mode Amplifier Biasing and Protection ............... 77
Loop Component Selection ...................................................... 78
Outline Dimensions ....................................................................... 79
Ordering Guide .......................................................................... 79
Data Sheet AD7293
Rev. D | Page 3 of 79
REVISION HISTORY
8/2018—Rev. C to Rev. D
Changes to Table 2 ............................................................................ 7
Changes to Table 11 ........................................................................ 14
Changes to Internal Channel Monitoring Section ...................... 25
Changes to Table 81 ........................................................................ 58
Changes to Table 86 ........................................................................ 60
5/2018—Rev. B to Rev. C
Changed 0xFFFF to 0xFFF0 ........................................ Throughout
Changes to Table 81 ........................................................................ 58
1/2018—Rev. A to Rev. B
Changes to Figure 7 ........................................................................ 13
Changes to Table 11 ........................................................................ 14
Updated Outline Dimensions ....................................................... 78
Changes to Ordering Guide .......................................................... 78
6/2016—Revision A: Initial Version
AD7293 Data Sheet
Rev. D | Page 4 of 79
FUNCTIONAL BLOCK DIAGRAMS
BI-V
OUT
3
MON
BI-V
OUT
2
MON
BI-V
OUT
1
MON
BI-V
OUT
0
MON
V
IN
0
V
IN
1
V
IN
2
V
IN
3
DACV
DD-BI
DACV
DD-UNI
AV
SS
AV
DD
V
DRIVE
DV
DD
D1+
D1–
D0+
D0–
V
REFIN
V
REFOUT
AD7293
UNI-V
OUT
3
UNIPOLAR
DAC
UNI-V
OUT
2
UNIPOLAR
DAC
UNI-V
OUT
1
UNIPOLAR
DAC
UNI-V
OUT
0
UNIPOLAR
DAC
BI-V
OUT
0
BIPOLAR
DAC
0V T O 5V
2.5V TO 7.5V
5V T O 10V
CLOSED-LOOP 3
CLOSED-LOOP 2
CLOSED-LOOP 1
CLOSED-LOOP 0
V
CLAMP
0
V
CLAMP
1
DGND
AGND
SPI
INTERFACE
SCLK
DOUT
DIN
CS
RESET
LOGIC
RESET
FACTORY TEST
GPIO0/IS BLANK
GPIO1/CONVST
GPIO2/BUSY
GPIO3/ALERT0
GPIO4/ALERT1
GPIO5/SLEEP0
GPIO6/SLEEP1
GPIO7/LDAC
DIGITAL
INPUT/OUTPUT LDAC AND
CLAM P CONTROL
BI-V
OUT
1
BIPOLAR
DAC RS0+
RS0–
BI-V
OUT
2
BIPOLAR
DAC RS1+
RS1–
BI-V
OUT
3
BIPOLAR
DAC RS2+
RS2–
RS3+
RS3–
PAV
DD
PA_ON
PMOS
CONTROL
PRECISION
2.5V
REFERENCE
×1
2
REF
ADC
CONTROL
LOGIC
12-BIT
SAR ADC
TEMPERATURE
SENSOR
ALE RT AND
LIMIT
REGISTERS
MUX
2.5V1.25V
1
1
13016-002
Σ
–
+
Σ
–
+
Σ
–
+
Σ
–
+
Figure 2. Closed-Loop Functional Block Diagram
Data Sheet AD7293
Rev. D | Page 5 of 79
BI-V
OUT
3
MON
BI-V
OUT
2
MON
BI-V
OUT
1
MON
BI-V
OUT
0
MON
V
IN
0
V
IN
1
V
IN
2
V
IN
3
DACV
DD-BI
DACV
DD-UNI
AV
SS
AV
DD
V
DRIVE
DV
DD
D1+
D1–
D0+
D0–
V
REFIN
V
REFOUT
AD7293
UNI-V
OUT
3
UNIPOLAR
DAC
UNI-V
OUT
2
UNIPOLAR
DAC
UNI-V
OUT
1
UNIPOLAR
DAC
UNI-V
OUT
0
UNIPOLAR
DAC
BI-V
OUT
3
BIPOLAR
DAC
0V T O 5V
2.5V TO 7.5V
5V T O 10V
0V T O + 5V
–4V T O + 1V
–5V T O 0V
V
CLAMP
0
V
CLAMP
1
DGND
AGND
SPI
INTERFACE
SCLK
DOUT
DIN
CS
RESET
LOGIC
RESET
FACTORY TEST
GPIO0/IS BLANK
GPIO1/CONVST
GPIO2/BUSY
GPIO3/ALERT0
GPIO4/ALERT1
GPIO5/SLEEP0
GPIO6/SLEEP1
GPIO7/LDAC
DIGITAL
INPUT/OUTPUT LDAC AND
CLAM P CONTROL
BI-V
OUT
2
BIPOLAR
DAC RS3+
RS3–
CURRENT
SENSOR
BI-V
OUT
1
BIPOLAR
DAC RS2+
RS2–
CURRENT
SENSOR
BI-V
OUT
0
BIPOLAR
DAC RS1+
RS1–
CURRENT
SENSOR
RS0+
RS0–
CURRENT
SENSOR
PAV
DD
PA_ON
PMOS
CONTROL
PRECISION
2.5V
REFERENCE
×1
2
REF
ADC
CONTROL
LOGIC
12-BIT
SAR ADC
TEMPERATURE
SENSOR
ALE RT AND
LIMIT
REGISTERS
MUX
2.5V1.25V
1
1
13016-003
Figure 3. Open-Loop Functional Block Diagram
AD7293 Data Sheet
Rev. D | Page 6 of 79
SPECIFICATIONS
ADC
AVDD, DVDD, DACVDD-BI = 4.5 V to 5.5 V (connect AVDD and DACVDD-BI to the same potential), DACVDD-UNI = 5 V, AV SS = − 5 V, PAV DD =
5 V, AGND = DGND = 0 V, VREFIN = 2.5 V internal or external; VDRIVE = 1.7 V to 5.5 V; TA = −40°C to +125°C, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
DC ACCURACY
Resolution 12 Bits
Integral Nonlinearity (INL)
±0.5
±1
LSB
Differential Nonlinearity (DNL) ±0.5 ±0.99 LSB No missing codes
Single-Ended Mode
Zero Code Error ±0.4 ±2.5 LSB
Zero Code Error Mismatch ±0.6 LSB
Full-Scale Error ±6.5 LSB
Full-Scale Error Mismatch ±1.5 LSB
Differential Mode
Gain Error ±3 ±6.5 LSB
Gain Error Mismatch ±1.5 LSB
Zero Code Error ±0.5 ±2 LSB
Zero Code Error Mismatch ±0.6 LSB
DYNAMIC PERFORMANCE fIN = 1 kHz sine wave; single-ended mode;
0 V to 4 × REFADC
Signal-to-Noise Ratio (SNR)1, 2
72
dB
Signal-to-Noise + Distortion (SINAD) Ratio1, 2 72 dB
Total Harmonic Distortion (THD)1, 2 −90.5 dB
Channel to Channel Isolation2 95 dB fIN = 100 Hz to 80 kHz
Full Power Bandwidth2 7 MHz At 0.1 dB; single-ended mode; 0 V to 4 × REFADC
CONVERSION RATE
Conversion Time2 500 ns
Track-and-Hold Acquisition Time2 100 ns Voltage inputs in command mode
ANALOG INPUT1 REFADC = 1.25 V
Single-Ended Input Range 0 1.25 V 0 V to REFADC mode
0 2.5 V 0 V to 2 × REFADC mode
5
V
0 V to 4 × REF
ADC
mode
Pseudo Differential Range (VIN+ − VIN−3) 0 1.25 V 0 V to REFADC mode
0 2.5 V 0 V to 2 × REFADC mode
0 5 V 0 V to 4 × REFADC mode
Differential Range (VIN+ − VIN−)4 −1.25 +1.25 V 0 V to REFADC mode
−2.5 +2.5 V 0 V to 2 × REFADC mode
+5
V
0 V to 4 × REF
ADC
mode
Input Capacitance2 30 pF
DC Input Leakage Current ±1 µA
INTERNAL BI-VOUTx MONITORING INPUTS
Full-Scale Input Range −5 +5 V
Resolution 12 Bits LSB step size ≈ 2.5 mV
Gain Error ±0.53 %
Offset Error ±14 mV
INTERNAL RSx+ MONITORING INPUTS
Full-Scale Input Range 0 62.5 V
Resolution 12 Bits LSB step size ≈ 15.2 mV
Gain Error
0.06
%
Offset Error ±11 mV
Data Sheet AD7293
Rev. D | Page 7 of 79
Parameter Min Typ Max Unit Test Conditions/Comments
INTERNAL SUPPLY MONITORING INPUTS
AVDD
Gain Error ±0.33 %
Offset Error ±52 mV
AV
SS
Gain Error ±0.53 %
Offset Error ±14 mV
DACVDD-UNI
Gain Error ±0.16 %
Offset Error ±12 mV
DACV
DD-BI
Gain Error ±0.33 %
Offset Error ±52 mV
INTERNAL REFERENCE
2
Reference Output Voltage 2.495 2.5 2.505 V At TA = 25°C only
Reference Temperature Coefficient ±10 ±30 ppm/°C
EXTERNAL REFERENCE
Reference Input Voltage Range 2.48 2.5 2.52 V
DC Input Leakage Current ±2 µA
1 See the Analog-to-Digital Converter (ADC) Overview section for more details.
2 Guaranteed by design and characterization; not production tested.
3 VIN− = 0 V for specified performance.
4 VIN+ and VIN− must remain within GND and AVDD.
DAC
AVDD, DVDD, DACVDD-BI = 4.5 V to 5.5 V (connect AVDD and DACVDD-BI to the same potential), DACVDD-UNI = 5 V, AV SS = − 5 V, PAV DD =
5 V, AGND = DGND = 0 V, VREFIN = 2.5 V internal or external; VDRIVE = 1.7 V to 5.5 V; TA = −40°C to +125°C, unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
ACCURACY1
Resolution 12 Bits
Integral Nonlinearity (INL) ±1 ±1.7 LSB Bipolar
±3 Unipolar
±1 LSB Load current ±10 mA within 300 mV of supply
Differential Nonlinearity (DNL) −0.99 ±0.3 +1 LSB Guaranteed monotonic
Full-Scale (FS) Error ±2.5 mV All 1s loaded to DAC register, no load applied
±0.65 % of FS 10 mA load applied
Offset Error ±10 mV Unipolar, 2.5 V to 7.5 V range, 5 V to 10 V range
±10 mV Unipolar, 0 V to 5 V range
±10 mV Bipolar, 0 V to 5 V range
±11
mV
Bipolar, −4 V to +1 V, −5 V to 0 V range
Offset Error Temperature Coefficient ±8 µV/°C Measured in the linear region, TA = 25°C
Gain Error ±0.15 % FSR Bipolar
±0.4 % FSR Unipolar
Gain Error Temperature Coefficient ±3 ppm/°C
DAC OUTPUT CHARACTERISTICS
Bipolar Open-Loop DAC Range 0 5 V BI-VOUT0, BI-VOUT1, BI-VOUT2, and BI-VOUT3
−4 +1 V
−5 0 V
Unipolar DAC Range 0 5 V UNI-VOUT0, UNI-VOUT1, UNI-VOUT2, and UNI-VOUT3
2.5 7.5 V
5 10 V
AD7293 Data Sheet
Rev. D | Page 8 of 79
Parameter Min Typ Max Unit Test Conditions/Comments
Unipolar DAC Short-Circuit Current 40 mA Shorted to AGND or DACVDD-UNI
Bipolar DAC Short-Circuit Current 42 mA Shorted to AVSS or DACVDD-BI
Load Current2 −10 +10 mA Source and/or sink within 300 mV of supply
Capacitive Load Stability 10 nF RL = ∞
DC Output Impedance
1
Ω
Midscale
AC CHARACTERISTICS
Output Voltage Settling Time2 1.2 1.3 µs ¼ to ¾ change within ±1 LSB, measured from
the last SCLK rising edge, CL = 200 pF
Slew Rate2 7.5 V/µs
Digital Feedthrough2 0.1 nV-sec
DAC to DAC Crosstalk2, 3 0.2 nV-sec
Output Noise Spectral Density2, 3 55 nV/√Hz fIN = 10 kHz, bipolar
110 nV/√Hz fIN = 10 kHz, unipolar
Output Noise2, 3 102 µV p-p Bipolar
135 µV p-p Unipolar
CLAMP INPUTS Controlled by SLEEP0 and SLEEP1 digital pins
Clamp Output Voltage2 −3 ×
VCLAMP0,
VCLAMP1
V BI-VOUTx = −3 × VCLAMP0, VCLAMP1
Gain Error 0.2 % Within 200 mV of AVSS
Input Referred Offset Error 5 mV
V
CLAMP
0 and V
CLAMP
1 Input Current
±1
µA
Clamp Voltage Range AVSS 0 V
Output Current2 −10 +10 mA Source and/or sink within 300 mV of supply
Clamp to Open-Loop Settling Time2 5 µs RL = ∞, CL = 200 pF, output voltage within 10%,
5 V transition
1 Specification tested with output unloaded. Linearity calculated using best fit line method and based on a reduced code range equivalent to 100 mV within either side
of supply or ground ± 82 codes.
2 Guaranteed by design and characterization; not production tested.
3 All unipolar DACs must be enabled with an output code set to a minimum code of 41 LSBs.
TEMPERATURE SENSOR
AVDD, DVDD, DACVDD-BI = 4.5 V to 5.5 V (connect AVDD and DACVDD-BI to the same potential), DACVDD-UNI = 5 V, AV SS = − 5 V, PAV DD =
5 V, AGND = DGND = 0 V, VREFIN = 2.5 V internal or external; VDRIVE = 1.7 V to 5.5 V; TA = −40°C to +125°C, unless otherwise noted.
Table 3.
Parameter Min Typ Max Unit Test Conditions/Comments
INTERNAL TEMPERATURE SENSOR1
Operating Range2 −40 +125 °C See Figure 30 for −55°C to +125°C operation
Accuracy ±1.25 ±3 °C Internal temperature sensor, TA = −40°C to +125°C
±1.25 °C TA = 25°C
Resolution
0.125
°C
EXTERNAL TEMPERATURE SENSOR1 External transistor = 2N3906; no capacitor between Dx−/Dx+ pins, and
no series resistor between transistor and Dx−/Dx+ pins
Operating Range
−55
+150
°C
Limited by external transistor
Accuracy ±1.1 ±3 °C TA = −40°C to +105°C
Resolution 0.125 °C LSB size
1 Guaranteed by design and characterization; not production tested.
2 Guaranteed functional to −55°C by design but accuracy is not guaranteed.
Data Sheet AD7293
Rev. D | Page 9 of 79
CURRENT SENSOR
AVDD, DVDD, DACVDD-BI = 4.5 V to 5.5 V (connect AVDD and DACVDD-BI to the same potential), DACVDD-UNI = 5 V, AV SS = −5 V, PAV DD = 5 V,
AGND = DGND = 0 V, VREFIN = 2.5 V internal or external; VDRIVE = 1.7 V to 5.5 V; TA = −40°C to +125°C, gain = 6.25, unless otherwise noted.
Table 4.
Parameter Min Typ Max Unit Test Conditions/Comments
CURRENT SENSE RSx+ = AVDD to AVSS + 60 V
Common-Mode Input Voltage Range 4 60 V AVSS = 0 V
4 55 V AVSS = −5 V
Differential Input Voltage Range −200 +200 mV Gain = 6.25, for gain settings, see Table 44
Gain Error
±0.1
±0.7
%
Gain Error Temperature Coefficient −16 ppm/°C
Offset Error (Referred to Input, RTI) ±200 µV
Offset Error Drift 1 µV/°C
DC Common-Mode Rejection 100 140 dB
RSx+1 Pin Input Current 105 µA
RSx−
1
Pin Input Current
10
nA
Differential Input Resistance2 700 kΩ
1 Where x is 0, 1, 2, or 3.
2 Guaranteed by design and characterization; not production tested.
CLOSED-LOOP SPECIFICATIONS
AVDD, DVDD, DACVDD-BI = 4.5 V to 5.5 V (connect AVDD and DACVDD-BI to the same potential), DACVDD-UNI = 5 V, AV SS = − 5 V, PAV DD =
5 V, AGND = DGND = 0 V, VREFIN = 2.5 V internal or external; VDRIVE = 1.7 V to 5.5 V; TA = −40°C to +125°C, unless otherwise noted.
Power amplifier transconductance = 1 S to 5 S, and external gate filter time constant (τG) = 5 µs to 50 µs.
Table 5.
Parameter Min Typ Max Unit Test Conditions/Comments
NORMAL OPERATION1, 2
Setpoint Resolution 12 Bits Equivalent to 200 mV/4096 = 49 µV at the current
sense input
Sense Resistor Voltage Range 0 200 mV
Setpoint Gain Error ±0.5 %
Setpoint Offset Error (RTI) ±100 µV Referred to current sense input; see Figure 31
Integrator Time Constant3 840 µs Programmable; see Table 50
Closed-Loop Update Rate3 59.6 kHz
Capacitive Load Stability 1 µF 5 Ω series resistance
Closed-Loop to Clamp Settling Time 1 µs Within ±10%
Bipolar Closed-Loop Output Range AVSS AVDD V See the Bipolar DAC (BI-VOUTx) Offset Registers
(Register 0x34 to Register 0x37) section
Integrator Programmable Voltage Limit Resolution 2.5 mV See the Closed-Loop Integrator Programmable
Voltage Limit section
START SEQUENCING PA_ON CONTROL2
PA_ON Pin Output Voltage AGND PAVDD V
PA_ON Off State Enable 500 µs Measured from AVSS failure event, CL = 1 nF
500 µs Measured from SLEEP0 or SLEEP1 pin, 0 to 1
transition, CL = 1 nF
PA_ON On State Enable 500 µs Measured from SLEEP1 to SLEEP0 transition, CL = 1 nF
PA_ON Short-Circuit Current ±10 mA
PA_ON Resistance 250 Ω
AVDD/AVSS ALARM
AVDD Alarm Threshold 3.2 3.6 3.9 V
AVSS Alarm Threshold −3.8 −4.1 −4.4 V
1 Power amplifier characteristic dependent.
2 Guaranteed by design and characterization; not production tested.
3 Expressed as a function of the internal oscillator frequency.
AD7293 Data Sheet
Rev. D | Page 10 of 79
GENERAL
DVDD, AVDD, DACVDD-BI = 4.5 V to 5.5 V (connect AVDD and DACVDD-BI to the same potential), DACVDD-BI = 5 V, AV SS = −5 V, RSx+ = AVDD to
55 V, AGND = DGND = 0 V, VREFIN = 2.5 V internal or external, VDRIVE = 1.7 V to 5.5 V, T A = −40°C to +125°C, unless otherwise noted.
Table 6.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
LOGIC INPUTS
Input Voltage
High VIH 0.8 × VDRIVE V
Low VIL 0.2 × VDRIVE V
Input Leakage Current
I
IN
±1
µA
Input Capacitance CIN 3 pF
LOGIC OUTPUTS1 GPIO0/IS BLANK, GPIO1/CONVST,
GPIO2/BUSY, GPIO3/ALERT0, and
GPIO4/ALERT1 are open-drain outputs
Output Voltage
High VOH 0.4 V ISINK = 3 mA
Low VOL 0.6 V ISINK = 6 mA
Floating-State Leakage Current ±1 µA
Floating-State Output Capacitance
8
pF
GENERAL-PURPOSE OUPUTS
Output Voltage
High VOH VDRIVE − 0.2 V ISINK/ISOURCE = 1 mA
Low VOL 0.4 V ISINK/ISOURCE = 1 mA
POWER REQUIREMENTS
Supply Voltages
Positive Analog AVDD 4.5 5.5 V
Negative Analog AVSS −5.5 −4.5 or 0 V
Logic Power VDRIVE 1.7 5.5 V Supports 1.8 V, 3 V, and 5 V interfaces
Unipolar DAC DACVDD-UNI 4.5 12.5 V
Bipolar DAC
DACV
DD-BI
4.5
5.5
V
PA_ON Power PAVDD 4.5 AVSS + 60 V
RSx+ Voltage VRSx+ 4 AVSS + 60 V
Supply Currents All power supplies set to maximum
voltage; ADC on and converting;
DACs enabled with no load applied
AVDD AIDD 9 12.5 mA
AVSS AISS −4.4 −5.4 mA
VDRIVE IDRIVE 1 2.1 mA
DACVDD-UNI DACIDD-UNI 2.1 3 mA
DACVDD-BI DACIDD-BI 5 8.2 mA
PAV
DD
PAI
DD
81
100
µA
Power Dissipation 110 mW
1 Guaranteed by design and characterization; not production tested.
Data Sheet AD7293
Rev. D | Page 11 of 79
TIMING CHARACTERISTICS
SPI Serial Interface
AVDD, DVDD, DACVDD-BI = 4.5 V to 5.5 V (connec t AVDD and DACVDD-BI to the same potential), DACVDD-UNI = 2.7 V to 16 V, AVSS = 0 V,
RSx+ = AVDD to 55 V, AGND = DGND = 0 V, VREFIN = 2.5 V internal or external, VDRIVE = 1.7 V to 5.5 V, TA = −40°C to +125°C, unless
otherwise noted.
Table 7.
Limit at TMIN/TMAX
Parameter Description VDRIVE = 1.7 V to 2.7 V VDRIVE = 2.7 V to 5.5 V Unit
fSCLK Frequency of serial read clock1 8 15 MHz max
t1 SCLK period 150 66.67 ns min
t2 SCLK low 40 26 ns min
t3 SCLK high 40 26 ns min
t4 CS falling edge to SCLK rising edge 5 5 ns min
t5 DIN setup time to SCLK rising edge 10 10 ns min
t62 DIN hold time after SCLK rising edge 10 10 ns max
t7 Last SCLK rising edge to CS rising edge 5 5 ns min
t
8
CS high
12
10
ns min
t93 CS rising edge to next SCLK rising edge 1 1 ns min
t10 SCLK falling edge to CS falling edge 1 1 ns min
t11 SCLK falling edge to output data valid delay time from
high impedance4
60 30 ns max
t12 SCLK falling edge to output data valid delay time4 60 30 ns max
t13 Last SCLK falling edge to DOUT high impedance4 20 20 ns typ
t14 CS rising edge to DOUT high impedance4 25 15 ns max
1 DOUT loaded with 10 pF for DOUT timing specifications.
2 Time required for the output to cross 0.2 × VDRIVE and 0.8 × VDRIVE when VDRIVE < 2.7 V; time required for the output to cross 0.3 × VDRIVE and 0.7 × VDRIVE when 2.7 ≤ VDRIVE ≤5.5 V.
3 Guaranteed by design and characterization; not production tested.
4 MISO speed set to maximum in the general register.
Asynchronous Inputs
AVDD, DVDD, DACVDD-BI = 4.5 V to 5.5 V (connect AVDD and DACVDD-BI to the same potential), DACVDD-UNI = 2.7 V to 16 V, AVSS = 0 V,
RSx+ = AVDD to 55 V, AGND = DGND = 0 V, VREFIN = 2.5 V internal or external, VDRIVE = 1.7 V to 5.5 V, TA = −40°C to +125°C, unless
otherwise noted.
Table 8.
Limit at TMIN/TMAX
Parameter Description VDRIVE = 1.7 V to 2.7 V VDRIVE = 2.7 V to 5.5 V Unit
t151 Minimum LDAC pulse width 90 90 ns min
t16 Minimum CONVST pulse width 90 90 ns min
t17 Minimum IS BLANK pulse width 90 90 ns min
t18 Minimum RESET pulse width 90 90 ns min
1 Guaranteed by design and characterization; not production tested.
AD7293 Data Sheet
Rev. D | Page 12 of 79
Timing Diagrams
CS
SCLK
P7(W/R) P0 MSB LSB
DIN
MSB LSBDOUT
t
11
t
12
t
14
t
2
t
9
t
10
t
3
t
6
t
4
t
1
t
8
t
13
t
5
t7
13016-004
Figure 4. Serial Interface Timing Diagram
LDAC
CONVST
IS BLANK
RESET
t
15
t
16
t
17
t
18
13016-005
Figure 5. Asynchronous Inputs
C
L
50pF
TO OUTPUT PIN V
DRIVE
2
200µA
200µA
I
OL
I
OH
13016-006
Figure 6. Load Circuit for Digital Output (DOUT) Timing Specifications
Data Sheet AD7293
Rev. D | Page 13 of 79
ABSOLUTE MAXIMUM RATINGS
Table 9.
Parameter Rating
±5 V Analog Output Pins (BI-VOUT0, BI-VOUT1,
BI-VOUT2, BI-VOUT3) to AVSS
AVSS − 0.3 V to
DACVDD-BI + 0.3 V
12.5 V Analog Output Pins (UNI-VOUT0,
UNI-VOUT1, UNI-VOUT2, UNI-VOUT3) to AGND
−0.3 V to
DACVDD-UNI + 0.3 V
12.5 V Supply (DACVDD-UNI) to AGND −0.3 V to +15 V
2 V Analog Pins (REFADC, D1−, D1+, D0−, D0+)
to AGND
−0.3 V to +2 V
5 V Analog Pins (FACTORY TEST, VREFIN,
VREFOUT, VCLAMP0, VCLAMP1, VINx1) to AGND
−0.3 V to
AVDD + 0.3 V
5 V Digital Pins (GPIO5/SLEEP0,
GPIO6/SLEEP1, RESET, GPIO7/LDAC, CS,
DOUT) to DGND
−0.3 V to
VDRIVE + 0.3 V
5 V Open-Drain Pins (GPIO4/ALERT1, SCLK,
DIN, DVDD, GPIO3/ALERT0, GPIO2/BUSY,
GPIO1/CONVST, GPIO0/IS BLANK) to DGND
−0.3 V to +7 V
5 V Supply Pins2 (VDRIVE, DACVDD-BI, AVDD) to
AGND
−0.3 V to +7 V
−5 V Supply Pin (AVSS) to AGND −7 V to +0.3 V
60 V Analog Pins (RSx−) to RSx+ (RSx+) − 0.3 V to
(RSx+) + 0.3 V
60 V Digital Pin (PA_ON) to AGND −0.3 V to
PAVDD + 0.3 V
60 V Supply Pins (RSx+, PAVDD) to AGND −0.3 V to
AVSS + 65 V
Ground Pins (DGND, AGND) to AGND
−0.3 V to +0.3 V
Operating Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +125°C
Reflow Profile J-STD 20 (JEDEC)
Maximum Junction Temperature 150°C
ESD Rating, All Pins
Human Body Model (HBM) 2 kV
Field-Induced Charged Device Model
(FICDM)
1 kV
1 x = 0, 1, 2, or 3.
2 Connect AVDD and DACVDD-BI to the same potential.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for a 4-layer JEDEC 2S2P type printed circuit
board (PCB) with a thermal via, that is, a device soldered in a
circuit board for surface-mount packages, per JESD51-7.
Table 10. Thermal Resistance
Package Type θJA θJC Unit
56-Lead LFCSP 27 0.5 °C/W
ESD CAUTION
AD7293 Data Sheet
Rev. D | Page 14 of 79
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
15
16
17
18
19
20
21
22
23
24
25
26
27
28
UNI-V
OUT
0
UNI-V
OUT
1
AGND
UNI-V
OUT
2
UNI-V
OUT
3
V
REFIN
V
REFOUT
AGND
BI-V
OUT
0
BI-V
OUT
1
AV
SS
DACV
DD-BI
BI-V
OUT
2
BI-V
OUT
3
56
55
54
53
52
51
50
49
GPIO0/IS BLANK
GPIO1/CONVST
GPIO2/BUSY
GPIO3/ALERT0
D0+
D0–
D1+
D1–
48
47
46
45
V
IN
0
V
IN
1
V
IN
2
V
IN
3
44
43 AV
DD
AGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
FACTORY TEST
GPIO4/ALERT1
GPIO5/SLEEP0
GPIO6/SLEEP1
RESET
GPIO7/LDAC
SCLK
CS
DIN
DOUT
DGND
V
DRIVE
DV
DD
DACV
DD-UNI
REF
ADC
PAV
DD
PA_ON
RS0+
RS0–
RS1+
RS1–
AGND
RS2+
RS2–
RS3+
RS3–
V
CLAMP
0
V
CLAMP
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
TOP VIEW
(No t t o Scal e)
AD7293
NOTES
1. EXPOSED PAD. THE EXPOSED PAD IS LOCATED ON THE UNDERSIDE OF THE
PACKAGE . CO NNE CT T HE E X P OSED P AD TO AV
SS
USING MULTIPLE VIAS OR
LEAVE IT FLOATING.
13016-007
Figure 7. Pin Configuration
Table 11. Pin Function Descriptions
Pin Number
Mnemonic
Description
1 FACTORY TEST Factory Test Pin. Leave this pin unconnected, or connect it to DGND.
2
GPIO4/ALERT1
General-Purpose Input/Output 4 Pin (GPIO4).
Alert 1 Pin (ALERT1, Default). When configured as an alert, this pin acts as an out of range
indicator. The polarity of the pin is register selectable. This pin is an open-drain output, and
requires a pull-up resistor connected to VDRIVE.
3 GPIO5/SLEEP0 General-Purpose Input/Output 5 Pin (GPIO5).
Sleep 0 Pin (SLEEP0, Default). DAC power-down digital input pin (polarity is register
selectable). This pin can be configured to trigger DAC clamping on any combination of DAC
channels.
4 GPIO6/SLEEP1 General-Purpose Input/Output 6 Pin (GPIO6).
Sleep 1 Pin (SLEEP1, Default). DAC power-down digital input pin (polarity is register
selectable). This pin can be configured to trigger DAC clamping on any combination of DAC
channels.
5 RESET Reset Input. Taking this pin low performs a hardware reset.
6 GPIO7/LDAC General-Purpose Input/Output 7 Pin (GPIO7).
DAC Load Pin (LDAC, Default). When this input is active, the DAC registers are updated. The
polarity of this pin is register selectable. See the Load DAC (LDAC Pin) section for more
information.
7
SCLK
SPI Serial Clock Input.
8 CS Chip Select Signal. This active low, logic input signal frames the serial data input.
9 DIN SPI Serial Data Input. The serial data loaded into the registers is provided on this pin. Data is
clocked into the device on the rising edge of SCLK.
10 DOUT SPI Serial Data Output. The serial data read from the registers is provided on this pin. Data is
clocked out on the falling edge of SCLK. DOUT is high impedance when it is not outputting
data.
Data Sheet AD7293
Rev. D | Page 15 of 79
Pin Number
Mnemonic
Description
11 DGND Digital Ground. DGND is the ground reference point for all digital circuitry. Refer all digital
signals to DGND. Connect both the DGND and AGND pins to the ground plane of the system.
12 VDRIVE Drive Voltage Reference Level of the SPI Bus from 1.7 V to 5.5 V.
13 DVDD Digital Supply Voltage from 4.5 V to 5.5 V.
14 DACVDD-UNI DAC Positive Supply Pin for the Unipolar DAC Output Amplifiers on UNI-VOUT0, UNI-VOUT1,
UNI-VOUT2, and UNI-VOUT3.
15, 16, 18, 19 UNI-VOUT0, UNI-VOUT1,
UNI-VOUT2, UNI-VOUT3,
Unipolar DAC Outputs. The clamp and power-on reset voltage for these DACs is 0 V.
17, 22, 35, 43 AGND Analog Ground. Connect both the AGND and DGND pins to the ground plane of the system.
20 VREFIN Reference Input to the Device. Connect this pin to an external reference voltage, or tie this
pin to VREFOUT.
21 VREFOUT 2.5 V Reference Output. Connect to VREFIN to operate in internal reference mode. An optional
10 nF capacitor is recommended between the reference output and AGND for noise filtering.
23, 24, 27, 28 BI-VOUT0, BI-VOUT1,
BI-VOUT2, BI-VOUT3
Bipolar DAC Outputs in Open-Loop Mode and Integrator Outputs in Closed-Loop Mode. The
clamp and power-on reset voltage for these DACs is dictated by the VCLAMPx pins.
25 AVSS DAC Negative Supply Pin for the BI-VOUT0, BI-VOUT1, BI-VOUT2, and BI-VOUT3 DAC Output
Amplifiers.
26 DACVDD-BI Analog Supply Pin for BI-VOUT0, BI-VOUT1, BI-VOUT2, and BI-VOUT3. Connect AVDD and DACVDD-BI to
the same potential.
29 VCLAMP1 Power-On Reset and Clamp Voltage for BI-VOUT2 and BI-VOUT3.
30 VCLAMP0 Power-On Reset and Clamp Voltage for BI-VOUT0 and BI-VOUT1.
31, 33, 36, 38
RS3−, RS2−, RS1−, RS0−
Negative Connection for External Shunt Resistors.
32, 34, 37, 39
RS3+, RS2+, RS1+, RS0+
Positive Connection for External Shunt Resistors.
40 PA_ON Power Amplifier On. This pin drives an external, positive channel metal oxide semiconductor
(PMOS) switch capable of turning on/off the drain current to a PA transistor. The maximum
voltage is set by PAVDD and limited to AVSS + 60 V. The power amplifier is turned on when the
output is low. The AVSS and AVDD supply alarms can be configured to automatically trigger
PA_ON. An alert condition can be configured to trigger PA_ON. Additionally, PA_ON can be
turned on/off by issuing a register write.
41 PAVDD Power Supply for the PA_ON Control Signal. This pin is limited to 4 V to AVSS + 60 V.
42 REFADC Internal ADC Reference Voltage. The output at this pin is half the reference value (VREFIN),
1.25 V. Connect decoupling capacitors to this pin to decouple the reference buffer. For best
performance, connect a 4.7 µF compensation capacitor between REFADC and AGND. For
stability, the amplifier requires a minimum capacitance of 220 nF (X7R/C0G ceramic)
connected between REFADC and AGND, located as close to the AD7293 as possible (no more
than 1 Ω of interconnect resistance).
44 AVDD Supply Voltage for All of the Analog Circuitry on the AD7293. The operating range is 4.5 V to
5.5 V. Connect AVDD and DACVDD-BI to the same potential.
45 to 48
V
IN
3, V
IN
2, V
IN
1, V
IN
0
ADC Analog Inputs. Unused inputs must not be left floating. The input range of these pins is
register selectable: 0 V to 1.25 V, 0 V to 2.5 V, or 0 V to 5 V.
49, 50, 51, 52 D1−, D1+, D0−, D0+ Temperature Sensor Analog Inputs. Connect these pins to the external temperature sensing
transistor. Tie these pins to AGND if unused.
53 GPIO3/ALERT0 General-Purpose Input/Output 3 Pin (GPIO3, Default).
Alert 0 Pin (ALERT0). When ALERT0 is configured as an alert, this pin acts as an out of range
indicator. Open-drain output whether in GPIO mode or alert mode. The polarity of this pin is
register selectable. A pull-up resistor connected to VDRIVE is required.
54 GPIO2/BUSY General-Purpose Input/Output 2 Pin (GPIO2, Default).
Busy Pin (BUSY). When BUSY is configured as a busy output, this pin becomes active when a
conversion is in progress. Open-drain output whether in GPIO mode or busy mode. The
polarity of this pin is register selectable. A pull-up resistor connected to VDRIVE is required.
55 GPIO1/CONVST General-Purpose Input/Output 1 Pin (GPIO1, Default). This pin is an open-drain output in
GPIO mode. The polarity of this pin is register selectable.
ADC External Convert Start Input Pin (CONVST). CONVST triggers conversions via this pin. The
CONVST pin is useful for synchronizing the ADC sampling instant with an external source. A
pull-up resistor connected to VDRIVE is required in GPIO mode or if unused.
AD7293 Data Sheet
Rev. D | Page 16 of 79
Pin Number
Mnemonic
Description
56 GPIO0/IS BLANK General-Purpose Input/Output 0 Pin (GPIO0, Default). This pin is an open-drain output in
GPIO mode. The polarity of this pin is register selectable. A pull-up resistor connected to VDRIVE
is required in GPIO mode or if unused.
Current Sensor Conversion Blank Pin (IS BLANK). This pin can blank current sensor
conversions and the polarity of this pin is register selectable.
EPAD Exposed Pad. The exposed pad is located on the underside of the package. Connect the
exposed pad to AVSS using multiple vias or leave it floating.
Data Sheet AD7293
Rev. D | Page 17 of 79
TYPICAL PERFORMANCE CHARACTERISTICS
0
–180
–160
–120
–140
–100
–80
–60
–40
–20
0605040302010
AMPLITUDE (dBFS)
FRE Q UE NCY ( kHz )
13016-008
NONCO HE RE NT SAM P LI NG
SEVE N- TERM BLACKMAN- HARRIS WINDOW US E D
M = 131072 SAMPL E S
fS = 131.072kHz
fIN = 1.005kHz
SNR = 72. 6366dB
THD = –91.63d B
fIN = 1.005kHz
Figure 8. Signal-to-Noise Ratio, Single-Ended Input, 2 × REFADC Range
0
–180
–160
–120
–140
–100
–80
–60
–40
–20
0605040302010
AMPLITUDE (dBFS)
FRE Q UE NCY ( kHz )
13016-009
NONCO HE RE NT SAM P LI NG
SEVE N- TERM BLACKMAN- HARRIS WINDOW US E D
M = 131072 SAMPL E S
fS = 131.072kHz
fIN = 1.005kHz
SNR = 73. 5961dB
THD = –90.23d B
fIN = 1.005kHz
Figure 9. Signal-to-Noise Ratio, Differential Input, REFADC Range
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
04000350030002500200015001000500
DNL ( LSB)
CODE
13016-010
M = 131072 SAMPL E S
fS = 131.072kHz
fIN = 1.005kHz
RUNS = 20
EFFECTI VE SAMPLES = 2621440
HITS/ CODE = 640
Figure 10. ADC DNL Single-Ended, REFADC Range
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
04000350030002500200015001000500
INL (LSB)
CODE
13016-011
M = 131072 SAMPL E S
fS = 131.072kHz
fIN = 1.005kHz
RUNS = 20
EFFECTI VE SAMPLES = 2621440
HITS/ CODE = 640
Figure 11. ADC INL Single-Ended, REFADC Range
2.5
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
–40 120
100806040200–20
ZERO CO DE E RROR (LSB)
TEMPERATURE (°C)
13016-012
Figure 12. ADC Zero Code Error vs. Temperature
0
–6.5
–6.0
–5.5
–5.0
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
–40 120 140100806040200–20
FULL- S CALE E RROR
TEMPERATURE (°C)
13016-013
Figure 13. ADC Full-Scale Error vs. Temperature
AD7293 Data Sheet
Rev. D | Page 18 of 79
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
INL AND DNL ( LSB)
CODE
13016-014
40 540 1040 1540 2040 2540 3040 3540 4040
BIPOL AR DNL, –5V TO 0V
BIPOLAR INL, –5V TO 0V
BIPOL AR DNL, –4V TO +1V
BIPOLAR INL, –4V TO +1V
BIPOL AR DNL, 0V TO +5V
BIPOLAR INL, 0V TO +5V
Figure 14. Bipolar DAC INL and DNL
3
–3
–2
–1
0
1
2
INL AND DNL ( LSB)
CODE
13016-015
40 540 1040 1540 2040 2540 3040 3540 4040
DNL UNI P OL AR, 2. 5V TO 7.5V
INL UNIPOLAR, 2.5V TO 7.5V
DNL UNI P OL AR, 5V TO 10V
INL UNIP OL AR, 5V TO 10V
DNL UNI P OL AR, 0V TO 5V
INL UNIPOLAR, 0V TO 5V
Figure 15. Unipolar DAC INL and DNL
40
–40
–30
–20
–10
0
10
20
30
0 5 10 15 20 25 30 35 40
VOLTAGE (µ V)
TIME (Seconds)
13016-016
Figure 16. 0.1 Hz to 10 Hz DAC Output Noise, Input Code 0x000
400
0
50
100
150
200
250
300
350
0500 1000 1500 2000 2500 3000 3500 4500
4000
DAC OUTPUT NOISE (µV p-p)
CODE
13016-017
EXTERNA
LREFERENCE, 0VTO+5V, UNIPOLAR DAC
EXTERNA
LREFERENCE,+5VTO+10V, UNIPOLAR DAC
INTERNALREFERENCE, +5VTO+10V, UNIPOLAR
INTERNA
LREFERENCE, 0VTO+5V, BIPOLAR DAC
INTERNA
LREFERENCE, –5VTO0V, BIPOLAR DAC
INTERNA
LREFERENCE, 0VTO+5V, UNIPOLAR DAC
INTERNALREFERENCE, –4V TO+1V,BIPOLAR DAC
EXTERNALREFERENCE, 0V TO+5V, BIPOLAR DAC
EXTERNAL REFERENCE, –4V TO+1V,BIPOLAR DAC
EXTERNALREFERENCE, –5V TO0V, BIPOLAR DAC
Figure 17. 0.1 Hz to 10 Hz DAC Output Noise vs. Code
4.00
3.75
3.50 0 2 4 6 8 10 12 14 16 28 20
DAC OUTPUT VOLTAGE (V)
TIME (µs)
13016-018
BIPOLAR, 0nF
BIPOLAR, 1nF
BIPOL AR, 10n F
UNIPOL AR, 0n F
UNIPOL AR, 1n F
UNIPOL AR, 10n F
Figure 18. Zoomed In Settling Time for a ¼ to ¾ Output Voltage Step
5.05
4.65
4.70
4.75
4.80
4.85
4.90
4.95
5.00
0246810 12 14 16
DAC4 OUTPUT ( V )
LOAD CURRENT ( mA)
13016-019
0V TO 5V, CODE 4095 ( FUL L SCAL E )
0V TO 5V, CODE 3850 ( FUL L SCAL E – 300mV)
Figure 19. DAC4 Output (Full Scale) vs. Load Current
Data Sheet AD7293
Rev. D | Page 19 of 79
–4.65
–5.05
–5.00
–4.95
–4.90
–4.85
–4.80
–4.75
–4.70
–16 –14 –12 –10 –8 –6 –4 –2 0
BI-VOUT0 O UTPUT (V)
LOAD CURRENT ( mA)
13016-020
–5V T O 0V , CO DE 246 ( ZERO SCALE + 300mV )
–5V T O 0V , CO DE 0 ( ZERO SCALE)
Figure 20. BI-VOUT0 Output Voltage (Zero Scale) vs. Load Current
6
–6
–4
–2
0
2
4
–80 –60 –40 –20 020 40 60 80
BI-VOUT0 O UTPUT (V)
LOAD CURRENT ( mA)
13016-021
BI-VOUT00/ 4 S CALE
BI-VOUT01/ 4 S CALE
BI-VOUT02/ 4 S CALE
BI-VOUT03/ 4 S CALE
BI-VOUT04/ 4 S CALE
Figure 21. BI-VOUT0 Output Voltage vs. Load Current
500
–500
–400
–300
–200
–100
0
100
200
300
400
–40 120100806040200–20
GAI N E RROR (m%)
TEMPERATURE (°C)
13016-022
UNIPOL AR GAI N E RROR, +2.5V TO + 7.5V
UNIPOL AR GAI N E RROR, +5V TO + 10V
UNIPOL AR GAI N E RROR, 0V TO + 5V
BIPOL AR GAI N E RROR, 0V TO + 5V
BIPOL AR GAI N E RROR, –4V TO + 1V
BIPOL AR GAI N E RROR, –5V TO 0V
Figure 22. DAC Gain Error vs. Temperature
16
–4
–2
0
2
4
6
8
10
12
14
–40 120100806040200–20
OFF SET ERROR (mV)
TEMPERATURE (°C)
13016-023
UNIPOLAR OFFSET ERROR 0V TO +5V
UNIPOLAR OFFSET ERROR +2.5V TO +7.5V
UNIPOL AR OF FSE T ERRO R + 5V TO + 10V
BIPOLAR OFFSET ERROR 0V TO +5V
BIPOLAR OFFSET ERROR –4V TO +1V
BIPOLAR OFFSET ERROR –5V TO 0V
Figure 23. DAC Offset Error vs. Temperature
12
11
10
9
8
7
6
5
4
3
2
1
0
–1
–4.45
–5.10
–5.05
–5.00
–4.95
–4.90
–4.85
–4.80
–4.75
–4.70
–4.65
–4.60
–4.55
–4.50
0510 15 20 25 30 35 40
AV
DD
AND PA_ON (V)
AV
SS
AND BIPOL AR DAC OUT P UT (V )
TIME (ms)
13016-024
AVDD
PA_ON
AVSS
DAC BIPOL AR OUT P UT
Figure 24. Bipolar DAC Response to AVDD Failure
10
5
0
–5
–10
–15
–20 0500 1000 1500 2000 2500 3000 3500 4000
GLITCH ENE RGY ( nV-sec)
CODE
13016-025
UNIPOLAR, 0V TO 5V, HIGH TO LOW
UNIPOLAR, 5V TO 10V, LOW TO HIGH
UNIPOLAR, 0V TO 5V, LOW TO HIGH
BIPOLAR, 0V TO 5V, HIGH TO LOW
UNIPOLAR, 5V TO 10V, HIGH TO LOW
BIPOLAR, 0V TO 5V, LOW TO HIGH
Figure 25. DAC Glitch Energy vs. Code
AD7293 Data Sheet
Rev. D | Page 20 of 79
10 100001000100
TE M P ERATURE E RROR
NORMALIZED TO 20pF POINT (°C)
CAPACITANCE ( pF )
13016-026
–7.5
–7.0
–6.5
–6.0
–5.5
–5.0
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
SENSOR RES ULT AT +25°C
SENSOR RES ULT AT +105°C
SENSOR RES ULT AT +150°C
SENSOR RES ULT AT –40° C
Figure 26. Temperature Error vs. Capacitance from Dx+ to Dx−
0109
876
54321
TE M P ERATURE E RROR
NORMALIZED TO 0Ω POINT (°C)
SERIES RESISTANCE (kΩ)
13016-027
–0.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
SENSO R RESUL T AT +25 ° C
SENSO R RESUL T AT +10 5° C
SENSO R RESUL T AT +15 0° C
SENSO R RESUL T AT – 40 ° C
SENSO R RESUL T AT – 55 ° C
Figure 27. Temperature Error vs. Series Resistance for Typical Devices
–40 –20 020 40 60 80 100 120
TE M P ERATURE S E NS OR ERROR (°C)
DUT TEMP E RATURE ( °C)
13016-028
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
Figure 28. Temperature Sensor Error vs. Device Under Test (DUT)
Temperature
–60
–120
–115
–110
–105
–100
–95
–90
–85
–80
–75
–70
–65
100 100M10M1M100k10k1k
AC CMRR (dB)
FRE Q UE NCY ( Hz )
13016-030
Figure 29. High-Side Current Sensor at Common-Mode Rejection Ratio (CMRR)
2.504
2.495
2.496
2.497
2.498
2.499
2.500
2.501
2.502
2.503
–60 –40 140120100806040200–20
ADC REF ERE NCE ( V )
TEMPERATURE (°C)
13016-031
TESTER TRIMM ED DUT 1
TESTER TRIMM ED DUT 6
TESTER TRIMM ED DUT 4
TESTER TRIMM ED DUT 9
TESTER TRIMM ED DUT 5
TESTER TRIMM ED DUT 10
TESTER TRIMM ED DUT 11
TESTER TRIMM ED DUT 2
TESTER TRIMM ED DUT 7
TESTER TRIMM ED DUT 12
TESTER TRIMM ED DUT 3
TESTER TRIMM ED DUT 8
TESTER TRIMM ED DUT 13
Figure 30. ADC Reference vs. Temperature
–40 –20 120100806040200
R
SENSE
VOLTAGE REGULATION (V)
TEMPERATURE (°C)
13016-033
0.10002
0.10004
0.10006
0.10008
0.10010
0.10012
0.10014
0.10016
0.10018
0.10020
0.10022 M IDSCAL E DRIF T W ITH E X TERNAL REFERENCE
MI DS CALE DRI FT WI TH INTERNAL REFERENCE
Figure 31. Closed-Loop RSENSE Voltage Regulation vs. Temperature
Data Sheet AD7293
Rev. D | Page 21 of 79
0.8
0.3
–0.2
–0.7
–1.2
–1.7
INL AND DNL ( LSB)
DAC (Co des)
13016-034
0
256
512
768
1024
1280
1536
1792
2048
2304
2560
2816
3072
3328
3584
3840
4096
DNL: +25°C
INL : +25° C
INL : +125° C
DNL: +125°C
DNL: –40°C
INL : –40°C
Figure 32. Closed-Loop INL and DNL
–1.5
–5.0
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
01067 8 954321
C
L
TO CLAMP TRANSITION VOLTAGE (V)
TIME (µs)
13016-035
BIPOL AR CHANNE L 0
10% LINE
1% LINE POSTIVE
1% LINE NEGAT IVE
TIME Z ERO
Figure 33. Open Loop to Clamp Settling Time
–1.5
–5.0
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
010
9
87
654321
CL TO CLAMP TRANSITION VOLTAGE (V)
TIME (µs)
13016-150
BIPOL AR CHANNE L 0
10% LINE
1% LINE POSITIVE
1% LINE NEGAT IVE
TIME Z ERO
Figure 34. Closed Loop to Clamp Settling Time
AD7293 Data Sheet
Rev. D | Page 22 of 79
THEORY OF OPERATION
ANALOG-TO-DIGITAL CONVERTER (ADC)
OVERVIEW
The AD7293 provides the user with a multichannel multiplexer,
an on-chip track-and-hold, and a successive approximation ADC
based around a capacitive DAC. The analog input range for the
ADC is selectable as a 0 V to REFADC, 0 V to 2 × REFADC, or 0 V
to 4 × REFADC input single-ended input, where REFADC = 1.25 V.
The various monitored and uncommitted input signals are
multiplexed into the ADC. The AD7293 has four uncommitted
analog input channels, VIN0 to VIN3.
ADC TRANSFER FUNCTIONS
The designed code transitions occur at successive integer least
significant bit (LSB) values (1 LSB, 2 × LSB, and so on). The
reference voltage for the ADC is referred from the main 2.5 V
reference through an amplifier that attenuates the voltage by
one half. REFADC = 1.25 V.
In single-ended mode, the LSB size is REFADC/4096 when the
0 V to REFADC range is selected, 2 × REFADC/4096 when the 0 V
to 2 × REFADC range is selected, and 4 × REFADC/4096 when the
0 V to 4 × REFADC range is selected (which is the default value).
Figure 35 shows the ideal transfer characteristic for the ADC
when outputting straight binary coding.
13016-037
000...000
111...111
1LSB REF
ADC
– 1LS B
ANALOG INPUT
ADC CODE
0V
000...001
000...010
111...110
111...000
011...111
1LS B = RE F
ADC
/4096
NOTES
1.REF
ADC
IS REF
ADC
, 2 × RE F
ADC
, O R 4 × RE F
ADC
.
Figure 35. Single-Ended Transfer Characteristics
In differential mode, the LSB size is 2 × REFADC/4096 when the
0 V to REFADC range is selected, 4 × REFADC/4096 when the 0 V to
2 × REFADC range is selected, and 8 × REFADC/4096 when the 0 V
to 4 × REFADC range is selected. Figure 36 shows the ideal transfer
characteristic for the ADC when outputting differential coding
(with the 2 × REFADC range).
13016-038
ANALO G I NP UT
ADC CODE
100...000
011...111
REF
ADC
– 1LSB0–REF
ADC
+ 1LS B
100...001
100...010
011...110
000...001
000...000
111...111
1LSB = 2 × RE F
ADC
/4096
Figure 36. Differential Transfer Characteristics
Table 12. Code Transition and Voltage
Code
Transition
Single-Ended
Voltage (VIN)
Differential Voltage
(VIN+ − VIN−)
0x000 to 0x001 REFADC × Range/4096 −REFADC × Range ×
2047/2048
0x7FF to 0x800
REF
ADC
× Range/2
0 V
0xFFE to 0xFFF REFADC × Range ×
4095/4096
+REFADC × Range ×
2047/2048
For VIN0 to VIN3 in single-ended mode, the output code is
straight binary, and the ideal input voltage is given by
VIN = ((Code + 0.5)/ 4096) × REFADC × Range
The differential code is shown in Table 12, and the associated
voltage is calculated by
VIN+ − VIN− = ((Code − 2047.5)/2048) × REFADC × Range
where:
Code is the decimal equivalent of the binary code read from the
ADC register.
REFADC = 1.25 V.
Range = 1 when in the 0 V to REFADC range.
Range = 2 when in the 0 V to 2 × REFADC range.
Range = 4 when in the 0 V to 4 × REFADC range.
Table 13. ADC Range Selected vs. LSB Size
Range Value
Single-Ended
ADC LSB
Differential
ADC LSB
00 4 × REFADC1 4 × REFADC/4096 8 × REFADC/4096
01 2 × REFADC1 2 × REFADC/4096 4 × REFADC/4096
10
2 × REF
ADC1
2 × REF
ADC
/4096
4 × REF
ADC
/4096
11 REFADC1 REFADC/4096 2 × REFADC/4096
1 REFADC = 1.25 V.
Data Sheet AD7293
Rev. D | Page 23 of 79
ANALOG INPUTS
The AD7293 has four analog inputs, VIN3 to VIN0. Depending
on the configuration register setup, they can be configured as
four single-ended inputs or two fully differential channels.
Single-Ended Mode
The AD7293 can have four single-ended analog input channels.
In applications where the signal source is high impedance, it is
recommended to buffer the analog input before applying it to the
ADC. The analog input range is programmed to the following
modes: 0 V to REFADC, 0 V to 2 × REFADC, or 4 × REFADC mode.
The voltage, with respect to AGND on the ADC analog input
pins, cannot exceed AVDD.
Differential Mode
The AD7293 can have two differential input pairs (VIN3 and VIN2,
VIN1 and VIN0). The amplitude of the differential signal is the
difference between the signals at VIN+ and VIN− (VIN0 and VIN1,
or VIN3 and VIN2). Simultaneously drive VIN+ and VIN− by two
signals, each of amplitude REFADC, 2 × REFADC, or 4 × REFADC,
depending on the range chosen, which are 180° out of phase.
V
IN+
AD72931
V
IN–
ADC
REF
p-p
ADC
REF
p-p
COMMON-MODE
VOLTAGE
1
ADDITIONAL PINS OMITTED FOR CLARITY.
13016-039
Figure 37. Differential Input (VIN+/VIN− Refer to VIN0 to VIN3)
Assuming that the 0 V to REFADC range is selected, the amplitude
of the differential signal is, therefore, −REFADC to +REFADC peak
to peak, regardless of the common-mode voltage (VCM).
The common-mode voltage is the average of the two signals.
(VIN+ + VIN−)/2
The common-mode voltage is the voltage on which the two
inputs are centered. The result is that the span of each input is
VCM ± REFADC/2. This common-mode voltage must be set up
externally.
When a conversion takes place, the common-mode voltage is
rejected, resulting in a virtually noise free signal of amplitude
−REFADC to +REFADC, corresponding to the digital output codes
of −2048 to +2047 in twos complement format.
When using the 2 × REFADC range, the input signal amplitude
extends from −2 × REFADC (VIN+ = 0 V and VIN− = REFADC) to
+2 × REFADC (VIN− = 0 V and VIN+ = REFADC).
Similarly, when using the 4 × REFADC range, the input signal
amplitude extends from −4 × REFADC (VIN+ = 0 V and VIN− =
REFADC) to +4 × REFADC (VIN− = 0 V and VIN+ = REFADC).
Pseudo Differential Mode
The four uncommitted analog input channels can be configured
as two pseudo differential pairs. Two uncommitted inputs, VIN0
and VIN1, are a pseudo differential pair, as are VIN2 and VIN3. In
this mode, VIN+ is connected to the signal source, which can have
a maximum amplitude of REFADC, 2 × REFADC, or 4 × REFADC,
depending on the range that is chosen, to make use of the full
dynamic range of the device. A dc input is applied to VIN−. The
voltage applied to this input provides an offset from ground or a
pseudo ground for the VIN+ input. The ADC channel allocation
determines the channel specified as VIN+. The differential mode
must be selected to operate in the pseudo differential mode. The
resulting converted pseudo differential data is stored in twos
complement format in the result register.
For VIN0, the governing equation for the pseudo differential
mode is
VOUT = 2(VIN+ − VIN−) − REFADC
where:
VIN+ is the single-ended signal.
VIN− is a dc voltage.
REFADC = 1.25 V.
The benefit of pseudo differential inputs is that they separate
the analog input signal ground from the ADC ground, allowing
dc common-mode voltages to be cancelled.
1
ADDITIONAL PINS OMITTED FOR CLARITY.
AD7293
1
V
IN+
V
IN–
DC INPUT
VOLTAGE
V
REF
p-p
13016-040
Figure 38. Pseudo Differential Input (VIN+/VIN− Refer to VIN0 to VIN3)
CURRENT SENSOR
Four bidirectional high-side current sense amplifiers are
provided that can accurately amplify differential current shunt
voltages in the presence of high common-mode voltages from
AVDD up to AVSS + 60 V. The current sensors can be read
directly, or optionally, they can be set to operate as part of the four
independent closed-loop, drain current controllers. See the
Closed-Loop Mode section for more information.
In open-loop operation, the current sense amplifiers measure
the current through a shunt resistor. Each amplifier can accept
differential inputs up to ±200 mV. A selectable gain amplifies
the measured voltage drop across the current sensor.
AD7293 Data Sheet
Rev. D | Page 24 of 79
The AD7293 high-side current sense amplifier is configured as
a differential integrator.
13016-0102
224kΩ
224kΩ
+
–
–
+
6pF
6pF
RESET
RESET
RSx+
RSx–
RESET, HOLD
Figure 39. Current Sensor Internal Diagram
Before each measurement, the integrator is held in a reset state
for 9.2 µs. The input is then connected and measured for a
programmable amount of time, resulting in a gain equal to the
following:
Gain = Integration Time/(224 kΩ × 6 pF)
Table 14. Current Sensor Gain Settings
Code
Typical
Gain
Voltage Across
RSENSE1 (mV)
Typical
Integration
Time (µs)
0000 (Default) 6.25 ±200 8.4
0001 12.5 ±100 16.8
0010 18.75 ±66.67 25.2
0011 25 ±50 33.6
0100 37.5 ±33.33 50.4
0101 50 ±25 67.2
0110
75
±16.67
100.8
0111 100 ±12.5 134.4
1000 200 ±6.25 268.8
1001 400 ±3.125 537.6
1010 781.25 ±1.6 1050
1 RSENSE is the external sense resistor.
When integration is complete, the input switches open, keeping
the output constant until the ADC completes its conversion of
the output signal. If no other ADC channels are enabled, the
conversion takes an additional 4.2 µs. Otherwise, the current
sense amplifier waits for its turn in the ADC conversion
sequence before resetting and starting a new measurement.
Keep the external source impedance low with respect to the
input resistance of the integrator to avoid creating a gain error.
Calculate the current sensor input channel LSB as follows:
VSENSE LSB = (2 × REFADC)/(Gain × 4096)
VRSx+ − VRSx− = −REFADC/Gain, with DOUT = 0x000
VRSx+ − VRSx− = 0 V, with DOUT = 0x7FF
VRSx+ − VRSx− = REFADC/Gain, with DOUT = 0xFFF
where:
VSENSE LSB is the current sense input channel LSB size in volts.
VRSx+ is the voltage for the RSx+ pins.
VRSx− is the voltage for the RSx− pins.
REFADC = 1.25 V.
Gain can be set between 6.25 and 781.25 as shown in Tabl e 14.
ISENSE LSB = 2 × (REFADC/(Gain × 4096 × RSENSE))
where:
ISENSE LSB is the current sense input channel LSB size in
amperes.
RSENSE is the external sense resistor.
Choosing the External Sense Resistor (RSENSE)
The resistor values used in conjunction with the current sense
amplifiers on the AD7293 are determined by the specific applica-
tion requirements in terms of voltage, current, and power.
Small resistors minimize power dissipation, have low induct-
ance to prevent induced voltage spikes, and have good tolerance,
which reduces current variations. The final values chosen are a
compromise between low power dissipation and good accuracy.
Low value resistors have less power dissipation and good accu-
racy; however, higher value resistors may be required to use the
full input range of the ADC.
When the sense current is known, the voltage range of the
AD7293 current sensor is divided by the maximum sense
current to yield a suitable resistor value. If the power dissipation
in the shunt resistor is too large, the shunt resistor can be
reduced, in which case, the current sensor gain can be increased
to maximize the ADC input range used.
RSENSE must be able to dissipate the I2R losses. If the power
dissipation rating of the resistor is exceeded, its value may drift,
or the resistor may be damaged, resulting in an open circuit. If
the power dissipation of the resistor is exceeded, it can result in
a differential voltage across the AD7293 terminals in excess of
the absolute maximum ratings.
)(MAXSENSE
SENSE
I
RangeVoltageInputSensorCurrent
R≤
where:
RSENSE is the value of the current sense resistor in Ω.
Current Sensor Input Voltage Range is the current sensor
amplifier input voltage range as dictated by the gain setting
chosen (see Table 14).
ISENSE (MAX) is the maximum current required in A.
TEMPERATURE SENSOR
The AD7293 contains one local and two remote temperature
sensors. The temperature sensors can continuously monitor the
three temperature inputs, and new readings are automatically
available every 5 ms.
The on-chip temperature sensor measures the device die
temperature. The internal temperature sensor measures
between −40°C and 125°C, where the LSB size is 0.125°C.
The AD7293 includes two remote temperate sensors. The
device is factory calibrated to work with 2N3906 discrete
transistors.
Data Sheet AD7293
Rev. D | Page 25 of 79
For RF applications, the use of high Q capacitors functioning as
a filter protects the integrity of the measurement. Connect these
capacitors between the base and the emitter, as close to the
external device as possible. However, large capacitances affect
the accuracy of the temperature measurement; therefore, the
recommended maximum capacitor value is 100 pF. In most
cases, a capacitor is not required; the selection of any capacitor
is dependent on the noise frequency level.
The AD7293 automatically cancels out the effect of parasitic,
base, and collector resistance on the temperature reading. This
cancelation gives a more accurate result, without the need for
any user characterization of the parasitic resistance. The AD7293
can compensate for up to 4 kΩ series resistance typically.
2N3904
NPN
AD7293
Dx+
Dx–
10pF
13016-042
Figure 40. Measuring Temperature Using a NPN Transistor
10pF
2
N3906
PNP
AD7293
Dx+
Dx–
13016-043
Figure 41. Measuring Temperature Using a PNP Transistor
Table 15. Temperature Sensor Data Format
Temperature
(°C)
TSENSEx Result Registers (Page 0x00,
Register 0x20 to Register 0x22), Bits[D15:D4]
−40 0110 1100 0000
−25 0111 0011 1000
−10 0111 1011 0000
−0.125 0111 1111 1111
0 1000 0000 0000
+0.125 1000 0000 0001
+10 1000 0101 0000
+25 1000 1100 1000
+50 1001 10 01 0000
+75 1010 0101 1000
+100 1011 0010 0000
+125 1011 1110 1000
INTERNAL CHANNEL MONITORING
The ADC can internally read the outputs of the four bipolar
DACs, AVDD, DACVDD-UNI, DACVDD-BI, AVSS, and the voltage on
the RS0+ to RS3+ pins in the background. A sequencer is
available that allows multiple channels to be converted in a
predetermined sequence.
The ADC is used in its single-ended mode. The LSB size varies
with the different supply monitoring registers. AVDD and DACVDD-BI
are divided by 5, and DACVDD-UNI is divided by 20 to scale within
the 0 V to REFADC range. AVSS is divided by 8 and level shifted
to within a −7.5 V to +2.5 V range, where 0x000 equates to
approximately −7.5 V, and 0xFFF equates to approximately
+2.5 V. REFADC = 1.25 V. For RSx+MON (internal monitoring of
the voltage on the RS0+ to RS3+ pins), divide by 50 to scale
them to the 0 V to REFADC range. For BI-VOUTxMON, divide by 8
and level shift within a −5 V to +5 V range, where 0x000
equates to approximately −5 V, and 0xFFF equates to approx-
imately +5 V. The RSx+MON monitor result registers store the 12-bit
ADC results for the current sense supply channels (see Figure 42).
12-BIT
SAR ADC
MUX
0V TO +1.25V0V TO +62.5V
RS0+
MON
0V TO +1.25V0V TO +62.5V
RS1+
MON
0V TO +1.25V0V TO +62.5V
RS2+
MON
0V TO +1.25V0V TO +62.5V
RS3+
MON
0V TO +1.25V–5V TO +5V
BI-V
OUT
0
MON
0V TO +1.25V–5V TO +5V
BI-V
OUT
1
MON
0V TO +1.25V–5V TO +5V
BI-V
OUT
2
MON
0V TO +1.25V–5V TO +5V
BI-V
OUT
3
MON
0V TO +1.25V0V TO +6.25V
DACV
DD-BI
0V TO +1.25V0V TO 25V
DACV
DD-UNI
0V TO +1.25V–7.5V TO +2.5V
AV
SS
0V TO +1.25V0V TO +6.25V
AV
DD
13016-044
Figure 42. Internal Channel Monitoring
DAC OPERATION
The AD7293 contains eight 12-bit DACs, four bipolar DACs,
and four unipolar DACs. These provide digital control with 12 bits
of resolution combined with offset range select registers and a
2.5 V internal reference. The DAC core is a 12-bit string DAC. The
resistor string structure consists of a string of resistors, each of
Value R. The code loaded to the DAC register determines at
which node on the string the voltage is tapped off to be fed into
the output amplifier. When one of the switches connecting the
string to an amplifier is closed, the voltage is tapped off. This
architecture is inherently monotonic and linear. The eight DACs
are split into two groups based on their output range.
Bipolar DACs
The bipolar DACs (BI-VOUT0, BI-VOUT1, BI-VOUT2, and BI-VOUT3)
can be configured through the offset range registers to 0 V to
+5 V, −5 V to 0 V, or −4 V to +1 V (see Table 85).
Writing to these register addresses sets the 12-bit DAC output
voltage. There is also a load bit and a copy bit (see Table 27).
If the load bit is set to 1, the device waits for LDAC to become
active before loading the voltage codes onto the DACs rather than
immediately after the write operation. If the copy bit is set to 1
when writing to a bipolar DAC register, it sets all bipolar DAC
registers to the same value in open-loop mode only.
AD7293 Data Sheet
Rev. D | Page 26 of 79
OFFSET
n
REFIN
OUT
V
D
VV +
××=
2
2
where:
VREFIN = 2.5 V.
D is the decimal equivalent of the binary code that is loaded to
the DAC register (0 to 4095 for the 12-bit AD7293).
n is the resolution of the DAC.
VOFFSET = 0 V (0 V to +5 V range), −4 V (−4 V to +1 V range), or
−5 V (−5 V to 0 V range).
Table 16. Bipolar DAC Voltage Offset Ranges
Range (V) 0x000 0xFFF VOFFSET (V )
0 to +5 0 V 2 V × VREFIN 0
−4 to +1 −1.6 V × VREFIN 0.4 V × VREFIN −4
−5 to 0 −2 V × VREFIN 0 V −5
The ADC can also monitor these four outputs.
The bipolar DACs in addition to the four current sensors in the
PA controller can operate as four independent closed-loop
drain current controllers (see the Closed-Loop Mode section).
13016-146
RESISTOR
STRING
REF(+)
REF(–) –3
2.5V
REF
INPUT
REGISTER DAC
REGISTER
V
CLAMP
X
CLAMP/
DAC
ENABLE RANGE
SELECT
BI-V
OUT
X
0V TO +5V
–4V T O + 1V
–5V T O 0V
Figure 43. Bipolar DAC Architecture Block Diagram
Unipolar DACs
The unipolar DAC outputs, UNI-VOUT0, UNI-VOUT1, UNI-
VOUT2, and UNI-VOUT3, can be configured through the offset
range registers to 0 to 5 V, 2.5 V to 7.5 V, or 5 V to 10 V (see
Table 84).
The DACs have one control register to control the interaction
between two registers: input registers and output registers. The
output registers contain the digital code used by the resistor
strings as well as a copy and load bit. Writing to these register
addresses sets the 12-bit DAC output voltage codes.
If the load bit is set to one, the device waits for LDAC to become
active before loading the voltage codes onto the DACs rather than
immediately after the write operation. If the copy bit is set to 1,
writing to a unipolar DAC registers sets all the other unipolar
DAC registers to the same value.
OFFSET
n
REFIN
OUT V
D
V
V+
××
=
2
2
where:
VREFIN = 2.5 V.
D is the decimal equivalent of the binary code that is loaded to
the DAC register (0 to 4095 for the 12-bit AD7293).
n is the resolution of the DAC.
VOFFSET = 0 V (0 V to 5 V range), 2.5 V (2.5 V to 7.5 V range), or
5 V (5 V to 10 V range).
13016-147
RESISTOR
STRING
REF(+)
REF(–)
2.5V
REF
INPUT
REGISTER DAC
REGISTER
CLAMP/
DAC
ENABLE RANGE
SELECT
UNI-V
OUT
X
0V TO 5V
2.5V TO 7.5V
5V TO 10V
Figure 44. Unipolar DAC Architecture Block Diagram
Table 17. Unipolar DAC Voltage Offset Ranges
Range (V) 0x000 0xFFF VOFFSET (V)
0 to 5 0 V 2 V × VREFIN 0
2.5 to 7.5 VREFIN 3 V × VREFIN 2.5
5 to 10 2 V × VREFIN 4 V × VREFIN 5
DAC Enabling and Clamping
On power-up, the DAC outputs default to their clamp values
(see Table 18). All DACs can be enabled and disabled/clamped
via the DAC enable register (common to all pages).
Table 18. Clamp Values
DAC Output Clamp Value
UNI-VOUT0 0 V
UNI-VOUT1 0 V
UNI-VOUT2 0 V
UNI-VOUT3 0 V
BI-VOUT0 −3 × VCLAMP0
BI-VOUT1 −3 × VCLAMP0
BI-VOUT2 −3 × VCLAMP1
BI-VOUT3 −3 × VCLAMP1
All DACs (bipolar DACs only on power-up) can be set to clamp
using the digital SLEEP0 and SLEEP1 pins. The DAC outputs
controlled by the digital SLEEP0 and SLEEP1 pins are selectable by
writing to the corresponding sleep bit in the DAC snooze/SLEEPx
pin register (see Table 45) in the configuration page. When the
SLEEPx pin is pulled active, the corresponding unipolar and
bipolar DACs associated with the pin are forced into clamp.
Clamping does not clear the DAC output register value, making
it possible to return to the same voltage as before the clamp
event. While in clamp mode, the DAC registers can be updated.
When a SLEEPx pin is used, a snooze function is available that
clears the DAC registers and requires an additional write to the
DAC enable register to wake up the DAC after clearing the clamp
condition.
Data Sheet AD7293
Rev. D | Page 27 of 79
The bipolar DACs power-on reset and clamp value is dependent
on the VCLAMP0 and VCLAMP1 voltage level. After a power-on reset
or when the digital SLEEP0 or SLEEP1 pin is configured to trigger
a clamp, the bipolar DAC outputs reset to the clamp value (see
Table 18).
After a power-on reset or when the digital SLEEP0 or SLEEP1
pin is configured to trigger clamping, the unipolar DAC outputs
default to 0 V.
Software Clamping: Internal ALERT0 Routing
There is an option to allow the ALERT0 alert to trigger the
clamp function. The DACs power back up when the alert is
cleared without an additional write to the DAC enable registers.
Bit D1 of the general register in the configuration page allows
ALERT0 control over the clamping function of the four bipolar
DACs.
PMOS Drain Switch Control
The AD7293 PA_ON output pin is capable of driving an
external PMOS switch. This external PMOS turns on or off the
drain current to a PA field effect transistor (FET). The PA_ON
output pin controls the device during power-up and power-down.
This feature can also be used as a protection feature when an
alert condition is detected because ALERT0 alerts or an AVSS or
AVDD supply failure can be used to trigger the PA_ON pin.
PAVDD determines the maximum voltage at the output of the
PA_ON pin. The off state is equal to PAVDD while the on state is
equal to AGND. The default state of the PA_ON signal is off.
PAV
DD
PA_ON
PMOS
CONTROL
R
SENSE
V p-p
PMOS
DRAIN
SWITCH
RSx+
RSx–
CURRENT
SENSOR
PA FET
FILTER
RF IN
CHOKE
RF OUT
13016-045
Figure 45. PMOS Drain Switch Control
REFERENCE
The AD7293 has one high performance, 2.5 V on-chip reference
accessed via the VREFOUT pin. Noise performance can be improved
by the addition of a 10 nF capacitor between the VREFOUT pin and
the AGND pin. Connect VREFOUT to the VREFIN pin to use the
on-chip reference of the AD7293. An internal amplifier attenu-
ates to the ADC core, making the voltage at the ADC, REFADC =
1.25 V, half of VREFIN = 2.5 V. Use the REFADC pin for measurement
purposes only.
A 220 nF capacitor is required on the REFADC pin and must be
placed as close to the AD7293 as possible with no vias. The
internal reference typically requires 20 ms to power up and settle
when using a 220 nF decoupling capacitor on the REFADC pin.
Buffer the internal reference before it is used by external circuitry.
The AD7293 can also operate with an external reference of
2.5 V connected to the VREFIN pin.
If using an external reference, select a low temperature coefficient
specification, such as the ADR4525, to reduce the temperature
dependence of the system output voltage on ambient conditions.
VDRIVE FEATURE
The AD7293 also has a VDRIVE feature that controls the voltage at
which the SPI operates. Connect the VDRIVE pin to the supply to
which the SPI bus is pulled. The VDRIVE pin sets the input and
output threshold levels for the digital logic pins. The VDRIVE
feature allows the AD7293 to interface with 1.8 V, 3.3 V, and 5 V
processors.
OPEN-LOOP MODE
In open-loop mode, the default mode of operation, the current
sense amplifiers and bipolar DACs operate independently.
CLOSED-LOOP MODE
Alternatively, the AD7293 current sensors and bipolar DACs
can operate as four independent closed-loop drain current
controllers (closed-loop mode).
In closed-loop operation, the drain current through the PA FET
is set and automatically maintained by the PA controller through a
regulation circuit that includes the DAC and current sense moni-
tor. The control loop sets the PA bias current and continuously
maintains a constant voltage across the sense resistor (VSENSE =
ISENSE × RSENSE). When the DAC current updates, the closed-loop
adjusts the gate voltage of the PA until the drain current matches
the corresponding DAC code. The continuous regulation of the
loop compensates for variations of the PA threshold or voltage
drop on the LPF due to the PA gate current. The integrator
leads to a smooth transition on the output of the pin.
RSx+
RSx–
LPF
Σ
BIPOLAR
DAC
(PROGRAMMABLE
RAMP T IM E)
AD7293
13016-046
Figure 46. Closed-Loop Control
AD7293 Data Sheet
Rev. D | Page 28 of 79
Each of the four current closed loops consists of a DAC, an
error amplifier, and an integrator in the forward path to drive
the gate of the PA FET. A high-side current sense amplifier in
the feedback path senses that PA drain bias current and closes
the loop.
An external gate filter can be introduced between the gate of the
power amplifier and the integrator output pins when operating
in closed-loop mode to limit the noise bandwidth and to ensure
PA stability. The gate filter time constant (τG) must be between
5 µs and 50 µs.
Adjustable Closed-Loop Setpoint Ramp Time
The transition between two successive setpoints of the DAC are
interpolated in a linear manner with the aid of a ramp generator.
When moving to a new closed-loop setpoint, limiting the rate of
change of the drain current is often required. To facilitate this,
the AD7293 can automatically generate a linear ramp between
the old and new DAC settings, over a programmable duration.
Write to the ramp time register to enable this feature, which
allows ramp times of between 4 ms and 31.75 ms to generate,
programmable in 250 µs steps. If a value of less than 4 ms is
written to the register, the ramp generator disables, and the new
target DAC code is set immediately. Depending on the overall
loop time constant, an additional settling time can be required
after the end of the ramp for the drain current to reach the
prescribed set point.
RAMP TIME SETTLING
TIME
DAC RAMP
R
S
VOLTAGE
13016-047
Figure 47. Programmable Ramp Time Representation
Fast Ramp Feature
To accelerate the initial settling of the closed loop, the fast ramp
feature can be enabled. When the ramp time register is programmed
to 0x0000, the ramp generator disables. In this mode, when the
current sense reading is less than 0x00F, the integrator time
constant is reduced to 408 µs, allowing the gate control voltage
to reach the PA threshold voltage as quickly as possible. When
above this current, the time constant automatically returns to its
programmed value. When a different switching threshold is
desired, use the current sense offset register to allow Code 0x00F to
represent a higher or lower current. This features may be useful to
prevent unwanted overshoot (lower threshold) or to speed up
settling (higher threshold).
Closed-Loop Sequencing
On power-up or following a reset, the system is configured as
follows:
• The four bipolar outputs (BI-VOUT0 to BI-VOUT3) are set to
their clamp value, regardless of the levels of the SLEEP0 or
the SLEEP1 pin.
• All of the DAC data registers are set to 0x0000, and the
bipolar DACs operate in open loop.
• The PA_ON signal is set to the off state.
To enter closed-loop operation, it is important to follow these steps:
1. Configure the AD7293 for closed-loop operating mode by
writing to the integrator limit and closed-loop control register
(Register 0x28) from the configuration page. Additionally,
if PMOS drain switch control is used, set the PA_ON signal
to the on state by writing to the PA_ON control register
(Register 0x29) from the same page.
2. The DACs must be programmed at this point. Choose the
target drain current such that the PA is within its operating
region. The ISENSE gain setting must be left at the default
value of 6.25 in closed-loop mode. At this point, setting the
corresponding ramp time to 0 may be required so that the
ramp generator disables, and the DAC jumps to the target
value quickly.
3. Release the DACs out of clamp by writing to the DAC
enable register (Register 0x04) and wait 5 ms for the PAs to
settle to the initial drain current. At this point, ensure that
the programmed ramp time is 0, such that the ramp generator
is disabled, and the DAC resolves to the target value.
4. Program the desired ramp times for each channel by writing
to the corresponding ramp time registers (Register 0x2A to
Register 0x2D) from the configuration page.
5. Program the target drain current by writing to the DAC
registers. In addition to the ramp time, allow a delay of
1 ms before checking whether the PA drain current
corresponds to the intended target current. During the
active ramp period, if the DAC input register (Page 0x00,
Register 0x30 to Register 0x37) is read back, it is seen as
ramping up or ramping down to the target code.
If the user writes a new target drain current while the ramp is
active, the device restarts the internal timer and aims to reach
the new drain current within the programmed ramp time.
If the device is configured in closed-loop mode, the ADC runs
conversions on the corresponding current sensor channel in the
background. In addition to the current sensor conversions,
additional channels can be configured to run background
conversions (via the corresponding background enable registers).
The user can read back the conversion results via the channel
specific result registers in Page 0x00 and Page 0x01.
Data Sheet AD7293
Rev. D | Page 29 of 79
Closed-Loop Integrator Programmable Voltage Limit
The AD7293 ADC can monitor the voltage at the output of the
integrator by writing to a register (Register 0x23) from the
configuration page (see Table 46).
The integrator voltage limit feature allows the user to set upper
and lower limits on the integrator output voltage in closed-loop
mode of operation. When the integrator limit is active, the
integrator pauses and the output voltage holds constant. The
polarity of the error amplifier (comparison between measured
current and target current) determines when it is safe to deactivate
the soft limit. For example, a lower target current is programmed,
which makes the integrator output decrease, making it safe to
deactivate the integrator limit.
It is recommended to use the hysteresis registers (see Table 66
and Table 69) to avoid the device switching in and out of the
alert condition close to the limits. Additionally, the integrator
limit feature can be made a function of the upper/lower limits
only by ignoring the polarity of the error amplifier (via D2 of
the general register (Register 0x14) from the configuration page).
The integrator limit feature does not enable by default and can
be enabled by writing to the integrator limit and closed-loop
control register (Register 0x28).
Closed-Loop Range Upper Voltage Limit
An analog circuit within the output integrator creates a
hardware range upper limit on the output voltage of either 0 V or
1 V, as shown in Tabl e 19. If the hardware limiting circuitry is
active, an alert appears on the INTLIMITx and AVSS/AVDD alert
register (Register 0x1A). See the INTLIMITx and AVSS/AVDD
Alert Register (Register 0x1A) section.
Table 19. Closed-Loop Range Upper Voltage Limit
Operation Bipolar DAC Range (V) Range Limit
Open Loop X = don’t care Off
Closed Loop 0 to +5 Off
Closed Loop
−4 to +1
On (1 V)
Closed Loop −5 to 0 On (0 V)
DIGITAL INPUT/OUTPUT REGISTERS
Eight pins can be set as GPIOs or can perform various digital
functions. Three registers located on the configuration page set
up the functionality of the GPIO interface. GPIO0 to GPIO3
default to the GPIOs on power-up. ALERT1, SLEEP0, SLEEP1,
and LDAC default to digital functions on power-up.
The GPIO register (Register 0x5) configures the GPIOs in the
device. In GPIO mode, and with the output drivers enabled, the
GPIO outputs reflect the value written to this register. In
functional mode, any write to this register has no effect on the
GPIO outputs. See the GPIO Register (Register 0x05) section.
The digital output enable register (Register 0x11) enables the
output drivers of the GPIO pins; therefore, when using one of
the pins as an output in GPIO mode or functional mode (for
alerts and busy), the corresponding bit must be set. See the
Digital Output Enable Register (Register 0x11) section.
The digital input/output function register (Register 0x12) allows the
user to put the relevant pin into GPIO mode or functional mode.
See the Digital Input/Output Function Register (Register 0x12)
section.
The digital functional polarity register (Register 0x13) sets the
polarity of the digital input/output pins in functional mode only.
The associated input/output signal can be made active low or
active high. See the Digital Functional Polarity Register
(Register 0x13) section.
LOAD DAC (LDAC PIN)
The AD7293 DACs have doubled buffered interfaces consisting
of two banks of registers: input registers and DAC registers. The
user can write to any combination of the input registers. If the
load bit is held high when writing to a DAC, updates to the
DAC register are controlled by the LDAC pin.
Instantaneous DAC Updating (Asynchronous)
In this operation mode, the SPI data is clocked into the DAC
input register on the rising edge of the SCLK. The output register is
updated, and the output begins to change. Instantaneous DAC
updating is only applicable when the load bit is not set when
writing to the DAC register. Hold the LDAC pin in its false state.
Deferred DAC Updating (Synchronous)
In this mode, the SPI data is clocked into the DAC input registers
on the rising edge of the SCLK. However, the update of the
output registers can be blocked during the SPI write by setting
the load bit. The output registers can be synchronously updated
(data is transferred from the DAC input register to the DAC
output register) by taking the LDAC pin to its true state.
ALERTS AND LIMITS
The high and low limit pages comprise registers that set the
high and low alerts for the analog input channels, the current
sensors, the internal supply monitoring channels, the internal
bipolar DAC monitoring channels, and the RSx+ monitoring
channels. Each register is 16 bits in length; values are 12-bit, left
justified (padded with 0s as the four LSBs). On power-up, the
low limit registers contain all zeros, whereas the high limit
registers contain 0xFFF0.
The alert high limit registers on Page 0x04 (High Limit 0) and
Page 0x05 (High Limit 1) store the upper limit that activates an
alert (see the High Limit 0 (Page 0x04) section and the High Limit
1 (Page 0x05) section). If the conversion result is greater than the
value in the alert high limit register, an alert triggers. The alert low
registers on Page 0x06 (Low Limit 0) and Page 0x07 (Low Limit 1)
store the low limit that activates an alert (see the Low Limit 0
(Page 0x06) section and the Low Limit 1 (Page 0x07) section). If
the conversion result is less than the value in the alert low limit
register, an alert triggers.
AD7293 Data Sheet
Rev. D | Page 30 of 79
1
PROV IDED THE GPI O7/ LDAC PIN I S CO NFI GURED AS AN LDAC PIN.
DAC CHANNEL
DAC OUTPUT
REGISTER
DAC INPUT
REGISTER DAC VOUTx
READ
WRITE
SCLK
SCLK
LOAD BIT
GPIO7/LDAC
PIN
1
LDAC
POLARITY
13016-048
Figure 48. Simplified Diagram of Input Loading Circuitry for a Single DAC
If a conversion result exceeds the high or low limit set in the
alert limits register, the AD7293 signals an alert in one or more
of the following ways:
• Via hardware using the GPIO3/ALERT0 and
GPIO4/ALERT1 pins
• Via software using the alert bits or registers on the alert
page (Page 0x10).
ALERTx Pins
Two pins can be configured as ALERTx pins. On power-up,
Pin 2 (GPIO4/ALERT1) is configured as an alert whereas
Pin 53 is configured as a GPIO (GPIO3/ALERT0). When these
pins are configured as ALERTx pins, any combination of high
and low alerts on any of the ADC channels can route to these
pins. The polarity of the alert output pins can be set to active
high or active low via the digital function polarity register on
the configuration page.
If an alert pin signals an alert event and the contents of the alert
flags registers are not read before the next conversion is completed,
the contents of the register may change if the out of range signal
returns to the specified range. In this case, the ALERT0 or
ALERT1 pin no longer signals the occurrence of an alert event.
Software Alerts Page
The alert summary register (Register 0x10) contains a summary of
alerts for the voltage, temperature sensor, current sensor, and
other monitoring inputs that have violated limits. See the Alert
Summary (ALERTSUM) Register (Register 0x10) section.
To gather more detailed information, the remaining registers
contain two individual status bits per channel: one corresponding
to the high limit and the other corresponding to the low limit.
A bit with a status of one shows the channel on which the
violation occurred and whether the violation occurred on the
high or low limit.
13016-148
D11
D10
D9
D8
D3
D2
D1
D0
D11
D10
D9
D8
D3
D2
D1
D0
D10
D9
D8
D2
D1
D0
D11
D10
D9
D8
D3
D2
D1
D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ALERT
FLAG
OR
D9
D8
D2
D1
D0
ALERT SUMMARY REGISTER
V
IN
ALERT
REGISTER
T
SENSE
ALERT
REGISTER
I
SENSE
ALERT
REGISTER
SUPPLY
AND
BI-V
OUT
x
MON
ALERT
REGISTER
RSx+
MON
ALERT
REGISTER
INT
LIMIT
AND
AV
SS
/AV
DD
ALERT
REGISTER
V
IN
3 HIG H ALERT
V
IN
2 HIG H ALERT
V
IN
1 HIG H ALERT
V
IN
0 HIG H ALERT
V
IN
3 LOW ALERT
V
IN
2 LOW ALERT
V
IN
1 LOW ALERT
V
IN
0 LOW ALERT
T
SENSE
D1 HIGH ALERT
T
SENSE
D0 HIGH ALERT
T
SENSE
INT HIGH ALE RT
T
SENSE
D1 LO W ALE RT
T
SENSE
D0 HIGH ALERT
T
SENSE
INT LOW ALERT
I
SENSE
3 HIG H ALERT
I
SENSE
2 HIG H ALERT
I
SENSE
1 HIG H ALERT
I
SENSE
0 HIG H ALERT
I
SENSE
3 LOW ALERT
I
SENSE
2 LOW ALERT
I
SENSE
1 LOW ALERT
I
SENSE
0 LOW ALERT
BI-V
OUT
3
MON
HIG H ALERT
BI-V
OUT
2
MON
HIG H ALERT
BI-V
OUT
1
MON
HIG H ALERT
BI-V
OUT
0
MON
HIG H ALERT
BI-V
OUT
3
MON
LOW ALERT
BI-V
OUT
2
MON
LOW ALERT
BI-V
OUT
1
MON
LOW ALERT
BI-V
OUT
0
MON
LOW ALERT
AV
SS
LOW ALERT
AV
DD
LOW ALERT
AV
SS
HIG H ALERT
DACV
DD-BI
HIG H ALERT
DACV
DD-UNI
HIG H ALERT
DACV
DD-BI
LOW ALERT
DACV
DD-UNI
LOW ALERT
RS3+
MON
HIG H ALERT
RS2+
MON
HIG H ALERT
RS1+
MON
HIG H ALERT
RS0+
MON
HIG H ALERT
RS3+
MON
LOW ALERT
RS2+
MON
LOW ALERT
RS1+
MON
LOW ALERT
RS0+
MON
LOW ALERT
INT
LIMIT
3 HIG H ALERT
INT
LIMIT
2 HIG H ALERT
INT
LIMIT
1 HIG H ALERT
INT
LIMIT
0 HIG H ALERT
AV
SS
/AV
DD
ALARM
AV
DD
HIG H ALERT
Figure 49. Software Alerts Page
Data Sheet AD7293
Rev. D | Page 31 of 79
GPIO0 to GPIO3 Routing to ALERT1
A bit in the general register allows the GPIO0 to GPIO3 status
to route to the ALERT1 pin. Set GPIO0 to GPIO3 up as inputs
(bit set to 0 in the digital output enable register). If the GPIO is
read as 1, this read appears on ALERT1, and the GPIO register
can be read for the status of the pin to detect which pin has
caused ALERT1 to become active.
AVDD AND AVSS ALARM
There are comparators on AVDD (+3.6 V typical) and AVSS
(−4.1 V typical) that can be routed to the ALERTx pins or can
be used to control the PA_ON state and to put the bipolar
DACs/integrator outputs in the clamp state. By default, these
alarms are enabled.
When AVSS is greater than −4.1 V, there is a mask register
available whereby an alert of AVSS or AVDD is not creating an
alert on the ALERTx pin.
MAXIMUM AND MINIMUM PAGES
The maximum and minimum pages contain storage registers
for the maximum and minimum conversion results. This
function is useful when monitoring the minimum and maxi-
mum conversion values over time is required.
HYSTERESIS
The hysteresis value determines the reset point for the ALERTx
pin and/or software alert bit if a violation of the limits occurs. The
hysteresis register stores the hysteresis value when using the
limit registers. Each pair of limit registers has a dedicated hysteresis
register (see Figure 50). If software is periodically polling the
device to detect an alert, the hysteresis can be useful to ensure
that no out of limit condition is missed.
HIGH LIMIT
LOW LIMIT
HIGH LIMIT – HYSTERESIS
LOW LIMIT + HYSTERESIS
TIME
INPUT SIG NAL
ALERT SIG NAL
13016-049
Figure 50. Hysteresis
AD7293 Data Sheet
Rev. D | Page 32 of 79
REGISTER SETTINGS
The register structure for the AD7293 is partitioned using pages.
There are 19 pages in total. Each contains a different number
of registers that are used to store and access information to
configure and control the device. Each page and subregister
have an address that an 8-bit address pointer register points
to when communicating with it. The address pointer register is
an 8-bit register. The six LSBs (D5 to D0) are the pointer
address bits that point to one of the AD7293 data registers, and
the MSB (D7) is the read (high)/write (low) bit. There are read
only and read/write registers.
ADDRESS
POINTER
REGISTER
PAGE 0x00
RESUL T 0/ DAC INPUT
PAGE 0x01
RESUL T 1
PAGE 0x02
CONFIGURATION
PAGE 0x03
SEQUENCE
PAGE 0x04
HIGH LIMIT 0
PAGE 0x05
HIGH LIMIT 1
PAGE 0x06
LOW LIMIT 0
PAGE 0x07
LOW LIMIT 1
PAGE 0x08
HYSTERESIS 0
PAGE 0x09
HYSTERESIS 1
PAGE 0x0A
MINIMUM 0
PAGE 0x0B
MINIMUM 1
PAGE 0x0C
MAXIMUM 0
PAGE 0x0D
MAXIMUM 1
PAGE 0x0E
OFFSET 0
PAGE 0x0F
OFFSET 1
PAGE 0x10
ALERT
PAGE 0x11
ALE RT0 PI N
PAGE 0x12
ALE RT1 PI N
SERI AL BUS INT E RFACE
DIN
SCLK
DOUT
CS
DATA
NOTES
1. EACH P AGE CONT AINS 7 CO MMMON REGI S TERS IN ADDI TI ON TO PAGE S P E CIFIC REGI S TERS.
2. THE CO NFI GURAT ION P AGE CONT AINS T HE RE GI S TERS THAT S E LECT T HE BACKGROUND M ODE
CYCL E OF CHANNE LS TO BE CO NV E RTED BY THE ADC. T HE S E QUENCE P AGE AP P LIE S TO COMM AND M ODE O NLY.
NO OP
PAGE SELECT POI NTER
CONVE RSIO N COMM AND
RESULT
DAC ENABLE
GPIO
DEVICE I D
...
...
...
...
...
...
...
...
NO OP
PAGE SELECT POI NTER
CONVE RSIO N COMM AND
RESULT
DAC ENABLE
GPIO
DEVICE I D
...
...
...
...
...
...
...
...
13016-050
Figure 51. Register Structure
Data Sheet AD7293
Rev. D | Page 33 of 79
REGISTERS COMMON TO ALL PAGES
A number of registers is common to all pages. The register
function is the same for all pages.
No Op Register (Register 0x00)
The no op register does not physically exist and this address
space is reserved to prevent any writes to the device when the
input data line is held low.
Page Select Pointer Register (Register 0x01)
This 8-bit pointer register selects the page that the user is trying
to access. A read of this register indicates the page the user is
currently pointing to. The two MSBs are reserved and the six
LSBs can be written to select any of the pages.
Conversion Command (Register 0x02)
The conversion command register is a special 8-bit register used
to initiate a conversion. To command a conversion, write the
command register address to the device with the MSB read bit
set. When the device address pointer register receives a special
conversion command, the previous contents of the address pointer
are retained and used to determine which channel to convert. If
pointing to the sequence register, the next channel in the sequence
converts.
Result Register (Register 0x03)
The 16-bit, read only ADC data register provides read access to
the most recent ADC conversion result in command mode.
Otherwise, it is necessary for the application software to keep
track of what channel was converted.
DAC Enable Register (Register 0x04)
This 8-bit register enables the DACs. See Table 20.
GPIO Register (Register 0x05)
This 8-bit register configures the GPIOs in the device. In GPIO
mode, and with the output drivers enabled, the GPIO outputs
reflect the value written to this register. In functional mode, any
write to this register has no effect on the GPIO outputs. The status
(high/low) of the GPIO pins can be read back by reading this
register (both in functional and GPIO modes). See Table 21.
Device ID Register (Register 0x0C)
This 16-bit read-only register stores the Device ID assigned to
Analog Devices, Inc. See Table 22 for more information.
Software Reset Register (Register 0x0F)
To issue a software reset write a specific value, 0x7293, to this
16-bit register and pull CS high. The user must write 0x0000 to
this register to clear it following the software reset. See Tabl e 23.
Table 20. DAC Enable Register
Bit Number(s) Bit Name Description
D7 BI-VOUT3 0: disable.
1: enable.
D6 BI-VOUT2 0: disable.
1: enable.
D5 BI-VOUT1 0: disable.
1: enable.
D4 BI-VOUT0 0: disable.
1: enable.
D3 UNI-VOUT3 0: disable.
1: enable.
D2
UNI-V
OUT
2
0: disable.
1: enable.
D1 UNI-VOUT1 0: disable.
1: enable.
D0 UNI-VOUT0 0: disable.
1: enable.
Table 21. GPIO Register
Bit Number(s) Bit Name Description
D7 GPIO7 0: disable.
1: enable.
D6
GPIO6
0: disable.
1: enable.
D5 GPIO5 0: disable.
1: enable.
D4 GPIO4 0: disable.
1: enable.
D3 GPIO3 0: disable.
1: enable.
D2 GPIO2 0: disable.
1: enable.
D1
GPIO1
0: disable.
1: enable.
D0 GPIO0 0: disable.
1: enable.
Table 22. Device ID Register
Bit Number(s)
Bit Name
Description
[15:0] ID register Analog Devices,
Device ID = 0x0018
Table 23. Software Reset Register
Bit Number(s)
Bit Name
Description
[15:0]
Reset register
Software reset =
0x7293
AD7293 Data Sheet
Rev. D | Page 34 of 79
RESULT 0/DAC INPUT (PAGE 0x00)
Result 0/DAC input is located at Page 0x00. It contains result
registers for the ADC, the temperature sensor, and the current
sensor channel. The page also contains DAC input registers to
set the output voltage.
Table 24. Result 0/DAC Input (Page 0x0)
Address
(Hex)
Name
Byte
1
Access
Type
1
Default
Value
1
0x00 No op N/A N/A 0x00
0x01
Page select pointer
1
R/W
0x00
0x02 Conversion command2 1 W N/A
0x03 Result 2 R 0x0000
0x04 DAC enable 1 R/W 0x00
0x05 GPIO 1 R/W 0x00
0x0C Device ID 2 R 0x0018
0x0F Software reset 2 R/W 0x0000
0x10 VIN0 2 R 0x0000
0x11 VIN1 2 R 0x0000
0x12 VIN2 2 R 0x0000
0x13 VIN3 2 R 0x0000
0x20
T
SENSE
INT
2
R
0x0000
0x21 TSENSED0 2 R 0x0000
0x22 TSENSED1 2 R 0x0000
0x28 ISENSE0 2 R 0x0000
0x29 ISENSE1 2 R 0x0000
0x2A ISENSE2 2 R 0x0000
0x2B
I
SENSE
3
2
R
0x0000
0x30 UNI-VOUT0 2 R/W 0x0000
0x31 UNI-VOUT1 2 R/W 0x0000
0x32 UNI-VOUT2 2 R/W 0x0000
0x33 UNI-VOUT3 2 R/W 0x0000
0x34 BI-VOUT0 2 R/W 0x0000
0x35 BI-VOUT1 2 R/W 0x0000
0x36 BI-VOUT2 2 R/W 0x0000
0x37 BI-VOUT3 2 R/W 0x0000
1 N/A means not applicable.
2 Not a physical register.
Voltage Input (VINx) Result Registers (Register 0x10 to
Register 0x13)
These registers store the 12-bit ADC results from the four input
channels.
In single-ended mode, the LSB size is REFADC/4096 when the
0 V to REFADC range is selected, 2 × REFADC/4096 when the 0 V
to 2 × REFADC range is selected, and 4 × REFADC/4096 when the
0 V to 4 × REFADC range is selected (which is the default value).
REFADC = 1.25 V. See the ADC Transfer Functions section for
more information. See Table 25 for more information.
Temperature Sensor (TSENSEINT and TSENSEDx) Result
Registers (Register 0x20 to Register 0x22)
These registers store the 12-bit ADC results from the three
temperature sensor channels. 1 LSB = 0.125°C. See Table 26 for
more information.
Current Sensor (ISENSEx) Result Registers (Register 0x28 to
Register 0x2B)
These registers store the 12-bit ADC results from the four
current sensor channels. See Table 25 for more information.
DAC Input (UNI-VOUTx and BI-VOUTx) Registers
(Register 0x30 to Register 0x37)
Writing to these register addresses sets the 12-bit DAC output
voltage codes, as shown in Table 27.
If the load bit is set to 1, the device waits for the DAC load pin
(GPIO7/LDAC) before loading the voltage codes onto the
DACs rather than immediately after the write operation. If the
copy bit is set to 1, writing to any of the four DAC registers
(unipolar and bipolar are grouped separately) sets all the other
DAC registers to the same value.
While reading back the DAC result registers, only the 12-bit
internal DAC output register value is visible to the user.
Bits[D3:D0] read 0 irrespective of the status of the copy and
load bits.
Table 25. Voltage Input (Register 0x10 to Register 0x13) and Current Sensor (Register 0x28 to Register 0x2B) Result Registers
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 [D3:D0]
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Reserved
Data Sheet AD7293
Rev. D | Page 35 of 79
Table 26. Temperature Sensor Result Register
Bit Number(s) Bit Name Description
D15 B11 0: −256°C
1: 0°C
D14 B10 0: 0°C
1: 128°C
D13 B9 0: 0°C
1: 64°C
D12 B8 0: 0°C
1: 32°C
D11 B7 0: 0°C
1: 16°C
D10 B6 0: 0°C
1: 8°C
D9 B5 0: 0°C
1: 4°C
D8 B4 0: 0°C
1: 2°C
D7 B3 0: 0°C
1: 1°C
D6 B2 0: 0°C
1: 0.5°C
D5 B1 0: 0°C
1: 0.25°C
D4 B0 0: 0°C
1: 0.125°C
[D3:D0] Reserved Reserved
Table 27. DAC Input Register
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 [D3:D2] D1 D0
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Reserved Copy Load
Table 28. Copy and Load Bit Descriptions
Bit Number(s)
Bit Name
Description
[D15:D4] B11 to B0 Data bits
D1 Copy 0: no action
1: copies data to all DAC registers
D0
Load
0: all channels updated with latest results
1: input register loaded but output voltage dependent on LDAC
AD7293 Data Sheet
Rev. D | Page 36 of 79
RESULT 1 (PAGE 0x01)
Table 29. Result 1 (Page 0x01)
Address
(Hex) Name Byte1
Access
Type1
Default
Value1
0x00 No op N/A N/A 0x00
0x01 Page select pointer 1 R/W 0x00
0x02 Conversion command2 1 W N/A
0x03 Result 2 R 0x0000
0x04
DAC enable
1
R/W
0x00
0x05 GPIO 1 R/W 0x00
0x0C Device ID 2 R 0x0018
0x0F Software reset 2 R/W 0x0000
0x10 AVDD 2 R 0x0000
0x11 DACVDD-UNI 2 R 0x0000
0x12 DACVDD-BI 2 R 0x0000
0x13 AVSS 2 R 0x0000
0x14 BI-VOUT0MON 2 R 0x0000
0x15 BI-VOUT1MON 2 R 0x0000
0x16 BI-VOUT2MON 2 R 0x0000
0x17 BI-VOUT3MON 2 R 0x0000
0x28 RS0+MON 2 R 0x0000
0x29 RS1+MON 2 R 0x0000
0x2A RS2+MON 2 R 0x0000
0x2B RS3+MON 2 R 0x0000
1 N/A means not applicable.
2 Not a physical register.
Voltage Supply Monitor Result Registers (Register 0x10
to Register 0x13)
The ADC is used in its single-ended mode. The LSB size varies
with the different supply monitoring registers. AVDD and
DACVDD-BI are divided by 5, and DACVDD-UNI is divided by 20 to
scale within the 0 V to REFADC range. AVSS is level shifted to within
a −7.5 V to +2.5 V range, where 0x0000 equates to approximately
−7.5 V and 0xFFF0 equates to approximately +2.5 V. R E F ADC =
1.25 V.
Bipolar DAC Internal Monitor Result (BI-VOUT0MON to
BI-VOUT3MON) Registers (Register 0x14 to Register 0x17)
These registers store the 12-bit ADC results from the four internal
inputs for monitoring the bipolar DAC outputs in open-loop
mode or the integrator outputs in closed-loop mode. The DAC
monitoring channel voltages between −5 V and +5 V are level
shifted to the 0 V to REFADC range before conversions.
RSx+MON Result Registers (Register 0x28 to Register 0x2B)
The voltages on the RSx+ pins (RSx+MON) are divided by 50 to
scale them to the 0 V to REFADC range. Use the ADC in single-
ended mode. The RSx+MON monitor result registers store the
12-bit ADC results for the current sense supply channels.
Table 30. Monitor Register Configuration
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 [D3:D0]
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Reserved
Data Sheet AD7293
Rev. D | Page 37 of 79
CONFIGURATION (PAGE 0x02)
This page contains the registers that configure the device
operation.
Table 31. Configuration (Page 0x2)
Address
(Hex) Name Byte1
Access
Type1
Default
Value1
0x00 No op N/A N/A 0x00
0x01 Page select pointer 1 R/W 0x00
0x02 Conversion command2 1 W N/A
0x03 Result 2 R 0x0000
0x04 DAC enable 1 R/W 0x00
0x05 GPIO 1 R/W 0x00
0x0C Device ID 2 R 0x0018
0x0F Software reset 2 R/W 0x0000
0x11 Digital output enable 2 R/W 0x0010
0x12
Digital input/output
function
2
R/W
0x000F
0x13 Digital functional
polarity
2 R/W 0x0090
0x14 General 2 R/W 0x0000
0x15 VINx Range 0 2 R/W 0x0000
0x16 VINx Range 1 2 R/W 0x0000
0x17 VINx differential/
single-ended enable
2 R/W 0x0000
0x18 VINx filter 2 R/W 0x0000
0x19 VINx background enable 2 R/W 0x0000
0x1A Conversion delay 2 R/W 0x0000
0x1B TSENSEx background
enable
2 R/W 0x0000
0x1C ISENSEx background
enable
2 R/W 0x0000
0x1D ISENSEx gain 2 R/W 0x0000
0x1F DAC snooze/SLEEP0
pin
2 R/W 0xFF00
0x20 DAC snooze/SLEEP1
pin
2 R/W 0xFF00
0x23 RSx+MON, supply
monitor, BI-VOUTx
background enable
2 R/W 0x0000
0x28 Integrator limit and
closed-loop control
2 R/W 0x0000
0x29 PA_ON control 2 R/W 0x0130
0x2A Ramp Time 0 2 R/W 0x0000
0x2B Ramp Time 1 2 R/W 0x0000
0x2C Ramp Time 2 2 R/W 0x0000
0x2D Ramp Time 3 2 R/W 0x0000
0x2E
Closed-loop fast ramp
and integrator time
constant
2
R/W
0xBBBB
0x2F INTLIMITx and AVSS/
AVDD alarm mask
2 R/W 0x0000
1 N/A means not applicable.
2 Not a physical register.
Digital Output Enable Register (Register 0x11)
This 16-bit register enables the output drivers of the GPIO pins
by setting the corresponding bit to one. When using one of the
pins as an output in GPIO mode or functional mode (for alerts
or busy), the corresponding bit must be set.
Digital Input/Output Function Register (Register 0x12)
All GPIOs are in either functional mode (power-up) or GPIO
mode. The relevant GPIO pin is in GPIO mode when the
corresponding bit in this register is set to 1. The relevant GPIO
pin is in functional mode when the corresponding bit in this
register is cleared to 0. Four pins are in functional mode and
four pins are in GPIO mode after a power-on reset.
Digital Functional Polarity Register (Register 0x13)
This register sets the polarity of the digital input/output pins in
functional mode only. The associated input/output signal can be
made active low by setting the corresponding bit in this register
to 1. Functional mode is set up in the digital input/output
function register (Register 0x12).
General Register (Register 0x14)
This 16-bit register selects the internal ADC reference or an
external reference and other general functions. The status on
GPIO0 to GPIO3 can be routed to ALERT1. Error amplifier
control over the integrator limit feature is also configurable in
this register. ALERT0 can be routed internally to clamp the
bipolar DACs.
VINx Range x Registers (Register 0x15 and Register 0x16)
These two 16-bit registers combine together to specify the input
range of the VINx channels. The default range is 4 × REFADC. If
either of the corresponding range bits from the two range
registers is set to one, the analog input voltage range is set to
2 × REFADC. If both the bits are set to one, the analog input
voltage range is REFADC. See Table 36 and Table 37 for range
selection. REFADC = 1.25 V.
VINx Differential/Single-Ended Enable Register
(Register 0x17)
This register runs the ADC conversions for the voltage input
channels in differential and pseudo differential mode. The
corresponding differential pairs for the channels are as follows:
VIN0 to VIN1 for Channel 0, VIN1 to VIN0 for Channel 1, VIN2 to
VIN3 for Channel 2, and VIN3 to VIN2 for Channel 3. The
differential mode bits are ignored when the device is in pseudo
differential mode.
VINx Filter Register (Register 0x18)
A digital filter can be applied to the conversion result of all four
VINx channels. Set the corresponding filter bit to 1 to apply the
digital filter.
VINx Background Enable Register (Register 0x19)
Set the corresponding enable bit to 1 to convert the VINx channels
in the background.
AD7293 Data Sheet
Rev. D | Page 38 of 79
Conversion Delay Register (Register 0x1A)
This register can add a conversion delay (during the acquisition
phase) to the VINx channels in command mode conversions.
The resolution of this register is 320 ns. That is, each bit adds
320 ns to the conversion delay.
Temperature Sensor (TSENSEx) Background Enable
Register (Register 0x1B)
To enable the temperature sensor conversions, write to the
corresponding bit from this register. To enable digital filtering,
also write to the corresponding bit.
Current Sensor (ISENSEx) Background Enable Register
(Register 0x1C)
To enable the ISENSEx conversions, write to the corresponding bit
from this register. To enable digital filtering, also write to the
corresponding bit.
Current Sensor (ISENSEx) Gain Register (Register 0x1D)
The ISENSEx gain register is a 16-bit register that controls the gain
settings for the four current sense channels.
DAC Snooze/SLEEP0 Pin Register (Register 0x1F)
To clamp the relevant DAC output via the GPIO5/SLEEP0 pin
set the corresponding bit in this register to 1. The snooze bits
determine the power-up/power-down condition of the DACs
after removing the clamp signal. If any of the snooze bits are set
to 1, an additional write to the DAC enable register is required
to wake up the corresponding DAC. If the snooze bits are not
set, directly use the SLEEP0 pin to wake up the DAC.
DAC Snooze/SLEEP1 Pin Register (Register 0x20)
To clamp the relevant DAC output via the GPIO6/SLEEP1 pin,
set the corresponding bit in this register to 1.
RSx+MON, Supply Monitor, BI-VOUTx Background Enable
Register (Register 0x23)
The RSx+MON and voltage supply channels can convert in the
background by setting the corresponding enable bit to 1.
Integrator Limit and Closed-Loop Control Register
(Register 0x28)
This register configures the device in closed-loop mode and
controls the integrator limit function as described in the
Closed-Loop Integrator Programmable Voltage Limit section.
PA_ON Control Register (Register 0x29)
This register controls the PA_ON pin and allows AVss/AVDD
alarm control over the PA_ON pin. Note that the AVSS/AVDD
alarm must be cleared before the PA_ON pin can switch back to
the on state.
This register also allows clamp pin control over the PA_ON pin.
Setting the clamp bit to 1 allows control of the PA_ON pin via
the SLEEP0 and SLEEP1 pins, where, if the pin goes high, the
PA_ON pin goes to the off state. If the snooze bit is set to 1, an
additional write to this register is required to set the PA_ON pin
to the on state after clearing the corresponding SLEEP0 and
SLEEP1 pins.
Ramp Time 0 to Ramp Time 3 Registers (Register 0x2A to
Register 0x2D)
These 16-bit registers (Ramp Time 0 to Ramp Time 3) configure
the ramp time for the closed-loop channels. The resolution of
each bit is 250 µs and the maximum programmable ramp time
is 31.75 ms.
The minimum programmable ramp time for each channel is
4 ms. Enter 0x0000 to disable the ramp circuitry and to have the
DAC resolve the target value immediately.
Closed-Loop Fast Ramp and Integrator Time Constant
Register (Register 0x2E)
Use this register to disable or to enable the fast ramp scheme for
the closed-loop channels when they release from clamp. The
integrator time constant can trim to the values shown in Table 50.
Integrator Limit Active Status (INTLIMITx) and AVSS/AVDD
Alarm Mask Register (Register 0x2F)
Use this 16-bit register to mask any of the closed-loop integrator
limit active status values or the AVss/AVDD alarm. When masked,
the status values are not visible when reading back the correspond-
ing alert registers, or if the status values are routed to any of the
ALERTx pins.
Table 32. Digital Output Enable Register (Register 0x11)
Bit Number(s) Bit Name Description
[D15:D8] Reserved Reserved
D7 GPIO7/LDAC (Pin 6) 1: enable output drivers. 0: disable output drivers.
D6 GPIO6/SLEEP1 (Pin 4) 1: enable output drivers. 0: disable output drivers.
D5
GPIO5/SLEEP0 (Pin 3)
1: enable output drivers. 0: disable output drivers.
D4 GPIO4/ALERT1 (Pin 2) 1: enable output drivers (default). 0: disable output drivers.
D3
GPIO3/ALERT0 (Pin 53)
1: enable output drivers. 0: disable output drivers.
D2 GPIO2/BUSY (Pin 54) 1: enable output drivers. 0: disable output drivers.
D1 GPIO1/CONVST (Pin 55) 1: enable output drivers. 0: disable output drivers.
D0 GPIO0/IS BLANK (Pin 56) 1: enable output drivers. 0: disable output drivers.
Data Sheet AD7293
Rev. D | Page 39 of 79
Table 33. Digital Input/Output Function Register (Register 0x12)
Bit Number(s)
Bit Name
Description
[D15:D8] Reserved Reserved
D7
Pin 6
0: LDAC (default)
1: GPIO7
D6 Pin 4 0: SLEEP1 (default)
1: GPIO6
D5 Pin 3 0: SLEEP0 (default)
1: GPIO5
D4 Pin 2 0: ALERT1 (default)
1: GPIO4
D3 Pin 53 0: ALERT0
1: GPIO3 (default)
D2 Pin 54 0: BUSY
1: GPIO2 (default)
D1 Pin 55 0: CONVST
1: GPIO1 (default)
D0
Pin 56
0: IS BLANK
1: GPIO0 (default)
Table 34. Digital Functional Polarity Register (Register 0x13)
Bit Number(s)
Bit Name
Description
[D15:D8] Reserved Reserved
D7 LDAC 0: LDAC is active high
1: LDAC is active low (default)
D6
SLEEP1
0: SLEEP1 is active high (default)
1: SLEEP1 is active low
D5 SLEEP0 0: SLEEP0 is active high (default)
1: SLEEP0 is active low
D4 ALERT1 0: ALERT1 is active high
1: ALERT1 is active low (default)
D3 ALERT0 0: ALERT0 is active high (default)
1: ALERT0 is active low
D2 BUSY 0: BUSY is active high (default)
1: BUSY is active low
D1 CONVST 0: CONVST is active high (default)
1: CONVST is active low
D0 IS BLANK 0: IS BLANK is active high (default)
1: IS BLANK is active low
Table 35. General Register (Register 0x14)
Bit Number(s)
Bit Name
Description
[D15:D8] Reserved Reserved
D7 ADC_REF 0: external reference (default)
1: internal reference
D6 GPIO ALERT1 routing 0: feature disabled (default)
1: GPIO0 to GPIO3 status routed to ALERT1 if configured as general-purpose input
[D5:D4]
MISO speed
00: maximum (default)
01: fast
10: slow
11: minimum
AD7293 Data Sheet
Rev. D | Page 40 of 79
Bit Number(s)
Bit Name
Description
D3 TSENSE diode check 0: external check on (default)
1: external check off
D2 Limit control 0: alert control over software limit feature (default)
1: alert and error amplifier control over software limit feature
D1 ALERT0 clamp 0: no control (default)
1: ALERT0 routed internally to clamp bipolar DACs
D0 Reserved Reserved
Table 36. Voltage Input (VINx) Range 0 Voltage Input Range Register (Register 0x15)
Bit Number(s)
Bit Name
Description1, 2
[D15:D4] Reserved Reserved
D3 VIN3 Range 0 Used in conjunction with VIN3 Range 1 bit (see Table 37) to specify the input range of VIN3
D2 VIN2 Range 0 Used in conjunction with VIN2 Range 1 bit (see Table 37) to specify the input range of VIN2
D1 VIN1 Range 0 Used in conjunction with VIN1 Range 1 bit (see Table 37) to specify the input range of VIN1
D0 VIN0 Range 0 Used in conjunction with VIN0 Range 1 bit (see Table 37) to specify the input range of VIN0
1 REFADC = 1.25 V.
2 See Table 38 for bit descriptions.
Table 37. VINx Range 1 Voltage Input Range Register (Register 0x16)
Bit Number(s)
Bit Name
Description1, 2
[D15:D4] Reserved Reserved
D3
V
IN
3 Range 1
Used in conjunction with V
IN
3 Range 0 bit (see Table 36) to specify the input range of V
IN
3
D2 VIN2 Range 1 Used in conjunction with VIN2 Range 0 bit (see Table 36) to specify the input range of VIN2
D1 VIN1 Range 1 Used in conjunction with VIN1 Range 0 bit (see Table 36) to specify the input range of VIN1
D0
V
IN
0 Range 1
Used in conjunction with V
IN
0 Range 0 bit (see Table 36) to specify the input range of V
IN
0
1 REFADC = 1.25 V.
2 See Table 38 for bit descriptions.
Table 38. VINx Range 1 and VIN Range 0 Bit Descriptions
VIN Range 0, VINx1 Range Bit
VIN Range 1, VINx1 Range Bit
VINx1 Input Range Bit
0 0 4 × REFADC (default)
0 1 2 × REFADC
1 0 2 × REFADC
1 1 REFADC
1 x = 3, 2, 1, or 0.
Table 39. VINx Differential/Single-Ended Enable Register (Register 0x17)
Bit Number(s)
Bit Name
Description
[D15:D10] Reserved Reserved
D9
V
IN
2_V
IN
3_PDIFF
V
IN
2 and V
IN
3 pseudo differential mode
0: disable (default)
1: enable
D8
V
IN
0_V
IN
1_PDIFF
V
IN
0 and V
IN
1 pseudo differential mode
0: disable (default)
1: enable
[D7:D2]
Reserved
Reserved
D1 VIN2_VIN3_DIFF VIN2 and VIN3 differential mode
0: disable (default)
1: enable
D0 VIN0_VIN1_DIFF VIN0 and VIN1 differential mode
0: disable (default)
1: enable
Data Sheet AD7293
Rev. D | Page 41 of 79
Table 40. VINx Filter Register (Register 0x18)
Bit Number(s)
Bit Name
Description
[D15:D4] Reserved Reserved
D3
V
IN
3 filter
0: disable (default)
1: enable
D2 VIN2 filter 0: disable (default)
1: enable
D1 VIN1 filter 0: disable (default)
1: enable
D0 VIN0 filter 0: disable (default)
1: enable
Table 41. VINx Background Enable Register (Register 0x19)
Bit Number(s)
Bit Name
Description
[D15:D4] Reserved Reserved
D3 VIN3_BG_EN 0: disable background conversions (default)
1: enable background conversions
D2 VIN2_BG_EN 0: disable background conversions (default)
1: enable background conversions
D1 VIN1_BG_EN 0: disable background conversions (default)
1: enable background conversions
D0 VIN0_BG_EN 0: disable background conversions (default)
1: enable background conversions
Table 42. Temperature Sensor (TSENSEx) Background Enable Register (Register 0x1B)
Bit Number(s)
Bit Name
Description
[D15:D11] Reserved Reserved
D10 TSENSED1 filter 0: disable digital filtering (default)
1: enable digital filtering
D9 TSENSED0 filter 0: disable digital filtering (default)
1: enable digital filtering
D8
T
SENSE
INT filter
0: disable digital filtering (default)
1: enable digital filtering
[D7:D3] Reserved Reserved
D2 TSENSED1_EN 0: disable background conversions (default)
1: enable background conversions
D1 TSENSED0_EN 0: disable background conversions (default)
1: enable background conversions
D0 TSENSEINT_EN 0: disable background conversions (default)
1: enable background conversions
Table 43. Current Sensor (ISENSEx) Background Enable Register (Register 0x1C)
Bit Number(s)
Bit Name
Description
[D15:D12] Reserved Reserved
D11 ISENSE3 filter 0: disable digital filtering (default)
1: enable digital filtering
D10 ISENSE2 filter 0: disable digital filtering (default)
1: enable digital filtering
D9 ISENSE1 filter 0: disable digital filtering (default)
1: enable digital filtering
D8
I
SENSE
0 filter
0: disable digital filtering (default)
1: enable digital filtering
AD7293 Data Sheet
Rev. D | Page 42 of 79
Bit Number(s)
Bit Name
Description
[D7:D4] Reserved Reserved
D3 ISENSE3_EN 0: disable background conversions (default)
1: enable background conversions
D2 ISENSE2_EN 0: disable background conversions (default)
1: enable background conversions
D1 ISENSE1_EN 0: disable background conversions (default)
1: enable background conversions
D0 ISENSE0_EN 0: disable background conversions (default)
1: enable background conversions
Table 44. ISENSEx Gain Register (Register 0x1D)
Bit Number(s)
Bit Name
Description
[D15:D12], [D11:D8],
[D7:D4], [D3:D0]
ISENSE3 gain, ISENSE2 gain,
ISENSE1 gain, ISENSE0 gain
These bits control the gain settings for the four current sense channels.
Code Gain Value Voltage Across RSENSE (mV)
0000 (default) 6.25 ±200
0001 12.5 ±100
0010 18.75 ±66.67
0011
25
±50
0100 37.5 ±33.33
0101 50 ±25
0110 75 ±16.67
0111 100 ±12.5
1000 200 ±6.25
1001
400
±3.125
1010 781.25 ±1.6
Others 6.25 ±200
Table 45. DAC Snooze/SLEEP0 Pin Register (Register 0x1F) and DAC Snooze/SLEEP1 Pin Register (Register 0x20)
Bit Number(s) Bit Name Description
D15 BI-VOUT3 0: no control
snooze 1: snooze enabled when clamped by the SLEEP0 pin (Register 0x1F) or by the SLEEP1 pin (Register 0x20) (default)
D14 BI-VOUT2 0: no control
snooze 1: snooze enabled when clamped by the SLEEP0 pin (Register 0x1F) or by the SLEEP1 pin (Register 0x20) (default)
D13 BI-VOUT1 0: no control
snooze 1: snooze enabled when clamped by the SLEEP0 pin (Register 0x1F) or by the SLEEP1 pin (Register 0x20) (default)
D12 BI-VOUT0 0: no control
snooze 1: snooze enabled when clamped by the SLEEP0 pin (Register 0x1F) or by the SLEEP1 pin (Register 0x20) (default)
D11
UNI-V
OUT
3
0: no control
snooze 1: snooze enabled when clamped by the SLEEP0 pin (Register 0x1F) or by SLEEP1 pin (Register 0x20) (default)
D10 UNI-VOUT2 0: no control
snooze 1: snooze enabled when clamped by the SLEEP0 pin (Register 0x1F) or by the SLEEP1 pin (Register 0x20) (default)
D9 UNI-VOUT1 0: no control
snooze 1: snooze enabled when clamped by the SLEEP0 pin (Register 0x1F) or by the SLEEP1 pin (Register 0x20) (default)
D8 UNI-VOUT0 0: no control
snooze 1: snooze enabled when clamped by the SLEEP0 pin (Register 0x1F) or by the SLEEP1 pin (Register 0x20) (default)
D7 BI-VOUT3 0: no control (default)
sleep 1: can be clamped by the SLEEP0 pin (Register 0x1F) or clamped by the SLEEP1 pin (Register 0x20)
D6 BI-VOUT2 0: no control (default)
sleep 1: can be clamped by the SLEEP0 pin (Register 0x1F) or clamped by the SLEEP1 pin (Register 0x20)
D5
BI-V
OUT
1
0: no control (default)
sleep
1: can be clamped by the SLEEP0 pin (Register 0x1F) or clamped by the SLEEP1 pin (Register 0x20)
Data Sheet AD7293
Rev. D | Page 43 of 79
Bit Number(s) Bit Name Description
D4 BI-VOUT0 0: no control (default)
sleep 1: can be clamped by the SLEEP0 pin (Register 0x1F) or clamped by the SLEEP1 pin (Register 0x20)
D3 UNI-VOUT3 0: no control (default)
sleep
1: can be clamped by the SLEEP0 pin (Register 0x1F) or clamped by the SLEEP1 pin (Register 0x20)
D2 UNI-VOUT2 0: no control (default)
sleep 1: can be clamped by the SLEEP0 pin (Register 0x1F) or clamped by the SLEEP1 pin (Register 0x20)
D1 UNI-VOUT1 0: no control (default)
sleep 1: can be clamped by the SLEEP0 pin (Register 0x1F) or clamped by the SLEEP1 pin (Register 0x20)
D0 UNI-VOUT0 0: no control (default)
sleep 1: can be clamped by the SLEEP0 pin (Register 0x1F) or clamped by the SLEEP1 pin (Register 0x20)
Table 46. RSx+MON, Supply Monitor, BI-VOUTx Background Enable Register (Register 0x23)
Bit Number(s) Bit Name Description
[D15:D12] Reserved Reserved
D11 RS3+MON 0: disable background conversions (default)
1: enable background conversions
D10 RS2+MON 0: disable background conversions (default)
1: enable background conversions
D9
RS1+
MON
0: disable background conversions (default)
1: enable background conversions
D8 RS0+MON 0: disable background conversions (default)
1: enable background conversions
D7 BI-VOUT3MON 0: disable background conversions (default)
1: enable background conversions
D6 BI-VOUT2MON 0: disable background conversions (default)
1: enable background conversions
D5 BI-VOUT1MON 0: disable background conversions (default)
1: enable background conversions
D4 BI-VOUT0MON 0: disable background conversions (default)
1: enable background conversions
D3 AVSS 0: disable background conversions (default)
1: enable background conversions
D2
DACV
DD-BI
0: disable background conversions (default)
1: enable background conversions
D1 DACVDD-UNI 0: disable background conversions (default)
1: enable background conversions
D0 AVDD 0: disable background conversions (default)
1: enable background conversions
Table 47. Integrator Limit and Closed-Loop (CL) Control Register (Register 0x28)
Bit Number(s) Bit Name Description
[D15:D12] Reserved Reserved
D11 INT_CL_LIMIT_CH3 0: no control (default)
1: the soft closed-loop limit for the channel is enabled
D10 INT_CL_LIMIT_CH2 0: no control (default)
1: the soft closed-loop limit for the channel is enabled
D9 INT_CL_LIMIT_CH1 0: no control (default)
1: the soft closed-loop limit for the channel is enabled
D8 INT_CL_LIMIT_CH0 0: no control (default)
1: the soft closed-loop limit for the channel is enabled
[D7:D4] Reserved Reserved
AD7293 Data Sheet
Rev. D | Page 44 of 79
Bit Number(s) Bit Name Description
D3 Closed-Loop 3 0: closed loop is disabled (default)
1: closed loop is enabled
D2 Closed-Loop 2 0: closed loop is disabled (default)
1: closed loop is enabled
D1 Closed-Loop 1 0: closed loop is disabled (default)
1: closed loop is enabled
D0 Closed-Loop 0 0: closed loop is disabled (default)
1: closed loop is enabled
Table 48. PA_ON Control Register (Register 0x29)
Bit Number(s) Bit Name Description
[D15:D10] Reserved Reserved
D9 PA_ON enable 0: PA_ON signal is in the off state (default)
1: PA_ON signal is in the on state
D8 PA_ON trigger 0: no control
1: AVSS/AVDD alarm or ALERT0 triggers PA_ON (default)
[D7:D6] Reserved Reserved
D5 SLEEP1 snooze 0: no control
1: PA_ON snooze after SLEEP1 enable (default)
D4 SLEEP0 snooze 0: no control
1: PA_ON snooze after SLEEP0 enable (default)
[D3:D2] Reserved Reserved
D1 PA_ON SLEEP1 0: no control (default)
1: PA_ON controlled by the SLEEP1 pin
D0
PA_ON SLEEP0
0: no control (default)
1: PA_ON controlled by the SLEEP0 pin
Table 49. Ramp Time 0 to Ramp Time 3 Registers (Register 0x2A to Register 0x2D)
Bit Number(s) Bit Name Description
[D15:D7] Reserved Reserved
[D6:D0] B6 to B0 Ramp time bits configure the ramp time for the DACs in closed-loop mode
0000000 = no ramp function (default)
0000001 to 0010000 = 4 ms
0010001 = 4.25 ms
…
1111110 = 31.5 ms
1111111 = 31.75 ms
Table 50. Closed-Loop Fast Ramp and Integrator Time Constant Register (Register 0x2E)
Bit Number(s) Bit Name Description
D15 CL3_FR 0: Closed-Loop 3 fast ramp disable
1: Closed-Loop 3 fast ramp enable (default)
[D14:D12] CL3_CAP_TRIM[2:0] 000: not applicable
001: 2.352 ms
010: 1.218 ms
011: 840 µs (default)
100: 650 µs
101: 538 µs
110: 462 µs
111: 408 µs
Data Sheet AD7293
Rev. D | Page 45 of 79
Bit Number(s) Bit Name Description
D11 CL2_FR 0: Closed-Loop 2 fast ramp disable
1: Closed-Loop 2 fast ramp enable (default)
[D10:D8] CL2_CAP_TRIM[2:0] 000: not applicable
001: 2.352 ms
010: 1.218 ms
011: 840 µs (default)
100: 650 µs
101: 538 µs
110: 462 µs
111: 408 µs
D7
CL1_FR
0: Closed-Loop 1 fast ramp disable
1: Closed-Loop 1 fast ramp enable (default)
[D6:D4] CL1_CAP_TRIM[2:0] 000: not applicable
001: 2.352 ms
010: 1.218 ms
011: 840 µs (default)
100: 650 µs
101: 538 µs
110: 462 µs
111: 408 µs
D3 CL0_FR 0: Closed-Loop 0 fast ramp disable
1: Closed-Loop 0 fast ramp enable (default)
[D2:D0] CL0_CAP_TRIM[2:0] 000: not applicable
001: 2.352 ms
010: 1.218 ms
011: 840 µs (default)
100: 650 µs
101: 538 µs
110: 462 µs
111: 408 µs
Table 51. Integrator Limit Active Status (INTLIMITx) and AVSS/AVDD Alarm Mask Register (Register 0x2F)
Bit Number(s) Bit Name Description
[D15:D12] Reserved Reserved
D11 INTLIMIT3 0: no masking (default)
1: masks alerts such that they are not visible when reading back the corresponding alert registers and/or
if routed to ALERTx pins
D10 INTLIMIT2 0: no masking (default)
1: masks alerts such that they are not visible when reading back the corresponding alert registers and/or
if routed to ALERTx pins
D9 INTLIMIT1 0: no masking (default)
1: masks alerts such that they are not visible when reading back the corresponding alert registers and/or
if routed to ALERTx pins
D8
INT
LIMIT
0
0: no masking (default)
1: masks alerts such that they are not visible when reading back the corresponding alert registers and/or
if routed to ALERTx pins
[D7:D1]
Reserved
Reserved
D0 AVSS/AVDD alarm 0: no masking (default)
1: masks alert
AD7293 Data Sheet
Rev. D | Page 46 of 79
SEQUENCE (PAGE 0x03)
The sequence page contains registers that allow the user to
sequence and read back the conversions results from selected
channels in command mode.
Table 52. Sequence (Page 0x03)
Address
(Hex) Name Byte1
Access
Type1
Default
Value1
0x00 No op N/A N/A 0x00
0x01 Page select pointer 1 R/W 0x00
0x02
Conversion command
2
1
W
N/A
0x03 Result 2 R 0x0000
0x04 DAC enable 1 R/W 0x00
0x05 GPIO 1 R/W 0x00
0x0C Device ID 2 R 0x0018
0x0F Software reset 2 R/W 0x0000
0x10 VINx sequence 2 R/W 0x0000
0x11 ISENSEx and TSENSEx
sequence
2 R/W 0x0000
0x12 RSx+MON, supply
monitor, and BI-VOUTx
monitor sequence
2 R/W 0x0000
1 N/A means not applicable.
2 Not a physical register.
Voltage Input (VINx) Sequence Register (Register 0x10)
This 16-bit register allows the user to sequence the ADC
conversions for the four input channels in command mode.
Current Sensor (ISENSEx) and Temperature Sensor (TSENSEx)
Sequence Register (Register 0x11)
This 16-bit register allows the user to sequence the results read
back for the four current sense and three temperature sensor
channels. The range for the current sense and temperature
sense channels is fixed at 0 V to REFADC (1.25 V). However, the
corresponding bit from the enable registers on the configuration
page must be set to run a conversion for a temperature sensor
or current sensor channel in command mode.
RSx+MON, Supply Monitor, and BI-VOUTx Monitor Sequence
Register (Register 0x12)
This 16-bit register allows the user to sequence and read back
the ADC conversion results for the four RSx+ pins, four voltage
supplies, and the four DAC monitor channels in command mode.
Table 53. VINx Sequence Register (Register 0x10)
Bit Number(s) Bit Name Description
[D15:D4] Reserved Reserved
D3 VIN3 1: command mode sequencing enabled
0: command mode sequencing disabled (default)
D2
V
IN
2
1: command mode sequencing enabled
0: command mode sequencing disabled (default)
D1 VIN1 1: command mode sequencing enabled
0: command mode sequencing disabled (default)
D0 VIN0 1: command mode sequencing enabled
0: command mode sequencing disabled (default)
Table 54. ISENSEx and TSENSEx Sequence Register (Register 0x11)
Bit Number(s) Bit Name Description
[D15:D12] Reserved Reserved
D11 ISENSE3 0: no control (default)
1: command mode sequencing enabled
D10 ISENSE2 0: no control (default)
1: command mode sequencing enabled
D9 ISENSE1 0: no control (default)
1: command mode sequencing enabled
D8
I
SENSE
0
0: no control (default)
1: command mode sequencing enabled
[D7:D3] Reserved Reserved
D2 TSENSED1 0: no control (default)
1: command mode sequencing enabled
D1 TSENSED0 0: no control (default)
1: command mode sequencing enabled
D0 TSENSEINT 0: no control (default)
1: command mode sequencing enabled
Data Sheet AD7293
Rev. D | Page 47 of 79
Table 55. RSx+MON, Supply Monitor, and BI-VOUTx Monitor Sequence Register (Register 0x12)
Bit Number(s) Bit Name Description
[D15:D12] Reserved Reserved
D11
RS3+
MON
0: no control (default)
1: command mode sequencing enabled
D10 RS2+MON 0: no control (default)
1: command mode sequencing enabled
D9 RS1+MON 0: no control (default)
1: command mode sequencing enabled
D8 RS0+MON 0: no control (default)
1: command mode sequencing enabled
D7 BI-VOUT3MON 0: no control (default)
1: command mode sequencing enabled
D6 BI-VOUT2MON 0: no control (default)
1: command mode sequencing enabled
D5 BI-VOUT1MON 0: no control (default)
1: command mode sequencing enabled
D4
BI-V
OUT
0
MON
0: no control (default)
1: command mode sequencing enabled
D3 AVSS 0: no control (default)
1: command mode sequencing enabled
D2 DACVDD-BI 0: no control (default)
1: command mode sequencing enabled
D1 DACVDD-UNI 0: no control (default)
1: command mode sequencing enabled
D0 AVDD 0: no control (default)
1: command mode sequencing enabled
AD7293 Data Sheet
Rev. D | Page 48 of 79
HIGH LIMIT 0 (PAGE 0x04)
Table 56. High Limit 0 (Page 0x04)
Address
(Hex) Name Byte1
Access
Type1
Default
Value1
0x00 No op N/A N/A 0x00
0x01 Page select pointer 1 R/W 0x00
0x02 Conversion command2 1 W N/A
0x03 Result 2 R 0x0000
0x04
DAC enable
1
R/W
0x00
0x05 GPIO 1 R/W 0x00
0x0C Device ID 2 R 0x0018
0x0F Software reset 2 R/W 0x0000
0x10 VIN0 high limit 2 R/W 0xFFF0
0x11 VIN1 high limit 2 R/W 0xFFF0
0x12 VIN2 high limit 2 R/W 0xFFF0
0x13 VIN3 high limit 2 R/W 0xFFF0
0x20 TSENSEINT high limit 2 R/W 0xFFF0
0x21 TSENSED0 high limit 2 R/W 0xFFF0
0x22 TSENSED1 high limit 2 R/W 0xFFF0
0x28 ISENSE0 high limit 2 R/W 0xFFF0
0x29 ISENSE1 high limit 2 R/W 0xFFF0
0x2A ISENSE2 high limit 2 R/W 0xFFF0
0x2B ISENSE3 high limit 2 R/W 0xFFF0
1 N/A means not applicable.
2 Not a physical register.
VINx High Limit Registers (Register 0x10 to Register 0x13)
These read/write 16-bit registers set the high limits for the four
input channels. The default value of these registers is 0xFFF0.
Temperature Sensor (TSENSEx) High Limit Registers
(Register 0x20 to Register 0x22)
These read/write 16-bit registers set the high limits for the three
temperature sensor channels. The default value of these
registers is 0xFFF0.
Table 57. Temperature Sensor High Limit Registers
(Register 0x20 to Register 0x22)
Bit Number(s) Bit Name Description
D15 B11 0: −256°C
1: 0°C (default)
D14 B10 0: 0°C
1: 128°C (default)
D13 B9 0: 0°C
1: 64°C (default)
D12 B8 0: 0°C
1: 32°C (default)
D11 B7 0: 0°C
1: 16°C (default)
D10
B6
0: 0°C
1: 8°C (default)
D9 B5 0: 0°C
1: 4°C (default)
D8 B4 0: 0°C
1: 2°C (default)
D7 B3 0: 0°C
1: 1°C (default)
D6 B2 0: 0°C
1: 0.5°C (default)
D5 B1 0: 0°C
1: 0.25°C (default)
D4 B0 0: 0°C
1: 0.125°C (default)
[D3:D0]
Reserved
Reserved
Current Sensor (ISENSEx) High Limit Registers (Register 0x28
to Register 0x2B)
These read/write 16-bit registers set the high limits for the four
current sensor channels. The default value of these registers is
0xFFF0.
Table 58. VINx (Register 0x10 to Register 0x13) and ISENSEx High Limit Registers (Register 0x28 to Register 0x2B)
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 [D3:D0]
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Reserved
Data Sheet AD7293
Rev. D | Page 49 of 79
HIGH LIMIT 1 (PAGE 0x05)
Table 59. High Limit 1 (Page 0x05)
Address
(Hex) Name Byte1
Access
Type1
Default
Value1
0x00 No op N/A N/A 0x00
0x01 Page select pointer 1 R/W 0x00
0x02 Conversion command2 1 W N/A
0x03 Result 2 R 0x0000
0x04
DAC enable
1
R/W
0x00
0x05 GPIO 1 R/W 0x00
0x0C Device ID 2 R 0x0018
0x0F Software reset 2 R/W 0x0000
0x10 AVDD high limit 2 R/W 0xFFF0
0x11 DACVDD-UNI high limit 2 R/W 0xFFF0
0x12 DACVDD-BI high limit 2 R/W 0xFFF0
0x13 AVSS high limit 2 R/W 0xFFF0
0x14 BI-VOUT0MON high limit 2 R/W 0xFFF0
0x15 BI-VOUT1MON high limit 2 R/W 0xFFF0
0x16 BI-VOUT2MON high limit 2 R/W 0xFFF0
0x17 BI-VOUT3MON high limit 2 R/W 0xFFF0
0x28 RS0+MON high limit 2 R/W 0xFFF0
0x29 RS1+MON high limit 2 R/W 0xFFF0
0x2A RS2+MON 2 R/W 0xFFF0
0x2B RS3+MON 2 R/W 0xFFF0
1 N/A means not applicable.
2 Not a physical register.
AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI) and AVSS High
Limit Registers (Register 0x10 to Register 0x13)
These read/write 16-bit registers set the high limits for the four
voltage supply conversions. The default value of these registers
is 0xFFF0.
BI-VOUT0MON to BI-VOUT3MON High Limit Registers
(Register 0x14 to Register 0x17)
These registers store the high limits for the four internal inputs
for monitoring the bipolar DAC outputs in open-loop mode or
the integrator outputs in closed-loop mode.
RSx+MON High Limit Registers (Register 0x28 to
Register 0x2B)
These registers store the high limits for the RSx+MON monitoring
channels.
Table 60. AVDD, DAC Supply, AVSS, BI-VOUTxMON, and RSx+MON High Limit Registers (Register 0x10 to Register 0x2B)
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 [D3:D0]
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Reserved
AD7293 Data Sheet
Rev. D | Page 50 of 79
LOW LIMIT 0 (PAGE 0x06)
Table 61. Low Limit 0 (Page 0x06)
Address
(Hex) Name Byte1
Access
Type1
Default
Value1
0x00 No op N/A N/A 0x00
0x01 Page select pointer 1 R/W 0x00
0x02 Conversion command2 1 W N/A
0x03 Result 2 R 0x0000
0x04
DAC enable
1
R/W
0x00
0x05 GPIO 1 R/W 0x00
0x0C Device ID 2 R 0x0018
0x0F Software reset 2 R/W 0x0000
0x10 VIN0 low limit 2 R/W 0x0000
0x11 VIN1 low limit 2 R/W 0x0000
0x12 VIN2 low limit 2 R/W 0x0000
0x13 VIN3 low limit 2 R/W 0x0000
0x20 TSENSEINT low limit 2 R/W 0x0000
0x21 TSENSED0 low limit 2 R/W 0x0000
0x22 TSENSED1 low limit 2 R/W 0x0000
0x28 ISENSE0 low limit 2 R/W 0x0000
0x29 ISENSE1 low limit 2 R/W 0x0000
0x2A ISENSE2 low limit 2 R/W 0x0000
0x2B ISENSE3 low limit 2 R/W 0x0000
1 N/A means not applicable.
2 Not a physical register.
VINx Low Limit Registers (Register 0x10 to Register 0x13)
These read/write 16-bit registers set the low limits for the four
input channels.
Temperature Sensor (TSENSEx) Low Limit Registers
(Register 0x20 to Register 0x22)
These read/write 16-bit registers set the low limits for the three
temperature sensor channels.
Table 62. Temperature Sensor Low Limit Registers
(Register 0x20 to Register 0x22)
Bit Number(s) Bit Name Description
D15 B11 0: −256°C (default)
1: 0°C
D14 B10 0: 0°C (default)
1: 128°C
D13 B9 0: 0°C (default)
1: 64°C
D12 B8 0: 0°C (default)
1: 32°C
D11 B7 0: 0°C (default)
1: 16°C
D10 B6 0: 0°C (default)
1: 8°C
D9 B5 0: 0°C (default)
1: 4°C
D8 B4 0: 0°C (default)
1: 2°C
D7 B3 0: 0°C (default)
1: 1°C
D6 B2 0: 0°C (default)
1: 0.5°C
D5 B1 0: 0°C (default)
1: 0.25°C
D4
B0
0: 0°C (default)
1: 0.125°C
[D3:D0] Reserved Reserved
Current Sensor (ISENSEx) Low Limit Registers (Register 0x28
to Register 0x2B)
These read/write 16-bit registers set the low limits for the four
current sensor channels.
Table 63. VINx and Current Sensor Low Limit Registers (Register 0x10 to Register 0x13, and Register 0x28 to Register 0x2B)
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 [D3:D0]
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Reserved
Data Sheet AD7293
Rev. D | Page 51 of 79
LOW LIMIT 1 (PAGE 0x07)
Table 64. Low Limit 1 (Page 0x07)
Address
(Hex) Name Byte1
Access
Type1
Default
Value1
0x00 No op N/A N/A 0x00
0x01 Page select pointer 1 R/W 0x00
0x02 Conversion command2 1 W N/A
0x03 Result 2 R 0x0000
0x04
DAC enable
1
R/W
0x00
0x05 GPIO 1 R/W 0x00
0x0C Device ID 2 R 0x0018
0x0F Software reset 2 R/W 0x0000
0x10 AVDD low limit 2 R/W 0x0000
0x11 DACVDD-UNI low limit 2 R/W 0x0000
0x12 DACVDD-BI low limit 2 R/W 0x0000
0x13 AVSS low limit 2 R/W 0x0000
0x14 BI-VOUT0MON low limit 2 R/W 0x0000
0x15 BI-VOUT1MON low limit 2 R/W 0x0000
0x16 BI-VOUT2MON low limit 2 R/W 0x0000
0x17 BI-VOUT3MON low limit 2 R/W 0x0000
0x28 RS0+MON low limit 2 R/W 0x0000
0x29 RS1+MON low limit 2 R/W 0x0000
0x2A RS2+MON low limit 2 R/W 0x0000
0x2B RS3+MON low limit 2 R/W 0x0000
1 N/A means not applicable.
2 Not a physical register.
AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI), and AVSS Low
Limit Registers (Register 0x10 to Register 0x13)
These read/write 16-bit registers set the low limits for the four
supply channels.
BI-VOUT0MON to BI-VOUT3 MON Low Limit Registers
(Register 0x14 to Register 0x17)
These registers store the low limits from the four internal inputs
for monitoring the bipolar DAC outputs, although the intention
is to monitor the bipolar DAC outputs in open-loop mode or
the integrator outputs in closed-loop mode.
RSx+MON Low Limit Registers (Register 0x28 to
Register 0x2B)
These registers store the low limits for the RSx+MON monitoring
channels.
Table 65. AVDD, DAC Supply, AVSS, BI-VOUTxMON, and RSx+MON Low Limit Registers (Register 0x10 to Register 0x2B)
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 [D3:D0]
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Reserved
AD7293 Data Sheet
Rev. D | Page 52 of 79
HYSTERESIS 0 (PAGE 0x08)
Table 66. Hysteresis 0 (Page 0x08)
Address
(Hex) Name Byte1
Access
Type1
Default
Value1
0x00 No op N/A N/A 0x00
0x01 Page select pointer 1 R/W 0x00
0x02 Conversion command2 1 W N/A
0x03 Result 2 R 0x0000
0x04
DAC enable
1
R/W
0x00
0x05 GPIO 1 R/W 0x00
0x0C Device ID 2 R 0x0018
0x0F Software reset 2 R/W 0x0000
0x10 VIN0 hysteresis 2 R/W 0x0000
0x11 VIN1 hysteresis 2 R/W 0x0000
0x12 VIN2 hysteresis 2 R/W 0x0000
0x13 VIN3 hysteresis 2 R/W 0x0000
0x20 TSENSEINT hysteresis 2 R/W 0x0000
0x21 TSENSED0 hysteresis 2 R/W 0x0000
0x22 TSENSED1 hysteresis 2 R/W 0x0000
0x28 ISENSE0 hysteresis 2 R/W 0x0000
0x29 ISENSE1 hysteresis 2 R/W 0x0000
0x2A ISENSE2 hysteresis 2 R/W 0x0000
0x2B ISENSE3 hysteresis 2 R/W 0x0000
1 N/A means not applicable.
2 Not a physical register.
VINx Hysteresis Registers (Register 0x10 to Register 0x13)
These read/write 16-bit registers set the hysteresis values for the
four input channels.
Temperature Sensor (TSENSEx) Hysteresis Registers
(Register 0x20 to Register 0x22)
These read/write 16-bit registers set the hysteresis values for the
three temperature sensor channels. The MSB of this register
must be set to 1.
Table 67. Temperature Sensor Hysteresis Registers
(Register 0x20 to Register 0x22)
Bit Number(s) Bit Name Description
D15 Reserved Reserved. Must be set to 1.
D14 B10 0: 0°C (default)
1: 128°C
D13 B9 0: 0°C (default)
1: 64°C
D12
B8
0: 0°C (default)
1: 32°C
D11 B7 0: 0°C (default)
1: 16°C
D10 B6 0: 0°C (default)
1: 8°C
D9 B5 0: 0°C (default)
1: 4°C
D8 B4 0: 0°C (default)
1: 2°C
D7 B3 0: 0°C (default)
1: 1°C
D6 B2 0: 0°C (default)
1: 0.5°C
D5
B1
0: 0°C (default)
1: 0.25°C
D4 B0 0: 0°C (default)
1: 0.125°C
[D3:D0] Reserved Reserved
Current Sensor (ISENSEx) Hysteresis Registers
(Register 0x28 to Register 0x2B)
These read/write 16-bit registers set the hysteresis values for the
four current sensor channels.
Table 68. VINx and Current Sensor Hysteresis Registers (Register 0x10 to Register 0x13, and Register 0x28 to Register 0x2B)
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 [D3:D0]
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Reserved
Data Sheet AD7293
Rev. D | Page 53 of 79
HYSTERESIS 1 (PAGE 0x09)
Table 69. Hysteresis 1 (Page 0x09)
Address
(Hex) Name Byte1
Access
Type1
Default
Value1
0x00 No op N/A N/A 0x00
0x01 Page select pointer 1 R/W 0x00
0x02 Conversion command2 1 W N/A
0x03 Result 2 R 0x0000
0x04
DAC enable
1
R/W
0x00
0x05 GPIO 1 R/W 0x00
0x0C Device ID 2 R 0x0018
0x0F Software reset 2 R/W 0x0000
0x10 AVDD hysteresis 2 R/W 0x0000
0x11 DACVDD-UNI hysteresis 2 R/W 0x0000
0x12 DACVDD-BI hysteresis 2 R/W 0x0000
0x13 AVSS hysteresis 2 R/W 0x0000
0x14 BI-VOUT0MON hysteresis 2 R/W 0x0000
0x15 BI-VOUT1MON hysteresis 2 R/W 0x0000
0x16 BI-VOUT2MON hysteresis 2 R/W 0x0000
0x17 BI-VOUT3MON hysteresis 2 R/W 0x0000
0x28 RS0+MON hysteresis 2 R/W 0x0000
0x29 RS1+MON hysteresis 2 R/W 0x0000
0x2A RS2+MON hysteresis 2 R/W 0x0000
0x2B RS3+MON hysteresis 2 R/W 0x0000
1 N/A means not applicable.
2 Not a physical register.
AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI), and AVSS
Hysteresis Registers (Register 0x10 to Register 0x13)
These read/write 16-bit registers set the hysteresis values for the
four supply voltage conversions.
BI-VOUT0MON to BI-VOUT3MON Hysteresis Registers
(Register 0x14 to Register 0x17)
These read/write 16-bit registers set the hysteresis values for the
four DAC monitoring conversions.
RSx+MON Hysteresis Registers (Register 0x28 to
Register 0x2B)
These read/write 16-bit registers set the hysteresis values for the
four RSx+ conversions.
Table 70. AVDD, DAC Supply, AVSS, BI-VOUTxMON, and RSx+MON Hysteresis Registers (Register 0x10 to Register 0x2B)
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 [D3:D0]
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Reserved
AD7293 Data Sheet
Rev. D | Page 54 of 79
MINIMUM 0 (PAGE 0x0A)
Table 71. Minimum 0 (Page 0x0A)
Address
(Hex) Name Byte1
Access
Type1
Default
Value1
0x00 No op N/A N/A 0x00
0x01 Page select pointer 1 R/W 0x00
0x02 Conversion command2 1 W N/A
0x03 Result 2 R 0x0000
0x04
DAC enable
1
R/W
0x00
0x05 GPIO 1 R/W 0x00
0x0C Device ID 2 R 0x0018
0x0F Software reset 2 R/W 0x0000
0x10 VIN0 minimum 2 R/W 0xFFF0
0x11 VIN1 minimum 2 R/W 0xFFF0
0x12 VIN2 minimum 2 R/W 0xFFF0
0x13 VIN3 minimum 2 R/W 0xFFF0
0x20 TSENSEINT minimum 2 R/W 0xFFF0
0x21 TSENSED0 minimum 2 R/W 0xFFF0
0x22 TSENSED1 minimum 2 R/W 0xFFF0
0x28 ISENSE0 minimum 2 R/W 0xFFF0
0x29 ISENSE1 minimum 2 R/W 0xFFF0
0x2A ISENSE2 minimum 2 R/W 0xFFF0
0x2B ISENSE3 minimum 2 R/W 0xFFF0
1 N/A means not applicable.
2 Not a physical register.
VINx Minimum Registers (Register 0x10 to Register 0x13)
These 16-bit registers store the minimum ADC conversion
results for the relevant input channel. The default value of these
registers is 0xFFF0. These registers can be set back to their
default value by writing to them (the 12-bit write value is not
written to these registers).
Temperature Sensor (TSENSEx) Minimum Registers
(Register 0x20 to Register 0x22)
These 16-bit registers store the minimum ADC conversion results
for the relevant temperature sensor channel. The default value
of these registers is 0xFFF0. These registers can be set back to
their default value by writing to them (the 12-bit write value is
not written to these registers).
Table 72. Temperature Sensor Minimum Registers
(Register 0x20 to Register 0x22)
Bit Number(s) Bit Name Description
D15 B11 0: −256°C
1: 0°C
D14 B10 0: 0°C
1: 128°C
D13 B9 0: 0°C
1: 64°C
D12 B8 0: 0°C
1: 32°C
D11 B7 0: 0°C
1: 16°C
D10 B6 0: 0°C
1: 8°C
D9 B5 0: 0°C
1: 4°C
D8 B4 0: 0°C
1: 2°C
D7 B3 0: 0°C
1: 1°C
D6 B2 0: 0°C
1: 0.5°C
D5 B1 0: 0°C
1: 0.25°C
D4 B0 0: 0°C
1: 0.125°C
[D3:D0] Reserved Reserved
Current Sensor (ISENSEx) Minimum Registers
(Register 0x28 to Register 0x2B)
These 16-bit registers store the minimum ADC conversion
results for the relevant current sensor channel. The default value
of these registers is 0xFFF0. These registers can be set back to
their default value by writing to them (the 12-bit write value is
not written to these registers).
Table 73. VINx and Current Sensor Minimum Registers (Register 0x10 to Register 0x13, and Register 0x28 to Register 0x2B)
MSB LSB
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
[D3:D0]
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Reserved
Data Sheet AD7293
Rev. D | Page 55 of 79
MINIMUM 1 (PAGE 0x0B)
Table 74. Minimum 1 (Page 0x0B)
Address
(Hex) Name Byte1
Access
Type1
Default
Value1
0x00 No op N/A N/A 0x00
0x01 Page select pointer 1 R/W 0x00
0x02 Conversion command2 1 W N/A
0x03 Result 2 R 0x0000
0x04
DAC enable
1
R/W
0x00
0x05 GPIO 1 R/W 0x00
0x0C Device ID 2 R 0x0018
0x0F Software reset 2 R/W 0x0000
0x10 AVDD minimum 2 R/W 0xFFF0
0x11 DACVDD-UNI minimum 2 R/W 0xFFF0
0x12 DACVDD-BI minimum 2 R/W 0xFFF0
0x13 AVSS minimum 2 R/W 0xFFF0
0x14 BI-VOUT0MON minimum 2 R/W 0xFFF0
0x15 BI-VOUT1MON minimum 2 R/W 0xFFF0
0x16 BI-VOUT2MON minimum 2 R/W 0xFFF0
0x17
BI-V
OUT
3
MON
minimum
2
R/W
0xFFF0
0x28 RS0+MON minimum 2 R/W 0xFFF0
0x29 RS1+MON minimum 2 R/W 0xFFF0
0x2A RS2+MON minimum 2 R/W 0xFFF0
0x2B RS3+MON minimum 2 R/W 0xFFF0
1 N/A means not applicable.
2 Not a physical register.
AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI), and AVSS
Minimum Registers (Register 0x10 to Register 0x13)
These 16-bit registers store the minimum ADC conversion
results for the relevant channels. These registers can be set back
to their default value by writing to them.
BI-VOUT0MON to BI-VOUT3MON Minimum Registers
(Register 0x14 to Register 0x17)
These 16-bit registers store the minimum ADC conversion
results for the relevant DAC monitoring channels. These
registers can be set back to their default value by writing to
them.
RSx+MON Minimum Registers (Register 0x28 to
Register 0x2B)
These 16-bit registers store the minimum ADC conversion
results for the relevant channels. These registers can be set back
to their default value by writing to them.
Table 75. AVDD, DAC Supply, AVSS, BI-VOUTxMON, and RSx+MON Minimum Registers (Register 0x10 to Register 0x2B)
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 [D3:D0]
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Reserved
AD7293 Data Sheet
Rev. D | Page 56 of 79
MAXIMUM 0 (PAGE 0x0C)
Table 76. Maximum 0 (Page 0x0C)
Address
(Hex) Name Byte1
Access
Type1
Default
Value1
0x00 No op N/A N/A 0x00
0x01 Page select pointer 1 R/W 0x00
0x02 Conversion command2 1 W N/A
0x03 Result 2 R 0x0000
0x04
DAC enable
1
R/W
0x00
0x05 GPIO 1 R/W 0x00
0x0C Device ID 2 R 0x0018
0x0F Software reset 2 R/W 0x0000
0x10 VIN0 maximum 2 R/W 0x0000
0x11 VIN1 maximum 2 R/W 0x0000
0x12 VIN2 maximum 2 R/W 0x0000
0x13 VIN3 maximum 2 R/W 0x0000
0x20 TSENSEINT maximum 2 R/W 0x0000
0x21 TSENSED0 maximum 2 R/W 0x0000
0x22 TSENSED1 maximum 2 R/W 0x0000
0x28 ISENSE0 maximum 2 R/W 0x0000
0x29 ISENSE1 maximum 2 R/W 0x0000
0x2A ISENSE2 maximum 2 R/W 0x0000
0x2B ISENSE3 maximum 2 R/W 0x0000
1 N/A means not applicable.
2 Not a physical register.
VINx Maximum Registers (Register 0x10 to Register 0x13)
These 16-bit registers store the maximum ADC conversion
results for the relevant input channel. These registers can be set
back to their default value by writing to them (the 12-bit write
value is not written to these registers).
Temperature Sensor (TSENSEx) Maximum Registers
(Register 0x20 to Register 0x22)
These 16-bit registers store the maximum ADC conversion
results for the relevant temperature sensor channel. These
registers can be set back to their default value by writing to
them (the 12-bit write value is not written to these registers).
Table 77. Temperature Sensor Maximum Registers
(Register 0x20 to Register 0x22)
Bit
Number(s)
Bit
Name Description
D15 B11 0: −256°C
1: 0°C
D14
B10
0: 0°C
1: 128°C
D13 B9 0: 0°C
1: 64°C
D12 B8 0: 0°C
1: 32°C
D11 B7 0: 0°C
1: 16°C
D10 B6 0: 0°C
1: 8°C
D9 B5 0: 0°C
1: 4°C
D8 B4 0: 0°C
1: 2°C
D7
B3
0: 0°C
1: 1°C
D6 B2 0: 0°C
1: 0.5°C
D5 B1 0: 0°C
1: 0.25°C
D4 B0 0: 0°C
1: 0.125°C
[D3:D0] Reserved Reserved
Current Sensor (ISENSEx) Maximum Registers
(Register 0x28 to Register 0x2B)
These 16-bit registers store the maximum ADC conversion
results for the relevant current sensor channel. These registers can
be set back to their default value by writing to them (the 12-bit
write value is not written to these registers).
Table 78. VINx and Current Sensor Maximum Registers (Register 0x10 to Register 0x13, and Register 0x28 to Register 0x2B)
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 [D3:D0]
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Reserved
Data Sheet AD7293
Rev. D | Page 57 of 79
MAXIMUM 1 (PAGE 0x0D)
Table 79. Maximum 1 (Page 0x0D)
Address
(Hex)
Name
Byte
1
Access
Type
1
Default
Value
1
0x00 No op N/A N/A 0x00
0x01 Page select pointer 1 R/W 0x00
0x02 Conversion command2 1 W N/A
0x03 Result 2 R 0x0000
0x04
DAC enable
1
R/W
0x00
0x05 GPIO 1 R/W 0x00
0x0C Device ID 2 R 0x0018
0x0F Software reset 2 R/W 0x0000
0x10 AVDD maximum 2 R/W 0x0000
0x11 DACVDD-UNI maximum 2 R/W 0x0000
0x12 DACVDD-BI maximum 2 R/W 0x0000
0x13 AVSS maximum 2 R/W 0x0000
0x14 BI-VOUT0MON maximum 2 R/W 0x0000
0x15 BI-VOUT1MON maximum 2 R/W 0x0000
0x16 BI-VOUT2MON maximum 2 R/W 0x0000
0x17 BI-VOUT3MON maximum 2 R/W 0x0000
0x28 RS0+MON maximum 2 R/W 0x0000
0x29 RS1+MON maximum 2 R/W 0x0000
0x2A RS2+MON maximum 2 R/W 0x0000
0x2B RS3+MON maximum 2 R/W 0x0000
1 N/A means not applicable.
2 Not a physical register.
AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI), and AVSS
Maximum Registers (Register 0x10 to Register 0x13)
These 16-bit registers store the maximum ADC conversion
results for the relevant channels.
BI-VOUT0MON to BI-VOUT3MON Maximum Registers
(Register 0x14 to Register 0x17)
These 16-bit registers store the maximum ADC conversion
results for the relevant DAC monitoring channels. These
registers can be set back to their default value by writing to
them.
RSx+MON Maximum Registers (Register 0x28 to
Register 0x2B)
These 16-bit registers store the maximum ADC conversion
results for the relevant channels. These registers can be set back
to their default value by writing to them.
Table 80. AVDD, DAC Supply, AVSS, BI-VOUTxMON, and RSx+MON Maximum Registers (Register 0x10 to Register 0x2B)
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 [D3:D0]
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Reserved
AD7293 Data Sheet
Rev. D | Page 58 of 79
OFFSET 0 (PAGE 0x0E)
Table 81. Offset 0 (Page 0x0E)
Address
(Hex)
Name
Byte
1
Access
Type
1
Default
Value
1
0x00 No op N/A N/A 0x00
0x01 Page select
pointer
1 R/W 0x00
0x02 Conversion
command2
1 W N/A
0x03 Result 2 R 0x0000
0x04 DAC enable 1 R/W 0x00
0x05 GPIO 1 R/W 0x00
0x0C Device ID 2 R 0x0018
0x0F Software reset 2 R/W 0x0000
0x10 VIN0 offset 1 R/W 0x00
0x11 VIN1 offset 1 R/W 0x00
0x12 VIN2 offset 1 R/W 0x00
0x13 VIN3 offset 1 R/W 0x00
0x20 TSENSEINT offset 1 R/W 0x00
0x21
T
SENSE
D0 offset
1
R/W
0x00
0x22 TSENSED1 offset 1 R/W 0x00
0x28 ISENSE0 offset 1 R/W 0x00
0x29 ISENSE1 offset 1 R/W 0x00
0x2A ISENSE2 offset 1 R/W 0x00
0x2B ISENSE3 offset 1 R/W 0x00
0x30
UNI-V
OUT
0 offset
1
R/W
0x00
0x31 UNI-VOUT1 offset 1 R/W 0x00
0x32 UNI-VOUT2 offset 1 R/W 0x00
0x33 UNI-VOUT3 offset 1 R/W 0x00
0x34 BI-VOUT0 offset 1 R/W 0x00
0x35 BI-VOUT1 offset 1 R/W 0x00
0x36 BI-VOUT2 offset 1 R/W 0x00
0x37 BI-VOUT3 offset 1 R/W 0x00
1 N/A means not applicable.
2 Not a physical register.
VINx Offset Registers (Register 0x10 to Register 0x13)
These read/write 8-bit registers store the offset values for the
relevant input channel.
Temperature Sensor (TSENSEx) Offset Registers
(Register 0x20 to Register 0x22)
These read/write 8-bit registers store the offset values for the
relevant temperature sensor channel.
Current Sensor (ISENSEx) Offset Registers (Register 0x28 to
Register 0x2B)
These read/write 8-bit registers store the offset values for the
relevant current sensor channel.
Unipolar DAC (UNI-VOUTx) Offset Registers (Register 0x30
to Register 0x33)
These read/write registers store the offset values for the
corresponding DAC output. If the copy bit is set to 1, writing to
any of the DAC offset registers sets all the other unipolar DAC
offset registers to the same value.
Bipolar DAC (BI-VOUTx) Offset Registers (Register 0x34 to
Register 0x37)
These read/write registers store the offset values for the
corresponding DAC output. If the copy bit is set to 1, writing to
any of the DAC offset registers sets all the other bipolar DAC
offset registers to the same value. Any write to these registers
affects the DAC range in open-loop mode and the integrator
limit in closed-loop mode.
Table 82. VINx and Current Sensor Offset Registers (Register 0x10 to Register 0x13, and Register 0x28 to Register 0x2B)
Bit Number(s) Bit Name Description
D7 B7 0: 0 LSB (default)
1: −128 LSB
D6 B6 0: 0 LSB (default)
1: 64 LSB
D5 B5 0: 0 LSB (default)
1: 32 LSB
D4 B4 0: 0 LSB (default)
1: 16 LSB
D3 B3 0: 0 LSB (default)
1: 8 LSB
D2 B2 0: 0 LSB (default)
1: 4 LSB
D1 B1 0: 0 LSB (default)
1: 2 LSB
D0 B0 0: 0 LSB (default)
1: 1 LSB
Data Sheet AD7293
Rev. D | Page 59 of 79
Table 83. Temperature Sensor Offset Registers (Register 0x20 to Register 0x22)
Bit Number(s) Bit Name Description
D7 B7 0: 0°C (default)
1: −16°C
D6 B6
0: 0°C (default)
1: 8°C
D5 B5 0: 0°C (default)
1: 4°C
D4 B4 0: 0°C (default)
1: 2°C
D3 B3 0: 0°C (default)
1: 1°C
D2 B2 0: 0°C (default)
1: 0.5°C
D1 B1 0: 0°C (default)
1: 0.25°C
D0 B0 0: 0°C (default)
1: 0.125°C
Table 84. Unipolar DAC Offset Registers (Register 0x30 to Register 0x33)
Bit Number(s) Bit Name Description
[D7:D6] Reserved Reserved
[D5:D4] Offset 00: 0 V to 5 V (default)
01: 2.5 V to 7.5 V
10: 5 V to 10 V
11: 5 V to 10 V
[D3:D2] Reserved Reserved
D1 Copy 0: do not copy (default)
1: sets all unipolar DACs to same value
D0 Reserved Reserved
Table 85. Bipolar DAC Offset Registers (Register 0x34 to Register 0x37)
Bit Number(s) Bit Name Description
[D7:D6] Reserved Reserved
[D5:D4] Offset 00: 0 V to +5 V (default)
01: −4 V to +1 V
10: −5 V to 0 V
11: 0 V to +5 V in open loop, disables upper voltage limit in closed loop
[D3:D2] Reserved Reserved
D1
Copy
0: do not copy (default)
1: sets all bipolar DACs to same value
D0 Reserved Reserved
AD7293 Data Sheet
Rev. D | Page 60 of 79
OFFSET 1 (PAGE 0x0F)
Table 86. Offset 1 (Page 0x0F)
Address
(Hex)
Name
Byte
1
Access
Type
1
Default
Value
1
0x00 No op N/A N/A 0x00
0x01 Page select pointer 1 R/W 0x00
0x02 Conversion
command2
1 W N/A
0x03
Result
2
R
0x0000
0x04 DAC enable 1 R/W 0x00
0x05 GPIO 1 R/W 0x00
0x0C Device ID 2 R 0x0018
0x0F Software reset 2 R/W 0x0000
0x10 AVDD offset 1 R/W 0x00
0x11 DACVDD-UNI offset 1 R/W 0x00
0x12
DACV
DD-BI
offset
1
R/W
0x00
0x13 AVSS offset 1 R/W 0x00
0x14 BI-VOUT0MON offset 1 R/W 0x00
0x15 BI-VOUT1MON offset 1 R/W 0x00
0x16 BI-VOUT2MON offset 1 R/W 0x00
0x17 BI-VOUT3MON offset 1 R/W 0x00
0x28 RS0+MON offset 1 R/W 0x00
0x29 RS1+MON offset 1 R/W 0x00
0x2A RS2+MON offset 1 R/W 0x00
0x2B RS3+MON offset 1 R/W 0x00
1 N/A means not applicable.
2 Not a physical register.
AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI), and AVSS Offset
Registers (Register 0x10 to Register 0x13)
These read/write 8-bit registers store the offset values for the
relevant supply voltage monitoring channels.
BI-VOUT0MON to BI-VOUT3 MON Offset Registers (Register 0x14
to Register 0x17)
These read/write 8-bit registers store the offset values for the
relevant DAC monitoring channels.
RSx+MON Offset Registers (Register 0x28 to Register 0x2B)
These read/write 8-bit registers store the offset values for the
relevant DAC monitoring channels. Note that, prior to
conversion, the RSx+MON voltages are divided by 50.
Table 87. AVDD, DAC Supply, AVSS, BI-VOUTxMON, and RSx+MON Offset Registers (Register 0x10 to Register 0x2B)
Bit Number(s)
Bit Name
Description
D7 B7 0: 0 LSB (default)
1: −128 LSB
D6 B6 0: 0 LSB (default)
1: 64 LSB
D5 B5 0: 0 LSB (default)
1: 32 LSB
D4 B4 0: 0 LSB (default)
1: 16 LSB
D3 B3 0: 0 LSB (default)
1: 8 LSB
D2 B2 0: 0 LSB (default)
1: 4 LSB
D1 B1 0: 0 LSB (default)
1: 2 LSB
D0 B0 0: 0 LSB (default)
1: 1 LSB
Data Sheet AD7293
Rev. D | Page 61 of 79
ALERT (PAGE 0x10)
Table 88. Alert (Page 0x10)
Address
(Hex)
Name
Byte
1
Access
Type
1
Default
Value
1
0x00 No op N/A N/A 0x00
0x01 Page select pointer 1 R/W 0x00
0x02 Conversion command2 1 W N/A
0x03 Result 2 R 0x0000
0x04
DAC enable
1
R/W
0x00
0x05 GPIO 1 R/W 0x00
0x0C Device ID 2 R 0x0018
0x0F Software reset 2 R/W 0x0000
0x10 ALERTSUM 2 R/W 0x0000
0x12 VINx alert 2 R/W 0x0000
0x14 TSENSEx alert 2 R/W 0x0000
0x15 ISENSEx alert 2 R/W 0x0000
0x18 Supply and BI-VOUTxMON
alert
2 R/W 0x0000
0x19 RSx+MON alert 2 R/W 0x0000
0x1A
INT
LIMIT
x and AV
SS
/AV
DD
alert
2
R/W
0x0000
1 N/A means not applicable.
2 Not a physical register.
Alert Summary (ALERTSUM) Register (Register 0x10)
This 16-bit register stores the summary from the channel
dedicated alert registers. If any of the bits from the corresponding
alert register are set, the register bit is set to 1 (OR function of
individual alert register bits). When 1 is written to any of the
register bits, this bit is cleared, that is, removing alerts and the
alert bits from the corresponding alert register. This write is a
quick way to clear any alerts in the device. The upper byte
contains the high alerts, whereas the lower byte contains the low
alerts. This format is applicable to the individual alert registers
as well. The default value of this register is 0x0000.
VINx Alert Register (Register 0x12)
This 16-bit register stores the VIN channel related high and low
alerts. When 1 is written to any of the register bits, this bit
clears, removing the corresponding alert.
Temperature Sensor (TSENSEx) Alert Register (Register 0x14)
This 16-bit register stores the temperature sensor related high
and low alerts. When 1 is written to any of the register bits, this
bit clears, removing the corresponding alert.
Current Sensor (ISENSEx) Alert Register (Register 0x15)
This 16-bit register stores the current sensor related high and
low alerts. When 1 is written to any of the register bits, this bit
clears, removing the corresponding alert.
Table 89. Alert Summary (ALERTSUM) Register (Register 0x10), Bit D15 to Bit D8
D15 D14 D13 D12 D11 D10 D9 D8
RSx+ high AVDD/BI-VOUTx high INTLIMITx active AVSS/AVSS alarm ISENSEx high TSENSEx high Reserved VINx high
Table 90. Alert Summary (ALERTSUM) Register (Register 0x10), Bit D7 to Bit D0
D7 D6 D5 D4 D3 D2 D1 D0
RSx+ low AVDD/BI-VOUTx low Reserved ISENSEx low TSENSEx low Reserved VINx low
Table 91. VINx Alert Register (Register 0x12)
MSB LSB
[D15:D12] D11 D10 D9 D8 [D7:D4] D3 D2 D1 D0
Reserved
V
IN
3 high
V
IN
2 high
V
IN
1 v
V
IN
0 high
Reserved
V
IN
3 low
V
IN
2 low
V
IN
1 low
V
IN
0 low
Table 92. Temperature Sensor Alert Register (Register 0x14)
MSB LSB
[D15:D11] D10 D9 D8 [D7:D3] D2 D1 D0
Reserved TSENSED1 high TSENSED0 high TSENSEINT high Reserved TSENSED1 low TSENSED0 low TSENSEINT low
Table 93. Current Sensor Alert Register (Register 0x15)
MSB LSB
[D15:D12] D11 D10 D9 D8 [D7:D4] D3 D2 D1 D0
Reserved ISENSE3 high ISENSE2 high ISENSE1 high ISENSE0 high Reserved ISENSE3 low ISENSE2 low ISENSE1 low ISENSE0 low
AD7293 Data Sheet
Rev. D | Page 62 of 79
Supply and BI-VOUTxMON Alert Register (Register 0x18)
This 16-bit register stores the AVDD, DACVDD-UNI, DACVDD-BI,
AVSS, BI-VOUTxMON high and low alerts. When 1 is written to any
of the register bits, this bit clears, removing the corresponding
alert.
RSx+MON Alert Register (Register 0x19)
This 16-bit register stores the RSx+ high and low alerts. When 1
is written to any of the register bits, this bit clears, removing the
corresponding alert.
INTLIMITx and AVSS/AVDD Alert Register (Register 0x1A)
This 16-bit register stores the closed-loop integrator limit active
status and AVSS/ AVDD alarm status.
Table 94. Supply and BI-VOUTxMON Alert Register (Register 0x18), Bit D15 to Bit D8
D15 D14 D13 D12 D11 D10 D9 D8
BI-VOUT3MON high BI-VOUT2MON high BI-VOUT1MON high BI-VOUT0MON high AVSS high DACVDD-BI high DACVDD-UNI high AVDD high
Table 95. Supply and BI-VOUTxMON Alert Register (Register 0x18), Bit D7 to Bit D0
D7 D6 D5 D4 D3 D2 D1 D0
BI-VOUT3MON low BI-VOUT2MON low BI-VOUT1MON low BI-VOUT0MON low AVSS low DACVDD-BI low DACVDD-UNI low AVDD low
Table 96. RSx+MON Alert Register (Register 0x19)
MSB LSB
[D15:D12] D11 D10 D9 D8 [D7:D4] D3 D2 D1 D0
Reserved RS3+MON high RS2+MON high RS1+MON high RS0+MON high Reserved RS3+MON low RS2+MON low RS1+MON low RS0+MON low
Table 97. INTLIMITx and AVSS/AVDD Alert Register (Register 0x1A)
MSB
LSB
[D15:D12] D11 D10 D9 D8 [D7:D1] D0
Reserved INTLIMIT3 high INTLIMIT2 high INTLIMIT1 high INTLIMIT0 high Reserved AVSS/AVDD alarm
Data Sheet AD7293
Rev. D | Page 63 of 79
ALERT0 PIN ROUTING (PAGE 0x11)
All the registers from this page allow routing of the alert signals
generated by the corresponding inputs/channels to the GPIO3/
ALERT0 pin of the device. The upper byte controls the high
alerts routing, whereas the lower byte controls the low alerts
routing.
Table 98. ALERT0 Pin Routing (Page 0x11)
Address
(Hex)
Name
Byte
1
Access
Type
1
Default
Value
1
0x00
No op
N/A
N/A
0x00
0x01 Page select pointer 1 R/W 0x00
0x02 Conversion
command2
1 W N/A
0x03 Result 2 R 0x0000
0x04 DAC enable 1 R/W 0x00
0x05
GPIO
1
R/W
0x00
0x0C Device ID 2 R 0x0018
0x0F Software reset 2 R/W 0x0000
0x12 VINx ALERT0 2 R/W 0x0000
0x14 TSENSEx ALERT0 2 R/W 0x0000
0x15 ISENSEx ALERT0 2 R/W 0x0000
0x18 Supply and
BI-VOUTxMON ALERT0
2 R/W 0x0000
0x19 RSx+MON ALERT0 2 R/W 0x0000
0x1A INTLIMITx and
AVss/AVDD ALERT0
2 R/W 0x0000
1 N/A means not applicable.
2 Not a physical register.
VINx ALERT0 Register (Register 0x12)
This 16-bit register allows routing of the VINx generated alerts
to the ALERT0 pin.
Temperature Sensor (TSENSEx) ALERT0 Register
(Register 0x14)
This 16-bit register allows routing of the temperature sensor
generated alerts to the ALERT0 pin.
Current Sensor (ISENSEx) ALERT0 Register (Register 0x15)
This 16-bit register allows routing of the current sensor
generated alerts to the ALERT0 pin.
Supply and BI-VOUTxMON ALERT0 Register (Register 0x18)
This 16-bit register allows routing of the supply channels and
the bipolar DAC monitor channels generated alerts to the
ALERT0 pin.
RSx+MON ALERT0 Register (Register 0x19)
This 16-bit register allows routing of the RSx+MON alerts to the
ALERT0 pin.
INTLIMITx and AVss/AVDD ALERT0 Register (Register 0x1A)
This 16-bit register allows routing of the closed-loop integrator
limit and AVSS/AVDD alerts to the ALERT0 pin.
Table 99. VINx ALERT0 Register (Register 0x12)
Bit Number(s) Bit Name Description
[D15:D12] Reserved Reserved
D11 VIN3 high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT0 pin
D10 VIN2 high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT0 pin
D9
V
IN
1 high
0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT0 pin
D8 VIN0 high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT0 pin
[D7:D4] Reserved Reserved
D3 VIN3 low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT0 pin
D2 VIN2 low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT0 pin
D1 VIN1 low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT0 pin
D0
V
IN
0 low
0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT0 pin
AD7293 Data Sheet
Rev. D | Page 64 of 79
Table 100. Temperature Sensor ALERT0 Register (Register 0x14)
Bit Number(s) Bit Name Description
[D15:D11] Reserved Reserved
D10
T
SENSE
D1 high
0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT0 pin
D9 TSENSED0 high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT0 pin
D8 TSENSEINT high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT0 pin
[D7:D3] Reserved Reserved
D2 TSENSED1 low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT0 pin
D1 TSENSED0 low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT0 pin
D0
T
SENSE
INT low
0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT0 pin
Table 101. Current Sensor ALERT0 Register (Register 0x15)
Bit Number(s) Bit Name Description
[D15:D12] Reserved Reserved
D11 ISENSE3 high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT0 pin
D10
I
SENSE
2 high
0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT0 pin
D9 ISENSE1 high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT0 pin
D8 ISENSE0 high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT0 pin
[D7:D4] Reserved Reserved
D3 ISENSE3 low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT0 pin
D2 ISENSE2 low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT0 pin
D1 ISENSE1 low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT0 pin
D0 ISENSE0 low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT0 pin
Data Sheet AD7293
Rev. D | Page 65 of 79
Table 102. Supply and BI-VOUTxMON ALERT0 Register (Register 0x18)
Bit Number(s) Bit Name Description
D15 BI-VOUT3MON high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT0 pin
D14 BI-VOUT2MON high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT0 pin
D13 BI-VOUT1MON high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT0 pin
D12 BI-VOUT0MON high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT0 pin
D11 AVSS high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT0 pin
D10 DACVDD-BI high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT0 pin
D9 DACVDD-UNI high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT0 pin
D8 AVDD high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT0 pin
D7 BI-VOUT3MON low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT0 pin
D6 BI-VOUT2MON low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT0 pin
D5 BI-VOUT1MON low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT0 pin
D4 BI-VOUT0MON low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT0 pin
D3 AVSS low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT0 pin
D2 DACVDD-BI low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT0 pin
D1 DACVDD-UNI low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT0 pin
D0 AVDD low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT0 pin
AD7293 Data Sheet
Rev. D | Page 66 of 79
Table 103. RSx+MON ALERT0 Register (Register 0x19)
Bit Number(s) Bit Name Description
[D15:D12] Reserved Reserved
D11
RS3+
MON
high
0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT0 pin
D10 RS2+MON high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT0 pin
D9 RS1+MON high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT0 pin
D8 RS0+MON high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT0 pin
[D7:D4] Reserved Reserved
D3 RS3+MON low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT0 pin
D2
RS2+
MON
low
0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT0 pin
D1 RS1+MON low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT0 pin
D0 RS0+MON low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT0 pin
Table 104. INTLIMITx and AVss/AVDD ALERT0 Register (Register 0x1A)
Bit Number(s) Bit Name Description
[D15:D12] Reserved Reserved
D11 INTLIMIT3 0: no routing (default)
1: integrator limit active status routed to the ALERT0 pin
D10 INTLIMIT2 0: no routing (default)
1: integrator limit active status routed to the ALERT0 pin
D9 INTLIMIT1 0: no routing (default)
1: integrator limit active status routed to the ALERT0 pin
D8 INTLIMIT0 0: no routing (default)
1: integrator limit active status routed to the ALERT0 pin
[D7:D1] Reserved Reserved
D0 AVSS/AVDD 0: no routing (default)
1: AVSS or AVDD alarm is routed to the ALERT0 pin
Data Sheet AD7293
Rev. D | Page 67 of 79
ALERT1 PIN ROUTING (PAGE 0x12)
All the registers from this page allow routing of the alert signals
generated by the corresponding inputs/channels to the GPIO4/
ALERT1 pin of the device. The upper byte controls the high
alerts routing, whereas the lower byte controls the low alerts
routing.
Table 105. ALERT1 Pin Routing (Page 0x12)
Address
(Hex)
Name
Byte
1
Access
Type
1
Default
Value
1
0x00
No op
N/A
N/A
0x00
0x01 Page select
pointer
1 R/W 0x00
0x02 Conversion
command2
1 W N/A
0x03 Result 2 R 0x0000
0x04
DAC enable
1
R/W
0x00
0x05 GPIO 1 R/W 0x00
0x0C Device ID 2 R 0x0018
0x0F Software reset 2 R/W 0x0000
0x12 VINx ALERT1 2 R/W 0x0000
0x14 TSENSEx ALERT1 2 R/W 0x0000
0x15 ISENSEx ALERT1 2 R/W 0x0000
0x18 Supply and
BI-VOUTxMON
ALERT1
2 R/W 0x0000
0x19 RSx+MON ALERT1 2 R/W 0x0000
0x1A
INT
LIMIT
x and
AVss/AVDD
ALERT1
2
R/W
0x0000
1 N/A means not applicable.
2 Not a physical register.
VINx ALERT1 Register (Register 0x12)
This 16-bit register allows routing of the VINx generated alerts
to the ALERT1 pin.
Temperature Sensor (TSENSEx) ALERT1 Register
(Register 0x14)
This 16-bit register allows routing of the temperature sensor
generated alerts to the ALERT1 pin.
Current Sensor (ISENSEx) ALERT1 Register (Register 0x15)
This 16-bit register allows routing of the current sensor
generated alerts to the ALERT1 pin.
Supply and BI-VOUTxMON ALERT1 Register (Register 0x18)
This 16-bit register allows routing of the supply channels and
the bipolar DAC monitor channels generated alerts to the
ALERT1 pin.
RSx+MON ALERT1 Register (Register 0x19)
This 16-bit register allows routing of the RSx+MON alerts to the
ALERT1 pin.
INTLIMITx and AVSS/AVDD ALERT1 Register (Register 0x1A)
This 16-bit register allows routing of the closed-loop integrator
limit and AVSS/AVDD alerts to the ALERT1 pin.
Table 106. VINx ALERT1 Register (Register 0x12)
Bit Number(s) Bit Name Description
[D15:D12] Reserved Reserved
D11 VIN3 high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT1 pin
D10 VIN2 high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT1 pin
D9
V
IN
1 high
0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT1 pin
D8 VIN0 high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT1 pin
[D7:D4] Reserved Reserved
D3 VIN3 low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT1 pin
D2 VIN2 low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT1 pin
D1 VIN1 low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT1 pin
D0
V
IN
0 low
0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT1 pin
AD7293 Data Sheet
Rev. D | Page 68 of 79
Table 107. Temperature Sensor ALERT1 Register (Register 0x14)
Bit Number(s) Bit Name Description
[D15:D11] Reserved Reserved
D10
T
SENSE
D1 high
0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT1 pin
D9 TSENSED0 high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT1 pin.
D8 TSENSEINT high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT1 pin.
[D7:D3] Reserved Reserved
D2 TSENSED1 low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT1 pin
D1 TSENSED0 low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT1 pin
D0
T
SENSE
INT low
0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT1 pin
Table 108. Current Sensor ALERT1 Register (Register 0x15)
Bit Number(s) Bit Name Description
[D15:D12] Reserved Reserved
D11 ISENSE3 high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT1 pin
D10
I
SENSE
2 high
0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT1 pin
D9 ISENSE1 high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT1 pin
D8 ISENSE0 high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT1 pin
[D7:D4] Reserved Reserved
D3 ISENSE3 low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT1 pin
D2 ISENSE2 low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT1 pin
D1 ISENSE1 low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT1 pin
D0 ISENSE0 low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT1 pin
Table 109. Supply and BI-VOUTxMON ALERT1 Register (Register 0x18)
Bit Number(s) Bit Name Description
D15 BI-VOUT3MON high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT1 pin
D14 BI-VOUT2MON high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT1 pin
D13
BI-V
OUT
1
MON
high
0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT1 pin
D12 BI-VOUT0MON high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT1 pin
D11 AVSS high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT1 pin
Data Sheet AD7293
Rev. D | Page 69 of 79
Bit Number(s) Bit Name Description
D10 DACVDD-BI high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT1 pin
D9 DACVDD-UNI high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT1 pin
D8 AVDD high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT1 pi.
D7 BI-VOUT3MON low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT1 pin
D6 BI-VOUT2MON low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT1 pin
D5 BI-VOUT1MON low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT1 pin
D4 BI-VOUT0MON low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT1 pin
D3 AVSS low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT1 pin
D2 DACVDD-BI low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT1 pin
D1
DACV
DD-UNI
low
0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT1 pin
D0 AVDD low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT1 pin
Table 110. RSx+MON ALERT1 Register (Register 0x19)
Bit Number(s) Bit Name Description
[D15:D12] Reserved Reserved
D11 RS3+MON high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT1 pin
D10 RS2+MON high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT1 pin
D9 RS1+MON high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT1 pin
D8 RS0+MON high 0: no routing (default)
1: high alert on the corresponding channel routes to the ALERT1 pin
[D7:D4] Reserved Reserved (default)
D3
RS3+
MON
low
0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT1 pin
D2 RS2+MON low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT1 pin
D1 RS1+MON low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT1 pin
D0 RS0+MON low 0: no routing (default)
1: low alert on the corresponding channel routes to the ALERT1 pin
AD7293 Data Sheet
Rev. D | Page 70 of 79
Table 111. INTLIMITx and AVss/AVDD ALERT1 Register (Register 0x1A)
Bit Number(s) Bit Name Description
[D15:D12] Reserved Reserved
D11
INT
LIMIT
3
0: no routing (default)
1: integrator limit active status routed to the ALERT1 pin
D10 INTLIMIT2 0: no routing (default)
1: integrator limit active status routed to the ALERT1 pin
D9 INTLIMIT1 0: no routing (default)
1: integrator limit active status routed to the ALERT1 pin
D8 INTLIMIT0 0: no routing (default)
1: integrator limit active status routed to the ALERT1 pin
[D7:D1] Reserved Reserved
D0 AVSS/AVDD 0: no routing (default)
1: AVSS or AVDD alarm is routed to the ALERT1 pin
Data Sheet AD7293
Rev. D | Page 71 of 79
SERIAL PORT INTERFACE
The AD7293 SPI allows the user to configure the device for
specific functions and operations through an internal structured
register space. The interface consists of four signals: CS, SCLK,
DIN, and DOUT. The device is capable of interfacing within a
range of 1.7 V to 5.5 V, which is set by the VDRIVE pin. SCLK is the
serial clock input for the device. All data transfers on DIN or
DOUT take place with respect to SCLK. The chip select input
pin (CS) is an active low control. For the interface to be active,
the chip select must be low. Data is clocked into the AD7293 on
the SCLK rising edge and is loaded into the device MSB first.
The length of each SPI frame can vary according to the command
being sent. A no op command is available for interface flexibil-
ity. Data is clocked out of the AD7293 on DOUT in the same
frame as the read command, on the falling edge of SCLK,
while CS is low. The SCLK and DIN signals are ignored
when CS is high, and the DOUT line becomes high impedance.
INTERFACE PROTOCOL
When reading from or writing to the AD7293, the first byte
contains the address pointer. Bit D7 of the address pointer is the
read (high) and write (low) bit.
Table 112. Address Pointer
D7 D6 D5 D4 D3 D2 D1 D0
R/W X1 Register/page select
1 X means don’t care.
Bit D5 to Bit D0 of the address pointer specify the register
address for the read or write operation.
After the address pointer, the data to be written to the device is
supplied in bytes. The register structure of the AD7293 is page
based and divided according to their specific functions. Some
registers are common to all pages, whereas the rest of the
registers are contained within a particular page. To s el ect a
page, write to the 8-bit page select register. When a particular
page is selected, the user does not have to rewrite to the page
select register every time prior to writing to a register from the
same page. Figure 52 to Figure 54 show the read and write data
formats for the AD7293.
For a register write, the read/write bit is zero, and the DOUT
line remains high impedance. Upon completion of a read or
write, the AD7293 is ready to accept a new register address;
alternatively, to terminate the operation, take the CS pin high.
PAGE NUM BE R[ D7: D0]PAGE SELECT[D5:D0]
DIN
DOUT
0 X
CS
NOTES
1. R/W IS CLEARED WHEN WRITING TO THE PAGE SELECT REGISTER.
2. T HE ADDRE S S OF THE P AGE SE LECT REGIS TER IS 0x01.
3. X = DON’ T CARE.
13016-051
Figure 52. Accessing a Page
REG ADDRE S S [ D5: D0]XR/W NO OP( 0x00) [ D7: D0]
DOUT[D7:D0]
DIN
DOUT
CS
NOTES
1. R/ W I S S E T W HE N RE ADING FRO M A RE GI S TER AND CL E ARE D WHEN
WRITING TO A REGISTER.
2. X = DON’ T CARE.
13016-052
Figure 53. Accessing an 8-Bit Register
DIN
DOUT
CS
NOTES
1. R/ W I S S E T W HE N RE ADING FRO M A RE GI S TER AND CL E ARE D WHEN
WRITING TO A REGISTER.
2. X = DON’ T CARE.
REG ADDRE S S [ D5: D0] DIN[D15:D8] DIN[D7:D0]
DOUT[D15:D0]
1
XR/W
13016-053
Figure 54. Accessing a 16-Bit Register
AD7293 Data Sheet
Rev. D | Page 72 of 79
MODES OF OPERTION
There are two methods of initiating a conversion on the
AD7293: background mode and command mode.
Background Mode (BG)
The AD7293 can be configured to continuously convert on a
programmable cycle of channels, making it the ideal mode of
operation for system monitoring. These conversions take place
in the background and are transparent to the master. Typically,
this mode is used to automatically monitor a selection of channels
with either the limit registers programmed to signal an out of
range condition via the alert function or with the minimum/
maximum recorders tracking the variation over time of a
particular channel. Reads and writes can be performed at any
time during this mode (the result registers contains the most
recent conversion results).
On power-up, this mode is disabled. This mode can be enabled
by writing to the background enable bits (VINx background enable
register; temperature sensor background enable register; current
sensor background enable register; and the RS+MON, supply
monitor, and BI-VOUTx background enable register) from the
configuration page. The background conversions are active only
when CS is pulled high, that is, the interface is not active.
When CS is pulled low, the conversions pauses and resumes
from the last channel in the cycle when CS is pulled high again.
The user can read back the conversion results via the channel
specific result registers.
If a command mode conversion is requested while the background
mode is active, the scheduled background mode conversion from
the cycle pauses while CS is low and tags onto the command mode
conversion. Conversion is reflected in the ADC busy signal, which
stays true for the combined duration of the command mode
conversion and the background mode.
If the background conversions are enabled during the closed-
loop mode operation, they run continuously irrespective of CS
status. However, the results of the ADC conversions are only
stored if CS is pulled high.
The ADC background cycle prioritizes in the following order:
VIN0 to VIN3, TSENSEINT, TSENSED0, TSENSED1, ISENSE0 to ISENSE3,
voltage supply monitoring, BI-VOUT0MON to BI-VOUT3MON, and
RS0+MON to RS3+MON.
Command Mode
Command mode is useful for controlling the sampling instant
on the VINx channels if an ac waveform is being converted. To
enter this mode and initiate a conversion on a channel, the
special command byte, 0x82, must be written to the device.
When the conversion command is received, the AD7293 uses
the current values in the registers on the sequence page to
determine which channel to convert on and subsequently read
back from. The common result register is updated with the
result of the current conversion channel, which allows the user
to continuously read back the conversion results in command
mode. The ADC command mode sequencer prioritizes in this
order: VIN0 to VIN3, TSENSEI NT, TSENSED0, TSENSED1, ISENSE0 to
ISENSE3, voltage supply monitoring, BI-VOUT0MON to BI-VOUT3MON,
and RS0+MON to RS3+MON. The sequencer can be reset by writing
to any of the sequence registers.
In the example in Figure 55, to initiate the continuous conversion
command mode, point to the sequence page and write to the
relevant sequence registers. The ADC sequence register is
programmed to convert on analog input channels, VIN0 to VIN2,
in this example. The first conversion takes place when the AD7293
enters command mode after the special command byte. Every
subsequent conversion is initiated after the result readback
frame, as shown in Figure 55.
Figure 56 shows another example for a command mode conver-
sion with a fixed 24-bit SPI frame length. The first conversion is
initiated when the device enters the command mode after the
special command byte, which is followed by a 24-bit readback
of the conversion result. The device exits command mode
when CS is pulled high, although the sequencer is not reset.
Every subsequent conversion is initiated by reentering the
command mode via the special command byte after which the
user must wait long enough to allow the device to finish any
conversions before reading back the next result.
Current Sensor and Temperature Sensor Conversions
Conversions on the temperature and current sensor channels
can be enabled only via one set of registers, TSENSEx background
enable and ISENSEx background enable, respectively, unlike the
other channels, because the current sense and temperature
sense amplifiers work by integrating the input voltage for a
fixed amount of time, depending on the gain required. At the
end of this integration period, a request is sent to the ADC for a
conversion to be performed. The ADC deals with these requests
in the order in which they arrive. For the other channels, the
ADC starts converting immediately. The corresponding sequence
register for these channels is used only to put the temperature
and current sensor results in the command mode readback
sequence and not to enable conversions on these channels.
Data Sheet AD7293
Rev. D | Page 73 of 79
1 8 16 24
WRI T E T O ADC SEQUENCE REGI S TER
24 32 40 48 56 1816
READ FRO M ADC DATA REGI S TER CONVERS IO N COM MAND
PREVIOUS CONVERSIO N RESULT CONVE RSIO N RE SULT FOR VIN0 D15:D0
CONVERT
VIN0
16 1 8 16 1816
CONVE RSIO N RE SULT FOR VIN1 D15:D0 CONVERS IO N RES ULT FOR VIN2 D15:D0
CONVERT
VIN1CONVERT
VIN2
DIN
SCLK
DOUT
BUSY
CS
DIN
SCLK
DOUT
BUSY
CS
DIN
SCLK
DOUT
BUSY
CS
13016-054
Figure 55. Continuous Conversion Command Mode Example
1 8 16 24 1 8 16 24
0 X 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 X 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
18 16 24 1 8 16 24
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 X 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0000 0 0 0
b11 b10 b9 b8b7b6 b5 b4 b3 b2 b1 b0 X X X X
1 8 16 24 1 8 16 24
0 0 0 0 0 0 0 0 0000 0 0 0 0 1 0 0 0 0 0 1 0 1 X 0000 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 X X X X
PAGE SELECT POI NTER SEQUENCE PAGE NO OP ADC SEQUENCE
REGISTE R W RITE VIN3 VIN2 VIN1 VIN0 SELECT ED
NO OPNO OP CONVERSIO N COM MAND RES ULT REGI ST ER READ NO OP NO OP
NO OPNO OP CONVE RSIO N COM MAND RES ULT REGI S TER READ NO OP NO OP
VIN0 RESULT
VIN1 RESULT
DIN
SCLK
CS
DIN
DOUT
SCLK
CS
DOUT
DIN
SCLK
CS
DOUT
13016-055
Figure 56. Command Mode Read Example (24-Bit Fixed Frame, CS Taken High After Each Conversion)
Conversion Timing
Table 113 shows the approximate conversion times for each type
of channel under nominal conditions. Note that the temperature
and current sensor channels, when enabled, are background
conversions that are added on in command mode because the
integration/sense times are greater than other ADC reads.
Table 113. Typical Conversion Time
Channel Command Mode Background Mode (µs)
VINx 0.7 µs 2.3
ISENSEx Not applicable 4.2
TSENSEx Not applicable 2.3
Monitor 4.0 µs 4.0
Current Sense and Temperature Sense Channel
Integration Time
The internal current sense and temperature sense amplifiers
function by integrating the input voltage for a fixed amount of
time depending on the gain required. At the end of the integration
period, a request is sent to the ADC for a conversion to be
performed. The ADC deals with these requests in the order in
which they arrive.
AD7293 Data Sheet
Rev. D | Page 74 of 79
Table 114. Current Sensor Integration Time
Code Gain Clocks Typical Integration Time (µs)
0000 6.25 440 17.6
0001 12.5 650 26.0
0010 18.75 860 34.4
0011 25 1070 42.8
0100 37.5 1490 59.6
0101 50 1910 76.4
0110 75 2750 110.0
0111 100 3590 143.6
1000 200 6950 278.0
1001
400
13670
546.8
1010 781.25 26480 1059.2
Table 115. Temperature Sensor Integration time
Channel Clocks Typical Integration Time (µs)
TSENSEINT 30523 1220.92
TSENSED0 60987 2439.48
TSENSED1 60987 2439.48
Each current sense channel has its own integrator, whereas
there is only one integrator for all three temperature channels.
Therefore, temperature inputs that are enabled are measured
sequentially. This means that, for example, if all are enabled, the
update time is (1220.92 µs + 2 × 2439.48 µs) = 6099.88 µs
Conversion and Integration Timing Example 1
Enable three of the current sense channels with a gain of 6.25.
All three integrations start as soon as the enable register is
written to. After 17.6 µs, all three voltages are ready to be
converted by the ADC. The ISENSE0 channel is converted first,
while the ISENSE1 channel and the ISENSE2 channel are held in the
queue. After the ISENSE0 conversion is complete, the ISENSE0
amplifier is released to start a new integration, and the ADC
moves on to convert the ISENSE1 voltage.
The AD7293 settles into a routine, converting the three ISENSEx
channels, each with an update time of (17.6 µs + 4.2 µs) = 21.8 µs.
See Figure 57 for more details.
Conversion and Integration Timing Example 2
In this example, in addition to the three current sense channels,
three monitor channels are also enabled, as shown in Figure 58.
The ADC is busy all the time; therefore, the time it takes to
complete a cycle of conversions is the sum of all the conversion
times: (4.2 µs × 3 + 4.0 µs × 3) = 24.6 µs.
If the temperature sensor is also enabled, when the output of the
temperature sensor is ready (once every 1 ms to 2 ms depending
on which channels are selected), the ADC sequencer waits for
its turn in the sequence before initiating a conversion on the
particular TSENSEx channel. The combination of conversions
increases the duration of that particular cycle from 24.6 µs to
(24.6 µs + 2.3 µs) = 26.9 µs in this example.
Digital Filtering
A digital filter is available on the ADC channels. The digital
filter consists of a simple low-pass filter function to help reduce
unwanted noise on dc signals. This low-pass filter has a −3 dB
cutoff frequency of
400642
SS
3dB
ff
f≈
×
=
−
π
where fS is the sample frequency. The sample frequency depends
on the type of channel, how many other channels are enabled,
and whether it is in background mode or command mode (for
example, if the internal temperature sensor channel is enabled
alone, the update period is 1220.92 µs typically, which is close to
fS ≈ 819 Hz). If VIN0, VIN1, VIN2, and VIN3 are also enabled in
background mode, a conversion then takes place on VIN0 every
9.2 µs (2.3 µs × 4), meaning fS ≈ 1 ÷ 9.2 µs ≈ 108.7 kHz. To
avoid aliasing of high frequencies at the input, use an antialias
filter to reject input frequencies above fS/2.
Data Sheet AD7293
Rev. D | Page 75 of 79
13016-056
012012012012
I
SENSE
x
ENABLE
I
SENSE
0
INTEGRATOR OUT
I
SENSE
1
INTEGRATOR OUT
I
SENSE
0
READY
I
SENSE
1
READY
I
SENSE
2
INTEGRATOR OUT
I
SENSE
2
READY
ADC BUSY
17.6µs
21.8µs
4.2µs
Figure 57. Conversation and Integration Internal Timing Example 1
13016-057
I0 I1 I2
V0 V1 V2 I0 I1 I2V0 V1 V2 I0 I1 I2
V0 V1 V2 I0 I1 I2
V0 V1 V2
I
SENSE
x
ENABLE
I
SENSE
0
INTEGRATOR OUT
I
SENSE
0
READY
I
SENSE
1
READY
I
SENSE
2
READY
ADC BUSY
I
SENSE
1
INTEGRATOR OUT
I
SENSE
2
INTEGRATOR OUT
V
IN
x
ENABLE
I
SENSE
0
INTEGRATION
I
SENSE
0
CONVERSION
24.6µs
Figure 58. Conversion and Integration Internal Timing Example 2
AD7293 Data Sheet
Rev. D | Page 76 of 79
APPLICATIONS INFORMATION
The AD7293 contains all the functions required for general-
purpose monitoring and control of current, voltage, and
temperature. With its 60 V maximum common-mode range,
the device is useful in applications where current sensing in the
presence of a high common-mode voltage is required. Closed-
loop mode is designed for monitoring and controlling, for
example, the power amplifier in a cellular base station.
BASE STATION POWER AMPLIFIER CONTROL
The AD7293 is used in a signal chain to achieve the optimal
bias conditioning for enhancement mode or depletion mode
power amplifiers. The main factors influencing the bias
conditions are temperature, supply voltage, gate voltage drift,
and general processing parameters. The overall performance of
a power amplifier configuration is determined by the inherent
trade-offs required in efficiency, gain, and linearity. The high
level of integration as well as the intelligent features offered by
the AD7293 allows the use of a single chip to dynamically
control the drain bias current to maintain a constant value over
temperature and time, thus significantly improving the overall
performance of the power amplifier. The AD7293 incorporates
the functionality of eight discrete components, providing
considerable board area savings over discrete solutions.
The circuit shown in Figure 59 is the typical power amplifier
control application diagram for the AD7293. The device
monitors and controls the overall performance of four final
stage amplifiers. The gain control and phase adjustment of the
driver stage are incorporated in the application and are carried
out by the four available uncommitted outputs of the AD7293.
The high-side current sensor measures the amount of current
on the respective final stage amplifiers while the closed-loop
system maintains the programmed current across the sense
resistor. Furthermore, the PA_ON provides optional control for
a cutoff switch on the supply. The ALERTx pins can be configured
to trigger when current readings are more than a specified limit
and the RF input signal can be switched off by the ALERTx pin.
The alert feature can also be routed internally to clamp the DAC
outputs and turn off the power.
By measuring the transmitted (Tx) power and the received (Rx)
power, the device can dynamically change the drivers and PA
signal to optimize performance.
Data Sheet AD7293
Rev. D | Page 77 of 79
TEMPERATURE
SENSOR
AV
DD
DGND
AGND
V
DRIVE
GPIO0/IS BLANK
GPIO1/CONVST
GPIO2/BUSY
V
IN
0
V
IN
1
V
IN
2
V
IN
3
UNI-V
OUT
0
UNI-V
OUT
1
UNI-V
OUT
2
UNI-V
OUT
3
V
CLAMP
0
DAC
CLAMP
CONTROL V
CLAMP
1
BI-V
OUT
3
BI-V
OUT
2
BI-V
OUT
1
BI-V
OUT
0
DOUT
DIN
SCLK
CS
AV
SS
DACV
DD-UNI
DV
DD
V
REFOUT
REF
ADC
GPIO3/ALERT0
RESET
MUX
PAV
DD
PA_ON
GPIO4/ALERT1
GPIO5/SLEEP0
GPIO6/SLEEP1
GPIO7/LDAC
FACTORY TEST
V
REFIN
1
D1–
D0–
D1+
D0+
DACV
DD-BI
BIPOLAR
DAC
UNIPOLAR
DAC
UNIPOLAR
DAC
UNIPOLAR
DAC
UNIPOLAR
DAC
1
2
×
1.25V
RS3–
RS3+
RS2–
RS2+
RS1–
RS1+
–
–
+
+
BIPOLAR
DAC
BIPOLAR
DAC
BIPOLAR
DAC
RS0–
RS0+
2.5V
PMOS
CONTROL
SPI
INTERFACE DIGITALI/Os
ALE RT AND LIMIT
REGISTERS
CONTROL
LOGIC
12-BIT
SAR ADC
1
AD7293
RESET
LOGIC
BI-V
OUT
0
MON
BI-V
OUT
1
MON
BI-V
OUT
2
MON
BI-V
OUT
3
MON
FILTER
RFOUT
GaN
RFIN
R
SENSE
FILTER
RFOUT
GaN
RFIN
R
SENSE
FILTER
RFOUT
GaN
RFIN
R
SENSE
FILTER
RFOUT
GaN
RFIN
R
SENSE
V
PP
GAIN
CONTROL
GAIN
CONTROL
GAIN
CONTROL
GAIN
CONTROL
Rx POWER
MONITOR
Tx POWER
MONITOR
PRECISION
2.5V
REFERENCE
–
+
–
+
13016-059
Figure 59. Typical Power Amplifier Control Application
DEPLETION MODE AMPLIFIER BIASING AND
PROTECTION
Depletion mode devices (for example, gallium nitride (GaN) or
gallium arsenide (GaAs)) require temperature compensated
gate biasing voltages similar to enhancement mode devices (for
example, laterally diffused metal oxide semiconductor (LDMOS))
to maintain constant quiescent drain current with temperature.
The most important consideration for a depletion mode device
is the biasing sequence. If the gate of a depletion mode device is
at 0 V and the drain voltage is applied, the device may be
damaged by drawing excessive current. It is also likely that a
device may become potentially unstable at lower drain source
voltages. Therefore, decreasing the gate voltage to less than the
pinch off voltage while the drain voltage is being powered on
and off is necessary.
The AD7293 was designed for depletion mode power amplifier
biasing. Bipolar DAC outputs enable negative voltage biasing of
the gate on the depletion mode device. A closed-loop mode
combined with a low temperature drift reference ensures that
the loop is steady over temperature.
The AD7293 works to ensure that instability or destruction of
the depletion mode device is avoided. A PA_ON signal allows
the user the option to control an external PMOS switch to turn
on and off the drain current. This signal is set to the off state on
power-up. Because depletion mode devices require a negative
bias to remain at an acceptable level, and bipolar DACs transmit
on t he AVSS supply for proper operation, PA_ON can be triggered
when AVSS exceeds an acceptable level.
In the event of an AVDD voltage supply failure, the bipolar DACs
clamp to the AVSS supply (−5 V), which ensures that the PA
AD7293 Data Sheet
Rev. D | Page 78 of 79
threshold voltage is not exceeded in the event of AVDD voltage
supply failure.
The on-chip bipolar DAC clamping circuitry ensures that the
four bipolar outputs are set to their clamp value on power-up,
and the DACs can be triggered to clamp by the external SLEEPx
pins at any stage by the user.
The voltage monitoring of the supply voltages can help to
quickly detect any system issues. The bipolar DAC output
monitoring can be useful in closed-loop mode to sense the
voltage output controlling the PA gate. Monitoring of the RSx+
pins voltages helps in detecting issues on the high side of the
sense resistor.
To adhere to radio standards, it may be necessary to control the
rate at which the PA gain changes. A ramp register is available
that allows the user to control the slew rate of the DAC in
closed-loop mode. Additionally, a closed-loop sequence is
provided in the Closed-Loop Sequencing section to ensure the
protection of the power amplifier from an overvoltage.
LOOP COMPONENT SELECTION
To select the loop component, use the following conditions:
RS ≤ 0.2/IDS(MAX)
RS ≤ τI/(52.5 µs × gm(MAX))
τG ≤ τI/(25 × gm(MAX) × RS)
τS ≤ (1/10) × τG
where:
RS is the value of the current sense resistor in ohms.
IDS(MAX) is the PA drain current at the maximum required PA
gain in amperes.
τI is the integrator time constant (default value = 840 s) in
seconds.
gm(MAX) is the PA transconductance at the maximum required PA
gain in Siemens.
τG is the gate filter time constant in seconds.
τS is the current sense filter time constant in seconds.
To optimize the loop response from this point, the RS, τI, τG, and
τS values can be adjusted (see Table 116).
Table 116. RS, τI, τG, and τS Adjustment Values
Parameter Benefit of Increasing Benefit of Decreasing
RS Setpoint resolution
increased, improved
dynamic range, and
faster settling
Reduced overshoot,
reduced power
dissipation, and allows
higher τG and τS
τI Reduced overshoot,
allows higher τG and τS
Faster settling
τG Reduced noise from
current control loop
Reduced overshoot,
allows lower τI
τS Improved filtering of
disturbances at current
sense input
Reduced overshoot,
allows lower τI
When setting τG, do not exceed the maximum load capacitance
specification (10 nF when RG = 0 , and 1 µF when RG = 5 ).
Include the PA gate capacitance in the calculation.
13016-060
τ
S
τ
G
τ
I
VPP
AD7293
RSx+
RSx–
DAC
BI-VOUTx
RS
Figure 60. Loop Component Selection and Filtering
Data Sheet AD7293
Rev. D | Page 79 of 79
OUTLINE DIMENSIONS
0.50
BSC
BOTTOM VIEW
TOP VIEW
PIN 1
INDICATOR
*5.90
5.80 SQ
5.70
0.50
0.40
0.30
0.80
0.75
0.70 0. 05 MAX
0.02 NO M
0.203 REF
COPLANARITY
0.08
0.30
0.25
0.20
10-27-2017-A
8.10
8.00 SQ
7.90
0.20 M IN
6.50 REF
*COM P LIANT T O JEDE C S TANDARDS MO-220- WL LD-2
WIT H EXCEPTIO N TO EXPO SED PAD DIMENSION.
1
56
14
15
43
42
28
29
EXPOSED
PAD
PKG-004097
SEATING
PLANE
PIN 1
INDIC ATOR AREA O P TIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
FOR PRO P E R CONNECTI O N OF
THE EXPOSED PAD, REFER TO
THE PIN CO NFI GURAT ION AND
FUNCTION DES CRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 61. 56-Lead Lead Frame Chip Scale Package [LFCSP]
8 mm × 8 mm Body and 0.75 mm Package Height
(CP-56-8)
Dimensions Shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD7293BCPZ −40°C to +125°C 56-Lead Lead Frame Chip Scale Package [LFCSP] CP-56-8
AD7293BCPZ-RL −40°C to +125°C 56-Lead Lead Frame Chip Scale Package [LFCSP] CP-56-8
EVAL-AD7293SDZ Evaluation Control Board
EVAL-SDP-CB1Z Controller Board
1 Z = RoHS Compliant Part.
©2016–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13016-0-8/18(D)