Z9308 Zero Delay Clock Buffer Preliminary Product Features Product Description * * * * * * * * The Z9308 and the dash number derivatives are 3.3V zero delay buffers designed to distribute high-speed clocks in the PC, workstation, datacom, telecom, and other high-performance applications. Zero Delay 8-Output Buffer High Frequency Operation (150 MHz) Low Jitter < + 100 pS Low Skew <250 pS Externally Controllable Output Delay 45 -55% Output Duty Cycle 16 pin SOIC and TSSOP Packages >2000 V ESD HBM The Z9308 has two banks of four outputs each, which can be controlled by the Select inputs as shown in the table 1. The Z9308 is available in several logic configurations (-1,-2,-3,-4) shown in the Configurations Table of this datasheet. Select Input Functionality S2 0 0 S1 CLKA1- CLKB1- A4 B4 (1) (1) OFF (1) ON PLL OFF (Bypassed) ON 0 Tri-State 1 2 Tri-State 2 2 Driven 1 0 Driven 1 1 Driven Tri-State Driven 2 PLL 2 Driven Table 1 Note 1: Outputs have weak pulldowns Note 2: See Configuration Table, pg. 2, for actual output vs. REF relationship. Block Diagram Pin Configuration (-3, -4 versions only) FBK REF /2 PLL CLKA1 CLKA2 CLKA3 S2 S1 CLKA4 Select Input Decoding /2 CLKB1 REF CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 FBK CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1 (-2, -3 versions only) CLKB2 CLKB3 CLKB4 INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.3 3/9/00 Page 1 of 10 Z9308 Zero Delay Clock Buffer Preliminary Z9308 Configurations Device Feedback From Bank A Frequency Bank B Frequency Z9308-1 Bank A or Bank B Reference Reference Z9308-2 Bank A Reference Reference/2 Bank B 2X Ref. Reference Z9308-3 Bank A 2X Ref. Reference Bank B 4X Ref. 2X Ref. Z9308-4 Bank A or Bank B 2X Ref. 2X Ref. Pin Description PIN No. Pin Name I/O Description (1) 1 REF I Input reference frequency, 5.0 V tolerant input. 2 CLKA1 O Clock Output, Bank A. 3 CLKA2 O Clock Output, Bank A. 4 VDD I 3.3 V Supply 5 GND I Ground 6 CLKB1 O Clock Output, Bank B. 7 CLKB2 O Clock Output, Bank B. 8 S2 I Select Input pin, bit 2. 9 S1 I Select Input pin, bit 1 10 CLKB3 O Clock Output, Bank B. 11 CLKB4 O Clock Output, Bank B. 12 GND Ground 13 VDD 3.3V supply 14 CLKA3 O Clock Output, Bank A. 15 CLKA4 O Clock Output, Bank A. 16 FBK I PLL feedback input. Note 1: Includes internal week pull-downs. Maximum Ratings Voltage Relative to VSS: -0.5V Voltage Relative to VDD: Storage Temperature: Operating Temperature: 0.5V o o -65 C to + 150 C o o 0 C to +85 C Maximum Power Supply: 7V Reference Input Voltage: -.5 to 7V This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS<(Vin or Vout)<VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.3 3/9/00 Page 2 of 10 Z9308 Zero Delay Clock Buffer Preliminary Operating Conditions Parameter VDD Description Min. Supply Voltage Max. 3.0 Unit 3.6 V TA Operating Temperature (Ambient Temperature 85 o Cout Output Capacitance 10 pF CIN Input Capacitance 7 pF CL Load Capacitance 30 pF 0 C DC Electrical Characteristics Parameters Symbol Min VIL - - VIH 2.0 - Input Low Current IIL1 - Input High Current IIH1 - (1) Input Low Voltage (1) Input High Voltage 2 Output Low Voltage 2 Output High Voltage Tri-State leakage Current Dynamic Supply Current Typ - VOL VOH (3) Ioz Idd Max 0.8 Units Conditions Vdc Vdc - 50 A VIN = 0 V 100 A VIN = VDD 0.4 V IOL = 12 mA V IOH = - 12 mA 2.4 - - 16.5 A VO = 3.3 V - - 40 mA Unload outputs, 66.66 MHz, Select inputs at VDD or GND. Static Supply Current Isdd 50 S1 = S2 = VSS - VIN = VDD or VSS A Notes: 1. REF and FBK inputs have a threshold voltage of VDD/2. 2. Output (clock) pins have pulldown devices attached internally. 3. Weak pulldown is active when the output buffers are tri-stated. The value of this pulldown resistor is >200k <1.55 m, typically 550k. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev. 1.3 3/9/00 Page 3 of 10 Z9308 Zero Delay Clock Buffer Preliminary AAC Electrical Characteristics Parameter Output Frequency (Z9308) (1) Duty Cycle (T2/T1) Output Rise Time (1) Symbol Min t1 10 - 45 t3 (1) Typ Max Units Conditions 150 MHz 30 pF load (all devices) 50 55 % Measured @ 1.4V (-1,-2,-3,-4 devices) - 2.5 nSec Measured between 0.8V & 2.0V, 30 pF Load (-1,-2,-3,-4 devices) Output Rise Time t3 1.5 nSec Measured between 0.8V & 2.0V, 20 pF Load (-1,-2,-3,-4 devices) Output Fall Time (1) t4 2.5 nSec Measured between 0.8V & 2.0V, 30 pF Load (-1,-2,-3,-4 devices) Output Fall Time (1) t4 1.5 nSec Measured between 0.8V & 2.0V, 20 pF Load (-1,-2,-3,-4 devices) Output to Output Skew Delay, REF Rising Edge to (1) FBK Rising Edge (1) t5 - - 250 pSec All output equally loaded @ 66MHz t6 - 0 + 350 pSec Measured at VDD/2 All outputs equally loaded. t7 - 0 700 pSec Measured at VDD/2 on FBK pins of devices Cycle to Cycle Jitter (-1,-4 devices) (1) tj - - 200 pSec Measured at 66.67 MHz, loaded outputs Cycle to Cycle Jitter (-2,-3 devices) (1) tj - - 500 pSec Measured at 66.67 MHz, loaded outputs 1.0 ms Stable power supply, valid clocks presented on REF and FBK pins Device to Device Skew Maximum PLL Lock Time (1) tLOCK Notes: 1. Parameter is guaranteed by design and characterization. Not 100% tested in production. All parameters specified with equally loaded outputs, input rise/fall max 2nS. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.3 3/9/00 Page 4 of 10 Z9308 Zero Delay Clock Buffer Preliminary Switching Waveforms Duty Cycle Timing t1 t2 1.4V 1.4V 1.4V All Outputs Rise/Fall Time 2.0V Output 3.3V 2.0V 0.8V 0.8V t3 t4 0V Output-Output Skew 1.4V Output 1.4V Output t5 INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev. 1.3 3/9/00 Page 5 of 10 Z9308 Zero Delay Clock Buffer Preliminary Switching Waveforms (Cont.) Input-Output Propagation Delay V D D /2 Input V D D /2 FBK t6 Device-Device Skew V D D /2 FBK, Device 1 V D D /2 FBK, Device 2 t7 INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.3 3/9/00 Page 6 of 10 Z9308 Zero Delay Clock Buffer Preliminary Output Delay vs. Feedback Loading REF. Input to CLKA/CLKB Delay (ps) 1500 1000 500 0 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 -500 -1000 -1500 Output Load Difference: FBK Load - CLKA/CLKB Load (pF) The FBK pin can be driven from any of the 8 available output pins. The output driving the FBK pin will be driving a FBK load of 7 pF plus the additional output load. The relative loading of this output (with respect to the remaining outputs) will vary the input-output delay. This is shown in the graph above. For applications requiring zero input-output delay, all outputs including the one providing feedback should have equal loads. If input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and remaining outputs. Test Circuit Diagram VDD 0.1 uF Outputs CLK out C LOAD VDD 0.1 uF GND GND INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev. 1.3 3/9/00 Page 7 of 10 Z9308 Zero Delay Clock Buffer Preliminary Package Drawing and Dimensions 16 Pin 150 Mil SOIC Outline Dimensions INCHES SYMBOL C L MIN NOM MAX MIN NOM MAX A 0.097 0.101 0.104 2.46 2.56 2.64 A1 0.0050 0.009 0.0115 0.127 0.22 0.29 A2 0.090 0.092 0.094 2.29 2.34 2.39 B 0.014 0.016 0.019 0.35 0.41 0.48 C 0.0091 0.010 0.0125 0.23 0.25 0.32 D 0.402 0.407 0.412 10.21 10.34 10.46 E 0.150 - 0.157 3.81 - 3.988 H E a D A2 A A1 B MILLIMETERS e INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 e 0.050 BSC 1.27 BSC H 0.400 0.406 0.410 10.16 10.31 10.41 L 0.024 0.032 0.040 0.61 0.81 1.02 a 0 5 10 0 5 10 Rev.1.3 3/9/00 Page 8 of 10 Z9308 Zero Delay Clock Buffer Preliminary Package Drawings and Dimensions (Cont.) D R0.1 16 Pin TSSOP Dimensions INCHES SYMBOL E1 MIN NOM MILLIMETERS NOM MAX A - - MAX 0.0433 MIN - - 1.10 A1 0.0019 0.0039 0.0059 0.05 0.10 0.15 A2 0.0346 0.0354 0.0374 0.85 0.90 0.95 L 0.0196 0.0236 0.0275 0.50 0.60 0.75 L1 0.0354 0.0393 0.0433 0.90 1.00 1.10 R 0.0035 - - 0.09 - - b 0.0076 - 0.0108 0.195 - 0.275 b1 0.0076 0.0086 0.0096 0.195 0.22 0.245 c 0.0041 - 0.0068 0.105 - 0.175 c1 0.0041 0.0049 0.0057 0.105 0.125 0.145 0 - 8 0 - 8 BO 1.20 -B1.50 SURFACES ROUGHNESS: 6+ 27n(RZ) 4 [10 TYP R0.15 -C- 0.07 C B e e R0.15 14 TYP 1.0 0.05 MAX. 1.0 0.05 MAX. 0.026 BSC 0.65 BSC D 0.1948 0.1968 0.1988 4.95 5.0 5.05 E 0.2480 0.2519 0.2559 6.3 6.4 6.5 E1 0.1712 0.1732 0.1752 4.35 4.4 4.45 S 0.0078 - - 0.20 - - A E b .08 8 A C B A R A2 c c1 0.25 S L b1 A1 L1 DETAIL A DETAIL B INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev. 1.3 3/9/00 Page 9 of 10 Z9308 Zero Delay Clock Buffer Preliminary Ordering Information Part Number Package Type Z9308-1CZ 16 Pin SOIC Commercial, 0C to +85C Z9308-2CZ 16 Pin SOIC Commercial, 0C to +85C Z9308-3CZ 16 Pin SOIC Commercial, 0C to +85C Z9308-4CZ 16 Pin SOIC Commercial, 0C to +85C Z9308-1CT 16 Pin TSSOP Commercial, 0C to +85C Z9308-2CT 16 Pin TSSOP Commercial, 0C to +85C Z9308-3CT 16 Pin TSSOP Commercial, 0C to +85C Z9308-4CT 16 Pin TSSOP Commercial, 0C to +85C Note: Production Flow The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. Marking: Example: IMI Date Code 9308CZ Lot # 9308-1CZ Package Z = SOIC, 150 mil. T = TSSOP Revision Option IMI Device Number INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.3 3/9/00 Page 10 of 10