Z9308
Zero Delay Clock Buffer
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.3 3/9/00
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 1 of 10
PLL
REF
FBK
CLKA1
Select Input
Decoding
S2
S1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
(-3, -4 versions only)
/2
(-2, -3 versions only)
/2
Product Features
• Zero Delay 8-Output Buffer
• High Frequency Operation (150 MHz)
• Low Jitter < + 100 pS
• Low Skew <250 pS
• Externally Controllable Output Delay
• 45 –55% Output Duty Cycle
• 16 pin SOIC and TSSOP Packages
• >2000 V ESD HBM
Select Input Functionality
S2 S1 CLKA1-
A4 CLKB1-
B4 PLL
00Tri-State
(1) Tri-State(1) OFF
01 Driven
2Tri-State(1) ON
10 Driven
2Driven2PLL OFF
(Bypassed)
11 Driven
2Driven2ON
Table 1
Note 1: Outputs have weak pulldowns
Note 2: See Configuration Table, pg. 2, for actual output
vs. REF relationship.
Product Description
The Z9308 and the dash number derivatives are 3.3V
zero delay buffers designed to distribute high-speed
clocks in the PC, workstation, datacom, telecom, and
other high-performance applications.
The Z9308 has two banks of four outputs each, which
can be controlled by the Select inputs as shown in the
table 1. The Z9308 is available in several logic
configurations (-1,-2,-3,-4) shown in the Configurations
Table of this datasheet.
FBK
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
REF
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
S2
Block Dia
g
ram Pin Confi
g
uration
Z9308
Zero Delay Clock Buffer
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.3 3/9/00
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 2 of 10
Z9308 Configurations
Device Feedback From Bank A Frequency Bank B Frequency
Z9308-1 Bank A or Bank B Reference Reference
Z9308-2 Bank A Reference Reference/2
Bank B 2X Ref. Reference
Z9308-3 Bank A 2X Ref. Reference
Bank B 4X Ref. 2X Ref.
Z9308-4 Bank A or Bank B 2X Ref. 2X Ref.
Pin Description
PIN No. Pin Name I/O Description
1REF
(1) I Input reference frequency, 5.0 V tolerant input.
2 CLKA1 O Clock Output, Bank A.
3 CLKA2 O Clock Output, Bank A.
4 VDD I 3.3 V Supply
5 GND I Ground
6 CLKB1 O Clock Output, Bank B.
7 CLKB2 O Clock Output, Bank B.
8 S2 I Select Input pin, bit 2.
9 S1 I Select Input pin, bit 1
10 CLKB3 O Clock Output, Bank B.
11 CLKB4 O Clock Output, Bank B.
12 GND Ground
13 VDD 3.3V supply
14 CLKA3 O Clock Output, Bank A.
15 CLKA4 O Clock Output, Bank A.
16 FBK I PLL feedback input.
Note 1: Includes internal week pull-downs.
Maximum Ratings
Voltage Relative to VSS: -0.5V
Voltage Relative to VDD: 0.5V
Storage Temperature: -65oC to + 150oC
Operating Temperature: 0oC to +85oC
Maximum Power Supply: 7V
Reference Input Voltage: -.5 to 7V
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
Z9308
Zero Delay Clock Buffer
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev. 1.3 3/9/00
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 3 of 10
Operating Conditions
Parameter Description Min. Max. Unit
VDD Supply Voltage 3.0 3.6 V
TA Operating Temperature (Ambient Temperature 0 85 oC
Cout Output Capacitance 10 pF
CIN Input Capacitance 7 pF
CL Load Capacitance 30 pF
DC Electrical Characteristics
Parameters Symbol Min Typ Max Units Conditions
Input Low Voltage(1) VIL - - 0.8 Vdc
Input High Voltage(1) VIH 2.0 - Vdc -
Input Low Current IIL1- 50 µA VIN = 0 V
Input High Current IIH1- - 100 µA VIN = VDD
Output Low Voltage2VOL 0.4 V IOL = 12 mA
Output High Voltage2VOH 2.4 V IOH = - 12 mA
Tri-State leakage Current Ioz(3) - - 16.5 µA VO = 3.3 V
Dynamic Supply Current Idd - - 40 mA Unload outputs, 66.66 MHz, Select inputs
at VDD or GND.
Static Supply Current Isdd - - 50 µAS1 = S2 = VSS – VIN = VDD or VSS
Notes:
1. REF and FBK inputs have a threshold voltage of VDD/2.
2. Output (clock) pins have pulldown devices attached internally.
3. Weak pulldown is active when the output buffers are tri-stated. The value of this pulldown resistor is >200kΩ <1.55
mΩ, typically 550kΩ.
Z9308
Zero Delay Clock Buffer
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.3 3/9/00
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 4 of 10
A
AC Electrical Characteristics
Parameter Symbol Min Typ Max Units Conditions
Output Frequency (Z9308) t110 150 MHz 30 pF load (all devices)
Duty Cycle (T2/T1) (1) - 45 50 55 % Measured @ 1.4V (-1,-2,-3,-4 devices)
Output Rise Time(1) t3- 2.5 nSec Measured between 0.8V & 2.0V, 30 pF
Load (-1,-2,-3,-4 devices)
Output Rise Time(1) t31.5 nSec Measured between 0.8V & 2.0V, 20 pF
Load (-1,-2,-3,-4 devices)
Output Fall Time(1) t42.5 nSec Measured between 0.8V & 2.0V, 30 pF
Load (-1,-2,-3,-4 devices)
Output Fall Time(1) t41.5 nSec Measured between 0.8V & 2.0V, 20 pF
Load (-1,-2,-3,-4 devices)
Output to Output Skew t5- - 250 pSec All output equally loaded @ 66MHz
Delay, REF Rising Edge to
FBK Rising Edge(1) t6- 0 + 350 pSec Measured at VDD/2
All outputs equally loaded.
Device to Device Skew(1) t7- 0 700 pSec Measured at VDD/2 on FBK pins of devices
Cycle to Cycle Jitter(1)
(-1,-4 devices) tj - - 200 pSec Measured at 66.67 MHz, loaded outputs
Cycle to Cycle Jitter(1)
(-2,-3 devices) tj - - 500 pSec Measured at 66.67 MHz, loaded outputs
Maximum PLL Lock Time(1) tLOCK 1.0 ms Stable power supply, valid clocks
presented on REF and FBK pins
Notes:
1. Parameter is guaranteed by design and characterization. Not 100% tested in production. All parameters specified
with equally loaded outputs, input rise/fall max 2nS.
Z9308
Zero Delay Clock Buffer
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev. 1.3 3/9/00
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 5 of 10
Sw itching Waveforms
Duty Cycle Timing
t
t
1
2
1.4V 1.4V 1.4V
All Outputs Rise/Fall Time
t
3
t
4
0.8V
2.0V 2.0V
0.8V
3.3V
0VOutput
Output-Output Skew
t
5
1.4V
1.4V
Output
Output
Z9308
Zero Delay Clock Buffer
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.3 3/9/00
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 6 of 10
Sw itching Waveforms (Cont.)
Input-Output Propagation Delay
t
6
Input
FBK
V
DD
/2
V
DD
/2
Device-Device Skew
t
7
V
DD
/2
V
DD
/2
FBK, Device 1
FBK, Device 2
Z9308
Zero Delay Clock Buffer
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev. 1.3 3/9/00
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 7 of 10
Output Delay vs. Feedback Loading
0-5-10-15-20-25-30 5 1015202530
1500
1000
500
0
-500
-1000
-1500
REF. Input to CLKA/CLKB Delay (ps)
Output Load Difference: FBK Load - CLKA/CLKB Load (pF)
The FBK pin can be dr iven f rom any of the 8 available output pins. The output driving the F BK pin will be dr iving a FBK
load of 7 pF plus the additional output load. The relative loading of this output ( with r es pect to the r emaining outputs) will
vary the input-output delay. This is shown in the graph above.
For applications requiring zero input-output delay, all outputs including the one providing feedback should have equal
loads. If input- output delay adjus tments are required, use the above gr aph to calculate loading dif ferenc es between the
feedback output and remaining outputs.
Test Circuit Diagram
VDD
VDD
GND GND
Outputs
0.1 uF
0.1 uF
CLK out
C
LOAD
Z9308
Zero Delay Clock Buffer
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.3 3/9/00
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 8 of 10
Package Drawing and Dimensions
16 Pin 150 Mil SOIC Outline Dimensions
INCHES MILLIMETERS
SYMBOL MIN NOM MAX MIN NOM MAX
A 0.097 0.101 0.104 2.46 2.56 2.64
A10.0050 0.009 0.0115 0.127 0.22 0.29
A2 0.090 0.092 0.094 2.29 2.34 2.39
B 0.014 0.016 0.019 0.35 0.41 0.48
C 0.0091 0.010 0.0125 0.23 0.25 0.32
D 0.402 0.407 0.412 10.21 10.34 10.46
E 0.150 - 0.157 3.81 - 3.988
e 0.050 BSC 1.27 BSC
H 0.400 0.406 0.410 10.16 10.31 10.41
L 0.024 0.032 0.040 0.61 0.81 1.02
a 0º 5º 10º 0º 5º 10º
a
Be
A
A1
A2
D
EH
L
C
Z9308
Zero Delay Clock Buffer
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev. 1.3 3/9/00
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 9 of 10
Package Drawings and Dimensions (Cont.)
BO
SURFACES ROUGHNESS: 6+ 27n(RZ)
D
-B-
1.50
E1
1.20
R0.1
B
e
-C- C0.07
R0.15
4
[10° TYP
0.05 MAX.
0.05 MAX.
1.0
1.0
E
R0.15
A
A1
0.25
A2
R
L1
L
A
8°
b
cc1
b1
DETAIL B
.08 CB A
DETAIL A
14° TYP
S
16 Pin TSSOP Dimensions
INCHES MILLIMETERS
SYMBOL MIN NOM MAX MIN NOM MAX
A - - 0.0433 - - 1.10
A1 0.0019 0.0039 0.0059 0.05 0.10 0.15
A2 0.0346 0.0354 0.0374 0.85 0.90 0.95
L 0.0196 0.0236 0.0275 0.50 0.60 0.75
L1 0.0354 0.0393 0.0433 0.90 1.00 1.10
R 0.0035 - - 0.09 - -
b 0.0076 - 0.0108 0.195 - 0.275
b1 0.0076 0.0086 0.0096 0.195 0.22 0.245
c 0.0041 - 0.0068 0.105 - 0.175
c1 0.0041 0.0049 0.0057 0.105 0.125 0.145
θ0°-8°0°-8°
e 0.026 BSC 0.65 BSC
D 0.1948 0.1968 0.1988 4.95 5.0 5.05
E 0.2480 0.2519 0.2559 6.3 6.4 6.5
E1 0.1712 0.1732 0.1752 4.35 4.4 4.45
S 0.0078 - - 0.20 - -
Z9308
Zero Delay Clock Buffer
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.3 3/9/00
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 10 of 10
Ordering Information
Part Number Package Type Production Flow
Z9308-1CZ 16 Pin SOIC Commercial, 0°C to +85°C
Z9308-2CZ 16 Pin SOIC Commercial, 0°C to +85°C
Z9308-3CZ 16 Pin SOIC Commercial, 0°C to +85°C
Z9308-4CZ 16 Pin SOIC Commercial, 0°C to +85°C
Z9308-1CT 16 Pin TSSOP Commercial, 0°C to +85°C
Z9308-2CT 16 Pin TSSOP Commercial, 0°C to +85°C
Z9308-3CT 16 Pin TSSOP Commercial, 0°C to +85°C
Z9308-4CT 16 Pin TSSOP Commercial, 0°C to +85°C
Note: The ordering part number is formed by a combination of device number, device revision, package style, and
screening as shown below.
Marking: Example: IMI Date Code
9308CZ
Lot #
9308-1CZ
Package
Z = SOIC, 150 mil.
T = TSSOP
Revision
Option
IMI Device Number
