IS61LV12816 IS61LV12816L WITH 3.3V SUPPLY FEATURES * High-speed access time: 10, 12, and 15 ns * CMOS low power operation 250 mW (typical) operating 250 uW (typical) standby * TTL compatible interface levels * Single 3.3V + 10% power supply * Fully static operation: no clock or refresh required * Three state outputs * Data control for upper and lower bytes * Industrial temperature available FUNCTIONAL BLOCK DIAGRAM 128K x 16 HIGH-SPEED CMOS STATIC RAM ADVANCE INFORMATION AUGUST 1998 DESCRIPTION The JSS/ 1S61LV12816 is a high-speed, 2,097,152-bit static RAM organized as 131,072 words by 16 bits. It is fabricated using /SS/'s high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 10 ns with low power consumption. When CEis HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory.A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The 1S61LV12816 and IS61LV12816L are packaged in the JEDEC standard LV44-pin 400-mil SOJ, 44-pin TSOP, and 48-pin mini BGA. AO-A16 VCC >> GND -> 1/00-1/O7 Lower Byte /08-1/015 Upper Byte Bl Sl all 2 DECODER DATA CIRCUIT CONTROL CIRCUIT 128K x 16 MEMORY ARRAY COLUMN I/O The specification contains ADVANCE INFORMATION. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. Copyright 1998, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. ADVANCE INFORMATION SRO051-0A 08/13/98IS61LV12816 IS61LV12816L PIN CONFIGURATIONS 44-Pin SOJ 44-Pin TSOP Ais (1 441] Ao Ai5 (1 4477] Ao A14 [2 43[] At Ai4 [2 43{_] At A13 13 421] A2 Ai3 [13 421] A2 A12 (4 41[] OE Ai2 [74 41{-] OE A1i 5 40[] UB Ai1 (5 40{_] UB cE O6 301] LB CE Cy6 39{_] LB voo [7 38[] VO15 oo [7 38{-] 015 voi Es 3700) vo14 o1 C8 37] vo14 vo2 Te 36[] vo13 voz (49 36] 1/013 03 [] 10 351] vo12 03 [J 10 35{-] 1/012 vec Of 11 34] GND Vee [11 34[7] GND GND [J 12 33[] Voc GND [7] 12 33[7] Vee vo4 [] 13 321] vott o4 (13 32{-] 1/011 vos [] 14 311] vo10 O5 (J 14 31] 1/010 vos [] 15 30f] vos voe (15 30[7] 1/09 vo7 [] 16 20] vos vo7 CL] 16 29{-] 1/08 Ato [] 18 271] a3 Aio (18 27[-] A3 ag [] 19 26f] A4 Ao L] 19 26] A4 ae [20 ast] AS A8 [] 20 25] A5 A7 21 247] AG A7 C21 2407] AG A16 [] 22 a3] NC A16 [} 22 23[-] NC 48-Pin mini BGA PIN DESCRIPTIONS , i \ AO-A16 Address Inputs A (9) /00-/015 Data Inputs/Outputs B Ce) () CE Chip Enable Input Cc OE Output Enable Input D (ee) (2) WE Write Enable Input EL &) LB Lower-byte Control (I/00-//07) F UB Upper-byte Control (I/08-1/015) G (ee) @) Nc No Connection HL OOOOLO Voc Power ~. f GND Ground TRUTH TABLE /O PIN Mode WE CE OE LB UB 00-07 = 1/08-/015 Vcc Current Not Selected X H X X X High-2 High-2 IsB1, IsB2 Output Disabled H L H x x High-Z High-2 Icc X L X H H High-2 High-2 Read H L L L H Dout High-2 Icc H L L H L High-2 Dout H L L L L Dout Dout Write L L X L H DIN High-2 Icc L L X H L High-2 DIN L L Xx L L DIN DIN 2 Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR051-0A 08/13/98IS61LV12816 IS61LV12816L ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VrerRm Terminal Voltage with Respect to GND 0.5 to Vcc + 0.5 Vv TsTG Storage Temperature 65 to + 150 C Pr Power Dissipation 1.5 Ww lout DC Output Current (LOW) 20 mA Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE Range Ambient Temperature Vcc Commercial 0C to + 70C 3.3V + 10% Industrial 40C to + 85C 3.3V + 10% DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VoH Output HIGH Voltage Vcc = Min., loH = -4.0 mA 2.4 _ Vv VoL Output LOW Voltage Vcc = Min., lo. = 8.0 mA _ 0.4 Vv VIH Input HIGH Voltage 2 Veco + 0.3 Vv VIL Input LOW Voltage -0.3 0.8 Vv Iu Input Leakage GND < Vin s Vec -2 2 LA ILo Output Leakage GND < Vout < Vcc, Outputs Disabled 2 2 LA Note: 1. Vit (min.) = -2.0V for pulse width less than 10 ns. Integrated Silicon Solution, Inc. 3 ADVANCE INFORMATION SRO051-0A 08/13/98IS61LV12816 IS61LV12816L __ 1IS61LV12816 POWER SUPPLY CHARACTERISTICS (Over Operating Range) -10ns -12ns -15ns Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit lec Vcc Dynamic Operating Vcc = Max., Com. 190 160 130 mA Supply Current lour=OmA, f=fmax Ind. - = 180 150 IsBt TTL Standby Current Vcc = Max., Com. 30 30 30 mA (TTL Inputs) Vin = ViH or VIL Ind. - - 35 35 CE>ViH, f=0 Isp2 CMOS Standby Voc = Max., Com. 3 3 3 mA Current (CMOS Inputs) CE > Vcc - 0.2V, Ind. - = 10 10 Vin > Voc - 0.2V, or Vin<0.2V, f=0 Note: 1. At f =fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 1IS61LV12816L POWER SUPPLY CHARACTERISTICS" (Over Operating Range) -10ns -12ns -15ns Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit lec Vcc Dynamic Operating Vcc = Max., Com. 180 150 120 mA Supply Current lour=OmA, f=fmax Ind. - = 170 140 IsBt TTL Standby Current Vcc = Max., Com. 2 2 2 mA (TTL Inputs) Vin = ViH or ViL Ind. - - 30 30 CE>Vin, f=0 Isp2 CMOS Standby Voc = Max., Com. 03 03 03 mA Current (CMOS Inputs) CE > Vcc - 0.2V, Ind. - = - 4 - 4 Vin > Voc - 0.2V, or Vin<0.2V, f=0 Note: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR051-0A 08/13/98IS61LV12816 IS61LV12816L CAPACITANCE Symbol Parameter Conditions Max Unit CIN Input Capacitance Vin = OV 6 pF Cout Input/Output Capacitance Vout = OV 8 pF Note: 1. Tested initially and after any design or process changes that may affect these parameters. READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) -10 -12 -15 Symbol Parameter Min. Max. Min. Max. Min. Max. Unit trc Read Cycle Time 10 12 15 ns TAA Address Access Time 10 _ 12 _ 15 ns foHA Output Hold Time 3 3 3 ns tace CE Access Time 10 12 15 ns tooe OE Access Time 5 6 7 ns tHzoE) OE to High-Z Output _ 5 _ 6 0 6 ns tizoe) OE to Low-Z Output 0 0 0 ns thzce) CE to High-Z Output 0 5 0 6 0 6 ns tizce) CE to Low-Z Output 3 3 3 ns tea LB, UB Access Time 5 6 7 ns thze LB, UB to High-Z Output 0 5 0 6 0 6 ns tize LB, UB to Low-Z Output 0 0 0 ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of OV to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured +500 mV from steady-state voltage. Not 100% tested. AC TEST CONDITIONS Parameter Unit Input Pulse Level OV to 3.0V Input Rise and Fall Times 3ns Input and Output Timing 1.5V and Reference Level Output Load See Figures 1 and 2 AC TEST LOADS 319 3.3V OUTPUT 30 pF 353 Q 5 pF 353 Q Including Including jig and jig and scope = = scope = = Figure 1. Figure 2. 319.Q 3.3V OUTPUT Integrated Silicon Solution, ADVANCE INFORMATION SRO051-0A 08/13/98 Inc.IS61LV12816 IS61LV12816L AC WAVEFORMS READ CYCLE NO. 1) (Address Controlled) (CE = OE = Vi, UB or LB = Vi) <t tRC | ADDRESS x dH tAA tOHA }att TOHA DOUT PREVIOUS DATA VALID DATA VALID READ CYCLE NO. 2) ADDRESS DOUT DATA VALID Notes: 1. WE is HIGH for a Read Cycle. ee 2. The device is continuously selected. OE, CE, UB, or LB = Vi. 3. Address is valid prior to or coincident with CE LOW transition. Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR051-0A 08/13/98IS61LV12816 IS61LV12816L ia WRITE CYCLE SWITCHING CHARACTERISTICS:*) (Over Operating Range) -10 -12 -15 Symbol Parameter Min. Max. Min. Max. Min. Max. Unit twe Write Cycle Time 10 12 15 ns tsce CE to Write End 8 9 10 ns taw Address Setup Time 8 9 10 ns to Write End THA Address Hold from Write End 0 _ 0 _ 0 ns tsa Address Setup Time 0 0 0 ns tows LB, UB Valid to End of Write 8 9 = 10 ns tewe WE Pulse Width 8 9 10 ns tsp Data Setup to Write End 5 6 7 ns tHD Data Hold from Write End 0 _ 0 _ 0 ns tuzwe = WE LOW to High-Z Output 5 6 7 ns tizwe WEHIGH to Low-Z Output 3 3 3 ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of OV to 3.0V and output loading specified in Figure1. = 2. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. Tested with the load in Figure 2. Transition is measured +500 mV from steady-state voltage. Not 100% tested. Integrated Silicon Solution, Inc. 7 ADVANCE INFORMATION SRO051-0A 08/13/98IS61LV12816 IS61LV12816L AC WAVEFORMS WRITE CYCLE NO. 1) (WE Controlled) two ADDRESS T~. V Lea | LB, UB S i < tAW tPWE J N tSCE | -at wet tHA tPWB Y |< tS A_ WRITE) Wn N w {SD > -<4{tHD DIN tHZWE ~# aa + tL2WE HIGH-Z HIGH-Z DOUT 82 _ unnernen UNDEFINED Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CE) [ (LB) = (UB) ] (WE). 8 Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR051-0A 08/13/98IS61LV12816 IS61LV12816L IS61LV12816 STANDARD VERSION ORDERING INFORMATION Commercial Range: 0C to +70C IS61LV12816 STANDARD VERSION ORDERING INFORMATION Industrial Range: 40C to +85C Speed (ns) Order Part No. Package Speed (ns) Order Part No. Package 10 IS61LV12816-10B mini BGA 12 IS61LV12816-12BI mini BGA 10 IS61LV12816-10T Plastic TSOP 12 IS61LV12816-12TI Plastic TSOP 10 IS61LV12816-10K 400-mil Plastic SOJ 12 IS61LV12816-12KI 400-mil Plastic SOJ 12 IS61LV12816-12B mini BGA 15 IS61LV12816-15BI mini BGA 12 IS61LV12816-12T Plastic TSOP 15 IS61LV12816-15TI Plastic TSOP 12 IS61LV12816-12K 400-mil Plastic SOJ 15 IS61LV12816-15KI 400-mil Plastic SOJ 15 IS61LV12816-15B mini BGA 15 IS61LV12816-15T Plastic TSOP 15 IS61LV12816-15K 400-mil Plastic SOJ IS61LV12816L LOW POWER VERSION ORDERING INFORMATION Commercial Range: 0C to +70C IS61LV12816L LOW POWER VERSION ORDERING INFORMATION Industrial Range: 40C to +85C Speed (ns) Order Part No. Package 10 IS61LV12816L-10B mini BGA 10 IS61LV12816L-10T Plastic TSOP 10 IS61LV12816L-10K 400-mil Plastic SOJ 12 IS61LV12816L-12B mini BGA 12 IS61LV12816L-12T Plastic TSOP 12 IS61LV12816L-12K 400-mil Plastic SOJ 15 IS61LV12816L-15B mini BGA 15 IS61LV12816L-15T Plastic TSOP 15 IS61LV12816L-15K 400-mil Plastic SOJ Speed (ns) Order Part No. Package 12 IS61LV12816L-12Bl mini BGA 12 IS61LV12816L-12Tl Plastic TSOP 12 IS61LV12816L-12KI 400-mil Plastic SOJ 15 IS61LV12816L-15Bl mini BGA 15 IS61LV12816L-15Tl Plastic TSOP 15 IS61LV12816L-15KI 400-mil Plastic SOJ a Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Fax: (408) 588-0806 Toll Free: 1-800-379-4774 email: sales@issi.com http://www.issi.com Integrated Silicon Solution, Inc. ADVANCE INFORMATION SRO051-0A 08/13/98 9