SEPTEMBER 2010
DSC-5304/07
1
Pin Description Summary
Description
The AS8C803601/801801 are3.3V high-speed 9,437,184 bit
(9 Megabit) synchronous SRAMS. They are designed to eliminate dead bus
cycles when turning the bus around between reads and writes, or writes and
reads. Thus, they have been given the name ZBT
TM, or Zero Bus Turnaround.
Features
◆◆
◆◆
◆256K x 36, 512K x 18 memory configurations
◆◆
◆◆
◆Supports high performance system speed - 150MHz
(3.8ns Clock-to-Data Access)
◆◆
◆◆
◆ZBTTM Feature - No dead cycles between write and read cycles
◆◆
◆◆
◆Internally synchronized output buffer enable eliminates the
need to control OE
◆◆
◆◆
◆Single R/W (READ/WRITE) control pin
◆◆
◆◆
◆Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
◆◆
◆◆
◆4-word burst capability (interleaved or linear)
◆◆
◆◆
◆Individual byte write (BW1 - BW4) control (May tie active)
◆◆
◆◆
◆Three chip enables for simple depth expansion
◆◆
◆◆
◆3.3V power supply (±5%)
◆◆
◆◆
◆3.3V I/O Supply (V DDQ)
◆◆
◆◆
◆Power down controlled by ZZ input
◆◆
◆◆
◆Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP).
A
0
-A
18
Address Inputs Input Synchronous
CE
1
, CE
2
, CE
2
Chip E nables Input Synchronous
OE Output Enable Input Asynchronous
R/WRead/Write S ignal Input Synchronous
CEN Clock Enable Input Synchronous
BW
1
, BW
2
, BW
3
, BW
4
Individual Byte Write Selects Input Synchronous
CLK Clock Input N/A
ADV/LD Advance burst address / Load new address Input Synchronous
LBO Linear / Interleaved B urst Order Input Static
ZZ Sleep Mode Input Asynchronous
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
Data Input / O utput I/O Synchronous
V
DD
, V
DDQ
Core P ower, I/ O Power Supply Static
V
SS
Ground Supply Static
5304 tbl 01
256K x 36, 512K x 18
3.3V Synchronous ZBT™ SRAMs
ZBT™ Feature
3.3V I/O, Burst Counter
Pipelined Outputs
AS8C803601
AS8C801801
Address and control signals are applied to the SRAM during one clock
cycle, and two cycles later the associated data cycle occurs, be it read or write.
The AS8C803601/801801 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be
used to disable the outputs at any given time.
A Clock Enable( CEN) pin allows operation of the to AS8C803601/ 801801
be suspended as long as necessary. All synchronous inputs are ignored when
(CEN)is high and the internal device registers will hold their previous values.
There are three chip enable pins (CE1, CE2, CE2) that allow the user
to deselect the device when desired. If any one of these three are not
asserted
when ADV/LD is low, no new memory operation can be initiated. However,
any pending data transfers (reads or writes) will be completed. The data bus
will tri-state two cycles after chip is deselected or a write is initiated.
TheAS8C803601/801801 have an on-chip burst counter. In the burst
mode,the AS8C803601/801801 can provide fourcycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load a new
external address (ADV/LD = LOW) or increment the internal burst counter
(ADV/LD = HIGH).
The AS8C803601/801801 SRAM utilize IDT's latest high-performance
CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm 100-
pin thin plastic quad flatpack (TQFP) .
6.422
AS8C803601, AS8C801801, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial Temperature Range
Pin Definitions(1)
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
Symbol Pin Function I/O Active Description
A
0
-A
18
Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combination of the
rising edge of CLK, ADV/LD low, CEN low, and true c hip e nables.
ADV/LD Advance / Load I N/A ADV/LD is a synchronous input that is used to load the internal registers with new address
and control when it is sampled low at the rising edge of clock with the chip selected. When
ADV/LD is low with the chip deselected, any burst in progress is terminated. When ADV/LD
is sampled high then the internal burst counter is advanced for any burst that was in
progress. The external addresses are ignored when ADV/LD is s ampled high.
R/WRead / Write I N/A R/W signal is a synchronous input that identifies whether the current load cycle initiated is a
Read or Write access to the memory array. The data bus activity for the current cycle takes
place two clock cycles later.
CEN Clock Enable I LOW Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous
inputs, including clock are ignored and outputs remain unchanged. The effect of CEN
sampled high on the device outputs is as if the low to high clock transition did not occur.
For normal operation, CEN must be sampled low at rising edge of clock.
BW
1
-BW
4
Individual B yte
Write E nables
I LOW Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable.
On load write cycles (When R/W and ADV/LD are sampled low) the appropriate byte write
signal (BW
1
-BW
4
) must be valid. The byte write signal must also be valid on each cycle of
a burst write. Byte Write signals are ignored when R/W is sampled high. The appropriate
byte(s) of data are written into the device two cycles later. BW
1
-BW
4
can all be tied low if
always doing write to the entire 36-bit word.
CE
1
, CE
2
Chip E nables I LOW Synchronous active low c hip e nable. CE
1
an d CE
2
are used with CE
2
to e nable the AS8C
803601/ 801801 (CE
1
or CE
2
sampled high or CE
2
sampled low) and ADV/LD lo w at the
rising edge of clock, initiates a deselect cycle. The ZBT
TM
has a two cycle deselect, i.e.,
the data bus will tri-state two clock cycles after deselect is initiated.
CE
2
Chip Enable I HIGH Synchrono us active high c hip e nable. CE
2
is used with CE
1
and CE
2
to enable the chip.
CE
2
has inverted polarity but otherwise identical to CE
1
and CE
2
.
CLK Clock I N/A This i s the c lock input to theAS8C803601/801801. Except for OE, all timing references for the
device are made with respect to the rising edge of CLK.
I/O
0
-I/O
31
I/O
P1
-I/O
P4
Data Inp ut/Output I/O N/A Synchro nous data i nput/output ( I/O) p ins. B oth the d ata i nput path and d ata output p ath a re
registered and triggered by the rising edge of CLK.
LBO Linear Burst Order I LOW Burst order selection input. When LBO is high the Interleaved burst sequence is selected.
When LBO is low the Linear burst sequence is selected. LBO is a static input and it m ust
not change during device operation.
OE Output E nable I LOW Asynchronous o utput enable. OEm ust b e lo w to readdata fromtheAS8C803601/801801.When
OE is high the I/O pins are in a high-impedance state. OE does not need to be actively
controlled for read and write cycles. In no rmal operation, OE can be tied low.
ZZ Sleep Mode I N/A Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
AS8C803601/801801to its lowest power consumption level.Data retention is guaranteed in
Sleep Mode.
V
DD
Power Supply N/A N/A 3.3V core power supply.
V
DDQ
Power Supply N/A N/A 3.3V I/O Supply.
V
SS
Ground N/A N/A Ground.
5304tbl 02
6.42
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperatur e Ranges
3
Functional Block Diagram
Clk
DQ
DQ
DQ
Address A [0:18]
Control Logic
Address
Control
DI DO
InputRegister
5304 drw 01
Clock
Data I/O [0:15],
I/O P[1:2]
D
Q
Clk
Output Register
Mux Sel
Gate
OE
CE1, CE2, CE2
R/W
CEN
ADV/LD
BWx
LBO 512x18 BIT
MEMORY ARRAY
,
6.424
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Recommended DC Operating
Conditions
NOTES:
1. VIL (min.) = –1.0V for pulse width less than t CYC/2, once per cycle.
Functional Block Diagram
Symbol Parameter Min. Typ. Max. Unit
V
DD
Core S upply Voltage 3.135 3.3 3.465 V
V
DDQ
I/O S upply Voltage 3.135 3.3 3.465 V
V
SS
Supply Voltage 0 0 0 V
V
IH
Input High Voltage - Inputs 2.0
____
V
DD
+0.3 V
V
IH
Input High Voltage - I/O 2.0
____
V
DDQ
+0.3 V
V
IL
Input L ow V oltag e -0.3
(1 )
____
0.8 V
5304 tbl 04
Clk
DQ
DQ
DQ
Address A [0:18]
Control Logic
Address
Control
DI DO
InputRegister
5304 drw 01
Clock
Data I/O [0:15],
I/O P[1:2]
D
Q
Clk
Output Register
Mux Sel
Gate
OE
CE1, CE2, CE2
R/W
CEN
ADV/LD
BWx
LBO 512x18 BIT
MEMORY ARRAY
,
6.42
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperatur e Ranges
5
10099989796959493929190 8786858483828189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
CE
1
CE
2
BW
4
BW
3
BW
2
BW
1
CE
2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
NC
(2)
A
17
A
8
A
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DNU
(3)
DNU
(3)
DNU
(3)
DNU
(3)
LBO
A
14
A
13
A
12
A
11
A
10
V
DD
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
I/O
31
I/O
30
V
DDQ
V
SS
I/O
29
I/O
28
I/O
27
I/O
26
V
SS
V
DDQ
I/O
25
I/O
24
V
SS
V
DD
I/O
23
I/O
22
V
DDQ
V
SS
I/O
21
I/O
20
I/O
19
I/O
18
V
SS
V
DDQ
I/O
17
I/O
16
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O
14
V
DDQ
V
SS
I/O
13
I/O
12
I/O
11
I/O
10
V
SS
V
DDQ
I/O
9
I/O
8
V
SS
V
DD
I/O
7
I/O
6
V
DDQ
V
SS
I/O
5
I/O
4
I/O
3
I/O
2
V
SS
V
DDQ
I/O
1
I/O
0
5304 drw 02
V
DD
(1)
I/O
15
I/O
P3
V
DD
(1)
I/O
P4
A
15
A
16
I/O
P1
V
DD
(1)
I/O
P2
ZZ
,
Recommended Operating
Temperature and Supply Voltage
Pin Configuration - 256K x 36
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as the input voltage is ≥ VIH.
2. Pin 84 is reserved for a future 16M.
3. DNU=Do not use. Pins 38, 39, 42 and 43 are reserved for respective JTAG pins: TMS, TDI, TDO and TCK. The
current die revision allows these pins to be left unconnected, tied LOW (V SS), or tied HIGH (V DD).
Top View
100 TQFP
Grade Ambient
Temperature
(1)
V
SS
V
DD
V
DDQ
Commercial 0° C t o +70° C 0V 3.3V±5% 3.3V±5%
Industrial -40°C to +85°C 0V 3.3V±5% 3.3V±5%
5304 tbl 05
NOTES:
1. During production testing, the case temperature equals the ambient temperature .
6.42
6
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings
(1)
Pin Configuration - 512K x 18
119 BGA Capacitance
(1)
(TA = +25° C, f = 1.0MHz)
Top View
100 TQFP
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed V DDQ during power
supply ramp up.
7. During production testing, the case temperature equals T A.
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
Symbol Rating Commercial &
Industrial Unit
V
TE RM
(2)
Terminal Voltage with
Re sp ect to GND
-0.5 to +4.6 V
V
TE RM
(3,6)
Terminal Voltage with
Re sp ect to GND
-0.5 to V
DD
V
V
TE RM
(4,6)
Terminal Voltage with
Re sp ect to GND
-0.5 to V
DD
+0.5 V
V
TE RM
(5,6)
Terminal Voltage with
Re sp ect to GND
-0.5 to V
DDQ
+0.5 V
T
A
(7)
Commercial
Operating Temperature
-0 to +70
o
C
Industrial
Operating Temperature -40 to + 85
o
C
T
BIAS
Temperature
Under B ias
-55 to + 125
o
C
T
STG
Storage
Temperature
-55 to + 125
o
C
P
T
Power Di ssipation 2.0 W
I
OUT
DC O utput Cu rrent 50 mA
5304 tbl 06
Symbol Parameter
(1 )
Conditions Max. Unit
C
IN
Input Capacitance V
IN
= 3dV 5 pF
C
I/O
I/O C apacitance V
OUT
= 3dV 7 pF
5304 t bl 07
100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 8189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
CE
1
CE
2
NC
NC
BW
2
BW
1
CE
2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
NC
(2)
A
18
A
8
A
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DNU
(3)
DNU
(3)
DNU
(3)
DNU
(3)
LBO
A
15
A
14
A
13
A
12
A
11
V
DD
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
NC
NC
V
DDQ
V
SS
NC
I/O
P2
I/O
15
I/O
14
V
SS
V
DDQ
I/O
13
I/O
12
V
SS
V
DD
I/O
11
I/O
10
V
DDQ
V
SS
I/O
9
I/O
8
NC
NC
V
SS
V
DDQ
NC
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
V
DDQ
V
SS
NC
I/O
P1
I/O
7
I/O
6
V
SS
V
DDQ
I/O
5
I/O
4
V
SS
V
DD
I/O
3
I/O
2
V
DDQ
V
SS
I/O
1
I/O
0
NC
NC
V
SS
V
DDQ
NC
NC
5304 drw 02a
V
DD
(1)
NC
NC
V
DD
(1)
NC
A
16
A
17
NC
V
DD
(1)
A
10
ZZ
,
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to V DD as long as
the input voltage is ≥ VIH.
2. Pin 84 is reserved for a future 16M.
3. DNU=Do not use. Pins 38, 39, 42 and 43 are reserved for respective
JTAG pins: TMS, TDI, TDO and TCK. The current die revision allows
these pins to be left unconnected, tied LOW (V SS), or tied HIGH (V DD).
Symbol Parameter
(1 )
Conditions Max. Unit
C
IN
Input Capacitance V
IN
= 3dV 7 pF
C
I/O
I/O C apacitance V
OUT
= 3dV 7 pF
5304 t bl 07a
100 TQFP Capacitance(1)
(TA = +25° C, f = 1.0MHz)
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Input Capacitance V
IN
= 3 dV TBD pF
C
I/O
I/O C apacitance V
OUT
= 3 dV TBD pF
5304 t b l 0 7b
165 fBGA Capacitance
(1)
(TA = +25° C, f = 1.0MHz)
6.42
AS8C803601, AS8C801801, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial Temperature Range
7
Synchronous Truth Table(1)
Partial Truth Table for Writes(1)
NOTES:
1. L = V IL, H = V IH, X = Don’t Care.
2. When ADV/ LD signal is sampled high, the internal burst counter is incremented. The R/ W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/ W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either ( CE1, or CE2 is sampled high or CE 2 is sampled low) and ADV/ LD is sampled low at rising edge of clock. The data bus will
tri-state two cycles after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/Os
remains unchanged.
5. To select the chip requires CE1 = L, CE2 = L, CE 2 = H on these chip enables. Chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.
NOTES:
1. L = V IL, H = V IH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for X18 configuration.
CEN R/WChip
(5)
Enable
ADV/LD BWxADDRESS
USED
PREVIOUS CYCLE CURRENT CYCLE I/O
(2 cycles l ater)
L L Select L Valid External X LOAD WRITE D
(7)
L H Select L X External X LOAD READ Q
(7)
L X X H Valid Internal LOAD W RITE /
BURST WRITE
BURST W RITE
(Advance burst counter)
(2)
D
(7)
L X X H X Internal LOAD RE AD /
BURST RE AD
BURST RE AD
(Advance burst counter)
(2)
Q
(7)
L X Deselect L X X X DESELECT or STOP
(3)
HiZ
L X X H X X DESELECT / NO OP NOOP HiZ
H X X X X X X SUSPEND
(4)
Previous Value
5304 tbl 08
OPERATION R/WBW
1
BW
2
BW
3
(3)
BW
4
(3 )
READ H X X X X
WRITE ALL BYTES L L L L L
WRITE BYTE 1 (I/O[0:7], I/O
P1
)
(2)
LLHHH
WRITE BYTE 2 (I/O[8:15], I/O
P2
)
(2)
LHLHH
WRITE BYTE 3 (I/O[16:23], I/O
P3
)
(2,3)
LHHLH
WRITE BYTE 4 (I/O[24:31], I/O
P4
)
(2,3)
LHHHL
NO WRITE LHHHH
5304 tbl 09
88
AS8C803601, AS8C801801, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial Temperature Range
Linear Burst Sequence T able (LBO=VSS)
Interleaved Burst Sequence Table (LBO=VDDDD
DDDD
DD)
Functional Timing Diagram
(1)
NOTES:
1. This assumes CEN, CE1, CE 2, CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Sequence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address 0 0 0 1 1 0 1 1
Second Address 0 1 0 0 1 1 1 0
Third Address 1 0 1 1 0 0 0 1
Fourth A ddress
(1)
11100 100
5304 tbl 10
Sequence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address 0 0 0 1 1 0 1 1
Second Address 0 1 1 0 1 1 0 0
Third Address 1 0 1 1 0 0 0 1
Fourth A ddress
(1)
11000 110
5304 tbl 11
n+29
A29
C29
D/Q27
ADDRESS
(2)
(A0 - A17)
CONTROL
(2)
(R/W,ADV/LD,BWx)
DATA
(2)
I/O [0:31], I/O P[1:4]
CYCLE
CLOCK
n+30
A30
C30
D/Q28
n+31
A31
C31
D/Q29
n+32
A32
C32
D/Q30
n+33
A33
C33
D/Q31
n+34
A34
C34
D/Q32
n+35
A35
C35
D/Q33
n+36
A36
C36
D/Q34
n+37
A37
C37
D/Q35
5304 drw 03
,
99AS8C803601, AS8C801801, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial Temperature Range
9
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE 2 = H. CE = H is defined as CE1 = H, CE2 = H or CE 2 = L.
Read Operation
(1)
Device Operation - Showing Mixed Load, Burst,
Deselect and NOOP Cycles
(2)
NOTES:
1. CE = L is defined as CE1 = L, CE2 = L and CE 2 = H. CE = H is defined as CE1 = H, CE2 = H or CE 2 = L.
2. H = High; L = Low; X = Don’t Care; Z = High Impedance.
CycleAddressR/WADV/LD CE
(1)
CEN BWxOE I/O Comments
nA
0
H L L L X X X Load read
n+1 X X H X L X X X Burst r ead
n+2 A
1
HL LLXLQ
0
Load read
n+3 X X L H L X L Q
0+1
Deselect or STOP
n+4 X X H XLXLQ
1
NOOP
n+5 A
2
H L L L X X Z Load read
n+6 X X H X L X X Z Burst r ead
n+7 X X L H L X L Q
2
Deselect or STOP
n+8 A
3
L L LLLLQ
2+1
Load write
n+9 X X H X L L X Z Burst write
n+10 A
4
L L LLLXD
3
Load write
n+11 X X L H L X X D
3+1
Deselect or STOP
n+12 X X H X L X X D
4
NOOP
n+13 A
5
L L L L L X Z Load write
n+14 A
6
H L L L X X Z Load read
n+15 A
7
L L LLLXD
5
Load write
n+16 X X H X L L L Q
6
Burst write
n+17 A
8
HL LLXXD
7
Load read
n+18 X X H X L X X D
7+1
Burst read
n+19 A
9
L L LLLLQ
8
Load write
5304tbl 12
CycleAddressR/WADV/LD CE
(2)
CEN BWxOE I/O Comments
nA
0
H L L L X X X Address and Control meet setup
n+1 X X X XLXXXClockS Setup Va
lid
n+2 X X X XXXLQ
0
Contents of Address A
0
Read O ut
10 10
AS8C803601, AS8C801801, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial Temperature Range
Burst Write Operation
(1)
Burst Read Operation
(1)
Write Operation(1)
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance..
2. CE = L is defined as CE1 = L, CE2 = L and CE 2 = H. CE = H is defined as CE1 = H, CE2 = H or CE 2 = L.
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE 2 = H. CE = H is defined as CE1 = H, CE2 = H or CE 2 = L.
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE 2 = H. CE = H is defined as CE1 = H, CE2 = H or CE 2 = L.
Cycle Address R/WADV/LD CE
(2)
CEN BWxOE I/O Comments
nA
0
H L L L X X X Address and Control meet setup
n+1 X X H X L X X X Clock Setup Valid, Advance Counter
n+2 X X H XLXLQ
0
Address A
0
Read Out, Inc. Count
n+3 X X H XLXLQ
0+1
Address A
0+1
Read O ut, Inc . Co unt
n+4 X X H XLXLQ
0+2
Address A
0+2
Read O ut, Inc . Co unt
n+5 A
1
HL LLXLQ
0+3
Address A
0+3
Re ad Out, Load A
1
n+6 X X H XLXLQ
0
Address A
0
Read Out, Inc. Count
n+7 X X H XLXLQ
1
Address A
1
Read Out, Inc. Count
n+8 A
2
HL LLXLQ
1+1
Address A
1+1
Read Out, Lo ad A
2
Cycle Address R/WADV/LD CE
(2)
CEN BWxOE I/O Comments
nA
0
L L L L L X X Address and Control meet setup
n+1 X X X X L X X X Clock S etup Valid
n+2 X X X X L X X D
0
Write to Address A
0
CycleAddressR/WADV/LD CE
(2)
CEN BWxOE I/O Comments
nA
0
L L L L L X X Address and Control meet setup
n+1 X X H X L L X X Clock Setup Valid, Inc. C ount
n+2 X X H X L L X D
0
Address A
0
Write, Inc. Count
n+3 X X H X L L X D
0+1
Address A
0+1
Write , I nc. C ount
n+4 X X H X L L X D
0+2
Address A
0+2
Write , I nc. C ount
n+5 A
1
L L LLLXD
0+3
Address A
0+3
Write , L oad A
1
n+6 X X H X L L X D
0
Address A
0
Write, Inc. Count
n+7 X X H X L L X D
1
Address A
1
Write, Inc. Count
n+8 A
2
L L LLLXD
1+1
Address A
1+1
Write, L oad A
2
AS8C803601, AS8C801801, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial Temperature Range
11
Read Operation with Clock Enable Used
(1)
Write Operation with Clock Enable Used
(1)
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE 2 = H. CE = H is defined as CE1 = H, CE2 = H or CE 2 = L.
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE 2 = H. CE = H is defined as CE1 = H, CE2 = H or CE 2 = L.
CycleAddressR/WADV/LD CE
(2)
CEN BWxOE I/O Comments
nA
0H L L L X X X Address and Control meet setup
n+1 X X X X H X X X Clock n+1 I gnored
n+2 A1H L LLXXXClockV alid
n+3 X X X X H X L Q0Clock Ignored, Data Q0 is on the bus.
n+4 X X X X H X L Q0Clock Ignored, Data Q0 is on the bus.
n+5 A2HL LLXLQ0Address A0 Read o ut (bus trans.)
n+6 A3HL LLXLQ1Address A1 R ead o ut ( bus tr ans.)
n+7 A4HL LLXLQ2Ad dress A2 Read o ut (bus trans.)
CycleAddressR/WADV/LD CE
(2)
CEN BWxOE I/O Comments
nA
0L L L L L X X Address and Control meet setup.
n+1 X X X X H X X X Clock n+ 1 Ignored.
n+2 A1L L L L L X X Clock Valid.
n+3 X X X X H X X X Clock Ignored.
n+4 X X X X H X X X Clock Ignored.
n+5 A2LL LLLXD0Write D ata D 0
n+6 A3LL LLLXD1Write D ata D 1
n+7 A4LL LLLXD2Write D ata D 2
12
AS8C803601, AS8C801801, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial TemperatureRange
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE 2 = H. CE = H is defined as CE1 = H, CE2 = H or CE 2 = L.
3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
Read Operation with Chip Enable Used
(1)
Write Operation with Chip Enable Used
(1)
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE 2 = H. CE = H is defined as CE1 = H, CE2 = H or CE 2 = L.
Cycle Address R/WADV/LD CE
(2)
CEN BWxOE I/O
(3)
Comments
n X X L H L X X ? Deselected.
n+1 X X L H L X X ? Deselected.
n+2 A
0
H L L L X X Z Address and Control meet setup
n+3 X X L H L X X Z Deselected or STOP.
n+4 A
1
HL LLXLQ
0
Address A
0
Read o ut. Load A
1
.
n+5 X X L H L X X Z Deselected or STOP.
n+6 X X L H L X L Q
1
Address A
1
Re ad o ut. De selected.
n+7 A
2
H L L L X X Z Address and control meet setup.
n+8 X X L H L X X Z Deselected or STOP.
n+9 X X L H L X L Q
2
Address A
2
Read out. Deselected.
CycleAddressR/W ADV/LD CE
(2)
CEN BWxOE I/O
(3)
Comments
n X X L H L X X ? Deselected.
n+1 X X L H L X X ? Deselected.
n+2 A
0
L L L L L X Z Address and Control meet setup
n+3 X X L H L X X Z Deselected or STOP.
n+4 A
1
L L LLLXD
0
Address D
0
Write in. Load A
1
.
n+5 X X L H L X X Z Deselected or STOP.
n+6 X X L H L X X D
1
Address D
1
Write in. Deselected.
n+7 A
2
L L L L L X Z Address and control meet setup.
n+8 X X L H L X X Z Deselected or STOP.
n+9 X X L H L X X D
2
Address D
2
Write in. Deselected.
14
13
AS8C803601, AS8C801801, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial Temperature Range
AC Electrical Characteristics
(VDD = 3.3V +/-5%, Industrial Temperature Range)
NOTES:
1. tF = 1/t CYC.
2. Measured as HIGH above 0.6V DDQ and LOW below 0.4V DDQ.
3. Transition is measured ±200mV from steady-state.
4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
5. To avoid bus contention, the output buffers are designed such that t CHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and voltage.
The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) thantCHZ,
which is a Max. parameter (worse case at 70 deg. C, 3.135V).
150MHz 133MHz 100MHz
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
t
CY C
Clock Cycle Time 6.7
____
7.5
____
10
____
ns
t
F
(1)
Clock Frequency
____
150
____
133
____
100 MHz
t
CH
(2)
Clock High Pulse Width 2.0
____
2.2
____
3.2
____
ns
t
CL
(2)
Clock Low Pulse Width 2.0
____
2.2
____
3.2
____
ns
Output Parameters
t
CD
Clock High to Valid Data
____
3.8.
____
4.2
____
5ns
t
CDC
Clock High to Data Change 1.5
____
1.5
____
1.5
____
ns
t
CL Z
(3 , 4,5)
Clock H ig h to Ou tput A ctive 1.5
____
1.5
____
1.5
____
ns
t
CHZ
(3 , 4,5)
Clock High to Data High-Z 1.5 3 1.5 3 1.5 3.3 ns
t
OE
Output Enable Access Time
____
3.8
____
4.2
____
5ns
t
OLZ
(3,4)
Output Enable L ow to Data Active 0
____
0
____
0
____
ns
t
OHZ
(3,4)
Output Enable High to Data High-Z
____
3.8
____
4.2
____
5ns
Set Up Times
t
SE
Clock E nab le S etup Ti me 1.5
____
1.7
____
2.0
____
ns
t
SA
Address Setup Time 1.5
____
1.7
____
2.0
____
ns
t
SD
Data In S etup Time 1.5
____
1.7
____
2.0
____
ns
t
SW
Read/Write (R/ W) S etup Time 1.5
____
1.7
____
2.0
____
ns
t
SADV
Advance/Load (ADV/LD) S e tup T ime 1.5
____
1.7
____
2.0
____
ns
t
SC
Chip Enable/Select S etup Time 1.5
____
1.7
____
2.0
____
ns
t
SB
Byte Write E nable (BWx) Setup Time 1.5
____
1.7
____
2.0
____
ns
Hold T imes
t
HE
Clock Enable Hold Time 0.5
____
0.5
____
0.5
____
ns
t
HA
Address Hold Time 0.5
____
0.5
____
0.5
____
ns
t
HD
Data In H old T ime 0.5
____
0.5
____
0.5
____
ns
t
HW
Read/Write (R/ W) Ho ld Time 0.5
____
0.5
____
0.5
____
ns
t
HADV
Advance/Load (ADV/LD) H o ld T ime 0.5
____
0.5
____
0.5
____
ns
t
HC
Chip Enable/Select Hold Time 0.5
____
0.5
____
0.5
____
ns
t
HB
Byte Write E nable (BWx) Hold Time 0.5
____
0.5
____
0.5
____
ns
5304 tbl 24
(CENhigh,eliminates
currentL-Hclockedge)
O2(A2)
t
CD
t
HADV
Pipeline
Read
(BurstWrapsaround
to initialstate)
t
CDC
t
CLZ
t
CHZ
t
CD
t
CDC
R/W
CLK
CEN
ADDRESS
OE
DATA
OUT
t
HE
t
SE
A1A2
O1(A2)O1(A2)
t
CH
t
CL
t
CYC
t
SADV
t
HW
t
SW
t
HA
t
SA
t
HC
t
SC
BurstPipelineRead
Pipeline
Read
BW
1
-BW
4
5304drw06
CE
1
,
CE
2(2)
Q(A
2+3
)Q(A
2
)
Q(A
2+2
)
Q(A
2+2
)
Q(A
2+1
)
Q(A
2
)
Q(A
1
)
,
t
HE
t
SE
R/W
A
1
A
2
CLK
CEN
ADV/LD
ADDRESS
OE
DATA
IN
t
HD
t
SD
t
CH
t
CL
t
CYC
t
HADV
t
SADV
t
HW
t
SW
t
HA
t
SA
t
HC
t
SC
BurstPipelineWrite
Pipeline
Write
Pipeline
Write
t
HB
t
SB
(BurstWrapsaround
to initialstate)
t
HD
t
SD
(CENhigh,eliminates
currentL-H clockedge)
(2)
D(
A2+2
)D(
A2+3
)
D(A
1
)D(A
2
)D(A
2
)
5304drw07
BW1-BW4
CE1,CE2
D(A
2+1
)
.
t
HE
t
SE
R/W
A
1
A
2
CLK
CEN
ADV/LD
ADDRESS
CE
1
,CE
2(2)
BW
1
-BW
4
DATA
OUT
Q(A
3
)
Q(A
1
)Q(A
6
)Q(A
7
)
t
CD
Read
t
CHZ
5304drw08
Write
t
CLZ
D(A
2
)D(A
4
)
t
CDC
D(A
5
)
Write
t
CH
t
CL
t
CYC
t
HW
t
SW
t
HA
t
SA
A
4
A
3
t
HC
t
SC
t
SD
t
HD
t
HADV
t
SADV
A
6
A
7
A
8
A
5
A
9
DATA
IN
t
HB
t
SB
OE
Read
Read
,,
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two
cycles before the actual data is presented to the SRAM.
Timing Waveform of Combined Read and Write Cycles(1,2,3)
t
HE
t
SE
R/W
A
1
A
2
CLK
CEN
ADV/LD
ADDRESS
BW1-BW4
OE
DATA
OUT
Q(A
3
)
t
CD
t
CLZ
t
CHZ
t
CH
t
CL
t
CYC
t
HC
t
SC
D(A
2
)
t
SD
t
HD
t
CDC
A
4
A
5
t
HADV
tSADV
t
HW
t
SW
t
HA
t
SA
A
3
t
HB
t
SB
DATA
IN
Q(A
1
)
5304drw09
Q(A
1
)
B(A
2
)
CE
1
,CE
2
(2)
R/W
A1
CLK
ADV/LD
ADDRESS
OE
DATA
OUT
Q(A
1
)
t
CD
t
CLZ
t
CHZ
t
CDC
t
CH
t
CL
t
CYC
t
HC
t
SC
t
SD
t
HD
A
5
A
3
t
SB
DATA
IN
t
HE
t
SE
A
2
t
HA
t
SA
A
4
t
HW
t
SW
t
HB
CEN
t
HADV
t
SADV
5304drw10
Q(A
2
)Q(A
4
)
D(A
3
)
BW1-BW4
CE1,CE2
(2)
,
19
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
100-Pin Plastic Thin Quad Flatpack (TQFP) Package Diagram Outline
25
AS8C803601, AS8C801801, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial Temperatur e Range
2
Timing Waveform of OE Operation(1)
NOTE:
1. A read operation is assumed to be in progress.
OE
DATA
OUT
t
OHZ
t
OLZ
t
OE
Valid
5304 drw 11
,
1. EMLSI Memory
2. Device Type 11. Power
3. Density 10. Speed
4. Function 9. Package
5. Technology 8. Version
6. Operating Voltage 7. Organization
1. EMLSI Memory
2. Device Type 11. Power
3. Density 10. Speed
4. Function 9. Package
5. Technology 8. Version
6. Operating Voltage 7. Organization
Alliance Organization VCC
Range Package Operating Temp Speed
Mhz
AS8C803601-QC150N 256K x 36 3.1- 3.4V 100 pin TQFP Comercial 0 - 70C 150
AS8C801801-QC150N 512K x 18 3.1- 3.4V 100 pin TQFP Comercial 0 - 70C 150
ORDERING INFORMATION
ORDERING INFORMATION
Alliance OrganizationVCC
Range Package Operating TempSpeed
ns
AS6C8016A-55ZIN512K x 16 2.7- 5.5V44pin TSOP IIIndustrial ~ -40 C - 85 C 55
AS6C8016A-55BIN512K x 16 2.7- 5.5V48ball FBGAIndustrial ~ -40 C - 85 C 55
PART NUMBERING SYSTEM
AS6C 8016 -55 X X N
Device Number Package OptionTemperature Range
80 = 8M Z- 44pin TSOP I = Industrial
low power
SRAM prefix16 = x16
Access
TimeB = 48ball TFBGA (-40 to + 85 C)
N = Lead Free
RoHS
compliant part
PART NUMBERING SYSTEM
AS8C
01= ZBT Q = 100 Pin TQFP
Sync.
SRAM prefix
18= x18
36 = x36 25 = Flow- Thru
0 ~ 70C 150MHz N= Leadfree
80 = 8M 00 = Pipelined
®
Alliance Memory, Inc.
551 Taylor way, suite#1
San Carlos, CA 94070
Tel: 650-610-6800
Fax: 650-620-9211
www.alliancememory.com
Copyright © Alliance Memory
All Rights Reserved
Part Number: AS8C803601/801801
Document Version: v. 1.0
© Copyright 2003 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of
Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this
document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data
contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any
time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in
this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide,
any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any
product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or
warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in
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Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights,
trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in
life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of
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claims arising from such use.
Speed
Device Conf. Mode Package Operating Temp N
