Ultralow Noise XFET Voltage References
with Current Sink and Source Capability
ADR430/ADR431/ADR433/ADR434/ADR435/ADR439
Rev. J
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FEATURES
Low noise (0.1 Hz to 10.0 Hz): 3.5 μV p-p @ 2.5 V output
No external capacitor required
Low temperature coefficient
A Grade: 10 ppm/°C maximum
B Grade: 3 ppm/°C maximum
Load regulation: 15 ppm/mA
Line regulation: 20 ppm/V
Wide operating range
ADR430: 4.1 V to 18 V
ADR431: 4.5 V to 18 V
ADR433: 5.0 V to 18 V
ADR434: 6.1 V to 18 V
ADR435: 7.0 V to 18 V
ADR439: 6.5 V to 18 V
High output source and sink current: +30 mA and −20 mA
Wide temperature range: −40°C to +125°C
APPLICATIONS
Precision data acquisition systems
High resolution data converters
Medical instruments
Industrial process control systems
Optical control circuits
Precision instruments
PIN CONFIGURATIONS
NOTES
1. NIC = NO INTERNAL CONNECTION
2. TP = TEST PIN (DO NOT CONNECT)
ADR43x
TOP VIEW
(Not to Scale)
TP
1
V
IN 2
NIC
3
GND
4
TP
COMP
V
OUT
TRIM
8
7
6
5
04500-001
Figure 1. 8-Lead MSOP (RM-8)
NOTES
1. NIC = NO INTERNAL CONNECTION
2. TP = TEST PIN (DO NOT CONNECT)
ADR43x
TOP VIEW
(Not to Scale)
TP
1
V
IN 2
NIC
3
GND
4
TP
COMP
V
OUT
TRIM
8
7
6
5
04500-041
Figure 2. 8-Lead SOIC_N (R-8)
GENERAL DESCRIPTION
The ADR43x series is a family of XFET® voltage references
featuring low noise, high accuracy, and low temperature drift
performance. Using Analog Devices, Inc., patented temperature
drift curvature correction and XFET (eXtra implanted junction
FET) technology, voltage change vs. temperature nonlinearity in
the ADR43x is minimized.
The XFET references operate at lower current (800 µA) and
lower supply voltage headroom (2 V) than buried Zener
references. Buried Zener references require more than 5 V
headroom for operation. The ADR43x XFET references are
the only low noise solutions for 5 V systems.
The ADR43x family has the capability to source up to 30 mA of
output current and sink up to 20 mA. It also comes with a trim
terminal to adjust the output voltage over a 0.5% range without
compromising performance.
The ADR43x is available in 8-lead MSOP and 8-lead narrow
SOIC packages. All versions are specified over the extended
industrial temperature range of −40°C to +125°C.
Table 1. Selection Guide
Model
Output
Voltage (V) Accuracy (mV)
Temperature
Coefficient
(ppm/°C)
ADR430A 2.048 ±3 10
ADR430B 2.048 ±1 3
ADR431A 2.500 ±3 10
ADR431B 2.500 ±1 3
ADR433A 3.000 ±4 10
ADR433B 3.000 ±1.5 3
ADR434A 4.096 ±5 10
ADR434B 4.096 ±1.5 3
ADR435A 5.000 ±6 10
ADR435B 5.000 ±2 3
ADR439A 4.500 ±5.5 10
ADR439B 4.500 ±2 3
ADR430/ADR431/ADR433/ADR434/ADR435/ADR439
Rev. J | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Pin Configurations........................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
ADR430 Electrical Characteristics............................................. 4
ADR431 Electrical Characteristics............................................. 5
ADR433 Electrical Characteristics............................................. 6
ADR434 Electrical Characteristics............................................. 7
ADR435 Electrical Characteristics............................................. 8
ADR439 Electrical Characteristics............................................. 9
Absolute Maximum Ratings.......................................................... 10
Thermal Resistance.................................................................... 10
ESD Caution................................................................................ 10
Typical Performance Characteristics ........................................... 11
Theory of Operation ...................................................................... 16
Basic Voltage Reference Connections...................................... 16
Noise Performance..................................................................... 16
High Frequency Noise............................................................... 16
Turn-On Time ............................................................................ 17
Applications Information.............................................................. 18
Output Adjustment.................................................................... 18
Reference for Converters in Optical Network Control
Circuits......................................................................................... 18
High Voltage Floating Current Source.................................... 18
Kelvin Connection ..................................................................... 18
Dual Polarity References........................................................... 19
Programmable Current Source ................................................ 19
Programmable DAC Reference Voltage .................................. 20
Precision Voltage Reference for Data Converters.................. 20
Precision Boosted Output Regulator....................................... 21
Outline Dimensions....................................................................... 22
Ordering Guide .......................................................................... 23
ADR430/ADR431/ADR433/ADR434/ADR435/ADR439
Rev. J | Page 3 of 24
REVISION HISTORY
7/11—Rev. I to Rev. J
Changes to Figure 1 and Figure 2....................................................1
Changes to Ordering Guide...........................................................23
5/11—Rev. H to Rev. I
Added Endnote 1 in Table 2.............................................................4
Added Endnote 1 in Table 3.............................................................5
Added Endnote 1 in Table 4.............................................................6
Added Endnote 1 in Table 5.............................................................7
Added Endnote 1 in Table 6.............................................................8
Added Endnote 1 in Table 7.............................................................9
Deleted Negative Precision Reference Without Precision
Resistors Section..............................................................................17
Deleted Figure 36; Renumbered Sequentially.............................18
2/11—Rev. G to Rev. H
Updated Outline Dimensions........................................................21
Changes to Ordering Guide...........................................................22
7/10—Rev. F to Rev. G
Changes to Storage Temperature Range in Table 9.......................9
6/10—Rev. E to Rev. F
Updated Pin Name NC to COMP Throughout ............................1
Changes to Figure 1 and Figure 2....................................................1
Changes to Figure 30 and High Frequency Noise Section ........15
Updated Outline Dimensions........................................................21
Changes to Ordering Guide...........................................................22
1/09—Rev. D to Rev. E
Added High Frequency Noise Section and Equation 3;
Renumbered Sequentially ..............................................................15
Inserted Figure 31, Figure 32, and Figure 33; Renumbered
Sequentially......................................................................................16
Changes to the Ordering Guide ....................................................22
12/07—Rev. C to Rev. D
Changes to Initial Accuracy and Ripple Rejection Ratio
Parameters in Table 2 through Table 7...........................................3
Changes to Table 9 ............................................................................9
Changes to Theory of Operation Section ....................................15
Updated Outline Dimensions........................................................20
8/06—Rev. B to Rev. C
Updated Format ................................................................. Universal
Changes to Table 1 ............................................................................1
Changes to Table 3 ............................................................................4
Changes to Table 4 ............................................................................5
Changes to Table 7 ............................................................................8
Changes to Figure 26 ......................................................................14
Changes to Figure 31 ......................................................................16
Updated Outline Dimensions........................................................20
Changes to Ordering Guide...........................................................21
9/04—Rev. A to Rev. B
Added New Grade.............................................................. Universal
Changes to Specifications ................................................................3
Replaced Figure 3, Figure 4, Figure 5 ...........................................10
Updated Ordering Guide...............................................................21
6/04—Rev. 0 to Rev. A
Changes to Format............................................................. Universal
Changes to the Ordering Guide....................................................20
12/03—Revision 0: Initial Version
ADR430/ADR431/ADR433/ADR434/ADR435/ADR439
Rev. J | Page 4 of 24
SPECIFICATIONS
ADR430 ELECTRICAL CHARACTERISTICS
VIN = 4.1 V to 18 V, IL = 0 mA, TA = 25°C, unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ Max Unit
OUTPUT VOLTAGE VO
A Grade 2.045 2.048 2.051 V
B Grade 2.047 2.048 2.049 V
INITIAL ACCURACY1 V
OERR
A Grade ±3 mV
±0.15 %
B Grade ±1 mV
±0.05 %
TEMPERATURE COEFFICIENT TCVO
A Grade −40°C < TA < +125°C 2 10 ppm/°C
B Grade −40°C < TA < +125°C 1 3 ppm/°C
LINE REGULATION ∆VO/∆VIN V
IN = 4.1 V to 18 V, −40°C < TA < +125°C 5 20 ppm/V
LOAD REGULATION ∆VO/∆IL I
L = 0 mA to 10 mA, VIN = 5.0 V, −40°C < TA < +125°C 15 ppm/mA
∆VO/∆IL I
L = −10 mA to 0 mA, VIN = 5.0 V, −40°C < TA < +125°C 15 ppm/mA
QUIESCENT CURRENT IIN No load, −40°C < TA < +125°C 560 800 μA
VOLTAGE NOISE eN p-p 0.1 Hz to 10.0 Hz 3.5 μV p-p
VOLTAGE NOISE DENSITY eN 1 kHz 60 nV/√Hz
TURN-ON SETTLING TIME tR C
L = 0 μF 10 μs
LONG-TERM STABILITY2 ∆VO 1000 hours 40 ppm
OUTPUT VOLTAGE HYSTERESIS VO_HYS 20 ppm
RIPPLE REJECTION RATIO RRR fIN = 1 kHz –70 dB
SHORT CIRCUIT TO GND ISC 40 mA
SUPPLY VOLTAGE
OPERATING RANGE VIN 4.1 18 V
SUPPLY VOLTAGE HEADROOM VINVO 2 V
1 Initial accuracy does not include shift due to solder heat effect.
2 The long-term stability specification is noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period.
ADR430/ADR431/ADR433/ADR434/ADR435/ADR439
Rev. J | Page 5 of 24
ADR431 ELECTRICAL CHARACTERISTICS
VIN = 4.5 V to 18 V, IL = 0 mA, TA = 25°C, unless otherwise noted.
Table 3.
Parameter Symbol Conditions Min Typ Max Unit
OUTPUT VOLTAGE VO
A Grade 2.497 2.500 2.503 V
B Grade 2.499 2.500 2.501 V
INITIAL ACCURACY1 V
OERR
A Grade ±3 mV
±0.12 %
B Grade ±1 mV
±0.04 %
TEMPERATURE COEFFICIENT TCVO
A Grade −40°C < TA < +125°C 2 10 ppm/°C
B Grade −40°C < TA < +125°C 1 3 ppm/°C
LINE REGULATION ∆VO/∆VIN V
IN = 4.5 V to 18 V, −40°C < TA < +125°C 5 20 ppm/V
LOAD REGULATION ∆VO/∆IL I
L = 0 mA to 10 mA, VIN = 5.0 V, −40°C < TA < +125°C 15 ppm/mA
∆VO/∆IL I
L = −10 mA to 0 mA, VIN = 5.0 V, −40°C < TA < +125°C 15 ppm/mA
QUIESCENT CURRENT IIN No load, −40°C < TA < +125°C 580 800 μA
VOLTAGE NOISE eN p-p 0.1 Hz to 10.0 Hz 3.5 μV p-p
VOLTAGE NOISE DENSITY eN 1 kHz 80 nV/√Hz
TURN-ON SETTLING TIME tR C
L = 0 μF 10 μs
LONG-TERM STABILITY2 ∆VO 1000 hours 40 ppm
OUTPUT VOLTAGE HYSTERESIS VO_HYS 20 ppm
RIPPLE REJECTION RATIO RRR fIN = 1 kHz −70 dB
SHORT CIRCUIT TO GND ISC 40 mA
SUPPLY VOLTAGE
OPERATING RANGE VIN 4.5 18 V
SUPPLY VOLTAGE HEADROOM VINVO 2 V
1 Initial accuracy does not include shift due to solder heat effect.
2 The long-term stability specification is noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period.
ADR430/ADR431/ADR433/ADR434/ADR435/ADR439
Rev. J | Page 6 of 24
ADR433 ELECTRICAL CHARACTERISTICS
VIN = 5.0 V to 18 V, IL = 0 mA, TA = 25°C, unless otherwise noted.
Table 4.
Parameter Symbol Conditions Min Typ Max Unit
OUTPUT VOLTAGE VO
A Grade 2.996 3.000 3.004 V
B Grade 2.9985 3.000 3.0015 V
INITIAL ACCURACY1 V
OERR
A Grade ±4 mV
±0.13 %
B Grade ±1.5 mV
±0.05 %
TEMPERATURE COEFFICIENT TCVO
A Grade −40°C < TA < +125°C 2 10 ppm/°C
B Grade −40°C < TA < +125°C 1 3 ppm/°C
LINE REGULATION ∆VO/∆VIN V
IN = 5 V to 18 V, −40°C < TA < +125°C 5 20 ppm/V
LOAD REGULATION ∆VO/∆IL I
L = 0 mA to 10 mA, VIN = 6 V, −40°C < TA < +125°C 15 ppm/mA
∆VO/∆IL I
L = −10 mA to 0 mA, VIN = 6 V, −40°C < TA < +125°C 15 ppm/mA
QUIESCENT CURRENT IIN No load, −40°C < TA < +125°C 590 800 μA
VOLTAGE NOISE eN p-p 0.1 Hz to 10.0 Hz 3.75 μV p-p
VOLTAGE NOISE DENSITY eN 1 kHz 90 nV/√Hz
TURN-ON SETTLING TIME tR C
L = 0 μF 10 μs
LONG-TERM STABILITY2 ∆VO 1000 hours 40 ppm
OUTPUT VOLTAGE HYSTERESIS VO_HYS 20 ppm
RIPPLE REJECTION RATIO RRR fIN = 1 kHz −70 dB
SHORT CIRCUIT TO GND ISC 40 mA
SUPPLY VOLTAGE
OPERATING RANGE VIN 5.0 18 V
SUPPLY VOLTAGE HEADROOM VIN − VO 2 V
1 Initial accuracy does not include shift due to solder heat effect.
2 The long-term stability specification is noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period.
ADR430/ADR431/ADR433/ADR434/ADR435/ADR439
Rev. J | Page 7 of 24
ADR434 ELECTRICAL CHARACTERISTICS
VIN = 6.1 V to 18 V, IL = 0 mA, TA = 25°C, unless otherwise noted.
Table 5.
Parameter Symbol Conditions Min Typ Max Unit
OUTPUT VOLTAGE VO
A Grade 4.091 4.096 4.101 V
B Grade 4.0945 4.096 4.0975 V
INITIAL ACCURACY1 V
OERR
A Grade ±5 mV
±0.12 %
B Grade ±1.5 mV
±0.04 %
TEMPERATURE COEFFICIENT TCVO
A Grade −40°C < TA < +125°C 2 10 ppm/°C
B Grade −40°C < TA < +125°C 1 3 ppm/°C
LINE REGULATION ∆VO/∆VIN V
IN = 6.1 V to 18 V, −40°C < TA < +125°C 5 20 ppm/V
LOAD REGULATION ∆VO/∆IL I
L = 0 mA to 10 mA, VIN = 7 V, −40°C < TA < +125°C 15 ppm/mA
∆VO/∆IL I
L = −10 mA to 0 mA, VIN = 7 V, −40°C < TA < +125°C 15 ppm/mA
QUIESCENT CURRENT IIN No load, −40°C < TA < +125°C 595 800 μA
VOLTAGE NOISE eN p-p 0.1 Hz to 10.0 Hz 6.25 μV p-p
VOLTAGE NOISE DENSITY eN 1 kHz 100 nV/√Hz
TURN-ON SETTLING TIME tR C
L = 0 μF 10 μs
LONG-TERM STABILITY2 ∆VO 1000 hours 40 ppm
OUTPUT VOLTAGE HYSTERESIS VO_HYS 20 ppm
RIPPLE REJECTION RATIO RRR fIN = 1 kHz −70 dB
SHORT CIRCUIT TO GND ISC 40 mA
SUPPLY VOLTAGE
OPERATING RANGE VIN 6.1 18 V
SUPPLY VOLTAGE HEADROOM VIN − VO 2 V
1 Initial accuracy does not include shift due to solder heat effect.
2 The long-term stability specification is noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period.
ADR430/ADR431/ADR433/ADR434/ADR435/ADR439
Rev. J | Page 8 of 24
ADR435 ELECTRICAL CHARACTERISTICS
VIN = 7.0 V to 18 V, IL = 0 mA, TA = 25°C, unless otherwise noted.
Table 6.
Parameter Symbol Conditions Min Typ Max Unit
OUTPUT VOLTAGE VO
A Grade 4.994 5.000 5.006 V
B Grade 4.998 5.000 5.002 V
INITIAL ACCURACY1 V
OERR
A Grade ±6 mV
±0.12 %
B Grade ±2 mV
±0.04 %
TEMPERATURE COEFFICIENT TCVO
A Grade −40°C < TA < +125°C 2 10 ppm/°C
B Grade −40°C < TA < +125°C 1 3 ppm/°C
LINE REGULATION ∆VO/∆VIN V
IN = 7 V to 18 V, −40°C < TA < +125°C 5 20 ppm/V
LOAD REGULATION ∆VO/∆IL I
L = 0 mA to 10 mA, VIN = 8 V, −40°C < TA < +125°C 15 ppm/mA
∆VO/∆IL I
L = −10 mA to 0 mA, VIN = 8 V, −40°C < TA < +125°C 15 ppm/mA
QUIESCENT CURRENT IIN No load, −40°C < TA < +125°C 620 800 μA
VOLTAGE NOISE eN p-p 0.1 Hz to 10 Hz 8 μV p-p
VOLTAGE NOISE DENSITY eN 1 kHz 115 nV/√Hz
TURN-ON SETTLING TIME tR C
L = 0 μF 10 μs
LONG-TERM STABILITY2 ∆VO 1000 hours 40 ppm
OUTPUT VOLTAGE HYSTERESIS VO_HYS 20 ppm
RIPPLE REJECTION RATIO RRR fIN = 1 kHz −70 dB
SHORT CIRCUIT TO GND ISC 40 mA
SUPPLY VOLTAGE OPERATING RANGE VIN 7.0 18 V
SUPPLY VOLTAGE HEADROOM VINVO 2 V
1 Initial accuracy does not include shift due to solder heat effect.
2 The long-term stability specification is noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period.
ADR430/ADR431/ADR433/ADR434/ADR435/ADR439
Rev. J | Page 9 of 24
ADR439 ELECTRICAL CHARACTERISTICS
VIN = 6.5 V to 18 V, IL = 0 mV, TA = 25°C, unless otherwise noted.
Table 7.
Parameter Symbol Conditions Min Typ Max Unit
OUTPUT VOLTAGE VO
A Grade 4.4946 4.500 4.5054 V
B Grade 4.498 4.500 4.502 V
INITIAL ACCURACY1 V
OERR
A Grade ±5.5 mV
±0.12 %
B Grade ±2 mV
±0.04 %
TEMPERATURE COEFFICIENT TCVO
A Grade −40°C < TA < +125°C 2 10 ppm/°C
B Grade −40°C < TA < +125°C 1 3 ppm/°C
LINE REGULATION ∆VO/∆VIN V
IN = 6.5 V to 18 V, −40°C < TA < +125°C 5 20 ppm/V
LOAD REGULATION ∆VO/∆IL I
L = 0 mA to 10 mA, VIN = 6.5 V, −40°C < TA < +125°C 15 ppm/mA
∆VO/∆IL I
L = −10 mA to 0 mA, VIN = 6.5 V, −40°C < TA < +125°C 15 ppm/mA
QUIESCENT CURRENT IIN No load, −40°C < TA < +125°C 600 800 μA
VOLTAGE NOISE eN p-p 0.1 Hz to 10.0 Hz 7.5 μV p-p
VOLTAGE NOISE DENSITY eN 1 kHz 110 nV/√Hz
TURN-ON SETTLING TIME tR C
L = 0 μF 10 μs
LONG-TERM STABILITY2 ∆VO 1000 hours 40 ppm
OUTPUT VOLTAGE HYSTERESIS VO_HYS 20 ppm
RIPPLE REJECTION RATIO RRR fIN = 1 kHz −70 dB
SHORT CIRCUIT TO GND ISC 40 mA
SUPPLY VOLTAGE OPERATING RANGE VIN 6.5 18 V
SUPPLY VOLTAGE HEADROOM VINVO 2 V
1 Initial accuracy does not include shift due to solder heat effect.
2 The long-term stability specification is noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period.
ADR430/ADR431/ADR433/ADR434/ADR435/ADR439
Rev. J | Page 10 of 24
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 8.
Parameter Rating
Supply Voltage 20 V
Output Short-Circuit Duration to GND Indefinite
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +125°C
Junction Temperature Range −65°C to +150°C
Lead Temperature, Soldering (60 sec) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 9. Thermal Resistance
Package Type θJA θ
JC Unit
8-Lead SOIC_N (R) 130 43 °C/W
8-Lead MSOP (RM) 142 44 °C/W
ESD CAUTION
ADR430/ADR431/ADR433/ADR434/ADR435/ADR439
Rev. J | Page 11 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
Default conditions: ±5 V, CL = 5 pF, G = 2, RG = RF = 1 kΩ, RL = 2 kΩ, VO = 2 V p-p, f = 1 MHz, TA = 25°C, unless otherwise noted.
2.4995
OUTPUT VOLTAGE (V)
2.5009
2.5007
2.5005
2.5003
2.5001
2.4999
2.4997
TEMPERATURE (°C)
–40 –25 –10 5 20 35 50 65 80 95 110 125
04500-015
Figure 3. ADR431 Output Voltage vs. Temperature
OUTPUT VOL
T
AGE (V)
TEMPERATURE (°C)
–40 –25 –10 5 20 35 50 65 80 95 110 125
4.0950
4.0980
4.0975
4.0970
4.0965
4.0960
4.0955
04500-016
Figure 4. ADR434 Output Voltage vs. Temperature
OUTPUT VOL
T
AGE (V)
TEMPERATURE (°C)
–40 –25 –10 5 20 35 50 65 80 95 110 125
4.9990
5.0025
5.0020
5.0015
5.0010
5.0005
5.0000
4.9995
04500-017
Figure 5. ADR435 Output Voltage vs. Temperature
0.3
0.4
0.5
0.6
0.7
0.8
SUPPLY CURRENT (mA)
8104 6 12 14 16
INPUT VOLTAGE (V)
+125°C
+25°C
–40°C
04500-018
Figure 6. ADR435 Supply Current vs. Input Voltage
400
450
500
550
600
650
700
SUPPLY CURRENT (µA)
TEMPERATURE (°C)
–40 –25 –10 5 20 35 50 65 80 95 110 125
04500-019
Figure 7. ADR435 Supply Current vs. Temperature
0.40
0.42
0.44
0.46
0.48
0.50
0.52
0.54
0.56
0.58
0.60
SUPPLY CURRENT (mA)
10 126 8 14 16 18
INPUT VOLTAGE (V)
+125°C
+25°C
–40°C
04500-020
Figure 8. ADR431 Supply Current vs. Input Voltage
ADR430/ADR431/ADR433/ADR434/ADR435/ADR439
Rev. J | Page 12 of 24
400
430
460
490
520
550
580
610
SUPPLY CURRENT (µA)
TEMPERATURE (°C)
–40 –25 –10 5 20 35 50 65 80 95 110 125
04500-021
Figure 9. ADR431 Supply Current vs. Temperature
0
3
6
9
12
15
LOAD REGUL
A
TION (ppm/mA)
I
L
= 0mA to 10mA
TEMPERATURE (°C)
–40 –25 –10 5 20 35 50 65 80 95 110 125
04500-022
Figure 10. ADR431 Load Regulation vs. Temperature
0
3
6
9
12
15
LOAD REGUL
A
TION (ppm/mA)
I
L
= 0mA to 10mA
TEMPERATURE (°C)
–40 –25 –10 5 20 35 50 65 80 95 110 125
04500-023
Figure 11. ADR435 Load Regulation vs. Temperature
0
0.5
1.0
1.5
2.0
2.5
DIFFERENTIAL VOLTAGE (V)
LOAD CURRENT (mA)
–5–10 0 5 10
–40°C
+25°C
+125°C
04500-024
Figure 12. ADR431 Minimum Input/Output
Differential Voltage vs. Load Current
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
MINIMUM HEADROOM (V)
TEMPERATURE (°C)
–40 –25 –10 5 20 35 50 65 80 95 110 125
NO LOAD
04500-025
Figure 13. ADR431 Minimum Headroom vs. Temperature
0
0.5
1.0
1.5
2.0
2.5
DIFFERENTI
A
L VOLTAGE (V)
LOAD CURRENT (mA)
–5–10 0 5 10
–40°C
+25°C
+125°C
04500-026
Figure 14. ADR435 Minimum Input/Output
Differential Voltage vs. Load Current
ADR430/ADR431/ADR433/ADR434/ADR435/ADR439
Rev. J | Page 13 of 24
0.9
1.1
1.3
1.5
1.7
1.9
MINIMUM HEADROOM (V)
TEMPERATURE (°C)
–40 –25 –10 5 20 35 50 65 80 95 110 125
NO LOAD
04500-027
Figure 15. ADR435 Minimum Headroom vs. Temperature
–4
0
4
8
12
16
20
LINE REGUL
A
TION (ppm/V)
V
IN
=7VTO18V
TEMPERATURE (°C)
–40 –25 –10 5 20 35 50 65 80 95 110 125
04500-028
Figure 16. ADR435 Line Regulation vs. Temperature
CIN = 0.01µF
NO LOAD
VO = 1V/DIV
VIN = 2V/DIV
TIME = 4µs/DIV
0
4500-030
Figure 17. ADR431 Turn-On Response
CL = 0.01µF
NO INPUT CAPACITOR
VO = 1V/DIV
VIN = 2V/DIV
TIME = 4µs/DIV
04500-031
Figure 18. ADR431 Turn-On Response, 0.01 μF Load Capacitor
C
IN
= 0.01µF
NO LOAD
V
O
= 1V/DIV
V
IN
= 2V/DIV TIME = 4µs/DIV
0
4500-032
Figure 19. ADR431 Turn-Off Response
BYPASS CAPACITOR = 0µF
V
O
= 50mV/DIV
TIME = 100µs/DIV
LINE
INTERRUPTION
V
IN
= 500mV/DIV
04500-033
Figure 20. ADR431 Line Transient Response
ADR430/ADR431/ADR433/ADR434/ADR435/ADR439
Rev. J | Page 14 of 24
BYPASS CAPACITOR = 0.1µF
V
O
= 50mV/DIV
TIME = 100µs/DIV
LINE
INTERRUPTION
V
IN
= 500mV/DIV
04500-034
Figure 21. ADR431 Line Transient Response, 0.1 μF Bypass Capacitor
1µV/DIV
TIME = 1s/DIV
04500-035
Figure 22. ADR431 0.1 Hz to 10.0 Hz Voltage Noise
TIME = 1s/DIV
50µV/DIV
04500-036
Figure 23. ADR431 10 Hz to 10 kHz Voltage Noise
TIME = 1s/DIV
2µV/DIV
04500-037
Figure 24. ADR435 0.1 Hz to 10.0 Hz Voltage Noise
TIME = 1s/DIV
50µV/DIV
04500-038
Figure 25. ADR435 10 Hz to 10 kHz Voltage Noise
0
2
4
6
8
10
12
14
NUMBER OF PARTS
DEVIATION (PPM)
–110 –90 –70 –50 –30 –10 10 30 50 70 90 110
04500-029
Figure 26. ADR431 Typical Hysteresis
ADR430/ADR431/ADR433/ADR434/ADR435/ADR439
Rev. J | Page 15 of 24
0
5
10
15
20
25
30
35
40
45
50
OUTPUT IMPEDANCE (Ω)
FREQUENCY (Hz)
100 10k1k 100k
ADR435
ADR433
ADR430
04500-039
Figure 27. Output Impedance vs. Frequency
–150
–130
–110
–90
–70
–50
RIPPLE REJECTION (dB)
–30
–10
10
10 100 1k 10k 100k 1M
FREQUENCY (Hz)
04500-040
Figure 28. Ripple Rejection
ADR430/ADR431/ADR433/ADR434/ADR435/ADR439
Rev. J | Page 16 of 24
THEORY OF OPERATION
The ADR43x series of references uses a reference generation
technique known as XFET (eXtra implanted junction FET).
This technique yields a reference with low supply current, good
thermal hysteresis, and exceptionally low noise. The core of the
XFET reference consists of two junction field-effect transistors
(JFETs), one of which has an extra channel implant to raise its
pinch-off voltage. By running the two JFETs at the same drain
current, the difference in pinch-off voltage can be amplified and
used to form a highly stable voltage reference.
The intrinsic reference voltage is around 0.5 V with a negative
temperature coefficient of about −120 ppm/°C. This slope is
essentially constant to the dielectric constant of silicon and can
be compensated closely by adding a correction term generated
in the same fashion as the proportional-to-temperature (PTAT)
term used to compensate band gap references. The primary
advantage of an XFET reference is its correction term, which is
~30 times lower and requires less correction than that of a band
gap reference. Because most of the noise of a band gap reference
comes from the temperature compensation circuitry, the XFET
results in much lower noise.
Figure 29 shows the basic topology of the ADR43x series. The
temperature correction term is provided by a current source
with a value designed to be proportional to absolute temperature.
The general equation is
VOUT = G (ΔVPR1 × IPTAT) (1)
where:
G is the gain of the reciprocal of the divider ratio.
VP is the difference in pinch-off voltage between the two JFETs.
IPTAT is the positive temperature coefficient correction current.
ADR43x devices are created by on-chip adjustment of R2 and R3 to
achieve 2.048 V or 2.500 V, respectively, at the reference output.
**
I
PTAT
I
1
I
1
*EXTRA CHANNEL IMPLANT
V
OUT
= G(V
P
– R1 × I
PTAT
)
R2
V
IN
V
OUT
GND
R3
R1
V
P
ADR43x
04500-002
Figure 29. Simplified Schematic Device
Power Dissipation Considerations
The ADR43x family of references is guaranteed to deliver load
currents to 10 mA with an input voltage that ranges from 4.1 V
to 18 V. When these devices are used in applications at higher
currents, use the following equation to account for the
temperature effects due to the power dissipation increases:
TJ = PD × θJA + TA (2)
where:
TJ and TA are the junction and ambient temperatures, respectively.
PD is the device power dissipation.
θJA is the device package thermal resistance.
BASIC VOLTAGE REFERENCE CONNECTIONS
Voltage references, in general, require a bypass capacitor
connected from VOUT to GND. The circuit in Figure 30
illustrates the basic configuration for the ADR43x family
of references. Other than a 0.1 µF capacitor at the output to
help improve noise suppression, a large output capacitor at
the output is not required for circuit stability.
+
NOTES:
1. NC = NO CONNECT
2. TP = TEST PIN (DO NOT CONNECT)
1
2
3
45
8
6
7
ADR43x
TOP VIEW
(Not to Scale)
TP
COMP
V
OUT
TRIM
TP
NC
GND
V
IN
10µF 0.1µF
0.1µF
04500-044
Figure 30. Basic Voltage Reference Configuration
NOISE PERFORMANCE
The noise generated by the ADR43x family of references is
typically less than 3.75 µV p-p over the 0.1 Hz to 10.0 Hz band
for ADR430, ADR431, and ADR433. Figure 22 shows the 0.1 Hz
to 10.0 Hz noise of the ADR431, which is only 3.5 µV p-p. The
noise measurement is made with a band-pass filter made of a
2-pole high-pass filter with a corner frequency at 0.1 Hz and a
2-pole low-pass filter with a corner frequency at 10.0 Hz.
HIGH FREQUENCY NOISE
The total noise generated by the ADR43x family of references is
composed of the reference noise and the op amp noise. Figure 31
shows the wideband noise from 10 Hz to 25 kHz. An internal node
of the op amp is brought out on Pin 7, and by overcompensating
the op amp, the overall noise can be reduced.
This is understood by considering that in a closed-loop
configuration, the effective output impedance of an op amp is
β+
=
VO
O
OA
r
R1 (3)
where:
RO is the apparent output impedance.
rO is the output resistance of the op amp.
AVO is the open-loop gain at the frequency of interest.
β is the feedback factor.
ADR430/ADR431/ADR433/ADR434/ADR435/ADR439
Rev. J | Page 17 of 24
Equation 3 shows that the apparent output impedance is reduced
by approximately the excess loop gain; therefore, as the frequency
increases, the excess loop gain decreases, and the apparent output
impedance increases. A passive element whose impedance
increases as its frequency increases is an inductor. When a
capacitor is added to the output of an op amp or a reference, it
forms a tuned circuit that resonates at a certain frequency and
results in gain peaking. This can be observed by using a model
of a semiperfect op amp with a single-pole response and some
pure resistance in series with the output. Changing capacitive
loads results in peaking at different frequencies. For most normal
op amp applications with low capacitive loading (<100 pF), this
effect is usually not observed.
However, references are used increasingly to drive the reference
input of an ADC that may present a dynamic, switching capacitive
load. Large capacitors, in the microfarad range, are used to reduce
the change in reference voltage to less than one-half LSB. Figure 31
shows the ADR431 noise spectrum with various capacitive values
to 50 µF. With no capacitive load, the noise spectrum is relatively
flat at approximately 60 nV/√Hz to 70 nV/Hz. With various
values of capacitive loading, the predicted noise peaking
becomes evident.
10
100
1000
10 100 1k 10k 100k
ADR431
NO COMPENSATION
C
L
= 0µF
C
L
= 1µF
C
L
= 50µF
C
L
= 10µF
04500-042
FREQUENCY (Hz)
NOISE DENSITY (nV/Hz)
Figure 31. Noise vs. Capacitive Loading
The op amp within the ADR43x family uses the classic RC
compensation technique. Monolithic capacitors in an IC are
limited to tens of picofarads. With very large external capacitive
loads, such as 50 µF, it is necessary to overcompensate the op amp.
The internal compensation node is brought out on Pin 7, and
an external series RC network can be added between Pin 7 and
the output, Pin 6, as shown in Figure 32.
+
NOTES
1. NC = NO CONNEC
T
2
. TP = TEST PIN (DO NOT CONNECT)
1
2
3
45
8
6
7
ADR43x
TOP VIEW
(Not to Scale)
TP
COMP
V
OUT
TRIM
TP
NC
GND
V
IN
10µF 0.1µF
0.1µF
04500-003
82k
10nF
Figure 32. Compensated Reference
The 82 kΩ resistor and 10 nF capacitor can eliminate the noise
peaking (see Figure 33). The COMP pin should be left
unconnected if unused.
10
100
10 100 1k 10k
04500-043
FREQUENCY (Hz)
NOISE DENSITY (nV/Hz)
C
L
= 1µF
RC 82k AND 10nF
C
L
= 10µF
RC 82k AND 10nF
C
L
= 50µF
RC 82k AND 10nF
Figure 33. Noise with Compensation Network
TURN-ON TIME
Upon application of power (cold start), the time required for the
output voltage to reach its final value within a specified error band
is defined as the turn-on settling time. Two components normally
associated with this are the time for the active circuits to settle
and the time for the thermal gradients on the chip to stabilize.
Figure 17 and Figure 18 show the turn-on settling time for the
ADR431.
ADR430/ADR431/ADR433/ADR434/ADR435/ADR439
Rev. J | Page 18 of 24
APPLICATIONS INFORMATION
OUTPUT ADJUSTMENT
The ADR43x trim terminal can be used to adjust the output
voltage over a ±0.5% range. This feature allows the system designer
to trim system errors out by setting the reference to a voltage
other than the nominal. This is also helpful if the part is used in
a system at temperature to trim out any error. Adjustment of the
output has negligible effect on the temperature performance of the
device. To avoid degrading temperature coefficients, both the
trimming potentiometer and the two resistors need to be low
temperature coefficient types, preferably <100 ppm/°C.
INPUT
OUTPUT
TRIM
V
IN
V
O
= ±0.5%
GND
R1
470k
R2 10k (ADR430)
15k (ADR431)
R
P
10k
ADR43x
V
OUT
0
4500-004
Figure 34. Output Trim Adjustment
REFERENCE FOR CONVERTERS IN OPTICAL
NETWORK CONTROL CIRCUITS
In Figure 35, the high capacity, all optical router network
employs arrays of micromirrors to direct and route optical
signals from fiber to fiber without first converting them to
electrical form, which reduces the communication speed. The
tiny micromechanical mirrors are positioned so that each is
illuminated by a single wavelength that carries unique information
and can be passed to any desired input and output fiber. The
mirrors are tilted by the dual-axis actuators, which are controlled
by precision ADCs and DACs within the system. Due to the
microscopic movement of the mirrors, not only is the precision
of the converters important but the noise associated with these
controlling converters is also extremely critical. Total noise
within the system can be multiplied by the number of converters
employed. Therefore, to maintain the stability of the control
loop for this application, the ADR43x, with its exceptionally low
noise, is necessary.
GND
SOURCE FIBER
GIMBAL + SENSOR
DESTINATION
FIBER
ACTIVATOR
RIGHT
MEMS MIRROR
LASER BEAM
ACTIVATOR
LEFT
AMPL PREAMP AMPL
CONTROL
ELECTRONICS
DAC
ADC
DAC
DSP
ADR431
ADR431
ADR431
04500-005
Figure 35. All Optical Router Network
HIGH VOLTAGE FLOATING CURRENT SOURCE
The circuit in Figure 36 can be used to generate a floating
current source with minimal self heating. This particular
configuration can operate on high supply voltages determined
by the breakdown voltage of the N-channel JFET.
V
IN
V
OUT
GND
OP90
+
V
S
SST111
VISHAY
2N3904
R
L
2.1k
–V
S
ADR43x
2
6
4
04500-007
Figure 36. High Voltage Floating Current Source
KELVIN CONNECTION
In many portable instrumentation applications, where printed
circuit board (PCB) cost and area go hand in hand, circuit
interconnects are very often of dimensionally minimum width.
These narrow lines can cause large voltage drops if the voltage
reference is required to provide load currents to various functions.
In fact, circuit interconnects can exhibit a typical line resistance
of 0.45 mΩ/square (for example, 1 oz. Cu). Force and sense
connections, also referred to as Kelvin connections, offer a
convenient method of eliminating the effects of voltage drops
in circuit wires. Load currents flowing through wiring resistance
produce an error (VERROR = R × IL) at the load. However, the
Kelvin connection of Figure 37 overcomes the problem by
including the wiring resistance within the forcing loop of the
operational amplifier.
Because the amplifier senses the load voltage, the operational
amplifier loop control forces the output to compensate for the
wiring error and to produce the correct voltage at the load.