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Date: 11/29/04 SP6680 High Efficiency Buck/Boost Charge Pump Regulator © Copyright 2004 Sipex Corporation
DESCRIPTION
The SP6680 device is a regulated CMOS charge
pump voltage converter that can be used to
convert a +2.7V to +6.3V input voltage to a
nominal +5.2V to +6.3V output. These devices
are ideal for cellular phone designs involving
battery-powered and/or board level voltage
conversion applications.
An external clock signal with a frequency of
32.768kHz nominal is required for device
operation. A designer can set the SP6680 device
to operate at 3 different charge pump frequencies:
8.192kHz (fINPUT / 4), 32.768kHz (fINPUT x 1), and
262.14kHz (fINPUT x 8). The three frequencies
correspond to three nominal load current ranges:
2mA, 20mA, and 60mA, respectively. The
SP6680 device optimizes for high power
efficiency with a low quiescent current of 100µA
at 8.198kHz, 200µA at 32.768kHz, and 1.0mA
at 262.14kHz. When there is no external clock
signal input, the device is in a low-power
shutdown mode drawing 4.4µA (typical) current.
The SP6680 device is ideal for designs using
+3.6V lithium ion batteries such as cell phones,
PDAs, medical instruments, and other portable
equipment. For designs involving power sources
above +2.7V up to +6.3V, the internal charge
pump switch architecture dynamically selects an
operational mode that optimizes efficiency. The
SP6680 device regulates the maximum output
voltage in steady state to +6.3V.
THEORY OF OPERATION
There are seven major circuit blocks for the
SP6680 device. Refer to Figure 1.
1) The Voltage Reference contains a band gap
and other circuits that provide the proper current
biases and voltage references used in the other
blocks.
2) The Clock Manager accepts the digital input
voltage levels (including the input clock) and
translates them to VCC and 0V. It also determines
if a clock is present in which case the device is
powered up. If the CLK input is left floating or
pulled near ground, the device shuts down and
VIN is shorted to VOUT. The worst case digital low
is 0.4V and the worst case digital high is 1.3V.
This block contains a synthesizer that generates
the internal pump clock which runs at the
frequency controlled with the C/4 and Cx8 logic
pins.
3) The Charge Pump Switch Configuration
Control determines the pump configuration
depending upon VIN as described earlier and
programs the Clock Phase Control. For an input
supply voltage from +2.7V to +3.7V, an X2
doubling architecture is enabled. This mode
requires one flying capacitor and one output
capacitor. For an input supply voltage greater
than +3.7V up to +6.3V, an X1.5 multiplier
architecture is enabled. This mode requires two
flying capacitors and one output capacitor.
Figure 1. Internal Block Diagram of the SP6680
Charge
Pump
Switches
Voltage
Reference CF1P
CF1N
CLK
Cx8
C/4
Clock
Manager Drivers
V
IN
GND
SP6680
2
9
8
6
5
4
3
Clock Phase
Control
Charge Pump Switch
Configuration Control
V
OUT
Control
V
OUT
1
CF2P
CF2N
10
7CF2
C
OUT
CF1